Re: [PATCH 3/7] staging: ccree: add support for older HW revisions

[kbuild test robot]

Hi Gilad,

[auto build test WARNING on staging/staging-testing]
[also build test WARNING on next-20170623]
[cannot apply to v4.12-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Gilad-Ben-Yossef/staging-ccree-bug-fixes-and-TODO-items-for-4-13/20170623-134445
config: x86_64-randconfig-b0-06241039 (attached as .config)
compiler: gcc-4.4 (Debian 4.4.7-8) 4.4.7
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All warnings (new ones prefixed by >>):

   drivers/staging/ccree/ssi_sram_mgr.c: In function 'ssi_sram_mgr_init':
>> drivers/staging/ccree/ssi_sram_mgr.c:76: warning: format '%x' expects type 
>> 'unsigned int', but argument 3 has type 'dma_addr_t'

vim +76 drivers/staging/ccree/ssi_sram_mgr.c

60  /* Allocate "this" context */
61  drvdata->sram_mgr_handle = kzalloc(
62  sizeof(struct ssi_sram_mgr_ctx), GFP_KERNEL);
63  if (!drvdata->sram_mgr_handle) {
64  SSI_LOG_ERR("Not enough memory to allocate SRAM_MGR ctx 
(%zu)\n",
65  sizeof(struct ssi_sram_mgr_ctx));
66  rc = -ENOMEM;
67  goto out;
68  }
69  smgr_ctx = drvdata->sram_mgr_handle;
70  
71  if (drvdata->hw_rev < CC_HW_REV_712) {
72  /* Pool starts after ROM bytes */
73  start = 
(dma_addr_t)CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF,
74  HOST_SEP_SRAM_THRESHOLD));
75  if ((start & 0x3) != 0) {
  > 76  SSI_LOG_ERR("Invalid SRAM offset 0x%x\n", 
start);
77  rc = -ENODEV;
78  goto out;
79  }
80  }
81  
82  smgr_ctx->sram_free_offset = start;
83  return 0;
84  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

Re: [PATCH 3/7] staging: ccree: add support for older HW revisions

[kbuild test robot]

Hi Gilad,

[auto build test WARNING on staging/staging-testing]
[also build test WARNING on next-20170623]
[cannot apply to v4.12-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Gilad-Ben-Yossef/staging-ccree-bug-fixes-and-TODO-items-for-4-13/20170623-134445
config: x86_64-randconfig-b0-06241039 (attached as .config)
compiler: gcc-4.4 (Debian 4.4.7-8) 4.4.7
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All warnings (new ones prefixed by >>):

   drivers/staging/ccree/ssi_sram_mgr.c: In function 'ssi_sram_mgr_init':
>> drivers/staging/ccree/ssi_sram_mgr.c:76: warning: format '%x' expects type 
>> 'unsigned int', but argument 3 has type 'dma_addr_t'

vim +76 drivers/staging/ccree/ssi_sram_mgr.c

60  /* Allocate "this" context */
61  drvdata->sram_mgr_handle = kzalloc(
62  sizeof(struct ssi_sram_mgr_ctx), GFP_KERNEL);
63  if (!drvdata->sram_mgr_handle) {
64  SSI_LOG_ERR("Not enough memory to allocate SRAM_MGR ctx 
(%zu)\n",
65  sizeof(struct ssi_sram_mgr_ctx));
66  rc = -ENOMEM;
67  goto out;
68  }
69  smgr_ctx = drvdata->sram_mgr_handle;
70  
71  if (drvdata->hw_rev < CC_HW_REV_712) {
72  /* Pool starts after ROM bytes */
73  start = 
(dma_addr_t)CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF,
74  HOST_SEP_SRAM_THRESHOLD));
75  if ((start & 0x3) != 0) {
  > 76  SSI_LOG_ERR("Invalid SRAM offset 0x%x\n", 
start);
77  rc = -ENODEV;
78  goto out;
79  }
80  }
81  
82  smgr_ctx->sram_free_offset = start;
83  return 0;
84  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

Re: [PATCH 3/7] staging: ccree: add support for older HW revisions

[kbuild test robot]

Hi Gilad,

[auto build test WARNING on staging/staging-testing]
[also build test WARNING on next-20170622]
[cannot apply to v4.12-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Gilad-Ben-Yossef/staging-ccree-bug-fixes-and-TODO-items-for-4-13/20170623-134445
config: sparc64-allmodconfig (attached as .config)
compiler: sparc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=sparc64 

All warnings (new ones prefixed by >>):

   In file included from drivers/staging/ccree/ssi_sram_mgr.c:17:0:
   drivers/staging/ccree/ssi_sram_mgr.c: In function 'ssi_sram_mgr_init':
   include/linux/kern_levels.h:4:18: warning: format '%x' expects argument of 
type 'unsigned int', but argument 3 has type 'dma_addr_t {aka long long 
unsigned int}' [-Wformat=]
#define KERN_SOH "\001"  /* ASCII Start Of Header */
 ^
   drivers/staging/ccree/ssi_driver.h:97:9: note: in definition of macro 
'SSI_LOG'
 printk(level "ccree::%s: " format, __func__, ##__VA_ARGS__)
^
   include/linux/kern_levels.h:10:18: note: in expansion of macro 'KERN_SOH'
#define KERN_ERR KERN_SOH "3" /* error conditions */
 ^~~~
>> drivers/staging/ccree/ssi_driver.h:98:42: note: in expansion of macro 
>> 'KERN_ERR'
#define SSI_LOG_ERR(format, ...) SSI_LOG(KERN_ERR, format, ##__VA_ARGS__)
 ^~~~
>> drivers/staging/ccree/ssi_sram_mgr.c:76:4: note: in expansion of macro 
>> 'SSI_LOG_ERR'
   SSI_LOG_ERR("Invalid SRAM offset 0x%x\n", start);
   ^~~

vim +/KERN_ERR +98 drivers/staging/ccree/ssi_driver.h

abefd674 Gilad Ben-Yossef 2017-04-23   91  /* AXI_ID is not actually the AXI ID 
of the transaction but the value of AXI_ID
250a00a7 Derek Robson 2017-05-30   92   * field in the HW descriptor. The 
DMA engine +8 that value.
250a00a7 Derek Robson 2017-05-30   93   */
abefd674 Gilad Ben-Yossef 2017-04-23   94  
abefd674 Gilad Ben-Yossef 2017-04-23   95  /* Logging macros */
abefd674 Gilad Ben-Yossef 2017-04-23   96  #define SSI_LOG(level, format, ...) \
891144d7 Gilad Ben-Yossef 2017-06-22  @97   printk(level "ccree::%s: " 
format, __func__, ##__VA_ARGS__)
abefd674 Gilad Ben-Yossef 2017-04-23  @98  #define SSI_LOG_ERR(format, ...) 
SSI_LOG(KERN_ERR, format, ##__VA_ARGS__)
abefd674 Gilad Ben-Yossef 2017-04-23   99  #define SSI_LOG_WARNING(format, ...) 
SSI_LOG(KERN_WARNING, format, ##__VA_ARGS__)
abefd674 Gilad Ben-Yossef 2017-04-23  100  #define SSI_LOG_NOTICE(format, ...) 
SSI_LOG(KERN_NOTICE, format, ##__VA_ARGS__)
abefd674 Gilad Ben-Yossef 2017-04-23  101  #define SSI_LOG_INFO(format, ...) 
SSI_LOG(KERN_INFO, format, ##__VA_ARGS__)

:: The code at line 98 was first introduced by commit
:: abefd6741d540fc624e73a2a3bdef2397bcbd064 staging: ccree: introduce 
CryptoCell HW driver

:: TO: Gilad Ben-Yossef 
:: CC: Greg Kroah-Hartman 

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

Re: [PATCH 3/7] staging: ccree: add support for older HW revisions

[kbuild test robot]

Hi Gilad,

[auto build test WARNING on staging/staging-testing]
[also build test WARNING on next-20170622]
[cannot apply to v4.12-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Gilad-Ben-Yossef/staging-ccree-bug-fixes-and-TODO-items-for-4-13/20170623-134445
config: sparc64-allmodconfig (attached as .config)
compiler: sparc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=sparc64 

All warnings (new ones prefixed by >>):

   In file included from drivers/staging/ccree/ssi_sram_mgr.c:17:0:
   drivers/staging/ccree/ssi_sram_mgr.c: In function 'ssi_sram_mgr_init':
   include/linux/kern_levels.h:4:18: warning: format '%x' expects argument of 
type 'unsigned int', but argument 3 has type 'dma_addr_t {aka long long 
unsigned int}' [-Wformat=]
#define KERN_SOH "\001"  /* ASCII Start Of Header */
 ^
   drivers/staging/ccree/ssi_driver.h:97:9: note: in definition of macro 
'SSI_LOG'
 printk(level "ccree::%s: " format, __func__, ##__VA_ARGS__)
^
   include/linux/kern_levels.h:10:18: note: in expansion of macro 'KERN_SOH'
#define KERN_ERR KERN_SOH "3" /* error conditions */
 ^~~~
>> drivers/staging/ccree/ssi_driver.h:98:42: note: in expansion of macro 
>> 'KERN_ERR'
#define SSI_LOG_ERR(format, ...) SSI_LOG(KERN_ERR, format, ##__VA_ARGS__)
 ^~~~
>> drivers/staging/ccree/ssi_sram_mgr.c:76:4: note: in expansion of macro 
>> 'SSI_LOG_ERR'
   SSI_LOG_ERR("Invalid SRAM offset 0x%x\n", start);
   ^~~

vim +/KERN_ERR +98 drivers/staging/ccree/ssi_driver.h

abefd674 Gilad Ben-Yossef 2017-04-23   91  /* AXI_ID is not actually the AXI ID 
of the transaction but the value of AXI_ID
250a00a7 Derek Robson 2017-05-30   92   * field in the HW descriptor. The 
DMA engine +8 that value.
250a00a7 Derek Robson 2017-05-30   93   */
abefd674 Gilad Ben-Yossef 2017-04-23   94  
abefd674 Gilad Ben-Yossef 2017-04-23   95  /* Logging macros */
abefd674 Gilad Ben-Yossef 2017-04-23   96  #define SSI_LOG(level, format, ...) \
891144d7 Gilad Ben-Yossef 2017-06-22  @97   printk(level "ccree::%s: " 
format, __func__, ##__VA_ARGS__)
abefd674 Gilad Ben-Yossef 2017-04-23  @98  #define SSI_LOG_ERR(format, ...) 
SSI_LOG(KERN_ERR, format, ##__VA_ARGS__)
abefd674 Gilad Ben-Yossef 2017-04-23   99  #define SSI_LOG_WARNING(format, ...) 
SSI_LOG(KERN_WARNING, format, ##__VA_ARGS__)
abefd674 Gilad Ben-Yossef 2017-04-23  100  #define SSI_LOG_NOTICE(format, ...) 
SSI_LOG(KERN_NOTICE, format, ##__VA_ARGS__)
abefd674 Gilad Ben-Yossef 2017-04-23  101  #define SSI_LOG_INFO(format, ...) 
SSI_LOG(KERN_INFO, format, ##__VA_ARGS__)

:: The code at line 98 was first introduced by commit
:: abefd6741d540fc624e73a2a3bdef2397bcbd064 staging: ccree: introduce 
CryptoCell HW driver

:: TO: Gilad Ben-Yossef 
:: CC: Greg Kroah-Hartman 

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

[PATCH 3/7] staging: ccree: add support for older HW revisions

[Gilad Ben-Yossef]

Add support for the older CryptoCell 710 and 630P hardware revisions.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/Kconfig|   7 +-
 drivers/staging/ccree/cc_crypto_ctx.h|  16 ---
 drivers/staging/ccree/cc_hw_queue_defs.h |   2 +-
 drivers/staging/ccree/cc_regs.h  |   7 +-
 drivers/staging/ccree/dx_crys_kernel.h   |   1 +
 drivers/staging/ccree/dx_host.h  |   3 +
 drivers/staging/ccree/dx_reg_common.h|   2 -
 drivers/staging/ccree/ssi_aead.c |  36 +++--
 drivers/staging/ccree/ssi_cipher.c   |  27 +++-
 drivers/staging/ccree/ssi_config.h   |   2 +-
 drivers/staging/ccree/ssi_driver.c   | 115 ++-
 drivers/staging/ccree/ssi_driver.h   |  25 +++-
 drivers/staging/ccree/ssi_fips_ll.c  |  59 
 drivers/staging/ccree/ssi_hash.c | 234 +--
 drivers/staging/ccree/ssi_hash.h |  10 +-
 drivers/staging/ccree/ssi_request_mgr.c  |  19 ++-
 drivers/staging/ccree/ssi_sram_mgr.c |  15 +-
 17 files changed, 349 insertions(+), 231 deletions(-)

diff --git a/drivers/staging/ccree/Kconfig b/drivers/staging/ccree/Kconfig
index 4be87f5..f1e75e8 100644
--- a/drivers/staging/ccree/Kconfig
+++ b/drivers/staging/ccree/Kconfig
@@ -19,9 +19,10 @@ config CRYPTO_DEV_CCREE
select CRYPTO_XTS
help
  Say 'Y' to enable a driver for the Arm TrustZone CryptoCell 
- C7xx. Currently only the CryptoCell 712 REE is supported.
- Choose this if you wish to use hardware acceleration of
- cryptographic operations on the system REE.
+ C7xx. Currently the REE interface of the CryptoCell 712,
+ 710 and 630p are supported. Choose this if you wish to use
+ hardware acceleration of cryptographic operations on the
+ system REE.
  If unsure say Y.
 
 config CCREE_FIPS_SUPPORT
diff --git a/drivers/staging/ccree/cc_crypto_ctx.h 
b/drivers/staging/ccree/cc_crypto_ctx.h
index 591f6fd..1542aa7 100644
--- a/drivers/staging/ccree/cc_crypto_ctx.h
+++ b/drivers/staging/ccree/cc_crypto_ctx.h
@@ -19,17 +19,6 @@
 
 #include 
 
-/* context size */
-#ifndef CC_CTX_SIZE_LOG2
-#if (CC_SUPPORT_SHA > 256)
-#define CC_CTX_SIZE_LOG2 8
-#else
-#define CC_CTX_SIZE_LOG2 7
-#endif
-#endif
-#define CC_CTX_SIZE BIT(CC_CTX_SIZE_LOG2)
-#define CC_DRV_CTX_SIZE_WORDS (CC_CTX_SIZE >> 2)
-
 #define CC_DRV_DES_IV_SIZE 8
 #define CC_DRV_DES_BLOCK_SIZE 8
 
@@ -72,13 +61,8 @@
 #define CC_SHA384_BLOCK_SIZE 128
 #define CC_SHA512_BLOCK_SIZE 128
 
-#if (CC_SUPPORT_SHA > 256)
 #define CC_DIGEST_SIZE_MAX CC_SHA512_DIGEST_SIZE
 #define CC_HASH_BLOCK_SIZE_MAX CC_SHA512_BLOCK_SIZE /*1024b*/
-#else /* Only up to SHA256 */
-#define CC_DIGEST_SIZE_MAX CC_SHA256_DIGEST_SIZE
-#define CC_HASH_BLOCK_SIZE_MAX CC_SHA256_BLOCK_SIZE /*512b*/
-#endif
 
 #define CC_HMAC_BLOCK_SIZE_MAX CC_HASH_BLOCK_SIZE_MAX
 
diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h 
b/drivers/staging/ccree/cc_hw_queue_defs.h
index aaa56c8..c730c3c 100644
--- a/drivers/staging/ccree/cc_hw_queue_defs.h
+++ b/drivers/staging/ccree/cc_hw_queue_defs.h
@@ -220,7 +220,7 @@ static inline void hw_desc_init(struct cc_hw_desc *pdesc)
  *
  * @pdesc: pointer HW descriptor struct
  */
-static inline void set_queue_last_ind(struct cc_hw_desc *pdesc)
+static inline void set_queue_last_ind_bit(struct cc_hw_desc *pdesc)
 {
pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1);
 }
diff --git a/drivers/staging/ccree/cc_regs.h b/drivers/staging/ccree/cc_regs.h
index 4a893a6..62ace81 100644
--- a/drivers/staging/ccree/cc_regs.h
+++ b/drivers/staging/ccree/cc_regs.h
@@ -25,12 +25,9 @@
 
 #include 
 
-#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
-#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
-   DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
-   DX_AXIM_MON_COMP_VALUE_BIT_SHIFT)
+#define AXIM_MON_BASE_712_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
+#define AXIM_MON_BASE_630_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP8)
 
-#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
 #define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
DX_AXIM_MON_COMP_VALUE_BIT_SHIFT)
diff --git a/drivers/staging/ccree/dx_crys_kernel.h 
b/drivers/staging/ccree/dx_crys_kernel.h
index 2196030..0d1d01e 100644
--- a/drivers/staging/ccree/dx_crys_kernel.h
+++ b/drivers/staging/ccree/dx_crys_kernel.h
@@ -131,6 +131,7 @@
 #define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT   0x0UL
 #define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE0x8UL
 #define DX_AXIM_MON_COMP_REG_OFFSET0xB80UL
+#define DX_AXIM_MON_COMP8_REG_OFFSET   0xBA0UL
 #define DX_AXIM_MON_COMP_VALUE_BIT_SHIFT   0x0UL
 #define DX_AXIM_MON_COMP_VALUE_BIT_SIZE0x10UL
 #define DX_AXIM_MON_ERR_REG_OFFSET 0xBC4UL
diff --git a/drivers/staging/ccree/dx_host.h 

[PATCH 3/7] staging: ccree: add support for older HW revisions

[Gilad Ben-Yossef]

Add support for the older CryptoCell 710 and 630P hardware revisions.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/Kconfig|   7 +-
 drivers/staging/ccree/cc_crypto_ctx.h|  16 ---
 drivers/staging/ccree/cc_hw_queue_defs.h |   2 +-
 drivers/staging/ccree/cc_regs.h  |   7 +-
 drivers/staging/ccree/dx_crys_kernel.h   |   1 +
 drivers/staging/ccree/dx_host.h  |   3 +
 drivers/staging/ccree/dx_reg_common.h|   2 -
 drivers/staging/ccree/ssi_aead.c |  36 +++--
 drivers/staging/ccree/ssi_cipher.c   |  27 +++-
 drivers/staging/ccree/ssi_config.h   |   2 +-
 drivers/staging/ccree/ssi_driver.c   | 115 ++-
 drivers/staging/ccree/ssi_driver.h   |  25 +++-
 drivers/staging/ccree/ssi_fips_ll.c  |  59 
 drivers/staging/ccree/ssi_hash.c | 234 +--
 drivers/staging/ccree/ssi_hash.h |  10 +-
 drivers/staging/ccree/ssi_request_mgr.c  |  19 ++-
 drivers/staging/ccree/ssi_sram_mgr.c |  15 +-
 17 files changed, 349 insertions(+), 231 deletions(-)

diff --git a/drivers/staging/ccree/Kconfig b/drivers/staging/ccree/Kconfig
index 4be87f5..f1e75e8 100644
--- a/drivers/staging/ccree/Kconfig
+++ b/drivers/staging/ccree/Kconfig
@@ -19,9 +19,10 @@ config CRYPTO_DEV_CCREE
select CRYPTO_XTS
help
  Say 'Y' to enable a driver for the Arm TrustZone CryptoCell 
- C7xx. Currently only the CryptoCell 712 REE is supported.
- Choose this if you wish to use hardware acceleration of
- cryptographic operations on the system REE.
+ C7xx. Currently the REE interface of the CryptoCell 712,
+ 710 and 630p are supported. Choose this if you wish to use
+ hardware acceleration of cryptographic operations on the
+ system REE.
  If unsure say Y.
 
 config CCREE_FIPS_SUPPORT
diff --git a/drivers/staging/ccree/cc_crypto_ctx.h 
b/drivers/staging/ccree/cc_crypto_ctx.h
index 591f6fd..1542aa7 100644
--- a/drivers/staging/ccree/cc_crypto_ctx.h
+++ b/drivers/staging/ccree/cc_crypto_ctx.h
@@ -19,17 +19,6 @@
 
 #include 
 
-/* context size */
-#ifndef CC_CTX_SIZE_LOG2
-#if (CC_SUPPORT_SHA > 256)
-#define CC_CTX_SIZE_LOG2 8
-#else
-#define CC_CTX_SIZE_LOG2 7
-#endif
-#endif
-#define CC_CTX_SIZE BIT(CC_CTX_SIZE_LOG2)
-#define CC_DRV_CTX_SIZE_WORDS (CC_CTX_SIZE >> 2)
-
 #define CC_DRV_DES_IV_SIZE 8
 #define CC_DRV_DES_BLOCK_SIZE 8
 
@@ -72,13 +61,8 @@
 #define CC_SHA384_BLOCK_SIZE 128
 #define CC_SHA512_BLOCK_SIZE 128
 
-#if (CC_SUPPORT_SHA > 256)
 #define CC_DIGEST_SIZE_MAX CC_SHA512_DIGEST_SIZE
 #define CC_HASH_BLOCK_SIZE_MAX CC_SHA512_BLOCK_SIZE /*1024b*/
-#else /* Only up to SHA256 */
-#define CC_DIGEST_SIZE_MAX CC_SHA256_DIGEST_SIZE
-#define CC_HASH_BLOCK_SIZE_MAX CC_SHA256_BLOCK_SIZE /*512b*/
-#endif
 
 #define CC_HMAC_BLOCK_SIZE_MAX CC_HASH_BLOCK_SIZE_MAX
 
diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h 
b/drivers/staging/ccree/cc_hw_queue_defs.h
index aaa56c8..c730c3c 100644
--- a/drivers/staging/ccree/cc_hw_queue_defs.h
+++ b/drivers/staging/ccree/cc_hw_queue_defs.h
@@ -220,7 +220,7 @@ static inline void hw_desc_init(struct cc_hw_desc *pdesc)
  *
  * @pdesc: pointer HW descriptor struct
  */
-static inline void set_queue_last_ind(struct cc_hw_desc *pdesc)
+static inline void set_queue_last_ind_bit(struct cc_hw_desc *pdesc)
 {
pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1);
 }
diff --git a/drivers/staging/ccree/cc_regs.h b/drivers/staging/ccree/cc_regs.h
index 4a893a6..62ace81 100644
--- a/drivers/staging/ccree/cc_regs.h
+++ b/drivers/staging/ccree/cc_regs.h
@@ -25,12 +25,9 @@
 
 #include 
 
-#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
-#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
-   DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
-   DX_AXIM_MON_COMP_VALUE_BIT_SHIFT)
+#define AXIM_MON_BASE_712_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
+#define AXIM_MON_BASE_630_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP8)
 
-#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
 #define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
DX_AXIM_MON_COMP_VALUE_BIT_SHIFT)
diff --git a/drivers/staging/ccree/dx_crys_kernel.h 
b/drivers/staging/ccree/dx_crys_kernel.h
index 2196030..0d1d01e 100644
--- a/drivers/staging/ccree/dx_crys_kernel.h
+++ b/drivers/staging/ccree/dx_crys_kernel.h
@@ -131,6 +131,7 @@
 #define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT   0x0UL
 #define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE0x8UL
 #define DX_AXIM_MON_COMP_REG_OFFSET0xB80UL
+#define DX_AXIM_MON_COMP8_REG_OFFSET   0xBA0UL
 #define DX_AXIM_MON_COMP_VALUE_BIT_SHIFT   0x0UL
 #define DX_AXIM_MON_COMP_VALUE_BIT_SIZE0x10UL
 #define DX_AXIM_MON_ERR_REG_OFFSET 0xBC4UL
diff --git a/drivers/staging/ccree/dx_host.h b/drivers/staging/ccree/dx_host.h
index