Re: [PATCH 8/9] Add devicetree bindings for Rockchip Soc EDP
Am Montag, 4. August 2014, 12:55:59 schrieb mark yao:
> Signed-off-by: mark yao
> ---
> .../devicetree/bindings/video/rockchip-panel.txt | 34
> 1 file changed, 34 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/video/rockchip-panel.txt
> b/Documentation/devicetree/bindings/video/rockchip-panel.txt index
> f599806..f6d80f6 100644
> --- a/Documentation/devicetree/bindings/video/rockchip-panel.txt
> +++ b/Documentation/devicetree/bindings/video/rockchip-panel.txt
> @@ -80,3 +80,37 @@ Example:
> rockchip,data-width = <24>;
> rockchip,panel = <>;
> };
> +
> +Rockchip RK3288 EDP interface
> +
> +Required properties:
> +-compatible: "rockchip,rk3288-edp";
> +
> +- reg: physical base address of the controller and length
> +- clocks: from common clock binding: handle to dp clock.
> + of memory mapped region.
> +- clock-names: from common clock binding:
> + Required elements: "clk_edp"
> + "clk_edp_24m"
> + "clk_edp_24m_parent"
> + "pclk_edp"
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +- resets: Must contain an entry for each entry in reset-names.
> + See ../reset/reset.txt for details.
> +- reset-names: Must include the following entries:
> + - edp
> +- rockchip,panel: required a panel node
> +
> +Example:
> + edp: edp@ff97 {
> + compatible = "rockchip,rk3288-edp";
> +reg = <0xff97 0x4000>;
> +interrupts = ;
> +clocks = < SCLK_EDP>, < SCLK_EDP_24M>, <
> PCLK_EDP_CTRL>, <>; +clock-names = "clk_edp",
> "clk_edp_24m", "pclk_edp", "clk_edp_24m_parent"; +
clk_epd_24m_parent is not part of the hardware, so instead of referencing the
target-parent as part of the device clocks, the new
"clk: Support for clock parents and rates assigned from device tree"
should be used for setting the target parent - so the re-parenting code should
also move out of the driver.
This commit [0] is part of the clk-pull request and thus will most likely be
part of 3.17.
Heiko
[0]
http://git.linaro.org/people/mike.turquette/linux.git/commitdiff/86be408bfbd846fab3c4ac21d6f9298bd2e4b790?hp=09575693a2511b5ddae0105546e0d9cefc936e34
> +rockchip,grf = <>;
> +resets = < 111>;
> +reset-names = "edp";
> + rockchip,panel = <>;
> + };
--
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Re: [PATCH 8/9] Add devicetree bindings for Rockchip Soc EDP
Am Montag, 4. August 2014, 12:55:59 schrieb mark yao:
Signed-off-by: mark yao y...@rock-chips.com
---
.../devicetree/bindings/video/rockchip-panel.txt | 34
1 file changed, 34 insertions(+)
diff --git a/Documentation/devicetree/bindings/video/rockchip-panel.txt
b/Documentation/devicetree/bindings/video/rockchip-panel.txt index
f599806..f6d80f6 100644
--- a/Documentation/devicetree/bindings/video/rockchip-panel.txt
+++ b/Documentation/devicetree/bindings/video/rockchip-panel.txt
@@ -80,3 +80,37 @@ Example:
rockchip,data-width = 24;
rockchip,panel = panel;
};
+
+Rockchip RK3288 EDP interface
+
+Required properties:
+-compatible: rockchip,rk3288-edp;
+
+- reg: physical base address of the controller and length
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped region.
+- clock-names: from common clock binding:
+ Required elements: clk_edp
+ clk_edp_24m
+ clk_edp_24m_parent
+ pclk_edp
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+ - edp
+- rockchip,panel: required a panel node
+
+Example:
+ edp: edp@ff97 {
+ compatible = rockchip,rk3288-edp;
+reg = 0xff97 0x4000;
+interrupts = GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH;
+clocks = cru SCLK_EDP, cru SCLK_EDP_24M, cru
PCLK_EDP_CTRL, xin24m; +clock-names = clk_edp,
clk_edp_24m, pclk_edp, clk_edp_24m_parent; +
clk_epd_24m_parent is not part of the hardware, so instead of referencing the
target-parent as part of the device clocks, the new
clk: Support for clock parents and rates assigned from device tree
should be used for setting the target parent - so the re-parenting code should
also move out of the driver.
This commit [0] is part of the clk-pull request and thus will most likely be
part of 3.17.
Heiko
[0]
http://git.linaro.org/people/mike.turquette/linux.git/commitdiff/86be408bfbd846fab3c4ac21d6f9298bd2e4b790?hp=09575693a2511b5ddae0105546e0d9cefc936e34
+rockchip,grf = grf;
+resets = cru 111;
+reset-names = edp;
+ rockchip,panel = panel;
+ };
--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH 8/9] Add devicetree bindings for Rockchip Soc EDP
Signed-off-by: mark yao
---
.../devicetree/bindings/video/rockchip-panel.txt | 34
1 file changed, 34 insertions(+)
diff --git a/Documentation/devicetree/bindings/video/rockchip-panel.txt
b/Documentation/devicetree/bindings/video/rockchip-panel.txt
index f599806..f6d80f6 100644
--- a/Documentation/devicetree/bindings/video/rockchip-panel.txt
+++ b/Documentation/devicetree/bindings/video/rockchip-panel.txt
@@ -80,3 +80,37 @@ Example:
rockchip,data-width = <24>;
rockchip,panel = <>;
};
+
+Rockchip RK3288 EDP interface
+
+Required properties:
+-compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped region.
+- clock-names: from common clock binding:
+ Required elements: "clk_edp"
+ "clk_edp_24m"
+ "clk_edp_24m_parent"
+ "pclk_edp"
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+ - edp
+- rockchip,panel: required a panel node
+
+Example:
+ edp: edp@ff97 {
+ compatible = "rockchip,rk3288-edp";
+reg = <0xff97 0x4000>;
+interrupts = ;
+clocks = < SCLK_EDP>, < SCLK_EDP_24M>, <
PCLK_EDP_CTRL>, <>;
+clock-names = "clk_edp", "clk_edp_24m", "pclk_edp",
"clk_edp_24m_parent";
+
+rockchip,grf = <>;
+resets = < 111>;
+reset-names = "edp";
+ rockchip,panel = <>;
+ };
--
1.7.9.5
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH 8/9] Add devicetree bindings for Rockchip Soc EDP
Signed-off-by: mark yao y...@rock-chips.com
---
.../devicetree/bindings/video/rockchip-panel.txt | 34
1 file changed, 34 insertions(+)
diff --git a/Documentation/devicetree/bindings/video/rockchip-panel.txt
b/Documentation/devicetree/bindings/video/rockchip-panel.txt
index f599806..f6d80f6 100644
--- a/Documentation/devicetree/bindings/video/rockchip-panel.txt
+++ b/Documentation/devicetree/bindings/video/rockchip-panel.txt
@@ -80,3 +80,37 @@ Example:
rockchip,data-width = 24;
rockchip,panel = panel;
};
+
+Rockchip RK3288 EDP interface
+
+Required properties:
+-compatible: rockchip,rk3288-edp;
+
+- reg: physical base address of the controller and length
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped region.
+- clock-names: from common clock binding:
+ Required elements: clk_edp
+ clk_edp_24m
+ clk_edp_24m_parent
+ pclk_edp
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+ - edp
+- rockchip,panel: required a panel node
+
+Example:
+ edp: edp@ff97 {
+ compatible = rockchip,rk3288-edp;
+reg = 0xff97 0x4000;
+interrupts = GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH;
+clocks = cru SCLK_EDP, cru SCLK_EDP_24M, cru
PCLK_EDP_CTRL, xin24m;
+clock-names = clk_edp, clk_edp_24m, pclk_edp,
clk_edp_24m_parent;
+
+rockchip,grf = grf;
+resets = cru 111;
+reset-names = edp;
+ rockchip,panel = panel;
+ };
--
1.7.9.5
--
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