Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, [...] Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. >>> >>> >>> It should then come under *single IP muliple PHY* category similar >>> to what >>> Sylwester has done. [...] >> >> The idea is to model the driver as close to the hardware though I understand >> there won't be any advantages w.r.t power or performance. maybe in later >> versions of the IP we'll have separate bits to control usb3 and usb2. > > Ok, i will prepare the next patchset for separating out the possible > code based on > the UTMI+ or PIPE3 phys. Though when experimenting with the PHY > settings i can see > there's little of such code :-) > >> >> I think for power control we should have both usb3 and usb2 power-on callback >> calling a single function that controls the power bit. > Right. I will do that. Have posted the next version of patch with functionality to support multiple PHYs as suggested. Please review the same. Thanks !! -- Best Regards Vivek Gautam Samsung R Institute, Bangalore India -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, [...] Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. [...] The idea is to model the driver as close to the hardware though I understand there won't be any advantages w.r.t power or performance. maybe in later versions of the IP we'll have separate bits to control usb3 and usb2. Ok, i will prepare the next patchset for separating out the possible code based on the UTMI+ or PIPE3 phys. Though when experimenting with the PHY settings i can see there's little of such code :-) I think for power control we should have both usb3 and usb2 power-on callback calling a single function that controls the power bit. Right. I will do that. Have posted the next version of patch with functionality to support multiple PHYs as suggested. Please review the same. Thanks !! -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
HI Kishon On Tue, Jan 7, 2014 at 3:19 PM, Kishon Vijay Abraham I wrote: > Hi, > > On Monday 30 December 2013 03:13 PM, Vivek Gautam wrote: >> Hi Kishon, >> >> >> On Tue, Dec 24, 2013 at 11:15 PM, Kishon Vijay Abraham I >> wrote: >>> Hi, >>> >>> >>> On Thursday 05 December 2013 01:44 PM, Vivek Gautam wrote: Hi Kishon, On Wed, Dec 4, 2013 at 7:58 PM, Kishon Vijay Abraham I wrote: > > Hi Vivek, > > On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote: >> >> Hi, >> >> On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote: >>> >>> On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I >>> wrote: On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: > > Hi Kishon, > > > On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I > wrote: >> >> Hi, > > sorry for the delayed response. > >> >> On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: >>> >>> On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han wrote: >>> >>> >>> [.] >>> > USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 > block. > This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 > block > and 2.0 block, respectively. > > Conclusion: > > 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device > Base address: 0x1213 > > 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) > Base address: 0x1210 > 2.0 block(UTMI+) & 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? >>> >>> >>> Right. >>> >>> While 3.0 block(PIPE3) can be used for Super Speed, 2.0 >>> block(UTMI+) >>> can be used for High speed. >> >> >> It should then come under *single IP muliple PHY* category similar >> to what >> Sylwester has done. > > > Do you mean that i should be including PHY IDs for UTMI+ phy and > PIPE3 > phy present in this PHY block ? > AFAICS the two phys (UTMI+ and PIPE3) do not really have separate > registers to program, and that's the reason > we program the entire PHY in a shot. you mean you program the same set of bits for UTMI+ and PIPE3? >>> >>> >>> No, looking closely into PHY datasheet as well as Exynos5250 manual, i >>> can see that UTMI+ and PIPE3 >>> phys have separate bit settings. So i think we should be able to >>> segregate the two PHYs (UTMI+ and PIPE3). >>> Pardon me for my earlier observations. >> >> >> no problem.. >>> >>> Let me clarify more with our h/w team also on this and then i will >>> confirm with this. > > > Did you get more information on this? Yes, i have been in contact with our hardware team. The functionality of setting up UTMI+ and PIPE3 phys separately, and thereby using only one functionality of the two at some point of time (either high speed or super speed) hasn't been tested so far. >>> >>> >>> Irrespective of whether we are able to test the functionality separately or >>> not, we should model it as multiple PHYs since you have separate bit >>> settings for UTMI+ and PIPE3. >>> >>> (I'll review your next patch version shortly). >> >> Thanks Kishon, i know i am disturbing you in the holiday season. :-) >> But there's one concern, on Exynos5 platforms we have only one bit to >> power control >> the entire PHY (irrespective of the two PHYs present in the USB 3.0 >> PHY controller). >> So anyways we won't be able to save anything on the power front even >> if we program only >> one PHY (UTMI/PIPE3). >> Although there are PHY settings register bits which seem separate for >> the two phys. r >> What do you suggest in that case ? > > The idea is to model the driver as close to the hardware though I understand > there won't be any advantages w.r.t power or performance. maybe in later > versions of the IP we'll have separate bits to control usb3 and usb2. Ok, i will prepare the next patchset for separating out the possible code based on the UTMI+ or PIPE3 phys. Though when experimenting with the PHY settings i can see there's little of such code :-) > > I think for power control we should have both usb3 and usb2 power-on callback > calling a single function that controls
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi, On Monday 30 December 2013 03:13 PM, Vivek Gautam wrote: > Hi Kishon, > > > On Tue, Dec 24, 2013 at 11:15 PM, Kishon Vijay Abraham I > wrote: >> Hi, >> >> >> On Thursday 05 December 2013 01:44 PM, Vivek Gautam wrote: >>> >>> Hi Kishon, >>> >>> >>> On Wed, Dec 4, 2013 at 7:58 PM, Kishon Vijay Abraham I >>> wrote: Hi Vivek, On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote: > > Hi, > > On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote: >> >> On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I >> wrote: >>> >>> On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I wrote: > > Hi, sorry for the delayed response. > > On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: >> >> On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: >>> >>> On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han >>> wrote: >> >> >> [.] >> USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) & 3.0 block(PIPE3) >>> >>> >>> And this is of course the PHY used by DWC3 controller, which works >>> at >>> both High speed as well as Super Speed. >>> Right ? >> >> >> Right. >> >> While 3.0 block(PIPE3) can be used for Super Speed, 2.0 >> block(UTMI+) >> can be used for High speed. > > > It should then come under *single IP muliple PHY* category similar > to what > Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. >>> >>> >>> you mean you program the same set of bits for UTMI+ and PIPE3? >> >> >> No, looking closely into PHY datasheet as well as Exynos5250 manual, i >> can see that UTMI+ and PIPE3 >> phys have separate bit settings. So i think we should be able to >> segregate the two PHYs (UTMI+ and PIPE3). >> Pardon me for my earlier observations. > > > no problem.. >> >> Let me clarify more with our h/w team also on this and then i will >> confirm with this. Did you get more information on this? >>> >>> >>> Yes, i have been in contact with our hardware team. >>> The functionality of setting up UTMI+ and PIPE3 phys separately, and >>> thereby using only one functionality of the two >>> at some point of time (either high speed or super speed) hasn't been >>> tested so far. >> >> >> Irrespective of whether we are able to test the functionality separately or >> not, we should model it as multiple PHYs since you have separate bit >> settings for UTMI+ and PIPE3. >> >> (I'll review your next patch version shortly). > > Thanks Kishon, i know i am disturbing you in the holiday season. :-) > But there's one concern, on Exynos5 platforms we have only one bit to > power control > the entire PHY (irrespective of the two PHYs present in the USB 3.0 > PHY controller). > So anyways we won't be able to save anything on the power front even > if we program only > one PHY (UTMI/PIPE3). > Although there are PHY settings register bits which seem separate for > the two phys. r > What do you suggest in that case ? The idea is to model the driver as close to the hardware though I understand there won't be any advantages w.r.t power or performance. maybe in later versions of the IP we'll have separate bits to control usb3 and usb2. I think for power control we should have both usb3 and usb2 power-on callback calling a single function that controls the power bit. Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi, On Monday 30 December 2013 03:13 PM, Vivek Gautam wrote: Hi Kishon, On Tue, Dec 24, 2013 at 11:15 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Thursday 05 December 2013 01:44 PM, Vivek Gautam wrote: Hi Kishon, On Wed, Dec 4, 2013 at 7:58 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi Vivek, On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote: Hi, On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote: On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, sorry for the delayed response. On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. you mean you program the same set of bits for UTMI+ and PIPE3? No, looking closely into PHY datasheet as well as Exynos5250 manual, i can see that UTMI+ and PIPE3 phys have separate bit settings. So i think we should be able to segregate the two PHYs (UTMI+ and PIPE3). Pardon me for my earlier observations. no problem.. Let me clarify more with our h/w team also on this and then i will confirm with this. Did you get more information on this? Yes, i have been in contact with our hardware team. The functionality of setting up UTMI+ and PIPE3 phys separately, and thereby using only one functionality of the two at some point of time (either high speed or super speed) hasn't been tested so far. Irrespective of whether we are able to test the functionality separately or not, we should model it as multiple PHYs since you have separate bit settings for UTMI+ and PIPE3. (I'll review your next patch version shortly). Thanks Kishon, i know i am disturbing you in the holiday season. :-) But there's one concern, on Exynos5 platforms we have only one bit to power control the entire PHY (irrespective of the two PHYs present in the USB 3.0 PHY controller). So anyways we won't be able to save anything on the power front even if we program only one PHY (UTMI/PIPE3). Although there are PHY settings register bits which seem separate for the two phys. r What do you suggest in that case ? The idea is to model the driver as close to the hardware though I understand there won't be any advantages w.r.t power or performance. maybe in later versions of the IP we'll have separate bits to control usb3 and usb2. I think for power control we should have both usb3 and usb2 power-on callback calling a single function that controls the power bit. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
HI Kishon On Tue, Jan 7, 2014 at 3:19 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Monday 30 December 2013 03:13 PM, Vivek Gautam wrote: Hi Kishon, On Tue, Dec 24, 2013 at 11:15 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Thursday 05 December 2013 01:44 PM, Vivek Gautam wrote: Hi Kishon, On Wed, Dec 4, 2013 at 7:58 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi Vivek, On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote: Hi, On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote: On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, sorry for the delayed response. On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. you mean you program the same set of bits for UTMI+ and PIPE3? No, looking closely into PHY datasheet as well as Exynos5250 manual, i can see that UTMI+ and PIPE3 phys have separate bit settings. So i think we should be able to segregate the two PHYs (UTMI+ and PIPE3). Pardon me for my earlier observations. no problem.. Let me clarify more with our h/w team also on this and then i will confirm with this. Did you get more information on this? Yes, i have been in contact with our hardware team. The functionality of setting up UTMI+ and PIPE3 phys separately, and thereby using only one functionality of the two at some point of time (either high speed or super speed) hasn't been tested so far. Irrespective of whether we are able to test the functionality separately or not, we should model it as multiple PHYs since you have separate bit settings for UTMI+ and PIPE3. (I'll review your next patch version shortly). Thanks Kishon, i know i am disturbing you in the holiday season. :-) But there's one concern, on Exynos5 platforms we have only one bit to power control the entire PHY (irrespective of the two PHYs present in the USB 3.0 PHY controller). So anyways we won't be able to save anything on the power front even if we program only one PHY (UTMI/PIPE3). Although there are PHY settings register bits which seem separate for the two phys. r What do you suggest in that case ? The idea is to model the driver as close to the hardware though I understand there won't be any advantages w.r.t power or performance. maybe in later versions of the IP we'll have separate bits to control usb3 and usb2. Ok, i will prepare the next patchset for separating out the possible code based on the UTMI+ or PIPE3 phys. Though when experimenting with the PHY settings i can see there's little of such code :-) I think for power control we should have both usb3 and usb2 power-on callback calling a single function that controls the power bit. Right. I will do that. -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, On Tue, Dec 24, 2013 at 11:15 PM, Kishon Vijay Abraham I wrote: > Hi, > > > On Thursday 05 December 2013 01:44 PM, Vivek Gautam wrote: >> >> Hi Kishon, >> >> >> On Wed, Dec 4, 2013 at 7:58 PM, Kishon Vijay Abraham I >> wrote: >>> >>> Hi Vivek, >>> >>> On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote: Hi, On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote: > > On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I > wrote: >> >> On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: >>> >>> Hi Kishon, >>> >>> >>> On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I >>> wrote: Hi, >>> >>> sorry for the delayed response. >>> On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: > > On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: >> >> On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han >> wrote: > > > [.] > >>> USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 >>> block. >>> This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 >>> block >>> and 2.0 block, respectively. >>> >>> Conclusion: >>> >>> 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device >>> Base address: 0x1213 >>> >>> 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) >>> Base address: 0x1210 >>> 2.0 block(UTMI+) & 3.0 block(PIPE3) >> >> >> And this is of course the PHY used by DWC3 controller, which works >> at >> both High speed as well as Super Speed. >> Right ? > > > Right. > > While 3.0 block(PIPE3) can be used for Super Speed, 2.0 > block(UTMI+) > can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. >>> >>> >>> Do you mean that i should be including PHY IDs for UTMI+ phy and >>> PIPE3 >>> phy present in this PHY block ? >>> AFAICS the two phys (UTMI+ and PIPE3) do not really have separate >>> registers to program, and that's the reason >>> we program the entire PHY in a shot. >> >> >> you mean you program the same set of bits for UTMI+ and PIPE3? > > > No, looking closely into PHY datasheet as well as Exynos5250 manual, i > can see that UTMI+ and PIPE3 > phys have separate bit settings. So i think we should be able to > segregate the two PHYs (UTMI+ and PIPE3). > Pardon me for my earlier observations. no problem.. > > Let me clarify more with our h/w team also on this and then i will > confirm with this. >>> >>> >>> Did you get more information on this? >> >> >> Yes, i have been in contact with our hardware team. >> The functionality of setting up UTMI+ and PIPE3 phys separately, and >> thereby using only one functionality of the two >> at some point of time (either high speed or super speed) hasn't been >> tested so far. > > > Irrespective of whether we are able to test the functionality separately or > not, we should model it as multiple PHYs since you have separate bit > settings for UTMI+ and PIPE3. > > (I'll review your next patch version shortly). Thanks Kishon, i know i am disturbing you in the holiday season. :-) But there's one concern, on Exynos5 platforms we have only one bit to power control the entire PHY (irrespective of the two PHYs present in the USB 3.0 PHY controller). So anyways we won't be able to save anything on the power front even if we program only one PHY (UTMI/PIPE3). Although there are PHY settings register bits which seem separate for the two phys. What do you suggest in that case ? May be i am not able to understand you properly on the front of multiple PHYs > > Cheers > Kishon > > >> So i will be looking into this and try to find out proper init >> sequences for the two available PHYs >> separately and as soon as i get a working solution for this, i will >> update. >> >>> >>> Thanks >>> Kishon >> >> >> >> > -- Best Regards Vivek Gautam Samsung R Institute, Bangalore India -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, On Tue, Dec 24, 2013 at 11:15 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Thursday 05 December 2013 01:44 PM, Vivek Gautam wrote: Hi Kishon, On Wed, Dec 4, 2013 at 7:58 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi Vivek, On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote: Hi, On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote: On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, sorry for the delayed response. On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. you mean you program the same set of bits for UTMI+ and PIPE3? No, looking closely into PHY datasheet as well as Exynos5250 manual, i can see that UTMI+ and PIPE3 phys have separate bit settings. So i think we should be able to segregate the two PHYs (UTMI+ and PIPE3). Pardon me for my earlier observations. no problem.. Let me clarify more with our h/w team also on this and then i will confirm with this. Did you get more information on this? Yes, i have been in contact with our hardware team. The functionality of setting up UTMI+ and PIPE3 phys separately, and thereby using only one functionality of the two at some point of time (either high speed or super speed) hasn't been tested so far. Irrespective of whether we are able to test the functionality separately or not, we should model it as multiple PHYs since you have separate bit settings for UTMI+ and PIPE3. (I'll review your next patch version shortly). Thanks Kishon, i know i am disturbing you in the holiday season. :-) But there's one concern, on Exynos5 platforms we have only one bit to power control the entire PHY (irrespective of the two PHYs present in the USB 3.0 PHY controller). So anyways we won't be able to save anything on the power front even if we program only one PHY (UTMI/PIPE3). Although there are PHY settings register bits which seem separate for the two phys. What do you suggest in that case ? May be i am not able to understand you properly on the front of multiple PHYs Cheers Kishon So i will be looking into this and try to find out proper init sequences for the two available PHYs separately and as soon as i get a working solution for this, i will update. Thanks Kishon -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi, On Thursday 05 December 2013 01:44 PM, Vivek Gautam wrote: Hi Kishon, On Wed, Dec 4, 2013 at 7:58 PM, Kishon Vijay Abraham I wrote: Hi Vivek, On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote: Hi, On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote: On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I wrote: On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I wrote: Hi, sorry for the delayed response. On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) & 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. you mean you program the same set of bits for UTMI+ and PIPE3? No, looking closely into PHY datasheet as well as Exynos5250 manual, i can see that UTMI+ and PIPE3 phys have separate bit settings. So i think we should be able to segregate the two PHYs (UTMI+ and PIPE3). Pardon me for my earlier observations. no problem.. Let me clarify more with our h/w team also on this and then i will confirm with this. Did you get more information on this? Yes, i have been in contact with our hardware team. The functionality of setting up UTMI+ and PIPE3 phys separately, and thereby using only one functionality of the two at some point of time (either high speed or super speed) hasn't been tested so far. Irrespective of whether we are able to test the functionality separately or not, we should model it as multiple PHYs since you have separate bit settings for UTMI+ and PIPE3. (I'll review your next patch version shortly). Cheers Kishon So i will be looking into this and try to find out proper init sequences for the two available PHYs separately and as soon as i get a working solution for this, i will update. Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi, On Thursday 05 December 2013 01:44 PM, Vivek Gautam wrote: Hi Kishon, On Wed, Dec 4, 2013 at 7:58 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi Vivek, On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote: Hi, On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote: On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, sorry for the delayed response. On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. you mean you program the same set of bits for UTMI+ and PIPE3? No, looking closely into PHY datasheet as well as Exynos5250 manual, i can see that UTMI+ and PIPE3 phys have separate bit settings. So i think we should be able to segregate the two PHYs (UTMI+ and PIPE3). Pardon me for my earlier observations. no problem.. Let me clarify more with our h/w team also on this and then i will confirm with this. Did you get more information on this? Yes, i have been in contact with our hardware team. The functionality of setting up UTMI+ and PIPE3 phys separately, and thereby using only one functionality of the two at some point of time (either high speed or super speed) hasn't been tested so far. Irrespective of whether we are able to test the functionality separately or not, we should model it as multiple PHYs since you have separate bit settings for UTMI+ and PIPE3. (I'll review your next patch version shortly). Cheers Kishon So i will be looking into this and try to find out proper init sequences for the two available PHYs separately and as soon as i get a working solution for this, i will update. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, On Wed, Dec 4, 2013 at 7:58 PM, Kishon Vijay Abraham I wrote: > Hi Vivek, > > On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote: >> Hi, >> >> On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote: >>> On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I >>> wrote: On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: > Hi Kishon, > > > On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I > wrote: >> Hi, > sorry for the delayed response. > >> >> On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: >>> On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han wrote: >>> >>> [.] >>> > USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. > This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block > and 2.0 block, respectively. > > Conclusion: > >1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device >Base address: 0x1213 > >2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) >Base address: 0x1210 >2.0 block(UTMI+) & 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? >>> >>> Right. >>> >>> While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) >>> can be used for High speed. >> >> It should then come under *single IP muliple PHY* category similar to >> what >> Sylwester has done. > > Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 > phy present in this PHY block ? > AFAICS the two phys (UTMI+ and PIPE3) do not really have separate > registers to program, and that's the reason > we program the entire PHY in a shot. you mean you program the same set of bits for UTMI+ and PIPE3? >>> >>> No, looking closely into PHY datasheet as well as Exynos5250 manual, i >>> can see that UTMI+ and PIPE3 >>> phys have separate bit settings. So i think we should be able to >>> segregate the two PHYs (UTMI+ and PIPE3). >>> Pardon me for my earlier observations. >> >> no problem.. >>> Let me clarify more with our h/w team also on this and then i will >>> confirm with this. > > Did you get more information on this? Yes, i have been in contact with our hardware team. The functionality of setting up UTMI+ and PIPE3 phys separately, and thereby using only one functionality of the two at some point of time (either high speed or super speed) hasn't been tested so far. So i will be looking into this and try to find out proper init sequences for the two available PHYs separately and as soon as i get a working solution for this, i will update. > > Thanks > Kishon -- Best Regards Vivek Gautam Samsung R Institute, Bangalore India -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, On Wed, Dec 4, 2013 at 7:58 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi Vivek, On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote: Hi, On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote: On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, sorry for the delayed response. On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. you mean you program the same set of bits for UTMI+ and PIPE3? No, looking closely into PHY datasheet as well as Exynos5250 manual, i can see that UTMI+ and PIPE3 phys have separate bit settings. So i think we should be able to segregate the two PHYs (UTMI+ and PIPE3). Pardon me for my earlier observations. no problem.. Let me clarify more with our h/w team also on this and then i will confirm with this. Did you get more information on this? Yes, i have been in contact with our hardware team. The functionality of setting up UTMI+ and PIPE3 phys separately, and thereby using only one functionality of the two at some point of time (either high speed or super speed) hasn't been tested so far. So i will be looking into this and try to find out proper init sequences for the two available PHYs separately and as soon as i get a working solution for this, i will update. Thanks Kishon -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Vivek, On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote: > Hi, > > On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote: >> On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I >> wrote: >>> On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I wrote: > Hi, sorry for the delayed response. > > On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: >> On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: >>> On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han wrote: >> >> [.] >> USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) & 3.0 block(PIPE3) >>> >>> And this is of course the PHY used by DWC3 controller, which works at >>> both High speed as well as Super Speed. >>> Right ? >> >> Right. >> >> While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) >> can be used for High speed. > > It should then come under *single IP muliple PHY* category similar to what > Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. >>> >>> you mean you program the same set of bits for UTMI+ and PIPE3? >> >> No, looking closely into PHY datasheet as well as Exynos5250 manual, i >> can see that UTMI+ and PIPE3 >> phys have separate bit settings. So i think we should be able to >> segregate the two PHYs (UTMI+ and PIPE3). >> Pardon me for my earlier observations. > > no problem.. >> Let me clarify more with our h/w team also on this and then i will >> confirm with this. Did you get more information on this? Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Vivek, On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote: Hi, On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote: On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, sorry for the delayed response. On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. you mean you program the same set of bits for UTMI+ and PIPE3? No, looking closely into PHY datasheet as well as Exynos5250 manual, i can see that UTMI+ and PIPE3 phys have separate bit settings. So i think we should be able to segregate the two PHYs (UTMI+ and PIPE3). Pardon me for my earlier observations. no problem.. Let me clarify more with our h/w team also on this and then i will confirm with this. Did you get more information on this? Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I wrote: > On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: >> Hi Kishon, >> >> >> On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I >> wrote: >>> Hi, >> sorry for the delayed response. >> >>> >>> On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: > On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han wrote: [.] >> USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. >> This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block >> and 2.0 block, respectively. >> >> Conclusion: >> >>1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device >>Base address: 0x1213 >> >>2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) >>Base address: 0x1210 >>2.0 block(UTMI+) & 3.0 block(PIPE3) > > And this is of course the PHY used by DWC3 controller, which works at > both High speed as well as Super Speed. > Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. >>> >>> It should then come under *single IP muliple PHY* category similar to what >>> Sylwester has done. >> >> Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 >> phy present in this PHY block ? >> AFAICS the two phys (UTMI+ and PIPE3) do not really have separate >> registers to program, and that's the reason >> we program the entire PHY in a shot. > > you mean you program the same set of bits for UTMI+ and PIPE3? No, looking closely into PHY datasheet as well as Exynos5250 manual, i can see that UTMI+ and PIPE3 phys have separate bit settings. So i think we should be able to segregate the two PHYs (UTMI+ and PIPE3). Pardon me for my earlier observations. Let me clarify more with our h/w team also on this and then i will confirm with this. > > Thanks > Kishon -- Best Regards Vivek Gautam Samsung R Institute, Bangalore India -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: > Hi Kishon, > > > On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I wrote: >> Hi, > sorry for the delayed response. > >> >> On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: >>> On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han wrote: >>> >>> [.] >>> > USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. > This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block > and 2.0 block, respectively. > > Conclusion: > >1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device >Base address: 0x1213 > >2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) >Base address: 0x1210 >2.0 block(UTMI+) & 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? >>> >>> Right. >>> >>> While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) >>> can be used for High speed. >> >> It should then come under *single IP muliple PHY* category similar to what >> Sylwester has done. > > Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 > phy present in this PHY block ? > AFAICS the two phys (UTMI+ and PIPE3) do not really have separate > registers to program, and that's the reason > we program the entire PHY in a shot. you mean you program the same set of bits for UTMI+ and PIPE3? Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I wrote: > Hi, sorry for the delayed response. > > On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: >> On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: >>> On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han wrote: >> >> [.] >> USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) & 3.0 block(PIPE3) >>> >>> And this is of course the PHY used by DWC3 controller, which works at >>> both High speed as well as Super Speed. >>> Right ? >> >> Right. >> >> While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) >> can be used for High speed. > > It should then come under *single IP muliple PHY* category similar to what > Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. > > Thanks > Kishon -- Best Regards Vivek Gautam Samsung R Institute, Bangalore India -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Wed, Nov 20, 2013 at 2:14 PM, Vivek Gautam wrote:
> Hi Tomasz,
>
>
> On Sun, Nov 10, 2013 at 7:38 PM, Tomasz Figa wrote:
>> Hi Vivek,
>>
>> On Thursday 31 of October 2013 13:15:41 Vivek Gautam wrote:
>>> Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
>>> The new driver uses the generic PHY framework and will interact
>>> with DWC3 controller present on Exynos5 series of SoCs.
>>>
>>> Signed-off-by: Vivek Gautam
>>> ---
>>> .../devicetree/bindings/phy/samsung-phy.txt| 20 +
>>> drivers/phy/Kconfig|7 +
>>> drivers/phy/Makefile |1 +
>>> drivers/phy/phy-exynos5-usb3.c | 562
>>>
>>> 4 files changed, 590 insertions(+), 0 deletions(-)
>>> create mode 100644 drivers/phy/phy-exynos5-usb3.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
>>> b/Documentation/devicetree/bindings/phy/samsung-phy.txt
>>> index c0fccaa..9b5c111 100644
>>> --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
>>> +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
>>> @@ -20,3 +20,23 @@ Required properties:
>>> - compatible : should be "samsung,exynos5250-dp-video-phy";
>>> - reg : offset and length of the Display Port PHY register set;
>>> - #phy-cells : from the generic PHY bindings, must be 0;
>>> +
>>> +Samsung Exynos5 SoC seiries USB 3.0 PHY controller
>>
>> typo: s/seiries/series/
> will correct it.
>
>>
>>> +--
>>> +
>>> +Required properties:
>>> +- compatible :
>>> + should be "samsung,exynos5250-usb3phy" for exynos5250 SoC
>>> + should be "samsung,exynos5420-usb3phy" for exynos5420 SoC
>>
>> I'd slightly change this into something like this:
>>
>> - compatible: Should be set to one of following supported values:
>> - "samsung,exynos5250-usb3phy" - for Exynos5250 SoC,
>> - "samsung,exynos5420-usb3phy" - for Exynos5420 SoC.
>
> sure, will make it as suggested.
>
>>
>>> +- reg : Register offset and length array
>>> + - first field corresponds to USB 3.0 PHY register set;
>>> + - second field corresponds to PHY power isolation register
>>> + present in PMU;
>>
>> For consistency and to make things more future-proof, you should consider
>> using the PMU indirectly, through the syscon interface, as done in Leela
>> Krishna Amudala's series[1] in case of watchdog driver.
>
> Right that's a better way to do.
> But this will again introduce the register offset arithmetic once again.
> And in case of multiple USB 3.0 PHY controllers (like for Exynos5420),
> we would need to take extra care of each such offset, by having
> provision for aliases
> for the usb3phy nodes and then setting required offset before doing isolation.
>
> For Exynos5420 USB3.0 PHY channel 0 is controlled by 0x10040704; and
> USB3.0 PHY channel 1 is controlled by 0x10040708.
Or i think i can add PHY IDs similar to what Sylwester does for
MIPI_CSIS and MIPI_DSIM,
so that i will have something like this:
enum exynos5_usb3phy_id {
EXYNOS5_USB3PHY0,
EXYNOS5_USB3PHY1,
};
and then make use of this to add respective offsets to the pmu reg
base address as obtained from syscon node (0x1004).
>
>>
>> I will tell Kamil to do the same for USB 2.0 PHY as well.
>>
>> [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/24652
>>
>>> +- clocks: Clock IDs array as required by the controller
>>> +- clock-names: names of clocks correseponding to IDs in the clock property;
>>> + Required clocks:
>>> + - first clock is main PHY clock (same as USB 3.0 controller IP clock)
>>> + - second clock is reference clock (usually crystal clock)
>>> + optional clock:
>>> + - third clock is special clock used by PHY for operation
>>
>> Is this clock really optional? It looks like it's required for Exynos5420.
>
> Yes, this clock is an additional clock for Exynos5420 rather then
> being just optional
>
>> If so, you should instead change this to:
>>
>> "Additional clocks required for Exynos5420:"
>
> Ok will change this.
>
>>
>> Also you have not specified names of the clocks, just what they are.
>> Please remember that those are input names, so you can imagine them as
>> names of clock input pins of the IP block, not SoC-level clock names.
>
> So you mean, similar to what driver requests (clocks with their input names) ?
> will add clock names.
>
>>
>>> +- #phy-cells : from the generic PHY bindings, must be 0;
>>
>> I'd also add an example of correct USB 3.0 PHY device tree node here.
>
> Sorry, forgot to add an example of the device node :-)
> will add one.
>
>>
>>> diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c
>>> new file mode 100644
>>> index 000..b9a2674
>>> --- /dev/null
>>> +++ b/drivers/phy/phy-exynos5-usb3.c
>>> @@ -0,0 +1,562 @@
>> [snip]
>>> +#define EXYNOS5_DRD_PHYRESUME(0x34)
>>> +#define
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Tomasz, On Sun, Nov 10, 2013 at 7:38 PM, Tomasz Figa wrote: > Hi Vivek, > > On Thursday 31 of October 2013 13:15:41 Vivek Gautam wrote: >> Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. >> The new driver uses the generic PHY framework and will interact >> with DWC3 controller present on Exynos5 series of SoCs. >> >> Signed-off-by: Vivek Gautam >> --- >> .../devicetree/bindings/phy/samsung-phy.txt| 20 + >> drivers/phy/Kconfig|7 + >> drivers/phy/Makefile |1 + >> drivers/phy/phy-exynos5-usb3.c | 562 >> >> 4 files changed, 590 insertions(+), 0 deletions(-) >> create mode 100644 drivers/phy/phy-exynos5-usb3.c >> >> diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt >> b/Documentation/devicetree/bindings/phy/samsung-phy.txt >> index c0fccaa..9b5c111 100644 >> --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt >> +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt >> @@ -20,3 +20,23 @@ Required properties: >> - compatible : should be "samsung,exynos5250-dp-video-phy"; >> - reg : offset and length of the Display Port PHY register set; >> - #phy-cells : from the generic PHY bindings, must be 0; >> + >> +Samsung Exynos5 SoC seiries USB 3.0 PHY controller > > typo: s/seiries/series/ will correct it. > >> +-- >> + >> +Required properties: >> +- compatible : >> + should be "samsung,exynos5250-usb3phy" for exynos5250 SoC >> + should be "samsung,exynos5420-usb3phy" for exynos5420 SoC > > I'd slightly change this into something like this: > > - compatible: Should be set to one of following supported values: > - "samsung,exynos5250-usb3phy" - for Exynos5250 SoC, > - "samsung,exynos5420-usb3phy" - for Exynos5420 SoC. sure, will make it as suggested. > >> +- reg : Register offset and length array >> + - first field corresponds to USB 3.0 PHY register set; >> + - second field corresponds to PHY power isolation register >> + present in PMU; > > For consistency and to make things more future-proof, you should consider > using the PMU indirectly, through the syscon interface, as done in Leela > Krishna Amudala's series[1] in case of watchdog driver. Right that's a better way to do. But this will again introduce the register offset arithmetic once again. And in case of multiple USB 3.0 PHY controllers (like for Exynos5420), we would need to take extra care of each such offset, by having provision for aliases for the usb3phy nodes and then setting required offset before doing isolation. For Exynos5420 USB3.0 PHY channel 0 is controlled by 0x10040704; and USB3.0 PHY channel 1 is controlled by 0x10040708. > > I will tell Kamil to do the same for USB 2.0 PHY as well. > > [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/24652 > >> +- clocks: Clock IDs array as required by the controller >> +- clock-names: names of clocks correseponding to IDs in the clock property; >> + Required clocks: >> + - first clock is main PHY clock (same as USB 3.0 controller IP clock) >> + - second clock is reference clock (usually crystal clock) >> + optional clock: >> + - third clock is special clock used by PHY for operation > > Is this clock really optional? It looks like it's required for Exynos5420. Yes, this clock is an additional clock for Exynos5420 rather then being just optional > If so, you should instead change this to: > > "Additional clocks required for Exynos5420:" Ok will change this. > > Also you have not specified names of the clocks, just what they are. > Please remember that those are input names, so you can imagine them as > names of clock input pins of the IP block, not SoC-level clock names. So you mean, similar to what driver requests (clocks with their input names) ? will add clock names. > >> +- #phy-cells : from the generic PHY bindings, must be 0; > > I'd also add an example of correct USB 3.0 PHY device tree node here. Sorry, forgot to add an example of the device node :-) will add one. > >> diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c >> new file mode 100644 >> index 000..b9a2674 >> --- /dev/null >> +++ b/drivers/phy/phy-exynos5-usb3.c >> @@ -0,0 +1,562 @@ > [snip] >> +#define EXYNOS5_DRD_PHYRESUME(0x34) >> +#define EXYNOS5_DRD_LINKPORT (0x44) >> + >> + > > nit: Duplicate blank line. will remove it. > >> +/* Isolation, configured in the power management unit */ >> +#define EXYNOS5_USB_ISOL_DRD (1 << 0) >> + >> +#define CLKSEL_ERROR -1 > > What's this? Hmm..i shouldn't be defining error codes out of blue, will remove it. > >> + >> +#ifndef KHZ >> +#define KHZ 1000 >> +#endif >> + >> +#ifndef MHZ >> +#define MHZ (KHZ * KHZ) >> +#endif > > Do you really need the #ifndef's above? You are right. #ifndef not
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Tomasz, On Sun, Nov 10, 2013 at 7:38 PM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Vivek, On Thursday 31 of October 2013 13:15:41 Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/phy/samsung-phy.txt| 20 + drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5-usb3.c | 562 4 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-exynos5-usb3.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index c0fccaa..9b5c111 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -20,3 +20,23 @@ Required properties: - compatible : should be samsung,exynos5250-dp-video-phy; - reg : offset and length of the Display Port PHY register set; - #phy-cells : from the generic PHY bindings, must be 0; + +Samsung Exynos5 SoC seiries USB 3.0 PHY controller typo: s/seiries/series/ will correct it. +-- + +Required properties: +- compatible : + should be samsung,exynos5250-usb3phy for exynos5250 SoC + should be samsung,exynos5420-usb3phy for exynos5420 SoC I'd slightly change this into something like this: - compatible: Should be set to one of following supported values: - samsung,exynos5250-usb3phy - for Exynos5250 SoC, - samsung,exynos5420-usb3phy - for Exynos5420 SoC. sure, will make it as suggested. +- reg : Register offset and length array + - first field corresponds to USB 3.0 PHY register set; + - second field corresponds to PHY power isolation register + present in PMU; For consistency and to make things more future-proof, you should consider using the PMU indirectly, through the syscon interface, as done in Leela Krishna Amudala's series[1] in case of watchdog driver. Right that's a better way to do. But this will again introduce the register offset arithmetic once again. And in case of multiple USB 3.0 PHY controllers (like for Exynos5420), we would need to take extra care of each such offset, by having provision for aliases for the usb3phy nodes and then setting required offset before doing isolation. For Exynos5420 USB3.0 PHY channel 0 is controlled by 0x10040704; and USB3.0 PHY channel 1 is controlled by 0x10040708. I will tell Kamil to do the same for USB 2.0 PHY as well. [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/24652 +- clocks: Clock IDs array as required by the controller +- clock-names: names of clocks correseponding to IDs in the clock property; + Required clocks: + - first clock is main PHY clock (same as USB 3.0 controller IP clock) + - second clock is reference clock (usually crystal clock) + optional clock: + - third clock is special clock used by PHY for operation Is this clock really optional? It looks like it's required for Exynos5420. Yes, this clock is an additional clock for Exynos5420 rather then being just optional If so, you should instead change this to: Additional clocks required for Exynos5420: Ok will change this. Also you have not specified names of the clocks, just what they are. Please remember that those are input names, so you can imagine them as names of clock input pins of the IP block, not SoC-level clock names. So you mean, similar to what driver requests (clocks with their input names) ? will add clock names. +- #phy-cells : from the generic PHY bindings, must be 0; I'd also add an example of correct USB 3.0 PHY device tree node here. Sorry, forgot to add an example of the device node :-) will add one. diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c new file mode 100644 index 000..b9a2674 --- /dev/null +++ b/drivers/phy/phy-exynos5-usb3.c @@ -0,0 +1,562 @@ [snip] +#define EXYNOS5_DRD_PHYRESUME(0x34) +#define EXYNOS5_DRD_LINKPORT (0x44) + + nit: Duplicate blank line. will remove it. +/* Isolation, configured in the power management unit */ +#define EXYNOS5_USB_ISOL_DRD (1 0) + +#define CLKSEL_ERROR -1 What's this? Hmm..i shouldn't be defining error codes out of blue, will remove it. + +#ifndef KHZ +#define KHZ 1000 +#endif + +#ifndef MHZ +#define MHZ (KHZ * KHZ) +#endif Do you really need the #ifndef's above? You are right. #ifndef not really needed, since no header included here have these definitions. Although for samsung i can see they are defined in
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Wed, Nov 20, 2013 at 2:14 PM, Vivek Gautam gautamvivek1...@gmail.com wrote:
Hi Tomasz,
On Sun, Nov 10, 2013 at 7:38 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Vivek,
On Thursday 31 of October 2013 13:15:41 Vivek Gautam wrote:
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver uses the generic PHY framework and will interact
with DWC3 controller present on Exynos5 series of SoCs.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
.../devicetree/bindings/phy/samsung-phy.txt| 20 +
drivers/phy/Kconfig|7 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos5-usb3.c | 562
4 files changed, 590 insertions(+), 0 deletions(-)
create mode 100644 drivers/phy/phy-exynos5-usb3.c
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index c0fccaa..9b5c111 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -20,3 +20,23 @@ Required properties:
- compatible : should be samsung,exynos5250-dp-video-phy;
- reg : offset and length of the Display Port PHY register set;
- #phy-cells : from the generic PHY bindings, must be 0;
+
+Samsung Exynos5 SoC seiries USB 3.0 PHY controller
typo: s/seiries/series/
will correct it.
+--
+
+Required properties:
+- compatible :
+ should be samsung,exynos5250-usb3phy for exynos5250 SoC
+ should be samsung,exynos5420-usb3phy for exynos5420 SoC
I'd slightly change this into something like this:
- compatible: Should be set to one of following supported values:
- samsung,exynos5250-usb3phy - for Exynos5250 SoC,
- samsung,exynos5420-usb3phy - for Exynos5420 SoC.
sure, will make it as suggested.
+- reg : Register offset and length array
+ - first field corresponds to USB 3.0 PHY register set;
+ - second field corresponds to PHY power isolation register
+ present in PMU;
For consistency and to make things more future-proof, you should consider
using the PMU indirectly, through the syscon interface, as done in Leela
Krishna Amudala's series[1] in case of watchdog driver.
Right that's a better way to do.
But this will again introduce the register offset arithmetic once again.
And in case of multiple USB 3.0 PHY controllers (like for Exynos5420),
we would need to take extra care of each such offset, by having
provision for aliases
for the usb3phy nodes and then setting required offset before doing isolation.
For Exynos5420 USB3.0 PHY channel 0 is controlled by 0x10040704; and
USB3.0 PHY channel 1 is controlled by 0x10040708.
Or i think i can add PHY IDs similar to what Sylwester does for
MIPI_CSIS and MIPI_DSIM,
so that i will have something like this:
enum exynos5_usb3phy_id {
EXYNOS5_USB3PHY0,
EXYNOS5_USB3PHY1,
};
and then make use of this to add respective offsets to the pmu reg
base address as obtained from syscon node (0x1004).
I will tell Kamil to do the same for USB 2.0 PHY as well.
[1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/24652
+- clocks: Clock IDs array as required by the controller
+- clock-names: names of clocks correseponding to IDs in the clock property;
+ Required clocks:
+ - first clock is main PHY clock (same as USB 3.0 controller IP clock)
+ - second clock is reference clock (usually crystal clock)
+ optional clock:
+ - third clock is special clock used by PHY for operation
Is this clock really optional? It looks like it's required for Exynos5420.
Yes, this clock is an additional clock for Exynos5420 rather then
being just optional
If so, you should instead change this to:
Additional clocks required for Exynos5420:
Ok will change this.
Also you have not specified names of the clocks, just what they are.
Please remember that those are input names, so you can imagine them as
names of clock input pins of the IP block, not SoC-level clock names.
So you mean, similar to what driver requests (clocks with their input names) ?
will add clock names.
+- #phy-cells : from the generic PHY bindings, must be 0;
I'd also add an example of correct USB 3.0 PHY device tree node here.
Sorry, forgot to add an example of the device node :-)
will add one.
diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c
new file mode 100644
index 000..b9a2674
--- /dev/null
+++ b/drivers/phy/phy-exynos5-usb3.c
@@ -0,0 +1,562 @@
[snip]
+#define EXYNOS5_DRD_PHYRESUME(0x34)
+#define EXYNOS5_DRD_LINKPORT (0x44)
+
+
nit: Duplicate blank line.
will remove it.
+/* Isolation, configured in the power management unit */
+#define EXYNOS5_USB_ISOL_DRD (1 0)
+
+#define
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, sorry for the delayed response. On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. Thanks Kishon -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, sorry for the delayed response. On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. you mean you program the same set of bits for UTMI+ and PIPE3? Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, sorry for the delayed response. On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. you mean you program the same set of bits for UTMI+ and PIPE3? No, looking closely into PHY datasheet as well as Exynos5250 manual, i can see that UTMI+ and PIPE3 phys have separate bit settings. So i think we should be able to segregate the two PHYs (UTMI+ and PIPE3). Pardon me for my earlier observations. Let me clarify more with our h/w team also on this and then i will confirm with this. Thanks Kishon -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi, On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: > On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: >> On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han wrote: > > [.] > >>> USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. >>> This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block >>> and 2.0 block, respectively. >>> >>> Conclusion: >>> >>>1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device >>>Base address: 0x1213 >>> >>>2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) >>>Base address: 0x1210 >>>2.0 block(UTMI+) & 3.0 block(PIPE3) >> >> And this is of course the PHY used by DWC3 controller, which works at >> both High speed as well as Super Speed. >> Right ? > > Right. > > While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) > can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi, On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Vivek,
On Thursday 31 of October 2013 13:15:41 Vivek Gautam wrote:
> Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
> The new driver uses the generic PHY framework and will interact
> with DWC3 controller present on Exynos5 series of SoCs.
>
> Signed-off-by: Vivek Gautam
> ---
> .../devicetree/bindings/phy/samsung-phy.txt| 20 +
> drivers/phy/Kconfig|7 +
> drivers/phy/Makefile |1 +
> drivers/phy/phy-exynos5-usb3.c | 562
>
> 4 files changed, 590 insertions(+), 0 deletions(-)
> create mode 100644 drivers/phy/phy-exynos5-usb3.c
>
> diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
> b/Documentation/devicetree/bindings/phy/samsung-phy.txt
> index c0fccaa..9b5c111 100644
> --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
> @@ -20,3 +20,23 @@ Required properties:
> - compatible : should be "samsung,exynos5250-dp-video-phy";
> - reg : offset and length of the Display Port PHY register set;
> - #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Samsung Exynos5 SoC seiries USB 3.0 PHY controller
typo: s/seiries/series/
> +--
> +
> +Required properties:
> +- compatible :
> + should be "samsung,exynos5250-usb3phy" for exynos5250 SoC
> + should be "samsung,exynos5420-usb3phy" for exynos5420 SoC
I'd slightly change this into something like this:
- compatible: Should be set to one of following supported values:
- "samsung,exynos5250-usb3phy" - for Exynos5250 SoC,
- "samsung,exynos5420-usb3phy" - for Exynos5420 SoC.
> +- reg : Register offset and length array
> + - first field corresponds to USB 3.0 PHY register set;
> + - second field corresponds to PHY power isolation register
> + present in PMU;
For consistency and to make things more future-proof, you should consider
using the PMU indirectly, through the syscon interface, as done in Leela
Krishna Amudala's series[1] in case of watchdog driver.
I will tell Kamil to do the same for USB 2.0 PHY as well.
[1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/24652
> +- clocks: Clock IDs array as required by the controller
> +- clock-names: names of clocks correseponding to IDs in the clock property;
> + Required clocks:
> + - first clock is main PHY clock (same as USB 3.0 controller IP clock)
> + - second clock is reference clock (usually crystal clock)
> + optional clock:
> + - third clock is special clock used by PHY for operation
Is this clock really optional? It looks like it's required for Exynos5420.
If so, you should instead change this to:
"Additional clocks required for Exynos5420:"
Also you have not specified names of the clocks, just what they are.
Please remember that those are input names, so you can imagine them as
names of clock input pins of the IP block, not SoC-level clock names.
> +- #phy-cells : from the generic PHY bindings, must be 0;
I'd also add an example of correct USB 3.0 PHY device tree node here.
> diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c
> new file mode 100644
> index 000..b9a2674
> --- /dev/null
> +++ b/drivers/phy/phy-exynos5-usb3.c
> @@ -0,0 +1,562 @@
[snip]
> +#define EXYNOS5_DRD_PHYRESUME(0x34)
> +#define EXYNOS5_DRD_LINKPORT (0x44)
> +
> +
nit: Duplicate blank line.
> +/* Isolation, configured in the power management unit */
> +#define EXYNOS5_USB_ISOL_DRD (1 << 0)
> +
> +#define CLKSEL_ERROR -1
What's this?
> +
> +#ifndef KHZ
> +#define KHZ 1000
> +#endif
> +
> +#ifndef MHZ
> +#define MHZ (KHZ * KHZ)
> +#endif
Do you really need the #ifndef's above?
> +
> +enum samsung_cpu_type {
> + TYPE_EXYNOS5250,
> + TYPE_EXYNOS5420,
> +};
Instead of using this kind of enumeration, I'd rather introduce a struct
that describes the differences between all supported types.
> +
> +enum usb3phy_state {
> + STATE_OFF,
> + STATE_ON,
> +};
Hmm, isn't it a simple boolean value - false and true?
> +
> +struct usb3phy_config {
> + enum samsung_cpu_type cpu;
> + bool has_sclk_usbphy30;
> +};
Oh, you already have such struct, so there is even a bigger reason to drop
the samsung_cpu_type enum above.
> +
> +struct usb3phy_instance {
> + char *label;
> + struct usb3phy_driver *drv;
> + struct phy *phy;
> + enum usb3phy_state state;
> + u32 clk;
> + unsigned long rate;
> +};
You seem to have just one instance in this driver. Do you really
need this struct?
> +
> +struct usb3phy_driver {
> + struct device *dev;
> + void __iomem *reg_phy;
> + void __iomem *reg_isol;
> + struct clk *clk;
> + struct clk *sclk_usbphy30;
> + struct usb3phy_instance instance;
Fields from that struct could be simply
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Vivek,
On Thursday 31 of October 2013 13:15:41 Vivek Gautam wrote:
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver uses the generic PHY framework and will interact
with DWC3 controller present on Exynos5 series of SoCs.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
.../devicetree/bindings/phy/samsung-phy.txt| 20 +
drivers/phy/Kconfig|7 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos5-usb3.c | 562
4 files changed, 590 insertions(+), 0 deletions(-)
create mode 100644 drivers/phy/phy-exynos5-usb3.c
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index c0fccaa..9b5c111 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -20,3 +20,23 @@ Required properties:
- compatible : should be samsung,exynos5250-dp-video-phy;
- reg : offset and length of the Display Port PHY register set;
- #phy-cells : from the generic PHY bindings, must be 0;
+
+Samsung Exynos5 SoC seiries USB 3.0 PHY controller
typo: s/seiries/series/
+--
+
+Required properties:
+- compatible :
+ should be samsung,exynos5250-usb3phy for exynos5250 SoC
+ should be samsung,exynos5420-usb3phy for exynos5420 SoC
I'd slightly change this into something like this:
- compatible: Should be set to one of following supported values:
- samsung,exynos5250-usb3phy - for Exynos5250 SoC,
- samsung,exynos5420-usb3phy - for Exynos5420 SoC.
+- reg : Register offset and length array
+ - first field corresponds to USB 3.0 PHY register set;
+ - second field corresponds to PHY power isolation register
+ present in PMU;
For consistency and to make things more future-proof, you should consider
using the PMU indirectly, through the syscon interface, as done in Leela
Krishna Amudala's series[1] in case of watchdog driver.
I will tell Kamil to do the same for USB 2.0 PHY as well.
[1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/24652
+- clocks: Clock IDs array as required by the controller
+- clock-names: names of clocks correseponding to IDs in the clock property;
+ Required clocks:
+ - first clock is main PHY clock (same as USB 3.0 controller IP clock)
+ - second clock is reference clock (usually crystal clock)
+ optional clock:
+ - third clock is special clock used by PHY for operation
Is this clock really optional? It looks like it's required for Exynos5420.
If so, you should instead change this to:
Additional clocks required for Exynos5420:
Also you have not specified names of the clocks, just what they are.
Please remember that those are input names, so you can imagine them as
names of clock input pins of the IP block, not SoC-level clock names.
+- #phy-cells : from the generic PHY bindings, must be 0;
I'd also add an example of correct USB 3.0 PHY device tree node here.
diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c
new file mode 100644
index 000..b9a2674
--- /dev/null
+++ b/drivers/phy/phy-exynos5-usb3.c
@@ -0,0 +1,562 @@
[snip]
+#define EXYNOS5_DRD_PHYRESUME(0x34)
+#define EXYNOS5_DRD_LINKPORT (0x44)
+
+
nit: Duplicate blank line.
+/* Isolation, configured in the power management unit */
+#define EXYNOS5_USB_ISOL_DRD (1 0)
+
+#define CLKSEL_ERROR -1
What's this?
+
+#ifndef KHZ
+#define KHZ 1000
+#endif
+
+#ifndef MHZ
+#define MHZ (KHZ * KHZ)
+#endif
Do you really need the #ifndef's above?
+
+enum samsung_cpu_type {
+ TYPE_EXYNOS5250,
+ TYPE_EXYNOS5420,
+};
Instead of using this kind of enumeration, I'd rather introduce a struct
that describes the differences between all supported types.
+
+enum usb3phy_state {
+ STATE_OFF,
+ STATE_ON,
+};
Hmm, isn't it a simple boolean value - false and true?
+
+struct usb3phy_config {
+ enum samsung_cpu_type cpu;
+ bool has_sclk_usbphy30;
+};
Oh, you already have such struct, so there is even a bigger reason to drop
the samsung_cpu_type enum above.
+
+struct usb3phy_instance {
+ char *label;
+ struct usb3phy_driver *drv;
+ struct phy *phy;
+ enum usb3phy_state state;
+ u32 clk;
+ unsigned long rate;
+};
You seem to have just one instance in this driver. Do you really
need this struct?
+
+struct usb3phy_driver {
+ struct device *dev;
+ void __iomem *reg_phy;
+ void __iomem *reg_isol;
+ struct clk *clk;
+ struct clk *sclk_usbphy30;
+ struct usb3phy_instance instance;
Fields from that struct could be simply moved here.
+};
+
+/*
+ * exynos5_rate_to_clk() converts the supplied clock rate to
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: > On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han wrote: [.] >> USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. >> This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block >> and 2.0 block, respectively. >> >> Conclusion: >> >>1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device >>Base address: 0x1213 >> >>2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) >>Base address: 0x1210 >>2.0 block(UTMI+) & 3.0 block(PIPE3) > > And this is of course the PHY used by DWC3 controller, which works at > both High speed as well as Super Speed. > Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. Best regards, Jingoo Han -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han wrote: > On Tuesday, November 05, 2013 8:13 PM, Jingoo Han wrote: >> On Tuesday, November 05, 2013 6:37 PM, Kamil Debski wrote: >> > On Tuesday, November 05, 2013 8:20 AM, Vivek Gautam wrote: >> > > On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I >> > > wrote: >> > > > On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: >> > > >> On Monday, November 04, 2013 7:55 AM, Kishon Vijay Abraham I wrote: >> > > >>> On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: >> > > >> > > Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. >> > > The new driver uses the generic PHY framework and will interact >> > > with >> > > DWC3 controller present on Exynos5 series of SoCs. >> > > >>> >> > > >>> >> > > >>> In Exynos, you have a single IP that supports both USB3 and USB2 >> > > PHY >> > > >>> right? I think that needs to be mentioned here. >> > > >> >> > > >> >> > > >> As far as I know the IP is different. >> > > > >> > > > >> > > > Ok. Sometime back Vivek was mentioning about a single IP for both >> > > USB3 >> > > > and USB2. Thought it should be this driver. Anyway thanks for the >> > > clarification. >> > > >> > > Right Kishon, I had mentioned that Exynos5's dwc3 controller have a >> > > single IP for USB2 and USB3 phy. >> > > From what i see, on exynos5 systems the dwc3 controller uses a combo of >> > > usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting >> > > 0x1210). >> > > >> > > Kamil, Tomasz, >> > > >> > > Please correct me if i am wrong. >> > >> > I have the Exynos 5250 documentation and I found two phy register ranges: >> > 1) USB 2.0 PHY having the base address of 0x1213 >> > Chapter 33. USB 2.0 Host Controller >> > Subchapter 33.5.2 Phy Control Register p. 1696 >> > First register's description is >> > "USB2.0 phy control register" >> > 2) USB 3.0 PHY (I guess) with the base address 0x1210 >> > Chapter 35. USB 3.0 DRD Controller >> > Subchapter 35.4.6 PHY Control Register p. 1872 >> > >> > Jingoo, could you comment on the above? You may know more than we do :) >> >> Hi Kamil, >> >> Thank you for trusting me. :-) >> I just asked my validation engineer about 5250 USB PHY. Thank you for clarifying this. This was really kind of you to help in making things clear. >> As I know, she has the best knowledge about Samsung SoC USB hardware. >> She said that there are 2 PHY controllers such as USB 2.0 PHY, USB 3.0 PHY. >> >> 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device >> 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) >> >> > In addition, I have a question to you Vivek - does your USB 3.0 >> > PHY support both host and device? >> >> According to her, USB3.0 PHY can support both 3.0 Host and 3.0 Device. >> Thank you. > > In addition to this, > > Vivek's comment is also right. :-) > A few minutes ago, I asked one of my USB S/W engineers. > > USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. > This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block > and 2.0 block, respectively. > > Conclusion: > >1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device >Base address: 0x1213 > >2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) >Base address: 0x1210 >2.0 block(UTMI+) & 3.0 block(PIPE3) And this is ofcourse the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? > > > Best regards, > Jingoo Han > -- Best Regards Vivek Gautam Samsung R Institute, Bangalore India -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kamil, On Tue, Nov 5, 2013 at 3:06 PM, Kamil Debski wrote: > Hi, > >> From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] >> Sent: Tuesday, November 05, 2013 8:20 AM >> To: Kishon Vijay Abraham I >> Cc: Kamil Debski; Vivek Gautam; Linux USB Mailing List; linux-samsung- >> s...@vger.kernel.org; linux-kernel@vger.kernel.org; >> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; >> linux-...@vger.kernel.org; Greg KH; Kukjin Kim; Sylwester Nawrocki; >> Tomasz Figa; Felipe Balbi; Julius Werner; Jingoo Han >> Subject: Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver >> >> Hi Kishon, >> >> >> >> On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I >> wrote: >> > Hi, >> > >> > >> > On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: >> >> >> >> Hi Kishon, >> >> >> >>> From: Kishon Vijay Abraham I [mailto:kis...@ti.com] >> >>> Sent: Monday, November 04, 2013 7:55 AM >> >>> >> >>> Hi Vivek, >> >>> >> >>> On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: >> >>>> >> >>>> Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. >> >>>> The new driver uses the generic PHY framework and will interact >> >>>> with >> >>>> DWC3 controller present on Exynos5 series of SoCs. >> >>> >> >>> >> >>> In Exynos, you have a single IP that supports both USB3 and USB2 >> PHY >> >>> right? I think that needs to be mentioned here. >> >> >> >> >> >> As far as I know the IP is different. >> > >> > >> > Ok. Sometime back Vivek was mentioning about a single IP for both >> USB3 >> > and USB2. Thought it should be this driver. Anyway thanks for the >> clarification. >> >> Right Kishon, I had mentioned that Exynos5's dwc3 controller have a >> single IP for USB2 and USB3 phy. >> From what i see, on exynos5 systems the dwc3 controller uses a combo of >> usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting >> 0x1210). >> >> Kamil, Tomasz, >> >> Please correct me if i am wrong. > > I have the Exynos 5250 documentation and I found two phy register ranges: > 1) USB 2.0 PHY having the base address of 0x1213 > Chapter 33. USB 2.0 Host Controller > Subchapter 33.5.2 Phy Control Register p. 1696 > First register's description is > "USB2.0 phy control register" > 2) USB 3.0 PHY (I guess) with the base address 0x1210 > Chapter 35. USB 3.0 DRD Controller > Subchapter 35.4.6 PHY Control Register p. 1872 > > Jingoo, could you comment on the above? You may know more than we do :) > > In addition, I have a question to you Vivek - does your USB 3.0 > PHY support both host and device? Yes, this PHY driver supports both Host as well as device type of operations of DWC3 controller. This driver is a straight port from older driver available at drivers/usb/phy/phy-samsung-usb3.c which also had been tested for host as well as device operation of DWC3. > > [snip] > > Best wishes, > Kamil Debski > -- Best Regards Vivek Gautam Samsung R Institute, Bangalore India -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tuesday, November 05, 2013 8:13 PM, Jingoo Han wrote: > On Tuesday, November 05, 2013 6:37 PM, Kamil Debski wrote: > > On Tuesday, November 05, 2013 8:20 AM, Vivek Gautam wrote: > > > On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I > > > wrote: > > > > On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: > > > >> On Monday, November 04, 2013 7:55 AM, Kishon Vijay Abraham I wrote: > > > >>> On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: > > > > > > Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. > > > The new driver uses the generic PHY framework and will interact > > > with > > > DWC3 controller present on Exynos5 series of SoCs. > > > >>> > > > >>> > > > >>> In Exynos, you have a single IP that supports both USB3 and USB2 > > > PHY > > > >>> right? I think that needs to be mentioned here. > > > >> > > > >> > > > >> As far as I know the IP is different. > > > > > > > > > > > > Ok. Sometime back Vivek was mentioning about a single IP for both > > > USB3 > > > > and USB2. Thought it should be this driver. Anyway thanks for the > > > clarification. > > > > > > Right Kishon, I had mentioned that Exynos5's dwc3 controller have a > > > single IP for USB2 and USB3 phy. > > > From what i see, on exynos5 systems the dwc3 controller uses a combo of > > > usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting > > > 0x1210). > > > > > > Kamil, Tomasz, > > > > > > Please correct me if i am wrong. > > > > I have the Exynos 5250 documentation and I found two phy register ranges: > > 1) USB 2.0 PHY having the base address of 0x1213 > > Chapter 33. USB 2.0 Host Controller > > Subchapter 33.5.2 Phy Control Register p. 1696 > > First register's description is > > "USB2.0 phy control register" > > 2) USB 3.0 PHY (I guess) with the base address 0x1210 > > Chapter 35. USB 3.0 DRD Controller > > Subchapter 35.4.6 PHY Control Register p. 1872 > > > > Jingoo, could you comment on the above? You may know more than we do :) > > Hi Kamil, > > Thank you for trusting me. :-) > I just asked my validation engineer about 5250 USB PHY. > As I know, she has the best knowledge about Samsung SoC USB hardware. > She said that there are 2 PHY controllers such as USB 2.0 PHY, USB 3.0 PHY. > > 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device > 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) > > > In addition, I have a question to you Vivek - does your USB 3.0 > > PHY support both host and device? > > According to her, USB3.0 PHY can support both 3.0 Host and 3.0 Device. > Thank you. In addition to this, Vivek's comment is also right. :-) A few minutes ago, I asked one of my USB S/W engineers. USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) & 3.0 block(PIPE3) Best regards, Jingoo Han -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tuesday, November 05, 2013 6:37 PM, Kamil Debski wrote: > On Tuesday, November 05, 2013 8:20 AM, Vivek Gautam wrote: > > On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I > > wrote: > > > On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: > > >> On Monday, November 04, 2013 7:55 AM, Kishon Vijay Abraham I wrote: > > >>> On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: > > > > Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. > > The new driver uses the generic PHY framework and will interact > > with > > DWC3 controller present on Exynos5 series of SoCs. > > >>> > > >>> > > >>> In Exynos, you have a single IP that supports both USB3 and USB2 > > PHY > > >>> right? I think that needs to be mentioned here. > > >> > > >> > > >> As far as I know the IP is different. > > > > > > > > > Ok. Sometime back Vivek was mentioning about a single IP for both > > USB3 > > > and USB2. Thought it should be this driver. Anyway thanks for the > > clarification. > > > > Right Kishon, I had mentioned that Exynos5's dwc3 controller have a > > single IP for USB2 and USB3 phy. > > From what i see, on exynos5 systems the dwc3 controller uses a combo of > > usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting > > 0x1210). > > > > Kamil, Tomasz, > > > > Please correct me if i am wrong. > > I have the Exynos 5250 documentation and I found two phy register ranges: > 1) USB 2.0 PHY having the base address of 0x1213 > Chapter 33. USB 2.0 Host Controller > Subchapter 33.5.2 Phy Control Register p. 1696 > First register's description is > "USB2.0 phy control register" > 2) USB 3.0 PHY (I guess) with the base address 0x1210 > Chapter 35. USB 3.0 DRD Controller > Subchapter 35.4.6 PHY Control Register p. 1872 > > Jingoo, could you comment on the above? You may know more than we do :) Hi Kamil, Thank you for trusting me. :-) I just asked my validation engineer about 5250 USB PHY. As I know, she has the best knowledge about Samsung SoC USB hardware. She said that there are 2 PHY controllers such as USB 2.0 PHY, USB 3.0 PHY. 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) > In addition, I have a question to you Vivek - does your USB 3.0 > PHY support both host and device? According to her, USB3.0 PHY can support both 3.0 Host and 3.0 Device. Thank you. Best regards, Jingoo Han -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi, > From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] > Sent: Tuesday, November 05, 2013 8:20 AM > To: Kishon Vijay Abraham I > Cc: Kamil Debski; Vivek Gautam; Linux USB Mailing List; linux-samsung- > s...@vger.kernel.org; linux-kernel@vger.kernel.org; > devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linux-...@vger.kernel.org; Greg KH; Kukjin Kim; Sylwester Nawrocki; > Tomasz Figa; Felipe Balbi; Julius Werner; Jingoo Han > Subject: Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver > > Hi Kishon, > > > > On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I > wrote: > > Hi, > > > > > > On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: > >> > >> Hi Kishon, > >> > >>> From: Kishon Vijay Abraham I [mailto:kis...@ti.com] > >>> Sent: Monday, November 04, 2013 7:55 AM > >>> > >>> Hi Vivek, > >>> > >>> On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: > >>>> > >>>> Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. > >>>> The new driver uses the generic PHY framework and will interact > >>>> with > >>>> DWC3 controller present on Exynos5 series of SoCs. > >>> > >>> > >>> In Exynos, you have a single IP that supports both USB3 and USB2 > PHY > >>> right? I think that needs to be mentioned here. > >> > >> > >> As far as I know the IP is different. > > > > > > Ok. Sometime back Vivek was mentioning about a single IP for both > USB3 > > and USB2. Thought it should be this driver. Anyway thanks for the > clarification. > > Right Kishon, I had mentioned that Exynos5's dwc3 controller have a > single IP for USB2 and USB3 phy. > From what i see, on exynos5 systems the dwc3 controller uses a combo of > usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting > 0x1210). > > Kamil, Tomasz, > > Please correct me if i am wrong. I have the Exynos 5250 documentation and I found two phy register ranges: 1) USB 2.0 PHY having the base address of 0x1213 Chapter 33. USB 2.0 Host Controller Subchapter 33.5.2 Phy Control Register p. 1696 First register's description is "USB2.0 phy control register" 2) USB 3.0 PHY (I guess) with the base address 0x1210 Chapter 35. USB 3.0 DRD Controller Subchapter 35.4.6 PHY Control Register p. 1872 Jingoo, could you comment on the above? You may know more than we do :) In addition, I have a question to you Vivek - does your USB 3.0 PHY support both host and device? [snip] Best wishes, Kamil Debski -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tuesday 05 of November 2013 12:50:18 Vivek Gautam wrote: > Hi Kishon, > > On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I wrote: > > Hi, > > > > On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: > >> Hi Kishon, > >> > >>> From: Kishon Vijay Abraham I [mailto:kis...@ti.com] > >>> Sent: Monday, November 04, 2013 7:55 AM > >>> > >>> Hi Vivek, > >>> > >>> On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: > Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. > The new driver uses the generic PHY framework and will interact > with > DWC3 controller present on Exynos5 series of SoCs. > >>> > >>> In Exynos, you have a single IP that supports both USB3 and USB2 PHY > >>> right? I think that needs to be mentioned here. > >> > >> As far as I know the IP is different. > > > > Ok. Sometime back Vivek was mentioning about a single IP for both USB3 > > and USB2. Thought it should be this driver. Anyway thanks for the > > clarification. > Right Kishon, I had mentioned that Exynos5's dwc3 controller have a > single IP for USB2 and USB3 phy. > From what i see, on exynos5 systems the dwc3 controller uses a combo > of usb 2 (utmi+) and usb 3 (pipe 3) phy > (with base address starting 0x1210). I meant there is a single PHY used with the USB 3.0 controller (dwc3) and it is different from the PHY used with the USB 2.0 controller (s3c-hsotg aka dwc2). The USB 3.0 PHY and controller blocks also support USB 2.0 operation, though. So we were both right. ;) Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tuesday 05 of November 2013 12:50:18 Vivek Gautam wrote: Hi Kishon, On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: Hi Kishon, From: Kishon Vijay Abraham I [mailto:kis...@ti.com] Sent: Monday, November 04, 2013 7:55 AM Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). I meant there is a single PHY used with the USB 3.0 controller (dwc3) and it is different from the PHY used with the USB 2.0 controller (s3c-hsotg aka dwc2). The USB 3.0 PHY and controller blocks also support USB 2.0 operation, though. So we were both right. ;) Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi, From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] Sent: Tuesday, November 05, 2013 8:20 AM To: Kishon Vijay Abraham I Cc: Kamil Debski; Vivek Gautam; Linux USB Mailing List; linux-samsung- s...@vger.kernel.org; linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-...@vger.kernel.org; Greg KH; Kukjin Kim; Sylwester Nawrocki; Tomasz Figa; Felipe Balbi; Julius Werner; Jingoo Han Subject: Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver Hi Kishon, On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: Hi Kishon, From: Kishon Vijay Abraham I [mailto:kis...@ti.com] Sent: Monday, November 04, 2013 7:55 AM Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). Kamil, Tomasz, Please correct me if i am wrong. I have the Exynos 5250 documentation and I found two phy register ranges: 1) USB 2.0 PHY having the base address of 0x1213 Chapter 33. USB 2.0 Host Controller Subchapter 33.5.2 Phy Control Register p. 1696 First register's description is USB2.0 phy control register 2) USB 3.0 PHY (I guess) with the base address 0x1210 Chapter 35. USB 3.0 DRD Controller Subchapter 35.4.6 PHY Control Register p. 1872 Jingoo, could you comment on the above? You may know more than we do :) In addition, I have a question to you Vivek - does your USB 3.0 PHY support both host and device? [snip] Best wishes, Kamil Debski -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tuesday, November 05, 2013 6:37 PM, Kamil Debski wrote: On Tuesday, November 05, 2013 8:20 AM, Vivek Gautam wrote: On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: On Monday, November 04, 2013 7:55 AM, Kishon Vijay Abraham I wrote: On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). Kamil, Tomasz, Please correct me if i am wrong. I have the Exynos 5250 documentation and I found two phy register ranges: 1) USB 2.0 PHY having the base address of 0x1213 Chapter 33. USB 2.0 Host Controller Subchapter 33.5.2 Phy Control Register p. 1696 First register's description is USB2.0 phy control register 2) USB 3.0 PHY (I guess) with the base address 0x1210 Chapter 35. USB 3.0 DRD Controller Subchapter 35.4.6 PHY Control Register p. 1872 Jingoo, could you comment on the above? You may know more than we do :) Hi Kamil, Thank you for trusting me. :-) I just asked my validation engineer about 5250 USB PHY. As I know, she has the best knowledge about Samsung SoC USB hardware. She said that there are 2 PHY controllers such as USB 2.0 PHY, USB 3.0 PHY. 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) In addition, I have a question to you Vivek - does your USB 3.0 PHY support both host and device? According to her, USB3.0 PHY can support both 3.0 Host and 3.0 Device. Thank you. Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tuesday, November 05, 2013 8:13 PM, Jingoo Han wrote: On Tuesday, November 05, 2013 6:37 PM, Kamil Debski wrote: On Tuesday, November 05, 2013 8:20 AM, Vivek Gautam wrote: On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: On Monday, November 04, 2013 7:55 AM, Kishon Vijay Abraham I wrote: On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). Kamil, Tomasz, Please correct me if i am wrong. I have the Exynos 5250 documentation and I found two phy register ranges: 1) USB 2.0 PHY having the base address of 0x1213 Chapter 33. USB 2.0 Host Controller Subchapter 33.5.2 Phy Control Register p. 1696 First register's description is USB2.0 phy control register 2) USB 3.0 PHY (I guess) with the base address 0x1210 Chapter 35. USB 3.0 DRD Controller Subchapter 35.4.6 PHY Control Register p. 1872 Jingoo, could you comment on the above? You may know more than we do :) Hi Kamil, Thank you for trusting me. :-) I just asked my validation engineer about 5250 USB PHY. As I know, she has the best knowledge about Samsung SoC USB hardware. She said that there are 2 PHY controllers such as USB 2.0 PHY, USB 3.0 PHY. 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) In addition, I have a question to you Vivek - does your USB 3.0 PHY support both host and device? According to her, USB3.0 PHY can support both 3.0 Host and 3.0 Device. Thank you. In addition to this, Vivek's comment is also right. :-) A few minutes ago, I asked one of my USB S/W engineers. USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kamil, On Tue, Nov 5, 2013 at 3:06 PM, Kamil Debski k.deb...@samsung.com wrote: Hi, From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] Sent: Tuesday, November 05, 2013 8:20 AM To: Kishon Vijay Abraham I Cc: Kamil Debski; Vivek Gautam; Linux USB Mailing List; linux-samsung- s...@vger.kernel.org; linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-...@vger.kernel.org; Greg KH; Kukjin Kim; Sylwester Nawrocki; Tomasz Figa; Felipe Balbi; Julius Werner; Jingoo Han Subject: Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver Hi Kishon, On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: Hi Kishon, From: Kishon Vijay Abraham I [mailto:kis...@ti.com] Sent: Monday, November 04, 2013 7:55 AM Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). Kamil, Tomasz, Please correct me if i am wrong. I have the Exynos 5250 documentation and I found two phy register ranges: 1) USB 2.0 PHY having the base address of 0x1213 Chapter 33. USB 2.0 Host Controller Subchapter 33.5.2 Phy Control Register p. 1696 First register's description is USB2.0 phy control register 2) USB 3.0 PHY (I guess) with the base address 0x1210 Chapter 35. USB 3.0 DRD Controller Subchapter 35.4.6 PHY Control Register p. 1872 Jingoo, could you comment on the above? You may know more than we do :) In addition, I have a question to you Vivek - does your USB 3.0 PHY support both host and device? Yes, this PHY driver supports both Host as well as device type of operations of DWC3 controller. This driver is a straight port from older driver available at drivers/usb/phy/phy-samsung-usb3.c which also had been tested for host as well as device operation of DWC3. [snip] Best wishes, Kamil Debski -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: On Tuesday, November 05, 2013 8:13 PM, Jingoo Han wrote: On Tuesday, November 05, 2013 6:37 PM, Kamil Debski wrote: On Tuesday, November 05, 2013 8:20 AM, Vivek Gautam wrote: On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: On Monday, November 04, 2013 7:55 AM, Kishon Vijay Abraham I wrote: On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). Kamil, Tomasz, Please correct me if i am wrong. I have the Exynos 5250 documentation and I found two phy register ranges: 1) USB 2.0 PHY having the base address of 0x1213 Chapter 33. USB 2.0 Host Controller Subchapter 33.5.2 Phy Control Register p. 1696 First register's description is USB2.0 phy control register 2) USB 3.0 PHY (I guess) with the base address 0x1210 Chapter 35. USB 3.0 DRD Controller Subchapter 35.4.6 PHY Control Register p. 1872 Jingoo, could you comment on the above? You may know more than we do :) Hi Kamil, Thank you for trusting me. :-) I just asked my validation engineer about 5250 USB PHY. Thank you for clarifying this. This was really kind of you to help in making things clear. As I know, she has the best knowledge about Samsung SoC USB hardware. She said that there are 2 PHY controllers such as USB 2.0 PHY, USB 3.0 PHY. 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) In addition, I have a question to you Vivek - does your USB 3.0 PHY support both host and device? According to her, USB3.0 PHY can support both 3.0 Host and 3.0 Device. Thank you. In addition to this, Vivek's comment is also right. :-) A few minutes ago, I asked one of my USB S/W engineers. USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is ofcourse the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Best regards, Jingoo Han -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I wrote: > Hi, > > > On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: >> >> Hi Kishon, >> >>> From: Kishon Vijay Abraham I [mailto:kis...@ti.com] >>> Sent: Monday, November 04, 2013 7:55 AM >>> >>> Hi Vivek, >>> >>> On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. >>> >>> >>> In Exynos, you have a single IP that supports both USB3 and USB2 PHY >>> right? I think that needs to be mentioned here. >> >> >> As far as I know the IP is different. > > > Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and > USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. >From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). Kamil, Tomasz, Please correct me if i am wrong. > > Cheers > Kishon > >> >>> Do you have separate registers that should be used for >>> initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? >>> If so, then you should model this driver as a single driver that >>> supports two PHYs similar to what Sylwester has done before? >> >> >> Best wishes, >> Kamil >> >>> Cheers >>> Kishon >>> Signed-off-by: Vivek Gautam --- .../devicetree/bindings/phy/samsung-phy.txt| 20 + drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5-usb3.c | 562 >>> >>> 4 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-exynos5-usb3.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index c0fccaa..9b5c111 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -20,3 +20,23 @@ Required properties: - compatible : should be "samsung,exynos5250-dp-video-phy"; - reg : offset and length of the Display Port PHY register set; - #phy-cells : from the generic PHY bindings, must be 0; + +Samsung Exynos5 SoC seiries USB 3.0 PHY controller +-- + +Required properties: +- compatible : + should be "samsung,exynos5250-usb3phy" for exynos5250 SoC + should be "samsung,exynos5420-usb3phy" for exynos5420 SoC +- reg : Register offset and length array + - first field corresponds to USB 3.0 PHY register set; + - second field corresponds to PHY power isolation register + present in PMU; +- clocks: Clock IDs array as required by the controller +- clock-names: names of clocks correseponding to IDs in the clock >>> >>> property; + Required clocks: + - first clock is main PHY clock (same as USB 3.0 controller IP >>> >>> clock) + - second clock is reference clock (usually crystal clock) + optional clock: + - third clock is special clock used by PHY for operation +- #phy-cells : from the generic PHY bindings, must be 0; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a344f3d..9a100c6 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO help Support for Display Port PHY found on Samsung EXYNOS SoCs. +config PHY_EXYNOS5_USB3 + tristate "Exynos5 SoC series USB 3.0 PHY driver" + depends on ARCH_EXYNOS5 + select GENERIC_PHY + help + Enable USB 3.0 PHY support for Exynos 5 SoC series + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d0caae9..9c06a61 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp- >>> >>> video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB)+= phy-twl4030-usb.o +obj-$(CONFIG_PHY_EXYNOS5_USB3) += phy-exynos5-usb3.o diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c new file mode 100644 index 000..b9a2674 --- /dev/null +++ b/drivers/phy/phy-exynos5-usb3.c @@ -0,0 +1,562 @@ +/* + * Samsung EXYNOS5 SoC
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tue, Nov 5, 2013 at 11:06 AM, Vivek Gautam wrote: > Hi Tomasz, Sorry my mail client had some problem, so forwarding this again. > > On Nov 4, 2013 5:59 PM, "Tomasz Figa" wrote: >> >> Hi Kishon, >> >> On Monday 04 of November 2013 12:24:42 Kishon Vijay Abraham I wrote: >> > Hi Vivek, >> > >> > On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: >> > > Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. >> > > The new driver uses the generic PHY framework and will interact >> > > with DWC3 controller present on Exynos5 series of SoCs. >> > >> > In Exynos, you have a single IP that supports both USB3 and USB2 PHY >> > right? I think that needs to be mentioned here. >> >> Nope. There are two separate, different IPs. > > AFAICS the dwc3 controller (aka usb 3.0 drd controller, as mentioned in > exynos5 UM) uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base > address starting 0x1210), thereby giving the driver only freedom to > control them as one. The entire set of registers with base 0x1210 for > exynos5250 and later 0x1250 for exynos5420 are being programmed by this > driver. That's the reason i structured the driver this way, and thereby it > makes the dwc3 controller to just use only single phy. > Please correct me if i am wrong. > >> >> > Do you have separate registers that should be used for >> > initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If >> > so, then you should model this driver as a single driver that supports >> > two PHYs similar to what Sylwester has done before? >> >> Sylwester's MIPI PHY uses such model because it has a single register >> that controls both PHYs. >> >> Best regards, >> Tomasz >> >> -- >> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in >> the body of a message to majord...@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html >> Please read the FAQ at http://www.tux.org/lkml/ -- Best Regards Vivek Gautam Samsung R Institute, Bangalore India -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi, On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: Hi Kishon, From: Kishon Vijay Abraham I [mailto:kis...@ti.com] Sent: Monday, November 04, 2013 7:55 AM Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Cheers Kishon Do you have separate registers that should be used for initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If so, then you should model this driver as a single driver that supports two PHYs similar to what Sylwester has done before? Best wishes, Kamil Cheers Kishon Signed-off-by: Vivek Gautam --- .../devicetree/bindings/phy/samsung-phy.txt| 20 + drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5-usb3.c | 562 4 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-exynos5-usb3.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index c0fccaa..9b5c111 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -20,3 +20,23 @@ Required properties: - compatible : should be "samsung,exynos5250-dp-video-phy"; - reg : offset and length of the Display Port PHY register set; - #phy-cells : from the generic PHY bindings, must be 0; + +Samsung Exynos5 SoC seiries USB 3.0 PHY controller +-- + +Required properties: +- compatible : + should be "samsung,exynos5250-usb3phy" for exynos5250 SoC + should be "samsung,exynos5420-usb3phy" for exynos5420 SoC +- reg : Register offset and length array + - first field corresponds to USB 3.0 PHY register set; + - second field corresponds to PHY power isolation register + present in PMU; +- clocks: Clock IDs array as required by the controller +- clock-names: names of clocks correseponding to IDs in the clock property; + Required clocks: + - first clock is main PHY clock (same as USB 3.0 controller IP clock) + - second clock is reference clock (usually crystal clock) + optional clock: + - third clock is special clock used by PHY for operation +- #phy-cells : from the generic PHY bindings, must be 0; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a344f3d..9a100c6 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO help Support for Display Port PHY found on Samsung EXYNOS SoCs. +config PHY_EXYNOS5_USB3 + tristate "Exynos5 SoC series USB 3.0 PHY driver" + depends on ARCH_EXYNOS5 + select GENERIC_PHY + help + Enable USB 3.0 PHY support for Exynos 5 SoC series + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d0caae9..9c06a61 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp- video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB)+= phy-twl4030-usb.o +obj-$(CONFIG_PHY_EXYNOS5_USB3) += phy-exynos5-usb3.o diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c new file mode 100644 index 000..b9a2674 --- /dev/null +++ b/drivers/phy/phy-exynos5-usb3.c @@ -0,0 +1,562 @@ +/* + * Samsung EXYNOS5 SoC series USB 3.0 PHY driver + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Vivek Gautam + * + * This program is free software; you can redistribute it and/or +modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Exynos USB PHY registers */ +#define EXYNOS5_FSEL_9MHZ6 0x0 +#define EXYNOS5_FSEL_10MHZ 0x1 +#define EXYNOS5_FSEL_12MHZ 0x2 +#define EXYNOS5_FSEL_19MHZ20x3 +#define EXYNOS5_FSEL_20MHZ 0x4 +#define EXYNOS5_FSEL_24MHZ 0x5 +#define EXYNOS5_FSEL_50MHZ 0x7 + +/* EXYNOS5: USB 3.0 DRD PHY registers */ +#define EXYNOS5_DRD_LINKSYSTEM (0x04) + +#define LINKSYSTEM_FLADJ_MASK
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Monday 04 November 2013 05:56 PM, Tomasz Figa wrote: Hi Kishon, On Monday 04 of November 2013 12:24:42 Kishon Vijay Abraham I wrote: Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. Nope. There are two separate, different IPs. Alright. Thanks for the clarification. Cheers Kishon Do you have separate registers that should be used for initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If so, then you should model this driver as a single driver that supports two PHYs similar to what Sylwester has done before? Sylwester's MIPI PHY uses such model because it has a single register that controls both PHYs. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, On Monday 04 of November 2013 12:24:42 Kishon Vijay Abraham I wrote: > Hi Vivek, > > On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: > > Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. > > The new driver uses the generic PHY framework and will interact > > with DWC3 controller present on Exynos5 series of SoCs. > > In Exynos, you have a single IP that supports both USB3 and USB2 PHY > right? I think that needs to be mentioned here. Nope. There are two separate, different IPs. > Do you have separate registers that should be used for > initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If > so, then you should model this driver as a single driver that supports > two PHYs similar to what Sylwester has done before? Sylwester's MIPI PHY uses such model because it has a single register that controls both PHYs. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, > From: Kishon Vijay Abraham I [mailto:kis...@ti.com] > Sent: Monday, November 04, 2013 7:55 AM > > Hi Vivek, > > On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: > > Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. > > The new driver uses the generic PHY framework and will interact with > > DWC3 controller present on Exynos5 series of SoCs. > > In Exynos, you have a single IP that supports both USB3 and USB2 PHY > right? I think that needs to be mentioned here. As far as I know the IP is different. > Do you have separate registers that should be used for > initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? > If so, then you should model this driver as a single driver that > supports two PHYs similar to what Sylwester has done before? Best wishes, Kamil > Cheers > Kishon > > > > > Signed-off-by: Vivek Gautam > > --- > > .../devicetree/bindings/phy/samsung-phy.txt| 20 + > > drivers/phy/Kconfig|7 + > > drivers/phy/Makefile |1 + > > drivers/phy/phy-exynos5-usb3.c | 562 > > > 4 files changed, 590 insertions(+), 0 deletions(-) > > create mode 100644 drivers/phy/phy-exynos5-usb3.c > > > > diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt > > b/Documentation/devicetree/bindings/phy/samsung-phy.txt > > index c0fccaa..9b5c111 100644 > > --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt > > +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt > > @@ -20,3 +20,23 @@ Required properties: > > - compatible : should be "samsung,exynos5250-dp-video-phy"; > > - reg : offset and length of the Display Port PHY register set; > > - #phy-cells : from the generic PHY bindings, must be 0; > > + > > +Samsung Exynos5 SoC seiries USB 3.0 PHY controller > > +-- > > + > > +Required properties: > > +- compatible : > > + should be "samsung,exynos5250-usb3phy" for exynos5250 SoC > > + should be "samsung,exynos5420-usb3phy" for exynos5420 SoC > > +- reg : Register offset and length array > > + - first field corresponds to USB 3.0 PHY register set; > > + - second field corresponds to PHY power isolation register > > + present in PMU; > > +- clocks: Clock IDs array as required by the controller > > +- clock-names: names of clocks correseponding to IDs in the clock > property; > > + Required clocks: > > + - first clock is main PHY clock (same as USB 3.0 controller IP > clock) > > + - second clock is reference clock (usually crystal clock) > > + optional clock: > > + - third clock is special clock used by PHY for operation > > +- #phy-cells : from the generic PHY bindings, must be 0; > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index > > a344f3d..9a100c6 100644 > > --- a/drivers/phy/Kconfig > > +++ b/drivers/phy/Kconfig > > @@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO > > help > > Support for Display Port PHY found on Samsung EXYNOS SoCs. > > > > +config PHY_EXYNOS5_USB3 > > + tristate "Exynos5 SoC series USB 3.0 PHY driver" > > + depends on ARCH_EXYNOS5 > > + select GENERIC_PHY > > + help > > + Enable USB 3.0 PHY support for Exynos 5 SoC series > > + > > endmenu > > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index > > d0caae9..9c06a61 100644 > > --- a/drivers/phy/Makefile > > +++ b/drivers/phy/Makefile > > @@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp- > video.o > > obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o > > obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o > > obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o > > +obj-$(CONFIG_PHY_EXYNOS5_USB3) += phy-exynos5-usb3.o > > diff --git a/drivers/phy/phy-exynos5-usb3.c > > b/drivers/phy/phy-exynos5-usb3.c new file mode 100644 index > > 000..b9a2674 > > --- /dev/null > > +++ b/drivers/phy/phy-exynos5-usb3.c > > @@ -0,0 +1,562 @@ > > +/* > > + * Samsung EXYNOS5 SoC series USB 3.0 PHY driver > > + * > > + * Copyright (C) 2013 Samsung Electronics Co., Ltd. > > + * Author: Vivek Gautam > > + * > > + * This program is free software; you can redistribute it and/or > > +modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* Exynos USB PHY registers */ > > +#define EXYNOS5_FSEL_9MHZ6 0x0 > > +#define EXYNOS5_FSEL_10MHZ 0x1 > > +#define EXYNOS5_FSEL_12MHZ 0x2 > > +#define EXYNOS5_FSEL_19MHZ20x3 > > +#define EXYNOS5_FSEL_20MHZ 0x4 > > +#define EXYNOS5_FSEL_24MHZ 0x5 > > +#define EXYNOS5_FSEL_50MHZ 0x7 > > + > > +/* EXYNOS5: USB 3.0 DRD PHY
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Tue, Nov 5, 2013 at 11:06 AM, Vivek Gautam gautamvivek1...@gmail.com wrote: Hi Tomasz, Sorry my mail client had some problem, so forwarding this again. On Nov 4, 2013 5:59 PM, Tomasz Figa t.f...@samsung.com wrote: Hi Kishon, On Monday 04 of November 2013 12:24:42 Kishon Vijay Abraham I wrote: Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. Nope. There are two separate, different IPs. AFAICS the dwc3 controller (aka usb 3.0 drd controller, as mentioned in exynos5 UM) uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210), thereby giving the driver only freedom to control them as one. The entire set of registers with base 0x1210 for exynos5250 and later 0x1250 for exynos5420 are being programmed by this driver. That's the reason i structured the driver this way, and thereby it makes the dwc3 controller to just use only single phy. Please correct me if i am wrong. Do you have separate registers that should be used for initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If so, then you should model this driver as a single driver that supports two PHYs similar to what Sylwester has done before? Sylwester's MIPI PHY uses such model because it has a single register that controls both PHYs. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, On Mon, Nov 4, 2013 at 6:42 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: Hi Kishon, From: Kishon Vijay Abraham I [mailto:kis...@ti.com] Sent: Monday, November 04, 2013 7:55 AM Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Right Kishon, I had mentioned that Exynos5's dwc3 controller have a single IP for USB2 and USB3 phy. From what i see, on exynos5 systems the dwc3 controller uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base address starting 0x1210). Kamil, Tomasz, Please correct me if i am wrong. Cheers Kishon Do you have separate registers that should be used for initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If so, then you should model this driver as a single driver that supports two PHYs similar to what Sylwester has done before? Best wishes, Kamil Cheers Kishon Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/phy/samsung-phy.txt| 20 + drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5-usb3.c | 562 4 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-exynos5-usb3.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index c0fccaa..9b5c111 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -20,3 +20,23 @@ Required properties: - compatible : should be samsung,exynos5250-dp-video-phy; - reg : offset and length of the Display Port PHY register set; - #phy-cells : from the generic PHY bindings, must be 0; + +Samsung Exynos5 SoC seiries USB 3.0 PHY controller +-- + +Required properties: +- compatible : + should be samsung,exynos5250-usb3phy for exynos5250 SoC + should be samsung,exynos5420-usb3phy for exynos5420 SoC +- reg : Register offset and length array + - first field corresponds to USB 3.0 PHY register set; + - second field corresponds to PHY power isolation register + present in PMU; +- clocks: Clock IDs array as required by the controller +- clock-names: names of clocks correseponding to IDs in the clock property; + Required clocks: + - first clock is main PHY clock (same as USB 3.0 controller IP clock) + - second clock is reference clock (usually crystal clock) + optional clock: + - third clock is special clock used by PHY for operation +- #phy-cells : from the generic PHY bindings, must be 0; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a344f3d..9a100c6 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO help Support for Display Port PHY found on Samsung EXYNOS SoCs. +config PHY_EXYNOS5_USB3 + tristate Exynos5 SoC series USB 3.0 PHY driver + depends on ARCH_EXYNOS5 + select GENERIC_PHY + help + Enable USB 3.0 PHY support for Exynos 5 SoC series + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d0caae9..9c06a61 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp- video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB)+= phy-twl4030-usb.o +obj-$(CONFIG_PHY_EXYNOS5_USB3) += phy-exynos5-usb3.o diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c new file mode 100644 index 000..b9a2674 --- /dev/null +++ b/drivers/phy/phy-exynos5-usb3.c @@ -0,0 +1,562 @@ +/* + * Samsung EXYNOS5 SoC series USB 3.0 PHY driver + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Vivek Gautam gautam.vi...@samsung.com + * + * This program is free software; you can redistribute it and/or +modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/delay.h +#include
RE: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, From: Kishon Vijay Abraham I [mailto:kis...@ti.com] Sent: Monday, November 04, 2013 7:55 AM Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Do you have separate registers that should be used for initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If so, then you should model this driver as a single driver that supports two PHYs similar to what Sylwester has done before? Best wishes, Kamil Cheers Kishon Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/phy/samsung-phy.txt| 20 + drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5-usb3.c | 562 4 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-exynos5-usb3.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index c0fccaa..9b5c111 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -20,3 +20,23 @@ Required properties: - compatible : should be samsung,exynos5250-dp-video-phy; - reg : offset and length of the Display Port PHY register set; - #phy-cells : from the generic PHY bindings, must be 0; + +Samsung Exynos5 SoC seiries USB 3.0 PHY controller +-- + +Required properties: +- compatible : + should be samsung,exynos5250-usb3phy for exynos5250 SoC + should be samsung,exynos5420-usb3phy for exynos5420 SoC +- reg : Register offset and length array + - first field corresponds to USB 3.0 PHY register set; + - second field corresponds to PHY power isolation register + present in PMU; +- clocks: Clock IDs array as required by the controller +- clock-names: names of clocks correseponding to IDs in the clock property; + Required clocks: + - first clock is main PHY clock (same as USB 3.0 controller IP clock) + - second clock is reference clock (usually crystal clock) + optional clock: + - third clock is special clock used by PHY for operation +- #phy-cells : from the generic PHY bindings, must be 0; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a344f3d..9a100c6 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO help Support for Display Port PHY found on Samsung EXYNOS SoCs. +config PHY_EXYNOS5_USB3 + tristate Exynos5 SoC series USB 3.0 PHY driver + depends on ARCH_EXYNOS5 + select GENERIC_PHY + help + Enable USB 3.0 PHY support for Exynos 5 SoC series + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d0caae9..9c06a61 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp- video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_EXYNOS5_USB3) += phy-exynos5-usb3.o diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c new file mode 100644 index 000..b9a2674 --- /dev/null +++ b/drivers/phy/phy-exynos5-usb3.c @@ -0,0 +1,562 @@ +/* + * Samsung EXYNOS5 SoC series USB 3.0 PHY driver + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Vivek Gautam gautam.vi...@samsung.com + * + * This program is free software; you can redistribute it and/or +modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/delay.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/of_address.h +#include linux/phy/phy.h +#include linux/platform_device.h +#include linux/mutex.h + +/* Exynos USB PHY registers */ +#define EXYNOS5_FSEL_9MHZ6 0x0 +#define EXYNOS5_FSEL_10MHZ 0x1 +#define EXYNOS5_FSEL_12MHZ 0x2 +#define EXYNOS5_FSEL_19MHZ20x3 +#define EXYNOS5_FSEL_20MHZ 0x4 +#define EXYNOS5_FSEL_24MHZ 0x5 +#define EXYNOS5_FSEL_50MHZ 0x7 + +/* EXYNOS5: USB 3.0 DRD PHY registers */ +#define EXYNOS5_DRD_LINKSYSTEM
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Kishon, On Monday 04 of November 2013 12:24:42 Kishon Vijay Abraham I wrote: Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. Nope. There are two separate, different IPs. Do you have separate registers that should be used for initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If so, then you should model this driver as a single driver that supports two PHYs similar to what Sylwester has done before? Sylwester's MIPI PHY uses such model because it has a single register that controls both PHYs. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Monday 04 November 2013 05:56 PM, Tomasz Figa wrote: Hi Kishon, On Monday 04 of November 2013 12:24:42 Kishon Vijay Abraham I wrote: Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. Nope. There are two separate, different IPs. Alright. Thanks for the clarification. Cheers Kishon Do you have separate registers that should be used for initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If so, then you should model this driver as a single driver that supports two PHYs similar to what Sylwester has done before? Sylwester's MIPI PHY uses such model because it has a single register that controls both PHYs. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi, On Monday 04 November 2013 03:45 PM, Kamil Debski wrote: Hi Kishon, From: Kishon Vijay Abraham I [mailto:kis...@ti.com] Sent: Monday, November 04, 2013 7:55 AM Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. As far as I know the IP is different. Ok. Sometime back Vivek was mentioning about a single IP for both USB3 and USB2. Thought it should be this driver. Anyway thanks for the clarification. Cheers Kishon Do you have separate registers that should be used for initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If so, then you should model this driver as a single driver that supports two PHYs similar to what Sylwester has done before? Best wishes, Kamil Cheers Kishon Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/phy/samsung-phy.txt| 20 + drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5-usb3.c | 562 4 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-exynos5-usb3.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index c0fccaa..9b5c111 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -20,3 +20,23 @@ Required properties: - compatible : should be samsung,exynos5250-dp-video-phy; - reg : offset and length of the Display Port PHY register set; - #phy-cells : from the generic PHY bindings, must be 0; + +Samsung Exynos5 SoC seiries USB 3.0 PHY controller +-- + +Required properties: +- compatible : + should be samsung,exynos5250-usb3phy for exynos5250 SoC + should be samsung,exynos5420-usb3phy for exynos5420 SoC +- reg : Register offset and length array + - first field corresponds to USB 3.0 PHY register set; + - second field corresponds to PHY power isolation register + present in PMU; +- clocks: Clock IDs array as required by the controller +- clock-names: names of clocks correseponding to IDs in the clock property; + Required clocks: + - first clock is main PHY clock (same as USB 3.0 controller IP clock) + - second clock is reference clock (usually crystal clock) + optional clock: + - third clock is special clock used by PHY for operation +- #phy-cells : from the generic PHY bindings, must be 0; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a344f3d..9a100c6 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO help Support for Display Port PHY found on Samsung EXYNOS SoCs. +config PHY_EXYNOS5_USB3 + tristate Exynos5 SoC series USB 3.0 PHY driver + depends on ARCH_EXYNOS5 + select GENERIC_PHY + help + Enable USB 3.0 PHY support for Exynos 5 SoC series + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d0caae9..9c06a61 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp- video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB)+= phy-twl4030-usb.o +obj-$(CONFIG_PHY_EXYNOS5_USB3) += phy-exynos5-usb3.o diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c new file mode 100644 index 000..b9a2674 --- /dev/null +++ b/drivers/phy/phy-exynos5-usb3.c @@ -0,0 +1,562 @@ +/* + * Samsung EXYNOS5 SoC series USB 3.0 PHY driver + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Vivek Gautam gautam.vi...@samsung.com + * + * This program is free software; you can redistribute it and/or +modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/delay.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/of_address.h +#include linux/phy/phy.h +#include linux/platform_device.h +#include linux/mutex.h + +/* Exynos USB PHY registers */ +#define EXYNOS5_FSEL_9MHZ6 0x0 +#define EXYNOS5_FSEL_10MHZ 0x1 +#define EXYNOS5_FSEL_12MHZ 0x2 +#define EXYNOS5_FSEL_19MHZ20x3 +#define EXYNOS5_FSEL_20MHZ 0x4 +#define EXYNOS5_FSEL_24MHZ 0x5
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. Do you have separate registers that should be used for initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If so, then you should model this driver as a single driver that supports two PHYs similar to what Sylwester has done before? Cheers Kishon Signed-off-by: Vivek Gautam --- .../devicetree/bindings/phy/samsung-phy.txt| 20 + drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5-usb3.c | 562 4 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-exynos5-usb3.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index c0fccaa..9b5c111 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -20,3 +20,23 @@ Required properties: - compatible : should be "samsung,exynos5250-dp-video-phy"; - reg : offset and length of the Display Port PHY register set; - #phy-cells : from the generic PHY bindings, must be 0; + +Samsung Exynos5 SoC seiries USB 3.0 PHY controller +-- + +Required properties: +- compatible : + should be "samsung,exynos5250-usb3phy" for exynos5250 SoC + should be "samsung,exynos5420-usb3phy" for exynos5420 SoC +- reg : Register offset and length array + - first field corresponds to USB 3.0 PHY register set; + - second field corresponds to PHY power isolation register + present in PMU; +- clocks: Clock IDs array as required by the controller +- clock-names: names of clocks correseponding to IDs in the clock property; + Required clocks: + - first clock is main PHY clock (same as USB 3.0 controller IP clock) + - second clock is reference clock (usually crystal clock) + optional clock: + - third clock is special clock used by PHY for operation +- #phy-cells : from the generic PHY bindings, must be 0; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a344f3d..9a100c6 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO help Support for Display Port PHY found on Samsung EXYNOS SoCs. +config PHY_EXYNOS5_USB3 + tristate "Exynos5 SoC series USB 3.0 PHY driver" + depends on ARCH_EXYNOS5 + select GENERIC_PHY + help + Enable USB 3.0 PHY support for Exynos 5 SoC series + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d0caae9..9c06a61 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_EXYNOS5_USB3) += phy-exynos5-usb3.o diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c new file mode 100644 index 000..b9a2674 --- /dev/null +++ b/drivers/phy/phy-exynos5-usb3.c @@ -0,0 +1,562 @@ +/* + * Samsung EXYNOS5 SoC series USB 3.0 PHY driver + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Vivek Gautam + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Exynos USB PHY registers */ +#define EXYNOS5_FSEL_9MHZ6 0x0 +#define EXYNOS5_FSEL_10MHZ 0x1 +#define EXYNOS5_FSEL_12MHZ 0x2 +#define EXYNOS5_FSEL_19MHZ20x3 +#define EXYNOS5_FSEL_20MHZ 0x4 +#define EXYNOS5_FSEL_24MHZ 0x5 +#define EXYNOS5_FSEL_50MHZ 0x7 + +/* EXYNOS5: USB 3.0 DRD PHY registers */ +#define EXYNOS5_DRD_LINKSYSTEM (0x04) + +#define LINKSYSTEM_FLADJ_MASK (0x3f << 1) +#define LINKSYSTEM_FLADJ(_x) ((_x) << 1) +#define LINKSYSTEM_XHCI_VERSION_CONTROL(0x1 << 27) + +#define EXYNOS5_DRD_PHYUTMI(0x08) + +#define PHYUTMI_OTGDISABLE (0x1 << 6) +#define PHYUTMI_FORCESUSPEND (0x1 << 1) +#define PHYUTMI_FORCESLEEP (0x1 << 0) + +#define EXYNOS5_DRD_PHYPIPE
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Vivek, On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. In Exynos, you have a single IP that supports both USB3 and USB2 PHY right? I think that needs to be mentioned here. Do you have separate registers that should be used for initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If so, then you should model this driver as a single driver that supports two PHYs similar to what Sylwester has done before? Cheers Kishon Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/phy/samsung-phy.txt| 20 + drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5-usb3.c | 562 4 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-exynos5-usb3.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index c0fccaa..9b5c111 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -20,3 +20,23 @@ Required properties: - compatible : should be samsung,exynos5250-dp-video-phy; - reg : offset and length of the Display Port PHY register set; - #phy-cells : from the generic PHY bindings, must be 0; + +Samsung Exynos5 SoC seiries USB 3.0 PHY controller +-- + +Required properties: +- compatible : + should be samsung,exynos5250-usb3phy for exynos5250 SoC + should be samsung,exynos5420-usb3phy for exynos5420 SoC +- reg : Register offset and length array + - first field corresponds to USB 3.0 PHY register set; + - second field corresponds to PHY power isolation register + present in PMU; +- clocks: Clock IDs array as required by the controller +- clock-names: names of clocks correseponding to IDs in the clock property; + Required clocks: + - first clock is main PHY clock (same as USB 3.0 controller IP clock) + - second clock is reference clock (usually crystal clock) + optional clock: + - third clock is special clock used by PHY for operation +- #phy-cells : from the generic PHY bindings, must be 0; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a344f3d..9a100c6 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO help Support for Display Port PHY found on Samsung EXYNOS SoCs. +config PHY_EXYNOS5_USB3 + tristate Exynos5 SoC series USB 3.0 PHY driver + depends on ARCH_EXYNOS5 + select GENERIC_PHY + help + Enable USB 3.0 PHY support for Exynos 5 SoC series + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d0caae9..9c06a61 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_EXYNOS5_USB3) += phy-exynos5-usb3.o diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c new file mode 100644 index 000..b9a2674 --- /dev/null +++ b/drivers/phy/phy-exynos5-usb3.c @@ -0,0 +1,562 @@ +/* + * Samsung EXYNOS5 SoC series USB 3.0 PHY driver + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Vivek Gautam gautam.vi...@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/delay.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/of_address.h +#include linux/phy/phy.h +#include linux/platform_device.h +#include linux/mutex.h + +/* Exynos USB PHY registers */ +#define EXYNOS5_FSEL_9MHZ6 0x0 +#define EXYNOS5_FSEL_10MHZ 0x1 +#define EXYNOS5_FSEL_12MHZ 0x2 +#define EXYNOS5_FSEL_19MHZ20x3 +#define EXYNOS5_FSEL_20MHZ 0x4 +#define EXYNOS5_FSEL_24MHZ 0x5 +#define EXYNOS5_FSEL_50MHZ 0x7 + +/* EXYNOS5: USB 3.0 DRD PHY registers */ +#define EXYNOS5_DRD_LINKSYSTEM (0x04) + +#define LINKSYSTEM_FLADJ_MASK (0x3f 1) +#define LINKSYSTEM_FLADJ(_x) ((_x) 1) +#define LINKSYSTEM_XHCI_VERSION_CONTROL(0x1 27) + +#define EXYNOS5_DRD_PHYUTMI(0x08) + +#define PHYUTMI_OTGDISABLE
[PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. Signed-off-by: Vivek Gautam --- .../devicetree/bindings/phy/samsung-phy.txt| 20 + drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5-usb3.c | 562 4 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-exynos5-usb3.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index c0fccaa..9b5c111 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -20,3 +20,23 @@ Required properties: - compatible : should be "samsung,exynos5250-dp-video-phy"; - reg : offset and length of the Display Port PHY register set; - #phy-cells : from the generic PHY bindings, must be 0; + +Samsung Exynos5 SoC seiries USB 3.0 PHY controller +-- + +Required properties: +- compatible : + should be "samsung,exynos5250-usb3phy" for exynos5250 SoC + should be "samsung,exynos5420-usb3phy" for exynos5420 SoC +- reg : Register offset and length array + - first field corresponds to USB 3.0 PHY register set; + - second field corresponds to PHY power isolation register + present in PMU; +- clocks: Clock IDs array as required by the controller +- clock-names: names of clocks correseponding to IDs in the clock property; + Required clocks: + - first clock is main PHY clock (same as USB 3.0 controller IP clock) + - second clock is reference clock (usually crystal clock) + optional clock: + - third clock is special clock used by PHY for operation +- #phy-cells : from the generic PHY bindings, must be 0; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a344f3d..9a100c6 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO help Support for Display Port PHY found on Samsung EXYNOS SoCs. +config PHY_EXYNOS5_USB3 + tristate "Exynos5 SoC series USB 3.0 PHY driver" + depends on ARCH_EXYNOS5 + select GENERIC_PHY + help + Enable USB 3.0 PHY support for Exynos 5 SoC series + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d0caae9..9c06a61 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_EXYNOS5_USB3) += phy-exynos5-usb3.o diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c new file mode 100644 index 000..b9a2674 --- /dev/null +++ b/drivers/phy/phy-exynos5-usb3.c @@ -0,0 +1,562 @@ +/* + * Samsung EXYNOS5 SoC series USB 3.0 PHY driver + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Vivek Gautam + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Exynos USB PHY registers */ +#define EXYNOS5_FSEL_9MHZ6 0x0 +#define EXYNOS5_FSEL_10MHZ 0x1 +#define EXYNOS5_FSEL_12MHZ 0x2 +#define EXYNOS5_FSEL_19MHZ20x3 +#define EXYNOS5_FSEL_20MHZ 0x4 +#define EXYNOS5_FSEL_24MHZ 0x5 +#define EXYNOS5_FSEL_50MHZ 0x7 + +/* EXYNOS5: USB 3.0 DRD PHY registers */ +#define EXYNOS5_DRD_LINKSYSTEM (0x04) + +#define LINKSYSTEM_FLADJ_MASK (0x3f << 1) +#define LINKSYSTEM_FLADJ(_x) ((_x) << 1) +#define LINKSYSTEM_XHCI_VERSION_CONTROL(0x1 << 27) + +#define EXYNOS5_DRD_PHYUTMI(0x08) + +#define PHYUTMI_OTGDISABLE (0x1 << 6) +#define PHYUTMI_FORCESUSPEND (0x1 << 1) +#define PHYUTMI_FORCESLEEP (0x1 << 0) + +#define EXYNOS5_DRD_PHYPIPE(0x0c) + +#define EXYNOS5_DRD_PHYCLKRST (0x10) + +#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) +#define PHYCLKRST_SSC_REFCLKSEL(_x)((_x) << 23) + +#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) +#define PHYCLKRST_SSC_RANGE(_x)((_x) << 21) + +#define PHYCLKRST_SSC_EN (0x1 << 20) +#define PHYCLKRST_REF_SSP_EN (0x1 << 19) +#define
[PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/phy/samsung-phy.txt| 20 + drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5-usb3.c | 562 4 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-exynos5-usb3.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index c0fccaa..9b5c111 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -20,3 +20,23 @@ Required properties: - compatible : should be samsung,exynos5250-dp-video-phy; - reg : offset and length of the Display Port PHY register set; - #phy-cells : from the generic PHY bindings, must be 0; + +Samsung Exynos5 SoC seiries USB 3.0 PHY controller +-- + +Required properties: +- compatible : + should be samsung,exynos5250-usb3phy for exynos5250 SoC + should be samsung,exynos5420-usb3phy for exynos5420 SoC +- reg : Register offset and length array + - first field corresponds to USB 3.0 PHY register set; + - second field corresponds to PHY power isolation register + present in PMU; +- clocks: Clock IDs array as required by the controller +- clock-names: names of clocks correseponding to IDs in the clock property; + Required clocks: + - first clock is main PHY clock (same as USB 3.0 controller IP clock) + - second clock is reference clock (usually crystal clock) + optional clock: + - third clock is special clock used by PHY for operation +- #phy-cells : from the generic PHY bindings, must be 0; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a344f3d..9a100c6 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO help Support for Display Port PHY found on Samsung EXYNOS SoCs. +config PHY_EXYNOS5_USB3 + tristate Exynos5 SoC series USB 3.0 PHY driver + depends on ARCH_EXYNOS5 + select GENERIC_PHY + help + Enable USB 3.0 PHY support for Exynos 5 SoC series + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d0caae9..9c06a61 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_EXYNOS5_USB3) += phy-exynos5-usb3.o diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c new file mode 100644 index 000..b9a2674 --- /dev/null +++ b/drivers/phy/phy-exynos5-usb3.c @@ -0,0 +1,562 @@ +/* + * Samsung EXYNOS5 SoC series USB 3.0 PHY driver + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Vivek Gautam gautam.vi...@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/delay.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/of_address.h +#include linux/phy/phy.h +#include linux/platform_device.h +#include linux/mutex.h + +/* Exynos USB PHY registers */ +#define EXYNOS5_FSEL_9MHZ6 0x0 +#define EXYNOS5_FSEL_10MHZ 0x1 +#define EXYNOS5_FSEL_12MHZ 0x2 +#define EXYNOS5_FSEL_19MHZ20x3 +#define EXYNOS5_FSEL_20MHZ 0x4 +#define EXYNOS5_FSEL_24MHZ 0x5 +#define EXYNOS5_FSEL_50MHZ 0x7 + +/* EXYNOS5: USB 3.0 DRD PHY registers */ +#define EXYNOS5_DRD_LINKSYSTEM (0x04) + +#define LINKSYSTEM_FLADJ_MASK (0x3f 1) +#define LINKSYSTEM_FLADJ(_x) ((_x) 1) +#define LINKSYSTEM_XHCI_VERSION_CONTROL(0x1 27) + +#define EXYNOS5_DRD_PHYUTMI(0x08) + +#define PHYUTMI_OTGDISABLE (0x1 6) +#define PHYUTMI_FORCESUSPEND (0x1 1) +#define PHYUTMI_FORCESLEEP (0x1 0) + +#define EXYNOS5_DRD_PHYPIPE(0x0c) + +#define EXYNOS5_DRD_PHYCLKRST (0x10) + +#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff 23) +#define PHYCLKRST_SSC_REFCLKSEL(_x)((_x) 23) + +#define PHYCLKRST_SSC_RANGE_MASK (0x03 21) +#define PHYCLKRST_SSC_RANGE(_x)
