Re: [PATCH V7 3/4] arm64: dts: freescale: imx8qxp: enable scu general irq channel

[Shawn Guo]

On Tue, Apr 09, 2019 at 05:00:01AM +, Anson Huang wrote:
> On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify
> user for IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox
> RX doorbell mode is used for this function, this patch adds
> support for it.
> 
> Signed-off-by: Anson Huang 
> Reviewed-by: Dong Aisheng 

Prefix 'arm64: dts: imx8qxp:' would be good enough, and no need for
'freescale' in there.

I fixed it up and applied the patch.

Shawn

[PATCH V7 3/4] arm64: dts: freescale: imx8qxp: enable scu general irq channel

[Anson Huang]

On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify
user for IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox
RX doorbell mode is used for this function, this patch adds
support for it.

Signed-off-by: Anson Huang 
Reviewed-by: Dong Aisheng 
---
No changes.
---
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi 
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 0cb9398..70ef3db 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -21,6 +21,7 @@
mmc1 = 
mmc2 = 
serial0 = _lpuart0;
+   mu1 = _mu1;
};
 
cpus {
@@ -117,7 +118,8 @@
scu {
compatible = "fsl,imx-scu";
mbox-names = "tx0", "tx1", "tx2", "tx3",
-"rx0", "rx1", "rx2", "rx3";
+"rx0", "rx1", "rx2", "rx3",
+"gip3";
mboxes = <_mu1 0 0
  _mu1 0 1
  _mu1 0 2
@@ -125,7 +127,8 @@
  _mu1 1 0
  _mu1 1 1
  _mu1 1 2
- _mu1 1 3>;
+ _mu1 1 3
+ _mu1 3 3>;
 
clk: clock-controller {
compatible = "fsl,imx8qxp-clk";
-- 
2.7.4