Re: [PATCH v1 1/2] arm64: dts: qcom: sc7280: Add cpufreq hw node

[Matthias Kaehlcke]

On Sat, Apr 10, 2021 at 07:34:39AM +0530, Taniya Das wrote:
> Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+
> cores on SC7280 SoCs.
> 
> Signed-off-by: Taniya Das 

Reviewed-by: Matthias Kaehlcke 

Re: [PATCH v1 1/2] arm64: dts: qcom: sc7280: Add cpufreq hw node

[Stephen Boyd]

Quoting Taniya Das (2021-04-09 19:04:39)
> @@ -1116,6 +1124,17 @@
> #clock-cells = <1>;
> };
> };
> +
> +   cpufreq_hw: cpufreq@18591000 {
> +   compatible = "qcom,cpufreq-epss";
> +   reg = <0 0x18591000 0 0x1000>,
> + <0 0x18592000 0 0x1000>,
> + <0 0x18593000 0 0x1000>;
> +   reg-names = "freq-domain0", "freq-domain1", 
> "freq-domain2";

The reg-names provides practically no value. Can you drop it?

> +   clocks = < RPMH_CXO_CLK>, < GCC_GPLL0>;
> +   clock-names = "xo", "alternate";
> +   #freq-domain-cells = <1>;
> +   };
> };
>

[PATCH v1 1/2] arm64: dts: qcom: sc7280: Add cpufreq hw node

[Taniya Das]

Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+
cores on SC7280 SoCs.

Signed-off-by: Taniya Das 
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2cc4785..cda3f2a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -70,6 +70,7 @@
   _CPU_SLEEP_1
   _SLEEP_0>;
next-level-cache = <_0>;
+   qcom,freq-domain = <_hw 0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <_0>;
@@ -88,6 +89,7 @@
   _CPU_SLEEP_1
   _SLEEP_0>;
next-level-cache = <_100>;
+   qcom,freq-domain = <_hw 0>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <_0>;
@@ -103,6 +105,7 @@
   _CPU_SLEEP_1
   _SLEEP_0>;
next-level-cache = <_200>;
+   qcom,freq-domain = <_hw 0>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <_0>;
@@ -118,6 +121,7 @@
   _CPU_SLEEP_1
   _SLEEP_0>;
next-level-cache = <_300>;
+   qcom,freq-domain = <_hw 0>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <_0>;
@@ -133,6 +137,7 @@
   _CPU_SLEEP_1
   _SLEEP_0>;
next-level-cache = <_400>;
+   qcom,freq-domain = <_hw 1>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <_0>;
@@ -148,6 +153,7 @@
   _CPU_SLEEP_1
   _SLEEP_0>;
next-level-cache = <_500>;
+   qcom,freq-domain = <_hw 1>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <_0>;
@@ -163,6 +169,7 @@
   _CPU_SLEEP_1
   _SLEEP_0>;
next-level-cache = <_600>;
+   qcom,freq-domain = <_hw 1>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <_0>;
@@ -178,6 +185,7 @@
   _CPU_SLEEP_1
   _SLEEP_0>;
next-level-cache = <_700>;
+   qcom,freq-domain = <_hw 2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <_0>;
@@ -1116,6 +1124,17 @@
#clock-cells = <1>;
};
};
+
+   cpufreq_hw: cpufreq@18591000 {
+   compatible = "qcom,cpufreq-epss";
+   reg = <0 0x18591000 0 0x1000>,
+ <0 0x18592000 0 0x1000>,
+ <0 0x18593000 0 0x1000>;
+   reg-names = "freq-domain0", "freq-domain1", 
"freq-domain2";
+   clocks = < RPMH_CXO_CLK>, < GCC_GPLL0>;
+   clock-names = "xo", "alternate";
+   #freq-domain-cells = <1>;
+   };
};

timer {
--
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