Re: [PATCH v1 1/4] dt-bindings: memory: Add binding for MediaTek Common DRAM Controller
Hello Rob,
Thanks for the remind about dt_binding_check fail and the comments, my
reply is as follows and will fix it in the next version (v2).
Po-Kai
On Tue, 2021-03-30 at 21:58 +0800, Rob Herring wrote:
> On Tue, Mar 30, 2021 at 01:22:08PM +0800, Po-Kai Chi wrote:
> > This patch adds the documentation of the device-tree binding for
> > MediaTek Common DRAM Controller.
> >
> > Signed-off-by: Po-Kai Chi
> > ---
> > .../memory-controllers/mediatek,dramc.yaml | 155
> >
> > 1 file changed, 155 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
> > b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
> > new file mode 100644
> > index 000..0217ce0
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
> > @@ -0,0 +1,155 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2021 MediaTek Inc.
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/memory-controllers/mediatek,dramc.yaml*__;Iw!!CTRNKA9wMg0ARbw!y9zM5d-aNLK99Y_ag2yvqq3TI1Xvm6TV_Vu03VVD3Qbe69N1qZXFFk2DUFb6CG0$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!y9zM5d-aNLK99Y_ag2yvqq3TI1Xvm6TV_Vu03VVD3Qbe69N1qZXFFk2DiMad89A$
> >
> > +
> > +title: MediaTek DRAM Controller
> > +
> > +maintainers:
> > + - Po-Kai Chi
> > +
> > +description: |
> > + MediaTek DRAM controller (DRAMC) provides an interface to query
> > information
> > + about DRAM which collected from bootloader and device tree.
> > + This is mainly used by MediaTek Extended Memory Interface (EMI) and DVFS
> > Resource
> > + Control (DVFSRC).
> > +
> > +properties:
> > + compatible:
> > +items:
> > + - enum:
> > + - mediatek,mt6779-dramc
> > +
> > + reg:
> > +description:
> > + Base address of MediaTek DRAM related hardware modules, each channel
> > has
> > + its own base address in order of
> > + DRAMC_AO_{CH}, DRAMC_NAO_{CH}, DDRPHY_AO_{CH}.
> > +minItems: 3# 3 * N channels
> > +maxItems: 6
> > +
> > + dram_type:
>
> These need to be either common or have a vendor prefix.
>
> Also, s/_/-/
Okay, I have revised the naming rule according to writing-schema.rst.
> > +description:
> > + The DRAM type of current DRAM chip.
> > + This property is filled in by bootloader according to the board
> > hardware
> > + configuration.
> > +$ref: /schemas/types.yaml#/definitions/uint32
> > +minimum: 0
> > +maximum: 7
> > +
> > + support_channel_cnt:
> > +description:
> > + The maximum DRAM channel count supported by SoC.
> > +$ref: /schemas/types.yaml#/definitions/uint32
> > +minimum: 1
> > +maximum: 4
> > +
> > + channel_cnt:
> > +description:
> > + The DRAM channel count of current DRAM chip.
> > + This property is filled in by bootloader according to the board
> > hardware
> > + configuration.
> > +$ref: /schemas/types.yaml#/definitions/uint32
> > +minimum: 1
> > +maximum: 4
> > +
> > + rank_cnt:
> > +description:
> > + The DRAM rank count of current DRAM chip.
> > + This property is filled in by bootloader according to the board
> > hardware
> > + configuration.
> > +$ref: /schemas/types.yaml#/definitions/uint32
> > +minimum: 1
> > +maximum: 2
> > +
> > + rank_size:
> > +description:
> > + The size of each DRAM rank.
> > + This property is filled in by bootloader according to the board
> > hardware
> > + configuration.
> > +$ref: /schemas/types.yaml#/definitions/uint64
There may be some misunderstanding.
rank_size uses the full 64 bits to describe the size of each DRAM rank.
So the type of rank_size should be uint64-array, instead of uint64.
> > +minItems: 1
> > +maxItems: 2
> > +items:
> > + minimum: 0x0
> > + maximum: 0x1# support up to 4GB in single rank
> > +
> > + mr_cnt:
> > +description:
> > + Specifies how many sets of DRAM mode register information to provide.
> > + This property is filled in by bootloader according to the board
> > hardware
> > + configuration.
> > +$ref: /schemas/types.yaml#/definitions/uint32
> > +maximum: 40# total 40 MRs for JEDEC LPDDR4X
> > +
> > + mr:
> > +description:
> > + Pair of DRAM mode register information.
> > + This property is filled in by bootloader according to the board
> > hardware
> > + configuration.
> > +$ref: /schemas/types.yaml#/definitions/uint32-matrix
> > +maxItems: 40# align with mr_cnt
> > +items:
> > + items:
> > +- description:
> > +Mode register index
> > +- description:
>
Re: [PATCH v1 1/4] dt-bindings: memory: Add binding for MediaTek Common DRAM Controller
On Tue, Mar 30, 2021 at 01:22:08PM +0800, Po-Kai Chi wrote:
> This patch adds the documentation of the device-tree binding for
> MediaTek Common DRAM Controller.
>
> Signed-off-by: Po-Kai Chi
> ---
> .../memory-controllers/mediatek,dramc.yaml | 155
>
> 1 file changed, 155 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
> b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
> new file mode 100644
> index 000..0217ce0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
> @@ -0,0 +1,155 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2021 MediaTek Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/memory-controllers/mediatek,dramc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek DRAM Controller
> +
> +maintainers:
> + - Po-Kai Chi
> +
> +description: |
> + MediaTek DRAM controller (DRAMC) provides an interface to query information
> + about DRAM which collected from bootloader and device tree.
> + This is mainly used by MediaTek Extended Memory Interface (EMI) and DVFS
> Resource
> + Control (DVFSRC).
> +
> +properties:
> + compatible:
> +items:
> + - enum:
> + - mediatek,mt6779-dramc
> +
> + reg:
> +description:
> + Base address of MediaTek DRAM related hardware modules, each channel
> has
> + its own base address in order of
> + DRAMC_AO_{CH}, DRAMC_NAO_{CH}, DDRPHY_AO_{CH}.
> +minItems: 3# 3 * N channels
> +maxItems: 6
> +
> + dram_type:
These need to be either common or have a vendor prefix.
Also, s/_/-/
> +description:
> + The DRAM type of current DRAM chip.
> + This property is filled in by bootloader according to the board
> hardware
> + configuration.
> +$ref: /schemas/types.yaml#/definitions/uint32
> +minimum: 0
> +maximum: 7
> +
> + support_channel_cnt:
> +description:
> + The maximum DRAM channel count supported by SoC.
> +$ref: /schemas/types.yaml#/definitions/uint32
> +minimum: 1
> +maximum: 4
> +
> + channel_cnt:
> +description:
> + The DRAM channel count of current DRAM chip.
> + This property is filled in by bootloader according to the board
> hardware
> + configuration.
> +$ref: /schemas/types.yaml#/definitions/uint32
> +minimum: 1
> +maximum: 4
> +
> + rank_cnt:
> +description:
> + The DRAM rank count of current DRAM chip.
> + This property is filled in by bootloader according to the board
> hardware
> + configuration.
> +$ref: /schemas/types.yaml#/definitions/uint32
> +minimum: 1
> +maximum: 2
> +
> + rank_size:
> +description:
> + The size of each DRAM rank.
> + This property is filled in by bootloader according to the board
> hardware
> + configuration.
> +$ref: /schemas/types.yaml#/definitions/uint64
> +minItems: 1
> +maxItems: 2
> +items:
> + minimum: 0x0
> + maximum: 0x1# support up to 4GB in single rank
> +
> + mr_cnt:
> +description:
> + Specifies how many sets of DRAM mode register information to provide.
> + This property is filled in by bootloader according to the board
> hardware
> + configuration.
> +$ref: /schemas/types.yaml#/definitions/uint32
> +maximum: 40# total 40 MRs for JEDEC LPDDR4X
> +
> + mr:
> +description:
> + Pair of DRAM mode register information.
> + This property is filled in by bootloader according to the board
> hardware
> + configuration.
> +$ref: /schemas/types.yaml#/definitions/uint32-matrix
> +maxItems: 40# align with mr_cnt
> +items:
> + items:
> +- description:
> +Mode register index
> +- description:
> +Mode register value
> +
> + freq_cnt:
> +description:
> + Specifies how many sets of DRAM data clock rate supported by SoC.
> +$ref: /schemas/types.yaml#/definitions/uint32
> +
> + freq_step:
> +description:
> + The DRAM data clock rate may be slightly different from those defined
> + by the specification due to errors in multiples of the base frequency.
> + This describe the mapping from real data clock rate measured by
> + frequency meter to JEDEC data clock rate.
> +$ref: /schemas/types.yaml#/definitions/uint32-matrix
> +items:
> + items:
> +- description:
> +Real data rate
> +- description:
> +Spec data rate
Looks like an OPP table.
> +
> +required:
> + - compatible
> + - reg
> + - dram_type
> + - support_channel_cnt
> + - channel_cnt
> + - rank_cnt
> + - mr_cnt
> + - freq_cnt
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
Re: [PATCH v1 1/4] dt-bindings: memory: Add binding for MediaTek Common DRAM Controller
On Tue, 30 Mar 2021 13:22:08 +0800, Po-Kai Chi wrote: > This patch adds the documentation of the device-tree binding for > MediaTek Common DRAM Controller. > > Signed-off-by: Po-Kai Chi > --- > .../memory-controllers/mediatek,dramc.yaml | 155 > > 1 file changed, 155 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Error: Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.example.dts:43.3-44.1 syntax error FATAL ERROR: Unable to parse input tree make[1]: *** [scripts/Makefile.lib:377: Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs make: *** [Makefile:1414: dt_binding_check] Error 2 See https://patchwork.ozlabs.org/patch/1459879 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
[PATCH v1 1/4] dt-bindings: memory: Add binding for MediaTek Common DRAM Controller
This patch adds the documentation of the device-tree binding for
MediaTek Common DRAM Controller.
Signed-off-by: Po-Kai Chi
---
.../memory-controllers/mediatek,dramc.yaml | 155
1 file changed, 155 insertions(+)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
diff --git
a/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
new file mode 100644
index 000..0217ce0
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2021 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/mediatek,dramc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek DRAM Controller
+
+maintainers:
+ - Po-Kai Chi
+
+description: |
+ MediaTek DRAM controller (DRAMC) provides an interface to query information
+ about DRAM which collected from bootloader and device tree.
+ This is mainly used by MediaTek Extended Memory Interface (EMI) and DVFS
Resource
+ Control (DVFSRC).
+
+properties:
+ compatible:
+items:
+ - enum:
+ - mediatek,mt6779-dramc
+
+ reg:
+description:
+ Base address of MediaTek DRAM related hardware modules, each channel has
+ its own base address in order of
+ DRAMC_AO_{CH}, DRAMC_NAO_{CH}, DDRPHY_AO_{CH}.
+minItems: 3# 3 * N channels
+maxItems: 6
+
+ dram_type:
+description:
+ The DRAM type of current DRAM chip.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 0
+maximum: 7
+
+ support_channel_cnt:
+description:
+ The maximum DRAM channel count supported by SoC.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 4
+
+ channel_cnt:
+description:
+ The DRAM channel count of current DRAM chip.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 4
+
+ rank_cnt:
+description:
+ The DRAM rank count of current DRAM chip.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 2
+
+ rank_size:
+description:
+ The size of each DRAM rank.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint64
+minItems: 1
+maxItems: 2
+items:
+ minimum: 0x0
+ maximum: 0x1# support up to 4GB in single rank
+
+ mr_cnt:
+description:
+ Specifies how many sets of DRAM mode register information to provide.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32
+maximum: 40# total 40 MRs for JEDEC LPDDR4X
+
+ mr:
+description:
+ Pair of DRAM mode register information.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32-matrix
+maxItems: 40# align with mr_cnt
+items:
+ items:
+- description:
+Mode register index
+- description:
+Mode register value
+
+ freq_cnt:
+description:
+ Specifies how many sets of DRAM data clock rate supported by SoC.
+$ref: /schemas/types.yaml#/definitions/uint32
+
+ freq_step:
+description:
+ The DRAM data clock rate may be slightly different from those defined
+ by the specification due to errors in multiples of the base frequency.
+ This describe the mapping from real data clock rate measured by
+ frequency meter to JEDEC data clock rate.
+$ref: /schemas/types.yaml#/definitions/uint32-matrix
+items:
+ items:
+- description:
+Real data rate
+- description:
+Spec data rate
+
+required:
+ - compatible
+ - reg
+ - dram_type
+ - support_channel_cnt
+ - channel_cnt
+ - rank_cnt
+ - mr_cnt
+ - freq_cnt
+
+additionalProperties: false
+
+examples:
+ - |
+dramc@1023 {
+compatible = "mediatek,mt6779-dramc";
+reg = <0 0x1023 0 0x2000>, /* DRAMC AO CHA */
+<0 0x1024 0 0x2000>, /* DRAMC AO CHB */
+<0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */
+<0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */
+<0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */
+<0 0x10248000 0 0x2000>; /* DDRPHY AO CHB */
+dram_type = <0>;
+support_channel_cnt = <2>;
+
