subject:"\[PATCH v3\] PCI\: al\: Add Amazon Annapurna Labs PCIe host controller driver"

Re: [PATCH v3] PCI: al: Add Amazon Annapurna Labs PCIe host controller driver

2019-04-25 Thread Bjorn Helgaas

On Thu, Mar 28, 2019 at 01:57:56PM +0200, Jonathan Chocron wrote:
> Add support for Amazon's Annapurna Labs PCIe driver. The HW controller
> is based on DesignWare's IP.
> 
> The HW doesn't support accessing the Root Port's config space via ECAM,
> so we obtain its base address via an AMZN0001 device.
> 
> Furthermore, the DesignWare PCIe controller doesn't filter out config
> transactions sent to devices 1 and up on its bus, so they are filtered
> by the driver.
> 
> All subordinate buses do support ECAM access.
> 
> Implementing specific PCI config access functions involves:
>  - Adding an init function to obtain the Root Port's base address from
>an AMZN0001 device.
>  - Adding a new entry in the MCFG quirk array
> 
> Co-developed-by: Vladimir Aerov 
> Signed-off-by: Jonathan Chocron 
> Signed-off-by: Vladimir Aerov 
> Reviewed-by: David Woodhouse 

Applied with Ben's reviewed-by and Lorenzo's ack to pci/host/al for v5.2,
thanks!

> ---
> 
> --v2:
>   - Fix commit message comments (incl. using AMZN0001 instead of
> PNP0C02)
>   - Use the usual multi-line comment style
> 
> --v3:
>   - Fix additional commit message comments
> 
>  MAINTAINERS  |  6 +++
>  drivers/acpi/pci_mcfg.c  | 12 +
>  drivers/pci/controller/dwc/Makefile  |  1 +
>  drivers/pci/controller/dwc/pcie-al.c | 93 
> 
>  include/linux/pci-ecam.h |  1 +
>  5 files changed, 113 insertions(+)
>  create mode 100644 drivers/pci/controller/dwc/pcie-al.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 32d76a90..7a17017f9f82 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11769,6 +11769,12 @@ T:   git 
> git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/
>  S:   Supported
>  F:   drivers/pci/controller/
>  
> +PCIE DRIVER FOR ANNAPURNA LABS
> +M:   Jonathan Chocron 
> +L:   linux-...@vger.kernel.org
> +S:   Maintained
> +F:   drivers/pci/controller/dwc/pcie-al.c
> +
>  PCIE DRIVER FOR AMLOGIC MESON
>  M:   Yue Wang 
>  L:   linux-...@vger.kernel.org
> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
> index a4e8432fc2fb..b42be067fb83 100644
> --- a/drivers/acpi/pci_mcfg.c
> +++ b/drivers/acpi/pci_mcfg.c
> @@ -52,6 +52,18 @@ struct mcfg_fixup {
>  static struct mcfg_fixup mcfg_quirks[] = {
>  /*   { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
>  
> +#define AL_ECAM(table_id, rev, seg, ops) \
> + { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
> +
> + AL_ECAM("GRAVITON", 0, 0, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 1, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 2, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 3, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 4, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 5, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 6, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 7, _pcie_ops),
> +
>  #define QCOM_ECAM32(seg) \
>   { "QCOM  ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, _32b_ops }
>  
> diff --git a/drivers/pci/controller/dwc/Makefile 
> b/drivers/pci/controller/dwc/Makefile
> index 7bcdcdf5024e..1ea773c0070d 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -28,5 +28,6 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
>  # depending on whether ACPI, the DT driver, or both are enabled.
>  
>  ifdef CONFIG_PCI
> +obj-$(CONFIG_ARM64) += pcie-al.o
>  obj-$(CONFIG_ARM64) += pcie-hisi.o
>  endif
> diff --git a/drivers/pci/controller/dwc/pcie-al.c 
> b/drivers/pci/controller/dwc/pcie-al.c
> new file mode 100644
> index ..65a9776c12be
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-al.c
> @@ -0,0 +1,93 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
> + * such as Graviton and Alpine)
> + *
> + * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
> + *
> + * Author: Jonathan Chocron 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include "../../pci.h"
> +
> +#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
> +
> +struct al_pcie_acpi  {
> + void __iomem *dbi_base;
> +};
> +
> +static void __iomem *al_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
> +  int where)
> +{
> + struct pci_config_window *cfg = bus->sysdata;
> + struct al_pcie_acpi *pcie = cfg->priv;
> + void __iomem *dbi_base = pcie->dbi_base;
> +
> + if (bus->number == cfg->busr.start) {
> + /*
> +  * The DW PCIe core doesn't filter out transactions to other
> +  * devices/functions on the primary bus num, so we do this here.
> +  */
> + if (PCI_SLOT(devfn) > 0)
> + return NULL;
> + else
> + return dbi_base + where;
> + }
> +
> + return pci_ecam_map_bus(bus, devfn, where);
> +}
> +
> +static int al_pcie_init(struct pci_config_window *cfg)
> +{
> +

Re: [PATCH v3] PCI: al: Add Amazon Annapurna Labs PCIe host controller driver

2019-04-16 Thread Lorenzo Pieralisi

On Thu, Mar 28, 2019 at 01:57:56PM +0200, Jonathan Chocron wrote:
> Add support for Amazon's Annapurna Labs PCIe driver. The HW controller
> is based on DesignWare's IP.
> 
> The HW doesn't support accessing the Root Port's config space via ECAM,
> so we obtain its base address via an AMZN0001 device.
> 
> Furthermore, the DesignWare PCIe controller doesn't filter out config
> transactions sent to devices 1 and up on its bus, so they are filtered
> by the driver.
> 
> All subordinate buses do support ECAM access.
> 
> Implementing specific PCI config access functions involves:
>  - Adding an init function to obtain the Root Port's base address from
>an AMZN0001 device.
>  - Adding a new entry in the MCFG quirk array
> 
> Co-developed-by: Vladimir Aerov 
> Signed-off-by: Jonathan Chocron 
> Signed-off-by: Vladimir Aerov 
> Reviewed-by: David Woodhouse 
> ---
> 
> --v2:
>   - Fix commit message comments (incl. using AMZN0001 instead of
> PNP0C02)
>   - Use the usual multi-line comment style
> 
> --v3:
>   - Fix additional commit message comments
> 
>  MAINTAINERS  |  6 +++
>  drivers/acpi/pci_mcfg.c  | 12 +
>  drivers/pci/controller/dwc/Makefile  |  1 +
>  drivers/pci/controller/dwc/pcie-al.c | 93 
> 
>  include/linux/pci-ecam.h |  1 +
>  5 files changed, 113 insertions(+)
>  create mode 100644 drivers/pci/controller/dwc/pcie-al.c

I think Bjorn can take this if he is OK with it, it is not really
necessary to queue it via the controller/dwc tree so:

Acked-by: Lorenzo Pieralisi 

> diff --git a/MAINTAINERS b/MAINTAINERS
> index 32d76a90..7a17017f9f82 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11769,6 +11769,12 @@ T:   git 
> git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/
>  S:   Supported
>  F:   drivers/pci/controller/
>  
> +PCIE DRIVER FOR ANNAPURNA LABS
> +M:   Jonathan Chocron 
> +L:   linux-...@vger.kernel.org
> +S:   Maintained
> +F:   drivers/pci/controller/dwc/pcie-al.c
> +
>  PCIE DRIVER FOR AMLOGIC MESON
>  M:   Yue Wang 
>  L:   linux-...@vger.kernel.org
> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
> index a4e8432fc2fb..b42be067fb83 100644
> --- a/drivers/acpi/pci_mcfg.c
> +++ b/drivers/acpi/pci_mcfg.c
> @@ -52,6 +52,18 @@ struct mcfg_fixup {
>  static struct mcfg_fixup mcfg_quirks[] = {
>  /*   { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
>  
> +#define AL_ECAM(table_id, rev, seg, ops) \
> + { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
> +
> + AL_ECAM("GRAVITON", 0, 0, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 1, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 2, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 3, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 4, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 5, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 6, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 7, _pcie_ops),
> +
>  #define QCOM_ECAM32(seg) \
>   { "QCOM  ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, _32b_ops }
>  
> diff --git a/drivers/pci/controller/dwc/Makefile 
> b/drivers/pci/controller/dwc/Makefile
> index 7bcdcdf5024e..1ea773c0070d 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -28,5 +28,6 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
>  # depending on whether ACPI, the DT driver, or both are enabled.
>  
>  ifdef CONFIG_PCI
> +obj-$(CONFIG_ARM64) += pcie-al.o
>  obj-$(CONFIG_ARM64) += pcie-hisi.o
>  endif
> diff --git a/drivers/pci/controller/dwc/pcie-al.c 
> b/drivers/pci/controller/dwc/pcie-al.c
> new file mode 100644
> index ..65a9776c12be
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-al.c
> @@ -0,0 +1,93 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
> + * such as Graviton and Alpine)
> + *
> + * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
> + *
> + * Author: Jonathan Chocron 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include "../../pci.h"
> +
> +#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
> +
> +struct al_pcie_acpi  {
> + void __iomem *dbi_base;
> +};
> +
> +static void __iomem *al_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
> +  int where)
> +{
> + struct pci_config_window *cfg = bus->sysdata;
> + struct al_pcie_acpi *pcie = cfg->priv;
> + void __iomem *dbi_base = pcie->dbi_base;
> +
> + if (bus->number == cfg->busr.start) {
> + /*
> +  * The DW PCIe core doesn't filter out transactions to other
> +  * devices/functions on the primary bus num, so we do this here.
> +  */
> + if (PCI_SLOT(devfn) > 0)
> + return NULL;
> + else
> + return dbi_base + where;
> + }
> +
> + return pci_ecam_map_bus(bus, devfn, where);
> +}
> +
> +static

Re: [PATCH v3] PCI: al: Add Amazon Annapurna Labs PCIe host controller driver

2019-04-16 Thread David Woodhouse

On Tue, 2019-04-09 at 08:57 +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2019-03-28 at 13:57 +0200, Jonathan Chocron wrote:
> > Add support for Amazon's Annapurna Labs PCIe driver. The HW
> > controller
> > is based on DesignWare's IP.
> > 
> > The HW doesn't support accessing the Root Port's config space via
> > ECAM,
> > so we obtain its base address via an AMZN0001 device.
> > 
> > Furthermore, the DesignWare PCIe controller doesn't filter out
> > config
> > transactions sent to devices 1 and up on its bus, so they are
> > filtered
> > by the driver.
> > 
> > All subordinate buses do support ECAM access.
> > 
> > Implementing specific PCI config access functions involves:
> >   - Adding an init function to obtain the Root Port's base address
> > from
> > an AMZN0001 device.
> >   - Adding a new entry in the MCFG quirk array
> > 
> > Co-developed-by: Vladimir Aerov 
> > Signed-off-by: Jonathan Chocron 
> > Signed-off-by: Vladimir Aerov 
> > Reviewed-by: David Woodhouse 
> 
> Late to the party, sorry :-) That kernel.crashing.org email is on its
> last legs...
> 
> Reviewed-by: Benjamin Herrenschmidt 

Lorenzo, is there anything else you need from Jonny before this can be
applied?

Thanks.



smime.p7s
Description: S/MIME cryptographic signature

Re: [PATCH v3] PCI: al: Add Amazon Annapurna Labs PCIe host controller driver

2019-04-08 Thread Benjamin Herrenschmidt

On Thu, 2019-03-28 at 13:57 +0200, Jonathan Chocron wrote:
> Add support for Amazon's Annapurna Labs PCIe driver. The HW
> controller
> is based on DesignWare's IP.
> 
> The HW doesn't support accessing the Root Port's config space via
> ECAM,
> so we obtain its base address via an AMZN0001 device.
> 
> Furthermore, the DesignWare PCIe controller doesn't filter out config
> transactions sent to devices 1 and up on its bus, so they are
> filtered
> by the driver.
> 
> All subordinate buses do support ECAM access.
> 
> Implementing specific PCI config access functions involves:
>  - Adding an init function to obtain the Root Port's base address
> from
>an AMZN0001 device.
>  - Adding a new entry in the MCFG quirk array
> 
> Co-developed-by: Vladimir Aerov 
> Signed-off-by: Jonathan Chocron 
> Signed-off-by: Vladimir Aerov 
> Reviewed-by: David Woodhouse 

Late to the party, sorry :-) That kernel.crashing.org email is on its
last legs...

Reviewed-by: Benjamin Herrenschmidt 

> ---
> 
> --v2:
>   - Fix commit message comments (incl. using AMZN0001 instead of
> PNP0C02)
>   - Use the usual multi-line comment style
> 
> --v3:
>   - Fix additional commit message comments
> 
>  MAINTAINERS  |  6 +++
>  drivers/acpi/pci_mcfg.c  | 12 +
>  drivers/pci/controller/dwc/Makefile  |  1 +
>  drivers/pci/controller/dwc/pcie-al.c | 93
> 
>  include/linux/pci-ecam.h |  1 +
>  5 files changed, 113 insertions(+)
>  create mode 100644 drivers/pci/controller/dwc/pcie-al.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 32d76a90..7a17017f9f82 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11769,6 +11769,12 @@ T:   git
> git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/
>  S:   Supported
>  F:   drivers/pci/controller/
>  
> +PCIE DRIVER FOR ANNAPURNA LABS
> +M:   Jonathan Chocron 
> +L:   linux-...@vger.kernel.org
> +S:   Maintained
> +F:   drivers/pci/controller/dwc/pcie-al.c
> +
>  PCIE DRIVER FOR AMLOGIC MESON
>  M:   Yue Wang 
>  L:   linux-...@vger.kernel.org
> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
> index a4e8432fc2fb..b42be067fb83 100644
> --- a/drivers/acpi/pci_mcfg.c
> +++ b/drivers/acpi/pci_mcfg.c
> @@ -52,6 +52,18 @@ struct mcfg_fixup {
>  static struct mcfg_fixup mcfg_quirks[] = {
>  /*   { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres },
> */
>  
> +#define AL_ECAM(table_id, rev, seg, ops) \
> + { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
> +
> + AL_ECAM("GRAVITON", 0, 0, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 1, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 2, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 3, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 4, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 5, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 6, _pcie_ops),
> + AL_ECAM("GRAVITON", 0, 7, _pcie_ops),
> +
>  #define QCOM_ECAM32(seg) \
>   { "QCOM  ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, _32b_ops }
>  
> diff --git a/drivers/pci/controller/dwc/Makefile
> b/drivers/pci/controller/dwc/Makefile
> index 7bcdcdf5024e..1ea773c0070d 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -28,5 +28,6 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
>  # depending on whether ACPI, the DT driver, or both are enabled.
>  
>  ifdef CONFIG_PCI
> +obj-$(CONFIG_ARM64) += pcie-al.o
>  obj-$(CONFIG_ARM64) += pcie-hisi.o
>  endif
> diff --git a/drivers/pci/controller/dwc/pcie-al.c
> b/drivers/pci/controller/dwc/pcie-al.c
> new file mode 100644
> index ..65a9776c12be
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-al.c
> @@ -0,0 +1,93 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PCIe host controller driver for Amazon's Annapurna Labs IP (used
> in chips
> + * such as Graviton and Alpine)
> + *
> + * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights
> Reserved.
> + *
> + * Author: Jonathan Chocron 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include "../../pci.h"
> +
> +#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
> +
> +struct al_pcie_acpi  {
> + void __iomem *dbi_base;
> +};
> +
> +static void __iomem *al_pcie_map_bus(struct pci_bus *bus, unsigned
> int devfn,
> +  int where)
> +{
> + struct pci_config_window *cfg = bus->sysdata;
> + struct al_pcie_acpi *pcie = cfg->priv;
> + void __iomem *dbi_base = pcie->dbi_base;
> +
> + if (bus->number == cfg->busr.start) {
> + /*
> +  * The DW PCIe core doesn't filter out transactions to
> other
> +  * devices/functions on the primary bus num, so we do
> this here.
> +  */
> + if (PCI_SLOT(devfn) > 0)
> + return NULL;
> + else
> + return dbi_base + where;
> + }
> +
> + return pci_ecam_map_bus(bus, devfn, where);
> +}
> +
> +static int

[PATCH v3] PCI: al: Add Amazon Annapurna Labs PCIe host controller driver

2019-03-28 Thread Jonathan Chocron

Add support for Amazon's Annapurna Labs PCIe driver. The HW controller
is based on DesignWare's IP.

The HW doesn't support accessing the Root Port's config space via ECAM,
so we obtain its base address via an AMZN0001 device.

Furthermore, the DesignWare PCIe controller doesn't filter out config
transactions sent to devices 1 and up on its bus, so they are filtered
by the driver.

All subordinate buses do support ECAM access.

Implementing specific PCI config access functions involves:
 - Adding an init function to obtain the Root Port's base address from
   an AMZN0001 device.
 - Adding a new entry in the MCFG quirk array

Co-developed-by: Vladimir Aerov 
Signed-off-by: Jonathan Chocron 
Signed-off-by: Vladimir Aerov 
Reviewed-by: David Woodhouse 
---

--v2:
  - Fix commit message comments (incl. using AMZN0001 instead of
PNP0C02)
  - Use the usual multi-line comment style

--v3:
  - Fix additional commit message comments

 MAINTAINERS  |  6 +++
 drivers/acpi/pci_mcfg.c  | 12 +
 drivers/pci/controller/dwc/Makefile  |  1 +
 drivers/pci/controller/dwc/pcie-al.c | 93 
 include/linux/pci-ecam.h |  1 +
 5 files changed, 113 insertions(+)
 create mode 100644 drivers/pci/controller/dwc/pcie-al.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 32d76a90..7a17017f9f82 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11769,6 +11769,12 @@ T: git 
git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/
 S: Supported
 F: drivers/pci/controller/
 
+PCIE DRIVER FOR ANNAPURNA LABS
+M: Jonathan Chocron 
+L: linux-...@vger.kernel.org
+S: Maintained
+F: drivers/pci/controller/dwc/pcie-al.c
+
 PCIE DRIVER FOR AMLOGIC MESON
 M: Yue Wang 
 L: linux-...@vger.kernel.org
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index a4e8432fc2fb..b42be067fb83 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -52,6 +52,18 @@ struct mcfg_fixup {
 static struct mcfg_fixup mcfg_quirks[] = {
 /* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
 
+#define AL_ECAM(table_id, rev, seg, ops) \
+   { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
+
+   AL_ECAM("GRAVITON", 0, 0, _pcie_ops),
+   AL_ECAM("GRAVITON", 0, 1, _pcie_ops),
+   AL_ECAM("GRAVITON", 0, 2, _pcie_ops),
+   AL_ECAM("GRAVITON", 0, 3, _pcie_ops),
+   AL_ECAM("GRAVITON", 0, 4, _pcie_ops),
+   AL_ECAM("GRAVITON", 0, 5, _pcie_ops),
+   AL_ECAM("GRAVITON", 0, 6, _pcie_ops),
+   AL_ECAM("GRAVITON", 0, 7, _pcie_ops),
+
 #define QCOM_ECAM32(seg) \
{ "QCOM  ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, _32b_ops }
 
diff --git a/drivers/pci/controller/dwc/Makefile 
b/drivers/pci/controller/dwc/Makefile
index 7bcdcdf5024e..1ea773c0070d 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -28,5 +28,6 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
 # depending on whether ACPI, the DT driver, or both are enabled.
 
 ifdef CONFIG_PCI
+obj-$(CONFIG_ARM64) += pcie-al.o
 obj-$(CONFIG_ARM64) += pcie-hisi.o
 endif
diff --git a/drivers/pci/controller/dwc/pcie-al.c 
b/drivers/pci/controller/dwc/pcie-al.c
new file mode 100644
index ..65a9776c12be
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-al.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
+ * such as Graviton and Alpine)
+ *
+ * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Author: Jonathan Chocron 
+ */
+
+#include 
+#include 
+#include 
+#include "../../pci.h"
+
+#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
+
+struct al_pcie_acpi  {
+   void __iomem *dbi_base;
+};
+
+static void __iomem *al_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
+int where)
+{
+   struct pci_config_window *cfg = bus->sysdata;
+   struct al_pcie_acpi *pcie = cfg->priv;
+   void __iomem *dbi_base = pcie->dbi_base;
+
+   if (bus->number == cfg->busr.start) {
+   /*
+* The DW PCIe core doesn't filter out transactions to other
+* devices/functions on the primary bus num, so we do this here.
+*/
+   if (PCI_SLOT(devfn) > 0)
+   return NULL;
+   else
+   return dbi_base + where;
+   }
+
+   return pci_ecam_map_bus(bus, devfn, where);
+}
+
+static int al_pcie_init(struct pci_config_window *cfg)
+{
+   struct device *dev = cfg->parent;
+   struct acpi_device *adev = to_acpi_device(dev);
+   struct acpi_pci_root *root = acpi_driver_data(adev);
+   struct al_pcie_acpi *al_pcie;
+   struct resource *res;
+   int ret;
+
+   al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
+   if (!al_pcie)
+   return -ENOMEM;
+
+

Re: [PATCH v3] PCI: al: Add Amazon Annapurna Labs PCIe host controller driver

Re: [PATCH v3] PCI: al: Add Amazon Annapurna Labs PCIe host controller driver

Re: [PATCH v3] PCI: al: Add Amazon Annapurna Labs PCIe host controller driver

Re: [PATCH v3] PCI: al: Add Amazon Annapurna Labs PCIe host controller driver

[PATCH v3] PCI: al: Add Amazon Annapurna Labs PCIe host controller driver

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