Re: [PATCH v3 1/2] pwm: sunxi: Add Allwinner SoC PWM controller driver
Hi! On Mon, Mar 08, 2021 at 10:47:03AM +0800, 班涛 wrote: > Maxime Ripard 于2021年3月5日周五 上午12:07写道： > > > Hi, > > > > On Tue, Mar 02, 2021 at 08:37:37PM +0800, Ban Tao wrote: > > > From: Ban Tao > > > > > > The Allwinner R818, A133, R329, V536 and V833 has a new PWM controller > > > IP compared to the older Allwinner SoCs. > > > > > > Signed-off-by: Ban Tao > > > > Thanks for sending an update. > > > > Like I said in the previous version though, without proper SoC support > > upstream, that driver would effectively be dead code > > > > I'm not sure if the latest Linux code supports R818, A133, R329, V536 or > V833, It doesn't at the moment... > But the driver supports most of the sun50i family of SoCs and some of the > sun8i SoCs. > Maybe I shouldn't submit this code right now... ... but if that driver can drive controllers found on other SoCs that we support already, then you're very welcome to work on those first :) Maxime signature.asc Description: PGP signature
Re: [PATCH v3 1/2] pwm: sunxi: Add Allwinner SoC PWM controller driver
Hello, the Subject should mention sun8i-v536. On Tue, Mar 02, 2021 at 08:37:37PM +0800, Ban Tao wrote: > The Allwinner R818, A133, R329, V536 and V833 has a new PWM controller > IP compared to the older Allwinner SoCs. > > Signed-off-by: Ban Tao > > --- > v1->v2: > 1.delete unnecessary code. > 2.using a named define for some constants. > 3.Add comment in sun50i_pwm_config function. > 4.using dev_err_probe() for error handling. > 5.disable the clock after pwmchip_remove(). > --- > v2->v3: > 1.fix all emitted warnings when PWM_DEBUG enabled. > 2.modify the name of file pwm-sun50i to pwm-sun8i-v536. > 3.fix "sun50i_pwm_from_chip" -> "to_sun8i_pwm_chip". > 4.delete some unnecessary "compatible". > --- > MAINTAINERS | 6 + > drivers/pwm/Kconfig | 11 + > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-sun8i-v536.c | 401 +++ > 4 files changed, 419 insertions(+) > create mode 100644 drivers/pwm/pwm-sun8i-v536.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index e73636b75f29..387e187c635c 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -737,6 +737,12 @@ L: linux-me...@vger.kernel.org > S: Maintained > F: drivers/staging/media/sunxi/cedrus/ > > +ALLWINNER PWM DRIVER > +M: Ban Tao > +L: linux-...@vger.kernel.org > +S: Maintained > +F: drivers/pwm/pwm-sun8i-v536.c > + > ALPHA PORT > M: Richard Henderson > M: Ivan Kokshaysky > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > index 9a4f66ae8070..3418b5b898a9 100644 > --- a/drivers/pwm/Kconfig > +++ b/drivers/pwm/Kconfig > @@ -552,6 +552,17 @@ config PWM_SUN4I > To compile this driver as a module, choose M here: the module > will be called pwm-sun4i. > > +config PWM_SUN8I_V536 > + tristate "Allwinner SUN8I_V536 PWM support" > + depends on ARCH_SUNXI || COMPILE_TEST > + depends on HAS_IOMEM && COMMON_CLK > + help > + Enhanced PWM framework driver for Allwinner R818, A133, R329, > + V536 and V833 SoCs. > + > + To compile this driver as a module, choose M here: the module > + will be called pwm-sun8i-v536. > + > config PWM_TEGRA > tristate "NVIDIA Tegra PWM support" > depends on ARCH_TEGRA || COMPILE_TEST > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > index 6374d3b1d6f3..380d6b107308 100644 > --- a/drivers/pwm/Makefile > +++ b/drivers/pwm/Makefile > @@ -51,6 +51,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o > obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o > obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o > obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o > +obj-$(CONFIG_PWM_SUN8I_V536) += pwm-sun8i-v536.o > obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o > obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o > obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o > diff --git a/drivers/pwm/pwm-sun8i-v536.c b/drivers/pwm/pwm-sun8i-v536.c > new file mode 100644 > index ..52101df6bd41 > --- /dev/null > +++ b/drivers/pwm/pwm-sun8i-v536.c > @@ -0,0 +1,401 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Driver for Allwinner sun8i-v536 Pulse Width Modulation Controller > + * > + * Copyright (C) 2021 Ban Tao > + * > + * > + * Limitations: > + * - When PWM is disabled, the output is driven to inactive. > + * - If the register is reconfigured while PWM is running, > + * it does not complete the currently running period. > + * - If the user input duty is beyond acceptible limits, > + * -EINVAL is returned. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define PWM_GET_CLK_OFFSET(chan) (0x20 + ((chan >> 1) * 0x4)) Please add parenthesis around variable uses, i.e. +#define PWM_GET_CLK_OFFSET(chan) (0x20 + (((chan) >> 1) * 0x4)) > +#define PWM_CLK_APB_SCR BIT(7) > +#define PWM_DIV_M0 > +#define PWM_DIV_M_MASK GENMASK(3, PWM_DIV_M) > + > +#define PWM_CLK_REG 0x40 > +#define PWM_CLK_GATING BIT(0) > + > +#define PWM_ENABLE_REG 0x80 > +#define PWM_EN BIT(0) > + > +#define PWM_CTL_REG(chan)(0x100 + 0x20 * chan) > +#define PWM_ACT_STA BIT(8) > +#define PWM_PRESCAL_K0 > +#define PWM_PRESCAL_K_MASK GENMASK(7, PWM_PRESCAL_K) > + > +#define PWM_PERIOD_REG(chan) (0x104 + 0x20 * chan) > +#define PWM_ENTIRE_CYCLE 16 > +#define PWM_ENTIRE_CYCLE_MASKGENMASK(31, PWM_ENTIRE_CYCLE) > +#define PWM_ACT_CYCLE0 > +#define PWM_ACT_CYCLE_MASK GENMASK(15, PWM_ACT_CYCLE) > + > +#define BIT_CH(bit, chan)((bit) << (chan)) > +#define SET_BITS(shift, mask, reg, val) \ > + (((reg) & ~mask) | (val << (shift))) As already pointed out in v2: You're reinventing the stuff from here. Please
Re: [PATCH v3 1/2] pwm: sunxi: Add Allwinner SoC PWM controller driver
Hi, On Tue, Mar 02, 2021 at 08:37:37PM +0800, Ban Tao wrote: > From: Ban Tao > > The Allwinner R818, A133, R329, V536 and V833 has a new PWM controller > IP compared to the older Allwinner SoCs. > > Signed-off-by: Ban Tao Thanks for sending an update. Like I said in the previous version though, without proper SoC support upstream, that driver would effectively be dead code Maxime signature.asc Description: PGP signature
[PATCH v3 1/2] pwm: sunxi: Add Allwinner SoC PWM controller driver
From: Ban Tao
The Allwinner R818, A133, R329, V536 and V833 has a new PWM controller
IP compared to the older Allwinner SoCs.
Signed-off-by: Ban Tao
---
v1->v2:
1.delete unnecessary code.
2.using a named define for some constants.
3.Add comment in sun50i_pwm_config function.
4.using dev_err_probe() for error handling.
5.disable the clock after pwmchip_remove().
---
v2->v3:
1.fix all emitted warnings when PWM_DEBUG enabled.
2.modify the name of file pwm-sun50i to pwm-sun8i-v536.
3.fix "sun50i_pwm_from_chip" -> "to_sun8i_pwm_chip".
4.delete some unnecessary "compatible".
---
MAINTAINERS | 6 +
drivers/pwm/Kconfig | 11 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-sun8i-v536.c | 401 +++
4 files changed, 419 insertions(+)
create mode 100644 drivers/pwm/pwm-sun8i-v536.c
diff --git a/MAINTAINERS b/MAINTAINERS
index e73636b75f29..387e187c635c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -737,6 +737,12 @@ L: linux-me...@vger.kernel.org
S: Maintained
F: drivers/staging/media/sunxi/cedrus/
+ALLWINNER PWM DRIVER
+M: Ban Tao
+L: linux-...@vger.kernel.org
+S: Maintained
+F: drivers/pwm/pwm-sun8i-v536.c
+
ALPHA PORT
M: Richard Henderson
M: Ivan Kokshaysky
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 9a4f66ae8070..3418b5b898a9 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -552,6 +552,17 @@ config PWM_SUN4I
To compile this driver as a module, choose M here: the module
will be called pwm-sun4i.
+config PWM_SUN8I_V536
+ tristate "Allwinner SUN8I_V536 PWM support"
+ depends on ARCH_SUNXI || COMPILE_TEST
+ depends on HAS_IOMEM && COMMON_CLK
+ help
+ Enhanced PWM framework driver for Allwinner R818, A133, R329,
+ V536 and V833 SoCs.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-sun8i-v536.
+
config PWM_TEGRA
tristate "NVIDIA Tegra PWM support"
depends on ARCH_TEGRA || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 6374d3b1d6f3..380d6b107308 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
obj-$(CONFIG_PWM_STMPE)+= pwm-stmpe.o
obj-$(CONFIG_PWM_SUN4I)+= pwm-sun4i.o
+obj-$(CONFIG_PWM_SUN8I_V536) += pwm-sun8i-v536.o
obj-$(CONFIG_PWM_TEGRA)+= pwm-tegra.o
obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o
obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o
diff --git a/drivers/pwm/pwm-sun8i-v536.c b/drivers/pwm/pwm-sun8i-v536.c
new file mode 100644
index ..52101df6bd41
--- /dev/null
+++ b/drivers/pwm/pwm-sun8i-v536.c
@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Driver for Allwinner sun8i-v536 Pulse Width Modulation Controller
+ *
+ * Copyright (C) 2021 Ban Tao
+ *
+ *
+ * Limitations:
+ * - When PWM is disabled, the output is driven to inactive.
+ * - If the register is reconfigured while PWM is running,
+ * it does not complete the currently running period.
+ * - If the user input duty is beyond acceptible limits,
+ * -EINVAL is returned.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PWM_GET_CLK_OFFSET(chan) (0x20 + ((chan >> 1) * 0x4))
+#define PWM_CLK_APB_SCRBIT(7)
+#define PWM_DIV_M 0
+#define PWM_DIV_M_MASK GENMASK(3, PWM_DIV_M)
+
+#define PWM_CLK_REG0x40
+#define PWM_CLK_GATING BIT(0)
+
+#define PWM_ENABLE_REG 0x80
+#define PWM_EN BIT(0)
+
+#define PWM_CTL_REG(chan) (0x100 + 0x20 * chan)
+#define PWM_ACT_STABIT(8)
+#define PWM_PRESCAL_K 0
+#define PWM_PRESCAL_K_MASK GENMASK(7, PWM_PRESCAL_K)
+
+#define PWM_PERIOD_REG(chan) (0x104 + 0x20 * chan)
+#define PWM_ENTIRE_CYCLE 16
+#define PWM_ENTIRE_CYCLE_MASK GENMASK(31, PWM_ENTIRE_CYCLE)
+#define PWM_ACT_CYCLE 0
+#define PWM_ACT_CYCLE_MASK GENMASK(15, PWM_ACT_CYCLE)
+
+#define BIT_CH(bit, chan) ((bit) << (chan))
+#define SET_BITS(shift, mask, reg, val) \
+ (((reg) & ~mask) | (val << (shift)))
+
+#define PWM_OSC_CLK2400
+#define PWM_PRESCALER_MAX 256
+#define PWM_CLK_DIV_M__MAX 9
+#define PWM_ENTIRE_CYCLE_MAX 65536
+
+struct sun8i_pwm_data {
+ unsigned int npwm;
+};
+
+struct sun8i_pwm_chip {
+ struct pwm_chip chip;
+ struct clk *clk;
+ struct reset_control *rst_clk;
+ void __iomem *base;
+ const struct sun8i_pwm_data *data;
+};
+
+static inline struct sun8i_pwm_chip *to_sun8i_pwm_chip(struct pwm_chip *chip)
+{
+
