Re: [PATCH v3 2/2] pwm: sun8i-v536: document device tree bindings

2021-03-04 Thread Maxime Ripard
Hi,

On Tue, Mar 02, 2021 at 08:40:23PM +0800, Ban Tao wrote:
> From: Ban Tao 
> 
> This adds binding documentation for sun8i-v536 SoC PWM driver.
> 
> Signed-off-by: Ban Tao 
> ---
>  .../bindings/pwm/pwm-sun8i-v536.txt   | 24 +++

Bindings should be done using the YAML format now to enable the DT
validation.

Maxime


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[PATCH v3 2/2] pwm: sun8i-v536: document device tree bindings

2021-03-02 Thread Ban Tao
From: Ban Tao 

This adds binding documentation for sun8i-v536 SoC PWM driver.

Signed-off-by: Ban Tao 
---
 .../bindings/pwm/pwm-sun8i-v536.txt   | 24 +++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i-v536.txt

diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun8i-v536.txt 
b/Documentation/devicetree/bindings/pwm/pwm-sun8i-v536.txt
new file mode 100644
index ..ab3f4fe0560a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-sun8i-v536.txt
@@ -0,0 +1,24 @@
+Allwinner sun8i-v536 SoC PWM controller
+
+Required properties:
+ - compatible: should be "allwinner,-pwm"
+   "allwinner,sun8i-v833-pwm"
+   "allwinner,sun8i-v536-pwm"
+   "allwinner,sun50i-r818-pwm"
+   "allwinner,sun50i-a133-pwm"
+   "allwinner,sun50i-r329-pwm"
+ - reg: physical base address and length of the controller's registers
+ - #pwm-cells: should be 3. See pwm.txt in this directory for a description of
+   the cells format.
+ - clocks: From common clock binding, handle to the parent clock.
+ - resets: From reset clock binding, handle to the parent clock.
+
+Example:
+
+   pwm: pwm@300a {
+   compatible = "allwinner,sun50i-r818-pwm";
+   reg = <0x0300a000 0x3ff>;
+   clocks = < CLK_BUS_PWM>;
+   resets = < RST_BUS_PWM>;
+   #pwm-cells = <3>;
+   };
-- 
2.29.0