Re: [PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288

2014-10-23 Thread Doug Anderson 
Chris,

On Tue, Oct 21, 2014 at 4:25 PM, Chris Zhong  wrote:
> +static inline void rk3288_copy_data_to_sram(void)
> +{
> +   u32 resume_code_size = (u32)_bootdata_cpu_code -
> +  (u32)rockchip_slp_cpu_resume + 4;
> +
> +   /* save root sram data in ddr mem */
> +   memcpy(rk3288_bootram_base, bootram_save_data, SZ_4K);

I swore we looked at this before, but the above memcpy is backwards.

> +   /* move resume code and data to bootsram */
> +   memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
> +  resume_code_size);
> +}
> +
> +static inline void rk3288_restore_original_sram(void)
> +{
> +   memcpy(bootram_save_data, rk3288_bootram_base, SZ_4K);

This one too.
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Re: [PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288

2014-10-23 Thread Doug Anderson 
Chris,

On Tue, Oct 21, 2014 at 4:25 PM, Chris Zhong z...@rock-chips.com wrote:
 +static inline void rk3288_copy_data_to_sram(void)
 +{
 +   u32 resume_code_size = (u32)rkpm_bootdata_cpu_code -
 +  (u32)rockchip_slp_cpu_resume + 4;
 +
 +   /* save root sram data in ddr mem */
 +   memcpy(rk3288_bootram_base, bootram_save_data, SZ_4K);

I swore we looked at this before, but the above memcpy is backwards.

 +   /* move resume code and data to bootsram */
 +   memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
 +  resume_code_size);
 +}
 +
 +static inline void rk3288_restore_original_sram(void)
 +{
 +   memcpy(bootram_save_data, rk3288_bootram_base, SZ_4K);

This one too.
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Re: [PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288

2014-10-21 Thread Doug Anderson 
Chris,

On Tue, Oct 21, 2014 at 4:25 PM, Chris Zhong  wrote:
> @@ -34,7 +40,8 @@ static const char * const rockchip_board_dt_compat[] = {
>  };
>
>  DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
> -   .l2c_aux_val= 0,
> -   .l2c_aux_mask   = ~0,
> +   .l2c_aux_val= 0,
> +   .l2c_aux_mask   = ~0,

Please avoid unrelated spacing changes.


Other than that this is looking like a good starting point.  I'm sure
we'll find other things to do, but I'd be in favor of landing this and
spinning.  I can see a device suspend/resume with this patch, so:

Tested-by: Doug Anderson 
Reviewed-by: Doug Anderson 
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[PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288

2014-10-21 Thread Chris Zhong 
It's a basic version of suspend and resume for rockchip, it only support RK3288
now.

Signed-off-by: Tony Xie 
Signed-off-by: Chris Zhong 

---

Changes in v4:
- remove grf regmap

Changes in v3:
- move the pinmux of gpio6_c6 save and restore to pinctrl-rockchip

Changes in v2:
- add the regulator calls in prepare and finish.
- add the pinmux of gpio6_c6 save and restore

 arch/arm/mach-rockchip/Makefile   |1 +
 arch/arm/mach-rockchip/pm.c   |  307 +
 arch/arm/mach-rockchip/pm.h   |  102 
 arch/arm/mach-rockchip/rockchip.c |   11 +-
 arch/arm/mach-rockchip/sleep.S|   87 +++
 5 files changed, 506 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/pm.c
 create mode 100644 arch/arm/mach-rockchip/pm.h
 create mode 100644 arch/arm/mach-rockchip/sleep.S

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index b29d8ea..5c3a9b2 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1,4 +1,5 @@
 CFLAGS_platsmp.o := -march=armv7-a
 
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
+obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
new file mode 100644
index 000..c8e0091
--- /dev/null
+++ b/arch/arm/mach-rockchip/pm.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Tony Xie 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "pm.h"
+
+struct rockchip_pm_device_id {
+   const char *compatible;
+   const struct platform_suspend_ops *ops;
+   int (*init)(void);
+};
+
+static char bootram_save_data[SZ_4K];
+
+static void __iomem *rk3288_bootram_base;
+static phys_addr_t rk3288_bootram_phy;
+
+static struct regmap *pmu_regmap;
+static struct regmap *sgrf_regmap;
+
+static inline void rk3288_copy_data_to_sram(void)
+{
+   u32 resume_code_size = (u32)_bootdata_cpu_code -
+  (u32)rockchip_slp_cpu_resume + 4;
+
+   /* save root sram data in ddr mem */
+   memcpy(rk3288_bootram_base, bootram_save_data, SZ_4K);
+   /* move resume code and data to bootsram */
+   memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
+  resume_code_size);
+}
+
+static inline void rk3288_restore_original_sram(void)
+{
+   memcpy(bootram_save_data, rk3288_bootram_base, SZ_4K);
+}
+
+static inline u32 rk3288_l2_config(void)
+{
+   u32 l2ctlr;
+
+   asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
+   return l2ctlr;
+}
+
+static void rk3288_fill_in_bootram(u32 level)
+{
+   rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
+   rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume);
+
+   rkpm_bootdata_l2ctlr_f  = 1;
+   rkpm_bootdata_l2ctlr = rk3288_l2_config();
+
+   if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
+   /*
+   * In this mode the SDRAM power domain will be off,
+   * so it need to be resumed,
+   * but now the sdram resume code is not ready.
+   * i have to set "rkpm_bootdata_ddr_code" 0.
+   */
+   rkpm_bootdata_ddr_code = 0;
+   } else {
+   rkpm_bootdata_ddr_code = 0;
+   }
+
+   rk3288_copy_data_to_sram();
+}
+
+static u32 rk3288_pmu_pwr_mode_con;
+static u32 rk3288_sgrf_soc_con0;
+
+static void rk3288_slp_mode_set(int level)
+{
+   u32 mode_set, mode_set1;
+
+   regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, _sgrf_soc_con0);
+
+   regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
+   _pmu_pwr_mode_con);
+
+   /* set bit 8 so that system will resume to FAST_BOOT_ADDR */
+   regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
+BIT(SGRF_FAST_BOOT_EN) | BIT(SGRF_FAST_BOOT_EN + 16));
+
+   /* booting address of resuming system is from this register value */
+   regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
+rk3288_bootram_phy);
+
+   regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
+PMU_ARMINT_WAKEUP_EN);
+
+   mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
+  BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
+  BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
+  BIT(PMU_PWR_MODE_EN) |

[PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288

2014-10-21 Thread Chris Zhong 
It's a basic version of suspend and resume for rockchip, it only support RK3288
now.

Signed-off-by: Tony Xie x...@rock-chips.com
Signed-off-by: Chris Zhong z...@rock-chips.com

---

Changes in v4:
- remove grf regmap

Changes in v3:
- move the pinmux of gpio6_c6 save and restore to pinctrl-rockchip

Changes in v2:
- add the regulator calls in prepare and finish.
- add the pinmux of gpio6_c6 save and restore

 arch/arm/mach-rockchip/Makefile   |1 +
 arch/arm/mach-rockchip/pm.c   |  307 +
 arch/arm/mach-rockchip/pm.h   |  102 
 arch/arm/mach-rockchip/rockchip.c |   11 +-
 arch/arm/mach-rockchip/sleep.S|   87 +++
 5 files changed, 506 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/pm.c
 create mode 100644 arch/arm/mach-rockchip/pm.h
 create mode 100644 arch/arm/mach-rockchip/sleep.S

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index b29d8ea..5c3a9b2 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1,4 +1,5 @@
 CFLAGS_platsmp.o := -march=armv7-a
 
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
+obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
new file mode 100644
index 000..c8e0091
--- /dev/null
+++ b/arch/arm/mach-rockchip/pm.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Tony Xie tony@rock-chips.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include linux/init.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/regmap.h
+#include linux/suspend.h
+#include linux/mfd/syscon.h
+#include linux/regulator/machine.h
+
+#include asm/cacheflush.h
+#include asm/tlbflush.h
+#include asm/suspend.h
+
+#include pm.h
+
+struct rockchip_pm_device_id {
+   const char *compatible;
+   const struct platform_suspend_ops *ops;
+   int (*init)(void);
+};
+
+static char bootram_save_data[SZ_4K];
+
+static void __iomem *rk3288_bootram_base;
+static phys_addr_t rk3288_bootram_phy;
+
+static struct regmap *pmu_regmap;
+static struct regmap *sgrf_regmap;
+
+static inline void rk3288_copy_data_to_sram(void)
+{
+   u32 resume_code_size = (u32)rkpm_bootdata_cpu_code -
+  (u32)rockchip_slp_cpu_resume + 4;
+
+   /* save root sram data in ddr mem */
+   memcpy(rk3288_bootram_base, bootram_save_data, SZ_4K);
+   /* move resume code and data to bootsram */
+   memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
+  resume_code_size);
+}
+
+static inline void rk3288_restore_original_sram(void)
+{
+   memcpy(bootram_save_data, rk3288_bootram_base, SZ_4K);
+}
+
+static inline u32 rk3288_l2_config(void)
+{
+   u32 l2ctlr;
+
+   asm(mrc p15, 1, %0, c9, c0, 2 : =r (l2ctlr));
+   return l2ctlr;
+}
+
+static void rk3288_fill_in_bootram(u32 level)
+{
+   rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
+   rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume);
+
+   rkpm_bootdata_l2ctlr_f  = 1;
+   rkpm_bootdata_l2ctlr = rk3288_l2_config();
+
+   if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
+   /*
+   * In this mode the SDRAM power domain will be off,
+   * so it need to be resumed,
+   * but now the sdram resume code is not ready.
+   * i have to set rkpm_bootdata_ddr_code 0.
+   */
+   rkpm_bootdata_ddr_code = 0;
+   } else {
+   rkpm_bootdata_ddr_code = 0;
+   }
+
+   rk3288_copy_data_to_sram();
+}
+
+static u32 rk3288_pmu_pwr_mode_con;
+static u32 rk3288_sgrf_soc_con0;
+
+static void rk3288_slp_mode_set(int level)
+{
+   u32 mode_set, mode_set1;
+
+   regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, rk3288_sgrf_soc_con0);
+
+   regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
+   rk3288_pmu_pwr_mode_con);
+
+   /* set bit 8 so that system will resume to FAST_BOOT_ADDR */
+   regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
+BIT(SGRF_FAST_BOOT_EN) | BIT(SGRF_FAST_BOOT_EN + 16));
+
+   /* booting address of resuming system is from this register value */
+   regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
+rk3288_bootram_phy);
+
+   regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
+PMU_ARMINT_WAKEUP_EN);
+
+   mode_set

Re: [PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288

2014-10-21 Thread Doug Anderson 
Chris,

On Tue, Oct 21, 2014 at 4:25 PM, Chris Zhong z...@rock-chips.com wrote:
 @@ -34,7 +40,8 @@ static const char * const rockchip_board_dt_compat[] = {
  };

  DT_MACHINE_START(ROCKCHIP_DT, Rockchip Cortex-A9 (Device Tree))
 -   .l2c_aux_val= 0,
 -   .l2c_aux_mask   = ~0,
 +   .l2c_aux_val= 0,
 +   .l2c_aux_mask   = ~0,

Please avoid unrelated spacing changes.


Other than that this is looking like a good starting point.  I'm sure
we'll find other things to do, but I'd be in favor of landing this and
spinning.  I can see a device suspend/resume with this patch, so:

Tested-by: Doug Anderson diand...@chromium.org
Reviewed-by: Doug Anderson diand...@chromium.org
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