Adds dsi host controller support for the Unisoc's display subsystem.
Adds dsi phy support for the Unisoc's display subsystem.
Only MIPI DSI Displays supported, DP/TV/HMDI will be support
in the feature.
v1:
- Remove dphy and dsi graph binding, merge the dphy driver into the dsi.
v2:
- Use drm_xxx to replace all DRM_XXX.
- Use kzalloc to replace devm_kzalloc for sprd_dsi structure init.
v4:
- Use drmm_helpers to allocate encoder.
- Move allocate encoder and connector to bind funtion.
---
drivers/gpu/drm/sprd/Makefile |7 +-
drivers/gpu/drm/sprd/dw_dsi_ctrl.c | 794 +
drivers/gpu/drm/sprd/dw_dsi_ctrl.h | 1475
drivers/gpu/drm/sprd/dw_dsi_ctrl_ppi.c | 157 +++
drivers/gpu/drm/sprd/dw_dsi_ctrl_ppi.h | 26 +
drivers/gpu/drm/sprd/megacores_pll.c | 317 +
drivers/gpu/drm/sprd/megacores_pll.h | 146 +++
drivers/gpu/drm/sprd/sprd_drm.c|1 +
drivers/gpu/drm/sprd/sprd_drm.h|1 +
drivers/gpu/drm/sprd/sprd_dsi.c| 1132 ++
drivers/gpu/drm/sprd/sprd_dsi.h| 104 ++
11 files changed, 4158 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/sprd/dw_dsi_ctrl.c
create mode 100644 drivers/gpu/drm/sprd/dw_dsi_ctrl.h
create mode 100644 drivers/gpu/drm/sprd/dw_dsi_ctrl_ppi.c
create mode 100644 drivers/gpu/drm/sprd/dw_dsi_ctrl_ppi.h
create mode 100644 drivers/gpu/drm/sprd/megacores_pll.c
create mode 100644 drivers/gpu/drm/sprd/megacores_pll.h
create mode 100644 drivers/gpu/drm/sprd/sprd_dsi.c
create mode 100644 drivers/gpu/drm/sprd/sprd_dsi.h
diff --git a/drivers/gpu/drm/sprd/Makefile b/drivers/gpu/drm/sprd/Makefile
index 6c25bfa99..d49f4977b 100644
--- a/drivers/gpu/drm/sprd/Makefile
+++ b/drivers/gpu/drm/sprd/Makefile
@@ -1,5 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
obj-y := sprd_drm.o \
- sprd_dpu.o
-
+ sprd_dpu.o \
+ sprd_dsi.o \
+ dw_dsi_ctrl.o \
+ dw_dsi_ctrl_ppi.o \
+ megacores_pll.o
diff --git a/drivers/gpu/drm/sprd/dw_dsi_ctrl.c
b/drivers/gpu/drm/sprd/dw_dsi_ctrl.c
new file mode 100644
index 0..1034aba4a
--- /dev/null
+++ b/drivers/gpu/drm/sprd/dw_dsi_ctrl.c
@@ -0,0 +1,794 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "dw_dsi_ctrl.h"
+
+/*
+ * Modify power status of DSI Host core
+ */
+void dsi_power_enable(struct dsi_context *ctx, int enable)
+{
+ struct dsi_reg *reg = (struct dsi_reg *)ctx->base;
+
+ writel(enable, >SOFT_RESET);
+}
+/*
+ * Enable/disable DPI video mode
+ */
+void dsi_video_mode(struct dsi_context *ctx)
+{
+ struct dsi_reg *reg = (struct dsi_reg *)ctx->base;
+
+ writel(0, >DSI_MODE_CFG);
+}
+/*
+ * Enable command mode (Generic interface)
+ */
+void dsi_cmd_mode(struct dsi_context *ctx)
+{
+ struct dsi_reg *reg = (struct dsi_reg *)ctx->base;
+
+ writel(1, >DSI_MODE_CFG);
+}
+
+bool dsi_is_cmd_mode(struct dsi_context *ctx)
+{
+ struct dsi_reg *reg = (struct dsi_reg *)ctx->base;
+
+ return readl(>DSI_MODE_CFG);
+}
+/*
+ * Configure the read back virtual channel for the generic interface
+ */
+void dsi_rx_vcid(struct dsi_context *ctx, u8 vc)
+{
+ struct dsi_reg *reg = (struct dsi_reg *)ctx->base;
+ union _0x1C virtual_channel_id;
+
+ virtual_channel_id.val = readl(>VIRTUAL_CHANNEL_ID);
+ virtual_channel_id.bits.gen_rx_vcid = vc;
+
+ writel(virtual_channel_id.val, >VIRTUAL_CHANNEL_ID);
+}
+/*
+ * Write the DPI video virtual channel destination
+ */
+void dsi_video_vcid(struct dsi_context *ctx, u8 vc)
+{
+ struct dsi_reg *reg = (struct dsi_reg *)ctx->base;
+ union _0x1C virtual_channel_id;
+
+ virtual_channel_id.val = readl(>VIRTUAL_CHANNEL_ID);
+ virtual_channel_id.bits.video_pkt_vcid = vc;
+
+ writel(virtual_channel_id.val, >VIRTUAL_CHANNEL_ID);
+}
+/*
+ * Set DPI video mode type (burst/non-burst - with sync pulses or events)
+ */
+void dsi_dpi_video_burst_mode(struct dsi_context *ctx, int mode)
+{
+ struct dsi_reg *reg = (struct dsi_reg *)ctx->base;
+ union _0x38 vid_mode_cfg;
+
+ vid_mode_cfg.val = readl(>VID_MODE_CFG);
+ vid_mode_cfg.bits.vid_mode_type = mode;
+
+ writel(vid_mode_cfg.val, >VID_MODE_CFG);
+}
+/*
+ * Set DPI video color coding
+ */
+void dsi_dpi_color_coding(struct dsi_context *ctx, int coding)
+{
+ struct dsi_reg *reg = (struct dsi_reg *)ctx->base;
+ union _0x20 dpi_video_format;
+
+ dpi_video_format.val = readl(>DPI_VIDEO_FORMAT);
+ dpi_video_format.bits.dpi_video_mode_format = coding;
+
+ writel(dpi_video_format.val, >DPI_VIDEO_FORMAT);
+}
+/*
+ * Configure the Horizontal Line time
+ * param "byte_cycle" taken to transmit the total of the horizontal line
+ */
+void dsi_dpi_hline_time(struct dsi_context *ctx, u16 byte_cycle)
+{
+ struct dsi_reg *reg = (struct dsi_reg *)ctx->base;
+ union _0x2C
