subject:"\[PATCH v5 4\/7\] phy\: qcom\-qmp\: rename common registers"

Re: [PATCH v5 4/7] phy: qcom-qmp: rename common registers

2021-03-29 Thread Bjorn Andersson

On Sun 28 Mar 15:52 CDT 2021, Dmitry Baryshkov wrote:

> A plenty of DP PHY registers are common between V3 and V4. To simplify
> V4 code, rename all common registers.
> 
> Signed-off-by: Dmitry Baryshkov 

Reviewed-by: Bjorn Andersson 

Regards,
Bjorn

> ---
>  drivers/phy/qualcomm/phy-qcom-qmp.c | 50 ++---
>  drivers/phy/qualcomm/phy-qcom-qmp.h | 37 ++---
>  2 files changed, 44 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c 
> b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 4150096fd350..097bc005ba43 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -2435,20 +2435,20 @@ static void qcom_qmp_v3_phy_dp_aux_init(struct 
> qmp_phy *qphy)
>  {
>   writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
>  DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> -qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
> +qphy->pcs + QSERDES_DP_PHY_PD_CTL);
>  
>   /* Turn on BIAS current for PHY/PLL */
>   writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
>  QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
>  qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
>  
> - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
> + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
>  
>   writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
>  DP_PHY_PD_CTL_LANE_0_1_PWRDN |
>  DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
>  DP_PHY_PD_CTL_DP_CLAMP_EN,
> -qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
> +qphy->pcs + QSERDES_DP_PHY_PD_CTL);
>  
>   writel(QSERDES_V3_COM_BIAS_EN |
>  QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
> @@ -2456,16 +2456,16 @@ static void qcom_qmp_v3_phy_dp_aux_init(struct 
> qmp_phy *qphy)
>  QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
>  qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
>  
> - writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0);
> - writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
> - writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
> - writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3);
> - writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4);
> - writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5);
> - writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6);
> - writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7);
> - writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8);
> - writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9);
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
> + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
> + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
> + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
> + writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
> + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
>   qphy->dp_aux_cfg = 0;
>  
>   writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> @@ -2556,9 +2556,9 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct 
> qmp_phy *qphy)
>*  writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
>*/
>   val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
> - writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
> + writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
>  
> - writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
> + writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
>   writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
>   writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
>  
> @@ -2588,11 +2588,11 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct 
> qmp_phy *qphy)
>   clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 10);
>   clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
>  
> - writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
> - writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
> - writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
> - writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
> - writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
> + writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
> + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
>  
>   writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
>  
> @@ -2603,7 +2603,7 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct 
> qmp_phy *qphy)
>   1))
>

[PATCH v5 4/7] phy: qcom-qmp: rename common registers

2021-03-28 Thread Dmitry Baryshkov

A plenty of DP PHY registers are common between V3 and V4. To simplify
V4 code, rename all common registers.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/phy/qualcomm/phy-qcom-qmp.c | 50 ++---
 drivers/phy/qualcomm/phy-qcom-qmp.h | 37 ++---
 2 files changed, 44 insertions(+), 43 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c 
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 4150096fd350..097bc005ba43 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -2435,20 +2435,20 @@ static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy 
*qphy)
 {
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
   DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-  qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+  qphy->pcs + QSERDES_DP_PHY_PD_CTL);
 
/* Turn on BIAS current for PHY/PLL */
writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
   QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
   qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
 
-   writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+   writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
 
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
   DP_PHY_PD_CTL_LANE_0_1_PWRDN |
   DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
   DP_PHY_PD_CTL_DP_CLAMP_EN,
-  qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+  qphy->pcs + QSERDES_DP_PHY_PD_CTL);
 
writel(QSERDES_V3_COM_BIAS_EN |
   QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
@@ -2456,16 +2456,16 @@ static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy 
*qphy)
   QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
   qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
 
-   writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0);
-   writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
-   writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
-   writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3);
-   writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4);
-   writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5);
-   writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6);
-   writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7);
-   writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8);
-   writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9);
+   writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
+   writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
+   writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
+   writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
+   writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
+   writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
+   writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
+   writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
+   writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
+   writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
qphy->dp_aux_cfg = 0;
 
writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
@@ -2556,9 +2556,9 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct 
qmp_phy *qphy)
 *  writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
 */
val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-   writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+   writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
 
-   writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
+   writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
 
@@ -2588,11 +2588,11 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct 
qmp_phy *qphy)
clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 10);
clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
 
-   writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
-   writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
-   writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
-   writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
-   writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
+   writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
+   writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
+   writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
+   writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
+   writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
 
writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
 
@@ -2603,7 +2603,7 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct 
qmp_phy *qphy)
1))
return -ETIMEDOUT;
 
-   writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
+   writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
 
if

Re: [PATCH v5 4/7] phy: qcom-qmp: rename common registers

[PATCH v5 4/7] phy: qcom-qmp: rename common registers

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