Re: [PATCH v6 2/3] clocksource: keystone: add bindings for keystone timer

2014-02-11 Thread Daniel Lezcano 

On 02/10/2014 11:10 AM, Ivan Khoronzhuk wrote:

This patch provides bindings for the 64-bit timer in the KeyStone
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
timers, each half can operate in conjunction (chain mode) or independently
(unchained mode) of each other.

It is global timer is a free running up-counter and can generate interrupt
when the counter reaches preset counter values.

Documentation:
http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf

Acked-by: Rob Herring 
Acked-by: Santosh Shilimkar 
Signed-off-by: Ivan Khoronzhuk 
---


Applied to my tree for 3.15

Thanks !

  -- Daniel


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Re: [PATCH v6 2/3] clocksource: keystone: add bindings for keystone timer

2014-02-11 Thread Daniel Lezcano 

On 02/10/2014 11:10 AM, Ivan Khoronzhuk wrote:

This patch provides bindings for the 64-bit timer in the KeyStone
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
timers, each half can operate in conjunction (chain mode) or independently
(unchained mode) of each other.

It is global timer is a free running up-counter and can generate interrupt
when the counter reaches preset counter values.

Documentation:
http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf

Acked-by: Rob Herring r...@kernel.org
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---


Applied to my tree for 3.15

Thanks !

  -- Daniel


--
 http://www.linaro.org/ Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  http://www.facebook.com/pages/Linaro Facebook |
http://twitter.com/#!/linaroorg Twitter |
http://www.linaro.org/linaro-blog/ Blog

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[PATCH v6 2/3] clocksource: keystone: add bindings for keystone timer

2014-02-10 Thread Ivan Khoronzhuk 
This patch provides bindings for the 64-bit timer in the KeyStone
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
timers, each half can operate in conjunction (chain mode) or independently
(unchained mode) of each other.

It is global timer is a free running up-counter and can generate interrupt
when the counter reaches preset counter values.

Documentation:
http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf

Acked-by: Rob Herring 
Acked-by: Santosh Shilimkar 
Signed-off-by: Ivan Khoronzhuk 
---
 .../bindings/timer/ti,keystone-timer.txt   | 29 ++
 1 file changed, 29 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/timer/ti,keystone-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt 
b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt
new file mode 100644
index 000..5fbe361
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt
@@ -0,0 +1,29 @@
+* Device tree bindings for Texas instruments Keystone timer
+
+This document provides bindings for the 64-bit timer in the KeyStone
+architecture devices. The timer can be configured as a general-purpose 64-bit
+timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
+timers, each half can operate in conjunction (chain mode) or independently
+(unchained mode) of each other.
+
+It is global timer is a free running up-counter and can generate interrupt
+when the counter reaches preset counter values.
+
+Documentation:
+http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
+
+Required properties:
+
+- compatible : should be "ti,keystone-timer".
+- reg : specifies base physical address and count of the registers.
+- interrupts : interrupt generated by the timer.
+- clocks : the clock feeding the timer clock.
+
+Example:
+
+timer@22f {
+   compatible = "ti,keystone-timer";
+   reg = <0x022f 0x80>;
+   interrupts = ;
+   clocks = <>;
+};
-- 
1.8.3.2

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[PATCH v6 2/3] clocksource: keystone: add bindings for keystone timer

2014-02-10 Thread Ivan Khoronzhuk 
This patch provides bindings for the 64-bit timer in the KeyStone
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
timers, each half can operate in conjunction (chain mode) or independently
(unchained mode) of each other.

It is global timer is a free running up-counter and can generate interrupt
when the counter reaches preset counter values.

Documentation:
http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf

Acked-by: Rob Herring r...@kernel.org
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
 .../bindings/timer/ti,keystone-timer.txt   | 29 ++
 1 file changed, 29 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/timer/ti,keystone-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt 
b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt
new file mode 100644
index 000..5fbe361
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt
@@ -0,0 +1,29 @@
+* Device tree bindings for Texas instruments Keystone timer
+
+This document provides bindings for the 64-bit timer in the KeyStone
+architecture devices. The timer can be configured as a general-purpose 64-bit
+timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
+timers, each half can operate in conjunction (chain mode) or independently
+(unchained mode) of each other.
+
+It is global timer is a free running up-counter and can generate interrupt
+when the counter reaches preset counter values.
+
+Documentation:
+http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
+
+Required properties:
+
+- compatible : should be ti,keystone-timer.
+- reg : specifies base physical address and count of the registers.
+- interrupts : interrupt generated by the timer.
+- clocks : the clock feeding the timer clock.
+
+Example:
+
+timer@22f {
+   compatible = ti,keystone-timer;
+   reg = 0x022f 0x80;
+   interrupts = GIC_SPI 110 IRQ_TYPE_EDGE_RISING;
+   clocks = clktimer15;
+};
-- 
1.8.3.2

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