[PATCH v8 1/4] PCI: hisi: Add DT binding for PCIe of Kirin SoC series

[Xiaowei Song]

Signed-off-by: Xiaowei Song 
---
 .../devicetree/bindings/pci/kirin-pcie.txt | 49 ++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt 
b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
new file mode 100644
index ..2dd0e7a368ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
@@ -0,0 +1,49 @@
+HiSilicon Kirin SoCs PCIe host DT description
+
+Kirin PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver
+and inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible:
+   "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
+- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg-names: Must include the following entries:
+  "dbi": controller configuration registers;
+  "apb": apb Ctrl register defined by Kirin;
+  "phy": apb PHY register defined by Kirin;
+  "config": PCIe configuration space registers.
+- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
+
+Optional properties:
+
+Example based on kirin960:
+
+pcie@f400 {
+compatible = "hisilicon,kirin-pcie";
+reg =  <0x0 0xf400 0x0 0x1000>, <0x0 0xff3fe000 
0x0 0x1000>,
+ <0x0 0xf3f2 0x0 0x4>, <0x0 0xF400 
0 0x2000>;
+reg-names = "dbi","apb","phy", "config";
+bus-range = <0x0  0x1>;
+#address-cells = <3>;
+#size-cells = <2>;
+device_type = "pci";
+ranges = <0x0200 0x0 0x 0x0 0xf500 0x0 
0x200>;
+num-lanes = <1>;
+#interrupt-cells = <1>;
+interrupt-map-mask = <0xf800 0 0 7>;
+   interrupt-map = <0x0 0 0 2  0 0 0  283 4>,
+<0x0 0 0 3  0 0 0  284 4>,
+<0x0 0 0 4  0 0 0  285 4>;
+clocks = <_ctrl HI3660_PCIEPHY_REF>,
+<_ctrl HI3660_CLK_GATE_PCIEAUX>,
+<_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+<_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+<_ctrl HI3660_ACLK_GATE_PCIE>;
+clock-names = "pcie_phy_ref", "pcie_aux",
+"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+reset-gpios = < 1 0 >;
+};
-- 
2.11.GIT

[PATCH v8 1/4] PCI: hisi: Add DT binding for PCIe of Kirin SoC series

[Xiaowei Song]

Signed-off-by: Xiaowei Song 
---
 .../devicetree/bindings/pci/kirin-pcie.txt | 49 ++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt 
b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
new file mode 100644
index ..2dd0e7a368ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
@@ -0,0 +1,49 @@
+HiSilicon Kirin SoCs PCIe host DT description
+
+Kirin PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver
+and inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible:
+   "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
+- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg-names: Must include the following entries:
+  "dbi": controller configuration registers;
+  "apb": apb Ctrl register defined by Kirin;
+  "phy": apb PHY register defined by Kirin;
+  "config": PCIe configuration space registers.
+- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
+
+Optional properties:
+
+Example based on kirin960:
+
+pcie@f400 {
+compatible = "hisilicon,kirin-pcie";
+reg =  <0x0 0xf400 0x0 0x1000>, <0x0 0xff3fe000 
0x0 0x1000>,
+ <0x0 0xf3f2 0x0 0x4>, <0x0 0xF400 
0 0x2000>;
+reg-names = "dbi","apb","phy", "config";
+bus-range = <0x0  0x1>;
+#address-cells = <3>;
+#size-cells = <2>;
+device_type = "pci";
+ranges = <0x0200 0x0 0x 0x0 0xf500 0x0 
0x200>;
+num-lanes = <1>;
+#interrupt-cells = <1>;
+interrupt-map-mask = <0xf800 0 0 7>;
+   interrupt-map = <0x0 0 0 2  0 0 0  283 4>,
+<0x0 0 0 3  0 0 0  284 4>,
+<0x0 0 0 4  0 0 0  285 4>;
+clocks = <_ctrl HI3660_PCIEPHY_REF>,
+<_ctrl HI3660_CLK_GATE_PCIEAUX>,
+<_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+<_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+<_ctrl HI3660_ACLK_GATE_PCIE>;
+clock-names = "pcie_phy_ref", "pcie_aux",
+"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+reset-gpios = < 1 0 >;
+};
-- 
2.11.GIT