Re: [PATCHv7 00/14] x86: 5-level paging enabling for v4.13, Part 4

2017-06-22 Thread Ingo Molnar 

* Kirill A. Shutemov  wrote:

> On Thu, Jun 22, 2017 at 11:04:22AM +0200, Ingo Molnar wrote:
> > 
> > * Kirill A. Shutemov  wrote:
> > 
> > > On Tue, Jun 06, 2017 at 02:31:19PM +0300, Kirill A. Shutemov wrote:
> > > > Please review and consider applying.
> > > 
> > > Hi Ingo,
> > > 
> > > I've noticed you haven't applied last two patches of the patchset.
> > > 
> > > Is there any problem with them? Or what is you plan here?
> > 
> > As they change/extend the Linux ABI I still need to think about them some 
> > more.
> 
> Okay, I see.
> 
> Let me know if any action is required from my side.

Yeah, so I had a look, and the ABI principle of using the mmap() address hint 
to 
trigger 57-bit address space allocations still looks mostly good to me, but 
please 
split up this patch:

 Subject: [PATCHv7 14/14] x86/mm: Allow to have userspace mappings above 47-bits

 arch/x86/include/asm/elf.h   |  4 ++--
 arch/x86/include/asm/mpx.h   |  9 +
 arch/x86/include/asm/processor.h | 12 +---
 arch/x86/kernel/sys_x86_64.c | 30 ++
 arch/x86/mm/hugetlbpage.c| 27 +++
 arch/x86/mm/mmap.c   |  6 +++---
 arch/x86/mm/mpx.c| 33 -
 7 files changed, 104 insertions(+), 17 deletions(-)

One patch should add the MPX quirk, another should add all the TASK_SIZE 
variations, without actually changing the logic, etc. - while the final patch 
adds 
the larger task size. Please try to split it into as many patches as possible - 
I'd say 4-5 look ideal. All of this changes existing code paths and if things 
break we'd like some small patch to be bisected to. The finer grained structure 
also makes review easier.

Also, please rename the tasksize_*() functions to task_size_ (in yet another 
patch) - it's absolutely silly that we have 'TASK_SIZE' in uppercase but 
'tasksize' in lowercase ...

Thanks,

Ingo

Re: [PATCHv7 00/14] x86: 5-level paging enabling for v4.13, Part 4

2017-06-22 Thread Ingo Molnar 

* Kirill A. Shutemov  wrote:

> On Thu, Jun 22, 2017 at 11:04:22AM +0200, Ingo Molnar wrote:
> > 
> > * Kirill A. Shutemov  wrote:
> > 
> > > On Tue, Jun 06, 2017 at 02:31:19PM +0300, Kirill A. Shutemov wrote:
> > > > Please review and consider applying.
> > > 
> > > Hi Ingo,
> > > 
> > > I've noticed you haven't applied last two patches of the patchset.
> > > 
> > > Is there any problem with them? Or what is you plan here?
> > 
> > As they change/extend the Linux ABI I still need to think about them some 
> > more.
> 
> Okay, I see.
> 
> Let me know if any action is required from my side.

Yeah, so I had a look, and the ABI principle of using the mmap() address hint 
to 
trigger 57-bit address space allocations still looks mostly good to me, but 
please 
split up this patch:

 Subject: [PATCHv7 14/14] x86/mm: Allow to have userspace mappings above 47-bits

 arch/x86/include/asm/elf.h   |  4 ++--
 arch/x86/include/asm/mpx.h   |  9 +
 arch/x86/include/asm/processor.h | 12 +---
 arch/x86/kernel/sys_x86_64.c | 30 ++
 arch/x86/mm/hugetlbpage.c| 27 +++
 arch/x86/mm/mmap.c   |  6 +++---
 arch/x86/mm/mpx.c| 33 -
 7 files changed, 104 insertions(+), 17 deletions(-)

One patch should add the MPX quirk, another should add all the TASK_SIZE 
variations, without actually changing the logic, etc. - while the final patch 
adds 
the larger task size. Please try to split it into as many patches as possible - 
I'd say 4-5 look ideal. All of this changes existing code paths and if things 
break we'd like some small patch to be bisected to. The finer grained structure 
also makes review easier.

Also, please rename the tasksize_*() functions to task_size_ (in yet another 
patch) - it's absolutely silly that we have 'TASK_SIZE' in uppercase but 
'tasksize' in lowercase ...

Thanks,

Ingo

Re: [PATCHv7 00/14] x86: 5-level paging enabling for v4.13, Part 4

2017-06-22 Thread Kirill A. Shutemov 
On Thu, Jun 22, 2017 at 11:04:22AM +0200, Ingo Molnar wrote:
> 
> * Kirill A. Shutemov  wrote:
> 
> > On Tue, Jun 06, 2017 at 02:31:19PM +0300, Kirill A. Shutemov wrote:
> > > Please review and consider applying.
> > 
> > Hi Ingo,
> > 
> > I've noticed you haven't applied last two patches of the patchset.
> > 
> > Is there any problem with them? Or what is you plan here?
> 
> As they change/extend the Linux ABI I still need to think about them some 
> more.

Okay, I see.

Let me know if any action is required from my side.

-- 
 Kirill A. Shutemov

Re: [PATCHv7 00/14] x86: 5-level paging enabling for v4.13, Part 4

2017-06-22 Thread Kirill A. Shutemov 
On Thu, Jun 22, 2017 at 11:04:22AM +0200, Ingo Molnar wrote:
> 
> * Kirill A. Shutemov  wrote:
> 
> > On Tue, Jun 06, 2017 at 02:31:19PM +0300, Kirill A. Shutemov wrote:
> > > Please review and consider applying.
> > 
> > Hi Ingo,
> > 
> > I've noticed you haven't applied last two patches of the patchset.
> > 
> > Is there any problem with them? Or what is you plan here?
> 
> As they change/extend the Linux ABI I still need to think about them some 
> more.

Okay, I see.

Let me know if any action is required from my side.

-- 
 Kirill A. Shutemov

Re: [PATCHv7 00/14] x86: 5-level paging enabling for v4.13, Part 4

2017-06-22 Thread Ingo Molnar 

* Kirill A. Shutemov  wrote:

> On Tue, Jun 06, 2017 at 02:31:19PM +0300, Kirill A. Shutemov wrote:
> > Please review and consider applying.
> 
> Hi Ingo,
> 
> I've noticed you haven't applied last two patches of the patchset.
> 
> Is there any problem with them? Or what is you plan here?

As they change/extend the Linux ABI I still need to think about them some more.

Thanks,

Ingo

Re: [PATCHv7 00/14] x86: 5-level paging enabling for v4.13, Part 4

2017-06-22 Thread Ingo Molnar 

* Kirill A. Shutemov  wrote:

> On Tue, Jun 06, 2017 at 02:31:19PM +0300, Kirill A. Shutemov wrote:
> > Please review and consider applying.
> 
> Hi Ingo,
> 
> I've noticed you haven't applied last two patches of the patchset.
> 
> Is there any problem with them? Or what is you plan here?

As they change/extend the Linux ABI I still need to think about them some more.

Thanks,

Ingo

Re: [PATCHv7 00/14] x86: 5-level paging enabling for v4.13, Part 4

2017-06-22 Thread Kirill A. Shutemov 
On Tue, Jun 06, 2017 at 02:31:19PM +0300, Kirill A. Shutemov wrote:
> Please review and consider applying.

Hi Ingo,

I've noticed you haven't applied last two patches of the patchset.

Is there any problem with them? Or what is you plan here?

-- 
 Kirill A. Shutemov

Re: [PATCHv7 00/14] x86: 5-level paging enabling for v4.13, Part 4

2017-06-22 Thread Kirill A. Shutemov 
On Tue, Jun 06, 2017 at 02:31:19PM +0300, Kirill A. Shutemov wrote:
> Please review and consider applying.

Hi Ingo,

I've noticed you haven't applied last two patches of the patchset.

Is there any problem with them? Or what is you plan here?

-- 
 Kirill A. Shutemov

[PATCHv7 00/14] x86: 5-level paging enabling for v4.13, Part 4

2017-06-06 Thread Kirill A. Shutemov 
Here's updated version of the last bunch of of patches that brings initial
5-level paging enabling.

Please review and consider applying.

Changes since v6:
 - Major rework 5-level paging enabling in decompression code to fix #GP when
   bootloader enables long mode.
 - Fix in sync_global_pgds() (Andrey Ryabinin);
 - Couple Reviewed-by form Juergen Gross.

Kirill A. Shutemov (14):
  x86/mm/gup: Switch GUP to the generic get_user_page_fast()
implementation
  x86/asm: Fix comment in return_from_SYSCALL_64
  x86/boot/efi: Cleanup initialization of GDT entries
  x86/boot/efi: Fix __KERNEL_CS definition of GDT entry on 64-bit
configuration
  x86/boot/efi: Define __KERNEL32_CS GDT on 64-bit configurations
  x86/boot/compressed: Enable 5-level paging during decompression stage
  x86/boot/64: Rewrite startup_64 in C
  x86/boot/64: Rename init_level4_pgt and early_level4_pgt
  x86/boot/64: Add support of additional page table level during early
boot
  x86/mm: Add sync_global_pgds() for configuration with 5-level paging
  x86/mm: Make kernel_physical_mapping_init() support 5-level paging
  x86/mm: Add support for 5-level paging for KASLR
  x86: Enable 5-level paging support
  x86/mm: Allow to have userspace mappings above 47-bits

 arch/arm/Kconfig|   2 +-
 arch/arm64/Kconfig  |   2 +-
 arch/powerpc/Kconfig|   2 +-
 arch/x86/Kconfig|   8 +
 arch/x86/boot/compressed/eboot.c|  73 ++--
 arch/x86/boot/compressed/head_64.S  |  86 -
 arch/x86/entry/entry_64.S   |   3 +-
 arch/x86/include/asm/elf.h  |   4 +-
 arch/x86/include/asm/mmu_context.h  |  12 -
 arch/x86/include/asm/mpx.h  |   9 +
 arch/x86/include/asm/pgtable-3level.h   |  47 +++
 arch/x86/include/asm/pgtable.h  |  55 ++-
 arch/x86/include/asm/pgtable_64.h   |  22 +-
 arch/x86/include/asm/processor.h|  12 +-
 arch/x86/include/uapi/asm/processor-flags.h |   2 +
 arch/x86/kernel/espfix_64.c |   2 +-
 arch/x86/kernel/head64.c| 143 +++-
 arch/x86/kernel/head_64.S   | 131 ++--
 arch/x86/kernel/machine_kexec_64.c  |   2 +-
 arch/x86/kernel/sys_x86_64.c|  30 +-
 arch/x86/mm/Makefile|   2 +-
 arch/x86/mm/dump_pagetables.c   |   2 +-
 arch/x86/mm/gup.c   | 496 
 arch/x86/mm/hugetlbpage.c   |  27 +-
 arch/x86/mm/init_64.c   | 108 +-
 arch/x86/mm/kasan_init_64.c |  12 +-
 arch/x86/mm/kaslr.c |  81 +++--
 arch/x86/mm/mmap.c  |   6 +-
 arch/x86/mm/mpx.c   |  33 +-
 arch/x86/realmode/init.c|   2 +-
 arch/x86/xen/Kconfig|   1 +
 arch/x86/xen/mmu_pv.c   |  16 +-
 arch/x86/xen/xen-pvh.S  |   2 +-
 mm/Kconfig  |   2 +-
 mm/gup.c|  10 +-
 35 files changed, 722 insertions(+), 725 deletions(-)
 delete mode 100644 arch/x86/mm/gup.c

-- 
2.11.0

[PATCHv7 00/14] x86: 5-level paging enabling for v4.13, Part 4

2017-06-06 Thread Kirill A. Shutemov 
Here's updated version of the last bunch of of patches that brings initial
5-level paging enabling.

Please review and consider applying.

Changes since v6:
 - Major rework 5-level paging enabling in decompression code to fix #GP when
   bootloader enables long mode.
 - Fix in sync_global_pgds() (Andrey Ryabinin);
 - Couple Reviewed-by form Juergen Gross.

Kirill A. Shutemov (14):
  x86/mm/gup: Switch GUP to the generic get_user_page_fast()
implementation
  x86/asm: Fix comment in return_from_SYSCALL_64
  x86/boot/efi: Cleanup initialization of GDT entries
  x86/boot/efi: Fix __KERNEL_CS definition of GDT entry on 64-bit
configuration
  x86/boot/efi: Define __KERNEL32_CS GDT on 64-bit configurations
  x86/boot/compressed: Enable 5-level paging during decompression stage
  x86/boot/64: Rewrite startup_64 in C
  x86/boot/64: Rename init_level4_pgt and early_level4_pgt
  x86/boot/64: Add support of additional page table level during early
boot
  x86/mm: Add sync_global_pgds() for configuration with 5-level paging
  x86/mm: Make kernel_physical_mapping_init() support 5-level paging
  x86/mm: Add support for 5-level paging for KASLR
  x86: Enable 5-level paging support
  x86/mm: Allow to have userspace mappings above 47-bits

 arch/arm/Kconfig|   2 +-
 arch/arm64/Kconfig  |   2 +-
 arch/powerpc/Kconfig|   2 +-
 arch/x86/Kconfig|   8 +
 arch/x86/boot/compressed/eboot.c|  73 ++--
 arch/x86/boot/compressed/head_64.S  |  86 -
 arch/x86/entry/entry_64.S   |   3 +-
 arch/x86/include/asm/elf.h  |   4 +-
 arch/x86/include/asm/mmu_context.h  |  12 -
 arch/x86/include/asm/mpx.h  |   9 +
 arch/x86/include/asm/pgtable-3level.h   |  47 +++
 arch/x86/include/asm/pgtable.h  |  55 ++-
 arch/x86/include/asm/pgtable_64.h   |  22 +-
 arch/x86/include/asm/processor.h|  12 +-
 arch/x86/include/uapi/asm/processor-flags.h |   2 +
 arch/x86/kernel/espfix_64.c |   2 +-
 arch/x86/kernel/head64.c| 143 +++-
 arch/x86/kernel/head_64.S   | 131 ++--
 arch/x86/kernel/machine_kexec_64.c  |   2 +-
 arch/x86/kernel/sys_x86_64.c|  30 +-
 arch/x86/mm/Makefile|   2 +-
 arch/x86/mm/dump_pagetables.c   |   2 +-
 arch/x86/mm/gup.c   | 496 
 arch/x86/mm/hugetlbpage.c   |  27 +-
 arch/x86/mm/init_64.c   | 108 +-
 arch/x86/mm/kasan_init_64.c |  12 +-
 arch/x86/mm/kaslr.c |  81 +++--
 arch/x86/mm/mmap.c  |   6 +-
 arch/x86/mm/mpx.c   |  33 +-
 arch/x86/realmode/init.c|   2 +-
 arch/x86/xen/Kconfig|   1 +
 arch/x86/xen/mmu_pv.c   |  16 +-
 arch/x86/xen/xen-pvh.S  |   2 +-
 mm/Kconfig  |   2 +-
 mm/gup.c|  10 +-
 35 files changed, 722 insertions(+), 725 deletions(-)
 delete mode 100644 arch/x86/mm/gup.c

-- 
2.11.0