Re: [PATCH] ARM: dts: dra7-evm: add parallel NOR flash support
On Fri, Aug 1, 2014 at 1:24 PM, Tony Lindgren t...@atomide.com wrote: * Roger Quadros rog...@ti.com [140801 00:49]: On 08/01/2014 09:38 AM, Tony Lindgren wrote: * Roger Quadros rog...@ti.com [140731 04:46]: +Sourav for QSPI and Balaji for mmc On 07/30/2014 10:40 PM, Pekon Gupta wrote: Hi Roger, On Tue, Jul 29, 2014 at 5:45 PM, Roger Quadros rog...@ti.com wrote: On 07/23/2014 01:58 PM, Pekon Gupta wrote: This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM. The Flash device is connected to GPMC controller on chip-select[0] and accessed as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and is CFI compatible. As multiple devices are share GPMC pins on this board, so following board settings are required to detect NOR device: SW5.1 (NAND_BOOTn) = OFF (logic-1) SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */ SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) Why does NOR have any dependency on states of eMMC_BOOTn and QSPI_BOOTn? If you see the schematics of J6-EVM, GPMC data and control lines are shared between NAND, NOR, eMMC (and probably QSPI also). I don't have access to TI's hardaware or board schematics anymore, so please double check. I just took a deeper look in the schematics. It has nothing to do with GPMC Data and control lines but with the address lines. The GPMC address lines are muxed on the same pins of the SoC as QSPI and MMC2. i.e. A13-A18,CS2 for QSPI and A19-A27,CS1 for MMC2 NAND can probably work simultaneously with QSPI and MMC2 but for NOR case, QSPI and MMC2 need to be disabled. This is starting to look ugly where apart from changing the DIP switch the DTS has to be hand modified to support a certain case. Lets leave the most usable configuration for default case i.e. NAND, QSPI and MMC2 enabled and keep NOR information in the dts but keep it disabled with a note that if NOR is enabled then NAND, QSPI, and MMC2 nodes need to be disabled. I will resend this patch with the relevant changes. It might make sense for the gpmc driver to manage the pins in some cases. That would allow dynamic muxing of the pins depending which driver is loaded, or even during runtime if needed. It is more like a board configuration so something more generic than the gpmc driver has to manage. Also, QSPI and MMC don't fall under GPMC scope. There are 2 things that need to change to update the hardware configuration. 1) The pinmux via the enabling/disabling (or plugging in/out) of relevant nodes in the DT. 2) The I2C GPIOs which reconfigure the DIP Switch lines in order to reconfigure external Muxes. Oh OK, yeah gpmc should only manage gpmc pins, this would need a separate driver for coordinating things. You need to also consider the case where multiple devices of different types are connected to different chip-selects like; - NAND on chip-select[0] - NOR on chip-select[1] And with acceptance of 'Rostislav Lisovy''s patch [1] this multi-device configuration is possible on custom boards. It would have been appropriate if pinctrl-probe was called from protocol drivers (OMAP-NAND and NOR in this case). But I don't know if that's feasible even. Also how drivers would handle probe conflicts arising with common pins. Example: gpmc_ad[7:0] will be common to pin-mux of both NAND and NOR devices. Does pinctrl framework gives freedom to _ignore_ conflicts on already configured pins, and continues with configuring remaining non-conflicting pins ? If yes, then moving pinctrl-probe to OMAP-NAND | NOR protocol driver should be more appropriate. with regards, pekon [1] https://patchwork.kernel.org/patch/4514561/ -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP2+: fix gpmc_cs_remap: re-allocating chip-select address space based on DT
Hi Roger,
On Fri, Aug 1, 2014 at 4:30 PM, Roger Quadros rog...@ti.com wrote:
On 07/23/2014 09:17 PM, Pekon Gupta wrote:
+ /* allocate enough address-space under GPMC chip-select to device */
+ if (size SZ_256M) {
+ pr_err(%s: memory device 256MB not supported\n, __func__);
+ return -ENODEV;
+ } else if (size SZ_128M) {
+ WARN((size != SZ_256M), cs=%d: allocating 256MB\n, cs);
+ size = SZ_256M;
+ } else if (size SZ_64M) {
+ WARN((size != SZ_128M), cs=%d: allocating 128MB\n, cs);
+ size = SZ_128M;
+ } else if (size SZ_32M) {
+ WARN((size != SZ_64M), cs=%d: allocating 64MB\n, cs);
+ size = SZ_64M;
+ } else if (size SZ_16M) {
+ WARN((size != SZ_32M), cs=%d: allocating 64MB\n, cs);
Print message should be allocating 32MB
yes, my bad, copy-paste errors..
[...]
Otherwise it is fine. I can make the changes and resend.
cheers,
-roger
Yes please re-send. Thanks much.
with regards, pekon
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Re: [PATCH] ARM: dts: dra7-evm: add parallel NOR flash support
Hi Roger,
On Tue, Jul 29, 2014 at 5:45 PM, Roger Quadros rog...@ti.com wrote:
On 07/23/2014 01:58 PM, Pekon Gupta wrote:
This patch adds support for parallel NOR device (S29GL512S10) present on
J6-EVM.
The Flash device is connected to GPMC controller on chip-select[0] and
accessed
as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits)
and
is CFI compatible.
As multiple devices are share GPMC pins on this board, so following board
settings are required to detect NOR device:
SW5.1 (NAND_BOOTn) = OFF (logic-1)
SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */
SW5.3 (eMMC_BOOTn) = OFF (logic-1)
SW5.4 (QSPI_BOOTn) = OFF (logic-1)
Why does NOR have any dependency on states of eMMC_BOOTn and QSPI_BOOTn?
If you see the schematics of J6-EVM, GPMC data and control lines are shared
between NAND, NOR, eMMC (and probably QSPI also).
I don't have access to TI's hardaware or board schematics anymore, so
please double check.
Also to maintain NAND Boot functionality, following setting are kept as
default
- NAND status=enabled
- NOR status=disabled
Too bad they designed the hardware so that either NOR or NAND can be used at
a time.
Better to mention about this limitation by stating that CS0 is shared between
NOR and NAND
and only one can be used at a time.
NAND/NOR/eMMC/QSPI effectively all are storage devices, so users may
not use all of
them at once, so may be to optimize usage of pins they added multiple
devices on CS0.
Sorry, I may not be able to re-spin this patch anytime soon, as I have
no access to TI
resources so request you to please re-send it with appropriate commit
log change as you wish.
Signed-off-by: Pekon Gupta pe...@ti.com
---
/* Flash read/write access tested after enabling NOR sub-node in DT */
linux# flash_erase /dev/mtd9 0 0
linux# dd if=/dev/urandom of=/tmp/source.hex bs=1c count=2048
linux# mtd_debug write /dev/mtd9 0x0 2048 /tmp/source.hex
linux# mtd_debug read /dev/mtd9 0x0 2048 /tmp/destination.hex
linux# diff /tmp/source.hex /tmp/destination.hex
arch/arm/boot/dts/dra7-evm.dts | 141
-
1 file changed, 140 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 4adc280..1ee9727 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -151,6 +151,66 @@
0xd0(PIN_OUTPUT | MUX_MODE0)/*
gpmc_be0n_cle */
;
};
+
+ nor_flash_x16: nor_flash_x16 {
+ /* On DRA7 EVM, NOR_BOOTn comes from DIP switch
+ * So NOR flash requires following switch settings:
+ * SW5.1 (NAND_BOOTn) = OFF (logic-1)
+ * SW5.2 (NOR_BOOTn) = ON (logic-0) Active-low
+ * SW5.3 (eMMC_BOOTn) = OFF (logic-1)
+ * SW5.4 (QSPI_BOOTn) = OFF (logic-1)
+ */
The only requirement for NOR_BOOTn is SW5.2 = ON and SW5.1 (NAND_BOOTn) = OFF.
As mentioned above, please check board schematics
IIRC, GPMC lines pass through various levels of on-board
bi-directional multiplexers,
And 'select' lines of these multiplexers are controlled indirectly via
these xxx_BOOTn switches.
[...]
i2c1 {
@@ -417,8 +477,9 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = nand_flash_x16;
- ranges = 0 0 0 0x0100;/* minimum GPMC partition = 16MB */
+ ranges = 0 0 0x0800 0x0400; /* address offset=128MB,
range=512Mb=64MB */
nand@0,0 {
+ status = okay;
Not needed. If it is not explicitly disabled it is always enabled by default.
Yes, but good to have clarity in DTS, as most users will just copy-paste TI-EVM
DTS and then tweak it for their own custom board DTS. So better to have this
mentioned explicitely.
with regards, pekon
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[PATCH v2 0/3] ARM: dts: am335x-bone: Beaglebone cape DTS
*changes v1-v2 * - fixed pin-ctrl property, as GPMC does not configure pin-mux for individual sub-nodes. - fixed LCD pixed clock freq, and sync-ctrl *Original v1* This series adds DTS for following Beaglebone capes: Memory Cape: http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion NAND Cape: http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module NOR Cape: http://elinux.org/Beagleboardtoys:BeagleBone_128Mb_16-Bit_NOR_Module LCD4 Cape: http://elinux.org/CircuitCo:BeagleBone_LCD4 Based on Tree: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap omap-for-v3.16/dt-v2 Acceptance of cape DTS in mainline is still under discussion [1], so multiple 'Tested-by' would be helpful. Note: In order to avoid conflicts with existing DTS, device nodes added in these patches have status=disabled, and need to be enabled via u-boot. DT nodes can be selectively enabled | disabled via u-boot [2] Example: Below sequence works for NAND cape patch. --- /* load DTB */ u-boot tftp 0x8100 am335x-boneblack.dtb u-boot fdt addr 0x8100 /* disable MMC2 node */ u-boot fdt list /ocp/mmc@481d8000 u-boot fdt set /ocp/mmc@481d8000 status \d\i\s\a\b\l\e\d u-boot fdt list /ocp/mmc@481d8000 status /* enable GPMC node */ u-boot fdt list /ocp/gpmc u-boot fdt set /ocp/gpmc status \o\k\a\y u-boot fdt list /ocp/gpmc status /* enable ELM node */ u-boot fdt list /ocp/elm u-boot fdt set /ocp/elm status \o\k\a\y u-boot fdt list /ocp/elm status /* boot uImage */ tftp 0x8200 uImage bootm 0x8200 - 0x8100 Note: fdt set command does not accept string literals as binding values, it internally converts them to string, so escape sequenced characters were used here.. okay == \o\k\a\y disabled == \d\i\s\a\b\l\e\d --- [1] http://www.spinics.net/lists/linux-omap/msg108505.html [2] http://www.denx.de/wiki/view/DULG/UBootCmdFDT Pekon Gupta (3): ARM: dts: am335x-bone: add support for beaglebone NAND cape ARM: dts: am335x-bone: add support for beaglebone NOR cape ARM: dts: am335x-bone: add support for beaglebone LCD4 cape arch/arm/boot/dts/am335x-bone-display-cape.dts | 104 +++ arch/arm/boot/dts/am335x-bone-memory-cape.dts | 243 + arch/arm/boot/dts/am335x-bone.dts | 2 + arch/arm/boot/dts/am335x-boneblack.dts | 2 + 4 files changed, 351 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-bone-display-cape.dts create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/3] ARM: dts: am335x-bone: add support for beaglebone NOR cape
This patch adds support of NOR cape[1] for both Beaglebone (white) and
Beaglebone(Black) boards. NOR Flash on this cape is connected to GPMC
chip-select[0] and accesses as external memory-mapped device.
This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device.
As GPMC chip-select[0] can be shared by multiple capes, so NAND cape pin-mux
is kept by default.
[1] http://boardzoo.com/index.php/beaglebone/bone-128mb-16-bit-nor.html
http://boardzoo.com/index.php/beaglebone/bone-mem-exp.html
Note: These capes have been tested on Beaglebone-Black so these capes work
perfectly on BBB, as against the information provided on above links.
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-bone-memory-cape.dts | 118 +-
1 file changed, 117 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am335x-bone-memory-cape.dts
b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
index 08efed3..0283549 100644
--- a/arch/arm/boot/dts/am335x-bone-memory-cape.dts
+++ b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
@@ -38,11 +38,48 @@
0x9c (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_be0n_cle.gpmc_be0n_cle */
;
};
+
+ bbcape_nor_flash_pins: bbcape_nor_flash_pins {
+ pinctrl-single,pins =
+ 0x00 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad0.gpmc_ad0 */
+ 0x04 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad1.gpmc_ad1 */
+ 0x08 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad2.gpmc_ad2 */
+ 0x0c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad3.gpmc_ad3 */
+ 0x10 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad4.gpmc_ad4 */
+ 0x14 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad5.gpmc_ad5 */
+ 0x18 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad6.gpmc_ad6 */
+ 0x1c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad7.gpmc_ad7 */
+ 0x20 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad8.gpmc_ad8 */
+ 0x24 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad9.gpmc_ad9 */
+ 0x28 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad10.gpmc_ad10
*/
+ 0x2c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad11.gpmc_ad11
*/
+ 0x30 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad12.gpmc_ad12
*/
+ 0x34 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad13.gpmc_ad13
*/
+ 0x38 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad14.gpmc_ad14
*/
+ 0x3c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad15.gpmc_ad15
*/
+ 0x40 (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a0.gpmc_a0 */
+ 0x44 (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a1.gpmc_a1 */
+ 0x48 (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a2.gpmc_a2 */
+ 0x4c (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a3.gpmc_a3 */
+ 0x50 (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a4.gpmc_a4 */
+ 0x54 (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a5.gpmc_a5 */
+ 0x58 (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a6.gpmc_a6 */
+ 0x5c (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a7.gpmc_a7 */
+ 0x70 (MUX_MODE0 | PIN_INPUT_PULLUP )/*
gpmc_wait0.gpmc_wait0 */
+ /* 0x74 (MUX_MODE0 | PIN_OUTPUT_PULLUP) */ /* gpmc_wpn
(not connected) */
+ 0x7c (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_wen.gpmc_wen */
+ 0x9c (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_be0n_cle.gpmc_be0n_cle */
+ ;
+ };
};
gpmc {
- ranges = 0 0 0 0x0100;/* address range = 16MB (minimum GPMC
partition) */
+ ranges = 0 0 0x0800 0x0100; /* address offset=128MB,
range=128Mb=16MB */
+ /* For NOR support below pin-mux should be changed to
bbcape_nor_flash_pins */
pinctrl-names = default;
pinctrl-0 = bbcape_nand_flash_pins;
nand@0,0 {
@@ -124,4 +161,83 @@
reg = 0x00a0 0x3f60;
};
};
+
+ nor@0,0 {
+ status = disabled;
+ compatible = cfi-flash;
+ reg = 0 0 0x0100; /* device memory map = actual
device size = 16MB */
+ /* generic bindings */
+ linux,mtd-name = Micron,M29W128G;
+ bank-width = 2;
+ /* vendor specific bindings */
+ gpmc,device-width = 2;
+ gpmc,mux-add-data = 2;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 120
[PATCH v2 3/3] ARM: dts: am335x-bone: add support for beaglebone LCD4 cape
This patch adds support for LCD4 cape as advertised on
http://elinux.org/CircuitCo:BeagleBone_LCD4
This cape has:
* 480x272 TFT-LCD panel
- LCD panel datasheet and timing information are sourced from [1]
- LCD backlight is connected to 'EHRPWM1A' on cape board, but its used for
enabling backlight power-supply. So 'gpio-backlight' driver is used instead
of 'pwm-backlight' driver (Kconfig: BACKLIGHT_GPIO=y).
* 4-wire resistive Touchscreen
*Known constrains*
As LCD panel pins (lcd_data, hsync, vsync, pclk) are shared with on-board
NXP HDMI framer, so either HDMI or LCD-cape can be used at time. Thus while
using this cape 'hdmi' DT node needs to be disabled in am335x-boneblack.dts
[1] www.newhavendisplay.com/specs/NHD-4.3-480272MF-ATXI-T-1.pdf
www.newhavendisplay.com/app_notes/OTA5180A.pdf
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-bone-display-cape.dts | 104 +
arch/arm/boot/dts/am335x-bone.dts | 1 +
arch/arm/boot/dts/am335x-boneblack.dts | 1 +
3 files changed, 106 insertions(+)
create mode 100644 arch/arm/boot/dts/am335x-bone-display-cape.dts
diff --git a/arch/arm/boot/dts/am335x-bone-display-cape.dts
b/arch/arm/boot/dts/am335x-bone-display-cape.dts
new file mode 100644
index 000..fe10ad8
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone-display-cape.dts
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This DTS adds supports for display capes using LCD interface for display
+ * and GPIO or PWM interface for backlight controls.
+ */
+
+
+am33xx_pinmux {
+ bbcape_backlight_pins: bbcape_backlight_pins {
+ pinctrl-single,pins =
+ 0x48 (PIN_OUTPUT | MUX_MODE7) /*
gpmc_a[2].GPIO1[18] (backlight control) */
+ ;
+ };
+
+ bbcape_lcd_pins: bbcape_lcd_pins {
+ pinctrl-single,pins =
+ 0xa0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data0.lcd_data0 */
+ 0xa4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data1.lcd_data1 */
+ 0xa8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data2.lcd_data2 */
+ 0xac (PIN_OUTPUT | MUX_MODE0) /*
lcd_data3.lcd_data3 */
+ 0xb0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data4.lcd_data4 */
+ 0xb4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data5.lcd_data5 */
+ 0xb8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data6.lcd_data6 */
+ 0xbc (PIN_OUTPUT | MUX_MODE0) /*
lcd_data7.lcd_data7 */
+ 0xc0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data8.lcd_data8 */
+ 0xc4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data9.lcd_data9 */
+ 0xc8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data10.lcd_data10 */
+ 0xcc (PIN_OUTPUT | MUX_MODE0) /*
lcd_data11.lcd_data11 */
+ 0xd0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data12.lcd_data12 */
+ 0xd4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data13.lcd_data13 */
+ 0xd8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data14.lcd_data14 */
+ 0xdc (PIN_OUTPUT | MUX_MODE0) /*
lcd_data15.lcd_data15 */
+ 0xe0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_vsync.lcd_vsync */
+ 0xe4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_hsync.lcd_hsync */
+ 0xe8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_pclk.lcd_pclk */
+ 0xec (PIN_OUTPUT | MUX_MODE0) /*
lcd_ac_bias_en.lcd_ac_bias_en (lcd_en) */
+ 0x1a4 (PIN_OUTPUT_PULLUP | MUX_MODE7) /*
mcasp0_fsr.gpio3[19] (lcd_disen) */
+ ;
+ };
+
+ bbcape_touchscreen_pins: bbcape_touchscreen_pins {
+ pinctrl-single,pins =
+ 0x184 (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
uart1_txd.gpio0[15] (enter) */
+ 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
gpmc_a0.gpio1[16] (left) */
+ 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
gpmc_a1.gpio1[17] (right) */
+ 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
gpmc_a3.gpio1[19] (up) */
+ 0x198 (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
mcasp0_axr0.gpio3[16] (down) */
+ ;
+ };
+};
+
+
+/ {
+ backlight {
+ status = disabled;
+ compatible = gpio-backlight;
+ pinctrl-names = default;
+ pinctrl-0 = bbcape_backlight_pins
[PATCH v2 1/3] ARM: dts: am335x-bone: add support for beaglebone NAND cape
Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
Further information and datasheets can be found at [1] and [2]
* How to boot from NAND using Memory Expander + NAND Cape ? *
- Important: As BOOTSEL values are sampled only at POR, so after changing any
setting on SW2 (DIP switch), disconnect and reconnect all board power supply
(including mini-USB console port) to POR the beaglebone.
- Selection of ECC scheme
for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
for NAND cape(b), ROM code expects BCH16_HW ecc-scheme
- Selection of boot modes can be controlled via DIP switch(SW2) present on
Memory Expander cape, so first boot via MMC or other sources to flash NAND
device and then switch to SW2[SWITCH_BOOT]=ON to boot from NAND Cape.
SW2[SWITCH_BOOT] == OFF follow default boot order MMC- SPI - UART - USB
SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2)
- For NAND boot following switch settings need to be followed
SW2[ 1] = ON (SYSBOOT[ 0]==0: NAND boot mode selected )
SW2[ 2] = ON (SYSBOOT[ 1]==0: -- do -- )
SW2[ 3] = OFF (SYSBOOT[ 2]==1: -- do -- )
SW2[ 4] = OFF (SYSBOOT[ 3]==1: -- do -- )
SW2[ 5] = ON (SYSBOOT[ 4]==0: -- do -- )
SW2[ 6] = OFF (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
SW2[ 7] = ON (SYSBOOT[ 9]==0: ECC done by ROM )
SW2[ 8] = ON (SYSBOOT[10]==0: Non Muxed device )
SW2[ 9] = ON (SYSBOOT[11]==0:-- do -- )
[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2]
http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org
---
arch/arm/boot/dts/am335x-bone-memory-cape.dts | 127 ++
arch/arm/boot/dts/am335x-bone.dts | 1 +
arch/arm/boot/dts/am335x-boneblack.dts| 1 +
3 files changed, 129 insertions(+)
create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts
diff --git a/arch/arm/boot/dts/am335x-bone-memory-cape.dts
b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
new file mode 100644
index 000..08efed3
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This DTS adds supports for capes using GPMC interface to connect external
+ * memory like NAND, NOR Flash to Beaglebone-White and Beaglebone-Black.
+ */
+
+
+am33xx_pinmux {
+ bbcape_nand_flash_pins: bbcape_nand_flash_pins {
+ pinctrl-single,pins =
+ 0x00 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad0.gpmc_ad0 */
+ 0x04 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad1.gpmc_ad1 */
+ 0x08 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad2.gpmc_ad2 */
+ 0x0c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad3.gpmc_ad3 */
+ 0x10 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad4.gpmc_ad4 */
+ 0x14 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad5.gpmc_ad5 */
+ 0x18 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad6.gpmc_ad6 */
+ 0x1c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad7.gpmc_ad7 */
+ 0x20 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad8.gpmc_ad8 */
+ 0x24 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad9.gpmc_ad9 */
+ 0x28 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad10.gpmc_ad10
*/
+ 0x2c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad11.gpmc_ad11
*/
+ 0x30 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad12.gpmc_ad12
*/
+ 0x34 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad13.gpmc_ad13
*/
+ 0x38 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad14.gpmc_ad14
*/
+ 0x3c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad15.gpmc_ad15
*/
+ 0x70 (MUX_MODE0 | PIN_INPUT_PULLUP )/*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
gpmc_wpn.gpmc_wpn */
+ 0x7c (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (MUX_MODE0 | PIN_OUTPUT
[PATCH v3] ARM: dts: am335x-bone: add support for beaglebone LCD4 cape
This patch adds support for LCD4 cape as advertised on
http://elinux.org/CircuitCo:BeagleBone_LCD4
This cape has:
* 480x272 TFT-LCD panel
- LCD panel datasheet and timing information are sourced from [1]
- LCD backlight is connected to 'EHRPWM1A' on cape board, but its used for
enabling backlight power-supply. So 'gpio-backlight' driver is used instead
of 'pwm-backlight' driver (Kconfig: BACKLIGHT_GPIO=y).
* 4-wire resistive Touchscreen
*Known constrains*
As LCD panel pins (lcd_data, hsync, vsync, pclk) are shared with on-board
NXP HDMI framer, so either HDMI or LCD-cape can be used at time. Thus while
using this cape 'hdmi' DT node needs to be disabled in am335x-boneblack.dts
[1] www.newhavendisplay.com/specs/NHD-4.3-480272MF-ATXI-T-1.pdf
www.newhavendisplay.com/app_notes/OTA5180A.pdf
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-bone-display-cape.dts | 104 +
arch/arm/boot/dts/am335x-bone.dts | 1 +
arch/arm/boot/dts/am335x-boneblack.dts | 1 +
3 files changed, 106 insertions(+)
create mode 100644 arch/arm/boot/dts/am335x-bone-display-cape.dts
diff --git a/arch/arm/boot/dts/am335x-bone-display-cape.dts
b/arch/arm/boot/dts/am335x-bone-display-cape.dts
new file mode 100644
index 000..e2ab5e4
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone-display-cape.dts
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This DTS adds supports for display capes using LCD interface for display
+ * and GPIO or PWM interface for backlight controls.
+ */
+
+
+am33xx_pinmux {
+ bbcape_backlight_pins: bbcape_backlight_pins {
+ pinctrl-single,pins =
+ 0x48 (PIN_OUTPUT | MUX_MODE7) /*
gpmc_a[2].GPIO1[18] (backlight control) */
+ ;
+ };
+
+ bbcape_lcd_pins: bbcape_lcd_pins {
+ pinctrl-single,pins =
+ 0xa0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data0.lcd_data0 */
+ 0xa4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data1.lcd_data1 */
+ 0xa8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data2.lcd_data2 */
+ 0xac (PIN_OUTPUT | MUX_MODE0) /*
lcd_data3.lcd_data3 */
+ 0xb0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data4.lcd_data4 */
+ 0xb4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data5.lcd_data5 */
+ 0xb8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data6.lcd_data6 */
+ 0xbc (PIN_OUTPUT | MUX_MODE0) /*
lcd_data7.lcd_data7 */
+ 0xc0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data8.lcd_data8 */
+ 0xc4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data9.lcd_data9 */
+ 0xc8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data10.lcd_data10 */
+ 0xcc (PIN_OUTPUT | MUX_MODE0) /*
lcd_data11.lcd_data11 */
+ 0xd0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data12.lcd_data12 */
+ 0xd4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data13.lcd_data13 */
+ 0xd8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data14.lcd_data14 */
+ 0xdc (PIN_OUTPUT | MUX_MODE0) /*
lcd_data15.lcd_data15 */
+ 0xe0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_vsync.lcd_vsync */
+ 0xe4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_hsync.lcd_hsync */
+ 0xe8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_pclk.lcd_pclk */
+ 0xec (PIN_OUTPUT | MUX_MODE0) /*
lcd_ac_bias_en.lcd_ac_bias_en (lcd_en) */
+ 0x1a4 (PIN_OUTPUT_PULLUP | MUX_MODE7) /*
mcasp0_fsr.gpio3[19] (lcd_disen) */
+ ;
+ };
+
+ bbcape_touchscreen_pins: bbcape_touchscreen_pins {
+ pinctrl-single,pins =
+ 0x184 (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
uart1_txd.gpio0[15] (enter) */
+ 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
gpmc_a0.gpio1[16] (left) */
+ 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
gpmc_a1.gpio1[17] (right) */
+ 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
gpmc_a3.gpio1[19] (up) */
+ 0x198 (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
mcasp0_axr0.gpio3[16] (down) */
+ ;
+ };
+};
+
+
+/ {
+ backlight {
+ status = disabled;
+ compatible = gpio-backlight;
+ pinctrl-names = default;
+ pinctrl-0 = bbcape_backlight_pins
[PATCH] ARM: dts: dra7-evm: add parallel NOR flash support
This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
The Flash device is connected to GPMC controller on chip-select[0] and accessed
as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
is CFI compatible.
As multiple devices are share GPMC pins on this board, so following board
settings are required to detect NOR device:
SW5.1 (NAND_BOOTn) = OFF (logic-1)
SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */
SW5.3 (eMMC_BOOTn) = OFF (logic-1)
SW5.4 (QSPI_BOOTn) = OFF (logic-1)
Also to maintain NAND Boot functionality, following setting are kept as default
- NAND status=enabled
- NOR status=disabled
Signed-off-by: Pekon Gupta pe...@ti.com
---
/* Flash read/write access tested after enabling NOR sub-node in DT */
linux# flash_erase /dev/mtd9 0 0
linux# dd if=/dev/urandom of=/tmp/source.hex bs=1c count=2048
linux# mtd_debug write /dev/mtd9 0x0 2048 /tmp/source.hex
linux# mtd_debug read /dev/mtd9 0x0 2048 /tmp/destination.hex
linux# diff /tmp/source.hex /tmp/destination.hex
arch/arm/boot/dts/dra7-evm.dts | 141 -
1 file changed, 140 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 4adc280..1ee9727 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -151,6 +151,66 @@
0xd0(PIN_OUTPUT | MUX_MODE0)/*
gpmc_be0n_cle */
;
};
+
+ nor_flash_x16: nor_flash_x16 {
+ /* On DRA7 EVM, NOR_BOOTn comes from DIP switch
+* So NOR flash requires following switch settings:
+* SW5.1 (NAND_BOOTn) = OFF (logic-1)
+* SW5.2 (NOR_BOOTn) = ON (logic-0) Active-low
+* SW5.3 (eMMC_BOOTn) = OFF (logic-1)
+* SW5.4 (QSPI_BOOTn) = OFF (logic-1)
+*/
+ pinctrl-single,pins =
+ 0x00(PIN_INPUT | MUX_MODE0)/* gpmc_ad0 */
+ 0x04(PIN_INPUT | MUX_MODE0)/* gpmc_ad1 */
+ 0x08(PIN_INPUT | MUX_MODE0)/* gpmc_ad2 */
+ 0x0c(PIN_INPUT | MUX_MODE0)/* gpmc_ad3 */
+ 0x10(PIN_INPUT | MUX_MODE0)/* gpmc_ad4 */
+ 0x14(PIN_INPUT | MUX_MODE0)/* gpmc_ad5 */
+ 0x18(PIN_INPUT | MUX_MODE0)/* gpmc_ad6 */
+ 0x1c(PIN_INPUT | MUX_MODE0)/* gpmc_ad7 */
+ 0x20(PIN_INPUT | MUX_MODE0)/* gpmc_ad8 */
+ 0x24(PIN_INPUT | MUX_MODE0)/* gpmc_ad9 */
+ 0x28(PIN_INPUT | MUX_MODE0)/* gpmc_ad10 */
+ 0x2c(PIN_INPUT | MUX_MODE0)/* gpmc_ad11 */
+ 0x30(PIN_INPUT | MUX_MODE0)/* gpmc_ad12 */
+ 0x34(PIN_INPUT | MUX_MODE0)/* gpmc_ad13 */
+ 0x38(PIN_INPUT | MUX_MODE0)/* gpmc_ad14 */
+ 0x3c(PIN_INPUT | MUX_MODE0)/* gpmc_ad15 */
+ 0x40(PIN_INPUT | MUX_MODE0)/* gpmc_a0 */
+ 0x44(PIN_INPUT | MUX_MODE0)/* gpmc_a1 */
+ 0x48(PIN_INPUT | MUX_MODE0)/* gpmc_a2 */
+ 0x4c(PIN_INPUT | MUX_MODE0)/* gpmc_a3 */
+ 0x50(PIN_INPUT | MUX_MODE0)/* gpmc_a4 */
+ 0x54(PIN_INPUT | MUX_MODE0)/* gpmc_a5 */
+ 0x58(PIN_INPUT | MUX_MODE0)/* gpmc_a6 */
+ 0x5c(PIN_INPUT | MUX_MODE0)/* gpmc_a7 */
+ 0x60(PIN_INPUT | MUX_MODE0)/* gpmc_a8 */
+ 0x64(PIN_INPUT | MUX_MODE0)/* gpmc_a9 */
+ 0x68(PIN_INPUT | MUX_MODE0)/* gpmc_a10 */
+ 0x6c(PIN_INPUT | MUX_MODE0)/* gpmc_a11 */
+ 0x70(PIN_INPUT | MUX_MODE0)/* gpmc_a12 */
+ 0x74(PIN_INPUT | MUX_MODE0)/* gpmc_a13 */
+ 0x78(PIN_INPUT | MUX_MODE0)/* gpmc_a14 */
+ 0x7c(PIN_INPUT | MUX_MODE0)/* gpmc_a15 */
+ 0x80(PIN_INPUT | MUX_MODE0)/* gpmc_a16 */
+ 0x84(PIN_INPUT | MUX_MODE0)/* gpmc_a17 */
+ 0x88(PIN_INPUT | MUX_MODE0)/* gpmc_a18 */
+ 0x8c(PIN_INPUT | MUX_MODE0)/* gpmc_a19 */
+ 0x90(PIN_INPUT | MUX_MODE0)/* gpmc_a20 */
+ 0x94(PIN_INPUT
[PATCH] ARM: OMAP2+: fix gpmc_cs_remap: re-allocating chip-select address space based on DT
Each GPMC chip-select needs to be configured for (base-address,CS-size) so that
GPMC understands the address-space allocated to device connected externally.
These chip-select configurations (base-address, CS-size) follow some basic
mapping rules like:
- The CS size is programmable from 256 MBytes to 16 MBytes (must be a power of
2)
and is defined by the mask field. Attached memory smaller than the programmed
CS region size is accessed through the entire CS region (aliasing).
- The programmed 'base-address' must be aligned to the 'CS-size' boundary and
be a power of 2.
- Valid CS-size values are {256MB(max), 128MB, 64MB, 32MB and 16MB (min)}
Any intermediate values creates holes in the chip-select memory-map.
This patch adds above checks in gpmc_cs_remap() so that any invalid value
passed by DT reg property can be filtered before actually allocating the
address space.
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/mach-omap2/gpmc.c | 42 +-
1 file changed, 29 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 8bc1338..4a4cc04 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -521,26 +521,42 @@ static int gpmc_cs_delete_mem(int cs)
* base. Returns 0 on success and appropriate negative error code
* on failure.
*/
-static int gpmc_cs_remap(int cs, u32 base)
+static int gpmc_cs_remap(int cs, u32 base, u32 size)
{
int ret;
- u32 old_base, size;
if (cs gpmc_cs_num) {
pr_err(%s: requested chip-select is disabled\n, __func__);
return -ENODEV;
}
- /*
-* Make sure we ignore any device offsets from the GPMC partition
-* allocated for the chip select and that the new base confirms
-* to the GPMC 16MB minimum granularity.
-*/
- base = ~(SZ_16M - 1);
-
- gpmc_cs_get_memconf(cs, old_base, size);
- if (base == old_base)
- return 0;
+ /* allocate enough address-space under GPMC chip-select to device */
+ if (size SZ_256M) {
+ pr_err(%s: memory device 256MB not supported\n, __func__);
+ return -ENODEV;
+ } else if (size SZ_128M) {
+ WARN((size != SZ_256M), cs=%d: allocating 256MB\n, cs);
+ size = SZ_256M;
+ } else if (size SZ_64M) {
+ WARN((size != SZ_128M), cs=%d: allocating 128MB\n, cs);
+ size = SZ_128M;
+ } else if (size SZ_32M) {
+ WARN((size != SZ_64M), cs=%d: allocating 64MB\n, cs);
+ size = SZ_64M;
+ } else if (size SZ_16M) {
+ WARN((size != SZ_32M), cs=%d: allocating 64MB\n, cs);
+ size = SZ_32M;
+ } else {
+ WARN((size != SZ_16M), cs=%d: allocating 64MB\n, cs);
+ size = SZ_16M;
+ }
+
+ /* base address should be aligned with address-space size */
+ if (base (size - 1)) {
+ pr_err(base-addr=%x should be aligned to size=%x, base, size);
+ return -EINVAL;
+ }
+
gpmc_cs_disable_mem(cs);
ret = gpmc_cs_delete_mem(cs);
if (ret 0)
@@ -1551,7 +1567,7 @@ static int gpmc_probe_generic_child(struct
platform_device *pdev,
* CS to this location. Once DT migration is complete should
* just make gpmc_cs_request() map a specific address.
*/
- ret = gpmc_cs_remap(cs, res.start);
+ ret = gpmc_cs_remap(cs, res.start, resource_size(res));
if (ret 0) {
dev_err(pdev-dev, cannot remap GPMC CS %d to %pa\n,
cs, res.start);
--
1.8.5.1.163.gd7aced9
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[PATCH v1 3/3] ARM: dts: am335x-bone: add support for beaglebone LCD4 cape
This patch adds support for LCD4 cape as advertised on
http://elinux.org/CircuitCo:BeagleBone_LCD4
This cape has:
* 480x272 TFT-LCD panel
- LCD panel datasheet and timing information are sourced from [1]
- LCD backlight is connected to 'EHRPWM1A' on cape board, but its used for
enabling backlight power-supply. So 'gpio-backlight' driver is used instead
of 'pwm-backlight' driver (Kconfig: BACKLIGHT_GPIO=y).
* 4-wire resistive Touchscreen
*Known constrains*
As LCD panel pins (lcd_data, hsync, vsync, pclk) are shared with on-board
NXP HDMI framer, so either HDMI or LCD-cape can be used at time. Thus while
using this cape 'hdmi' DT node needs to be disabled in am335x-boneblack.dts
[1] www.newhavendisplay.com/specs/NHD-4.3-480272MF-ATXI-T-1.pdf
www.newhavendisplay.com/app_notes/OTA5180A.pdf
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-bone-display-cape.dts | 104 +
arch/arm/boot/dts/am335x-bone.dts | 1 +
arch/arm/boot/dts/am335x-boneblack.dts | 1 +
3 files changed, 106 insertions(+)
create mode 100644 arch/arm/boot/dts/am335x-bone-display-cape.dts
diff --git a/arch/arm/boot/dts/am335x-bone-display-cape.dts
b/arch/arm/boot/dts/am335x-bone-display-cape.dts
new file mode 100644
index 000..f3b7cef
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone-display-cape.dts
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This DTS adds supports for display capes using LCD interface for display
+ * and GPIO or PWM interface for backlight controls.
+ */
+
+
+am33xx_pinmux {
+ bbcape_backlight_pins: bbcape_backlight_pins {
+ pinctrl-single,pins =
+ 0x48 (PIN_OUTPUT | MUX_MODE7) /*
gpmc_a[2].GPIO1[18] (backlight control) */
+ ;
+ };
+
+ bbcape_lcd_pins: bbcape_lcd_pins {
+ pinctrl-single,pins =
+ 0xa0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data0.lcd_data0 */
+ 0xa4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data1.lcd_data1 */
+ 0xa8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data2.lcd_data2 */
+ 0xac (PIN_OUTPUT | MUX_MODE0) /*
lcd_data3.lcd_data3 */
+ 0xb0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data4.lcd_data4 */
+ 0xb4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data5.lcd_data5 */
+ 0xb8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data6.lcd_data6 */
+ 0xbc (PIN_OUTPUT | MUX_MODE0) /*
lcd_data7.lcd_data7 */
+ 0xc0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data8.lcd_data8 */
+ 0xc4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data9.lcd_data9 */
+ 0xc8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data10.lcd_data10 */
+ 0xcc (PIN_OUTPUT | MUX_MODE0) /*
lcd_data11.lcd_data11 */
+ 0xd0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data12.lcd_data12 */
+ 0xd4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data13.lcd_data13 */
+ 0xd8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_data14.lcd_data14 */
+ 0xdc (PIN_OUTPUT | MUX_MODE0) /*
lcd_data15.lcd_data15 */
+ 0xe0 (PIN_OUTPUT | MUX_MODE0) /*
lcd_vsync.lcd_vsync */
+ 0xe4 (PIN_OUTPUT | MUX_MODE0) /*
lcd_hsync.lcd_hsync */
+ 0xe8 (PIN_OUTPUT | MUX_MODE0) /*
lcd_pclk.lcd_pclk */
+ 0xec (PIN_OUTPUT | MUX_MODE0) /*
lcd_ac_bias_en.lcd_ac_bias_en (lcd_en) */
+ 0x1a4 (PIN_OUTPUT_PULLUP | MUX_MODE7) /*
mcasp0_fsr.gpio3[19] (lcd_disen) */
+ ;
+ };
+
+ bbcape_touchscreen_pins: bbcape_touchscreen_pins {
+ pinctrl-single,pins =
+ 0x184 (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
uart1_txd.gpio0[15] (enter) */
+ 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
gpmc_a0.gpio1[16] (left) */
+ 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
gpmc_a1.gpio1[17] (right) */
+ 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
gpmc_a3.gpio1[19] (up) */
+ 0x198 (PIN_INPUT_PULLDOWN | MUX_MODE7) /*
mcasp0_axr0.gpio3[16] (down) */
+ ;
+ };
+};
+
+
+/ {
+ backlight {
+ status = disabled;
+ compatible = gpio-backlight;
+ pinctrl-names = default;
+ pinctrl-0 = bbcape_backlight_pins
[PATCH v1 1/3] ARM: dts: am335x-bone: add support for beaglebone NAND cape
Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
Further information and datasheets can be found at [1] and [2]
* How to boot from NAND using Memory Expander + NAND Cape ? *
- Important: As BOOTSEL values are sampled only at POR, so after changing any
setting on SW2 (DIP switch), disconnect and reconnect all board power supply
(including mini-USB console port) to POR the beaglebone.
- Selection of ECC scheme
for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
for NAND cape(b), ROM code expects BCH16_HW ecc-scheme
- Selection of boot modes can be controlled via DIP switch(SW2) present on
Memory Expander cape, so first boot via MMC or other sources to flash NAND
device and then switch to SW2[SWITCH_BOOT]=ON to boot from NAND Cape.
SW2[SWITCH_BOOT] == OFF follow default boot order MMC- SPI - UART - USB
SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2)
- For NAND boot following switch settings need to be followed
SW2[ 1] = ON (SYSBOOT[ 0]==0: NAND boot mode selected )
SW2[ 2] = ON (SYSBOOT[ 1]==0: -- do -- )
SW2[ 3] = OFF (SYSBOOT[ 2]==1: -- do -- )
SW2[ 4] = OFF (SYSBOOT[ 3]==1: -- do -- )
SW2[ 5] = ON (SYSBOOT[ 4]==0: -- do -- )
SW2[ 6] = OFF (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
SW2[ 7] = ON (SYSBOOT[ 9]==0: ECC done by ROM )
SW2[ 8] = ON (SYSBOOT[10]==0: Non Muxed device )
SW2[ 9] = ON (SYSBOOT[11]==0:-- do -- )
[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2]
http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org
---
arch/arm/boot/dts/am335x-bone-memory-cape.dts | 127 ++
arch/arm/boot/dts/am335x-bone.dts | 1 +
arch/arm/boot/dts/am335x-boneblack.dts| 1 +
3 files changed, 129 insertions(+)
create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts
diff --git a/arch/arm/boot/dts/am335x-bone-memory-cape.dts
b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
new file mode 100644
index 000..6d8ebd8
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This DTS adds supports for capes using GPMC interface to connect external
+ * memory like NAND, NOR Flash to Beaglebone-White and Beaglebone-Black.
+ */
+
+
+am33xx_pinmux {
+ bbcape_nand_flash_pins: bbcape_nand_flash_pins {
+ pinctrl-single,pins =
+ 0x00 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad0.gpmc_ad0 */
+ 0x04 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad1.gpmc_ad1 */
+ 0x08 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad2.gpmc_ad2 */
+ 0x0c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad3.gpmc_ad3 */
+ 0x10 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad4.gpmc_ad4 */
+ 0x14 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad5.gpmc_ad5 */
+ 0x18 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad6.gpmc_ad6 */
+ 0x1c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad7.gpmc_ad7 */
+ 0x20 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad8.gpmc_ad8 */
+ 0x24 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad9.gpmc_ad9 */
+ 0x28 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad10.gpmc_ad10
*/
+ 0x2c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad11.gpmc_ad11
*/
+ 0x30 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad12.gpmc_ad12
*/
+ 0x34 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad13.gpmc_ad13
*/
+ 0x38 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad14.gpmc_ad14
*/
+ 0x3c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad15.gpmc_ad15
*/
+ 0x70 (MUX_MODE0 | PIN_INPUT_PULLUP )/*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
gpmc_wpn.gpmc_wpn */
+ 0x7c (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (MUX_MODE0 | PIN_OUTPUT
[PATCH v1 0/3] ARM: dts: am335x-bone: Beaglebone cape DTS
This series adds DTS for following Beaglebone capes: Memory Cape: http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion NAND Cape: http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module NOR Cape: http://elinux.org/Beagleboardtoys:BeagleBone_128Mb_16-Bit_NOR_Module LCD4 Cape: http://elinux.org/CircuitCo:BeagleBone_LCD4 Based on Tree: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap omap-for-v3.16/dt-v2 Acceptance of cape DTS in mainline is still under discussion [1], so multiple 'Tested-by' would be helpful. Note: In order to avoid conflicts with existing DTS, device nodes added in these patches have status=disabled, and need to be enabled via u-boot. DT nodes can be selectively enabled | disabled via u-boot [2] Example: Below sequence works for NAND cape patch. --- /* load DTB */ u-boot tftp 0x8100 am335x-boneblack.dtb u-boot fdt addr 0x8100 /* disable MMC2 node */ u-boot fdt list /ocp/mmc@481d8000 u-boot fdt set /ocp/mmc@481d8000 status \d\i\s\a\b\l\e\d u-boot fdt list /ocp/mmc@481d8000 status /* enable GPMC node */ u-boot fdt list /ocp/gpmc u-boot fdt set /ocp/gpmc status \o\k\a\y u-boot fdt list /ocp/gpmc status /* enable ELM node */ u-boot fdt list /ocp/elm u-boot fdt set /ocp/elm status \o\k\a\y u-boot fdt list /ocp/elm status /* boot uImage */ tftp 0x8200 uImage bootm 0x8200 - 0x8100 Note: fdt set command does not accept string literals as binding values, it internally converts them to string, so escape sequenced characters were used here.. okay == \o\k\a\y disabled == \d\i\s\a\b\l\e\d --- [1] http://www.spinics.net/lists/linux-omap/msg108505.html [2] http://www.denx.de/wiki/view/DULG/UBootCmdFDT Pekon Gupta (3): ARM: dts: am335x-bone: add support for beaglebone NAND cape ARM: dts: am335x-bone: add support for beaglebone NOR cape ARM: dts: am335x-bone: add support for beaglebone LCD4 cape arch/arm/boot/dts/am335x-bone-display-cape.dts | 104 +++ arch/arm/boot/dts/am335x-bone-memory-cape.dts | 249 + arch/arm/boot/dts/am335x-bone.dts | 2 + arch/arm/boot/dts/am335x-boneblack.dts | 2 + 4 files changed, 357 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-bone-display-cape.dts create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v1 2/3] ARM: dts: am335x-bone: add support for beaglebone NOR cape
This patch adds support for 'NOR cape' having '128Mb 16-Bit' device connected to
GPMC chip-select [1]. Due to shared nature of GPMC pins exposed on BeagleBone
connector this cape cannot be simulataneously used with 'NAND cape'.
[1] http://elinux.org/Beagleboardtoys:BeagleBone_128Mb_16-Bit_NOR_Module
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-bone-memory-cape.dts | 124 +-
1 file changed, 123 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am335x-bone-memory-cape.dts
b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
index 6d8ebd8..72131f6 100644
--- a/arch/arm/boot/dts/am335x-bone-memory-cape.dts
+++ b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
@@ -38,11 +38,47 @@
0x9c (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_be0n_cle.gpmc_be0n_cle */
;
};
+
+ bbcape_nor_flash_pins: bbcape_nor_flash_pins {
+ pinctrl-single,pins =
+ 0x00 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad0.gpmc_ad0 */
+ 0x04 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad1.gpmc_ad1 */
+ 0x08 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad2.gpmc_ad2 */
+ 0x0c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad3.gpmc_ad3 */
+ 0x10 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad4.gpmc_ad4 */
+ 0x14 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad5.gpmc_ad5 */
+ 0x18 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad6.gpmc_ad6 */
+ 0x1c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad7.gpmc_ad7 */
+ 0x20 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad8.gpmc_ad8 */
+ 0x24 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad9.gpmc_ad9 */
+ 0x28 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad10.gpmc_ad10
*/
+ 0x2c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad11.gpmc_ad11
*/
+ 0x30 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad12.gpmc_ad12
*/
+ 0x34 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad13.gpmc_ad13
*/
+ 0x38 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad14.gpmc_ad14
*/
+ 0x3c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad15.gpmc_ad15
*/
+ 0x40 (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a0.gpmc_a0 */
+ 0x44 (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a1.gpmc_a1 */
+ 0x48 (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a2.gpmc_a2 */
+ 0x4c (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a3.gpmc_a3 */
+ 0x50 (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a4.gpmc_a4 */
+ 0x54 (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a5.gpmc_a5 */
+ 0x58 (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a6.gpmc_a6 */
+ 0x5c (MUX_MODE0 | PIN_OUTPUT) /* gpmc_a7.gpmc_a7 */
+ 0x70 (MUX_MODE0 | PIN_INPUT_PULLUP )/*
gpmc_wait0.gpmc_wait0 */
+ /* 0x74 (MUX_MODE0 | PIN_OUTPUT_PULLUP) */ /* gpmc_wpn
(not connected) */
+ 0x7c (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_wen.gpmc_wen */
+ 0x9c (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_be0n_cle.gpmc_be0n_cle */
+ ;
+ };
};
gpmc {
- ranges = 0 0 0 0x0100;/* address range = 16MB (minimum GPMC
partition) */
+ ranges = 0 0 0x0800 0x0100; /* address offset=128MB,
range=128Mb=16MB */
nand@0,0 {
status = disabled;
reg = 0 0 4; /* device IO registers */
@@ -124,4 +160,90 @@
reg = 0x00a0 0x1f60;
};
};
+
+ nor@0,0 {
+ status = disabled;
+ pinctrl-names = default;
+ pinctrl-0 = bbcape_nor_flash_pins;
+ compatible = cfi-flash;
+ reg = 0 0 0x0100; /* device memory map = actual
device size = 16MB */
+ /* generic bindings */
+ linux,mtd-name = Micron,M29W128G;
+ bank-width = 2;
+ /* vendor specific bindings */
+ gpmc,device-width = 2;
+ gpmc,mux-add-data = 2;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 120;
+ gpmc,cs-wr-off-ns = 120;
+ gpmc,adv-on-ns = 10;
+ gpmc,adv-rd-off-ns = 40;
+ gpmc,adv-wr-off-ns = 40;
+ gpmc,we-on-ns = 50;
+ gpmc,we-off-ns = 120;
+ gpmc,oe-on-ns = 50;
+ gpmc,oe-off-ns = 120;
+ gpmc,access-ns = 100
[PATCH v2] ARM: OMAP2+: gpmc: enable wait-pin monitoring for NAND devices via DT
This patch enables 'wait-pin' monitoring in NAND driver if following properties
are present under NAND DT node
gpmc,wait-pin = wait-pin number
gpmc,wait-on-read
gpmc,wait-on-write
As NAND generic framework uses common path nand_chip-dev_ready() for monitoring
completion of Read and Write status, so wait-pin monitoring is enabled only when
*both* 'gpmc,wait-on-read' and 'gpmc,wait-on-write' are specified.
CC: devicet...@vger.kernel.org
Signed-off-by: Pekon Gupta pe...@ti.com
---
Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 8
arch/arm/mach-omap2/gpmc-nand.c | 8 +---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index eb81435..4039032 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -45,6 +45,14 @@ Optional properties:
ELM hardware engines should specify this device node in .dtsi
Using ELM for ECC error correction frees some CPU cycles.
+ - gpmc,wait-pin=pin number Specifies GPMC wait-pin number to monitor
+ - gpmc,wait-on-read Enable wait-pin monitoring for Read accesses
+ - gpmc,wait-on-write Enable wait-pin monitoring for Write accesses
+ As NAND generic framework uses single common function
+ nand_chip-dev_ready() for polling wait-pin both for Read and
+ Write accesses. So for NAND devices both 'gpmc,wait-on-read' and
+ 'gpmc,wait-on-write' need to be specified together.
+
For inline partiton table parsing (optional):
- #address-cells: should be set to 1
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 17cd393..62bc3de 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -123,11 +123,13 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
}
}
- if (gpmc_nand_data-of_node)
+ if (gpmc_nand_data-of_node) {
gpmc_read_settings_dt(gpmc_nand_data-of_node, s);
- else
+ if (s.wait_on_read s.wait_on_write)
+ gpmc_nand_data-dev_ready = true;
+ } else {
gpmc_set_legacy(gpmc_nand_data, s);
-
+ }
s.device_nand = true;
err = gpmc_cs_program_settings(gpmc_nand_data-cs, s);
--
1.8.5.1.163.gd7aced9
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[PATCH v4 2/4] mtd: nand: omap: add support for BCH16_ECC - ELM driver updates
ELM hardware engine is used to detect ECC errors for BCHx ecc-schemes
(like BCH4/BCH8/BCH16). This patch extends configuration of ELM registers
for adding support of BCH16_HW ecc-scheme.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/devices/elm.c | 36
include/linux/platform_data/elm.h | 3 ++-
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/elm.c b/drivers/mtd/devices/elm.c
index 1fd4a0f..8c55e0d 100644
--- a/drivers/mtd/devices/elm.c
+++ b/drivers/mtd/devices/elm.c
@@ -213,6 +213,28 @@ static void elm_load_syndrome(struct elm_info *info,
val = cpu_to_be32(*(u32 *) ecc[0]) 12;
elm_write_reg(info, offset, val);
break;
+ case BCH16_ECC:
+ val = cpu_to_be32(*(u32 *) ecc[22]);
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = cpu_to_be32(*(u32 *) ecc[18]);
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = cpu_to_be32(*(u32 *) ecc[14]);
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = cpu_to_be32(*(u32 *) ecc[10]);
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = cpu_to_be32(*(u32 *) ecc[6]);
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = cpu_to_be32(*(u32 *) ecc[2]);
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = cpu_to_be32(*(u32 *) ecc[0]) 16;
+ elm_write_reg(info, offset, val);
+ break;
default:
pr_err(invalid config bch_type\n);
}
@@ -435,6 +457,13 @@ static int elm_context_save(struct elm_info *info)
for (i = 0; i ERROR_VECTOR_MAX; i++) {
offset = i * SYNDROME_FRAGMENT_REG_SIZE;
switch (bch_type) {
+ case BCH16_ECC:
+ regs-elm_syndrome_fragment_6[i] = elm_read_reg(info,
+ ELM_SYNDROME_FRAGMENT_6 + offset);
+ regs-elm_syndrome_fragment_5[i] = elm_read_reg(info,
+ ELM_SYNDROME_FRAGMENT_5 + offset);
+ regs-elm_syndrome_fragment_4[i] = elm_read_reg(info,
+ ELM_SYNDROME_FRAGMENT_4 + offset);
case BCH8_ECC:
regs-elm_syndrome_fragment_3[i] = elm_read_reg(info,
ELM_SYNDROME_FRAGMENT_3 + offset);
@@ -473,6 +502,13 @@ static int elm_context_restore(struct elm_info *info)
for (i = 0; i ERROR_VECTOR_MAX; i++) {
offset = i * SYNDROME_FRAGMENT_REG_SIZE;
switch (bch_type) {
+ case BCH16_ECC:
+ elm_write_reg(info, ELM_SYNDROME_FRAGMENT_6 + offset,
+ regs-elm_syndrome_fragment_6[i]);
+ elm_write_reg(info, ELM_SYNDROME_FRAGMENT_5 + offset,
+ regs-elm_syndrome_fragment_5[i]);
+ elm_write_reg(info, ELM_SYNDROME_FRAGMENT_4 + offset,
+ regs-elm_syndrome_fragment_4[i]);
case BCH8_ECC:
elm_write_reg(info, ELM_SYNDROME_FRAGMENT_3 + offset,
regs-elm_syndrome_fragment_3[i]);
diff --git a/include/linux/platform_data/elm.h
b/include/linux/platform_data/elm.h
index 4edb406..780d1e9 100644
--- a/include/linux/platform_data/elm.h
+++ b/include/linux/platform_data/elm.h
@@ -21,6 +21,7 @@
enum bch_ecc {
BCH4_ECC = 0,
BCH8_ECC,
+ BCH16_ECC,
};
/* ELM support 8 error syndrome process */
@@ -38,7 +39,7 @@ struct elm_errorvec {
bool error_reported;
bool error_uncorrectable;
int error_count;
- int error_loc[ERROR_VECTOR_MAX];
+ int error_loc[16];
};
void elm_decode_bch_error_page(struct device *dev, u8 *ecc_calc,
--
1.8.5.1.163.gd7aced9
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[PATCH v4 0/4] mtd: nand: omap: add support for BCH16_ECC
As this series touches both linux-mtd and linux-omap (GPMC) sub-systems but in independent patch-sets, so looping both maintainers. 'Ack' from maintainers would help in getting this series accepted for 3.16 *changes v3 - v4* [PATCH v4 1/4]: minor update in comments [PATCH v4 2/4]: fixed coding style to keep it generic for big/little endianess [PATCH v4 3/4]: no change [PATCH v4 4/4]: use plain english (non linux stuff) *changes v2 - v3* [PATCH v2 3/4] rebased to http://lists.infradead.org/pipermail/linux-mtd/2014-March/052655.html - no change in other patches *changes v1 - v2* rebased and cleaned on following versions of pending patches (1) [PATCH v8 0/6] mtd: nand: omap: optimized chip-ecc.correct() for H/W ECC schemes http://lists.infradead.org/pipermail/linux-mtd/2014-February/052092.html (2) [PATCH v6 0/4] mtd: nand: omap: optimize chip-ecc.calculate() for H/W ECC schemes http://lists.infradead.org/pipermail/linux-mtd/2014-February/052272.html (3) [PATCH v5 0/4] mtd: nand: omap: optimize chip-ecc.hwctl() for H/W ECC schemes http://lists.infradead.org/pipermail/linux-mtd/2014-March/052327.html (4) [PATCH v6 0/4] mtd: devices: elm: add checks ELM H/W constrains, driver code cleanup http://lists.infradead.org/pipermail/linux-mtd/2014-March/052455.html Tested on Beaglebone-LT(white) NAND cape having NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224 *original v1* http://lists.infradead.org/pipermail/linux-mtd/2013-July/047562.html With increase in NAND flash densities and shrinking of technology NAND flash has become more suspectible to multiple bit-flips. Thus stronger ECC schemes are required for detecting and correcting multiple simultaneous bit-flips in same NAND page. But stronger ECC schemes have large ECC syndrome which require more space in OOB/Spare. This patch add support for BCH16 ecc-scheme on OMAP NAND driver: (a) BCH16 ecc-scheme can correct 16 bit-flips per 512Bytes of data. (b) BCH16 ecc-scheme generates 26-bytes of ECC syndrome / 512B. Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy following equation: OOBsize per page = 26 * (page-size / 512) Pekon Gupta (4): mtd: nand: omap: add support for BCH16_ECC - GPMC driver updates mtd: nand: omap: add support for BCH16_ECC - ELM driver updates mtd: nand: omap: add support for BCH16_ECC - NAND driver updates mtd: nand: omap: Documentation: How to select correct ECC scheme for your device ? .../devicetree/bindings/mtd/gpmc-nand.txt | 45 +++ arch/arm/mach-omap2/gpmc.c | 15 drivers/mtd/devices/elm.c | 36 + drivers/mtd/nand/omap2.c | 94 ++ include/linux/platform_data/elm.h | 3 +- include/linux/platform_data/mtd-nand-omap2.h | 5 ++ 6 files changed, 197 insertions(+), 1 deletion(-) -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/4] mtd: nand: omap: add support for BCH16_ECC - GPMC driver updates
This patch add support for BCH16_ECC in GPMC (controller) driver:
- extends configuration space to include BCH16 registers
- extends parsing of DT binding for selecting BCH16 ecc-scheme
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/mach-omap2/gpmc.c | 15 +++
include/linux/platform_data/mtd-nand-omap2.h | 5 +
2 files changed, 20 insertions(+)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 9fe8c94..4fc4963 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -68,6 +68,9 @@
#defineGPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
#defineGPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
#defineGPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
+#defineGPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
+#defineGPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
+#defineGPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
/* GPMC ECC control settings */
#define GPMC_ECC_CTRL_ECCCLEAR 0x100
@@ -677,6 +680,12 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int
cs)
GPMC_BCH_SIZE * i;
reg-gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
GPMC_BCH_SIZE * i;
+ reg-gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
+ i * GPMC_BCH_SIZE;
+ reg-gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
+ i * GPMC_BCH_SIZE;
+ reg-gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
+ i * GPMC_BCH_SIZE;
}
}
@@ -1412,6 +1421,12 @@ static int gpmc_probe_nand_child(struct platform_device
*pdev,
else
gpmc_nand_data-ecc_opt =
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
+ else if (!strcmp(s, bch16))
+ if (gpmc_nand_data-elm_of_node)
+ gpmc_nand_data-ecc_opt =
+ OMAP_ECC_BCH16_CODE_HW;
+ else
+ pr_err(%s: BCH16 requires ELM support\n, __func__);
else
pr_err(%s: ti,nand-ecc-opt invalid value\n, __func__);
diff --git a/include/linux/platform_data/mtd-nand-omap2.h
b/include/linux/platform_data/mtd-nand-omap2.h
index 3e9dd66..660c029 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -31,6 +31,8 @@ enum omap_ecc {
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
/* 8-bit ECC calculation by GPMC, Error detection by ELM */
OMAP_ECC_BCH8_CODE_HW,
+ /* 16-bit ECC calculation by GPMC, Error detection by ELM */
+ OMAP_ECC_BCH16_CODE_HW,
};
struct gpmc_nand_regs {
@@ -50,6 +52,9 @@ struct gpmc_nand_regs {
void __iomem*gpmc_bch_result1[GPMC_BCH_NUM_REMAINDER];
void __iomem*gpmc_bch_result2[GPMC_BCH_NUM_REMAINDER];
void __iomem*gpmc_bch_result3[GPMC_BCH_NUM_REMAINDER];
+ void __iomem*gpmc_bch_result4[GPMC_BCH_NUM_REMAINDER];
+ void __iomem*gpmc_bch_result5[GPMC_BCH_NUM_REMAINDER];
+ void __iomem*gpmc_bch_result6[GPMC_BCH_NUM_REMAINDER];
};
struct omap_nand_platform_data {
--
1.8.5.1.163.gd7aced9
--
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[PATCH v4 3/4] mtd: nand: omap: add support for BCH16_ECC - NAND driver updates
This patch add support for BCH16 ecc-scheme in OMAP NAND driver, by extending
following functions:
- omap_enable_hwecc (nand_chip-ecc.hwctl): configure GPMC controller
- omap_calculate_ecc_bch (nand_chip-ecc.calculate): fetch ECC signature from
GPMC controller
- omap_elm_correct_data (nand_chip-ecc.correct): detect and correct ECC
errors using ELM
(a) BCH16 ecc-scheme can detect and correct 16 bit-flips per 512Bytes of data.
(b) BCH16 ecc-scheme generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy the relation: OOBsize per page = 26 * (page-size / 512)
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 94
1 file changed, 94 insertions(+)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 0a68508..e0a6c82 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -137,6 +137,10 @@
#define BADBLOCK_MARKER_LENGTH 2
#ifdef CONFIG_MTD_NAND_OMAP_BCH
+static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
+ 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
+ 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
+ 0x07, 0x0e};
static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
0xac, 0x6b, 0xff, 0x99, 0x7b};
static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
@@ -1114,6 +1118,19 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
mtd_info *mtd, int mode)
ecc_size1 = BCH_ECC_SIZE1;
}
break;
+ case OMAP_ECC_BCH16_CODE_HW:
+ bch_type = 0x2;
+ nsectors = chip-ecc.steps;
+ if (mode == NAND_ECC_READ) {
+ wr_mode = 0x01;
+ ecc_size0 = 52; /* ECC bits in nibbles per sector */
+ ecc_size1 = 0; /* non-ECC bits in nibbles per sector */
+ } else {
+ wr_mode = 0x01;
+ ecc_size0 = 0; /* extra bits in nibbles per sector */
+ ecc_size1 = 52; /* OOB bits in nibbles per sector */
+ }
+ break;
default:
return;
}
@@ -1162,6 +1179,7 @@ static int __maybe_unused omap_calculate_ecc_bch(struct
mtd_info *mtd,
struct gpmc_nand_regs *gpmc_regs = info-reg;
u8 *ecc_code;
unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
+ u32 val;
int i;
nsectors = ((readl(info-reg.gpmc_ecc_config) 4) 0x7) + 1;
@@ -1201,6 +1219,41 @@ static int __maybe_unused omap_calculate_ecc_bch(struct
mtd_info *mtd,
*ecc_code++ = ((bch_val1 4) 0xFF);
*ecc_code++ = ((bch_val1 0xF) 4);
break;
+ case OMAP_ECC_BCH16_CODE_HW:
+ val = readl(gpmc_regs-gpmc_bch_result6[i]);
+ ecc_code[0] = ((val 8) 0xFF);
+ ecc_code[1] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result5[i]);
+ ecc_code[2] = ((val 24) 0xFF);
+ ecc_code[3] = ((val 16) 0xFF);
+ ecc_code[4] = ((val 8) 0xFF);
+ ecc_code[5] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result4[i]);
+ ecc_code[6] = ((val 24) 0xFF);
+ ecc_code[7] = ((val 16) 0xFF);
+ ecc_code[8] = ((val 8) 0xFF);
+ ecc_code[9] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result3[i]);
+ ecc_code[10] = ((val 24) 0xFF);
+ ecc_code[11] = ((val 16) 0xFF);
+ ecc_code[12] = ((val 8) 0xFF);
+ ecc_code[13] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result2[i]);
+ ecc_code[14] = ((val 24) 0xFF);
+ ecc_code[15] = ((val 16) 0xFF);
+ ecc_code[16] = ((val 8) 0xFF);
+ ecc_code[17] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result1[i]);
+ ecc_code[18] = ((val 24) 0xFF);
+ ecc_code[19] = ((val 16) 0xFF);
+ ecc_code[20] = ((val 8) 0xFF);
+ ecc_code[21] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result0[i]);
+ ecc_code[22] = ((val 24) 0xFF);
+ ecc_code[23] = ((val 16) 0xFF);
+ ecc_code[24] = ((val 8) 0xFF
[PATCH v4 4/4] mtd: nand: omap: Documentation: How to select correct ECC scheme for your device ?
- Adds DT binding property for BCH16 ECC scheme - Adds describes on factors which determine choice of ECC scheme for particular device CC: devicet...@vger.kernel.org Signed-off-by: Pekon Gupta pe...@ti.com --- .../devicetree/bindings/mtd/gpmc-nand.txt | 45 ++ 1 file changed, 45 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt index 5e1f31b..eb81435 100644 --- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt @@ -28,6 +28,8 @@ Optional properties: ham1 1-bit Hamming ecc code bch4 4-bit BCH ecc code bch8 8-bit BCH ecc code + bch16 16-bit BCH ECC code + Refer below How to select correct ECC scheme for your device ? - ti,nand-xfer-type: A string setting the data transfer type. One of: @@ -90,3 +92,46 @@ Example for an AM33xx board: }; }; +How to select correct ECC scheme for your device ? +-- +Higher ECC scheme usually means better protection against bit-flips and +increased system lifetime. However, selection of ECC scheme is dependent +on various other factors also like; + +(1) support of built in hardware engines. + Some legacy OMAP SoC do not have ELM harware engine, so those SoC cannot + support ecc-schemes with hardware error-correction (BCHx_HW). However + such SoC can use ecc-schemes with software library for error-correction + (BCHx_HW_DETECTION_SW). The error correction capability with software + library remains equivalent to their hardware counter-part, but there is + slight CPU penalty when too many bit-flips are detected during reads. + +(2) Device parameters like OOBSIZE. + Other factor which governs the selection of ecc-scheme is oob-size. + Higher ECC schemes require more OOB/Spare area to store ECC syndrome, + so the device should have enough free bytes available its OOB/Spare + area to accomodate ECC for entire page. In general following expression + helps in determining if given device can accomodate ECC syndrome: + 2 + (PAGESIZE / 512) * ECC_BYTES = OOBSIZE + where + OOBSIZE number of bytes in OOB/spare area + PAGESIZEnumber of bytes in main-area of device page + ECC_BYTES number of ECC bytes generated to protect + 512 bytes of data, which is: + '3' for HAM1_xx ecc schemes + '7' for BCH4_xx ecc schemes + '14' for BCH8_xx ecc schemes + '26' for BCH16_xx ecc schemes + + Example(a): For a device with PAGESIZE = 2048 and OOBSIZE = 64 and + trying to use BCH16 (ECC_BYTES=26) ecc-scheme. + Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B + which is greater than capacity of NAND device (OOBSIZE=64) + Hence, BCH16 cannot be supported on given device. But it can + probably use lower ecc-schemes like BCH8. + + Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and + trying to use BCH16 (ECC_BYTES=26) ecc-scheme. + Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B + which can be accomodate in the OOB/Spare area of this device + (OOBSIZE=128). So this device can use BCH16 ecc-scheme. -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 2/4] ARM: dts: am437x-gp-evm: add support for parallel NAND flash
Adds pinmux and DT node for Micron (MT29F4G08AB) x8 NAND device present on
am437x-gp-evm board.
(1) As NAND Flash data lines are muxed with eMMC, Thus at a given time either
eMMC or NAND can be enabled. Selection between eMMC and NAND is controlled:
(a) By dynamically driving following GPIO pin from software
SPI2_CS0(GPIO) == 0 NAND is selected (default)
SPI2_CS0(GPIO) == 1 eMMC is selected
(b) By statically using Jumper (J89) on the board
(2) As NAND device connnected to this board has page-size=4K and oob-size=224,
So ROM code expects boot-loaders to be flashed in BCH16 ECC scheme for
NAND boot.
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org
---
arch/arm/boot/dts/am437x-gp-evm.dts | 108
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 30ace1b..f432685 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -150,6 +150,27 @@
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
;
};
+
+ nand_flash_x8: nand_flash_x8 {
+ pinctrl-single,pins =
+ 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /*
spi2_cs0.gpio/eMMCorNANDsel */
+ 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)/*
gpmc_wpn.gpmc_wpn */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_wen.gpmc_wen */
+ 0x9c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_be0n_cle.gpmc_be0n_cle */
+ ;
+ };
};
i2c0 {
@@ -246,3 +267,90 @@
phy_id = davinci_mdio, 0;
phy-mode = rgmii;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x8;
+ ranges = 0 0 0 0x0100;/* minimum GPMC partition = 16MB */
+ nand@0,0 {
+ reg = 0 0 4; /* device IO registers */
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 8;
+ gpmc,device-width = 1;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 25;
+ gpmc,adv-wr-off-ns = 25;
+ gpmc,we-on-ns = 0;
+ gpmc,we-off-ns = 20;
+ gpmc,oe-on-ns = 3;
+ gpmc,oe-off-ns = 30;
+ gpmc,access-ns = 30;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-pin = 0;
+ gpmc,wait-on-read;
+ gpmc,wait-on-write;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-access-ns = 40;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable. For
+* NAND flash this is equal to size of erase-block */
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ label = NAND.SPL;
+ reg = 0x 0x0004;
+ };
+ partition@1 {
+ label = NAND.SPL.backup1;
+ reg = 0x0004 0x0004;
+ };
+ partition@2 {
+ label = NAND.SPL.backup2;
+ reg = 0x0008 0x0004;
+ };
+ partition@3 {
+ label = NAND.SPL.backup3;
+ reg
[PATCH v7 1/4] ARM: dts: am335x-bone: add support for beaglebone NAND cape
Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
Further information and datasheets can be found at [1] and [2]
* How to boot from NAND using Memory Expander + NAND Cape ? *
- Important: As BOOTSEL values are sampled only at POR, so after changing any
setting on SW2 (DIP switch), disconnect and reconnect all board power supply
(including mini-USB console port) to POR the beaglebone.
- Selection of ECC scheme
for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
for NAND cape(b), ROM code expects BCH16_HW ecc-scheme
- Selection of boot modes can be controlled via DIP switch(SW2) present on
Memory Expander cape, so first boot via MMC or other sources to flash NAND
device and then switch to SW2[SWITCH_BOOT]=ON to boot from NAND Cape.
SW2[SWITCH_BOOT] == OFF follow default boot order MMC- SPI - UART - USB
SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2)
- For NAND boot following switch settings need to be followed
SW2[ 0] = ON (SYSBOOT[ 0]==0: NAND boot mode selected )
SW2[ 1] = ON (SYSBOOT[ 1]==0: -- do -- )
SW2[ 2] = OFF (SYSBOOT[ 2]==1: -- do -- )
SW2[ 3] = OFF (SYSBOOT[ 3]==1: -- do -- )
SW2[ 4] = ON (SYSBOOT[ 4]==0: -- do -- )
SW2[ 8] = OFF (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
SW2[ 9] = ON (SYSBOOT[ 9]==0: ECC done by ROM )
SW2[10] = ON (SYSBOOT[10]==0: Non Muxed device )
SW2[11] = ON (SYSBOOT[11]==0:-- do -- )
[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2]
http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org
---
arch/arm/boot/dts/am335x-bone-memory-cape.dts | 123 ++
arch/arm/boot/dts/am335x-bone.dts | 1 +
arch/arm/boot/dts/am335x-boneblack.dts| 1 +
3 files changed, 125 insertions(+)
create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts
diff --git a/arch/arm/boot/dts/am335x-bone-memory-cape.dts
b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
new file mode 100644
index 000..ce3f87d
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This DTS adds supports for capes using GPMC interface to connect external
+ * memory like NAND, NOR Flash to Beaglebone-LT (white) and Beaglebone-Black.
+ */
+
+
+am33xx_pinmux {
+ nand_flash_x16: nand_flash_x16 {
+ pinctrl-single,pins =
+ 0x00 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad0.gpmc_ad0 */
+ 0x04 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad1.gpmc_ad1 */
+ 0x08 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad2.gpmc_ad2 */
+ 0x0c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad3.gpmc_ad3 */
+ 0x10 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad4.gpmc_ad4 */
+ 0x14 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad5.gpmc_ad5 */
+ 0x18 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad6.gpmc_ad6 */
+ 0x1c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad7.gpmc_ad7 */
+ 0x20 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad8.gpmc_ad8 */
+ 0x24 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad9.gpmc_ad9 */
+ 0x28 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad10.gpmc_ad10
*/
+ 0x2c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad11.gpmc_ad11
*/
+ 0x30 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad12.gpmc_ad12
*/
+ 0x34 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad13.gpmc_ad13
*/
+ 0x38 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad14.gpmc_ad14
*/
+ 0x3c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad15.gpmc_ad15
*/
+ 0x70 (MUX_MODE0 | PIN_INPUT_PULLUP )/*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (MUX_MODE7 | PIN_OUTPUT_PULLUP)/*
gpmc_wpn.gpio0_30 */
+ 0x7c (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_wen.gpmc_wen
[PATCH v7 4/4] ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition
MTD NAND partition for file-system should start at offset=0xA0
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org
---
arch/arm/boot/dts/am43x-epos-evm.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 2a0fbbb..ad362c5 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -366,7 +366,7 @@
};
partition@9 {
label = NAND.file-system;
- reg = 0x0080 0x1F60;
+ reg = 0x00a0 0x1f60;
};
};
};
--
1.8.5.1.163.gd7aced9
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[PATCH v7 0/4] add parallel NAND support for TI's new OMAPx and AMxx platforms (Part-2)
*changes v6 - v7* fixed 'reg = cs offset 'size' property for NAND nodes *changes v5 - v6* - removed explicit disabling of GPMC and ELM in am335x-bone-memorycape.dts as both modules are already disabled by default in am33xx.dtsi - fixed comments for range and reg properties. keeping it consistent across platforms. - fixed reg size property. Using 'exact' register space as in hardware. - fixed DT properties for wait-pin monitoring. Added gpmc,wait-pin = - using lower-case letter for hex digits Rebased on git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap :omap-for-v3.16/dt *changes v4 - v5* use lower-case hexadecimal numbers add comments for using different memory sizes in range and reg properties fix 'reg size' property for GPMC and ELM nodes in dra7.dtsi *changes v3 - v4* fixed reg and range property for all GPMC DT nodes added fix for am335x-evm and am437x-epos-evm rebased on git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap +omap-for-v3.16/dt *changes v2 - v3* rebased on git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap :master merged leftover patches (dra7-evm and am43x-epos-evm fix) from Part-1 series *changes v1 - v2* [PATCH v2 1/2] created new DTS for memory-capes based on following feedbacks http://www.spinics.net/lists/linux-omap/msg104348.html from 'Nishanth Menon n...@ti.com' http://www.spinics.net/lists/linux-omap/msg104447.html from 'Tony Lindgren t...@atomide.com' [PATCH v2 2/2] same as [PATCH v1 1/3] *original v1* This patch-set adds parallel NAND support on following TI platforms - AM335x (am335x-bone LT, am335x-boneblack): disabled by default - AM43xx (am437x-gp-evm) Minal Shah (1): ARM: dts: dra7: add support for parallel NAND flash Pekon Gupta (3): ARM: dts: am335x-bone: add support for beaglebone NAND cape ARM: dts: am437x-gp-evm: add support for parallel NAND flash ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition arch/arm/boot/dts/am335x-bone-memory-cape.dts | 123 ++ arch/arm/boot/dts/am335x-bone.dts | 1 + arch/arm/boot/dts/am335x-boneblack.dts| 1 + arch/arm/boot/dts/am437x-gp-evm.dts | 108 ++ arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- arch/arm/boot/dts/dra7-evm.dts| 118 arch/arm/boot/dts/dra7.dtsi | 20 + 7 files changed, 372 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 3/4] ARM: dts: dra7: add support for parallel NAND flash
From: Minal Shah minalks...@gmail.com
DRA7xx platform has in-build GPMC and ELM h/w engines which can be used
for accessing externel NAND flash device. This patch:
- adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines
- adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm
*Important*
On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch
So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH
Signed-off-by: Minal Shah minalks...@gmail.com
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org
---
arch/arm/boot/dts/dra7-evm.dts | 118 +
arch/arm/boot/dts/dra7.dtsi| 20 +++
2 files changed, 138 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index ec77907..4adc280 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -120,6 +120,37 @@
0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
;
};
+
+ nand_flash_x16: nand_flash_x16 {
+ /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
+* So NAND flash requires following switch settings:
+* SW5.9 (GPMC_WPN) = LOW
+* SW5.1 (NAND_BOOTn) = HIGH */
+ pinctrl-single,pins =
+ 0x0 (PIN_INPUT | MUX_MODE0)/* gpmc_ad0
*/
+ 0x4 (PIN_INPUT | MUX_MODE0)/* gpmc_ad1
*/
+ 0x8 (PIN_INPUT | MUX_MODE0)/* gpmc_ad2
*/
+ 0xc (PIN_INPUT | MUX_MODE0)/* gpmc_ad3
*/
+ 0x10(PIN_INPUT | MUX_MODE0)/* gpmc_ad4
*/
+ 0x14(PIN_INPUT | MUX_MODE0)/* gpmc_ad5
*/
+ 0x18(PIN_INPUT | MUX_MODE0)/* gpmc_ad6
*/
+ 0x1c(PIN_INPUT | MUX_MODE0)/* gpmc_ad7
*/
+ 0x20(PIN_INPUT | MUX_MODE0)/* gpmc_ad8
*/
+ 0x24(PIN_INPUT | MUX_MODE0)/* gpmc_ad9
*/
+ 0x28(PIN_INPUT | MUX_MODE0)/* gpmc_ad10
*/
+ 0x2c(PIN_INPUT | MUX_MODE0)/* gpmc_ad11
*/
+ 0x30(PIN_INPUT | MUX_MODE0)/* gpmc_ad12
*/
+ 0x34(PIN_INPUT | MUX_MODE0)/* gpmc_ad13
*/
+ 0x38(PIN_INPUT | MUX_MODE0)/* gpmc_ad14
*/
+ 0x3c(PIN_INPUT | MUX_MODE0)/* gpmc_ad15
*/
+ 0xd8(PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0
*/
+ 0xcc(PIN_OUTPUT | MUX_MODE0)/* gpmc_wen
*/
+ 0xb4(PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0
*/
+ 0xc4(PIN_OUTPUT | MUX_MODE0)/*
gpmc_advn_ale */
+ 0xc8(PIN_OUTPUT | MUX_MODE0)/* gpmc_oen_ren
*/
+ 0xd0(PIN_OUTPUT | MUX_MODE0)/*
gpmc_be0n_cle */
+ ;
+ };
};
i2c1 {
@@ -377,3 +408,90 @@
pinctrl-names = default;
pinctrl-0 = usb2_pins;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x16;
+ ranges = 0 0 0 0x0100;/* minimum GPMC partition = 16MB */
+ nand@0,0 {
+ reg = 0 0 4; /* device IO registers */
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 16;
+ gpmc,device-width = 2;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 30;
+ gpmc,adv-wr-off-ns = 30;
+ gpmc,we-on-ns = 5;
+ gpmc,we-off-ns = 25;
+ gpmc,oe-on-ns = 2;
+ gpmc,oe-off-ns = 20;
+ gpmc,access-ns = 20;
+ gpmc,wr-access-ns = 40;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-pin = 0;
+ gpmc,wait-on-read;
+ gpmc,wait-on-write;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable
[PATCH] ARM: OMAP2+: gpmc: enable BCH_HW ecc-scheme for AM43xx platforms
Fixes: commit 0611c41934ab35ce84dea34ab291897ad3cbc7be
ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms and ECC
schemes
Though the commit log of above commit mentions AM43xx platforms, but code change
missed AM43xx. This patch adds AM43xx to list of those SoC which have built-in
ELM hardware engine, so that BCH ecc-schemes with hardware error-correction can
be enabled on AM43xx devices.
Reported-by: Roger Quadros rog...@ti.com
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/mach-omap2/gpmc-nand.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 4349e82..17cd393 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -46,7 +46,7 @@ static struct platform_device gpmc_nand_device = {
static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
{
/* platforms which support all ECC schemes */
- if (soc_is_am33xx() || cpu_is_omap44xx() ||
+ if (soc_is_am33xx() || soc_is_am43xx() || cpu_is_omap44xx() ||
soc_is_omap54xx() || soc_is_dra7xx())
return 1;
--
1.8.5.1.163.gd7aced9
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[PATCH v6 0/4] add parallel NAND support for TI's new OMAPx and AMxx platforms (Part-2)
*changes v5 - v6* - removed explicit disabling of GPMC and ELM in am335x-bone-memorycape.dts as both modules are already disabled by default in am33xx.dtsi - fixed comments for range and reg properties. keeping it consistent across platforms. - fixed reg size property. Using 'exact' register space as in hardware. - fixed DT properties for wait-pin monitoring. Added gpmc,wait-pin = - using lower-case letter for hex digits Rebased on git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap :omap-for-v3.16/dt *changes v4 - v5* use lower-case hexadecimal numbers add comments for using different memory sizes in range and reg properties fix 'reg size' property for GPMC and ELM nodes in dra7.dtsi *changes v3 - v4* fixed reg and range property for all GPMC DT nodes added fix for am335x-evm and am437x-epos-evm rebased on git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap +omap-for-v3.16/dt *changes v2 - v3* rebased on git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap :master merged leftover patches (dra7-evm and am43x-epos-evm fix) from Part-1 series *changes v1 - v2* [PATCH v2 1/2] created new DTS for memory-capes based on following feedbacks http://www.spinics.net/lists/linux-omap/msg104348.html from 'Nishanth Menon n...@ti.com' http://www.spinics.net/lists/linux-omap/msg104447.html from 'Tony Lindgren t...@atomide.com' [PATCH v2 2/2] same as [PATCH v1 1/3] *original v1* This patch-set adds parallel NAND support on following TI platforms - AM335x (am335x-bone LT, am335x-boneblack): disabled by default - AM43xx (am437x-gp-evm) Minal Shah (1): ARM: dts: dra7: add support for parallel NAND flash Pekon Gupta (3): ARM: dts: am335x-bone: add support for beaglebone NAND cape ARM: dts: am437x-gp-evm: add support for parallel NAND flash ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition arch/arm/boot/dts/am335x-bone-memory-cape.dts | 123 ++ arch/arm/boot/dts/am335x-bone.dts | 1 + arch/arm/boot/dts/am335x-boneblack.dts| 1 + arch/arm/boot/dts/am437x-gp-evm.dts | 108 ++ arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- arch/arm/boot/dts/dra7-evm.dts| 118 arch/arm/boot/dts/dra7.dtsi | 20 + 7 files changed, 372 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 4/4] ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition
MTD NAND partition for file-system should start at offset=0xA0
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org
---
arch/arm/boot/dts/am43x-epos-evm.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 2a0fbbb..ad362c5 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -366,7 +366,7 @@
};
partition@9 {
label = NAND.file-system;
- reg = 0x0080 0x1F60;
+ reg = 0x00a0 0x1f60;
};
};
};
--
1.8.5.1.163.gd7aced9
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[PATCH v6 2/4] ARM: dts: am437x-gp-evm: add support for parallel NAND flash
Adds pinmux and DT node for Micron (MT29F4G08AB) x8 NAND device present on
am437x-gp-evm board.
(1) As NAND Flash data lines are muxed with eMMC, Thus at a given time either
eMMC or NAND can be enabled. Selection between eMMC and NAND is controlled:
(a) By dynamically driving following GPIO pin from software
SPI2_CS0(GPIO) == 0 NAND is selected (default)
SPI2_CS0(GPIO) == 1 eMMC is selected
(b) By statically using Jumper (J89) on the board
(2) As NAND device connnected to this board has page-size=4K and oob-size=224,
So ROM code expects boot-loaders to be flashed in BCH16 ECC scheme for
NAND boot.
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org
---
arch/arm/boot/dts/am437x-gp-evm.dts | 108
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 30ace1b..97b71e6 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -150,6 +150,27 @@
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
;
};
+
+ nand_flash_x8: nand_flash_x8 {
+ pinctrl-single,pins =
+ 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /*
spi2_cs0.gpio/eMMCorNANDsel */
+ 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)/*
gpmc_wpn.gpmc_wpn */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_wen.gpmc_wen */
+ 0x9c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_be0n_cle.gpmc_be0n_cle */
+ ;
+ };
};
i2c0 {
@@ -246,3 +267,90 @@
phy_id = davinci_mdio, 0;
phy-mode = rgmii;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x8;
+ ranges = 0 0 0 0x0100;/* minimum GPMC partition = 16MB */
+ nand@0,0 {
+ reg = 0 0 0x37c; /* device IO registers */
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 8;
+ gpmc,device-width = 1;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 25;
+ gpmc,adv-wr-off-ns = 25;
+ gpmc,we-on-ns = 0;
+ gpmc,we-off-ns = 20;
+ gpmc,oe-on-ns = 3;
+ gpmc,oe-off-ns = 30;
+ gpmc,access-ns = 30;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-pin = 0;
+ gpmc,wait-on-read;
+ gpmc,wait-on-write;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-access-ns = 40;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable. For
+* NAND flash this is equal to size of erase-block */
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ label = NAND.SPL;
+ reg = 0x 0x0004;
+ };
+ partition@1 {
+ label = NAND.SPL.backup1;
+ reg = 0x0004 0x0004;
+ };
+ partition@2 {
+ label = NAND.SPL.backup2;
+ reg = 0x0008 0x0004;
+ };
+ partition@3 {
+ label = NAND.SPL.backup3;
+ reg
[PATCH v6 1/4] ARM: dts: am335x-bone: add support for beaglebone NAND cape
Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
Further information and datasheets can be found at [1] and [2]
* How to boot from NAND using Memory Expander + NAND Cape ? *
- Important: As BOOTSEL values are sampled only at POR, so after changing any
setting on SW2 (DIP switch), disconnect and reconnect all board power supply
(including mini-USB console port) to POR the beaglebone.
- Selection of ECC scheme
for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
for NAND cape(b), ROM code expects BCH16_HW ecc-scheme
- Selection of boot modes can be controlled via DIP switch(SW2) present on
Memory Expander cape, so first boot via MMC or other sources to flash NAND
device and then switch to SW2[SWITCH_BOOT]=ON to boot from NAND Cape.
SW2[SWITCH_BOOT] == OFF follow default boot order MMC- SPI - UART - USB
SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2)
- For NAND boot following switch settings need to be followed
SW2[ 0] = ON (SYSBOOT[ 0]==0: NAND boot mode selected )
SW2[ 1] = ON (SYSBOOT[ 1]==0: -- do -- )
SW2[ 2] = OFF (SYSBOOT[ 2]==1: -- do -- )
SW2[ 3] = OFF (SYSBOOT[ 3]==1: -- do -- )
SW2[ 4] = ON (SYSBOOT[ 4]==0: -- do -- )
SW2[ 8] = OFF (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
SW2[ 9] = ON (SYSBOOT[ 9]==0: ECC done by ROM )
SW2[10] = ON (SYSBOOT[10]==0: Non Muxed device )
SW2[11] = ON (SYSBOOT[11]==0:-- do -- )
[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2]
http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org
---
arch/arm/boot/dts/am335x-bone-memory-cape.dts | 123 ++
arch/arm/boot/dts/am335x-bone.dts | 1 +
arch/arm/boot/dts/am335x-boneblack.dts| 1 +
3 files changed, 125 insertions(+)
create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts
diff --git a/arch/arm/boot/dts/am335x-bone-memory-cape.dts
b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
new file mode 100644
index 000..f9940bc
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This DTS adds supports for capes using GPMC interface to connect external
+ * memory like NAND, NOR Flash to Beaglebone-LT (white) and Beaglebone-Black.
+ */
+
+
+am33xx_pinmux {
+ nand_flash_x16: nand_flash_x16 {
+ pinctrl-single,pins =
+ 0x00 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad0.gpmc_ad0 */
+ 0x04 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad1.gpmc_ad1 */
+ 0x08 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad2.gpmc_ad2 */
+ 0x0c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad3.gpmc_ad3 */
+ 0x10 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad4.gpmc_ad4 */
+ 0x14 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad5.gpmc_ad5 */
+ 0x18 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad6.gpmc_ad6 */
+ 0x1c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad7.gpmc_ad7 */
+ 0x20 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad8.gpmc_ad8 */
+ 0x24 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad9.gpmc_ad9 */
+ 0x28 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad10.gpmc_ad10
*/
+ 0x2c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad11.gpmc_ad11
*/
+ 0x30 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad12.gpmc_ad12
*/
+ 0x34 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad13.gpmc_ad13
*/
+ 0x38 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad14.gpmc_ad14
*/
+ 0x3c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad15.gpmc_ad15
*/
+ 0x70 (MUX_MODE0 | PIN_INPUT_PULLUP )/*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (MUX_MODE7 | PIN_OUTPUT_PULLUP)/*
gpmc_wpn.gpio0_30 */
+ 0x7c (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_wen.gpmc_wen
[PATCH v6 3/4] ARM: dts: dra7: add support for parallel NAND flash
From: Minal Shah minalks...@gmail.com
DRA7xx platform has in-build GPMC and ELM h/w engines which can be used
for accessing externel NAND flash device. This patch:
- adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines
- adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm
*Important*
On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch
So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH
Signed-off-by: Minal Shah minalks...@gmail.com
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org
---
arch/arm/boot/dts/dra7-evm.dts | 118 +
arch/arm/boot/dts/dra7.dtsi| 20 +++
2 files changed, 138 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index ec77907..e624c17 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -120,6 +120,37 @@
0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
;
};
+
+ nand_flash_x16: nand_flash_x16 {
+ /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
+* So NAND flash requires following switch settings:
+* SW5.9 (GPMC_WPN) = LOW
+* SW5.1 (NAND_BOOTn) = HIGH */
+ pinctrl-single,pins =
+ 0x0 (PIN_INPUT | MUX_MODE0)/* gpmc_ad0
*/
+ 0x4 (PIN_INPUT | MUX_MODE0)/* gpmc_ad1
*/
+ 0x8 (PIN_INPUT | MUX_MODE0)/* gpmc_ad2
*/
+ 0xc (PIN_INPUT | MUX_MODE0)/* gpmc_ad3
*/
+ 0x10(PIN_INPUT | MUX_MODE0)/* gpmc_ad4
*/
+ 0x14(PIN_INPUT | MUX_MODE0)/* gpmc_ad5
*/
+ 0x18(PIN_INPUT | MUX_MODE0)/* gpmc_ad6
*/
+ 0x1c(PIN_INPUT | MUX_MODE0)/* gpmc_ad7
*/
+ 0x20(PIN_INPUT | MUX_MODE0)/* gpmc_ad8
*/
+ 0x24(PIN_INPUT | MUX_MODE0)/* gpmc_ad9
*/
+ 0x28(PIN_INPUT | MUX_MODE0)/* gpmc_ad10
*/
+ 0x2c(PIN_INPUT | MUX_MODE0)/* gpmc_ad11
*/
+ 0x30(PIN_INPUT | MUX_MODE0)/* gpmc_ad12
*/
+ 0x34(PIN_INPUT | MUX_MODE0)/* gpmc_ad13
*/
+ 0x38(PIN_INPUT | MUX_MODE0)/* gpmc_ad14
*/
+ 0x3c(PIN_INPUT | MUX_MODE0)/* gpmc_ad15
*/
+ 0xd8(PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0
*/
+ 0xcc(PIN_OUTPUT | MUX_MODE0)/* gpmc_wen
*/
+ 0xb4(PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0
*/
+ 0xc4(PIN_OUTPUT | MUX_MODE0)/*
gpmc_advn_ale */
+ 0xc8(PIN_OUTPUT | MUX_MODE0)/* gpmc_oen_ren
*/
+ 0xd0(PIN_OUTPUT | MUX_MODE0)/*
gpmc_be0n_cle */
+ ;
+ };
};
i2c1 {
@@ -377,3 +408,90 @@
pinctrl-names = default;
pinctrl-0 = usb2_pins;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x16;
+ ranges = 0 0 0 0x0100;/* minimum GPMC partition = 16MB */
+ nand@0,0 {
+ reg = 0 0 0x37c; /* device IO registers */
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 16;
+ gpmc,device-width = 2;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 30;
+ gpmc,adv-wr-off-ns = 30;
+ gpmc,we-on-ns = 5;
+ gpmc,we-off-ns = 25;
+ gpmc,oe-on-ns = 2;
+ gpmc,oe-off-ns = 20;
+ gpmc,access-ns = 20;
+ gpmc,wr-access-ns = 40;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-pin = 0;
+ gpmc,wait-on-read;
+ gpmc,wait-on-write;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable
[PATCH v5 1/4] ARM: dts: am335x-bone: add support for beaglebone NAND cape
Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
Further information and datasheets can be found at [1] and [2]
* How to boot from NAND using Memory Expander + NAND Cape ? *
- Important: As BOOTSEL values are sampled only at POR, so after changing any
setting on SW2 (DIP switch), disconnect and reconnect all board power supply
(including mini-USB console port) to POR the beaglebone.
- Selection of ECC scheme
for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
for NAND cape(b), ROM code expects BCH16_HW ecc-scheme
- Selection of boot modes can be controlled via DIP switch(SW2) present on
Memory Expander cape, so first boot via MMC or other sources to flash NAND
device and then switch to SW2[SWITCH_BOOT]=ON to boot from NAND Cape.
SW2[SWITCH_BOOT] == OFF follow default boot order MMC- SPI - UART - USB
SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2)
- For NAND boot following switch settings need to be followed
SW2[ 0] = ON (SYSBOOT[ 0]==0: NAND boot mode selected )
SW2[ 1] = ON (SYSBOOT[ 1]==0: -- do -- )
SW2[ 2] = OFF (SYSBOOT[ 2]==1: -- do -- )
SW2[ 3] = OFF (SYSBOOT[ 3]==1: -- do -- )
SW2[ 4] = ON (SYSBOOT[ 4]==0: -- do -- )
SW2[ 8] = OFF (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
SW2[ 9] = ON (SYSBOOT[ 9]==0: ECC done by ROM )
SW2[10] = ON (SYSBOOT[10]==0: Non Muxed device )
SW2[11] = ON (SYSBOOT[11]==0:-- do -- )
[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2]
http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-bone-memory-cape.dts | 130 ++
arch/arm/boot/dts/am335x-bone.dts | 1 +
arch/arm/boot/dts/am335x-boneblack.dts| 1 +
3 files changed, 132 insertions(+)
create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts
diff --git a/arch/arm/boot/dts/am335x-bone-memory-cape.dts
b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
new file mode 100644
index 000..d6cb9ff
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This DTS adds supports for capes using GPMC interface to connect external
+ * memory like NAND, NOR Flash to Beaglebone-LT (white) and Beaglebone-Black.
+ */
+
+
+am33xx_pinmux {
+ nand_flash_x16: nand_flash_x16 {
+ pinctrl-single,pins =
+ 0x00 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad0.gpmc_ad0 */
+ 0x04 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad1.gpmc_ad1 */
+ 0x08 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad2.gpmc_ad2 */
+ 0x0c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad3.gpmc_ad3 */
+ 0x10 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad4.gpmc_ad4 */
+ 0x14 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad5.gpmc_ad5 */
+ 0x18 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad6.gpmc_ad6 */
+ 0x1c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad7.gpmc_ad7 */
+ 0x20 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad8.gpmc_ad8 */
+ 0x24 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad9.gpmc_ad9 */
+ 0x28 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad10.gpmc_ad10
*/
+ 0x2c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad11.gpmc_ad11
*/
+ 0x30 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad12.gpmc_ad12
*/
+ 0x34 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad13.gpmc_ad13
*/
+ 0x38 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad14.gpmc_ad14
*/
+ 0x3c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad15.gpmc_ad15
*/
+ 0x70 (MUX_MODE0 | PIN_INPUT_PULLUP )/*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (MUX_MODE7 | PIN_OUTPUT_PULLUP)/*
gpmc_wpn.gpio0_30 */
+ 0x7c (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_wen.gpmc_wen */
+ 0x9c (MUX_MODE0 | PIN_OUTPUT
[PATCH v5 0/4] add parallel NAND support for TI's new OMAPx and AMxx platforms (Part-2)
*changes v4 - v5* use lower-case hexadecimal numbers add comments for using different memory sizes in range and reg properties fix 'reg size' property for GPMC and ELM nodes in dra7.dtsi *changes v3 - v4* fixed reg and range property for all GPMC DT nodes added fix for am335x-evm and am437x-epos-evm rebased on git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap +omap-for-v3.16/dt *changes v2 - v3* rebased on git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap :master merged leftover patches (dra7-evm and am43x-epos-evm fix) from Part-1 series *changes v1 - v2* [PATCH v2 1/2] created new DTS for memory-capes based on following feedbacks http://www.spinics.net/lists/linux-omap/msg104348.html from 'Nishanth Menon n...@ti.com' http://www.spinics.net/lists/linux-omap/msg104447.html from 'Tony Lindgren t...@atomide.com' [PATCH v2 2/2] same as [PATCH v1 1/3] *original v1* This patch-set adds parallel NAND support on following TI platforms - AM335x (am335x-bone LT, am335x-boneblack): disabled by default - AM43xx (am437x-gp-evm) Minal Shah (1): ARM: dts: dra7: add support for parallel NAND flash Pekon Gupta (3): ARM: dts: am335x-bone: add support for beaglebone NAND cape ARM: dts: am437x-gp-evm: add support for parallel NAND flash ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition arch/arm/boot/dts/am335x-bone-memory-cape.dts | 130 ++ arch/arm/boot/dts/am335x-bone.dts | 1 + arch/arm/boot/dts/am335x-boneblack.dts| 1 + arch/arm/boot/dts/am437x-gp-evm.dts | 107 + arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- arch/arm/boot/dts/dra7-evm.dts| 117 +++ arch/arm/boot/dts/dra7.dtsi | 20 7 files changed, 377 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 4/4] ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition
MTD NAND partition for file-system should start at offset=0xA0
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index cf8bdf1..9f6a176 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -360,7 +360,7 @@
};
partition@9 {
label = NAND.file-system;
- reg = 0x0080 0x1F60;
+ reg = 0x00a0 0x1f60;
};
};
};
--
1.8.5.1.163.gd7aced9
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 2/4] ARM: dts: am437x-gp-evm: add support for parallel NAND flash
Adds pinmux and DT node for Micron (MT29F4G08AB) x8 NAND device present on
am437x-gp-evm board.
(1) As NAND Flash data lines are muxed with eMMC, Thus at a given time either
eMMC or NAND can be enabled. Selection between eMMC and NAND is controlled:
(a) By dynamically driving following GPIO pin from software
SPI2_CS0(GPIO) == 0 NAND is selected (default)
SPI2_CS0(GPIO) == 1 eMMC is selected
(b) By statically using Jumper (J89) on the board
(2) As NAND device connnected to this board has page-size=4K and oob-size=224,
So ROM code expects boot-loaders to be flashed in BCH16 ECC scheme for
NAND boot.
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 107
1 file changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 2e0c636..bd7ca86 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -98,6 +98,27 @@
0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /*
spi2_d0.gpio3_22 */
;
};
+
+ nand_flash_x8: nand_flash_x8 {
+ pinctrl-single,pins =
+ 0x26C(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /*
spi2_cs0.gpio/eMMCorNANDsel */
+ 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)/*
gpmc_wpn.gpmc_wpn */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_wen.gpmc_wen */
+ 0x9c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_be0n_cle.gpmc_be0n_cle */
+ ;
+ };
};
i2c0 {
@@ -174,3 +195,89 @@
dr_mode = host;
status = okay;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x8;
+ ranges = 0 0 0 0x0100;/* CS0: min address-space configurable
under GPMC chip-select = 16MB */
+ nand@0,0 {
+ reg = 0 0 0x380; /* CS0, offset=0, GPMC register-space
size=0x380 */
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 8;
+ gpmc,device-width = 1;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 25;
+ gpmc,adv-wr-off-ns = 25;
+ gpmc,we-on-ns = 0;
+ gpmc,we-off-ns = 20;
+ gpmc,oe-on-ns = 3;
+ gpmc,oe-off-ns = 30;
+ gpmc,access-ns = 30;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-on-read = true;
+ gpmc,wait-on-write = true;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-access-ns = 40;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable. For
+* NAND flash this is equal to size of erase-block */
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ label = NAND.SPL;
+ reg = 0x 0x0004;
+ };
+ partition@1 {
+ label = NAND.SPL.backup1;
+ reg = 0x0004 0x0004;
+ };
+ partition@2 {
+ label = NAND.SPL.backup2;
+ reg = 0x0008 0x0004;
+ };
+ partition@3 {
+ label = NAND.SPL.backup3;
+ reg = 0x000c
[PATCH v5 3/4] ARM: dts: dra7: add support for parallel NAND flash
From: Minal Shah minalks...@gmail.com
DRA7xx platform has in-build GPMC and ELM h/w engines which can be used
for accessing externel NAND flash device. This patch:
- adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines
- adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm
*Important*
On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch
So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH
Signed-off-by: Minal Shah minalks...@gmail.com
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 117 +
arch/arm/boot/dts/dra7.dtsi| 20 +++
2 files changed, 137 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5f1f6da..c86755d 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -108,6 +108,37 @@
0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs3.qspi1_cs1 */
;
};
+
+ nand_flash_x16: nand_flash_x16 {
+ /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
+* So NAND flash requires following switch settings:
+* SW5.9 (GPMC_WPN) = LOW
+* SW5.1 (NAND_BOOTn) = HIGH */
+ pinctrl-single,pins =
+ 0x0 (PIN_INPUT | MUX_MODE0)/* gpmc_ad0
*/
+ 0x4 (PIN_INPUT | MUX_MODE0)/* gpmc_ad1
*/
+ 0x8 (PIN_INPUT | MUX_MODE0)/* gpmc_ad2
*/
+ 0xc (PIN_INPUT | MUX_MODE0)/* gpmc_ad3
*/
+ 0x10(PIN_INPUT | MUX_MODE0)/* gpmc_ad4
*/
+ 0x14(PIN_INPUT | MUX_MODE0)/* gpmc_ad5
*/
+ 0x18(PIN_INPUT | MUX_MODE0)/* gpmc_ad6
*/
+ 0x1c(PIN_INPUT | MUX_MODE0)/* gpmc_ad7
*/
+ 0x20(PIN_INPUT | MUX_MODE0)/* gpmc_ad8
*/
+ 0x24(PIN_INPUT | MUX_MODE0)/* gpmc_ad9
*/
+ 0x28(PIN_INPUT | MUX_MODE0)/* gpmc_ad10
*/
+ 0x2C(PIN_INPUT | MUX_MODE0)/* gpmc_ad11
*/
+ 0x30(PIN_INPUT | MUX_MODE0)/* gpmc_ad12
*/
+ 0x34(PIN_INPUT | MUX_MODE0)/* gpmc_ad13
*/
+ 0x38(PIN_INPUT | MUX_MODE0)/* gpmc_ad14
*/
+ 0x3C(PIN_INPUT | MUX_MODE0)/* gpmc_ad15
*/
+ 0xd8(PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0
*/
+ 0xcc(PIN_OUTPUT | MUX_MODE0)/* gpmc_wen
*/
+ 0xb4(PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0
*/
+ 0xc4(PIN_OUTPUT | MUX_MODE0)/*
gpmc_advn_ale */
+ 0xc8(PIN_OUTPUT | MUX_MODE0)/* gpmc_oen_ren
*/
+ 0xd0(PIN_OUTPUT | MUX_MODE0)/*
gpmc_be0n_cle */
+ ;
+ };
};
i2c1 {
@@ -353,3 +384,89 @@
};
};
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x16;
+ ranges = 0 0 0 0x0100; /* CS0: min. address-space configurable
under GPMC chip-select = 16MB */
+ nand@0,0 {
+ reg = 0 0 0x380; /* CS0, offet=0x0, GPMC register-space
size=0x380 */
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 16;
+ gpmc,device-width = 2;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 30;
+ gpmc,adv-wr-off-ns = 30;
+ gpmc,we-on-ns = 5;
+ gpmc,we-off-ns = 25;
+ gpmc,oe-on-ns = 2;
+ gpmc,oe-off-ns = 20;
+ gpmc,access-ns = 20;
+ gpmc,wr-access-ns = 40;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-on-read = true;
+ gpmc,wait-on-write = true;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable. For
+* NAND flash this is equal to size
[PATCH v3 1/4] mtd: nand: omap: add support for BCH16_ECC - GPMC driver updates
This patch add support for BCH16_ECC in GPMC (controller) driver:
- extend configuration space to include BCH16 registers
- extend parsing of DT binding for selecting BCH16 ecc-scheme
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/mach-omap2/gpmc.c | 15 +++
include/linux/platform_data/mtd-nand-omap2.h | 5 +
2 files changed, 20 insertions(+)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index ab43755..9b27773 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -68,6 +68,9 @@
#defineGPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
#defineGPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
#defineGPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
+#defineGPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
+#defineGPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
+#defineGPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
/* GPMC ECC control settings */
#define GPMC_ECC_CTRL_ECCCLEAR 0x100
@@ -666,6 +669,12 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int
cs)
GPMC_BCH_SIZE * i;
reg-gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
GPMC_BCH_SIZE * i;
+ reg-gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
+ i * GPMC_BCH_SIZE;
+ reg-gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
+ i * GPMC_BCH_SIZE;
+ reg-gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
+ i * GPMC_BCH_SIZE;
}
}
@@ -1401,6 +1410,12 @@ static int gpmc_probe_nand_child(struct platform_device
*pdev,
else
gpmc_nand_data-ecc_opt =
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
+ else if (!strcmp(s, bch16))
+ if (gpmc_nand_data-elm_of_node)
+ gpmc_nand_data-ecc_opt =
+ OMAP_ECC_BCH16_CODE_HW;
+ else
+ pr_err(%s: BCH16 requires ELM support\n, __func__);
else
pr_err(%s: ti,nand-ecc-opt invalid value\n, __func__);
diff --git a/include/linux/platform_data/mtd-nand-omap2.h
b/include/linux/platform_data/mtd-nand-omap2.h
index 3e9dd66..c2172e8 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -31,6 +31,8 @@ enum omap_ecc {
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
/* 8-bit ECC calculation by GPMC, Error detection by ELM */
OMAP_ECC_BCH8_CODE_HW,
+ /* 16-bit ECC calculation by GPMC, Error detection by ELM */
+ OMAP_ECC_BCH16_CODE_HW
};
struct gpmc_nand_regs {
@@ -50,6 +52,9 @@ struct gpmc_nand_regs {
void __iomem*gpmc_bch_result1[GPMC_BCH_NUM_REMAINDER];
void __iomem*gpmc_bch_result2[GPMC_BCH_NUM_REMAINDER];
void __iomem*gpmc_bch_result3[GPMC_BCH_NUM_REMAINDER];
+ void __iomem*gpmc_bch_result4[GPMC_BCH_NUM_REMAINDER];
+ void __iomem*gpmc_bch_result5[GPMC_BCH_NUM_REMAINDER];
+ void __iomem*gpmc_bch_result6[GPMC_BCH_NUM_REMAINDER];
};
struct omap_nand_platform_data {
--
1.8.5.1.163.gd7aced9
--
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[PATCH v3 0/4] mtd: nand: omap: add support for BCH16_ECC
(re-sending as forgot to loop in linux-omap and Tony Lindgren t...@atomide.com) *changes v2 - v3* [PATCH v2 3/4] rebased to http://lists.infradead.org/pipermail/linux-mtd/2014-March/052655.html - no change in other patches *changes v1 - v2* rebased and cleaned on following versions of pending patches (1) [PATCH v8 0/6] mtd: nand: omap: optimized chip-ecc.correct() for H/W ECC schemes http://lists.infradead.org/pipermail/linux-mtd/2014-February/052092.html (2) [PATCH v6 0/4] mtd: nand: omap: optimize chip-ecc.calculate() for H/W ECC schemes http://lists.infradead.org/pipermail/linux-mtd/2014-February/052272.html (3) [PATCH v5 0/4] mtd: nand: omap: optimize chip-ecc.hwctl() for H/W ECC schemes http://lists.infradead.org/pipermail/linux-mtd/2014-March/052327.html (4) [PATCH v6 0/4] mtd: devices: elm: add checks ELM H/W constrains, driver code cleanup http://lists.infradead.org/pipermail/linux-mtd/2014-March/052455.html Tested on Beaglebone-LT(white) NAND cape having NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224 *original v1* http://lists.infradead.org/pipermail/linux-mtd/2013-July/047562.html With increase in NAND flash densities and shrinking of technology NAND flash has become more suspectible to multiple bit-flips. Thus stronger ECC schemes are required for detecting and correcting multiple simultaneous bit-flips in same NAND page. But stronger ECC schemes have large ECC syndrome which require more space in OOB/Spare. This patch add support for BCH16 ecc-scheme on OMAP NAND driver: (a) BCH16 ecc-scheme can correct 16 bit-flips per 512Bytes of data. (b) BCH16 ecc-scheme generates 26-bytes of ECC syndrome / 512B. Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy following equation: OOBsize per page = 26 * (page-size / 512) Pekon Gupta (4): mtd: nand: omap: add support for BCH16_ECC - GPMC driver updates mtd: nand: omap: add support for BCH16_ECC - ELM driver updates mtd: nand: omap: add support for BCH16_ECC - NAND driver updates mtd: nand: omap: Documentation: How to select correct ECC scheme for your device ? .../devicetree/bindings/mtd/gpmc-nand.txt | 39 + arch/arm/mach-omap2/gpmc.c | 15 drivers/mtd/devices/elm.c | 42 ++ drivers/mtd/nand/omap2.c | 94 ++ include/linux/platform_data/elm.h | 3 +- include/linux/platform_data/mtd-nand-omap2.h | 5 ++ 6 files changed, 197 insertions(+), 1 deletion(-) -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/4] mtd: nand: omap: add support for BCH16_ECC - ELM driver updates
ELM hardware engine is used to detect ECC errors for BCHx ecc-schemes
(like BCH4/BCH8/BCH16). This patch extends configuration of ELM registers
for loading of BCH16 ECC syndrome.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/devices/elm.c | 42 +++
include/linux/platform_data/elm.h | 3 ++-
2 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/elm.c b/drivers/mtd/devices/elm.c
index 1fd4a0f..b4b02a1 100644
--- a/drivers/mtd/devices/elm.c
+++ b/drivers/mtd/devices/elm.c
@@ -213,6 +213,34 @@ static void elm_load_syndrome(struct elm_info *info,
val = cpu_to_be32(*(u32 *) ecc[0]) 12;
elm_write_reg(info, offset, val);
break;
+ case BCH16_ECC:
+ val = ecc[25] 0 | ecc[24] 8 |
+ ecc[23] 16 | ecc[22] 24;
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = ecc[21] 0 | ecc[20] 8 |
+ ecc[19] 16 | ecc[18] 24;
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = ecc[17] 0 | ecc[16] 8 |
+ ecc[15] 16 | ecc[14] 24;
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = ecc[13] 0 | ecc[12] 8 |
+ ecc[11] 16 | ecc[10] 24;
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = ecc[9]0 | ecc[8]8 |
+ ecc[7] 16 | ecc[6] 24;
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = ecc[5]0 | ecc[4]8 |
+ ecc[3] 16 | ecc[2] 24;
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = ecc[1]0 | ecc[0]8;
+ elm_write_reg(info, offset, val);
+ break;
default:
pr_err(invalid config bch_type\n);
}
@@ -435,6 +463,13 @@ static int elm_context_save(struct elm_info *info)
for (i = 0; i ERROR_VECTOR_MAX; i++) {
offset = i * SYNDROME_FRAGMENT_REG_SIZE;
switch (bch_type) {
+ case BCH16_ECC:
+ regs-elm_syndrome_fragment_6[i] = elm_read_reg(info,
+ ELM_SYNDROME_FRAGMENT_6 + offset);
+ regs-elm_syndrome_fragment_5[i] = elm_read_reg(info,
+ ELM_SYNDROME_FRAGMENT_5 + offset);
+ regs-elm_syndrome_fragment_4[i] = elm_read_reg(info,
+ ELM_SYNDROME_FRAGMENT_4 + offset);
case BCH8_ECC:
regs-elm_syndrome_fragment_3[i] = elm_read_reg(info,
ELM_SYNDROME_FRAGMENT_3 + offset);
@@ -473,6 +508,13 @@ static int elm_context_restore(struct elm_info *info)
for (i = 0; i ERROR_VECTOR_MAX; i++) {
offset = i * SYNDROME_FRAGMENT_REG_SIZE;
switch (bch_type) {
+ case BCH16_ECC:
+ elm_write_reg(info, ELM_SYNDROME_FRAGMENT_6 + offset,
+ regs-elm_syndrome_fragment_6[i]);
+ elm_write_reg(info, ELM_SYNDROME_FRAGMENT_5 + offset,
+ regs-elm_syndrome_fragment_5[i]);
+ elm_write_reg(info, ELM_SYNDROME_FRAGMENT_4 + offset,
+ regs-elm_syndrome_fragment_4[i]);
case BCH8_ECC:
elm_write_reg(info, ELM_SYNDROME_FRAGMENT_3 + offset,
regs-elm_syndrome_fragment_3[i]);
diff --git a/include/linux/platform_data/elm.h
b/include/linux/platform_data/elm.h
index 4edb406..ac2f266 100644
--- a/include/linux/platform_data/elm.h
+++ b/include/linux/platform_data/elm.h
@@ -21,6 +21,7 @@
enum bch_ecc {
BCH4_ECC = 0,
BCH8_ECC,
+ BCH16_ECC
};
/* ELM support 8 error syndrome process */
@@ -38,7 +39,7 @@ struct elm_errorvec {
bool error_reported;
bool error_uncorrectable;
int error_count;
- int error_loc[ERROR_VECTOR_MAX];
+ int error_loc[16];
};
void elm_decode_bch_error_page(struct device *dev, u8 *ecc_calc
[PATCH v3 4/4] mtd: nand: omap: Documentation: How to select correct ECC scheme for your device ?
- Adds DT binding property for BCH16 ECC scheme - Adds describes on factors which determine choice of ECC scheme for particular device Signed-off-by: Pekon Gupta pe...@ti.com --- .../devicetree/bindings/mtd/gpmc-nand.txt | 39 ++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt index 5e1f31b..f2dbb33 100644 --- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt @@ -28,6 +28,8 @@ Optional properties: ham1 1-bit Hamming ecc code bch4 4-bit BCH ecc code bch8 8-bit BCH ecc code + bch16 16-bit BCH ECC code + Refer below How to select correct ECC scheme for your device ? - ti,nand-xfer-type: A string setting the data transfer type. One of: @@ -90,3 +92,40 @@ Example for an AM33xx board: }; }; +How to select correct ECC scheme for your device ? +-- +Higher ECC scheme usually means better protection against bit-flips and +increased system lifetime. However, selection of ECC scheme is dependent +on various other factors like; +(1) Presence of supporting hardware engines on SoC. + Some legacy OMAP SoC do not have ELM h/w engine thus such SoC cannot + support BCHx_HW ECC schemes. But such SoC can support + BCHx_HW_DETECTION_SW ECC schemes which use s/w library with slight + CPU performance panalty only when too bit-flips are detected. +(2) Device parameters like OOBSIZE + Higher ECC schemes require more OOB/Spare area to store ECC. + So choice of ECC scheme is limited by NAND oobsize. In general + following expression help determine whether given device can + accomodate ECC syndrome or not: + 2 + (PAGESIZE / 512) * ECC_BYTES = OOBSIZE + where + OOBSIZE number of bytes in OOB/spare area + PAGESIZEnumber of bytes in main-area of device page + ECC_BYTES number of ECC bytes generated to protect + 512 bytes of data, which is: + '3' for HAM1_xx ecc schemes + '7' for BCH4_xx ecc schemes + '14' for BCH8_xx ecc schemes + '26' for BCH16_xx ecc schemes + + Example(a): For a device with PAGESIZE = 2048 and OOBSIZE = 64 + Number of spare/OOB bytes required for using BCH16 ecc-scheme + (2 + (2048 / 512) * 26) = 106 bytes is greater than OOBSIZE + (As per above table for BCH16 ecc-scheme, ECC_BYTES = 26) + Thus BCH16 cannot be supported on 2K NAND with OOBSIZE=64 bytes + + Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 + Number of spare/OOB bytes required for using BCH16 ecc-scheme + (2 + (2048 / 512) * 26) = 106 bytes is less than OOBSIZE + (As per above table for BCH16 ecc-scheme, ECC_BYTES = 26) + Thus BCH16 can be supported on 4K NAND with OOBSIZE=128 bytes -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 3/4] mtd: nand: omap: add support for BCH16_ECC - NAND driver updates
This patch add support for BCH16 ecc-scheme in OMAP NAND driver, by extending
following functions:
- omap_enable_hwecc (nand_chip-ecc.hwctl): configure GPMC controller
- omap_calculate_ecc_bch (nand_chip-ecc.calculate): fetch ECC signature from
GPMC controller
- omap_elm_correct_data (nand_chip-ecc.correct): detect and correct ECC
errors using ELM
(a) BCH16 ecc-scheme can detect and correct 16 bit-flips per 512Bytes of data.
(b) BCH16 ecc-scheme generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy the relation: OOBsize per page = 26 * (page-size / 512)
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 94
1 file changed, 94 insertions(+)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index d161c9b..c359af0 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -137,6 +137,10 @@
#define BADBLOCK_MARKER_LENGTH 2
#ifdef CONFIG_MTD_NAND_OMAP_BCH
+static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
+ 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
+ 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
+ 0x07, 0x0e};
static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
0xac, 0x6b, 0xff, 0x99, 0x7b};
static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
@@ -1115,6 +1119,19 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
mtd_info *mtd, int mode)
ecc_size1 = BCH_ECC_SIZE1;
}
break;
+ case OMAP_ECC_BCH16_CODE_HW:
+ bch_type = 0x2;
+ nsectors = chip-ecc.steps;
+ if (mode == NAND_ECC_READ) {
+ wr_mode = 0x01;
+ ecc_size0 = 52; /* ECC bits in nibbles per sector */
+ ecc_size1 = 0; /* non-ECC bits in nibbles per sector */
+ } else {
+ wr_mode = 0x01;
+ ecc_size0 = 0; /* extra bits in nibbles per sector */
+ ecc_size1 = 52; /* OOB bits in nibbles per sector */
+ }
+ break;
default:
return;
}
@@ -1163,6 +1180,7 @@ static int __maybe_unused omap_calculate_ecc_bch(struct
mtd_info *mtd,
struct gpmc_nand_regs *gpmc_regs = info-reg;
u8 *ecc_code;
unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
+ u32 val;
int i;
nsectors = ((readl(info-reg.gpmc_ecc_config) 4) 0x7) + 1;
@@ -1202,6 +1220,41 @@ static int __maybe_unused omap_calculate_ecc_bch(struct
mtd_info *mtd,
*ecc_code++ = ((bch_val1 4) 0xFF);
*ecc_code++ = ((bch_val1 0xF) 4);
break;
+ case OMAP_ECC_BCH16_CODE_HW:
+ val = readl(gpmc_regs-gpmc_bch_result6[i]);
+ ecc_code[0] = ((val 8) 0xFF);
+ ecc_code[1] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result5[i]);
+ ecc_code[2] = ((val 24) 0xFF);
+ ecc_code[3] = ((val 16) 0xFF);
+ ecc_code[4] = ((val 8) 0xFF);
+ ecc_code[5] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result4[i]);
+ ecc_code[6] = ((val 24) 0xFF);
+ ecc_code[7] = ((val 16) 0xFF);
+ ecc_code[8] = ((val 8) 0xFF);
+ ecc_code[9] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result3[i]);
+ ecc_code[10] = ((val 24) 0xFF);
+ ecc_code[11] = ((val 16) 0xFF);
+ ecc_code[12] = ((val 8) 0xFF);
+ ecc_code[13] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result2[i]);
+ ecc_code[14] = ((val 24) 0xFF);
+ ecc_code[15] = ((val 16) 0xFF);
+ ecc_code[16] = ((val 8) 0xFF);
+ ecc_code[17] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result1[i]);
+ ecc_code[18] = ((val 24) 0xFF);
+ ecc_code[19] = ((val 16) 0xFF);
+ ecc_code[20] = ((val 8) 0xFF);
+ ecc_code[21] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result0[i]);
+ ecc_code[22] = ((val 24) 0xFF);
+ ecc_code[23] = ((val 16) 0xFF);
+ ecc_code[24] = ((val 8) 0xFF
[PATCH v4 1/6] ARM: dts: am335x-bone: add support for beaglebone NAND cape
Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
Further information and datasheets can be found at [1] and [2]
* How to boot from NAND using Memory Expander + NAND Cape ? *
- Important: As BOOTSEL values are sampled only at POR, so after changing any
setting on SW2 (DIP switch), disconnect and reconnect all board power supply
(including mini-USB console port) to POR the beaglebone.
- Selection of ECC scheme
for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
for NAND cape(b), ROM code expects BCH16_HW ecc-scheme
- Selection of boot modes can be controlled via DIP switch(SW2) present on
Memory Expander cape, so first boot via MMC or other sources to flash NAND
device and then switch to SW2[SWITCH_BOOT]=ON to boot from NAND Cape.
SW2[SWITCH_BOOT] == OFF follow default boot order MMC- SPI - UART - USB
SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2)
- For NAND boot following switch settings need to be followed
SW2[ 0] = ON (SYSBOOT[ 0]==0: NAND boot mode selected )
SW2[ 1] = ON (SYSBOOT[ 1]==0: -- do -- )
SW2[ 2] = OFF (SYSBOOT[ 2]==1: -- do -- )
SW2[ 3] = OFF (SYSBOOT[ 3]==1: -- do -- )
SW2[ 4] = ON (SYSBOOT[ 4]==0: -- do -- )
SW2[ 8] = OFF (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
SW2[ 9] = ON (SYSBOOT[ 9]==0: ECC done by ROM )
SW2[10] = ON (SYSBOOT[10]==0: Non Muxed device )
SW2[11] = ON (SYSBOOT[11]==0:-- do -- )
[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2]
http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-bone-memory-cape.dts | 130 ++
arch/arm/boot/dts/am335x-bone.dts | 1 +
arch/arm/boot/dts/am335x-boneblack.dts| 1 +
3 files changed, 132 insertions(+)
create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts
diff --git a/arch/arm/boot/dts/am335x-bone-memory-cape.dts
b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
new file mode 100644
index 000..c59b3d7
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This DTS adds supports for capes using GPMC interface to connect external
+ * memory like NAND, NOR Flash to Beaglebone-LT (white) and Beaglebone-Black.
+ */
+
+
+am33xx_pinmux {
+ nand_flash_x16: nand_flash_x16 {
+ pinctrl-single,pins =
+ 0x00 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad0.gpmc_ad0 */
+ 0x04 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad1.gpmc_ad1 */
+ 0x08 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad2.gpmc_ad2 */
+ 0x0c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad3.gpmc_ad3 */
+ 0x10 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad4.gpmc_ad4 */
+ 0x14 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad5.gpmc_ad5 */
+ 0x18 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad6.gpmc_ad6 */
+ 0x1c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad7.gpmc_ad7 */
+ 0x20 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad8.gpmc_ad8 */
+ 0x24 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad9.gpmc_ad9 */
+ 0x28 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad10.gpmc_ad10
*/
+ 0x2c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad11.gpmc_ad11
*/
+ 0x30 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad12.gpmc_ad12
*/
+ 0x34 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad13.gpmc_ad13
*/
+ 0x38 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad14.gpmc_ad14
*/
+ 0x3c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad15.gpmc_ad15
*/
+ 0x70 (MUX_MODE0 | PIN_INPUT_PULLUP )/*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (MUX_MODE7 | PIN_OUTPUT_PULLUP)/*
gpmc_wpn.gpio0_30 */
+ 0x7c (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_wen.gpmc_wen */
+ 0x9c (MUX_MODE0 | PIN_OUTPUT
[PATCH v4 0/6] add parallel NAND support for TI's new OMAPx and AMxx platforms (Part-2)
*changes v3 - v4* fixed reg and range property for all GPMC DT nodes added fix for am335x-evm and am437x-epos-evm rebased on git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap +omap-for-v3.16/dt *changes v2 - v3* rebased on git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap :master merged leftover patches (dra7-evm and am43x-epos-evm fix) from Part-1 series *changes v1 - v2* [PATCH v2 1/2] created new DTS for memory-capes based on following feedbacks http://www.spinics.net/lists/linux-omap/msg104348.html from 'Nishanth Menon n...@ti.com' http://www.spinics.net/lists/linux-omap/msg104447.html from 'Tony Lindgren t...@atomide.com' [PATCH v2 2/2] same as [PATCH v1 1/3] *original v1* This patch-set adds parallel NAND support on following TI platforms - AM335x (am335x-bone LT, am335x-boneblack): disabled by default - AM43xx (am437x-gp-evm) Minal Shah (1): ARM: dts: dra7: add support for parallel NAND flash Pekon Gupta (5): ARM: dts: am335x-bone: add support for beaglebone NAND cape ARM: dts: am437x-gp-evm: add support for parallel NAND flash ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition ARM: dts: am43x-epos-evm: fix reg and range property of GPMC NAND node ARM: dts: am335x-evm: fix reg and range property of GPMC NAND node arch/arm/boot/dts/am335x-bone-memory-cape.dts | 130 ++ arch/arm/boot/dts/am335x-bone.dts | 1 + arch/arm/boot/dts/am335x-boneblack.dts| 1 + arch/arm/boot/dts/am335x-evm.dts | 4 +- arch/arm/boot/dts/am437x-gp-evm.dts | 107 + arch/arm/boot/dts/am43x-epos-evm.dts | 6 +- arch/arm/boot/dts/dra7-evm.dts| 117 +++ arch/arm/boot/dts/dra7.dtsi | 20 8 files changed, 381 insertions(+), 5 deletions(-) create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 2/6] ARM: dts: am437x-gp-evm: add support for parallel NAND flash
Adds pinmux and DT node for Micron (MT29F4G08AB) x8 NAND device present on
am437x-gp-evm board.
(1) As NAND Flash data lines are muxed with eMMC, Thus at a given time either
eMMC or NAND can be enabled. Selection between eMMC and NAND is controlled:
(a) By dynamically driving following GPIO pin from software
SPI2_CS0(GPIO) == 0 NAND is selected (default)
SPI2_CS0(GPIO) == 1 eMMC is selected
(b) By statically using Jumper (J89) on the board
(2) As NAND device connnected to this board has page-size=4K and oob-size=224,
So ROM code expects boot-loaders to be flashed in BCH16 ECC scheme for
NAND boot.
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 107
1 file changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 2e0c636..bfb2007 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -98,6 +98,27 @@
0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /*
spi2_d0.gpio3_22 */
;
};
+
+ nand_flash_x8: nand_flash_x8 {
+ pinctrl-single,pins =
+ 0x26C(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /*
spi2_cs0.gpio/eMMCorNANDsel */
+ 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)/*
gpmc_wpn.gpmc_wpn */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_wen.gpmc_wen */
+ 0x9c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_be0n_cle.gpmc_be0n_cle */
+ ;
+ };
};
i2c0 {
@@ -174,3 +195,89 @@
dr_mode = host;
status = okay;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x8;
+ ranges = 0 0 0 0x100; /* CS0: NAND */
+ nand@0,0 {
+ reg = 0 0 0x380; /* CS0, offset=0, reg-map size=0x380 */
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 8;
+ gpmc,device-width = 1;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 25;
+ gpmc,adv-wr-off-ns = 25;
+ gpmc,we-on-ns = 0;
+ gpmc,we-off-ns = 20;
+ gpmc,oe-on-ns = 3;
+ gpmc,oe-off-ns = 30;
+ gpmc,access-ns = 30;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-on-read = true;
+ gpmc,wait-on-write = true;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-access-ns = 40;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable. For
+* NAND flash this is equal to size of erase-block */
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ label = NAND.SPL;
+ reg = 0x 0x0004;
+ };
+ partition@1 {
+ label = NAND.SPL.backup1;
+ reg = 0x0004 0x0004;
+ };
+ partition@2 {
+ label = NAND.SPL.backup2;
+ reg = 0x0008 0x0004;
+ };
+ partition@3 {
+ label = NAND.SPL.backup3;
+ reg = 0x000c 0x0004;
+ };
+ partition@4
[PATCH v4 4/6] ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition
MTD NAND partition for file-system should start at offset=0xA0
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index cf8bdf1..fd29930 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -360,7 +360,7 @@
};
partition@9 {
label = NAND.file-system;
- reg = 0x0080 0x1F60;
+ reg = 0x00A0 0x1F60;
};
};
};
--
1.8.5.1.163.gd7aced9
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[PATCH v4 3/6] ARM: dts: dra7: add support for parallel NAND flash
From: Minal Shah minalks...@gmail.com
DRA7xx platform has in-build GPMC and ELM h/w engines which can be used
for accessing externel NAND flash device. This patch:
- adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines
- adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm
*Important*
On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch
So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH
Signed-off-by: Minal Shah minalks...@gmail.com
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 117 +
arch/arm/boot/dts/dra7.dtsi| 20 +++
2 files changed, 137 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5f1f6da..ed4e974 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -108,6 +108,37 @@
0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs3.qspi1_cs1 */
;
};
+
+ nand_flash_x16: nand_flash_x16 {
+ /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
+* So NAND flash requires following switch settings:
+* SW5.9 (GPMC_WPN) = LOW
+* SW5.1 (NAND_BOOTn) = HIGH */
+ pinctrl-single,pins =
+ 0x0 (PIN_INPUT | MUX_MODE0)/* gpmc_ad0
*/
+ 0x4 (PIN_INPUT | MUX_MODE0)/* gpmc_ad1
*/
+ 0x8 (PIN_INPUT | MUX_MODE0)/* gpmc_ad2
*/
+ 0xc (PIN_INPUT | MUX_MODE0)/* gpmc_ad3
*/
+ 0x10(PIN_INPUT | MUX_MODE0)/* gpmc_ad4
*/
+ 0x14(PIN_INPUT | MUX_MODE0)/* gpmc_ad5
*/
+ 0x18(PIN_INPUT | MUX_MODE0)/* gpmc_ad6
*/
+ 0x1c(PIN_INPUT | MUX_MODE0)/* gpmc_ad7
*/
+ 0x20(PIN_INPUT | MUX_MODE0)/* gpmc_ad8
*/
+ 0x24(PIN_INPUT | MUX_MODE0)/* gpmc_ad9
*/
+ 0x28(PIN_INPUT | MUX_MODE0)/* gpmc_ad10
*/
+ 0x2C(PIN_INPUT | MUX_MODE0)/* gpmc_ad11
*/
+ 0x30(PIN_INPUT | MUX_MODE0)/* gpmc_ad12
*/
+ 0x34(PIN_INPUT | MUX_MODE0)/* gpmc_ad13
*/
+ 0x38(PIN_INPUT | MUX_MODE0)/* gpmc_ad14
*/
+ 0x3C(PIN_INPUT | MUX_MODE0)/* gpmc_ad15
*/
+ 0xd8(PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0
*/
+ 0xcc(PIN_OUTPUT | MUX_MODE0)/* gpmc_wen
*/
+ 0xb4(PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0
*/
+ 0xc4(PIN_OUTPUT | MUX_MODE0)/*
gpmc_advn_ale */
+ 0xc8(PIN_OUTPUT | MUX_MODE0)/* gpmc_oen_ren
*/
+ 0xd0(PIN_OUTPUT | MUX_MODE0)/*
gpmc_be0n_cle */
+ ;
+ };
};
i2c1 {
@@ -353,3 +384,89 @@
};
};
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x16;
+ ranges = 0 0 0 0x100;
+ nand@0,0 {
+ reg = 0 0 0x380;
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 16;
+ gpmc,device-width = 2;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 30;
+ gpmc,adv-wr-off-ns = 30;
+ gpmc,we-on-ns = 5;
+ gpmc,we-off-ns = 25;
+ gpmc,oe-on-ns = 2;
+ gpmc,oe-off-ns = 20;
+ gpmc,access-ns = 20;
+ gpmc,wr-access-ns = 40;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-on-read = true;
+ gpmc,wait-on-write = true;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable. For
+* NAND flash this is equal to size of erase-block */
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0
[PATCH v4 5/6] ARM: dts: am43x-epos-evm: fix reg and range property of GPMC NAND node
1) NAND device memory is not directly accessible to CPU, its indirectly accessed
via registers. So the 'reg' property for GPMC NAND nodes should be limited to
address range of internal GPMC registers only.
2) Also, minimum granularity of address space under a GPMC chip-select is 16MB
so 'range' property for GPMC NAND node should specify 16MB as its memory-size
3) On AM437x, address map of external memory accessible via GPMC starts from 0x0
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index fd29930..63a6a59 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -287,9 +287,9 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = nand_flash_x8;
- ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
+ ranges = 0 0 0 0x100; /* CS0: NAND */
nand@0,0 {
- reg = 0 0 0; /* CS0, offset 0 */
+ reg = 0 0 0x380; /* CS0, offset=0, re-map size=0x380 */
ti,nand-ecc-opt = bch8;
ti,elm-id = elm;
nand-bus-width = 8;
--
1.8.5.1.163.gd7aced9
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[PATCH v4 6/6] ARM: dts: am335x-evm: fix reg and range property of GPMC NAND node
1) NAND device memory is not directly accessible to CPU, its indirectly accessed
via registers. So the 'reg' property for GPMC NAND nodes should be limited to
address range of internal GPMC registers only.
2) Also, minimum granularity of address space under a GPMC chip-select is 16MB
so 'range' property for GPMC NAND node should specify 16MB as its memory-size
3) On AM437x, address map of external memory accessible via GPMC starts from 0x0
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-evm.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 33f7c57..bae7575 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -437,9 +437,9 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = nandflash_pins_s0;
- ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
+ ranges = 0 0 0 0x100; /* CS0: NAND */
nand@0,0 {
- reg = 0 0 0; /* CS0, offset 0 */
+ reg = 0 0 0x380; /* CS0, offset=0, reg-map size=0x380 */
ti,nand-ecc-opt = bch8;
ti,elm-id = elm;
nand-bus-width = 8;
--
1.8.5.1.163.gd7aced9
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[PATCH v3 1/4] ARM: dts: am335x-bone: add support for beaglebone NAND cape
Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
Further information and datasheets can be found at [1] and [2]
* How to boot from NAND using Memory Expander + NAND Cape ? *
- Important: As BOOTSEL values are sampled only at POR, so after changing any
setting on SW2 (DIP switch), disconnect and reconnect all board power supply
(including mini-USB console port) to POR the beaglebone.
- Selection of ECC scheme
for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
for NAND cape(b), ROM code expects BCH16_HW ecc-scheme
- Selection of boot modes can be controlled via DIP switch(SW2) present on
Memory Expander cape, so first boot via MMC or other sources to flash NAND
device and then switch to SW2[SWITCH_BOOT]=ON to boot from NAND Cape.
SW2[SWITCH_BOOT] == OFF follow default boot order MMC- SPI - UART - USB
SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2)
- For NAND boot following switch settings need to be followed
SW2[ 0] = ON (SYSBOOT[ 0]==0: NAND boot mode selected )
SW2[ 1] = ON (SYSBOOT[ 1]==0: -- do -- )
SW2[ 2] = OFF (SYSBOOT[ 2]==1: -- do -- )
SW2[ 3] = OFF (SYSBOOT[ 3]==1: -- do -- )
SW2[ 4] = ON (SYSBOOT[ 4]==0: -- do -- )
SW2[ 8] = OFF (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
SW2[ 9] = ON (SYSBOOT[ 9]==0: ECC done by ROM )
SW2[10] = ON (SYSBOOT[10]==0: Non Muxed device )
SW2[11] = ON (SYSBOOT[11]==0:-- do -- )
[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2]
http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-bone-memory-cape.dts | 130 ++
arch/arm/boot/dts/am335x-bone.dts | 1 +
arch/arm/boot/dts/am335x-boneblack.dts| 1 +
3 files changed, 132 insertions(+)
create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts
diff --git a/arch/arm/boot/dts/am335x-bone-memory-cape.dts
b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
new file mode 100644
index 000..9c9f6a6
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This DTS adds supports for capes using GPMC interface to connect external
+ * memory like NAND, NOR Flash to Beaglebone-LT (white) and Beaglebone-Black.
+ */
+
+
+am33xx_pinmux {
+ nand_flash_x16: nand_flash_x16 {
+ pinctrl-single,pins =
+ 0x00 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad0.gpmc_ad0 */
+ 0x04 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad1.gpmc_ad1 */
+ 0x08 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad2.gpmc_ad2 */
+ 0x0c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad3.gpmc_ad3 */
+ 0x10 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad4.gpmc_ad4 */
+ 0x14 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad5.gpmc_ad5 */
+ 0x18 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad6.gpmc_ad6 */
+ 0x1c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad7.gpmc_ad7 */
+ 0x20 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad8.gpmc_ad8 */
+ 0x24 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad9.gpmc_ad9 */
+ 0x28 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad10.gpmc_ad10
*/
+ 0x2c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad11.gpmc_ad11
*/
+ 0x30 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad12.gpmc_ad12
*/
+ 0x34 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad13.gpmc_ad13
*/
+ 0x38 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad14.gpmc_ad14
*/
+ 0x3c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad15.gpmc_ad15
*/
+ 0x70 (MUX_MODE0 | PIN_INPUT_PULLUP )/*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (MUX_MODE7 | PIN_OUTPUT_PULLUP)/*
gpmc_wpn.gpio0_30 */
+ 0x7c (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_wen.gpmc_wen */
+ 0x9c (MUX_MODE0 | PIN_OUTPUT
[PATCH v3 0/4] add parallel NAND support for TI's new OMAPx and AMxx platforms (Part-2)
*changes v2 - v3* rebased on git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap :master merged leftover patches (dra7-evm and am43x-epos-evm fix) from Part-1 series *changes v1 - v2* [PATCH v2 1/2] created new DTS for memory-capes based on following feedbacks http://www.spinics.net/lists/linux-omap/msg104348.html from 'Nishanth Menon n...@ti.com' http://www.spinics.net/lists/linux-omap/msg104447.html from 'Tony Lindgren t...@atomide.com' [PATCH v2 2/2] same as [PATCH v1 1/3] *original v1* This patch-set adds parallel NAND support on following TI platforms - AM335x (am335x-bone LT, am335x-boneblack): disabled by default - AM43xx (am437x-gp-evm) Minal Shah (1): ARM: dts: dra7: add support for parallel NAND flash Pekon Gupta (3): ARM: dts: am335x-bone: add support for beaglebone NAND cape ARM: dts: am437x-gp-evm: add support for parallel NAND flash ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition arch/arm/boot/dts/am335x-bone-memory-cape.dts | 130 ++ arch/arm/boot/dts/am335x-bone.dts | 1 + arch/arm/boot/dts/am335x-boneblack.dts| 1 + arch/arm/boot/dts/am437x-gp-evm.dts | 107 + arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- arch/arm/boot/dts/dra7-evm.dts| 117 +++ arch/arm/boot/dts/dra7.dtsi | 20 7 files changed, 377 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/4] ARM: dts: am437x-gp-evm: add support for parallel NAND flash
Adds pinmux and DT node for Micron (MT29F4G08AB) x8 NAND device present on
am437x-gp-evm board.
(1) As NAND Flash data lines are muxed with eMMC, Thus at a given time either
eMMC or NAND can be enabled. Selection between eMMC and NAND is controlled:
(a) By dynamically driving following GPIO pin from software
SPI2_CS0(GPIO) == 0 NAND is selected (default)
SPI2_CS0(GPIO) == 1 eMMC is selected
(b) By statically using Jumper (J89) on the board
(2) As NAND device connnected to this board has page-size=4K and oob-size=224,
So ROM code expects boot-loaders to be flashed in BCH16 ECC scheme for
NAND boot.
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 107
1 file changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index df8798e..0027ea7 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -81,6 +81,27 @@
0x164 MUX_MODE0 /*
eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
;
};
+
+ nand_flash_x8: nand_flash_x8 {
+ pinctrl-single,pins =
+ 0x26C(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /*
spi2_cs0.gpio/eMMCorNANDsel */
+ 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)/*
gpmc_wpn.gpmc_wpn */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_wen.gpmc_wen */
+ 0x9c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_be0n_cle.gpmc_be0n_cle */
+ ;
+ };
};
i2c0 {
@@ -125,3 +146,89 @@
pinctrl-0 = mmc1_pins;
cd-gpios = gpio0 6 GPIO_ACTIVE_HIGH;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x8;
+ ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
+ nand@0,0 {
+ reg = 0 0 0; /* CS0, offset 0 */
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 8;
+ gpmc,device-width = 1;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 25;
+ gpmc,adv-wr-off-ns = 25;
+ gpmc,we-on-ns = 0;
+ gpmc,we-off-ns = 20;
+ gpmc,oe-on-ns = 3;
+ gpmc,oe-off-ns = 30;
+ gpmc,access-ns = 30;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-on-read = true;
+ gpmc,wait-on-write = true;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-access-ns = 40;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable. For
+* NAND flash this is equal to size of erase-block */
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ label = NAND.SPL;
+ reg = 0x 0x0004;
+ };
+ partition@1 {
+ label = NAND.SPL.backup1;
+ reg = 0x0004 0x0004;
+ };
+ partition@2 {
+ label = NAND.SPL.backup2;
+ reg = 0x0008 0x0004;
+ };
+ partition@3 {
+ label = NAND.SPL.backup3;
+ reg = 0x000C 0x0004
[PATCH v3 4/4] ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition
MTD NAND partition for file-system should start at offset=0xA0
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 167dbc8..d09e6fb 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -341,7 +341,7 @@
};
partition@9 {
label = NAND.file-system;
- reg = 0x0080 0x1F60;
+ reg = 0x00A0 0x1F60;
};
};
};
--
1.8.5.1.163.gd7aced9
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[PATCH v3 3/4] ARM: dts: dra7: add support for parallel NAND flash
From: Minal Shah minalks...@gmail.com
DRA7xx platform has in-build GPMC and ELM h/w engines which can be used
for accessing externel NAND flash device. This patch:
- adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines
- adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm
*Important*
On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch
So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH
Signed-off-by: Minal Shah minalks...@gmail.com
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 117 +
arch/arm/boot/dts/dra7.dtsi| 20 +++
2 files changed, 137 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..7b4e6f5 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,37 @@
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
;
};
+
+ nand_flash_x16: nand_flash_x16 {
+ /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
+* So NAND flash requires following switch settings:
+* SW5.9 (GPMC_WPN) = LOW
+* SW5.1 (NAND_BOOTn) = HIGH */
+ pinctrl-single,pins =
+ 0x0 (PIN_INPUT | MUX_MODE0)/* gpmc_ad0
*/
+ 0x4 (PIN_INPUT | MUX_MODE0)/* gpmc_ad1
*/
+ 0x8 (PIN_INPUT | MUX_MODE0)/* gpmc_ad2
*/
+ 0xc (PIN_INPUT | MUX_MODE0)/* gpmc_ad3
*/
+ 0x10(PIN_INPUT | MUX_MODE0)/* gpmc_ad4
*/
+ 0x14(PIN_INPUT | MUX_MODE0)/* gpmc_ad5
*/
+ 0x18(PIN_INPUT | MUX_MODE0)/* gpmc_ad6
*/
+ 0x1c(PIN_INPUT | MUX_MODE0)/* gpmc_ad7
*/
+ 0x20(PIN_INPUT | MUX_MODE0)/* gpmc_ad8
*/
+ 0x24(PIN_INPUT | MUX_MODE0)/* gpmc_ad9
*/
+ 0x28(PIN_INPUT | MUX_MODE0)/* gpmc_ad10
*/
+ 0x2c(PIN_INPUT | MUX_MODE0)/* gpmc_ad11
*/
+ 0x30(PIN_INPUT | MUX_MODE0)/* gpmc_ad12
*/
+ 0x34(PIN_INPUT | MUX_MODE0)/* gpmc_ad13
*/
+ 0x38(PIN_INPUT | MUX_MODE0)/* gpmc_ad14
*/
+ 0x3c(PIN_INPUT | MUX_MODE0)/* gpmc_ad15
*/
+ 0xD8(PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0
*/
+ 0xCC(PIN_OUTPUT | MUX_MODE0)/* gpmc_wen
*/
+ 0xB4(PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0
*/
+ 0xC4(PIN_OUTPUT | MUX_MODE0)/*
gpmc_advn_ale */
+ 0xC8(PIN_OUTPUT | MUX_MODE0)/* gpmc_oen_ren
*/
+ 0xD0(PIN_OUTPUT | MUX_MODE0)/*
gpmc_be0n_cle */
+ ;
+ };
};
i2c1 {
@@ -273,3 +304,89 @@
cpu0 {
cpu0-supply = smps123_reg;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x16;
+ ranges = 0 0 0x0800 0x1000;
+ nand@0,0 {
+ reg = 0 0 0;
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 16;
+ gpmc,device-width = 2;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 30;
+ gpmc,adv-wr-off-ns = 30;
+ gpmc,we-on-ns = 5;
+ gpmc,we-off-ns = 25;
+ gpmc,oe-on-ns = 2;
+ gpmc,oe-off-ns = 20;
+ gpmc,access-ns = 20;
+ gpmc,wr-access-ns = 40;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-on-read = true;
+ gpmc,wait-on-write = true;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable. For
+* NAND flash this is equal to size of erase-block */
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0
[PATCH v2 1/2] ARM: dts: am335x-bone: add support for beaglebone NAND cape
Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
Further information and datasheets can be found at [1] and [2]
* How to boot from NAND using Memory Expander + NAND Cape ? *
- Important: As BOOTSEL values are sampled only at POR, so after changing any
setting on SW2 (DIP switch), disconnect and reconnect all board power supply
(including mini-USB console port) to POR the beaglebone.
- Selection of ECC scheme
for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
for NAND cape(b), ROM code expects BCH16_HW ecc-scheme
- Selection of boot modes can be controlled via DIP switch(SW2) present on
Memory Expander cape, so first boot via MMC or other sources to flash NAND
device and then switch to SW2[SWITCH_BOOT]=ON to boot from NAND Cape.
SW2[SWITCH_BOOT] == OFF follow default boot order MMC- SPI - UART - USB
SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2)
- For NAND boot following switch settings need to be followed
SW2[ 0] = ON (SYSBOOT[ 0]==0: NAND boot mode selected )
SW2[ 1] = ON (SYSBOOT[ 1]==0: -- do -- )
SW2[ 2] = OFF (SYSBOOT[ 2]==1: -- do -- )
SW2[ 3] = OFF (SYSBOOT[ 3]==1: -- do -- )
SW2[ 4] = ON (SYSBOOT[ 4]==0: -- do -- )
SW2[ 8] = OFF (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
SW2[ 9] = ON (SYSBOOT[ 9]==0: ECC done by ROM )
SW2[10] = ON (SYSBOOT[10]==0: Non Muxed device )
SW2[11] = ON (SYSBOOT[11]==0:-- do -- )
[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2]
http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-bone-memory-cape.dts | 130 ++
arch/arm/boot/dts/am335x-bone.dts | 1 +
arch/arm/boot/dts/am335x-boneblack.dts| 1 +
3 files changed, 132 insertions(+)
create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts
diff --git a/arch/arm/boot/dts/am335x-bone-memory-cape.dts
b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
new file mode 100644
index 000..9c9f6a6
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone-memory-cape.dts
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This DTS adds supports for capes using GPMC interface to connect external
+ * memory like NAND, NOR Flash to Beaglebone-LT (white) and Beaglebone-Black.
+ */
+
+
+am33xx_pinmux {
+ nand_flash_x16: nand_flash_x16 {
+ pinctrl-single,pins =
+ 0x00 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad0.gpmc_ad0 */
+ 0x04 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad1.gpmc_ad1 */
+ 0x08 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad2.gpmc_ad2 */
+ 0x0c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad3.gpmc_ad3 */
+ 0x10 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad4.gpmc_ad4 */
+ 0x14 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad5.gpmc_ad5 */
+ 0x18 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad6.gpmc_ad6 */
+ 0x1c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad7.gpmc_ad7 */
+ 0x20 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad8.gpmc_ad8 */
+ 0x24 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad9.gpmc_ad9 */
+ 0x28 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad10.gpmc_ad10
*/
+ 0x2c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad11.gpmc_ad11
*/
+ 0x30 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad12.gpmc_ad12
*/
+ 0x34 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad13.gpmc_ad13
*/
+ 0x38 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad14.gpmc_ad14
*/
+ 0x3c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad15.gpmc_ad15
*/
+ 0x70 (MUX_MODE0 | PIN_INPUT_PULLUP )/*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (MUX_MODE7 | PIN_OUTPUT_PULLUP)/*
gpmc_wpn.gpio0_30 */
+ 0x7c (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_wen.gpmc_wen */
+ 0x9c (MUX_MODE0 | PIN_OUTPUT
[PATCH v2 0/2] add parallel NAND support for TI's new OMAPx and AMxx platforms (Part-2)
Series is rebased on following tree for OMAP DT git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap :omap-for-v3.15/dt *changes v1 - v2* [PATCH v2 1/2] created new DTS for memory-capes based on following feedbacks http://www.spinics.net/lists/linux-omap/msg104348.html from 'Nishanth Menon n...@ti.com' http://www.spinics.net/lists/linux-omap/msg104447.html from 'Tony Lindgren t...@atomide.com' [PATCH v2 2/2] same as [PATCH v1 1/3] *original v1* This patch-set adds parallel NAND support on following TI platforms - AM335x (am335x-bone LT, am335x-boneblack): disabled by default - AM43xx (am437x-gp-evm) Pekon Gupta (2): ARM: dts: am335x-bone: add support for beaglebone NAND cape ARM: dts: am437x-gp-evm: add support for parallel NAND flash arch/arm/boot/dts/am335x-bone-memory-cape.dts | 130 ++ arch/arm/boot/dts/am335x-bone.dts | 1 + arch/arm/boot/dts/am335x-boneblack.dts| 1 + arch/arm/boot/dts/am437x-gp-evm.dts | 107 + 4 files changed, 239 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-bone-memory-cape.dts -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/2] ARM: dts: am437x-gp-evm: add support for parallel NAND flash
Adds pinmux and DT node for Micron (MT29F4G08AB) x8 NAND device present on
am437x-gp-evm board.
(1) As NAND Flash data lines are muxed with eMMC, Thus at a given time either
eMMC or NAND can be enabled. Selection between eMMC and NAND is controlled:
(a) By dynamically driving following GPIO pin from software
SPI2_CS0(GPIO) == 0 NAND is selected (default)
SPI2_CS0(GPIO) == 1 eMMC is selected
(b) By statically using Jumper (J89) on the board
(2) As NAND device connnected to this board has page-size=4K and oob-size=224,
So ROM code expects boot-loaders to be flashed in BCH16 ECC scheme for
NAND boot.
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 107
1 file changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index df8798e..0027ea7 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -81,6 +81,27 @@
0x164 MUX_MODE0 /*
eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
;
};
+
+ nand_flash_x8: nand_flash_x8 {
+ pinctrl-single,pins =
+ 0x26C(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /*
spi2_cs0.gpio/eMMCorNANDsel */
+ 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)/*
gpmc_wpn.gpmc_wpn */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_wen.gpmc_wen */
+ 0x9c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_be0n_cle.gpmc_be0n_cle */
+ ;
+ };
};
i2c0 {
@@ -125,3 +146,89 @@
pinctrl-0 = mmc1_pins;
cd-gpios = gpio0 6 GPIO_ACTIVE_HIGH;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x8;
+ ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
+ nand@0,0 {
+ reg = 0 0 0; /* CS0, offset 0 */
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 8;
+ gpmc,device-width = 1;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 25;
+ gpmc,adv-wr-off-ns = 25;
+ gpmc,we-on-ns = 0;
+ gpmc,we-off-ns = 20;
+ gpmc,oe-on-ns = 3;
+ gpmc,oe-off-ns = 30;
+ gpmc,access-ns = 30;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-on-read = true;
+ gpmc,wait-on-write = true;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-access-ns = 40;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable. For
+* NAND flash this is equal to size of erase-block */
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ label = NAND.SPL;
+ reg = 0x 0x0004;
+ };
+ partition@1 {
+ label = NAND.SPL.backup1;
+ reg = 0x0004 0x0004;
+ };
+ partition@2 {
+ label = NAND.SPL.backup2;
+ reg = 0x0008 0x0004;
+ };
+ partition@3 {
+ label = NAND.SPL.backup3;
+ reg = 0x000C 0x0004
[PATCH v8 2/4] mtd: devices: elm: clean elm_load_syndrome
This patch refactors elm_load_syndrome() to make it scalable for newer
ECC schemes by removing scheme specific macros (like ECC_BYTES*xx),
and instead using ECC control information passed during elm_config.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/devices/elm.c | 18 +++---
include/linux/platform_data/elm.h | 7 ---
2 files changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/mtd/devices/elm.c b/drivers/mtd/devices/elm.c
index c51752a..4fbfaf6 100644
--- a/drivers/mtd/devices/elm.c
+++ b/drivers/mtd/devices/elm.c
@@ -84,6 +84,7 @@ struct elm_info {
struct list_head list;
enum bch_ecc bch_type;
struct elm_registers elm_regs;
+ int ecc_syndrome_size;
};
static LIST_HEAD(elm_devices);
@@ -126,7 +127,8 @@ int elm_config(struct device *dev, enum bch_ecc bch_type,
reg_val = (bch_type ECC_BCH_LEVEL_MASK) | (ELM_ECC_SIZE 16);
elm_write_reg(info, ELM_LOCATION_CONFIG, reg_val);
- info-bch_type = bch_type;
+ info-bch_type = bch_type;
+ info-ecc_syndrome_size = ecc_syndrome_size;
return 0;
}
@@ -175,10 +177,8 @@ static void elm_load_syndrome(struct elm_info *info,
elm_configure_page_mode(info, i, true);
offset = ELM_SYNDROME_FRAGMENT_0 +
SYNDROME_FRAGMENT_REG_SIZE * i;
-
- /* BCH8 */
- if (info-bch_type) {
-
+ switch (info-bch_type) {
+ case BCH8_ECC:
/* syndrome fragment 0 = ecc[9-12B] */
val = cpu_to_be32(*(u32 *) ecc[9]);
elm_write_reg(info, offset, val);
@@ -197,7 +197,8 @@ static void elm_load_syndrome(struct elm_info *info,
offset += 4;
val = ecc[0];
elm_write_reg(info, offset, val);
- } else {
+ break;
+ case BCH4_ECC:
/* syndrome fragment 0 = ecc[20-52b] bits */
val = (cpu_to_be32(*(u32 *) ecc[3]) 4) |
((ecc[2] 0xf) 28);
@@ -207,11 +208,14 @@ static void elm_load_syndrome(struct elm_info *info,
offset += 4;
val = cpu_to_be32(*(u32 *) ecc[0]) 12;
elm_write_reg(info, offset, val);
+ break;
+ default:
+ pr_err(invalid config bch_type\n);
}
}
/* Update ecc pointer with ecc byte size */
- ecc += info-bch_type ? BCH8_SIZE : BCH4_SIZE;
+ ecc += info-ecc_syndrome_size;
}
}
diff --git a/include/linux/platform_data/elm.h
b/include/linux/platform_data/elm.h
index 6e37156..4edb406 100644
--- a/include/linux/platform_data/elm.h
+++ b/include/linux/platform_data/elm.h
@@ -26,13 +26,6 @@ enum bch_ecc {
/* ELM support 8 error syndrome process */
#define ERROR_VECTOR_MAX 8
-#define BCH8_ECC_OOB_BYTES 13
-#define BCH4_ECC_OOB_BYTES 7
-/* RBL requires 14 byte even though BCH8 uses only 13 byte */
-#define BCH8_SIZE (BCH8_ECC_OOB_BYTES + 1)
-/* Uses 1 extra byte to handle erased pages */
-#define BCH4_SIZE (BCH4_ECC_OOB_BYTES + 1)
-
/**
* struct elm_errorvec - error vector for elm
* @error_reported:set true for vectors error is reported
--
1.8.5.1.163.gd7aced9
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[PATCH v8 1/4] mtd: devices: elm: check for hardware engine's design constraints
ELM hardware engine is used by BCH ecc-schemes for detecting and locating ECC
errors. This patch adds the following checks for ELM hardware engine:
- ELM internal buffers are of 1K,
so it cannot process data with ecc-step-size 1K.
- ELM engine can execute upto maximum of 8 threads in parallel,
so in *page-mode* (when complete page is processed in single iteration),
ELM cannot support ecc-steps 8.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/devices/elm.c | 13 -
drivers/mtd/nand/omap2.c | 9 ++---
include/linux/platform_data/elm.h | 3 ++-
3 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/devices/elm.c b/drivers/mtd/devices/elm.c
index f160d2c..c51752a 100644
--- a/drivers/mtd/devices/elm.c
+++ b/drivers/mtd/devices/elm.c
@@ -103,7 +103,8 @@ static u32 elm_read_reg(struct elm_info *info, int offset)
* @dev: ELM device
* @bch_type: Type of BCH ecc
*/
-int elm_config(struct device *dev, enum bch_ecc bch_type)
+int elm_config(struct device *dev, enum bch_ecc bch_type,
+ int ecc_steps, int ecc_step_size, int ecc_syndrome_size)
{
u32 reg_val;
struct elm_info *info = dev_get_drvdata(dev);
@@ -112,6 +113,16 @@ int elm_config(struct device *dev, enum bch_ecc bch_type)
dev_err(dev, Unable to configure elm - device not probed?\n);
return -ENODEV;
}
+ /* ELM cannot detect ECC errors for chunks 1KB */
+ if (ecc_step_size ((ELM_ECC_SIZE + 1) / 2)) {
+ dev_err(dev, unsupported config ecc-size=%d\n, ecc_step_size);
+ return -EINVAL;
+ }
+ /* ELM support 8 error syndrome process */
+ if (ecc_steps ERROR_VECTOR_MAX) {
+ dev_err(dev, unsupported config ecc-step=%d\n, ecc_steps);
+ return -EINVAL;
+ }
reg_val = (bch_type ECC_BCH_LEVEL_MASK) | (ELM_ECC_SIZE 16);
elm_write_reg(info, ELM_LOCATION_CONFIG, reg_val);
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index ab9c472..6f9b339 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1540,6 +1540,8 @@ static int is_elm_present(struct omap_nand_info *info,
struct device_node *elm_node, enum bch_ecc bch_type)
{
struct platform_device *pdev;
+ struct nand_ecc_ctrl *ecc = info-nand.ecc;
+ int err;
/* check whether elm-id is passed via DT */
if (!elm_node) {
pr_err(nand: error: ELM DT node not found\n);
@@ -1553,9 +1555,10 @@ static int is_elm_present(struct omap_nand_info *info,
}
/* ELM module available, now configure it */
info-elm_dev = pdev-dev;
- if (elm_config(info-elm_dev, bch_type))
- return -ENODEV;
- return 0;
+ err = elm_config(info-elm_dev, bch_type,
+ (info-mtd.writesize / ecc-size), ecc-size, ecc-bytes);
+
+ return err;
}
#endif /* CONFIG_MTD_NAND_ECC_BCH */
diff --git a/include/linux/platform_data/elm.h
b/include/linux/platform_data/elm.h
index bf0a83b..6e37156 100644
--- a/include/linux/platform_data/elm.h
+++ b/include/linux/platform_data/elm.h
@@ -50,5 +50,6 @@ struct elm_errorvec {
void elm_decode_bch_error_page(struct device *dev, u8 *ecc_calc,
struct elm_errorvec *err_vec);
-int elm_config(struct device *dev, enum bch_ecc bch_type);
+int elm_config(struct device *dev, enum bch_ecc bch_type,
+ int ecc_steps, int ecc_step_size, int ecc_syndrome_size);
#endif /* __ELM_H */
--
1.8.5.1.163.gd7aced9
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[PATCH v8 3/4] mtd: devices: elm: configure parallel channels based on ecc_steps
ELM hardware can process up to maximum of 8 hannels in parallel for
ECC error detection. Currently the number of channels getting configured for
processing is static determined by macro ERROR_VECTOR_MAX. However, the actual
number of channels that need to be processed is the ECC step number.
This patch just avoids configuring extra unused channels.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/devices/elm.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/devices/elm.c b/drivers/mtd/devices/elm.c
index 4fbfaf6..26df41f 100644
--- a/drivers/mtd/devices/elm.c
+++ b/drivers/mtd/devices/elm.c
@@ -84,6 +84,7 @@ struct elm_info {
struct list_head list;
enum bch_ecc bch_type;
struct elm_registers elm_regs;
+ int ecc_steps;
int ecc_syndrome_size;
};
@@ -128,6 +129,7 @@ int elm_config(struct device *dev, enum bch_ecc bch_type,
reg_val = (bch_type ECC_BCH_LEVEL_MASK) | (ELM_ECC_SIZE 16);
elm_write_reg(info, ELM_LOCATION_CONFIG, reg_val);
info-bch_type = bch_type;
+ info-ecc_steps = ecc_steps;
info-ecc_syndrome_size = ecc_syndrome_size;
return 0;
@@ -170,7 +172,7 @@ static void elm_load_syndrome(struct elm_info *info,
int i, offset;
u32 val;
- for (i = 0; i ERROR_VECTOR_MAX; i++) {
+ for (i = 0; i info-ecc_steps; i++) {
/* Check error reported */
if (err_vec[i].error_reported) {
@@ -238,7 +240,7 @@ static void elm_start_processing(struct elm_info *info,
* Set syndrome vector valid, so that ELM module
* will process it for vectors error is reported
*/
- for (i = 0; i ERROR_VECTOR_MAX; i++) {
+ for (i = 0; i info-ecc_steps; i++) {
if (err_vec[i].error_reported) {
offset = ELM_SYNDROME_FRAGMENT_6 +
SYNDROME_FRAGMENT_REG_SIZE * i;
@@ -267,7 +269,7 @@ static void elm_error_correction(struct elm_info *info,
int offset;
u32 reg_val;
- for (i = 0; i ERROR_VECTOR_MAX; i++) {
+ for (i = 0; i info-ecc_steps; i++) {
/* Check error reported */
if (err_vec[i].error_reported) {
--
1.8.5.1.163.gd7aced9
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[PATCH v8 0/4] mtd: devices: elm: add checks ELM H/W constrains, driver code cleanup
*changes v7 - v8* Incorporated feedbacks from Brian Norris computersforpe...@gmail.com - renamed ecc_step_bytes - ecc_syndrome_size *changes v6 - v7* Incorporated feedbacks from Ezequiel Garcia ezequiel.gar...@free-electrons.com - using dev_err() instead of pr_err() - moved un-related addition of info-ecc_steps, info-ecc_step_bytes, info-ecc_step_size from [PATCH v6 1/4] into subsequent patches - dropped pr_fmt() change *changes v5 - v6* [PATCH 02/04] minor cleanup *changes v4 - v5* This patch series is split version from earlier series [1]. This series refactors and cleans ELM driver which is used by Hardware based BCHx ecc-schemes. - Undo: introduction of 'struct mtd_info' and 'struct nand_chip'. Instead keep ELM driver independent of mtd_info and nand_chip structs and pass only required ECC configurations as elm_config() arguments elm_config(..., int ecc_steps, int ecc_step_size, int ecc_step_bytes) - Undo: re-writing of elm_load_syndrome() ECC register configurations. *changes v3 - v4 [1]* - in-corporated feedbacks from Brian Norris computersforpe...@gmail.com - updated: use 'pr_fmt(fmt)' to suffix DRIVER_NAME - removed: local 'eccsteps' in ELM driver, instead using nand_chip-ecc.steps - undo: irrelavant white-space changes [1] http://lists.infradead.org/pipermail/linux-mtd/2013-November/050242.html Pekon Gupta (4): mtd: devices: elm: check for hardware engine's design constraints mtd: devices: elm: clean elm_load_syndrome mtd: devices: elm: configure parallel channels based on ecc_steps mtd: devices: elm: update DRIVER_NAME as omap-elm drivers/mtd/devices/elm.c | 43 --- drivers/mtd/nand/omap2.c | 9 +--- include/linux/platform_data/elm.h | 10 ++--- 3 files changed, 39 insertions(+), 23 deletions(-) -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 4/4] mtd: devices: elm: update DRIVER_NAME as omap-elm
use omap-elm as DRIVER_NAME
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/devices/elm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/elm.c b/drivers/mtd/devices/elm.c
index 26df41f..1fd4a0f 100644
--- a/drivers/mtd/devices/elm.c
+++ b/drivers/mtd/devices/elm.c
@@ -15,6 +15,8 @@
*
*/
+#define DRIVER_NAMEomap-elm
+
#include linux/platform_device.h
#include linux/module.h
#include linux/interrupt.h
@@ -520,7 +522,7 @@ MODULE_DEVICE_TABLE(of, elm_of_match);
static struct platform_driver elm_driver = {
.driver = {
- .name = elm,
+ .name = DRIVER_NAME,
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(elm_of_match),
.pm = elm_pm_ops,
--
1.8.5.1.163.gd7aced9
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[PATCH v2 0/2] add parallel NAND support for TI's new OMAPx and AMxx platforms
*changes v1 - v2* - AM335x (am335x-evm): already accepted, so dropping in v2 - DRA7xx (dra7-evm): resending - AM43xx (am43X-epos-evm): fix MTD NAND.filesystem partition offset *Original v1* This patch-set adds and updates parallel NAND support on following TI platforms - AM335x (am335x-evm) - DRA7xx (dra7-evm - AM43xx (am43X-epos-evm) In addition, following OMAP2+/GPMC patch is also added in this series as it add checks DRA7xx and AM43xxx platforms for non-DT kernels. ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms Minal Shah (1): ARM: dts: dra7: add support for parallel NAND flash Pekon Gupta (1): ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- arch/arm/boot/dts/dra7-evm.dts | 117 +++ arch/arm/boot/dts/dra7.dtsi | 20 ++ 3 files changed, 138 insertions(+), 1 deletion(-) -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/2] ARM: dts: dra7: add support for parallel NAND flash
From: Minal Shah minal.s...@ti.com
DRA7xx platform has in-build GPMC and ELM h/w engines which can be used
for accessing externel NAND flash device. This patch:
- adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines
- adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm
*Important*
On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch
So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH
Signed-off-by: Minal Shah minal.s...@ti.com
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 117 +
arch/arm/boot/dts/dra7.dtsi| 20 +++
2 files changed, 137 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..7b4e6f5 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,37 @@
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
;
};
+
+ nand_flash_x16: nand_flash_x16 {
+ /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
+* So NAND flash requires following switch settings:
+* SW5.9 (GPMC_WPN) = LOW
+* SW5.1 (NAND_BOOTn) = HIGH */
+ pinctrl-single,pins =
+ 0x0 (PIN_INPUT | MUX_MODE0)/* gpmc_ad0
*/
+ 0x4 (PIN_INPUT | MUX_MODE0)/* gpmc_ad1
*/
+ 0x8 (PIN_INPUT | MUX_MODE0)/* gpmc_ad2
*/
+ 0xc (PIN_INPUT | MUX_MODE0)/* gpmc_ad3
*/
+ 0x10(PIN_INPUT | MUX_MODE0)/* gpmc_ad4
*/
+ 0x14(PIN_INPUT | MUX_MODE0)/* gpmc_ad5
*/
+ 0x18(PIN_INPUT | MUX_MODE0)/* gpmc_ad6
*/
+ 0x1c(PIN_INPUT | MUX_MODE0)/* gpmc_ad7
*/
+ 0x20(PIN_INPUT | MUX_MODE0)/* gpmc_ad8
*/
+ 0x24(PIN_INPUT | MUX_MODE0)/* gpmc_ad9
*/
+ 0x28(PIN_INPUT | MUX_MODE0)/* gpmc_ad10
*/
+ 0x2c(PIN_INPUT | MUX_MODE0)/* gpmc_ad11
*/
+ 0x30(PIN_INPUT | MUX_MODE0)/* gpmc_ad12
*/
+ 0x34(PIN_INPUT | MUX_MODE0)/* gpmc_ad13
*/
+ 0x38(PIN_INPUT | MUX_MODE0)/* gpmc_ad14
*/
+ 0x3c(PIN_INPUT | MUX_MODE0)/* gpmc_ad15
*/
+ 0xD8(PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0
*/
+ 0xCC(PIN_OUTPUT | MUX_MODE0)/* gpmc_wen
*/
+ 0xB4(PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0
*/
+ 0xC4(PIN_OUTPUT | MUX_MODE0)/*
gpmc_advn_ale */
+ 0xC8(PIN_OUTPUT | MUX_MODE0)/* gpmc_oen_ren
*/
+ 0xD0(PIN_OUTPUT | MUX_MODE0)/*
gpmc_be0n_cle */
+ ;
+ };
};
i2c1 {
@@ -273,3 +304,89 @@
cpu0 {
cpu0-supply = smps123_reg;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x16;
+ ranges = 0 0 0x0800 0x1000;
+ nand@0,0 {
+ reg = 0 0 0;
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 16;
+ gpmc,device-width = 2;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 30;
+ gpmc,adv-wr-off-ns = 30;
+ gpmc,we-on-ns = 5;
+ gpmc,we-off-ns = 25;
+ gpmc,oe-on-ns = 2;
+ gpmc,oe-off-ns = 20;
+ gpmc,access-ns = 20;
+ gpmc,wr-access-ns = 40;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-on-read = true;
+ gpmc,wait-on-write = true;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable. For
+* NAND flash this is equal to size of erase-block */
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0
[PATCH v2 2/2] ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition
MTD NAND partition for file-system should start at offset=0xA0
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 167dbc8..d09e6fb 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -341,7 +341,7 @@
};
partition@9 {
label = NAND.file-system;
- reg = 0x0080 0x1F60;
+ reg = 0x00A0 0x1F60;
};
};
};
--
1.8.5.1.163.gd7aced9
--
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[PATCH v1 3/3] ARM: dts: am437x-gp-evm: add support for parallel NAND flash
Adds pinmux and DT node for Micron (MT29F4G08AB) x8 NAND device present on
am437x-gp-evm board.
(1) As NAND Flash data lines are muxed with eMMC, Thus at a given time either
eMMC or NAND can be enabled. Selection between eMMC and NAND is controlled:
(a) By dynamically driving following GPIO pin from software
SPI2_CS0(GPIO) == 0 NAND is selected (default)
SPI2_CS0(GPIO) == 1 eMMC is selected
(b) By statically using Jumper (J89) on the board
(2) As NAND device connnected to this board has page-size=4K and oob-size=224,
So ROM code expects boot-loaders to be flashed in BCH16 ECC scheme for
NAND boot.
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 107
1 file changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index df8798e..0027ea7 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -81,6 +81,27 @@
0x164 MUX_MODE0 /*
eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
;
};
+
+ nand_flash_x8: nand_flash_x8 {
+ pinctrl-single,pins =
+ 0x26C(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /*
spi2_cs0.gpio/eMMCorNANDsel */
+ 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)/*
gpmc_wpn.gpmc_wpn */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_wen.gpmc_wen */
+ 0x9c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_be0n_cle.gpmc_be0n_cle */
+ ;
+ };
};
i2c0 {
@@ -125,3 +146,89 @@
pinctrl-0 = mmc1_pins;
cd-gpios = gpio0 6 GPIO_ACTIVE_HIGH;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x8;
+ ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
+ nand@0,0 {
+ reg = 0 0 0; /* CS0, offset 0 */
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 8;
+ gpmc,device-width = 1;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 25;
+ gpmc,adv-wr-off-ns = 25;
+ gpmc,we-on-ns = 0;
+ gpmc,we-off-ns = 20;
+ gpmc,oe-on-ns = 3;
+ gpmc,oe-off-ns = 30;
+ gpmc,access-ns = 30;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-on-read = true;
+ gpmc,wait-on-write = true;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-access-ns = 40;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable. For
+* NAND flash this is equal to size of erase-block */
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ label = NAND.SPL;
+ reg = 0x 0x0004;
+ };
+ partition@1 {
+ label = NAND.SPL.backup1;
+ reg = 0x0004 0x0004;
+ };
+ partition@2 {
+ label = NAND.SPL.backup2;
+ reg = 0x0008 0x0004;
+ };
+ partition@3 {
+ label = NAND.SPL.backup3;
+ reg = 0x000C 0x0004
[PATCH v1 0/3] add parallel NAND support for TI's new OMAPx and AMxx platforms (Part-2)
This patch-set adds parallel NAND support on following TI platforms - AM335x (am335x-bone LT, am335x-boneblack): disabled by default - AM43xx (am437x-gp-evm) Pekon Gupta (3): ARM: dts: am335x-bone: add support for beaglebone NAND cape ARM: dts: am335x-boneblack: add support for beaglebone NAND cape ARM: dts: am437x-gp-evm: add support for parallel NAND flash arch/arm/boot/dts/am335x-bone.dts | 123 + arch/arm/boot/dts/am335x-boneblack.dts | 120 arch/arm/boot/dts/am437x-gp-evm.dts| 107 3 files changed, 350 insertions(+) -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v1 2/3] ARM: dts: am335x-boneblack: add support for beaglebone NAND cape
Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
Further information and datasheets can be found at [1] and [2]
* How to boot from NAND using Memory Expander + NAND Cape ? *
- Important: As BOOTSEL values are sampled only at POR, so after changing any
setting on SW2 (DIP switch), disconnect and reconnect all board power supply
(including mini-USB console port) to POR the beaglebone.
- Selection of ECC scheme
for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
for NAND cape(b), ROM code expects BCH16_HW ecc-scheme
- Selction of boot modes can be controlled via DIP switch(SW2) present on
Memory Expander cape.
SW2[SWITCH_BOOT] == OFF follow default boot order MMC- SPI - UART - USB
SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2)
So to flash NAND, first boot via MMC or other sources and then switch to
SW2[SWITCH_BOOT]=ON to boot from NAND Cape.
- For NAND boot following switch settings need to be followed
SW2[ 0] = ON (SYSBOOT[ 0]==0: NAND boot mode selected )
SW2[ 1] = ON (SYSBOOT[ 1]==0: -- do -- )
SW2[ 2] = OFF (SYSBOOT[ 2]==1: -- do -- )
SW2[ 3] = OFF (SYSBOOT[ 3]==1: -- do -- )
SW2[ 4] = ON (SYSBOOT[ 4]==0: -- do -- )
SW2[ 8] = OFF (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
SW2[ 9] = ON (SYSBOOT[ 9]==0: ECC done by ROM )
SW2[10] = ON (SYSBOOT[10]==0: Non Muxed device )
SW2[11] = ON (SYSBOOT[11]==0:-- do -- )
[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2]
http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-boneblack.dts | 120 +
1 file changed, 120 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts
b/arch/arm/boot/dts/am335x-boneblack.dts
index 6b71ad9..596cfec 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -60,6 +60,33 @@
0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 |
AM33XX_PIN_OUTPUT */
;
};
+ nand_flash_x16: nand_flash_x16 {
+ pinctrl-single,pins =
+ 0x00 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad0.gpmc_ad0 */
+ 0x04 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad1.gpmc_ad1 */
+ 0x08 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad2.gpmc_ad2 */
+ 0x0c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad3.gpmc_ad3 */
+ 0x10 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad4.gpmc_ad4 */
+ 0x14 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad5.gpmc_ad5 */
+ 0x18 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad6.gpmc_ad6 */
+ 0x1c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad7.gpmc_ad7 */
+ 0x20 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad8.gpmc_ad8 */
+ 0x24 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad9.gpmc_ad9 */
+ 0x28 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad10.gpmc_ad10
*/
+ 0x2c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad11.gpmc_ad11
*/
+ 0x30 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad12.gpmc_ad12
*/
+ 0x34 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad13.gpmc_ad13
*/
+ 0x38 (MUX_MODE0 | PIN_INPUT)/* gpmc_ad14.gpmc_ad14
*/
+ 0x3c (MUX_MODE0 | PIN_INPUT)/* gpmc_ad15.gpmc_ad15
*/
+ 0x70 (MUX_MODE0 | PIN_INPUT_PULLUP )/*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (MUX_MODE7 | PIN_OUTPUT_PULLUP)/*
gpmc_wpn.gpio0_30 */
+ 0x7c (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_wen.gpmc_wen */
+ 0x9c (MUX_MODE0 | PIN_OUTPUT) /*
gpmc_be0n_cle.gpmc_be0n_cle */
+ ;
+ };
};
lcdc {
@@ -76,3 +103,96 @@
status = okay;
};
};
+
+/*
+ * uncomment following to enable NAND cape support
+ * mmc2 {
+ * status = disabled;
+ * };
+ * elm {
+ * status = okay;
+ * };
+ * gpmc {
+ * status = okay;
+ * };
+ */
+gpmc {
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x16;
+ ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
+ nand@0,0
[PATCH v2 0/4] mtd: nand: omap: add support for BCH16_ECC
*changes v1 - v2* Rebased and Cleaned on following versions of pending patches (1) [PATCH v8 0/6] mtd: nand: omap: optimized chip-ecc.correct() for H/W ECC schemes http://lists.infradead.org/pipermail/linux-mtd/2014-February/052092.html (2) [PATCH v6 0/4] mtd: nand: omap: optimize chip-ecc.calculate() for H/W ECC schemes http://lists.infradead.org/pipermail/linux-mtd/2014-February/052272.html (3) [PATCH v5 0/4] mtd: nand: omap: optimize chip-ecc.hwctl() for H/W ECC schemes http://lists.infradead.org/pipermail/linux-mtd/2014-March/052327.html (4) [PATCH v6 0/4] mtd: devices: elm: add checks ELM H/W constrains, driver code cleanup http://lists.infradead.org/pipermail/linux-mtd/2014-March/052455.html Tested on Beaglebone-LT(white) NAND cape having NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224 *original v1* http://lists.infradead.org/pipermail/linux-mtd/2013-July/047562.html With increase in NAND flash densities and shrinking of technology NAND flash has become more suspectible to multiple bit-flips. Thus stronger ECC schemes are required for detecting and correcting multiple simultaneous bit-flips in same NAND page. But stronger ECC schemes have large ECC syndrome which require more space in OOB/Spare. This patch add support for BCH16 ecc-scheme on OMAP NAND driver: (a) BCH16 ecc-scheme can correct 16 bit-flips per 512Bytes of data. (b) BCH16 ecc-scheme generates 26-bytes of ECC syndrome / 512B. Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy following equation: OOBsize per page = 26 * (page-size / 512) Pekon Gupta (4): mtd: nand: omap: add support for BCH16_ECC - GPMC driver updates mtd: nand: omap: add support for BCH16_ECC - ELM driver updates mtd: nand: omap: add support for BCH16_ECC - NAND driver updates mtd: nand: omap: Documentation: How to select correct ECC scheme for your device ? .../devicetree/bindings/mtd/gpmc-nand.txt | 39 ++ arch/arm/mach-omap2/gpmc.c | 15 drivers/mtd/devices/elm.c | 42 ++ drivers/mtd/nand/omap2.c | 89 ++ include/linux/platform_data/elm.h | 3 +- include/linux/platform_data/mtd-nand-omap2.h | 5 ++ 6 files changed, 192 insertions(+), 1 deletion(-) -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 3/4] mtd: nand: omap: add support for BCH16_ECC - NAND driver updates
This patch add support for BCH16 ecc-scheme in OMAP NAND driver, by extending
following functions:
- omap_enable_hwecc (nand_chip-ecc.hwctl): configure GPMC controller
- omap_calculate_ecc_bch (nand_chip-ecc.calculate): fetch ECC signature from
GPMC controller
- omap_elm_correct_data (nand_chip-ecc.correct): detect and correct ECC
errors using ELM
(a) BCH16 ecc-scheme can detect and correct 16 bit-flips per 512Bytes of data.
(b) BCH16 ecc-scheme generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy the relation: OOBsize per page = 26 * (page-size / 512)
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 89
1 file changed, 89 insertions(+)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 369aee7..dd48b94 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1110,6 +1110,19 @@ static void __maybe_unused omap_enable_hwecc_bch(struct
mtd_info *mtd, int mode)
ecc_size1 = BCH_ECC_SIZE1;
}
break;
+ case OMAP_ECC_BCH16_CODE_HW:
+ bch_type = 0x2;
+ nsectors = chip-ecc.steps;
+ if (mode == NAND_ECC_READ) {
+ wr_mode = 0x01;
+ ecc_size0 = 52; /* ECC bits in nibbles per sector */
+ ecc_size1 = 0; /* non-ECC bits in nibbles per sector */
+ } else {
+ wr_mode = 0x01;
+ ecc_size0 = 0; /* extra bits in nibbles per sector */
+ ecc_size1 = 52; /* OOB bits in nibbles per sector */
+ }
+ break;
default:
return;
}
@@ -1158,6 +1171,7 @@ static int __maybe_unused omap_calculate_ecc_bch(struct
mtd_info *mtd,
struct gpmc_nand_regs *gpmc_regs = info-reg;
u8 *ecc_code;
unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
+ u32 val;
int i;
nsectors = ((readl(info-reg.gpmc_ecc_config) 4) 0x7) + 1;
@@ -1197,6 +1211,41 @@ static int __maybe_unused omap_calculate_ecc_bch(struct
mtd_info *mtd,
*ecc_code++ = ((bch_val1 4) 0xFF);
*ecc_code++ = ((bch_val1 0xF) 4);
break;
+ case OMAP_ECC_BCH16_CODE_HW:
+ val = readl(gpmc_regs-gpmc_bch_result6[i]);
+ ecc_code[0] = ((val 8) 0xFF);
+ ecc_code[1] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result5[i]);
+ ecc_code[2] = ((val 24) 0xFF);
+ ecc_code[3] = ((val 16) 0xFF);
+ ecc_code[4] = ((val 8) 0xFF);
+ ecc_code[5] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result4[i]);
+ ecc_code[6] = ((val 24) 0xFF);
+ ecc_code[7] = ((val 16) 0xFF);
+ ecc_code[8] = ((val 8) 0xFF);
+ ecc_code[9] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result3[i]);
+ ecc_code[10] = ((val 24) 0xFF);
+ ecc_code[11] = ((val 16) 0xFF);
+ ecc_code[12] = ((val 8) 0xFF);
+ ecc_code[13] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result2[i]);
+ ecc_code[14] = ((val 24) 0xFF);
+ ecc_code[15] = ((val 16) 0xFF);
+ ecc_code[16] = ((val 8) 0xFF);
+ ecc_code[17] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result1[i]);
+ ecc_code[18] = ((val 24) 0xFF);
+ ecc_code[19] = ((val 16) 0xFF);
+ ecc_code[20] = ((val 8) 0xFF);
+ ecc_code[21] = ((val 0) 0xFF);
+ val = readl(gpmc_regs-gpmc_bch_result0[i]);
+ ecc_code[22] = ((val 24) 0xFF);
+ ecc_code[23] = ((val 16) 0xFF);
+ ecc_code[24] = ((val 8) 0xFF);
+ ecc_code[25] = ((val 0) 0xFF);
+ break;
default:
return -EINVAL;
}
@@ -1223,6 +1272,8 @@ static int __maybe_unused omap_calculate_ecc_bch(struct
mtd_info *mtd,
/* Set 14th ECC byte as 0x0 for ROM compatibility */
ecc_calc[eccbytes - 1] = 0x0;
break;
+ case OMAP_ECC_BCH16_CODE_HW:
+ break;
default:
return -EINVAL;
}
@@ -1296,6
[PATCH v2 1/4] mtd: nand: omap: add support for BCH16_ECC - GPMC driver updates
This patch add support for BCH16_ECC in GPMC (controller) driver:
- extend configuration space to include BCH16 registers
- extend parsing of DT binding for selecting BCH16 ecc-scheme
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/mach-omap2/gpmc.c | 15 +++
include/linux/platform_data/mtd-nand-omap2.h | 5 +
2 files changed, 20 insertions(+)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index d24926e..8d2d7c2 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -68,6 +68,9 @@
#defineGPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
#defineGPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
#defineGPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
+#defineGPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
+#defineGPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
+#defineGPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
/* GPMC ECC control settings */
#define GPMC_ECC_CTRL_ECCCLEAR 0x100
@@ -666,6 +669,12 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int
cs)
GPMC_BCH_SIZE * i;
reg-gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
GPMC_BCH_SIZE * i;
+ reg-gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
+ i * GPMC_BCH_SIZE;
+ reg-gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
+ i * GPMC_BCH_SIZE;
+ reg-gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
+ i * GPMC_BCH_SIZE;
}
}
@@ -1401,6 +1410,12 @@ static int gpmc_probe_nand_child(struct platform_device
*pdev,
else
gpmc_nand_data-ecc_opt =
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
+ else if (!strcmp(s, bch16))
+ if (gpmc_nand_data-elm_of_node)
+ gpmc_nand_data-ecc_opt =
+ OMAP_ECC_BCH16_CODE_HW;
+ else
+ pr_err(%s: BCH16 requires ELM support\n, __func__);
else
pr_err(%s: ti,nand-ecc-opt invalid value\n, __func__);
diff --git a/include/linux/platform_data/mtd-nand-omap2.h
b/include/linux/platform_data/mtd-nand-omap2.h
index 3e9dd66..c2172e8 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -31,6 +31,8 @@ enum omap_ecc {
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
/* 8-bit ECC calculation by GPMC, Error detection by ELM */
OMAP_ECC_BCH8_CODE_HW,
+ /* 16-bit ECC calculation by GPMC, Error detection by ELM */
+ OMAP_ECC_BCH16_CODE_HW
};
struct gpmc_nand_regs {
@@ -50,6 +52,9 @@ struct gpmc_nand_regs {
void __iomem*gpmc_bch_result1[GPMC_BCH_NUM_REMAINDER];
void __iomem*gpmc_bch_result2[GPMC_BCH_NUM_REMAINDER];
void __iomem*gpmc_bch_result3[GPMC_BCH_NUM_REMAINDER];
+ void __iomem*gpmc_bch_result4[GPMC_BCH_NUM_REMAINDER];
+ void __iomem*gpmc_bch_result5[GPMC_BCH_NUM_REMAINDER];
+ void __iomem*gpmc_bch_result6[GPMC_BCH_NUM_REMAINDER];
};
struct omap_nand_platform_data {
--
1.8.5.1.163.gd7aced9
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[PATCH v2 4/4] mtd: nand: omap: Documentation: How to select correct ECC scheme for your device ?
- Adds DT binding property for BCH16 ECC scheme - Adds describes on factors which determine choice of ECC scheme for particular device Signed-off-by: Pekon Gupta pe...@ti.com --- .../devicetree/bindings/mtd/gpmc-nand.txt | 39 ++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt index 5e1f31b..f2dbb33 100644 --- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt @@ -28,6 +28,8 @@ Optional properties: ham1 1-bit Hamming ecc code bch4 4-bit BCH ecc code bch8 8-bit BCH ecc code + bch16 16-bit BCH ECC code + Refer below How to select correct ECC scheme for your device ? - ti,nand-xfer-type: A string setting the data transfer type. One of: @@ -90,3 +92,40 @@ Example for an AM33xx board: }; }; +How to select correct ECC scheme for your device ? +-- +Higher ECC scheme usually means better protection against bit-flips and +increased system lifetime. However, selection of ECC scheme is dependent +on various other factors like; +(1) Presence of supporting hardware engines on SoC. + Some legacy OMAP SoC do not have ELM h/w engine thus such SoC cannot + support BCHx_HW ECC schemes. But such SoC can support + BCHx_HW_DETECTION_SW ECC schemes which use s/w library with slight + CPU performance panalty only when too bit-flips are detected. +(2) Device parameters like OOBSIZE + Higher ECC schemes require more OOB/Spare area to store ECC. + So choice of ECC scheme is limited by NAND oobsize. In general + following expression help determine whether given device can + accomodate ECC syndrome or not: + 2 + (PAGESIZE / 512) * ECC_BYTES = OOBSIZE + where + OOBSIZE number of bytes in OOB/spare area + PAGESIZEnumber of bytes in main-area of device page + ECC_BYTES number of ECC bytes generated to protect + 512 bytes of data, which is: + '3' for HAM1_xx ecc schemes + '7' for BCH4_xx ecc schemes + '14' for BCH8_xx ecc schemes + '26' for BCH16_xx ecc schemes + + Example(a): For a device with PAGESIZE = 2048 and OOBSIZE = 64 + Number of spare/OOB bytes required for using BCH16 ecc-scheme + (2 + (2048 / 512) * 26) = 106 bytes is greater than OOBSIZE + (As per above table for BCH16 ecc-scheme, ECC_BYTES = 26) + Thus BCH16 cannot be supported on 2K NAND with OOBSIZE=64 bytes + + Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 + Number of spare/OOB bytes required for using BCH16 ecc-scheme + (2 + (2048 / 512) * 26) = 106 bytes is less than OOBSIZE + (As per above table for BCH16 ecc-scheme, ECC_BYTES = 26) + Thus BCH16 can be supported on 4K NAND with OOBSIZE=128 bytes -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/4] mtd: nand: omap: add support for BCH16_ECC - ELM driver updates
ELM hardware engine is used to detect ECC errors for BCHx ecc-schemes
(like BCH4/BCH8/BCH16). This patch extends configuration of ELM registers
for loading of BCH16 ECC syndrome.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/devices/elm.c | 42 +++
include/linux/platform_data/elm.h | 3 ++-
2 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/elm.c b/drivers/mtd/devices/elm.c
index 16e62ae..c6465d6 100644
--- a/drivers/mtd/devices/elm.c
+++ b/drivers/mtd/devices/elm.c
@@ -216,6 +216,34 @@ static void elm_load_syndrome(struct elm_info *info,
val = cpu_to_be32(*(u32 *) ecc[0]) 12;
elm_write_reg(info, offset, val);
break;
+ case BCH16_ECC:
+ val = ecc[25] 0 | ecc[24] 8 |
+ ecc[23] 16 | ecc[22] 24;
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = ecc[21] 0 | ecc[20] 8 |
+ ecc[19] 16 | ecc[18] 24;
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = ecc[17] 0 | ecc[16] 8 |
+ ecc[15] 16 | ecc[14] 24;
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = ecc[13] 0 | ecc[12] 8 |
+ ecc[11] 16 | ecc[10] 24;
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = ecc[9]0 | ecc[8]8 |
+ ecc[7] 16 | ecc[6] 24;
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = ecc[5]0 | ecc[4]8 |
+ ecc[3] 16 | ecc[2] 24;
+ elm_write_reg(info, offset, val);
+ offset += 4;
+ val = ecc[1]0 | ecc[0]8;
+ elm_write_reg(info, offset, val);
+ break;
default:
pr_err(invalid config bch_type\n);
}
@@ -438,6 +466,13 @@ static int elm_context_save(struct elm_info *info)
for (i = 0; i ERROR_VECTOR_MAX; i++) {
offset = i * SYNDROME_FRAGMENT_REG_SIZE;
switch (bch_type) {
+ case BCH16_ECC:
+ regs-elm_syndrome_fragment_6[i] = elm_read_reg(info,
+ ELM_SYNDROME_FRAGMENT_6 + offset);
+ regs-elm_syndrome_fragment_5[i] = elm_read_reg(info,
+ ELM_SYNDROME_FRAGMENT_5 + offset);
+ regs-elm_syndrome_fragment_4[i] = elm_read_reg(info,
+ ELM_SYNDROME_FRAGMENT_4 + offset);
case BCH8_ECC:
regs-elm_syndrome_fragment_3[i] = elm_read_reg(info,
ELM_SYNDROME_FRAGMENT_3 + offset);
@@ -476,6 +511,13 @@ static int elm_context_restore(struct elm_info *info)
for (i = 0; i ERROR_VECTOR_MAX; i++) {
offset = i * SYNDROME_FRAGMENT_REG_SIZE;
switch (bch_type) {
+ case BCH16_ECC:
+ elm_write_reg(info, ELM_SYNDROME_FRAGMENT_6 + offset,
+ regs-elm_syndrome_fragment_6[i]);
+ elm_write_reg(info, ELM_SYNDROME_FRAGMENT_5 + offset,
+ regs-elm_syndrome_fragment_5[i]);
+ elm_write_reg(info, ELM_SYNDROME_FRAGMENT_4 + offset,
+ regs-elm_syndrome_fragment_4[i]);
case BCH8_ECC:
elm_write_reg(info, ELM_SYNDROME_FRAGMENT_3 + offset,
regs-elm_syndrome_fragment_3[i]);
diff --git a/include/linux/platform_data/elm.h
b/include/linux/platform_data/elm.h
index dc0218d..51312f0 100644
--- a/include/linux/platform_data/elm.h
+++ b/include/linux/platform_data/elm.h
@@ -21,6 +21,7 @@
enum bch_ecc {
BCH4_ECC = 0,
BCH8_ECC,
+ BCH16_ECC
};
/* ELM support 8 error syndrome process */
@@ -38,7 +39,7 @@ struct elm_errorvec {
bool error_reported;
bool error_uncorrectable;
int error_count;
- int error_loc[ERROR_VECTOR_MAX];
+ int error_loc[16];
};
void elm_decode_bch_error_page(struct device *dev, u8 *ecc_calc
[PATCH v1 0/5] add parallel NAND support for TI's new OMAPx and AMxx platforms
This patch-set adds and updates parallel NAND support on following TI platforms - AM335x (am335x-evm) - DRA7xx (dra7-evm - AM43xx (am43X-epos-evm) In addition, following OMAP2+/GPMC patch is also added in this series as it add checks DRA7xx and AM43xxx platforms for non-DT kernels. ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms Minal Shah (1): ARM: dts: dra7: add support for parallel NAND flash Pekon Gupta (4): ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms and ECC schemes ARM: dts: am335x-evm: NAND: update MTD partition table ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt ARM: dts: am43xx: add support for parallel NAND flash arch/arm/boot/dts/am335x-evm.dts | 51 +++ arch/arm/boot/dts/am4372.dtsi| 24 +++ arch/arm/boot/dts/am43x-epos-evm.dts | 107 arch/arm/boot/dts/dra7-evm.dts | 117 +++ arch/arm/boot/dts/dra7.dtsi | 20 ++ arch/arm/boot/dts/omap3430-sdp.dts | 3 +- arch/arm/mach-omap2/gpmc-nand.c | 31 ++ 7 files changed, 315 insertions(+), 38 deletions(-) -- 1.8.5.1.163.gd7aced9 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v1 1/5] ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms and ECC schemes
This patch
- refactors gpmc_hwecc_bch_capable()
- add checks for new platforms like dra7xx, am43xx
- add checks for OMAP3 SoC, w.r.t. new ECC schemes spawned in following commit:
commit ac65caf514ec3e55e8d3d510ee37f80dd97418fe
ARM: OMAP2+: cleaned-up DT support of various ECC schemes
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/mach-omap2/gpmc-nand.c | 31 ---
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 174caec..4349e82 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -45,24 +45,31 @@ static struct platform_device gpmc_nand_device = {
static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
{
- /* support only OMAP3 class */
- if (!cpu_is_omap34xx() !soc_is_am33xx()) {
- pr_err(BCH ecc is not supported on this CPU\n);
+ /* platforms which support all ECC schemes */
+ if (soc_is_am33xx() || cpu_is_omap44xx() ||
+soc_is_omap54xx() || soc_is_dra7xx())
+ return 1;
+
+ /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes
+* which require H/W based ECC error detection */
+ if ((cpu_is_omap34xx() || cpu_is_omap3630())
+ ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
+(ecc_opt == OMAP_ECC_BCH8_CODE_HW)))
return 0;
- }
/*
* For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x=1
* and AM33xx derivates. Other chips may be added if confirmed to work.
*/
- if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW)
- (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))
- (!soc_is_am33xx())) {
- pr_err(BCH 4-bit mode is not supported on this CPU\n);
+ if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW)
+ (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)))
return 0;
- }
- return 1;
+ /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
+ if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
+ return 1;
+ else
+ return 0;
}
/* This function will go away once the device-tree convertion is complete */
@@ -133,8 +140,10 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
gpmc_update_nand_reg(gpmc_nand_data-reg, gpmc_nand_data-cs);
- if (!gpmc_hwecc_bch_capable(gpmc_nand_data-ecc_opt))
+ if (!gpmc_hwecc_bch_capable(gpmc_nand_data-ecc_opt)) {
+ dev_err(dev, Unsupported NAND ECC scheme selected\n);
return -EINVAL;
+ }
err = platform_device_register(gpmc_nand_device);
if (err 0) {
--
1.8.5.1.163.gd7aced9
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[PATCH v1 2/5] ARM: dts: am335x-evm: NAND: update MTD partition table
This patch has following updates, specific to MTD/NAND DT
- update MTD NAND partition table to keep compatibility between
different boards and mainline u-boot.
- prefix 'NAND.' in names of NAND device MTD partitions to differentiate them
from other MTD device partitions (like NOR and QSPI)
Partition_NamePartition_Size
/dev/mtd0 NAND.SPL 1 block-size*
/dev/mtd1 NAND.SPL.backup1 1 block-size*
/dev/mtd2 NAND.SPL.backup2 1 block-size*
/dev/mtd3 NAND.SPL.backup3 1 block-size*
/dev/mtd5 NAND.u-boot-spl-os2 block-size* [for falcon boot]
/dev/mtd4 NAND.u-boot 1 MB
/dev/mtd6 NAND.u-boot-env 1 block-size*
/dev/mtd7 NAND.u-boot-env.backup1 1 block-size*
/dev/mtd8 NAND.kernel till 0xA0
/dev/mtd9 NAND.file-system till end of device
* am335x-evm uses NAND device with block-size=128KiB
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-evm.dts | 48 +---
1 file changed, 25 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 7e6c64e..17c3cc0 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -460,50 +460,52 @@
gpmc,wait-monitoring-ns = 0;
gpmc,wr-access-ns = 40;
gpmc,wr-data-mux-bus-ns = 0;
-
- #address-cells = 1;
- #size-cells = 1;
elm_id = elm;
-
/* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable. For
+* NAND flash this is equal to size of erase-block */
+ #address-cells = 1;
+ #size-cells = 1;
partition@0 {
- label = SPL1;
+ label = NAND.SPL;
reg = 0x 0x2;
};
-
partition@1 {
- label = SPL2;
+ label = NAND.SPL.backup1;
reg = 0x0002 0x0002;
};
-
partition@2 {
- label = SPL3;
+ label = NAND.SPL.backup2;
reg = 0x0004 0x0002;
};
-
partition@3 {
- label = SPL4;
+ label = NAND.SPL.backup3;
reg = 0x0006 0x0002;
};
-
partition@4 {
- label = U-boot;
- reg = 0x0008 0x001e;
+ label = NAND.u-boot-spl;
+ reg = 0x0008 0x0004;
};
-
partition@5 {
- label = environment;
- reg = 0x0026 0x0002;
+ label = NAND.u-boot;
+ reg = 0x000C 0x0010;
};
-
partition@6 {
- label = Kernel;
- reg = 0x0028 0x0050;
+ label = NAND.u-boot-env;
+ reg = 0x001C 0x0002;
};
-
partition@7 {
- label = File-System;
- reg = 0x0078 0x0F88;
+ label = NAND.u-boot-env.backup1;
+ reg = 0x001E 0x0002;
+ };
+ partition@8 {
+ label = NAND.kernel;
+ reg = 0x0020 0x0080;
+ };
+ partition@9 {
+ label = NAND.file-system;
+ reg = 0x00A0 0x0F60;
};
};
};
--
1.8.5.1.163.gd7aced9
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[PATCH v1 4/5] ARM: dts: dra7: add support for parallel NAND flash
From: Minal Shah minal.s...@ti.com
DRA7xx platform has in-build GPMC and ELM h/w engines which can be used
for accessing externel NAND flash device. This patch:
- adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines
- adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm
*Important*
On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch
So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH
Signed-off-by: Minal Shah minal.s...@ti.com
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 117 +
arch/arm/boot/dts/dra7.dtsi| 20 +++
2 files changed, 137 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..81c5f7f 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,37 @@
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
;
};
+
+ nand_flash_x16: nand_flash_x16 {
+ /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
+* So NAND flash requires following switch settings:
+* SW5.9 (GPMC_WPN) = LOW
+* SW5.1 (NAND_BOOTn) = HIGH */
+ pinctrl-single,pins =
+ 0x0 0x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad0*/
+ 0x4 0x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad1*/
+ 0x8 0x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad2*/
+ 0xc 0x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad3*/
+ 0x100x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad4*/
+ 0x140x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad5*/
+ 0x180x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad6*/
+ 0x1c0x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad7*/
+ 0x200x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad8*/
+ 0x240x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad9*/
+ 0x280x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad10 */
+ 0x2c0x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad11 */
+ 0x300x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad12 */
+ 0x340x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad13 */
+ 0x380x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad14 */
+ 0x3c0x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_ad15 */
+ 0xD80x7 /* (PIN_INPUT | MUX_MODE0)
gpmc_wait0 */
+ 0xCC0x0 /* (PIN_OUTPUT | MUX_MODE0)
gpmc_wen*/
+ 0xB40x0 /* (PIN_OUTPUT | MUX_MODE0)
gpmc_csn0 */
+ 0xC40x0 /* (PIN_OUTPUT | MUX_MODE0)
gpmc_advn_ale */
+ 0xC80x0 /* (PIN_OUTPUT | MUX_MODE0)
gpmc_oen_ren */
+ 0xD00x0 /* (PIN_OUTPUT | MUX_MODE0)
gpmc_be0n_cle */
+ ;
+ };
};
i2c1 {
@@ -273,3 +304,89 @@
cpu0 {
cpu0-supply = smps123_reg;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x16;
+ ranges = 0 0 0x0800 0x1000;
+ nand@0,0 {
+ reg = 0 0 0;
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 16;
+ gpmc,device-width = 2;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 30;
+ gpmc,adv-wr-off-ns = 30;
+ gpmc,we-on-ns = 5;
+ gpmc,we-off-ns = 25;
+ gpmc,oe-on-ns = 2;
+ gpmc,oe-off-ns = 20;
+ gpmc,access-ns = 20;
+ gpmc,wr-access-ns = 40;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-on-read = true;
+ gpmc,wait-on-write = true;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable
[PATCH v1 3/5] ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt
This patch updated MTD/NAND DT node binding to replace deprecated bindings
as per following commit.
commit ac65caf514ec3e55e8d3d510ee37f80dd97418fe
ARM: OMAP2+: cleaned-up DT support of various ECC schemes
Also Refer: Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Reviewed-by: Felipe Balbi ba...@ti.com
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-evm.dts | 5 ++---
arch/arm/boot/dts/omap3430-sdp.dts | 3 +--
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 17c3cc0..07d61bb 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -434,9 +434,9 @@
ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
nand@0,0 {
reg = 0 0 0; /* CS0, offset 0 */
- nand-bus-width = 8;
ti,nand-ecc-opt = bch8;
- gpmc,device-nand = true;
+ ti,elm-id = elm;
+ nand-bus-width = 8;
gpmc,device-width = 1;
gpmc,sync-clk-ps = 0;
gpmc,cs-on-ns = 0;
@@ -460,7 +460,6 @@
gpmc,wait-monitoring-ns = 0;
gpmc,wr-access-ns = 40;
gpmc,wr-data-mux-bus-ns = 0;
- elm_id = elm;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts
b/arch/arm/boot/dts/omap3430-sdp.dts
index 281914e..d48c085 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -103,9 +103,8 @@
#address-cells = 1;
#size-cells = 1;
reg = 1 0 0x0800;
+ ti,nand-ecc-opt = ham1;
nand-bus-width = 8;
-
- ti,nand-ecc-opt = sw;
gpmc,cs-on-ns = 0;
gpmc,cs-rd-off-ns = 36;
gpmc,cs-wr-off-ns = 36;
--
1.8.5.1.163.gd7aced9
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[PATCH v1 5/5] ARM: dts: am43xx: add support for parallel NAND flash
This patch:
- enables GPMC h/w and ELM h/w engine for AM43xx devices (am4372.dtsi)
- adds pinmux and DT node for Micron 4K-paged x8 NAND device (MT29F4G08AB)
present on following boards:
am43x-epos-evm:
On this board, NAND Flash control lines are muxed with QSPI, Thus only
one of the two can be used at a time. Selection is controlled by:
(a) dynamically driving following GPIO pin from software
GPMC_A0(GPIO) == 0 NAND is selected (default)
GPMC_A0(GPIO) == 1 eMMC is selected
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am4372.dtsi| 24
arch/arm/boot/dts/am43x-epos-evm.dts | 107 +++
2 files changed, 131 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index c6bd4d9..489a4ab 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -689,6 +689,30 @@
edma 11;
dma-names = tx, rx;
};
+
+ elm: elm@4808 {
+ compatible = ti,am3352-elm;
+ reg = 0x4808 0x2000;
+ interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH;
+ ti,hwmods = elm;
+ clocks = l4ls_gclk;
+ clock-names = fck;
+ status = disabled;
+ };
+
+ gpmc: gpmc@5000 {
+ compatible = ti,am3352-gpmc;
+ ti,hwmods = gpmc;
+ clocks = l3s_gclk;
+ clock-names = fck;
+ reg = 0x5000 0x2000;
+ interrupts = GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH;
+ gpmc,num-cs = 7;
+ gpmc,num-waitpins = 2;
+ #address-cells = 2;
+ #size-cells = 1;
+ status = disabled;
+ };
};
};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index fbf9c4c..15aa708 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -79,6 +79,27 @@
0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST |
MUX_MODE0)/* i2c0_scl.i2c0_scl */
;
};
+
+ nand_flash_x8: nand_flash_x8 {
+ pinctrl-single,pins =
+ 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /*
gpmc_a0.SELQSPIorNAND/GPIO */
+ 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad7.gpmc_ad7 */
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)/*
gpmc_wpn.gpmc_wpn */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_wen.gpmc_wen */
+ 0x9c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_be0n_cle.gpmc_be0n_cle */
+ ;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -184,3 +205,89 @@
gpio3 {
status = okay;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x8;
+ ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
+ nand@0,0 {
+ reg = 0 0 0; /* CS0, offset 0 */
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 8;
+ gpmc,device-width = 1;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40; /* tCEA + tCHZ + 1 */
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0; /* cs-on-ns */
+ gpmc,adv-rd-off-ns = 25; /* min( tALH + tALS + 1
[PATCH] ARM: OMAP2+: gpmc: fix: DT ONENAND child nodes not probed when MTD_ONENAND is built as module
Fixes: commit 75d3625e0e86b2d8d77b4e9c6f685fd7ea0d5a96
ARM: OMAP2+: gpmc: add DT bindings for OneNAND
OMAP SoC(s) depend on GPMC controller driver to parse GPMC DT child nodes and
register them platform_device for ONENAND driver to probe later. However this
does
not happen if generic MTD_ONENAND framework is built as module
(CONFIG_MTD_ONENAND=m).
Therefore, when MTD/ONENAND and MTD/ONENAND/OMAP2 modules are loaded, they are
unable
to find any matching platform_device and remain un-binded. This causes on board
ONENAND flash to remain un-detected.
This patch causes GPMC controller to parse DT nodes when
CONFIG_MTD_ONENAND=y || CONFIG_MTD_ONENAND=m
CC: sta...@vger.kernel.org # 3.9.x+
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/mach-omap2/gpmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index c77a84b..ab43755 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1429,7 +1429,7 @@ static int gpmc_probe_nand_child(struct platform_device
*pdev,
}
#endif
-#ifdef CONFIG_MTD_ONENAND
+#if IS_ENABLED(CONFIG_MTD_ONENAND)
static int gpmc_probe_onenand_child(struct platform_device *pdev,
struct device_node *child)
{
--
1.8.1
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[PATCH] ARM: OMAP2+: gpmc: fix: DT NAND child nodes not probed when MTD_NAND is built as module
Fixes: commit bc6b1e7b86f5d8e4a6fc1c0189e64bba4077efe0
ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
OMAP SoC(s) depend on GPMC controller driver to parse GPMC DT child nodes and
register them platform_device for NAND driver to probe later. However this does
not happen if generic MTD_NAND framework is built as module (CONFIG_MTD_NAND=m).
Therefore, when MTD/NAND and MTD/NAND/OMAP2 modules are loaded, they are unable
to find any matching platform_device and remain un-binded. This causes on board
NAND flash to remain un-detected.
This patch causes GPMC controller to parse DT nodes when
CONFIG_MTD_NAND=y || CONFIG_MTD_NAND=m
CC: sta...@vger.kernel.org # 3.9.x+
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/mach-omap2/gpmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index d24926e..c77a84b 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1339,7 +1339,7 @@ static void __maybe_unused gpmc_read_timings_dt(struct
device_node *np,
of_property_read_bool(np, gpmc,time-para-granularity);
}
-#ifdef CONFIG_MTD_NAND
+#if IS_ENABLED(CONFIG_MTD_NAND)
static const char * const nand_xfer_types[] = {
[NAND_OMAP_PREFETCH_POLLED] = prefetch-polled,
--
1.8.1
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[PATCH v1 2/2] mtd: nand: omap: fix ecclayout to be in sync with u-boot NAND driver
| |
||| |
+++--+
Test1: flash ubi image from u-boot and boot the kernel
U-boot mw 0x8200 0xff u-boot.img size aligned to NAND block boundary
U-boot fatload mmc 0 0x8200 u-boot.img
U-boot nand erase u-boot_offset u-boot.img size
U-boot nand write 0x8200 u-boot_offset u-boot.img size
U-boot setenv bootargs 'console=ttyO0,115200n8 noinitrd mem=256M \
root=ubi0 rw rootfstype=ubifs ubi.mtd=mtdpart-of-rootfs,\
page-size ip=off init=/init'
U-boot bootm kernel_offset
Test2: update u-boot.img from kernel and re-boot
Kernel flash_erase /dev/mtdpart-of-u-boot 0 0
Kernel nandwrite -s 0 /dev/mtdpart-of-u-boot u-boot.img
Kernel reboot
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 33 +
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index bbdb5e8..e7836bf 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1633,6 +1633,7 @@ static int omap_nand_probe(struct platform_device *pdev)
int i;
dma_cap_mask_t mask;
unsignedsig;
+ unsignedoob_index;
struct resource *res;
struct mtd_part_parser_data ppdata = {};
@@ -1832,9 +1833,11 @@ static int omap_nand_probe(struct platform_device *pdev)
(mtd-writesize /
nand_chip-ecc.size);
if (nand_chip-options NAND_BUSWIDTH_16)
- ecclayout-eccpos[0]= BADBLOCK_MARKER_LENGTH;
+ oob_index = BADBLOCK_MARKER_LENGTH;
else
- ecclayout-eccpos[0]= 1;
+ oob_index = 1;
+ for (i = 0; i ecclayout-eccbytes; i++, oob_index++)
+ ecclayout-eccpos[i]= oob_index;
break;
case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
@@ -1851,7 +1854,13 @@ static int omap_nand_probe(struct platform_device *pdev)
ecclayout-eccbytes = nand_chip-ecc.bytes *
(mtd-writesize /
nand_chip-ecc.size);
- ecclayout-eccpos[0]= BADBLOCK_MARKER_LENGTH;
+ oob_index = BADBLOCK_MARKER_LENGTH;
+ for (i = 0; i ecclayout-eccbytes; i++, oob_index++) {
+ if ((i % nand_chip-ecc.bytes) || (i == 0))
+ ecclayout-eccpos[i] = oob_index;
+ else
+ ecclayout-eccpos[i] = ++oob_index;
+ }
/* software bch library is used for locating errors */
nand_chip-ecc.priv = nand_bch_init(mtd,
nand_chip-ecc.size,
@@ -1885,7 +1894,9 @@ static int omap_nand_probe(struct platform_device *pdev)
ecclayout-eccbytes = nand_chip-ecc.bytes *
(mtd-writesize /
nand_chip-ecc.size);
- ecclayout-eccpos[0]= BADBLOCK_MARKER_LENGTH;
+ oob_index = BADBLOCK_MARKER_LENGTH;
+ for (i = 0; i ecclayout-eccbytes; i++, oob_index++)
+ ecclayout-eccpos[i]= oob_index;
/* This ECC scheme requires ELM H/W block */
if (is_elm_present(info, pdata-elm_of_node, BCH4_ECC) 0) {
pr_err(nand: error: could not initialize ELM\n);
@@ -1913,7 +1924,13 @@ static int omap_nand_probe(struct platform_device *pdev)
ecclayout-eccbytes = nand_chip-ecc.bytes *
(mtd-writesize /
nand_chip-ecc.size);
- ecclayout-eccpos[0]= BADBLOCK_MARKER_LENGTH;
+ oob_index = BADBLOCK_MARKER_LENGTH;
+ for (i = 0; i ecclayout-eccbytes; i++, oob_index++) {
+ if ((i % nand_chip-ecc.bytes) || (i == 0))
+ ecclayout-eccpos[i] = oob_index;
+ else
+ ecclayout-eccpos[i] = ++oob_index;
+ }
/* software bch library is used for locating errors */
nand_chip-ecc.priv = nand_bch_init(mtd,
nand_chip-ecc.size,
@@ -1954,7 +1971,9
[PATCH v1 0/2] mtd: nand: omap: booting from NAND using u-boot
: http://lists.denx.de/pipermail/u-boot/2013-December/168506.html http://lists.denx.de/pipermail/u-boot/2013-December/169021.html Test1: flash ubi image from u-boot and boot the kernel U-boot mw 0x8200 0xff u-boot.img size aligned to NAND block boundary U-boot fatload mmc 0 0x8200 u-boot.img U-boot nand erase u-boot_offset u-boot.img size U-boot nand write 0x8200 u-boot_offset u-boot.img size U-boot setenv bootargs 'console=ttyO0,115200n8 noinitrd mem=256M \ root=ubi0 rw rootfstype=ubifs ubi.mtd=mtdpart-of-rootfs,\ page-size ip=off init=/init' U-boot bootm kernel_offset Test2: update u-boot.img from kernel and re-boot Kernel flash_erase /dev/mtdpart-of-u-boot 0 0 Kernel nandwrite -s 0 /dev/mtdpart-of-u-boot u-boot.img Kernel reboot Signed-off-by: Pekon Gupta pe...@ti.com --- drivers/mtd/nand/omap2.c | 33 + 1 file changed, 25 insertions(+), 8 deletions(-) Pekon Gupta (2): mtd: nand: omap: fix ecclayout-oobfree-offset mtd: nand: omap: fix ecclayout to be in sync with u-boot NAND driver drivers/mtd/nand/omap2.c | 50 1 file changed, 29 insertions(+), 21 deletions(-) -- 1.8.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v1 1/2] mtd: nand: omap: fix ecclayout-oobfree-offset
This patch updates starting offset for free bytes in OOB which can be used by
file-systems to store their metadata (like clean-marker in case of JFFS2).
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index f777250..bbdb5e8 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1835,8 +1835,6 @@ static int omap_nand_probe(struct platform_device *pdev)
ecclayout-eccpos[0]= BADBLOCK_MARKER_LENGTH;
else
ecclayout-eccpos[0]= 1;
- ecclayout-oobfree-offset = ecclayout-eccpos[0] +
- ecclayout-eccbytes;
break;
case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
@@ -1854,8 +1852,6 @@ static int omap_nand_probe(struct platform_device *pdev)
(mtd-writesize /
nand_chip-ecc.size);
ecclayout-eccpos[0]= BADBLOCK_MARKER_LENGTH;
- ecclayout-oobfree-offset = ecclayout-eccpos[0] +
- ecclayout-eccbytes;
/* software bch library is used for locating errors */
nand_chip-ecc.priv = nand_bch_init(mtd,
nand_chip-ecc.size,
@@ -1890,8 +1886,6 @@ static int omap_nand_probe(struct platform_device *pdev)
(mtd-writesize /
nand_chip-ecc.size);
ecclayout-eccpos[0]= BADBLOCK_MARKER_LENGTH;
- ecclayout-oobfree-offset = ecclayout-eccpos[0] +
- ecclayout-eccbytes;
/* This ECC scheme requires ELM H/W block */
if (is_elm_present(info, pdata-elm_of_node, BCH4_ECC) 0) {
pr_err(nand: error: could not initialize ELM\n);
@@ -1920,8 +1914,6 @@ static int omap_nand_probe(struct platform_device *pdev)
(mtd-writesize /
nand_chip-ecc.size);
ecclayout-eccpos[0]= BADBLOCK_MARKER_LENGTH;
- ecclayout-oobfree-offset = ecclayout-eccpos[0] +
- ecclayout-eccbytes;
/* software bch library is used for locating errors */
nand_chip-ecc.priv = nand_bch_init(mtd,
nand_chip-ecc.size,
@@ -1963,8 +1955,6 @@ static int omap_nand_probe(struct platform_device *pdev)
(mtd-writesize /
nand_chip-ecc.size);
ecclayout-eccpos[0]= BADBLOCK_MARKER_LENGTH;
- ecclayout-oobfree-offset = ecclayout-eccpos[0] +
- ecclayout-eccbytes;
break;
#else
pr_err(nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n);
@@ -1978,9 +1968,6 @@ static int omap_nand_probe(struct platform_device *pdev)
goto return_error;
}
- /* populate remaining ECC layout data */
- ecclayout-oobfree-length = mtd-oobsize - (BADBLOCK_MARKER_LENGTH +
- ecclayout-eccbytes);
for (i = 1; i ecclayout-eccbytes; i++)
ecclayout-eccpos[i] = ecclayout-eccpos[0] + i;
/* check if NAND device's OOB is enough to store ECC signatures */
@@ -1990,6 +1977,10 @@ static int omap_nand_probe(struct platform_device *pdev)
err = -EINVAL;
goto return_error;
}
+ /* populate remaining ECC layout data */
+ ecclayout-oobfree-offset = ecclayout-eccpos[ecclayout-eccbytes] + 1;
+ ecclayout-oobfree-length = mtd-oobsize - (BADBLOCK_MARKER_LENGTH +
+ ecclayout-eccbytes);
/* second phase scan */
if (nand_scan_tail(mtd)) {
--
1.8.1
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[PATCH v11 03/10] mtd: nand: omap: cleanup: replace local references with generic framework names
This patch updates following in omap_nand_probe() and omap_nand_remove()
- replaces info-nand with nand_chip (struct nand_chip *nand_chip)
- replaces info-mtd with mtd (struct mtd_info *mtd)
- white-space and formatting cleanup
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 112 ---
1 file changed, 57 insertions(+), 55 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 8d521aa..5596368 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1824,10 +1824,12 @@ static int omap_nand_probe(struct platform_device *pdev)
{
struct omap_nand_info *info;
struct omap_nand_platform_data *pdata;
+ struct mtd_info *mtd;
+ struct nand_chip*nand_chip;
int err;
int i, offset;
- dma_cap_mask_t mask;
- unsigned sig;
+ dma_cap_mask_t mask;
+ unsignedsig;
struct resource *res;
struct mtd_part_parser_data ppdata = {};
@@ -1846,17 +1848,16 @@ static int omap_nand_probe(struct platform_device *pdev)
spin_lock_init(info-controller.lock);
init_waitqueue_head(info-controller.wq);
- info-pdev = pdev;
-
+ info-pdev = pdev;
info-gpmc_cs = pdata-cs;
info-reg = pdata-reg;
-
- info-mtd.priv = info-nand;
- info-mtd.name = dev_name(pdev-dev);
- info-mtd.owner = THIS_MODULE;
-
- info-nand.options = pdata-devsize;
- info-nand.options |= NAND_SKIP_BBTSCAN;
+ mtd = info-mtd;
+ mtd-priv = info-nand;
+ mtd-name = dev_name(pdev-dev);
+ mtd-owner = THIS_MODULE;
+ nand_chip = info-nand;
+ nand_chip-options = pdata-devsize;
+ nand_chip-options |= NAND_SKIP_BBTSCAN;
#ifdef CONFIG_MTD_NAND_OMAP_BCH
info-of_node = pdata-of_node;
#endif
@@ -1877,16 +1878,16 @@ static int omap_nand_probe(struct platform_device *pdev)
goto out_free_info;
}
- info-nand.IO_ADDR_R = ioremap(info-phys_base, info-mem_size);
- if (!info-nand.IO_ADDR_R) {
+ nand_chip-IO_ADDR_R = ioremap(info-phys_base, info-mem_size);
+ if (!nand_chip-IO_ADDR_R) {
err = -ENOMEM;
goto out_release_mem_region;
}
- info-nand.controller = info-controller;
+ nand_chip-controller = info-controller;
- info-nand.IO_ADDR_W = info-nand.IO_ADDR_R;
- info-nand.cmd_ctrl = omap_hwcontrol;
+ nand_chip-IO_ADDR_W = nand_chip-IO_ADDR_R;
+ nand_chip-cmd_ctrl = omap_hwcontrol;
/*
* If RDY/BSY line is connected to OMAP then use the omap ready
@@ -1896,26 +1897,26 @@ static int omap_nand_probe(struct platform_device *pdev)
* device and read status register until you get a failure or success
*/
if (pdata-dev_ready) {
- info-nand.dev_ready = omap_dev_ready;
- info-nand.chip_delay = 0;
+ nand_chip-dev_ready = omap_dev_ready;
+ nand_chip-chip_delay = 0;
} else {
- info-nand.waitfunc = omap_wait;
- info-nand.chip_delay = 50;
+ nand_chip-waitfunc = omap_wait;
+ nand_chip-chip_delay = 50;
}
switch (pdata-xfer_type) {
case NAND_OMAP_PREFETCH_POLLED:
- info-nand.read_buf = omap_read_buf_pref;
- info-nand.write_buf = omap_write_buf_pref;
+ nand_chip-read_buf = omap_read_buf_pref;
+ nand_chip-write_buf = omap_write_buf_pref;
break;
case NAND_OMAP_POLLED:
- if (info-nand.options NAND_BUSWIDTH_16) {
- info-nand.read_buf = omap_read_buf16;
- info-nand.write_buf = omap_write_buf16;
+ if (nand_chip-options NAND_BUSWIDTH_16) {
+ nand_chip-read_buf = omap_read_buf16;
+ nand_chip-write_buf = omap_write_buf16;
} else {
- info-nand.read_buf = omap_read_buf8;
- info-nand.write_buf = omap_write_buf8;
+ nand_chip-read_buf = omap_read_buf8;
+ nand_chip-write_buf = omap_write_buf8;
}
break;
@@ -1944,8 +1945,8 @@ static int omap_nand_probe(struct platform_device *pdev)
err);
goto out_release_mem_region;
}
- info-nand.read_buf = omap_read_buf_dma_pref;
- info-nand.write_buf
[PATCH v11 04/10] mtd: nand: omap: use DT specified bus-width only for scanning NAND device
This patch:
- calls nand_scan_ident() using bus-width as passed by DT
- removes double calls to nand_scan_ident(), incase first call fails
then omap_nand_probe just returns error.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 5596368..f464321 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1856,7 +1856,6 @@ static int omap_nand_probe(struct platform_device *pdev)
mtd-name = dev_name(pdev-dev);
mtd-owner = THIS_MODULE;
nand_chip = info-nand;
- nand_chip-options = pdata-devsize;
nand_chip-options |= NAND_SKIP_BBTSCAN;
#ifdef CONFIG_MTD_NAND_OMAP_BCH
info-of_node = pdata-of_node;
@@ -1904,6 +1903,15 @@ static int omap_nand_probe(struct platform_device *pdev)
nand_chip-chip_delay = 50;
}
+ /* scan NAND device connected to chip controller */
+ nand_chip-options |= pdata-devsize NAND_BUSWIDTH_16;
+ if (nand_scan_ident(mtd, 1, NULL)) {
+ pr_err(nand device scan failed, may be bus-width mismatch\n);
+ err = -ENXIO;
+ goto out_release_mem_region;
+ }
+
+ /* re-populate low-level callbacks based on xfer modes */
switch (pdata-xfer_type) {
case NAND_OMAP_PREFETCH_POLLED:
nand_chip-read_buf = omap_read_buf_pref;
@@ -2011,17 +2019,6 @@ static int omap_nand_probe(struct platform_device *pdev)
}
}
- /* DIP switches on some boards change between 8 and 16 bit
-* bus widths for flash. Try the other width if the first try fails.
-*/
- if (nand_scan_ident(mtd, 1, NULL)) {
- nand_chip-options ^= NAND_BUSWIDTH_16;
- if (nand_scan_ident(mtd, 1, NULL)) {
- err = -ENXIO;
- goto out_release_mem_region;
- }
- }
-
/* rom code layout */
if (pdata-ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
--
1.8.1
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[PATCH v11 01/10] ARM: OMAP2+: cleaned-up DT support of various ECC schemes
OMAP NAND driver support multiple ECC scheme, which can used in different
flavours, depending on in-build Hardware engines present on SoC.
This patch updates following in DT bindings related to sectionion of ecc-schemes
- ti,elm-id: replaces elm_id (maintains backward compatibility)
- ti,nand-ecc-opts: selection of h/w or s/w implementation of an ecc-scheme
depends on ti,elm-id. (supported values ham1, bch4, and bch8)
- maintain backward compatibility to deprecated DT bindings (sw, hw, hw-romcode)
Below table shows different flavours of ecc-schemes supported by OMAP devices
+---+---+---+
| ECC scheme|ECC calculation|Error detection|
+---+---+---+
|OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W|
+---+---+---+
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W|
|(requires CONFIG_MTD_NAND_ECC_BCH) | | |
+---+---+---+
|OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) |
|(requires CONFIG_MTD_NAND_OMAP_BCH | | |
| ti,elm-id in DT) | | |
+---+---+---+
To optimize footprint of omap2-nand driver, selection of some ECC schemes
also require enabling following Kconfigs, in addition to setting appropriate
DT bindings
- Kconfig:CONFIG_MTD_NAND_ECC_BCHerror detection done in software
- Kconfig:CONFIG_MTD_NAND_OMAP_BCH error detection done by h/w engine
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Felipe Balbi ba...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
.../devicetree/bindings/mtd/gpmc-nand.txt | 8 +++-
arch/arm/mach-omap2/gpmc.c | 48 +++---
include/linux/platform_data/mtd-nand-omap2.h | 13 +-
3 files changed, 51 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index df338cb..bfe07e1 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -36,8 +36,12 @@ Optional properties:
prefetch-dma Prefetch enabled sDMA mode
prefetch-irq Prefetch enabled irq mode
- - elm_id: Specifies elm device node. This is required to support BCH
- error correction using ELM module.
+ - elm_id: deprecated use ti,elm-id instead
+ - ti,elm-id: Specifies phandle of the ELM devicetree node.
+ ELM is an on-chip hardware engine on TI SoC which is used for
+ locating ECC errors for BCHx algorithms. SoC devices which have
+ ELM hardware engines should specify this device node in .dtsi
+ Using ELM for ECC error correction frees some CPU cycles.
For inline partiton table parsing (optional):
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 579697a..c877129 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1341,14 +1341,6 @@ static void __maybe_unused gpmc_read_timings_dt(struct
device_node *np,
#ifdef CONFIG_MTD_NAND
-static const char * const nand_ecc_opts[] = {
- [OMAP_ECC_HAMMING_CODE_DEFAULT] = sw,
- [OMAP_ECC_HAMMING_CODE_HW] = hw,
- [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = hw-romcode,
- [OMAP_ECC_BCH4_CODE_HW] = bch4,
- [OMAP_ECC_BCH8_CODE_HW] = bch8,
-};
-
static const char * const nand_xfer_types[] = {
[NAND_OMAP_PREFETCH_POLLED] = prefetch-polled,
[NAND_OMAP_POLLED] = polled,
@@ -1378,13 +1370,41 @@ static int gpmc_probe_nand_child(struct platform_device
*pdev,
gpmc_nand_data-cs = val;
gpmc_nand_data-of_node = child;
- if (!of_property_read_string(child, ti,nand-ecc-opt, s))
- for (val = 0; val ARRAY_SIZE(nand_ecc_opts); val++)
- if (!strcasecmp(s, nand_ecc_opts[val])) {
- gpmc_nand_data-ecc_opt = val;
- break;
- }
+ /* Detect availability of ELM module */
+ gpmc_nand_data-elm_of_node = of_parse_phandle(child, ti,elm-id, 0);
+ if (gpmc_nand_data-elm_of_node == NULL)
+ gpmc_nand_data-elm_of_node =
+ of_parse_phandle(child, elm_id, 0);
+ if (gpmc_nand_data-elm_of_node == NULL)
+ pr_warn(%s: ti,elm-id property not found\n, __func__);
+
+ /* select ecc-scheme for NAND */
+ if (of_property_read_string(child, ti
[PATCH v11 07/10] mtd: nand: omap: use drivers/mtd/nand/nand_bch.c wrapper for BCH ECC instead of lib/bch.c
generic frame-work in mtd/nand/nand_bch.c is a wrapper above lib/bch.h which
encapsulates all control information specific to BCH ecc algorithm in software.
Thus this patch:
(1) replace omap specific implementations with equivalent wrapper in nand_bch.c
so that generic code from nand_bch.c is re-used. like;
omap3_correct_data_bch() - nand_bch_correct_data()
omap3_free_bch() - nand_bch_free()
(2) replace direct calls to lib/bch.c with wrapper functions defined in
nand_bch.c
init_bch() - nand_bch_init()
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 96 +++-
1 file changed, 22 insertions(+), 74 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index b6a08b2..93aa35c 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -25,7 +25,7 @@
#include linux/of.h
#include linux/of_device.h
-#include linux/bch.h
+#include linux/mtd/nand_bch.h
#include linux/platform_data/elm.h
#include linux/platform_data/mtd-nand-omap2.h
@@ -140,7 +140,6 @@
#define BCH_ECC_SIZE1 0x20/* ecc_size1 = 32 */
#define BADBLOCK_MARKER_LENGTH 2
-#define OMAP_ECC_BCH8_POLYNOMIAL 0x201b
#ifdef CONFIG_MTD_NAND_OMAP_BCH
static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
@@ -173,7 +172,6 @@ struct omap_nand_info {
int buf_len;
struct gpmc_nand_regs reg;
/* fields specific for BCHx_HW ECC scheme */
- struct bch_control *bch;
boolis_elm_used;
struct device *elm_dev;
struct device_node *of_node;
@@ -1507,43 +1505,7 @@ static int omap_elm_correct_data(struct mtd_info *mtd,
u_char *data,
return stat;
}
-#endif /* CONFIG_MTD_NAND_OMAP_BCH */
-#ifdef CONFIG_MTD_NAND_ECC_BCH
-/**
- * omap3_correct_data_bch - Decode received data and correct errors
- * @mtd: MTD device structure
- * @data: page data
- * @read_ecc: ecc read from nand flash
- * @calc_ecc: ecc read from HW ECC registers
- */
-static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data,
- u_char *read_ecc, u_char *calc_ecc)
-{
- int i, count;
- /* cannot correct more than 8 errors */
- unsigned int errloc[8];
- struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
- mtd);
-
- count = decode_bch(info-bch, NULL, 512, read_ecc, calc_ecc, NULL,
- errloc);
- if (count 0) {
- /* correct errors */
- for (i = 0; i count; i++) {
- /* correct data only, not ecc bytes */
- if (errloc[i] 8*512)
- data[errloc[i]/8] ^= 1 (errloc[i] 7);
- pr_debug(corrected bitflip %u\n, errloc[i]);
- }
- } else if (count 0) {
- pr_err(ecc unrecoverable error\n);
- }
- return count;
-}
-#endif /* CONFIG_MTD_NAND_ECC_BCH */
-
-#ifdef CONFIG_MTD_NAND_OMAP_BCH
/**
* omap_write_page_bch - BCH ecc based write page function for entire page
* @mtd: mtd info structure
@@ -1660,28 +1622,6 @@ static int is_elm_present(struct omap_nand_info *info,
}
#endif /* CONFIG_MTD_NAND_ECC_BCH */
-#ifdef CONFIG_MTD_NAND_ECC_BCH
-/**
- * omap3_free_bch - Release BCH ecc resources
- * @mtd: MTD device structure
- */
-static void omap3_free_bch(struct mtd_info *mtd)
-{
- struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
- mtd);
- if (info-bch) {
- free_bch(info-bch);
- info-bch = NULL;
- }
-}
-
-#else
-
-static void omap3_free_bch(struct mtd_info *mtd)
-{
-}
-#endif /* CONFIG_MTD_NAND_ECC_BCH */
-
static int omap_nand_probe(struct platform_device *pdev)
{
struct omap_nand_info *info;
@@ -1714,13 +1654,13 @@ static int omap_nand_probe(struct platform_device *pdev)
info-pdev = pdev;
info-gpmc_cs = pdata-cs;
info-reg = pdata-reg;
- info-bch = NULL;
info-of_node = pdata-of_node;
mtd = info-mtd;
mtd-priv = info-nand;
mtd-name = dev_name(pdev-dev);
mtd-owner = THIS_MODULE;
nand_chip = info-nand;
+ nand_chip-ecc.priv = NULL;
nand_chip-options |= NAND_SKIP_BBTSCAN;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1903,7 +1843,7 @@ static int omap_nand_probe(struct platform_device *pdev)
nand_chip-ecc.bytes= 7;
nand_chip-ecc.strength = 4;
nand_chip
[PATCH v11 02/10] mtd: nand: omap: combine different flavours of 1-bit hamming ecc schemes
OMAP NAND driver currently supports multiple flavours of 1-bit Hamming
ecc-scheme, like:
- OMAP_ECC_HAMMING_CODE_DEFAULT
1-bit hamming ecc code using software library
- OMAP_ECC_HAMMING_CODE_HW
1-bit hamming ecc-code using GPMC h/w engine
- OMAP_ECC_HAMMING_CODE_HW_ROMCODE
1-bit hamming ecc-code using GPMC h/w engin with ecc-layout compatible
to ROM code.
This patch combines above multiple ecc-schemes into single implementation:
- OMAP_ECC_HAM1_CODE_HW
1-bit hamming ecc-code using GPMC h/w engine with ROM-code compatible
ecc-layout.
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Felipe Balbi ba...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 8
arch/arm/mach-omap2/board-flash.c | 2 +-
drivers/mtd/nand/omap2.c| 9 +++--
include/linux/platform_data/mtd-nand-omap2.h| 7 +--
4 files changed, 9 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index bfe07e1..5e1f31b 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -22,10 +22,10 @@ Optional properties:
width of 8 is assumed.
- ti,nand-ecc-opt:A string setting the ECC layout to use. One of:
-
- swSoftware method (default)
- hwHardware method
- hw-romcodegpmc hamming mode method romcode layout
+ swdeprecated use ham1 instead
+ hwdeprecated use ham1 instead
+ hw-romcodedeprecated use ham1 instead
+ ham1 1-bit Hamming ecc code
bch4 4-bit BCH ecc code
bch8 8-bit BCH ecc code
diff --git a/arch/arm/mach-omap2/board-flash.c
b/arch/arm/mach-omap2/board-flash.c
index fc20a61..ac82512 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8
nr_parts, u8 cs,
board_nand_data.nr_parts= nr_parts;
board_nand_data.devsize = nand_type;
- board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
+ board_nand_data.ecc_opt = OMAP_ECC_BCH8_CODE_HW;
gpmc_nand_init(board_nand_data, gpmc_t);
}
#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 4ecf0e5..8d521aa 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1993,10 +1993,7 @@ static int omap_nand_probe(struct platform_device *pdev)
}
/* select the ecc type */
- if (pdata-ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
- info-nand.ecc.mode = NAND_ECC_SOFT;
- else if ((pdata-ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
- (pdata-ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
+ if (pdata-ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
info-nand.ecc.bytes= 3;
info-nand.ecc.size = 512;
info-nand.ecc.strength = 1;
@@ -2025,7 +2022,7 @@ static int omap_nand_probe(struct platform_device *pdev)
}
/* rom code layout */
- if (pdata-ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
+ if (pdata-ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
if (info-nand.options NAND_BUSWIDTH_16)
offset = 2;
@@ -2033,7 +2030,7 @@ static int omap_nand_probe(struct platform_device *pdev)
offset = 1;
info-nand.badblock_pattern = bb_descrip_flashbased;
}
- omap_oobinfo.eccbytes = 3 * (info-mtd.oobsize/16);
+ omap_oobinfo.eccbytes = 3 * (info-mtd.writesize / 512);
for (i = 0; i omap_oobinfo.eccbytes; i++)
omap_oobinfo.eccpos[i] = i+offset;
diff --git a/include/linux/platform_data/mtd-nand-omap2.h
b/include/linux/platform_data/mtd-nand-omap2.h
index e4128f1..4da5bfa 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -23,13 +23,8 @@ enum nand_io {
};
enum omap_ecc {
- /* 1-bit ecc: stored at end of spare area */
- OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
- OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
- /* 1-bit ecc: stored at beginning of spare area as romcode */
- OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method romcode layout */
/* 1-bit ECC calculation by GPMC, Error detection by Software */
- OMAP_ECC_HAM1_CODE_HW,
+ OMAP_ECC_HAM1_CODE_HW = 0,
/* 4-bit ECC calculation by GPMC, Error detection
[PATCH v11 06/10] mtd: nand: omap: clean-up ecc layout for BCH ecc schemes
In current implementation omap3_init_bch_tail() is a common function to
define ecc layout for different BCHx ecc schemes.This patch:
(1) removes omap3_init_bch_tail() and defines ecc layout for individual
ecc-schemes along with populating their nand_chip-ecc data in
omap_nand_probe(). This improves the readability and scalability of
code for add new ecc schemes in future.
(2) removes 'struct nand_bbt_descr bb_descrip_flashbased' because default
nand_bbt_descr in nand_bbt.c matches the same (.len=1 for x8 devices).
(3) add the check to see if NAND device has enough OOB/Spare bytes to
store ECC signature of whole page, as defined by ecc-scheme.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 161 ++-
1 file changed, 62 insertions(+), 99 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 86ce48b..b6a08b2 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -139,6 +139,7 @@
#define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
#define BCH_ECC_SIZE1 0x20/* ecc_size1 = 32 */
+#define BADBLOCK_MARKER_LENGTH 2
#define OMAP_ECC_BCH8_POLYNOMIAL 0x201b
#ifdef CONFIG_MTD_NAND_OMAP_BCH
@@ -149,17 +150,6 @@ static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd,
0x41, 0xbc, 0x10};
/* oob info generated runtime depending on ecc algorithm and layout selected */
static struct nand_ecclayout omap_oobinfo;
-/* Define some generic bad / good block scan pattern which are used
- * while scanning a device for factory marked good / bad blocks
- */
-static uint8_t scan_ff_pattern[] = { 0xff };
-static struct nand_bbt_descr bb_descrip_flashbased = {
- .options = NAND_BBT_SCANALLPAGES,
- .offs = 0,
- .len = 1,
- .pattern = scan_ff_pattern,
-};
-
struct omap_nand_info {
struct nand_hw_control controller;
@@ -184,7 +174,6 @@ struct omap_nand_info {
struct gpmc_nand_regs reg;
/* fields specific for BCHx_HW ECC scheme */
struct bch_control *bch;
- struct nand_ecclayout ecclayout;
boolis_elm_used;
struct device *elm_dev;
struct device_node *of_node;
@@ -1686,65 +1675,8 @@ static void omap3_free_bch(struct mtd_info *mtd)
}
}
-/**
- * omap3_init_bch_tail - Build an oob layout for BCH ECC correction.
- * @mtd: MTD device structure
- */
-static int omap3_init_bch_tail(struct mtd_info *mtd)
-{
- int i, steps, offset;
- struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
- mtd);
- struct nand_ecclayout *layout = info-ecclayout;
-
- /* build oob layout */
- steps = mtd-writesize/info-nand.ecc.size;
- layout-eccbytes = steps*info-nand.ecc.bytes;
-
- /* do not bother creating special oob layouts for small page devices */
- if (mtd-oobsize 64) {
- pr_err(BCH ecc is not supported on small page devices\n);
- goto fail;
- }
-
- /* reserve 2 bytes for bad block marker */
- if (layout-eccbytes+2 mtd-oobsize) {
- pr_err(no oob layout available for oobsize %d eccbytes %u\n,
- mtd-oobsize, layout-eccbytes);
- goto fail;
- }
-
- /* ECC layout compatible with RBL for BCH8 */
- if (info-is_elm_used (info-nand.ecc.bytes == BCH8_SIZE))
- offset = 2;
- else
- offset = mtd-oobsize - layout-eccbytes;
-
- /* put ecc bytes at oob tail */
- for (i = 0; i layout-eccbytes; i++)
- layout-eccpos[i] = offset + i;
-
- if (info-is_elm_used (info-nand.ecc.bytes == BCH8_SIZE))
- layout-oobfree[0].offset = 2 + layout-eccbytes * steps;
- else
- layout-oobfree[0].offset = 2;
-
- layout-oobfree[0].length = mtd-oobsize-2-layout-eccbytes;
- info-nand.ecc.layout = layout;
-
- if (!(info-nand.options NAND_BUSWIDTH_16))
- info-nand.badblock_pattern = bb_descrip_flashbased;
- return 0;
-fail:
- omap3_free_bch(mtd);
- return -1;
-}
-
#else
-static int omap3_init_bch_tail(struct mtd_info *mtd)
-{
- return -1;
-}
+
static void omap3_free_bch(struct mtd_info *mtd)
{
}
@@ -1756,8 +1688,9 @@ static int omap_nand_probe(struct platform_device *pdev)
struct omap_nand_platform_data *pdata;
struct mtd_info *mtd;
struct nand_chip*nand_chip;
+ struct nand_ecclayout *ecclayout;
int err;
- int i, offset;
+ int i;
dma_cap_mask_t mask;
unsignedsig;
struct resource
[PATCH v11 05/10] mtd:nand:omap2: clean-up BCHx_HW and BCHx_SW ECC configurations in device_probe
current implementation in omap3_init_bch() has some redundant code like:
(1) omap3_init_bch() re-probes the DT-binding to detect presence of ELM h/w
engine on SoC. And based on that it selects implemetation of ecc-scheme.
However, this is already done as part of GPMC DT parsing.
(2) As omap3_init_bch() serves as common function for configuring all types of
BCHx ecc-schemes, so there are multiple levels of redudant if..then..else
checks while populating nand_chip-ecc.
This patch make following changes to OMAP NAND driver:
(1) removes omap3_init_bch(): each ecc-scheme is individually configured in
omap_nand_probe() there by removing redundant if..then..else checks.
(2) adds is_elm_present(): re-probing of ELM device via DT is not required as
it's done in GPMC driver probe. Thus is_elm_present() just initializes ELM
driver with NAND probe data, when ecc-scheme with h/w based error-detection
is used.
(3) separates out configuration of different flavours of BCH4 and BCH8
ecc-schemes as given in below table
(4) conditionally compiles callbacks implementations of ecc.hwctl(),
ecc.calculate(), ecc.correct() to avoid warning of un-used functions.
+---+---+---+
| ECC scheme|ECC calculation|Error detection|
+---+---+---+
|OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W|
+---+---+---+
|OMAP_ECC_BCH4_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.c)|
| (needs CONFIG_MTD_NAND_ECC_BCH) | | |
| | | |
|OMAP_ECC_BCH4_CODE_HW |H/W (GPMC) |H/W (ELM) |
| (needs CONFIG_MTD_NAND_OMAP_BCH | | |
|ti,elm-id) | | |
+---+---+---+
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.c)|
| (needs CONFIG_MTD_NAND_ECC_BCH) | | |
| | | |
|OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) |
| (needs CONFIG_MTD_NAND_OMAP_BCH | | |
|ti,elm-id) | | |
+---+---+---+
- 'CONFIG_MTD_NAND_ECC_BCH' is generic KConfig required to build lib/bch.c
which is required for ECC error detection done in software.
(mainly used for legacy platforms which do not have on-chip ELM engine)
- 'CONFIG_MTD_NAND_OMAP_BCH' is OMAP specific Kconfig to detemine presence
on ELM h/w engine on SoC.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 281 ++-
1 file changed, 158 insertions(+), 123 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index f464321..86ce48b 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -25,10 +25,8 @@
#include linux/of.h
#include linux/of_device.h
-#ifdef CONFIG_MTD_NAND_OMAP_BCH
#include linux/bch.h
#include linux/platform_data/elm.h
-#endif
#include linux/platform_data/mtd-nand-omap2.h
@@ -141,6 +139,8 @@
#define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
#define BCH_ECC_SIZE1 0x20/* ecc_size1 = 32 */
+#define OMAP_ECC_BCH8_POLYNOMIAL 0x201b
+
#ifdef CONFIG_MTD_NAND_OMAP_BCH
static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
0xac, 0x6b, 0xff, 0x99, 0x7b};
@@ -182,14 +182,12 @@ struct omap_nand_info {
u_char *buf;
int buf_len;
struct gpmc_nand_regs reg;
-
-#ifdef CONFIG_MTD_NAND_OMAP_BCH
+ /* fields specific for BCHx_HW ECC scheme */
struct bch_control *bch;
struct nand_ecclayout ecclayout;
boolis_elm_used;
struct device *elm_dev;
struct device_node *of_node;
-#endif
};
/**
@@ -1058,8 +1056,7 @@ static int omap_dev_ready(struct mtd_info *mtd)
}
}
-#ifdef CONFIG_MTD_NAND_OMAP_BCH
-
+#if defined(CONFIG_MTD_NAND_ECC_BCH) || defined(CONFIG_MTD_NAND_OMAP_BCH)
/**
* omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
* @mtd: MTD device structure
@@ -1140,7 +1137,9 @@ static void omap3_enable_hwecc_bch(struct mtd_info *mtd,
int mode)
/* Clear ecc and enable bits */
writel(ECCCLEAR | ECC1, info-reg.gpmc_ecc_control);
}
+#endif
+#ifdef CONFIG_MTD_NAND_ECC_BCH
/**
* omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC
[PATCH v11 00/10] [PATCH v10 00/10] mtd:nand:omap2: clean-up of supported ECC schemes
| +---+---+---+ |OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W| +---+---+---+ |OMAP_ECC_BCH4_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.c)| | (needs CONFIG_MTD_NAND_ECC_BCH) | | | | | | | |OMAP_ECC_BCH4_CODE_HW |H/W (GPMC) |H/W (ELM) | | (needs CONFIG_MTD_NAND_OMAP_BCH | | | |ti,elm-id) | | | +---+---+---+ |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.c)| | (needs CONFIG_MTD_NAND_ECC_BCH) | | | | | | | |OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) | | (needs CONFIG_MTD_NAND_OMAP_BCH | | | |ti,elm-id) | | | +---+---+---+ Pekon Gupta (10): ARM: OMAP2+: cleaned-up DT support of various ECC schemes mtd: nand: omap: combine different flavours of 1-bit hamming ecc schemes mtd: nand: omap: cleanup: replace local references with generic framework names mtd: nand: omap: use DT specified bus-width only for scanning NAND device mtd:nand:omap2: clean-up BCHx_HW and BCHx_SW ECC configurations in device_probe mtd: nand: omap: clean-up ecc layout for BCH ecc schemes mtd: nand: omap: use drivers/mtd/nand/nand_bch.c wrapper for BCH ECC instead of lib/bch.c ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt mtd: nand: omap: updated devm_xx for all resource allocation and free calls mtd: nand: omap: remove selection of BCH ecc-scheme via KConfig .../devicetree/bindings/mtd/gpmc-nand.txt | 16 +- arch/arm/boot/dts/am335x-evm.dts | 3 +- arch/arm/boot/dts/omap3430-sdp.dts | 2 +- arch/arm/mach-omap2/board-flash.c | 2 +- arch/arm/mach-omap2/gpmc.c | 48 +- drivers/mtd/nand/Kconfig | 40 +- drivers/mtd/nand/omap2.c | 641 + include/linux/platform_data/mtd-nand-omap2.h | 18 +- 8 files changed, 348 insertions(+), 422 deletions(-) -- 1.8.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v11 09/10] mtd: nand: omap: updated devm_xx for all resource allocation and free calls
Managed Device Resource or devm_xx calls takes care of automatic freeing
of the resource in case of:
- failure during driver probe
- failure during resource allocation
- detaching or unloading of driver module (rmmod)
Reference: Documentation/driver-model/devres.txt
Though OMAP NAND driver handles freeing of resource allocation in most of
the cases, but using devm_xx provides more clean and effortless approach
to handle all such cases.
- simplifies label for exiting probe during error
s/out_release_mem_region/return_error
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 85
1 file changed, 35 insertions(+), 50 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 93aa35c..ec40b8d 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1642,7 +1642,8 @@ static int omap_nand_probe(struct platform_device *pdev)
return -ENODEV;
}
- info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
+ info = devm_kzalloc(pdev-dev, sizeof(struct omap_nand_info),
+ GFP_KERNEL);
if (!info)
return -ENOMEM;
@@ -1667,22 +1668,23 @@ static int omap_nand_probe(struct platform_device *pdev)
if (res == NULL) {
err = -EINVAL;
dev_err(pdev-dev, error getting memory resource\n);
- goto out_free_info;
+ goto return_error;
}
info-phys_base = res-start;
info-mem_size = resource_size(res);
- if (!request_mem_region(info-phys_base, info-mem_size,
- pdev-dev.driver-name)) {
+ if (!devm_request_mem_region(pdev-dev, info-phys_base,
+ info-mem_size, pdev-dev.driver-name)) {
err = -EBUSY;
- goto out_free_info;
+ goto return_error;
}
- nand_chip-IO_ADDR_R = ioremap(info-phys_base, info-mem_size);
+ nand_chip-IO_ADDR_R = devm_ioremap(pdev-dev, info-phys_base,
+ info-mem_size);
if (!nand_chip-IO_ADDR_R) {
err = -ENOMEM;
- goto out_release_mem_region;
+ goto return_error;
}
nand_chip-controller = info-controller;
@@ -1710,14 +1712,14 @@ static int omap_nand_probe(struct platform_device *pdev)
if (nand_scan_ident(mtd, 1, NULL)) {
pr_err(nand device scan failed, may be bus-width mismatch\n);
err = -ENXIO;
- goto out_release_mem_region;
+ goto return_error;
}
/* check for small page devices */
if ((mtd-oobsize 64) (pdata-ecc_opt != OMAP_ECC_HAM1_CODE_HW)) {
pr_err(small page devices are not supported\n);
err = -EINVAL;
- goto out_release_mem_region;
+ goto return_error;
}
/* re-populate low-level callbacks based on xfer modes */
@@ -1745,7 +1747,7 @@ static int omap_nand_probe(struct platform_device *pdev)
if (!info-dma) {
dev_err(pdev-dev, DMA engine request failed\n);
err = -ENXIO;
- goto out_release_mem_region;
+ goto return_error;
} else {
struct dma_slave_config cfg;
@@ -1760,7 +1762,7 @@ static int omap_nand_probe(struct platform_device *pdev)
if (err) {
dev_err(pdev-dev, DMA engine slave config
failed: %d\n,
err);
- goto out_release_mem_region;
+ goto return_error;
}
nand_chip-read_buf = omap_read_buf_dma_pref;
nand_chip-write_buf = omap_write_buf_dma_pref;
@@ -1772,30 +1774,32 @@ static int omap_nand_probe(struct platform_device *pdev)
if (info-gpmc_irq_fifo = 0) {
dev_err(pdev-dev, error getting fifo irq\n);
err = -ENODEV;
- goto out_release_mem_region;
+ goto return_error;
}
- err = request_irq(info-gpmc_irq_fifo, omap_nand_irq,
- IRQF_SHARED, gpmc-nand-fifo, info);
+ err = devm_request_irq(pdev-dev, info-gpmc_irq_fifo,
+ omap_nand_irq, IRQF_SHARED,
+ gpmc-nand-fifo, info);
if (err) {
dev_err(pdev-dev, requesting irq(%d) error:%d,
info-gpmc_irq_fifo, err);
info-gpmc_irq_fifo = 0;
- goto out_release_mem_region;
+ goto
[PATCH v11 10/10] mtd: nand: omap: remove selection of BCH ecc-scheme via KConfig
With OMAP NAND driver updates, selection of ecc-scheme: *DT enabled kernel* depends on ti,nand-ecc-opt and ti,elm-id DT bindings. *Non DT enabled kernel* depends on elm_dev and ecc-scheme passed along with platform-data from board file. So, selection of ecc-scheme (BCH8 or BCH4) from KConfig can be removed Signed-off-by: Pekon Gupta pe...@ti.com --- drivers/mtd/nand/Kconfig | 40 ++-- 1 file changed, 6 insertions(+), 34 deletions(-) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index d885298..93ae6a6 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -96,43 +96,15 @@ config MTD_NAND_OMAP2 config MTD_NAND_OMAP_BCH depends on MTD_NAND MTD_NAND_OMAP2 ARCH_OMAP3 - tristate Enable support for hardware BCH error correction + tristate Support hardware based BCH error correction default n select BCH - select BCH_CONST_PARAMS help -Support for hardware BCH error correction. - -choice - prompt BCH error correction capability - depends on MTD_NAND_OMAP_BCH - -config MTD_NAND_OMAP_BCH8 - bool 8 bits / 512 bytes (recommended) - help -Support correcting up to 8 bitflips per 512-byte block. -This will use 13 bytes of spare area per 512 bytes of page data. -This is the recommended mode, as 4-bit mode does not work -on some OMAP3 revisions, due to a hardware bug. - -config MTD_NAND_OMAP_BCH4 - bool 4 bits / 512 bytes - help -Support correcting up to 4 bitflips per 512-byte block. -This will use 7 bytes of spare area per 512 bytes of page data. -Note that this mode does not work on some OMAP3 revisions, due to a -hardware bug. Please check your OMAP datasheet before selecting this -mode. - -endchoice - -if MTD_NAND_OMAP_BCH -config BCH_CONST_M - default 13 -config BCH_CONST_T - default 4 if MTD_NAND_OMAP_BCH4 - default 8 if MTD_NAND_OMAP_BCH8 -endif + This config enables the ELM hardware engine, which can be used to + locate and correct errors when using BCH ECC scheme. This offloads + the cpu from doing ECC error searching and correction. However some + legacy OMAP families like OMAP2xxx, OMAP3xxx do not have ELM engine + so they should not enable this config symbol. config MTD_NAND_IDS tristate -- 1.8.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v11 08/10] ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt
Updated DTS to replace deprecated binding with newer values
Refer: Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Felipe Balbi ba...@ti.com
---
arch/arm/boot/dts/am335x-evm.dts | 3 +--
arch/arm/boot/dts/omap3430-sdp.dts | 2 +-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index e8ec875..1aee6ac 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -269,7 +269,6 @@
reg = 0 0 0; /* CS0, offset 0 */
nand-bus-width = 8;
ti,nand-ecc-opt = bch8;
- gpmc,device-nand = true;
gpmc,device-width = 1;
gpmc,sync-clk-ps = 0;
gpmc,cs-on-ns = 0;
@@ -296,7 +295,7 @@
#address-cells = 1;
#size-cells = 1;
- elm_id = elm;
+ ti,elm-id = elm;
/* MTD partition table */
partition@0 {
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts
b/arch/arm/boot/dts/omap3430-sdp.dts
index e2249bc..501f863 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -105,7 +105,7 @@
reg = 1 0 0x0800;
nand-bus-width = 8;
- ti,nand-ecc-opt = sw;
+ ti,nand-ecc-opt = ham1;
gpmc,cs-on-ns = 0;
gpmc,cs-rd-off-ns = 36;
gpmc,cs-wr-off-ns = 36;
--
1.8.1
--
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[PATCH v10 00/10] mtd:nand:omap2: clean-up of supported ECC schemes
) | | | | | | | |OMAP_ECC_BCH4_CODE_HW |H/W (GPMC) |H/W (ELM) | | (needs CONFIG_MTD_NAND_OMAP_BCH | | | |ti,elm-id) | | | +---+---+---+ |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.c)| | (needs CONFIG_MTD_NAND_ECC_BCH) | | | | | | | |OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) | | (needs CONFIG_MTD_NAND_OMAP_BCH | | | |ti,elm-id) | | | +---+---+---+ Pekon Gupta (10): ARM: OMAP2+: cleaned-up DT support of various ECC schemes mtd: nand: omap: combine different flavours of 1-bit hamming ecc schemes mtd: nand: omap: cleanup: replace local references with generic framework names mtd: nand: omap: fix device scan: NAND_CMD_READID, NAND_CMD_RESET, CMD_CMD_PARAM use only x8 bus mtd:nand:omap2: clean-up BCHx_HW and BCHx_SW ECC configurations in device_probe mtd: nand: omap: clean-up ecc layout for BCH ecc schemes mtd: nand: omap: use drivers/mtd/nand/nand_bch.c wrapper for BCH ECC instead of lib/bch.c ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt mtd: nand: omap: updated devm_xx for all resource allocation and free calls mtd: nand: omap: remove selection of BCH ecc-scheme via KConfig .../devicetree/bindings/mtd/gpmc-nand.txt | 16 +- arch/arm/boot/dts/am335x-evm.dts | 3 +- arch/arm/boot/dts/omap3430-sdp.dts | 2 +- arch/arm/mach-omap2/board-flash.c | 2 +- arch/arm/mach-omap2/gpmc.c | 48 +- drivers/mtd/nand/Kconfig | 40 +- drivers/mtd/nand/omap2.c | 665 ++--- include/linux/platform_data/mtd-nand-omap2.h | 18 +- 8 files changed, 372 insertions(+), 422 deletions(-) -- 1.8.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v10 02/10] mtd: nand: omap: combine different flavours of 1-bit hamming ecc schemes
OMAP NAND driver currently supports multiple flavours of 1-bit Hamming
ecc-scheme, like:
- OMAP_ECC_HAMMING_CODE_DEFAULT
1-bit hamming ecc code using software library
- OMAP_ECC_HAMMING_CODE_HW
1-bit hamming ecc-code using GPMC h/w engine
- OMAP_ECC_HAMMING_CODE_HW_ROMCODE
1-bit hamming ecc-code using GPMC h/w engin with ecc-layout compatible
to ROM code.
This patch combines above multiple ecc-schemes into single implementation:
- OMAP_ECC_HAM1_CODE_HW
1-bit hamming ecc-code using GPMC h/w engine with ROM-code compatible
ecc-layout.
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Felipe Balbi ba...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 8
arch/arm/mach-omap2/board-flash.c | 2 +-
drivers/mtd/nand/omap2.c| 9 +++--
include/linux/platform_data/mtd-nand-omap2.h| 7 +--
4 files changed, 9 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index bfe07e1..5e1f31b 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -22,10 +22,10 @@ Optional properties:
width of 8 is assumed.
- ti,nand-ecc-opt:A string setting the ECC layout to use. One of:
-
- swSoftware method (default)
- hwHardware method
- hw-romcodegpmc hamming mode method romcode layout
+ swdeprecated use ham1 instead
+ hwdeprecated use ham1 instead
+ hw-romcodedeprecated use ham1 instead
+ ham1 1-bit Hamming ecc code
bch4 4-bit BCH ecc code
bch8 8-bit BCH ecc code
diff --git a/arch/arm/mach-omap2/board-flash.c
b/arch/arm/mach-omap2/board-flash.c
index fc20a61..ac82512 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8
nr_parts, u8 cs,
board_nand_data.nr_parts= nr_parts;
board_nand_data.devsize = nand_type;
- board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
+ board_nand_data.ecc_opt = OMAP_ECC_BCH8_CODE_HW;
gpmc_nand_init(board_nand_data, gpmc_t);
}
#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 4ecf0e5..8d521aa 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1993,10 +1993,7 @@ static int omap_nand_probe(struct platform_device *pdev)
}
/* select the ecc type */
- if (pdata-ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
- info-nand.ecc.mode = NAND_ECC_SOFT;
- else if ((pdata-ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
- (pdata-ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
+ if (pdata-ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
info-nand.ecc.bytes= 3;
info-nand.ecc.size = 512;
info-nand.ecc.strength = 1;
@@ -2025,7 +2022,7 @@ static int omap_nand_probe(struct platform_device *pdev)
}
/* rom code layout */
- if (pdata-ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
+ if (pdata-ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
if (info-nand.options NAND_BUSWIDTH_16)
offset = 2;
@@ -2033,7 +2030,7 @@ static int omap_nand_probe(struct platform_device *pdev)
offset = 1;
info-nand.badblock_pattern = bb_descrip_flashbased;
}
- omap_oobinfo.eccbytes = 3 * (info-mtd.oobsize/16);
+ omap_oobinfo.eccbytes = 3 * (info-mtd.writesize / 512);
for (i = 0; i omap_oobinfo.eccbytes; i++)
omap_oobinfo.eccpos[i] = i+offset;
diff --git a/include/linux/platform_data/mtd-nand-omap2.h
b/include/linux/platform_data/mtd-nand-omap2.h
index e4128f1..4da5bfa 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -23,13 +23,8 @@ enum nand_io {
};
enum omap_ecc {
- /* 1-bit ecc: stored at end of spare area */
- OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
- OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
- /* 1-bit ecc: stored at beginning of spare area as romcode */
- OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method romcode layout */
/* 1-bit ECC calculation by GPMC, Error detection by Software */
- OMAP_ECC_HAM1_CODE_HW,
+ OMAP_ECC_HAM1_CODE_HW = 0,
/* 4-bit ECC calculation by GPMC, Error detection
[PATCH v10 05/10] mtd:nand:omap2: clean-up BCHx_HW and BCHx_SW ECC configurations in device_probe
current implementation in omap3_init_bch() has some redundant code like:
(1) omap3_init_bch() re-probes the DT-binding to detect presence of ELM h/w
engine on SoC. And based on that it selects implemetation of ecc-scheme.
However, this is already done as part of GPMC DT parsing.
(2) As omap3_init_bch() serves as common function for configuring all types of
BCHx ecc-schemes, so there are multiple levels of redudant if..then..else
checks while populating nand_chip-ecc.
This patch make following changes to OMAP NAND driver:
(1) removes omap3_init_bch(): each ecc-scheme is individually configured in
omap_nand_probe() there by removing redundant if..then..else checks.
(2) adds is_elm_present(): re-probing of ELM device via DT is not required as
it's done in GPMC driver probe. Thus is_elm_present() just initializes ELM
driver with NAND probe data, when ecc-scheme with h/w based error-detection
is used.
(3) separates out configuration of different flavours of BCH4 and BCH8
ecc-schemes as given in below table
(4) conditionally compiles callbacks implementations of ecc.hwctl(),
ecc.calculate(), ecc.correct() to avoid warning of un-used functions.
+---+---+---+
| ECC scheme|ECC calculation|Error detection|
+---+---+---+
|OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W|
+---+---+---+
|OMAP_ECC_BCH4_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.c)|
| (needs CONFIG_MTD_NAND_ECC_BCH) | | |
| | | |
|OMAP_ECC_BCH4_CODE_HW |H/W (GPMC) |H/W (ELM) |
| (needs CONFIG_MTD_NAND_OMAP_BCH | | |
|ti,elm-id) | | |
+---+---+---+
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.c)|
| (needs CONFIG_MTD_NAND_ECC_BCH) | | |
| | | |
|OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) |
| (needs CONFIG_MTD_NAND_OMAP_BCH | | |
|ti,elm-id) | | |
+---+---+---+
- 'CONFIG_MTD_NAND_ECC_BCH' is generic KConfig required to build lib/bch.c
which is required for ECC error detection done in software.
(mainly used for legacy platforms which do not have on-chip ELM engine)
- 'CONFIG_MTD_NAND_OMAP_BCH' is OMAP specific Kconfig to detemine presence
on ELM h/w engine on SoC.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 281 ++-
1 file changed, 158 insertions(+), 123 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index d29edda..978240b 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -25,10 +25,8 @@
#include linux/of.h
#include linux/of_device.h
-#ifdef CONFIG_MTD_NAND_OMAP_BCH
#include linux/bch.h
#include linux/platform_data/elm.h
-#endif
#include linux/platform_data/mtd-nand-omap2.h
@@ -141,6 +139,8 @@
#define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
#define BCH_ECC_SIZE1 0x20/* ecc_size1 = 32 */
+#define OMAP_ECC_BCH8_POLYNOMIAL 0x201b
+
#ifdef CONFIG_MTD_NAND_OMAP_BCH
static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
0xac, 0x6b, 0xff, 0x99, 0x7b};
@@ -182,14 +182,12 @@ struct omap_nand_info {
u_char *buf;
int buf_len;
struct gpmc_nand_regs reg;
-
-#ifdef CONFIG_MTD_NAND_OMAP_BCH
+ /* fields specific for BCHx_HW ECC scheme */
struct bch_control *bch;
struct nand_ecclayout ecclayout;
boolis_elm_used;
struct device *elm_dev;
struct device_node *of_node;
-#endif
};
/**
@@ -1058,8 +1056,7 @@ static int omap_dev_ready(struct mtd_info *mtd)
}
}
-#ifdef CONFIG_MTD_NAND_OMAP_BCH
-
+#if defined(CONFIG_MTD_NAND_ECC_BCH) || defined(CONFIG_MTD_NAND_OMAP_BCH)
/**
* omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
* @mtd: MTD device structure
@@ -1140,7 +1137,9 @@ static void omap3_enable_hwecc_bch(struct mtd_info *mtd,
int mode)
/* Clear ecc and enable bits */
writel(ECCCLEAR | ECC1, info-reg.gpmc_ecc_control);
}
+#endif
+#ifdef CONFIG_MTD_NAND_ECC_BCH
/**
* omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC
[PATCH v10 10/10] mtd: nand: omap: remove selection of BCH ecc-scheme via KConfig
With OMAP NAND driver updates, selection of ecc-scheme: *DT enabled kernel* depends on ti,nand-ecc-opt and ti,elm-id DT bindings. *Non DT enabled kernel* depends on elm_dev and ecc-scheme passed along with platform-data from board file. So, selection of ecc-scheme (BCH8 or BCH4) from KConfig can be removed Signed-off-by: Pekon Gupta pe...@ti.com --- drivers/mtd/nand/Kconfig | 40 ++-- 1 file changed, 6 insertions(+), 34 deletions(-) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index d885298..93ae6a6 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -96,43 +96,15 @@ config MTD_NAND_OMAP2 config MTD_NAND_OMAP_BCH depends on MTD_NAND MTD_NAND_OMAP2 ARCH_OMAP3 - tristate Enable support for hardware BCH error correction + tristate Support hardware based BCH error correction default n select BCH - select BCH_CONST_PARAMS help -Support for hardware BCH error correction. - -choice - prompt BCH error correction capability - depends on MTD_NAND_OMAP_BCH - -config MTD_NAND_OMAP_BCH8 - bool 8 bits / 512 bytes (recommended) - help -Support correcting up to 8 bitflips per 512-byte block. -This will use 13 bytes of spare area per 512 bytes of page data. -This is the recommended mode, as 4-bit mode does not work -on some OMAP3 revisions, due to a hardware bug. - -config MTD_NAND_OMAP_BCH4 - bool 4 bits / 512 bytes - help -Support correcting up to 4 bitflips per 512-byte block. -This will use 7 bytes of spare area per 512 bytes of page data. -Note that this mode does not work on some OMAP3 revisions, due to a -hardware bug. Please check your OMAP datasheet before selecting this -mode. - -endchoice - -if MTD_NAND_OMAP_BCH -config BCH_CONST_M - default 13 -config BCH_CONST_T - default 4 if MTD_NAND_OMAP_BCH4 - default 8 if MTD_NAND_OMAP_BCH8 -endif + This config enables the ELM hardware engine, which can be used to + locate and correct errors when using BCH ECC scheme. This offloads + the cpu from doing ECC error searching and correction. However some + legacy OMAP families like OMAP2xxx, OMAP3xxx do not have ELM engine + so they should not enable this config symbol. config MTD_NAND_IDS tristate -- 1.8.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v10 04/10] mtd: nand: omap: fix device scan: NAND_CMD_READID, NAND_CMD_RESET, CMD_CMD_PARAM use only x8 bus
As per comments below, NAND_CMD_RESET, NAND_CMD_READID, and NAND_CMD_PARAM would
work only in x8 mode.
commit 64b37b2a63eb2f80b65c7185f0013f8ffc637ae3
Author: Matthieu CASTET matthieu.cas...@parrot.com
AuthorDate: 2012-11-06
Note that nand_scan_ident send command (NAND_CMD_RESET, NAND_CMD_READID,
NAND_CMD_PARAM), address and read data
The ONFI specificication is not very clear for x16 device if high byte of
address should be driven to 0,
but according to [1] it should be ok to not drive it during autodetection.
[1]
3.3.2. Target Initialization
[...]
The Read ID and Read Parameter Page commands only use the lower 8-bits of
the data bus.
The host shall not issue commands that use a word data width on x16 devices
until the host
determines the device supports a 16-bit data bus width in the parameter
page.
Thus this patch run nand_scan_ident() with driver configured as x8 device.
Once the NAND device is detected, and its ONFI params are read, the driver
is re-configured based on device-width as passed by DT bindinig 'nand-bus-width'
In-case there is a mis-match between the DT binding 'nand-bus-width' and actual
device-width detected during nand_get_flash_type() then probe returns failure.
All other low-level callback updates happen after the device detection.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 45 +
1 file changed, 33 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 5596368..d29edda 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1856,7 +1856,6 @@ static int omap_nand_probe(struct platform_device *pdev)
mtd-name = dev_name(pdev-dev);
mtd-owner = THIS_MODULE;
nand_chip = info-nand;
- nand_chip-options = pdata-devsize;
nand_chip-options |= NAND_SKIP_BBTSCAN;
#ifdef CONFIG_MTD_NAND_OMAP_BCH
info-of_node = pdata-of_node;
@@ -1904,6 +1903,39 @@ static int omap_nand_probe(struct platform_device *pdev)
nand_chip-chip_delay = 50;
}
+ /* scan NAND device connected to chip controller */
+ /* configure driver in x8 mode to read ONFI parameter page, as
+* NAND_CMD_READID NAND_CMD_PARAM may not work in x16 mode */
+ nand_chip-options = ~NAND_BUSWIDTH_16;
+ if (nand_scan_ident(mtd, 1, NULL)) {
+ /* nand_scan_ident failed */
+ if (pdata-devsize) {
+ /* may be because of mis-match of device-width,
+* platform data (DT binding) also says its x16 device
+* So re-scan with proper device-width */
+ nand_chip-options |= pdata-devsize;
+ if (nand_scan_ident(mtd, 1, NULL)) {
+ err = -ENXIO;
+ goto out_release_mem_region;
+ }
+ } else {
+ /* some genuine failure, because even platform-data
+* (DT binding) says that bus-width is x8 */
+ err = -ENXIO;
+ goto out_release_mem_region;
+ }
+ } else {
+ /* nand_scan_ident passed with x8 mode */
+ if (pdata-devsize) {
+ /* but platform-data (DT binding) say its x16 device */
+ pr_err(%s: incorrect bus-width config\n, DRIVER_NAME);
+ err = -EINVAL;
+ err = -ENXIO;
+ goto out_release_mem_region;
+ }
+ }
+
+ /* re-populate low-level callbacks based on xfer modes */
switch (pdata-xfer_type) {
case NAND_OMAP_PREFETCH_POLLED:
nand_chip-read_buf = omap_read_buf_pref;
@@ -2011,17 +2043,6 @@ static int omap_nand_probe(struct platform_device *pdev)
}
}
- /* DIP switches on some boards change between 8 and 16 bit
-* bus widths for flash. Try the other width if the first try fails.
-*/
- if (nand_scan_ident(mtd, 1, NULL)) {
- nand_chip-options ^= NAND_BUSWIDTH_16;
- if (nand_scan_ident(mtd, 1, NULL)) {
- err = -ENXIO;
- goto out_release_mem_region;
- }
- }
-
/* rom code layout */
if (pdata-ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
--
1.8.1
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[PATCH v10 01/10] ARM: OMAP2+: cleaned-up DT support of various ECC schemes
OMAP NAND driver support multiple ECC scheme, which can used in different
flavours, depending on in-build Hardware engines present on SoC.
This patch updates following in DT bindings related to sectionion of ecc-schemes
- ti,elm-id: replaces elm_id (maintains backward compatibility)
- ti,nand-ecc-opts: selection of h/w or s/w implementation of an ecc-scheme
depends on ti,elm-id. (supported values ham1, bch4, and bch8)
- maintain backward compatibility to deprecated DT bindings (sw, hw, hw-romcode)
Below table shows different flavours of ecc-schemes supported by OMAP devices
+---+---+---+
| ECC scheme|ECC calculation|Error detection|
+---+---+---+
|OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W|
+---+---+---+
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W|
|(requires CONFIG_MTD_NAND_ECC_BCH) | | |
+---+---+---+
|OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) |
|(requires CONFIG_MTD_NAND_OMAP_BCH | | |
| ti,elm-id in DT) | | |
+---+---+---+
To optimize footprint of omap2-nand driver, selection of some ECC schemes
also require enabling following Kconfigs, in addition to setting appropriate
DT bindings
- Kconfig:CONFIG_MTD_NAND_ECC_BCHerror detection done in software
- Kconfig:CONFIG_MTD_NAND_OMAP_BCH error detection done by h/w engine
Signed-off-by: Pekon Gupta pe...@ti.com
Reviewed-by: Felipe Balbi ba...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
.../devicetree/bindings/mtd/gpmc-nand.txt | 8 +++-
arch/arm/mach-omap2/gpmc.c | 48 +++---
include/linux/platform_data/mtd-nand-omap2.h | 13 +-
3 files changed, 51 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index df338cb..bfe07e1 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -36,8 +36,12 @@ Optional properties:
prefetch-dma Prefetch enabled sDMA mode
prefetch-irq Prefetch enabled irq mode
- - elm_id: Specifies elm device node. This is required to support BCH
- error correction using ELM module.
+ - elm_id: deprecated use ti,elm-id instead
+ - ti,elm-id: Specifies phandle of the ELM devicetree node.
+ ELM is an on-chip hardware engine on TI SoC which is used for
+ locating ECC errors for BCHx algorithms. SoC devices which have
+ ELM hardware engines should specify this device node in .dtsi
+ Using ELM for ECC error correction frees some CPU cycles.
For inline partiton table parsing (optional):
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 579697a..c877129 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1341,14 +1341,6 @@ static void __maybe_unused gpmc_read_timings_dt(struct
device_node *np,
#ifdef CONFIG_MTD_NAND
-static const char * const nand_ecc_opts[] = {
- [OMAP_ECC_HAMMING_CODE_DEFAULT] = sw,
- [OMAP_ECC_HAMMING_CODE_HW] = hw,
- [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = hw-romcode,
- [OMAP_ECC_BCH4_CODE_HW] = bch4,
- [OMAP_ECC_BCH8_CODE_HW] = bch8,
-};
-
static const char * const nand_xfer_types[] = {
[NAND_OMAP_PREFETCH_POLLED] = prefetch-polled,
[NAND_OMAP_POLLED] = polled,
@@ -1378,13 +1370,41 @@ static int gpmc_probe_nand_child(struct platform_device
*pdev,
gpmc_nand_data-cs = val;
gpmc_nand_data-of_node = child;
- if (!of_property_read_string(child, ti,nand-ecc-opt, s))
- for (val = 0; val ARRAY_SIZE(nand_ecc_opts); val++)
- if (!strcasecmp(s, nand_ecc_opts[val])) {
- gpmc_nand_data-ecc_opt = val;
- break;
- }
+ /* Detect availability of ELM module */
+ gpmc_nand_data-elm_of_node = of_parse_phandle(child, ti,elm-id, 0);
+ if (gpmc_nand_data-elm_of_node == NULL)
+ gpmc_nand_data-elm_of_node =
+ of_parse_phandle(child, elm_id, 0);
+ if (gpmc_nand_data-elm_of_node == NULL)
+ pr_warn(%s: ti,elm-id property not found\n, __func__);
+
+ /* select ecc-scheme for NAND */
+ if (of_property_read_string(child, ti
