Re: [PATCH/RFT 0/3] ARM: OMAP: PM: reduce overhead of pwrdm pre/post transitions

2012-04-25 Thread Shilimkar, Santosh
On Tue, Apr 24, 2012 at 7:53 PM, Kevin Hilman khil...@ti.com wrote:
 Here's a first pass attempt to reduce the overhead of the pre/post
 transitions by allowing them to be called per powerdomain and making
 them conditional on powerdomain transtions.

 This can be used for testing/measurements to see the reduction the
 latencies involved in entering/exiting idle with and without these
 patches.

 Kevin Hilman (3):
  ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdm
  ARM: OMAP3: PM: call pre/post transition per powerdomain
  ARM: OMAP3: PM: cleanup cam_pwrdm leftovers

I have reviewed and tested this series on OMAP4 with coupleidle and system
wide supsned. It continues to work as expected. I have done an additional
patch(end of email)  as mentioned to take advantage of per powerdomain
pre/post transition API update.

Thanks for the series. it certainly removes the big over-head we had before
with the pre-post APIs.

FWIW,
Reviewed-tested-by: Santosh Shilimkar santosh.shilim...@ti.com

Regards
Santosh

From e535b0d8948ed44732c6128ff4236cfe32d2f40a Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar santosh.shilim...@ti.com
Date: Wed, 25 Apr 2012 17:04:08 +0530
Subject: [PATCH] ARM: OMAP4: PM: call pre/post transition per powerdomain

Iteration over all power domains in the idle path is unnecessary since
only power domains that are transitioning need to be accounted for.

Update OMAP4 low power code accordingly.

Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
There is one issue though about MPUSS powerdomain accounting. It will
get called on both CPUs and might result in duplicate pm debug counter
update. There is no functional issue with that as such but needs to
be cleaned up.

Will address that issue in a seperate series.

 arch/arm/mach-omap2/omap-mpuss-lowpower.c |   22 --
 1 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index e35a86b..3a709b2 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -117,6 +117,20 @@ static inline void clear_cpu_prev_pwrst(unsigned
int cpu_id)
 }

 /*
+ * CPU powerdomain pre/post transition.
+ */
+static inline void cpu_pwrdm_pre_post_transition(unsigned int cpu_id,
+   bool pre_transition)
+{
+   struct omap4_cpu_pm_info *pm_info = per_cpu(omap4_pm_info, cpu_id);
+
+   if (pre_transition)
+   pwrdm_pre_transition(pm_info-pwrdm);
+   else
+   pwrdm_post_transition(pm_info-pwrdm);
+}
+
+/*
  * Store the SCU power status value to scratchpad memory
  */
 static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
@@ -255,7 +269,7 @@ int omap4_enter_lowpower(unsigned int cpu,
unsigned int power_state)
return -ENXIO;
}

-   pwrdm_pre_transition(NULL);
+   pwrdm_pre_transition(mpuss_pd);

/*
 * Check MPUSS next state and save interrupt controller if needed.
@@ -266,6 +280,7 @@ int omap4_enter_lowpower(unsigned int cpu,
unsigned int power_state)
(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
save_state = 2;

+   cpu_pwrdm_pre_post_transition(cpu, 1);
cpu_clear_prev_logic_pwrst(cpu);
set_cpu_next_pwrst(cpu, power_state);
set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
@@ -285,9 +300,10 @@ int omap4_enter_lowpower(unsigned int cpu,
unsigned int power_state)
 * domain transition
 */
wakeup_cpu = smp_processor_id();
+   cpu_pwrdm_pre_post_transition(wakeup_cpu, 0);
set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);

-   pwrdm_post_transition(NULL);
+   pwrdm_post_transition(mpuss_pd);

return 0;
 }
@@ -307,6 +323,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu,
unsigned int power_state)
if (power_state == PWRDM_POWER_OFF)
cpu_state = 1;

+   cpu_pwrdm_pre_post_transition(cpu, 1);
clear_cpu_prev_pwrst(cpu);
set_cpu_next_pwrst(cpu, power_state);
set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
@@ -319,6 +336,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu,
unsigned int power_state)
 */
omap4_finish_suspend(cpu_state);

+   cpu_pwrdm_pre_post_transition(wakeup_cpu, 0);
set_cpu_next_pwrst(cpu, PWRDM_POWER_ON);
return 0;
 }
-- 
1.7.5.4
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[PATCH/RFT 0/3] ARM: OMAP: PM: reduce overhead of pwrdm pre/post transitions

2012-04-24 Thread Kevin Hilman
Here's a first pass attempt to reduce the overhead of the pre/post
transitions by allowing them to be called per powerdomain and making
them conditional on powerdomain transtions.

This can be used for testing/measurements to see the reduction the
latencies involved in entering/exiting idle with and without these
patches.

Kevin Hilman (3):
  ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdm
  ARM: OMAP3: PM: call pre/post transition per powerdomain
  ARM: OMAP3: PM: cleanup cam_pwrdm leftovers

 arch/arm/mach-omap2/omap-mpuss-lowpower.c |4 ++--
 arch/arm/mach-omap2/pm34xx.c  |   14 --
 arch/arm/mach-omap2/powerdomain.c |   16 
 arch/arm/mach-omap2/powerdomain.h |4 ++--
 4 files changed, 24 insertions(+), 14 deletions(-)

-- 
1.7.9.2

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Re: [PATCH/RFT 0/3] ARM: OMAP: PM: reduce overhead of pwrdm pre/post transitions

2012-04-24 Thread Grazvydas Ignotas
On Tue, Apr 24, 2012 at 5:23 PM, Kevin Hilman khil...@ti.com wrote:
 Here's a first pass attempt to reduce the overhead of the pre/post
 transitions by allowing them to be called per powerdomain and making
 them conditional on powerdomain transtions.

 This can be used for testing/measurements to see the reduction the
 latencies involved in entering/exiting idle with and without these
 patches.

Seems to have similar effect as my earlier test of simply commenting
out pre/post transitions (~4.4MB/s), so this definitely helps.

Tested-by: Grazvydas Ignotas nota...@gmail.com

-- 
Gražvydas
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