Re: [PATCH v5 4/9] mmc: dw_mmc: lookup for optional biu and ciu clocks
On 09/05/2012 04:46 AM, Thomas Abraham wrote:
Some platforms allow for clock gating and control of bus interface unit clock
and card interface unit clock. Add support for clock lookup of optional biu
and ciu clocks for clock gating and clock speed determination.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Acked-by: Will Newton will.new...@imgtec.com
---
drivers/mmc/host/dw_mmc.c | 50 +--
include/linux/mmc/dw_mmc.h |4 +++
2 files changed, 51 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 227c42e..e8c8491 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1960,13 +1960,40 @@ int dw_mci_probe(struct dw_mci *host)
return -ENODEV;
}
- if (!host-pdata-bus_hz) {
+ host-biu_clk = clk_get(host-dev, biu);
+ if (IS_ERR(host-biu_clk)) {
+ dev_dbg(host-dev, biu clock not available\n);
+ } else {
+ ret = clk_prepare_enable(host-biu_clk);
+ if (ret) {
+ dev_err(host-dev, failed to enable biu clock\n);
+ return ret;
didn't clk_put() for biu_clk?
+ }
+ }
+
+ host-ciu_clk = clk_get(host-dev, ciu);
+ if (IS_ERR(host-ciu_clk)) {
+ dev_dbg(host-dev, ciu clock not available\n);
+ } else {
+ ret = clk_prepare_enable(host-ciu_clk);
+ if (ret) {
+ dev_err(host-dev, failed to enable ciu clock\n);
+ goto err_clk_biu;
+ }
+ }
+
+ if (IS_ERR(host-ciu_clk))
+ host-bus_hz = host-pdata-bus_hz;
+ else
+ host-bus_hz = clk_get_rate(host-ciu_clk);
+
+ if (!host-bus_hz) {
dev_err(host-dev,
Platform data must supply bus speed\n);
- return -ENODEV;
+ ret = -ENODEV;
+ goto err_clk_ciu;
}
- host-bus_hz = host-pdata-bus_hz;
host-quirks = host-pdata-quirks;
spin_lock_init(host-lock);
@@ -2116,6 +2143,17 @@ err_dmaunmap:
regulator_disable(host-vmmc);
regulator_put(host-vmmc);
}
+
+err_clk_ciu:
+ if (!IS_ERR(host-ciu_clk)) {
+ clk_disable_unprepare(host-ciu_clk);
+ clk_put(host-ciu_clk);
+ }
+err_clk_biu:
I think right that is located the clk_put(host-ciu_clk) at here
+ if (!IS_ERR(host-biu_clk)) {
+ clk_disable_unprepare(host-biu_clk);
+ clk_put(host-biu_clk);
+ }
return ret;
}
EXPORT_SYMBOL(dw_mci_probe);
@@ -2149,6 +2187,12 @@ void dw_mci_remove(struct dw_mci *host)
regulator_put(host-vmmc);
}
+ if (!IS_ERR(host-ciu_clk))
+ clk_disable_unprepare(host-ciu_clk);
+ if (!IS_ERR(host-biu_clk))
+ clk_disable_unprepare(host-biu_clk);
+ clk_put(host-ciu_clk);
+ clk_put(host-biu_clk);
}
EXPORT_SYMBOL(dw_mci_remove);
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index a37a573..787ad56 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -78,6 +78,8 @@ struct mmc_data;
* @data_offset: Set the offset of DATA register according to VERID.
* @dev: Device associated with the MMC controller.
* @pdata: Platform data associated with the MMC controller.
+ * @biu_clk: Pointer to bus interface unit clock instance.
+ * @ciu_clk: Pointer to card interface unit clock instance.
* @slot: Slots sharing this MMC controller.
* @fifo_depth: depth of FIFO.
* @data_shift: log2 of FIFO item size.
@@ -158,6 +160,8 @@ struct dw_mci {
u16 data_offset;
struct device *dev;
struct dw_mci_board *pdata;
+ struct clk *biu_clk;
+ struct clk *ciu_clk;
struct dw_mci_slot *slot[MAX_MCI_SLOTS];
/* FIFO push and pull */
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Re: [PATCH v2 1/5] mmc: host: sdhci-s3c: Add broken-voltage DT property for broken voltage quirk
Acked-by: Jaehoon Chung jh80.ch...@samsung.com
On 09/04/2012 05:50 PM, Tomasz Figa wrote:
Some boards use fixed voltage regulator for vmmc supply (e.g. for eMMC
memories). MMC_CAP2_BROKEN_VOLTAGE must be enabled for them to operate
correctly.
Cc: Ben Dooks ben-li...@fluff.org
Cc: Chris Ball c...@laptop.org
CC: linux-...@vger.kernel.org
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Documentation/devicetree/bindings/mmc/mmc.txt | 1 +
drivers/mmc/host/sdhci-s3c.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt
b/Documentation/devicetree/bindings/mmc/mmc.txt
index 8a6811f..ecbde68 100644
--- a/Documentation/devicetree/bindings/mmc/mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc.txt
@@ -16,6 +16,7 @@ Optional properties:
- wp-inverted: when present, polarity on the wp gpio line is inverted
- non-removable: non-removable slot (like eMMC)
- max-frequency: maximum operating clock frequency
+- broken-voltage: vmmc regulator does not allow voltage control
Example:
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 445910e..39715b8 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -443,6 +443,9 @@ static int __devinit sdhci_s3c_parse_dt(struct device
*dev,
if (!ourhost-gpios)
return -ENOMEM;
+ if (of_get_property(node, broken-voltage, 0))
+ pdata-host_caps2 |= MMC_CAP2_BROKEN_VOLTAGE;
+
/* get the card detection method */
if (of_get_property(node, broken-cd, 0)) {
pdata-cd_type = S3C_SDHCI_CD_NONE;
--
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Re: [PATCH 1/2] ARM: exynos: delete redundant HAVE_SCHED_CLOCK option in Kconfig
2012/9/5 Kukjin Kim kgene@samsung.com: Barry Song wrote: From: Barry Song baohua.s...@csr.com Signed-off-by: Barry Song baohua.s...@csr.com Acked-by: Kukjin Kim kgene@samsung.com Kukjin, Thanks. i assume this will be taken by samsung tree. Who will take care the other one: http://www.spinics.net/lists/arm-kernel/msg191939.html Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. --- arch/arm/mach-exynos/Kconfig |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index b5b4c8c..3fd4ab3 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -243,7 +243,6 @@ config MACH_UNIVERSAL_C210 select CPU_EXYNOS4210 select S5P_HRT select CLKSRC_MMIO - select HAVE_SCHED_CLOCK select S5P_GPIO_INT select S5P_DEV_FIMC0 select S5P_DEV_FIMC1 -- 1.7.0.4 -barry -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: Add MFC device tree support
Hi Karol,
Thank you very much for the detailed explanation.
Its indeed very well explained and seems like a great approach
to remove the hard codings.
I will go ahead with this implementation and post the updated patch.
Regards
Arun
On Wed, Sep 5, 2012 at 8:12 AM, Karol Lewandowski k.lewando...@samsung.com
wrote:
On 08/28/2012 07:08 PM, Arun Kumar K wrote:
Hi Karol,
Thanks for your comments.
Please find my response inline.
Hi... and sorry for so much delayed response.
+
+static void __init exynos5_reserve(void)
+{
+ s5p_mfc_reserve_mem(0x4300, 8 20, 0x5100, 8 20);
I think it would make sense to make this memory reservation dependent
on mfc* node being present in DTS. It's to early to use of_* functions
(because tree is not populated at this stage) but fdt_* family of functions
work just fine.
As I can see the fdt_* functions are not used in any of the ARM based SoC
init codes. Though I can see some references in powerpc.
The implementation and includes are present in arch/arm/boot/compressed/
which I think cannot be used directly in mach-exynos unless we make some
comon makefile changes.
It looks like I was writing from memory, and I actually mixed things
up. To be clear this time - we can't use regular device tree handling
functions in reserve() as it's too early. Namely, flattened device tree
is not yet converted to kernel's-natural representation. However,
I think we can scan fdt just fine. To do so one just needs to use
functions declared here
#include linux/of_fdt.h
Actual architecture-independent code is in drivers/of/fdt.c. This
provides of_fdt_ family of functions. Please see below for example.
Please clarify whether its ok to use fdt_* functions to parse the dts in
exynos machine init or please point me to some sample implementations
which I can refer to.
It should be ok to use anything that works on flattened device tree
rather than its uncompressed version. I've experimented a bit and
something like this worked for me just fine (it was around 3.3-kernel
timeframe, but I don't think that fdt api has changed):
[mach-exynos4-dt.c]
#include linux/of_fdt.h
int fdt_find_compat(unsigned long node, const char *uname, int depth, void
*data)
{
if (of_flat_dt_is_compatible(node, (char *)data))
return 1;
return 0;
}
static void __init exynos4210_dt_reserve(void)
{
/* Reserve memory for MFC only if it's available */
if (of_scan_flat_dt(fdt_find_compat, samsung,s5pv210-mfc)) {
printk(KERN_NOTICE exynos4-dt: mfc device node found -
setting up memory area for dma\n);
s5p_mfc_reserve_mem(0x4300, 8 20, 0x5100, 8 20);
}
}
[.dts]
codec@some-addr {
compatible = samsung,s5pv210-mfc;
};
So, in above code fragment I just check if mfc was defined in dts.
This could probably stay as it is.
Then I allocate _predefined_ region - and this part should be fixed.
If you have nodes like mfc-r-size/offset, then you could just get
this information directly from (f)dt rather than hardcoding it in the code.
Precisely, after we find compatible node we could do something like
following (untested):
unsigned long lsize, loff, rsize, roff len;
__be32 *prop;
prop = of_get_flat_dt_prop(node, samsung,mfc-l-size, len);
if (!prop)
return;
lsize = of_read_ulong(prop, len/4);
...
Regards,
--
Karol Lewandowski | Samsung Poland RD Center | Linux/Platform
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[PATCH 1/2] ARM: S3C24XX: Use module_platform_driver macro in h1940-bluetooth.c
module_platform_driver simplifies the code by eliminating
module_init and module_exit calls.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/mach-s3c24xx/h1940-bluetooth.c | 14 +-
1 files changed, 1 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c
b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
index a5eeb62..57aee91 100644
--- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
@@ -138,19 +138,7 @@ static struct platform_driver h1940bt_driver = {
.remove = h1940bt_remove,
};
-
-static int __init h1940bt_init(void)
-{
- return platform_driver_register(h1940bt_driver);
-}
-
-static void __exit h1940bt_exit(void)
-{
- platform_driver_unregister(h1940bt_driver);
-}
-
-module_init(h1940bt_init);
-module_exit(h1940bt_exit);
+module_platform_driver(h1940bt_driver);
MODULE_AUTHOR(Arnaud Patard arnaud.pat...@rtp-net.org);
MODULE_DESCRIPTION(Driver for the iPAQ H1940 bluetooth chip);
--
1.7.4.1
--
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[PATCH 2/2] ARM: S3C24XX: Use module_platform_driver macro in mach-osiris-dvs.c
module_platform_driver simplifies the code by eliminating
module_init and module_exit calls.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/mach-s3c24xx/mach-osiris-dvs.c | 13 +
1 files changed, 1 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
index ad2792d..5876c6b 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
@@ -175,18 +175,7 @@ static struct platform_driver osiris_dvs_driver = {
},
};
-static int __init osiris_dvs_init(void)
-{
- return platform_driver_register(osiris_dvs_driver);
-}
-
-static void __exit osiris_dvs_exit(void)
-{
- platform_driver_unregister(osiris_dvs_driver);
-}
-
-module_init(osiris_dvs_init);
-module_exit(osiris_dvs_exit);
+module_platform_driver(osiris_dvs_driver);
MODULE_DESCRIPTION(Simtec OSIRIS DVS support);
MODULE_AUTHOR(Ben Dooks b...@simtec.co.uk);
--
1.7.4.1
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RE: [PATCH v5 9/9] mmc: dw_mmc: add support for exynos specific implementation of dw-mshc
On Wednesday, September 05, 2012, Thomas Abraham thomas.abra...@linaro.org
wrote:
Version 6 is right?
Samsung Exynos SoC's extend the dw-mshc controller for additional clock and
bus
control. Add support for these extensions and include provide device tree
based
discovery suppory as well.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Acked-by: Will Newton will.new...@imgtec.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt | 86 +++
drivers/mmc/host/Kconfig |9 +
drivers/mmc/host/Makefile |1 +
drivers/mmc/host/dw_mmc-exynos.c | 253
4 files changed, 349 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
create mode 100644 drivers/mmc/host/dw_mmc-exynos.c
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
new file mode 100644
index 000..323a891
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -0,0 +1,86 @@
+* Samsung Exynos specific extensions to the Synopsis Designware Mobile
+ Storage Host Controller
+
+The Synopsis designware mobile storage host controller is used to interface
+a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
+differences between the core Synopsis dw mshc controller properties described
+by synposis-dw-mshc.txt and the properties used by the Samsung Exynos
specific
+extensions to the Synopsis Designware Mobile Storage Host Controller.
+
+Required Properties:
+
+* compatible: should be
+ - samsung,exynos4210-dw-mshc: for controllers with Samsung Exynos4210
+ specific extentions.
+ - samsung,exynos4412-dw-mshc: for controllers with Samsung Exynos4412
+ specific extentions.
+ - samsung,exynos5250-dw-mshc: for controllers with Samsung Exynos5250
+ specific extentions.
+
+* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
+ unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
+ ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
+
+* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift
value
+ in transmit mode and CIU clock phase shift value in receive mode for single
+ data rate mode operation. Refer notes below for the order of the cells and
the
+ valid values.
+
+* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift
value
+ in transmit mode and CIU clock phase shift value in receive mode for double
+ data rate mode operation. Refer notes below for the order of the cells and
the
+ valid values.
+
+ Notes for the sdr-timing and ddr-timing values:
+
+The order of the cells should be
+ - First Cell: CIU clock phase shift value for tx mode.
+ - Second Cell: CIU clock phase shift value for rx mode.
+
+Valid values for SDR and DDR CIU clock timing for Exynos5250:
+ - valid value for tx phase shift and rx phase shift is 0 to 7.
+ - when CIU clock divider value is set to 3, all possible 8 phase shift
+values can be used.
+ - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
+phase shift clocks should be 0.
+
+Required properties for a slot:
+
+* gpios: specifies a list of gpios used for command, clock and data bus. The
+ first gpio is the command line and the second gpio is the clock line. The
+ rest of the gpios (depending on the bus-width property) are the data lines
in
+ no particular order. The format of the gpio specifier depends on the gpio
+ controller.
+
+Example:
+
+ The MSHC controller node can be split into two portions, SoC specific and
+ board specific portions as listed below.
+
+ dwmmc0@1220 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1220 0x1000;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ dwmmc0@1220 {
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-sdr-timing = 2 3 3;
+ samsung,dw-mshc-ddr-timing = 1 2 3;
Third filed is still useful?
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ gpios = gpc0 0 2 0 3, gpc0 1 2 0 3,
+ gpc1 0 2 3 3, gpc1 1 2 3 3,
+ gpc1 2 2 3 3, gpc1 3 2 3 3,
+ gpc0 3 2 3 3, gpc0 4 2 3 3,
+ gpc0 5 2 3 3, gpc0 6 2 3 3;
+ };
+ };
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index aa131b3..9bf10e7 100644
---
RE: [PATCH v4 3/3] ARM: dts: Add nodes for dw_mmc controllers for Samsung Exynos5250 platforms
On Wednesday, September 05, 2012, Thomas Abraham thomas.abra...@linaro.org
wrote:
Add device nodes for the four instances of dw_mmc controllers in Exynos5250
and enable instance 0 and 2 for the smdk5250 board.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 57
+
arch/arm/boot/dts/exynos5250.dtsi | 32
2 files changed, 89 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..ae1cffe 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -16,6 +16,13 @@
model = SAMSUNG SMDK5250 board based on EXYNOS5250;
compatible = samsung,smdk5250, samsung,exynos5250;
+ aliases {
+ mshc0 = dwmmc_0;
+ mshc1 = dwmmc_1;
+ mshc2 = dwmmc_2;
+ mshc3 = dwmmc_3;
+ };
+
memory {
reg = 0x4000 0x8000;
};
@@ -72,6 +79,56 @@
status = disabled;
};
+ dwmmc_0: dwmmc0@1220 {
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3 3;
+ samsung,dw-mshc-ddr-timing = 1 2 3;
As adding dw-mshc-ciu-div, third field of dw-mshc-ddr-timing can be removed.
Thanks,
Seungwon Jeon
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ gpios = gpc0 0 2 0 3, gpc0 1 2 0 3,
+ gpc1 0 2 3 3, gpc1 1 2 3 3,
+ gpc1 2 2 3 3, gpc1 3 2 3 3,
+ gpc0 3 2 3 3, gpc0 4 2 3 3,
+ gpc0 5 2 3 3, gpc0 6 2 3 3;
+ };
+ };
+
+ dwmmc_1: dwmmc1@1221 {
+ status = disabled;
+ };
+
+ dwmmc_2: dwmmc2@1222 {
+ num-slots = 1;
+ supports-highspeed;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3 3;
+ samsung,dw-mshc-ddr-timing = 1 2 3;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ samsung,cd-pinmux-gpio = gpc3 2 2 3 3;
+ gpios = gpc3 0 2 0 3, gpc3 1 2 0 3,
+ gpc3 3 2 3 3, gpc3 4 2 3 3,
+ gpc3 5 2 3 3, gpc3 6 2 3 3,
+ gpc4 3 3 3 3, gpc4 3 3 3 3,
+ gpc4 5 3 3 3, gpc4 6 3 3 3;
+ };
+ };
+
+ dwmmc_3: dwmmc3@1223 {
+ status = disabled;
+ };
+
spi_0: spi@12d2 {
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8..f69e389 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -182,6 +182,38 @@
#size-cells = 0;
};
+ dwmmc0@1220 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1220 0x1000;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ dwmmc1@1221 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1221 0x1000;
+ interrupts = 0 76 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ dwmmc2@1222 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1222 0x1000;
+ interrupts = 0 77 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ dwmmc3@1223 {
+ compatible = samsung,exynos5250-dw-mshc;
+ reg = 0x1223 0x1000;
+ interrupts = 0 78 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
amba {
#address-cells = 1;
#size-cells = 1;
--
1.6.6.rc2
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[PATCH V4 0/2] video: drm: Add Device tree support to DRM-FIMD
This patch set adds device tree support for DRM-FIMD for Samsung's Exynos5250. It includes parsing platform data from dts file. Also, adds the driver data for exynos4 and exynos5 devices. This patchset is based and tested on top of v3.6-rc4 Also depends on below patchset http://lists.freedesktop.org/archives/dri-devel/2012-August/026076.html Changes since V3: - Removed the fimd version from driver data and using timing base address instead - Removed the drm_ prefixes to the structures and fucntions Changes since V2: - Added driver data to exynos5-drm-fimd as per Marek Szyprowski suggestion Changes since V1: - Corrected typo errors and changed compatibility string Leela Krishna Amudala (2): drm/exynos: add platform_device_id table and driver data for drm fimd video: drm: exynos: Add device tree support Documentation/devicetree/bindings/fb/drm-fimd.txt | 80 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 140 +++- 2 files changed, 213 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/fb/drm-fimd.txt -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 1/2] drm/exynos: add platform_device_id table and driver data for drm fimd
The name of the exynos drm fimd device is renamed to exynos-drm-fimd
and two device ids are created for exynos4-fb and exynos5-fb.
Also, added driver data for exynos4 and exynos5 to pick the timing base address
at runtime to write data into appropriate register address.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 45 ++---
1 files changed, 40 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 24c0bd4..3701fbe 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -57,6 +57,18 @@
#define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
+struct fimd_driver_data {
+ unsigned int timing_base;
+};
+
+struct fimd_driver_data exynos4_fimd_driver_data = {
+ .timing_base = 0x0,
+};
+
+struct fimd_driver_data exynos5_fimd_driver_data = {
+ .timing_base = 0x2,
+};
+
struct fimd_win_data {
unsigned intoffset_x;
unsigned intoffset_y;
@@ -91,6 +103,13 @@ struct fimd_context {
struct exynos_drm_panel_info *panel;
};
+static inline struct fimd_driver_data *drm_fimd_get_driver_data(
+ struct platform_device *pdev)
+{
+ return (struct fimd_driver_data *)
+ platform_get_device_id(pdev)-driver_data;
+}
+
static bool fimd_display_is_connected(struct device *dev)
{
DRM_DEBUG_KMS(%s\n, __FILE__);
@@ -194,32 +213,35 @@ static void fimd_commit(struct device *dev)
struct fimd_context *ctx = get_fimd_context(dev);
struct exynos_drm_panel_info *panel = ctx-panel;
struct fb_videomode *timing = panel-timing;
+ struct fimd_driver_data *driver_data;
+ struct platform_device *pdev = to_platform_device(dev);
u32 val;
+ driver_data = drm_fimd_get_driver_data(pdev);
if (ctx-suspended)
return;
DRM_DEBUG_KMS(%s\n, __FILE__);
/* setup polarity values from machine code. */
- writel(ctx-vidcon1, ctx-regs + VIDCON1);
+ writel(ctx-vidcon1, ctx-regs + driver_data-timing_base + VIDCON1);
/* setup vertical timing values. */
val = VIDTCON0_VBPD(timing-upper_margin - 1) |
VIDTCON0_VFPD(timing-lower_margin - 1) |
VIDTCON0_VSPW(timing-vsync_len - 1);
- writel(val, ctx-regs + VIDTCON0);
+ writel(val, ctx-regs + driver_data-timing_base + VIDTCON0);
/* setup horizontal timing values. */
val = VIDTCON1_HBPD(timing-left_margin - 1) |
VIDTCON1_HFPD(timing-right_margin - 1) |
VIDTCON1_HSPW(timing-hsync_len - 1);
- writel(val, ctx-regs + VIDTCON1);
+ writel(val, ctx-regs + driver_data-timing_base + VIDTCON1);
/* setup horizontal and vertical display size. */
val = VIDTCON2_LINEVAL(timing-yres - 1) |
VIDTCON2_HOZVAL(timing-xres - 1);
- writel(val, ctx-regs + VIDTCON2);
+ writel(val, ctx-regs + driver_data-timing_base + VIDTCON2);
/* setup clock source, clock divider, enable dma. */
val = ctx-vidcon0;
@@ -982,6 +1004,18 @@ static int fimd_runtime_resume(struct device *dev)
}
#endif
+static struct platform_device_id fimd_driver_ids[] = {
+ {
+ .name = exynos4-fb,
+ .driver_data= (unsigned long)exynos4_fimd_driver_data,
+ }, {
+ .name = exynos5-fb,
+ .driver_data= (unsigned long)exynos5_fimd_driver_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(platform, fimd_driver_ids);
+
static const struct dev_pm_ops fimd_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
@@ -990,8 +1024,9 @@ static const struct dev_pm_ops fimd_pm_ops = {
struct platform_driver fimd_driver = {
.probe = fimd_probe,
.remove = __devexit_p(fimd_remove),
+ .id_table = fimd_driver_ids,
.driver = {
- .name = exynos4-fb,
+ .name = exynos-drm-fimd,
.owner = THIS_MODULE,
.pm = fimd_pm_ops,
},
--
1.7.0.4
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[PATCH V4 2/2] video: drm: exynos: Add device tree support
Add device tree based discovery support for DRM-FIMD driver.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
Documentation/devicetree/bindings/fb/drm-fimd.txt | 80 +
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 95 -
2 files changed, 173 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/fb/drm-fimd.txt
diff --git a/Documentation/devicetree/bindings/fb/drm-fimd.txt
b/Documentation/devicetree/bindings/fb/drm-fimd.txt
new file mode 100644
index 000..4ff1829
--- /dev/null
+++ b/Documentation/devicetree/bindings/fb/drm-fimd.txt
@@ -0,0 +1,80 @@
+* Samsung Display Controller using DRM frame work
+
+The display controller is used to transfer image data from memory to an
+external LCD driver interface. It supports various color formats such as
+rgb and yuv.
+
+Required properties:
+ - compatible: Should be samsung,exynos5-fimd or samsung,exynos4-fb for
+ fimd using DRM frame work.
+ - reg: physical base address of the controller and length of memory
+ mapped region.
+ - interrupts: Three interrupts should be specified. The interrupts should be
+ specified in the following order.
+ - VSYNC interrupt
+ - FIFO level interrupt
+ - FIMD System Interrupt
+
+ - samsung,fimd-display: This property should specify the phandle of the
+ display device node which holds the video interface timing with the
+ below mentioned properties.
+
+ - lcd-htiming: Specifies the horizontal timing for the overlay. The
+ horizontal timing includes four parameters in the following order.
+
+ - horizontal back porch (in number of lcd clocks)
+ - horizontal front porch (in number of lcd clocks)
+ - hsync pulse width (in number of lcd clocks)
+ - Display panels X resolution.
+
+ - lcd-vtiming: Specifies the vertical timing for the overlay. The
+ vertical timing includes four parameters in the following order.
+
+ - vertical back porch (in number of lcd lines)
+ - vertical front porch (in number of lcd lines)
+ - vsync pulse width (in number of lcd clocks)
+ - Display panels Y resolution.
+
+
+ - samsung,default-window: Specifies the default window number of the fimd
controller.
+
+ - samsung,fimd-win-bpp: Specifies the bits per pixel.
+
+Optional properties:
+ - samsung,fimd-vidout-rgb: Video output format is RGB.
+ - samsung,fimd-inv-vclk: invert video clock polarity.
+ - samsung,fimd-frame-rate: Number of video frames per second.
+
+Example:
+
+ The following is an example for the fimd controller is split into
+ two portions. The SoC specific portion can be specified in the SoC
+ specific dts file. The board specific portion can be specified in the
+ board specific dts file.
+
+ - SoC Specific portion
+
+ fimd {
+ compatible = samsung,exynos5-fimd;
+ interrupt-parent = combiner;
+ reg = 0x1440 0x4;
+ interrupts = 18 5, 18 4, 18 6;
+ };
+
+ - Board Specific portion
+
+ lcd_fimd0: lcd_panel0 {
+ lcd-htiming = 4 4 4 480;
+ lcd-vtiming = 4 4 4 320;
+ supports-mipi-panel;
+ };
+
+ fimd {
+ samsung,fimd-display = lcd_fimd0;
+ samsung,fimd-vidout-rgb;
+ samsung,fimd-inv-vclk;
+ samsung,fimd-frame-rate = 60;
+ samsung,default-window = 0;
+ samsung,fimd-win-bpp = 32;
+ };
+
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 3701fbe..a4fa8e9 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -18,6 +18,7 @@
#include linux/platform_device.h
#include linux/clk.h
#include linux/pm_runtime.h
+#include linux/of.h
#include video/samsung_fimd.h
#include drm/exynos_drm.h
@@ -103,9 +104,18 @@ struct fimd_context {
struct exynos_drm_panel_info *panel;
};
+static const struct of_device_id fimd_dt_match[];
+
static inline struct fimd_driver_data *drm_fimd_get_driver_data(
struct platform_device *pdev)
{
+#ifdef CONFIG_OF
+ if (pdev-dev.of_node) {
+ const struct of_device_id *match;
+ match = of_match_ptr(fimd_dt_match);
+ return (struct fimd_driver_data *)match-data;
+ }
+#endif
return (struct fimd_driver_data *)
platform_get_device_id(pdev)-driver_data;
}
@@ -809,12 +819,77 @@ static int fimd_power_on(struct fimd_context *ctx, bool
enable)
return 0;
}
+#ifdef CONFIG_OF
+static struct exynos_drm_fimd_pdata *drm_fimd_dt_parse_pdata(struct device
*dev)
+{
+ struct device_node *np = dev-of_node;
+ struct device_node *disp_np;
+ struct exynos_drm_fimd_pdata *pd;
+ u32 data[4];
+
+ pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+ if (!pd) {
+
Re: [PATCH V4 2/2] video: drm: exynos: Add device tree support
Hi,
On Thu, Sep 6, 2012 at 12:39 AM, Leela Krishna Amudala
l.kris...@samsung.com wrote:
Add device tree based discovery support for DRM-FIMD driver.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
Documentation/devicetree/bindings/fb/drm-fimd.txt | 80 +
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 95
-
2 files changed, 173 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/fb/drm-fimd.txt
diff --git a/Documentation/devicetree/bindings/fb/drm-fimd.txt
b/Documentation/devicetree/bindings/fb/drm-fimd.txt
new file mode 100644
index 000..4ff1829
--- /dev/null
+++ b/Documentation/devicetree/bindings/fb/drm-fimd.txt
@@ -0,0 +1,80 @@
+* Samsung Display Controller using DRM frame work
+
+The display controller is used to transfer image data from memory to an
+external LCD driver interface. It supports various color formats such as
+rgb and yuv.
+
+Required properties:
+ - compatible: Should be samsung,exynos5-fimd or samsung,exynos4-fb for
Doesn't better to use single word? fimd or fb?. I think 'fb' is used
for framebuffer historically.
but now it's used both fb and drm, so fimd is neutral and architecture
specific.
To do this, Modify arch-exynos first and update it at each drivers it properly.
Thank you,
Kyungmin Park
+ fimd using DRM frame work.
+ - reg: physical base address of the controller and length of memory
+ mapped region.
+ - interrupts: Three interrupts should be specified. The interrupts should be
+ specified in the following order.
+ - VSYNC interrupt
+ - FIFO level interrupt
+ - FIMD System Interrupt
+
+ - samsung,fimd-display: This property should specify the phandle of the
+ display device node which holds the video interface timing with the
+ below mentioned properties.
+
+ - lcd-htiming: Specifies the horizontal timing for the overlay. The
+ horizontal timing includes four parameters in the following order.
+
+ - horizontal back porch (in number of lcd clocks)
+ - horizontal front porch (in number of lcd clocks)
+ - hsync pulse width (in number of lcd clocks)
+ - Display panels X resolution.
+
+ - lcd-vtiming: Specifies the vertical timing for the overlay. The
+ vertical timing includes four parameters in the following order.
+
+ - vertical back porch (in number of lcd lines)
+ - vertical front porch (in number of lcd lines)
+ - vsync pulse width (in number of lcd clocks)
+ - Display panels Y resolution.
+
+
+ - samsung,default-window: Specifies the default window number of the fimd
controller.
+
+ - samsung,fimd-win-bpp: Specifies the bits per pixel.
+
+Optional properties:
+ - samsung,fimd-vidout-rgb: Video output format is RGB.
+ - samsung,fimd-inv-vclk: invert video clock polarity.
+ - samsung,fimd-frame-rate: Number of video frames per second.
+
+Example:
+
+ The following is an example for the fimd controller is split into
+ two portions. The SoC specific portion can be specified in the SoC
+ specific dts file. The board specific portion can be specified in the
+ board specific dts file.
+
+ - SoC Specific portion
+
+ fimd {
+ compatible = samsung,exynos5-fimd;
+ interrupt-parent = combiner;
+ reg = 0x1440 0x4;
+ interrupts = 18 5, 18 4, 18 6;
+ };
+
+ - Board Specific portion
+
+ lcd_fimd0: lcd_panel0 {
+ lcd-htiming = 4 4 4 480;
+ lcd-vtiming = 4 4 4 320;
+ supports-mipi-panel;
+ };
+
+ fimd {
+ samsung,fimd-display = lcd_fimd0;
+ samsung,fimd-vidout-rgb;
+ samsung,fimd-inv-vclk;
+ samsung,fimd-frame-rate = 60;
+ samsung,default-window = 0;
+ samsung,fimd-win-bpp = 32;
+ };
+
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 3701fbe..a4fa8e9 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -18,6 +18,7 @@
#include linux/platform_device.h
#include linux/clk.h
#include linux/pm_runtime.h
+#include linux/of.h
#include video/samsung_fimd.h
#include drm/exynos_drm.h
@@ -103,9 +104,18 @@ struct fimd_context {
struct exynos_drm_panel_info *panel;
};
+static const struct of_device_id fimd_dt_match[];
+
static inline struct fimd_driver_data *drm_fimd_get_driver_data(
struct platform_device *pdev)
{
+#ifdef CONFIG_OF
+ if (pdev-dev.of_node) {
+ const struct of_device_id *match;
+ match = of_match_ptr(fimd_dt_match);
+ return (struct fimd_driver_data *)match-data;
+ }
+#endif
return (struct fimd_driver_data *)
[PATCH 1/2] s5p-fimc: fimc-lite: Correct Bayer pixel format definitions
Replace erroneous V4L2_PIX_FMT_* entries with their V4L2_MBUS_FMT_*
counterparts. This enables use of raw Bayer formats on FIMC-LITE.?
subdevs.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/media/video/s5p-fimc/fimc-lite-reg.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/media/video/s5p-fimc/fimc-lite-reg.c
b/drivers/media/video/s5p-fimc/fimc-lite-reg.c
index 09dc71e..a22d7eb 100644
--- a/drivers/media/video/s5p-fimc/fimc-lite-reg.c
+++ b/drivers/media/video/s5p-fimc/fimc-lite-reg.c
@@ -118,9 +118,9 @@ static const u32 src_pixfmt_map[8][3] = {
FLITE_REG_CIGCTRL_YUV422_1P },
{ V4L2_MBUS_FMT_VYUY8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY,
FLITE_REG_CIGCTRL_YUV422_1P },
- { V4L2_PIX_FMT_SGRBG8, 0, FLITE_REG_CIGCTRL_RAW8 },
- { V4L2_PIX_FMT_SGRBG10, 0, FLITE_REG_CIGCTRL_RAW10 },
- { V4L2_PIX_FMT_SGRBG12, 0, FLITE_REG_CIGCTRL_RAW12 },
+ { V4L2_MBUS_FMT_SGRBG8_1X8, 0, FLITE_REG_CIGCTRL_RAW8 },
+ { V4L2_MBUS_FMT_SGRBG10_1X10, 0, FLITE_REG_CIGCTRL_RAW10 },
+ { V4L2_MBUS_FMT_SGRBG12_1X12, 0, FLITE_REG_CIGCTRL_RAW12 },
{ V4L2_MBUS_FMT_JPEG_1X8, 0, FLITE_REG_CIGCTRL_USER(1) },
};
--
1.7.11.3
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[PATCH 2/2] s5p-fimc: fimc-lite: Propagate frame format on the subdev
When setting image format on subdev's sink pad there was no
propagation to the source pad. This resulted in wrong reported
format on the source pad and wrong device configuration when
used from subdev interace level only. Correct this by propagating
format from the sink to the source pad.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/media/video/s5p-fimc/fimc-lite.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/media/video/s5p-fimc/fimc-lite.c
b/drivers/media/video/s5p-fimc/fimc-lite.c
index 9289008..cd4cf12 100644
--- a/drivers/media/video/s5p-fimc/fimc-lite.c
+++ b/drivers/media/video/s5p-fimc/fimc-lite.c
@@ -1064,6 +1064,7 @@ static int fimc_lite_subdev_set_fmt(struct v4l2_subdev
*sd,
struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
struct v4l2_mbus_framefmt *mf = fmt-format;
struct flite_frame *sink = fimc-inp_frame;
+ struct flite_frame *source = fimc-out_frame;
const struct fimc_fmt *ffmt;
v4l2_dbg(1, debug, sd, pad%d: code: 0x%x, %dx%d,
@@ -1097,8 +1098,10 @@ static int fimc_lite_subdev_set_fmt(struct v4l2_subdev
*sd,
sink-rect.height = mf-height;
sink-rect.left = 0;
sink-rect.top = 0;
- /* Reset source crop rectangle */
- fimc-out_frame.rect = sink-rect;
+ /* Reset source format and crop rectangle */
+ source-rect = sink-rect;
+ source-f_width = mf-width;
+ source-f_height = mf-height;
} else {
/* Allow changing format only on sink pad */
mf-code = fimc-fmt-mbus_code;
--
1.7.11.3
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Re: [PATCH v3 1/4] pinctrl: add samsung pinctrl and gpiolib driver
Hi Thomas,
Thomas Abraham wrote:
Add a new device tree enabled pinctrl and gpiolib driver for Samsung
SoC's. This driver provides a common and extensible framework for all
Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This
driver supports only device tree based instantiation and hence can be
used only on those Samsung platforms that have device tree enabled.
This driver is split into two parts: the pinctrl interface and the gpiolib
interface. The pinctrl interface registers pinctrl devices with the
pinctrl subsystem and gpiolib interface registers gpio chips with the
gpiolib subsystem. The information about the pins, pin groups, pin
functions and gpio chips, which are SoC specific, are parsed from device
tree node.
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Does the driver provide any kind of compatibility with current gpiolib
users?
Let me show an example of what I mean. We have a fixed voltage regulator
defined in device tree of an imaginary board
vemmc_reg: voltage-regulator@0 {
compatible = regulator-fixed;
regulator-name = VMEM_VDD_2.8V;
regulator-min-microvolt = 280;
regulator-max-microvolt = 280;
gpio = gpk0 2 1 0 0;
enable-active-high;
};
The gpio pin used to control status of the regulator is defined using the
gpio property and regulator-fixed driver uses of_get_named_gpio to get the
pin number from device tree.
Is this kind of setup also valid when using your pinctrl driver?
Best regards,
--
Tomasz Figa
Samsung Poland RD Center
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Re: [PATCH v3 1/4] pinctrl: add samsung pinctrl and gpiolib driver
On 5 September 2012 19:20, Tomasz Figa t.f...@samsung.com wrote:
Hi Thomas,
Thomas Abraham wrote:
Add a new device tree enabled pinctrl and gpiolib driver for Samsung
SoC's. This driver provides a common and extensible framework for all
Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This
driver supports only device tree based instantiation and hence can be
used only on those Samsung platforms that have device tree enabled.
This driver is split into two parts: the pinctrl interface and the gpiolib
interface. The pinctrl interface registers pinctrl devices with the
pinctrl subsystem and gpiolib interface registers gpio chips with the
gpiolib subsystem. The information about the pins, pin groups, pin
functions and gpio chips, which are SoC specific, are parsed from device
tree node.
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Does the driver provide any kind of compatibility with current gpiolib
users?
Let me show an example of what I mean. We have a fixed voltage regulator
defined in device tree of an imaginary board
vemmc_reg: voltage-regulator@0 {
compatible = regulator-fixed;
regulator-name = VMEM_VDD_2.8V;
regulator-min-microvolt = 280;
regulator-max-microvolt = 280;
gpio = gpk0 2 1 0 0;
enable-active-high;
};
The gpio pin used to control status of the regulator is defined using the
gpio property and regulator-fixed driver uses of_get_named_gpio to get the
pin number from device tree.
Is this kind of setup also valid when using your pinctrl driver?
Hi Tomasz,
It is possible to get the pin number using of_get_named_gpio()
function with the gpiolib support included in the Samsung pinctrl
driver. The following are the steps on how this can be done. Please
note that, the old Samsung gpio binding will change when we switch the
pinctrl driver. But that was inevitable.
1. The gpio binding will now follow the standard gpio binding.
Which means, it will be something like
uart@1380 {
the usual bindings here
gpios = pinctrl_0 10 0;
};
Note that,
A. First cell: the pin-controller instance is used as the phandle
(i.e pinctrl_0).
B. Second cell: the pin number __local__ to the pin controller instance.
C. Third cell: Flags associated with the gpio pin (as per standard binding).
The pin number specified in the second cell is local to the
pin-controller instance.
For example, the Exynos4210 GPJ1[1] pin, which belongs to pinctrl instance 1,
will have pin number (pin number local to pinctrl instance 1) as 10.
That is because, the number of pins in GPJ0 is 8. So GPJ1[1] =
nr_pins(GPJ0) + 2
= 8 + 2 = 10.
Yes, I understand that this is hard to derive the pin number like
this and write
in the dts(i) files, but while writing the pinctrl driver, there
were two thoughts.
A. The pin numbers for all the pins included in a pinctrl instance
will be documented
in the device tree binding documentation. So it can be easily looked up.
B. How many instances of listing gpio number like this will ever be
needed for a
board dts file. Not much, maybe atmost 10.
Considering the two points above, it seemed okay to derive the pin
numbers for
the gpio as listed in the above example.
2. The client driver can now lookup the pin number using
gpio = of_get_gpio(dev-of_node);
which returns the pin number in the linux gpio space.
So, it is possible to lookup the pin number using Samsung pinctrl driver.
But, I have missed adding the #gpio-cells property in the three
instances of the pinctrl driver. If you are trying this, please add
#gpio-cells = 2;
line in all the three instances of the pinctrl controller nodes. I
will send this change as a separate patch.
Thanks,
Thomas.
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Re: [PATCH] ARM: Samsung: Remove unused code for the clocks debug-fs interface
On 09/05/2012 12:41 AM, Kukjin Kim wrote: Yeah, could be. BTW, following will fix it on Samsung platforms? Yes, that might be better. I tried something similar but thought it might not be worth to invest in a dead horse.. Anyway, since converting all Samsung platforms is expected to take some time (also all this out of tree code) probably better to apply this fix now, before we have an alternative solution. I noticed the most of clocks hove now reported wrong rate value in this debugs-fs tree, due to not calling get_rate when needed. It's not really important though (looks like it's by design). -- Regards, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: exynos: mct: cache mct upper count
Saves one register read.
BUG=none
TEST=See below.
Before (perf report):
1.40% [k] exynos4_frc_read
|
|--87.20%-- ktime_get_ts
| |
| |--93.60%-- posix_ktime_get_ts
After (perf report):
1.00% [k] exynos4_frc_read
|
|--88.61%-- ktime_get_ts
| |
| |--92.70%-- posix_ktime_get_ts
Signed-off-by: Mandeep Singh Baines m...@chromium.org
CC: Sonny Rao sonny...@chromium.org
CC: Olof Johansson ol...@chromium.org
CC: Kukjin Kim kgene@samsung.com
CC: Russell King li...@arm.linux.org.uk
CC: linux-arm-ker...@lists.infradead.org
CC: linux-samsung-soc@vger.kernel.org
---
arch/arm/mach-exynos/mct.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index b601fb8..2bbd533 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -128,8 +128,8 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
static cycle_t exynos4_frc_read(struct clocksource *cs)
{
- unsigned int lo, hi;
- u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+ u32 lo, hi;
+ static u32 hi2;
do {
hi = hi2;
--
1.7.7.3
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[PATCH] ARM: exynos: mct: cache mct upper count
Saves one register read.
Before (perf report):
1.40% [k] exynos4_frc_read
|
|--87.20%-- ktime_get_ts
| |
| |--93.60%-- posix_ktime_get_ts
After (perf report):
1.00% [k] exynos4_frc_read
|
|--88.61%-- ktime_get_ts
| |
| |--92.70%-- posix_ktime_get_ts
Signed-off-by: Mandeep Singh Baines m...@chromium.org
CC: Sonny Rao sonny...@chromium.org
CC: Olof Johansson ol...@chromium.org
CC: Kukjin Kim kgene@samsung.com
CC: Russell King li...@arm.linux.org.uk
CC: linux-arm-ker...@lists.infradead.org
CC: linux-samsung-soc@vger.kernel.org
---
arch/arm/mach-exynos/mct.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index b601fb8..2bbd533 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -128,8 +128,8 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
static cycle_t exynos4_frc_read(struct clocksource *cs)
{
- unsigned int lo, hi;
- u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+ u32 lo, hi;
+ static u32 hi2;
do {
hi = hi2;
--
1.7.7.3
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Re: [PATCH] ASoC: SAMSUNG: Add SND_SOC_DAIFMT_CONT option for snd_soc_set_fmt()
On Mon, Sep 03, 2012 at 11:10:03AM +0900, Sangsu Park wrote: On Sun, Aug 31, 2012 at 2:43 AM +0900, Mark Brown wrote: On Wed, Aug 29, 2012 at 08:06:32PM +0900, Sangsu Park wrote: Please check your mailer configuration, it looks like it's reformatting all the text with much longer line widths. I've changed line width configuration. Is it ok now? Looks like it, thanks. Do you think that changing pcm driver is right approach? Then I'll fix pcm driver. (I think that pcm driver has some strange code.) Well, we could do both. It'd certainly be more natural to make it have a default given that this isn't something that normally needs to be configured. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3] ARM: S3C24XX: Add WIZnet W5300E01-ARM board support
- The gpio routines are changed to use the gpio_request() functions from
comments of Vasily and Sylwester.
- The mistake of adding a character by my email client automatically is fixed.
Please review this patch and apply it if do not have any problems.
Signed-off-by: Taehun Kim kth3...@gmail.com
---
arch/arm/mach-s3c24xx/Kconfig |5 +
arch/arm/mach-s3c24xx/Makefile|1 +
arch/arm/mach-s3c24xx/mach-w5300e01.c | 193 +
3 files changed, 199 insertions(+)
create mode 100644 arch/arm/mach-s3c24xx/mach-w5300e01.c
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index d56b0f7..94b60ca 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -248,6 +248,11 @@ config MACH_VR1000
help
Say Y here if you are using the Thorcom VR1000 board.
+config MACH_W5300E01
+ bool WIZnet W5300E01-ARM Board
+ help
+ Say Y here if you are using the Wiznet W5300E01-ARM board.
+
endif # CPU_S3C2410
config S3C2412_PM_SLEEP
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 0ab6ab1..fc1a89e 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_MACH_QT2410) += mach-qt2410.o
obj-$(CONFIG_ARCH_SMDK2410)+= mach-smdk2410.o
obj-$(CONFIG_MACH_TCT_HAMMER) += mach-tct_hammer.o
obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o
+obj-$(CONFIG_MACH_W5300E01)+= mach-w5300e01.o
obj-$(CONFIG_MACH_JIVE)+= mach-jive.o
obj-$(CONFIG_MACH_SMDK2413)+= mach-smdk2413.o
diff --git a/arch/arm/mach-s3c24xx/mach-w5300e01.c
b/arch/arm/mach-s3c24xx/mach-w5300e01.c
new file mode 100644
index 000..ab648e5
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/mach-w5300e01.c
@@ -0,0 +1,193 @@
+/* linux/arch/arm/mach-s3c24xx/mach-w5300e01.c
+ *
+ * Copyright (c) 2012 Taehun Kim kth3...@gmail.com
+ *
+ * For product information, visit http://www.wiznet.co.kr/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * @History:
+ * derived from linux/arch/arm/mach-s3c24xx/mach-bast.c, written by
+ * Ben Dooks b...@simtec.co.uk
+ */
+
+#include linux/kernel.h
+#include linux/types.h
+#include linux/interrupt.h
+#include linux/list.h
+#include linux/timer.h
+#include linux/init.h
+#include linux/serial_core.h
+#include linux/platform_device.h
+#include linux/gpio.h
+#include linux/io.h
+#include linux/mtd/mtd.h
+#include linux/mtd/nand.h
+#include linux/mtd/map.h
+#include linux/mtd/partitions.h
+
+#include asm/mach/arch.h
+#include asm/mach/map.h
+#include asm/mach/irq.h
+#include asm/mach-types.h
+
+#include mach/regs-gpio.h
+#include plat/gpio-cfg.h
+#include plat/cpu.h
+#include plat/devs.h
+#include plat/regs-serial.h
+#include plat/nand.h
+#include plat/pm.h
+
+static struct map_desc w5300e01_iodesc[] __initdata = {
+ /* Character LCD register map. */
+ { 0xf800, __phys_to_pfn(S3C2410_CS3), SZ_1M, MT_DEVICE }
+};
+
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+
+static struct s3c2410_uartcfg w5300e01_uartcfgs[] __initdata = {
+ [0] = {
+ .hwport = 0,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+ [2] = {
+ .hwport = 2,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ }
+};
+
+static struct mtd_partition w5300e01_mtd_partitions[] = {
+ [0] = {
+ .name = Bootloader,
+ .size = 0x2,
+ .offset = 0,
+ .mask_flags = MTD_WRITEABLE,
+ },
+ [1] = {
+ .name = Boot Param,
+ .size = 0x2,
+ .offset = MTDPART_OFS_APPEND,
+ },
+ [2] = {
+ .name = Kernel,
+ .size = 0x3C,
+ .offset = MTDPART_OFS_APPEND,
+ },
+ [3] = {
+ .name = Ramdisk,
+ .size = 0x100,
+ .offset = MTDPART_OFS_APPEND,
+ },
+ [4] = {
+ .name = JFFS2 FileSystem,
+ .size = MTDPART_SIZ_FULL,
+ .offset = MTDPART_OFS_APPEND,
+ },
+};
+
+static struct resource w5300_resources[] = {
