Re: [PATCH V5 05/12] Documentation: Add DT bindings for panel-lvds driver

[Ajay kumar]

Hi Thierry,

Thanks for your comments.

On Fri, Jul 18, 2014 at 4:18 AM, Thierry Reding
 wrote:
> On Fri, Jul 18, 2014 at 02:20:39AM +0530, Ajay kumar wrote:
>> +devicet...@vger.kernel.org
>>
>> On Fri, Jul 18, 2014 at 2:13 AM, Ajay Kumar  wrote:
>> > Add DT binding documentation for panel-lvds driver.
>> >
>> > Signed-off-by: Ajay Kumar 
>> > ---
>> >  .../devicetree/bindings/panel/panel-lvds.txt   |   50 
>> > 
>> >  1 file changed, 50 insertions(+)
>> >  create mode 100644 Documentation/devicetree/bindings/panel/panel-lvds.txt
>> >
>> > diff --git a/Documentation/devicetree/bindings/panel/panel-lvds.txt 
>> > b/Documentation/devicetree/bindings/panel/panel-lvds.txt
>> > new file mode 100644
>> > index 000..fdf91da2
>> > --- /dev/null
>> > +++ b/Documentation/devicetree/bindings/panel/panel-lvds.txt
>> > @@ -0,0 +1,50 @@
>> > +panel interface for eDP/lvds panels
>> > +
>> > +Required properties:
>> > +  - compatible: "panel-lvds"
>
> I think I've said this before. I oppose the addition of this binding. We
> need to list a device-specific compatible value here, wildcards like
> this aren't a good choice. And then if we have that compatible value we
> can move most of the optional properties below into a driver.
Yes, "panel-lvds" is a wildcard for all lvds panels.
And since lvds panels from different vendors have different values
for power_up_delay, delay from video_to_backlight etc, I thought its
better to pick them up from device tree.

>> > +Optional properties:
>
> If all these properties are optional, then what happens if a device tree
> node doesn't contain any of them? Doesn't that turn the driver into one
> big no-op?
No! We need to provide lcd-supply and backlight-supply.

>> > +   -lcd-enable-gpios:
>> > +   panel LCD poweron GPIO.
>> > +   Indicates which GPIO needs to be powered up as 
>> > output
>> > +   to powerup/enable the switch to the LCD panel.
>> > +   -backlight-enable-gpios:
>> > +   panel LED enable GPIO.
>> > +   Indicates which GPIO needs to be powered up as 
>> > output
>> > +   to enable the backlight.
>
> I've also said before that this really belongs in a backlight driver.
> Chances are that you'll want to have a way to set the brightness of the
> backlight as well, so simply an enable GPIO won't be good enough.
Ok. I can handle this in backlight driver itself (with some minor glitches).
But, how do I map bridge functions to panel functions now?
The bridge supports (pre_enable, enable, disable and post_disable) which I map
with (prepare, enable, disable and unprepare) of the panel, using a sample layer
called bridge to panel_binder.
Moving out the backlight control from panel means I really don't need
those extra
panel calls(prepare and unprepare)!
Then how to distribute 2 panel calls(enable and disable) across 4 bridge calls?

>> > +   -panel-prepare-delay:
>> > +   delay value in ms required for panel_prepare process
>> > +   Delay in ms needed for the panel LCD unit to
>> > +   powerup completely.
>> > +   ex: delay needed till eDP panel throws HPD.
>> > +   delay needed so that we cans tart reading edid.
>
> If the panel signals HPD then we don't need this delay at all and we
> should just wait for HPD instead.
Not always for HPD, we need to wait for EDID module as well.

>> > +   -panel-enable-delay:
>> > +   delay value in ms required for panel_enable process
>> > +   Delay in ms needed for the panel backlight/LED unit
>> > +   to powerup, and delay needed between video_enable 
>> > and
>> > +   backlight_enable.
>> > +   -panel-disable-delay:
>> > +   delay value in ms required for panel_disable process
>> > +   Delay in ms needed for the panel backlight/LED unit
>> > +   powerdown, and delay needed between 
>> > backlight_disable
>> > +   and video_disable.
>> > +   -panel-unprepare-delay:
>> > +   delay value in ms required for panel_post_disable process
>> > +   Delay in ms needed for the panel LCD unit to
>> > +   to powerdown completely, and the minimum delay 
>> > needed
>> > +   before powering it on again.
>
> These delays are all panel specific and they don't vary per board, so
> they shouldn't go into the device tree at all.
But, fetching them from device tree would allow us to support all lvds
panels in this single driver.

Thanks and Regards,
Ajay Kumar
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Re: [PATCH v2 0/4] Add Exynos4412 based Odroid X2 and U2/U3/U3+ support

[Daniel Drake]

Hi Olof,

Thanks for joining the party here :)

On Fri, Jul 18, 2014 at 6:56 AM, Olof Johansson  wrote:
> Anyone got a simple writeup on the steps needed to boot, bl1/2 needed,
> expected offset into eMMC for where it goes, etc?

https://github.com/hardkernel/u-boot/blob/odroid-v2010.12/sd_fuse/sd_fusing.sh
is probably the best "writeup" :)
https://github.com/hardkernel/u-boot/tree/odroid-v2010.12/sd_fuse has
the blobs needed (they have not changed at all in the U3's history, so
the ones you have already will work fine).

Samsung guys are also upstreaming support into uboot, including a
README.odroid in the last commit with this info:
http://patchwork.ozlabs.org/project/uboot/list/?submitter=23519

> I gave the kernel (next-0717) a go here on my U3, and it boots (as you
> mention, no USB comes up).

Nice. USB works with the later patches floating around.

> I do see a few KERN_ERR printks though:
>
> [ERR] [0.00] L2C: failed to init: -19

This one is fixed with the patch series "Enable L2 cache support on
Exynos4210/4x12 SoCs"

> [ERR] [0.001302] missing device node for CPU 0
> [ERR] [0.001344] missing device node for CPU 1
> [ERR] [0.001366] missing device node for CPU 2
> [ERR] [0.001386] missing device node for CPU 3

Not sure about these - I still get them with all the patches applied.

> [ERR] [0.156490] max77686 0-0009: irq is not specified

I submitted a patch for this, "ARM: dts: Enable PMIC interrupts on ODROID"

> [ERR] [1.339498] /i2c@1386/usb3503@08: could not get
> #clock-cells for /system-controller@1002
> [ERR] [1.348050] ERROR: could not get clock
> /i2c@1386/usb3503@08:refclk(0)

I think these go away with the USB patches floating around.

> [ERR] [1.383055] max77686-rtc max77686-rtc: max77686_rtc_init_reg:
> fail to write controlm reg(-6)
> [ERR] [1.391108] max77686-rtc max77686-rtc: Failed to initialize RTC 
> reg:-6

Fixed with "ARM: dts: ODROID i2c improvements"

Daniel
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Re: [PATCH v2 0/4] Add Exynos4412 based Odroid X2 and U2/U3/U3+ support

[Olof Johansson]

On Thu, Jul 17, 2014 at 10:56 PM, Olof Johansson  wrote:

> I gave the kernel (next-0717) a go here on my U3, and it boots (as you
> mention, no USB comes up).

Btw, please update multi_v7_defconfig as well (as a separate patch,
since it needs to be merged directly by us). Right now it doesn't find
rootfs with that config.


-Olof
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[PATCHv6 2/4] iio: adc: exynos_adc: Control special clock of ADC to support Exynos3250 ADC

[Chanwoo Choi]

This patch control special clock for ADC in Exynos series's FSYS block.
If special clock of ADC is registerd on clock list of common clk framework,
Exynos ADC drvier have to control this clock.

Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
- 'adc' clock: bus clock for ADC

Exynos3250 has additional 'sclk_adc' clock as following:
- 'sclk_adc' clock: special clock for ADC which provide clock to internal ADC

Exynos 4210/4212/4412 and Exynos5250/5420 has not included 'sclk_adc' clock
in FSYS_BLK. But, Exynos3250 based on Cortex-A7 has only included 'sclk_adc'
clock in FSYS_BLK.

Signed-off-by: Chanwoo Choi 
Acked-by: Kyungmin Park 
Reviewed-by: Tomasz Figa 
---
 drivers/iio/adc/exynos_adc.c | 112 ++-
 1 file changed, 101 insertions(+), 11 deletions(-)

diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index 00d67fd..b63e882 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -81,9 +81,11 @@
 
 struct exynos_adc {
struct exynos_adc_data  *data;
+   struct device   *dev;
void __iomem*regs;
void __iomem*enable_reg;
struct clk  *clk;
+   struct clk  *sclk;
unsigned intirq;
struct regulator*vdd;
 
@@ -95,6 +97,7 @@ struct exynos_adc {
 
 struct exynos_adc_data {
int num_channels;
+   bool needs_sclk;
 
void (*init_hw)(struct exynos_adc *info);
void (*exit_hw)(struct exynos_adc *info);
@@ -102,6 +105,66 @@ struct exynos_adc_data {
void (*start_conv)(struct exynos_adc *info, unsigned long addr);
 };
 
+static void exynos_adc_unprepare_clk(struct exynos_adc *info)
+{
+   if (info->data->needs_sclk)
+   clk_unprepare(info->sclk);
+   clk_unprepare(info->clk);
+}
+
+static int exynos_adc_prepare_clk(struct exynos_adc *info)
+{
+   int ret;
+
+   ret = clk_prepare(info->clk);
+   if (ret) {
+   dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
+   return ret;
+   }
+
+   if (info->data->needs_sclk) {
+   ret = clk_prepare(info->sclk);
+   if (ret) {
+   clk_unprepare(info->clk);
+   dev_err(info->dev,
+   "failed preparing sclk_adc clock: %d\n", ret);
+   return ret;
+   }
+   }
+
+   return 0;
+}
+
+static void exynos_adc_disable_clk(struct exynos_adc *info)
+{
+   if (info->data->needs_sclk)
+   clk_disable(info->sclk);
+   clk_disable(info->clk);
+}
+
+static int exynos_adc_enable_clk(struct exynos_adc *info)
+{
+   int ret;
+
+   ret = clk_enable(info->clk);
+   if (ret) {
+   dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
+   return ret;
+   }
+
+   if (info->data->needs_sclk) {
+   ret = clk_enable(info->sclk);
+   if (ret) {
+   clk_disable(info->clk);
+   dev_err(info->dev,
+   "failed enabling sclk_adc clock: %d\n", ret);
+   return ret;
+   }
+   }
+
+   return 0;
+}
+
 static void exynos_adc_v1_init_hw(struct exynos_adc *info)
 {
u32 con1;
@@ -199,13 +262,20 @@ static void exynos_adc_v2_start_conv(struct exynos_adc 
*info,
writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
 }
 
+#define __EXYNOS_ADC_V2_DATA   \
+   .num_channels   = MAX_ADC_V2_CHANNELS,  \
+   .init_hw= exynos_adc_v2_init_hw,\
+   .exit_hw= exynos_adc_v2_exit_hw,\
+   .clear_irq  = exynos_adc_v2_clear_irq,  \
+   .start_conv = exynos_adc_v2_start_conv, \
+
 static struct exynos_adc_data const exynos_adc_v2_data = {
-   .num_channels   = MAX_ADC_V2_CHANNELS,
+   __EXYNOS_ADC_V2_DATA
+};
 
-   .init_hw= exynos_adc_v2_init_hw,
-   .exit_hw= exynos_adc_v2_exit_hw,
-   .clear_irq  = exynos_adc_v2_clear_irq,
-   .start_conv = exynos_adc_v2_start_conv,
+static struct exynos_adc_data const exynos3250_adc_v2_data = {
+   __EXYNOS_ADC_V2_DATA
+   .needs_sclk = true,
 };
 
 static const struct of_device_id exynos_adc_match[] = {
@@ -215,6 +285,9 @@ static const struct of_device_id exynos_adc_match[] = {
}, {
.compatible = "samsung,exynos-adc-v2",
.data = (void *)&exynos_adc_v2_data,
+   }, {
+   .compatible = "samsung,exynos3250-adc-v2",
+   .data = (void *)&exynos3250_adc_v2_data,
},
{},
 };
@@ -376,6 +449,7 @@ static int exynos_adc_probe(struct platform_device *pdev)
}
 
info->irq = irq;
+   info->dev = &pdev->dev;
 
init_completion(&info->completion);
 
@@ -386,6 +460,16 @@ static int exynos

[PATCHv6 4/4] ARM: dts: Fix wrong compatible string for Exynos3250 ADC

[Chanwoo Choi]

This patchset fix wrong compatible string for Exynos3250 ADC. Exynos3250 SoC
need to control only special clock for ADC. Exynos SoC except for Exynos3250
has not included special clock for ADC. The exynos ADC driver can control
special clock if compatible string is 'exynos3250-adc-v2'.

Signed-off-by: Chanwoo Choi 
Acked-by: Kyungmin Park 
Reviewed-by: Tomasz Figa 
Acked-by: Kukjin Kim 
---
 arch/arm/boot/dts/exynos3250.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos3250.dtsi 
b/arch/arm/boot/dts/exynos3250.dtsi
index 3d3c45b..e039818 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -391,10 +391,10 @@
};
 
adc: adc@126C {
-   compatible = "samsung,exynos-adc-v3";
+   compatible = "samsung,exynos3250-adc-v2";
reg = <0x126C 0x100>, <0x10020718 0x4>;
interrupts = <0 137 0>;
-   clock-names = "adc", "sclk_tsadc";
+   clock-names = "adc", "sclk_adc";
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
#io-channel-cells = <1>;
io-channel-ranges;
-- 
1.8.0

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[PATCHv6 3/4] iio: devicetree: Add DT binding documentation for Exynos3250 ADC

[Chanwoo Choi]

This patch add DT binding documentation for Exynos3250 ADC IP. Exynos3250 has
special clock ('sclk_adc') for ADC which provide clock to internal ADC.

Signed-off-by: Chanwoo Choi 
Acked-by: Kyungmin Park 
Reviewed-by: Naveen Krishna Chatradhi 
Reviewed-by: Tomasz Figa 
Acked-by: Kukjin Kim 
---
 .../devicetree/bindings/arm/samsung/exynos-adc.txt | 25 --
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt 
b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index 832fe8c..26232f9 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -14,14 +14,21 @@ Required properties:
for exynos4412/5250 controllers.
Must be "samsung,exynos-adc-v2" for
future controllers.
+   Must be "samsung,exynos3250-adc-v2" for
+   controllers compatible with ADC of Exynos3250.
 - reg: Contains ADC register address range (base address and
length) and the address of the phy enable register.
 - interrupts:  Contains the interrupt information for the timer. The
format is being dependent on which interrupt controller
the Samsung device uses.
 - #io-channel-cells = <1>; As ADC has multiple outputs
-- clocks   From common clock binding: handle to adc clock.
-- clock-names  From common clock binding: Shall be "adc".
+- clocks   From common clock bindings: handles to clocks specified
+   in "clock-names" property, in the same order.
+- clock-names  From common clock bindings: list of clock input names
+   used by ADC block:
+   - "adc" : ADC bus clock
+   - "sclk_adc" : ADC special clock (only for Exynos3250
+  and compatible ADC block)
 - vdd-supply   VDD input supply.
 
 Note: child nodes can be added for auto probing from device tree.
@@ -41,6 +48,20 @@ adc: adc@12D1 {
vdd-supply = <&buck5_reg>;
 };
 
+Example: adding device info in dtsi file for Exynos3250 with additional sclk
+
+adc: adc@126C {
+   compatible = "samsung,exynos3250-adc-v2";
+   reg = <0x126C 0x100>, <0x10020718 0x4>;
+   interrupts = <0 137 0>;
+   #io-channel-cells = <1>;
+   io-channel-ranges;
+
+   clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
+   clock-names = "adc", "sclk_adc";
+
+   vdd-supply = <&buck5_reg>;
+};
 
 Example: Adding child nodes in dts file
 
-- 
1.8.0

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[PATCHv6 1/4] iio: adc: exynos_adc: Add exynos_adc_data structure to improve readability

[Chanwoo Choi]

This patchset add 'exynos_adc_data' structure which includes some functions
to control ADC operation and specific data according to ADC version (v1 or v2).

Signed-off-by: Chanwoo Choi 
Acked-by: Kyungmin Park 
Reviewed-by: Naveen Krishna Chatradhi 
Reviewed-by: Tomasz Figa 
---
 drivers/iio/adc/exynos_adc.c | 226 ---
 1 file changed, 147 insertions(+), 79 deletions(-)

diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index 010578f..00d67fd 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -39,11 +39,6 @@
 #include 
 #include 
 
-enum adc_version {
-   ADC_V1,
-   ADC_V2
-};
-
 /* EXYNOS4412/5250 ADC_V1 registers definitions */
 #define ADC_V1_CON(x)  ((x) + 0x00)
 #define ADC_V1_DLY(x)  ((x) + 0x08)
@@ -85,6 +80,7 @@ enum adc_version {
 #define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
 
 struct exynos_adc {
+   struct exynos_adc_data  *data;
void __iomem*regs;
void __iomem*enable_reg;
struct clk  *clk;
@@ -97,43 +93,139 @@ struct exynos_adc {
unsigned intversion;
 };
 
-static const struct of_device_id exynos_adc_match[] = {
-   { .compatible = "samsung,exynos-adc-v1", .data = (void *)ADC_V1 },
-   { .compatible = "samsung,exynos-adc-v2", .data = (void *)ADC_V2 },
-   {},
+struct exynos_adc_data {
+   int num_channels;
+
+   void (*init_hw)(struct exynos_adc *info);
+   void (*exit_hw)(struct exynos_adc *info);
+   void (*clear_irq)(struct exynos_adc *info);
+   void (*start_conv)(struct exynos_adc *info, unsigned long addr);
 };
-MODULE_DEVICE_TABLE(of, exynos_adc_match);
 
-static inline unsigned int exynos_adc_get_version(struct platform_device *pdev)
+static void exynos_adc_v1_init_hw(struct exynos_adc *info)
 {
-   const struct of_device_id *match;
+   u32 con1;
 
-   match = of_match_node(exynos_adc_match, pdev->dev.of_node);
-   return (unsigned int)match->data;
+   writel(1, info->enable_reg);
+
+   /* set default prescaler values and Enable prescaler */
+   con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
+
+   /* Enable 12-bit ADC resolution */
+   con1 |= ADC_V1_CON_RES;
+   writel(con1, ADC_V1_CON(info->regs));
+}
+
+static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
+{
+   u32 con;
+
+   writel(0, info->enable_reg);
+
+   con = readl(ADC_V1_CON(info->regs));
+   con |= ADC_V1_CON_STANDBY;
+   writel(con, ADC_V1_CON(info->regs));
+}
+
+static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
+{
+   writel(1, ADC_V1_INTCLR(info->regs));
 }
 
-static void exynos_adc_hw_init(struct exynos_adc *info)
+static void exynos_adc_v1_start_conv(struct exynos_adc *info,
+unsigned long addr)
+{
+   u32 con1;
+
+   writel(addr, ADC_V1_MUX(info->regs));
+
+   con1 = readl(ADC_V1_CON(info->regs));
+   writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
+}
+
+static struct exynos_adc_data const exynos_adc_v1_data = {
+   .num_channels   = MAX_ADC_V1_CHANNELS,
+
+   .init_hw= exynos_adc_v1_init_hw,
+   .exit_hw= exynos_adc_v1_exit_hw,
+   .clear_irq  = exynos_adc_v1_clear_irq,
+   .start_conv = exynos_adc_v1_start_conv,
+};
+
+static void exynos_adc_v2_init_hw(struct exynos_adc *info)
 {
u32 con1, con2;
 
-   if (info->version == ADC_V2) {
-   con1 = ADC_V2_CON1_SOFT_RESET;
-   writel(con1, ADC_V2_CON1(info->regs));
+   writel(1, info->enable_reg);
 
-   con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
-   ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
-   writel(con2, ADC_V2_CON2(info->regs));
+   con1 = ADC_V2_CON1_SOFT_RESET;
+   writel(con1, ADC_V2_CON1(info->regs));
 
-   /* Enable interrupts */
-   writel(1, ADC_V2_INT_EN(info->regs));
-   } else {
-   /* set default prescaler values and Enable prescaler */
-   con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
+   con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
+   ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
+   writel(con2, ADC_V2_CON2(info->regs));
 
-   /* Enable 12-bit ADC resolution */
-   con1 |= ADC_V1_CON_RES;
-   writel(con1, ADC_V1_CON(info->regs));
-   }
+   /* Enable interrupts */
+   writel(1, ADC_V2_INT_EN(info->regs));
+}
+
+static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
+{
+   u32 con;
+
+   writel(0, info->enable_reg);
+
+   con = readl(ADC_V2_CON1(info->regs));
+   con &= ~ADC_CON_EN_START;
+   writel(con, ADC_V2_CON1(info->regs));
+}
+
+static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
+{
+   writel(1, ADC_V2_INT_ST(info->regs));
+}
+
+static void exynos_adc_v2_start_conv(struct exy

[PATCHv6 0/4] iio: adc: exynos_adc: Support Exynos3250 ADC and code clean

[Chanwoo Choi]

This patchset support Exynos3250 ADC (Analog Digital Converter) because
Exynos3250 has additional special clock for ADC IP.

Changes from v5:
- Add acked message by Kukjin Kim
- Add reviewed messgae by Tomasz Figa
- Fix typo (for for -> for)

Changes from v4:
- Use 'exynos_adc_data' structure instead of 'exynos_adc_ops' structure
  and remove enum variable of ADC version
- Fix wrong name of special clock (sclk_tsadc -> sclk_adc)
- Add reviewed message by Naveen Krishna Chatradhi
- Add functions for ADC clock control

Changes from v3:
- Add new 'exynos_adc_ops' structure to improve readability according to
 Tomasz Figa comment[1]
 [1] https://lkml.org/lkml/2014/4/16/238
- Add new 'exynos3250-adc-v2' compatible string to support Exynos3250 ADC
- Fix wrong compaitlbe string of ADC in Exynos3250 dtsi file

Changes from v2:
- Check return value of clock function to deal with error exception
- Fix minor coding style to improve readability

Changes from v1:
- Add new "samsung,exynos-adc-v3" compatible to support Exynos3250 ADC
- Add a patch about DT binding documentation

Chanwoo Choi (4):
  iio: adc: exynos_adc: Add exynos_adc_data structure to improve
readability
  iio: adc: exynos_adc: Control special clock of ADC to support
Exynos3250 ADC
  iio: devicetree: Add DT binding documentation for Exynos3250 ADC
  ARM: dts: Fix wrong compatible string for Exynos3250 ADC

 .../devicetree/bindings/arm/samsung/exynos-adc.txt |  25 +-
 arch/arm/boot/dts/exynos3250.dtsi  |   4 +-
 drivers/iio/adc/exynos_adc.c   | 326 +++--
 3 files changed, 267 insertions(+), 88 deletions(-)

-- 
1.8.0

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Re: [PATCH v2 0/4] Add Exynos4412 based Odroid X2 and U2/U3/U3+ support

[Olof Johansson]

On Sun, Jun 29, 2014 at 10:34 PM, Marek Szyprowski
 wrote:
> Hello,
>
>
> On 2014-06-25 15:26, Marek Szyprowski wrote:
>>
>> Hello,
>>
>> This is the second version of the initial patch series adding support
>> for Exynos 4412 based Odroid X2 and U2/U3/U3+ boards and improving
>> support for Odroid X.
>>
>> Complete USB support for Odroid U2/U3/U3+ still requires some fixes in
>> Exynos4 USB2 Phy driver and clock driver for CLKOUT:
>> http://thread.gmane.org/gmane.linux.kernel/1731843/
>> http://www.spinics.net/lists/linux-usb/msg109587.html
>> The above changes however don't affect Odroid DTS files, but without
>> them, usb3503 hub is not yet functional.
>>
>> Support for audio codec will be posted separately by Sylwester Nawrocki
>> soon. Support for HDMI video output will be also posted separately
>> together with the required ExynosDRM-HDMI fixes.
>>
>> If one is interested in more complete and open-source Odroid board
>> support, there are also patches for u-boot project:
>> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/188295/focus=188610
>
>
> Just to let everyone knows - updated Odroid patches for uboot has been
> posted in the following thread:
> http://www.mail-archive.com/u-boot@lists.denx.de/msg141234.html
> You can also download them here:
> http://patchwork.ozlabs.org/project/uboot/list/?submitter=23519

Anyone got a simple writeup on the steps needed to boot, bl1/2 needed,
expected offset into eMMC for where it goes, etc?


I gave the kernel (next-0717) a go here on my U3, and it boots (as you
mention, no USB comes up).

I do see a few KERN_ERR printks though:

[ERR] [0.00] L2C: failed to init: -19
[ERR] [0.001302] missing device node for CPU 0
[ERR] [0.001344] missing device node for CPU 1
[ERR] [0.001366] missing device node for CPU 2
[ERR] [0.001386] missing device node for CPU 3
[ERR] [0.156490] max77686 0-0009: irq is not specified
[ERR] [1.339498] /i2c@1386/usb3503@08: could not get
#clock-cells for /system-controller@1002
[ERR] [1.348050] ERROR: could not get clock
/i2c@1386/usb3503@08:refclk(0)
[ERR] [1.383055] max77686-rtc max77686-rtc: max77686_rtc_init_reg:
fail to write controlm reg(-6)
[ERR] [1.391108] max77686-rtc max77686-rtc: Failed to initialize RTC reg:-6


That can be fixed incrementally. I'll add the U3 to my boot farm
starting tonight. Thanks for submitting all this!


-Olof
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RE: [PATCHv5 0/4] iio: adc: exynos_adc: Support Exynos3250 ADC and code clean

[Kukjin Kim]

Jonathan Cameron wrote:
> 
> On 27/06/14 05:30, Chanwoo Choi wrote:
> > Changes from v4:
> > - Use 'exynos_adc_data' structure instead of 'exynos_adc_ops' structure
> >and remove enum variable of ADC version
> > - Fix wrong name of special clock (sclk_tsadc -> sclk_adc)
> > - Add reviewed message by Naveen Krishna Chatradhi
> > - Add functions for ADC clock control
> >
> > Changes from v3:
> > - Add new 'exynos_adc_ops' structure to improve readability according to
> >   Tomasz Figa comment[1]
> >   [1] https://lkml.org/lkml/2014/4/16/238
> > - Add new 'exynos3250-adc-v2' compatible string to support Exynos3250 ADC
> > - Fix wrong compaitlbe string of ADC in Exynos3250 dtsi file
> >
> > Changes from v2:
> > - Check return value of clock function to deal with error exception
> > - Fix minor coding style to improve readability
> >
> > Changes from v1:
> > - Add new "samsung,exynos-adc-v3" compatible to support Exynos3250 ADC
> > - Add a patch about DT binding documentation
> >
> > Chanwoo Choi (4):
> >iio: adc: exynos_adc: Add exynos_adc_data structure to improve 
> > readability
> >iio: adc: exynos_adc: Control special clock of ADC to support Exynos3250 
> > ADC
> >iio: devicetree: Add DT binding documentation for Exynos3250 ADC
> >ARM: dts: Fix wrong compatible string for Exynos3250 ADC
> >
> >   .../devicetree/bindings/arm/samsung/exynos-adc.txt |  26 +-
> >   arch/arm/boot/dts/exynos3250.dtsi  |   4 +-
> >   drivers/iio/adc/exynos_adc.c   | 326 
> > +++--
> >   3 files changed, 268 insertions(+), 88 deletions(-)
> >
> I am happy with this series, but given it touches some exynos bindings, I 
> would
> like an ack from Kukjin Kim (or according to MAINTAINERS Ben Dooks) before 
> taking it
> all through IIO.
> 
Hi,

Sorry for late response...

The change looks good to me, so please go ahead with my ack on exynos stuff.

Acked-by: Kukjin Kim 

Thanks,
Kukjin

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Re: [PATCH v7 0/6] cpufreq: use generic cpufreq drivers for exynos platforms

[Thomas Abraham]

On Fri, Jul 18, 2014 at 6:14 AM, Chanwoo Choi  wrote:
> Hi Thomas,
>
> On 07/17/2014 02:58 PM, Thomas Abraham wrote:
>> Hi Mike,
>>
>> On Tue, Jul 15, 2014 at 9:20 AM, Thomas Abraham  wrote:
>>> Hi Tomasz,
>>>
>>> On Mon, Jul 14, 2014 at 7:08 PM, Thomas Abraham  
>>> wrote:
 Changes since v6:
 - Fixes suggested by Amit Daniel .

 This patch series removes the use of Exynos4210 and Exynos5250 specific 
 cpufreq
 drivers and enables the use of cpufreq-cpu0 driver for these platforms. 
 This
 series also enabled cpufreq support for Exynos5420 using arm_big_little 
 cpufreq
 driver.

 Thomas Abraham (6):
   clk: samsung: add infrastructure to register cpu clocks
   clk: samsung: register exynos5420 apll/kpll configuration data
   clk: exynos: use cpu-clock provider type to represent arm clock
   ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data
   ARM: Exynos: switch to using generic cpufreq driver for exynos4210/5250
   cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
>>>
>>> In this series, support for Exynos5420 has been included. If there are
>>> any more changes required, could you please let me know.
>>
>> This patch series migrates exynos cpufreq support to use generic
>> cpufreq drivers. For this, cpu clock blocks are encapsulated into a
>> cpu clock type and cpufreq driver operates the cpu clock type.
>>
>> We had discussed in the [1] about using coordinated clocks. This
>> series is not using the concept of coordinated clocks but the code in
>> this series can be migrated to use coordinated clocks when it is
>> available.
>>
>> Is it okay to consider this series for v3.17-rc1. I will update this
>> code to use coordinated clocks when it is available. This series helps
>> with cpufreq support for newer Exynos SoCs such as Exynos5420/3250.
>>
>> [1] http://www.spinics.net/lists/cpufreq/msg10042.html
>>
>
> I tested this patchset with Exynos3250 cpufreq patchset[1] on Exynos3250 SoC.
>  [1] https://lkml.org/lkml/2014/6/18/126
>
> Tested-by: Chanwoo Choi 

Hi Chanwoo,

Thanks for using these patches for Exynos3250 cpufreq support.

Regards,
Thomas.


>
> Best Regards,
> Chanwoo Choi
>
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Re: [PATCH v6 09/14] ARM: dts: s6e3fa0: add DT bindings

[YoungJun Cho]

Hi Thierry,

On 07/17/2014 07:38 PM, Thierry Reding wrote:

On Thu, Jul 17, 2014 at 06:01:24PM +0900, YoungJun Cho wrote:

This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources and display timings.


The commit message here should preferably say which platform this is
used on.


Although only exynos drm could use this panel now, I think this panel 
could be used by any platform.

Do you have any good idea for that?




Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
  .../devicetree/bindings/panel/samsung,s6e3fa0.txt  | 46 ++
  1 file changed, 46 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt

diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt 
b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
new file mode 100644
index 000..2cd32f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
@@ -0,0 +1,46 @@
+Samsung S6E3FA0 AMOLED LCD 5.7 inch panel
+
+Required properties:
+  - compatible: "samsung,s6e3fa0"
+  - reg: the virtual channel number of a DSI peripheral
+  - vdd3-supply: core voltage supply
+  - vci-supply: voltage supply for analog circuits
+  - reset-gpios: a GPIO spec for the reset pin
+  - det-gpios: a GPIO spec for the OLED detection pin
+  - te-gpios: a GPIO spec for the TE pin
+  - display-timings: timings for the connected panel as described by [1]


display-timings should be optional. The panel driver should provide a
default mode. And only if you really need to override the default mode
you should provide the option of getting an alternative set of values
from DT.


Could you explain why this display-timings should be optional?
Most of DTs regard display-timings as required property.

Thank you.
Best regards YJ



Thierry



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Re: [PATCH v6 10/14] drm/panel: add S6E3FA0 driver

[YoungJun Cho]

Hi Thierry,

Thank you a lot for kind comments.

On 07/17/2014 07:36 PM, Thierry Reding wrote:

On Thu, Jul 17, 2014 at 06:01:25PM +0900, YoungJun Cho wrote:
[...]

diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c 
b/drivers/gpu/drm/panel/panel-s6e3fa0.c

[...]

+/* Manufacturer Command Set */
+#define MCS_GLOBAL_PARAMETER   0xb0
+#define MCS_AID0xb2
+#define MCS_ELVSSOPT   0xb6
+#define MCS_TEMPERATURE_SET0xb8
+#define MCS_PENTILE_CTRL   0xc0
+#define MCS_GAMMA_MODE 0xca
+#define MCS_VDDM   0xd7
+#define MCS_ALS0xe3
+#define MCS_ERR_FG 0xed
+#define MCS_KEY_LEV1   0xf0
+#define MCS_GAMMA_UPDATE   0xf7
+#define MCS_KEY_LEV2   0xfc
+#define MCS_RE 0xfe
+#define MCS_TOUT2_HSYNC0xff
+
+/* Content Adaptive Brightness Control */
+#define DCS_WRITE_CABC 0x55


Is this not a manufacturer specific command? I couldn't find it in the
DSI or DCS specifications, but it sounds like something standard (also
indicated by the DCS_ prefix). Can you point out the specification for
this?



Andrzej commented before and decided it as DCS one because if the value 
is less than 0xb0, it is DCS one and the others are MCS one.

But still I'm not sure it is correct.


+#define MTP_ID_LEN 3
+#define GAMMA_LEVEL_NUM30
+
+#define DEFAULT_VDDM_VAL   0x15
+
+struct s6e3fa0 {
+   struct device   *dev;
+   struct drm_panelpanel;
+
+   struct regulator_bulk_data  supplies[2];
+   struct gpio_desc*reset_gpio;
+   struct videomodevm;
+
+   unsigned intpower_on_delay;
+   unsigned intreset_delay;
+   unsigned intinit_delay;
+   unsigned intwidth_mm;
+   unsigned intheight_mm;
+
+   unsigned char   id;
+   unsigned char   vddm;
+   unsigned intbrightness;
+};


Please don't use this kind of artificial padding. A simple space will
do.


+
+#define panel_to_s6e3fa0(p) container_of(p, struct s6e3fa0, panel)


Please turn this into a function so we can get proper type checking.


+
+/* VDD Memory Lookup Table contains pairs of {ReadValue, WriteValue} */
+static const unsigned char s6e3fa0_vddm_lut[][2] = {
+   {0x00, 0x0d}, {0x01, 0x0d}, {0x02, 0x0e}, {0x03, 0x0f}, {0x04, 0x10},
+   {0x05, 0x11}, {0x06, 0x12}, {0x07, 0x13}, {0x08, 0x14}, {0x09, 0x15},
+   {0x0a, 0x16}, {0x0b, 0x17}, {0x0c, 0x18}, {0x0d, 0x19}, {0x0e, 0x1a},
+   {0x0f, 0x1b}, {0x10, 0x1c}, {0x11, 0x1d}, {0x12, 0x1e}, {0x13, 0x1f},
+   {0x14, 0x20}, {0x15, 0x21}, {0x16, 0x22}, {0x17, 0x23}, {0x18, 0x24},
+   {0x19, 0x25}, {0x1a, 0x26}, {0x1b, 0x27}, {0x1c, 0x28}, {0x1d, 0x29},
+   {0x1e, 0x2a}, {0x1f, 0x2b}, {0x20, 0x2c}, {0x21, 0x2d}, {0x22, 0x2e},
+   {0x23, 0x2f}, {0x24, 0x30}, {0x25, 0x31}, {0x26, 0x32}, {0x27, 0x33},
+   {0x28, 0x34}, {0x29, 0x35}, {0x2a, 0x36}, {0x2b, 0x37}, {0x2c, 0x38},
+   {0x2d, 0x39}, {0x2e, 0x3a}, {0x2f, 0x3b}, {0x30, 0x3c}, {0x31, 0x3d},
+   {0x32, 0x3e}, {0x33, 0x3f}, {0x34, 0x3f}, {0x35, 0x3f}, {0x36, 0x3f},
+   {0x37, 0x3f}, {0x38, 0x3f}, {0x39, 0x3f}, {0x3a, 0x3f}, {0x3b, 0x3f},
+   {0x3c, 0x3f}, {0x3d, 0x3f}, {0x3e, 0x3f}, {0x3f, 0x3f}, {0x40, 0x0c},
+   {0x41, 0x0b}, {0x42, 0x0a}, {0x43, 0x09}, {0x44, 0x08}, {0x45, 0x07},
+   {0x46, 0x06}, {0x47, 0x05}, {0x48, 0x04}, {0x49, 0x03}, {0x4a, 0x02},
+   {0x4b, 0x01}, {0x4c, 0x40}, {0x4d, 0x41}, {0x4e, 0x42}, {0x4f, 0x43},
+   {0x50, 0x44}, {0x51, 0x45}, {0x52, 0x46}, {0x53, 0x47}, {0x54, 0x48},
+   {0x55, 0x49}, {0x56, 0x4a}, {0x57, 0x4b}, {0x58, 0x4c}, {0x59, 0x4d},
+   {0x5a, 0x4e}, {0x5b, 0x4f}, {0x5c, 0x50}, {0x5d, 0x51}, {0x5e, 0x52},
+   {0x5f, 0x53}, {0x60, 0x54}, {0x61, 0x55}, {0x62, 0x56}, {0x63, 0x57},
+   {0x64, 0x58}, {0x65, 0x59}, {0x66, 0x5a}, {0x67, 0x5b}, {0x68, 0x5c},
+   {0x69, 0x5d}, {0x6a, 0x5e}, {0x6b, 0x5f}, {0x6c, 0x60}, {0x6d, 0x61},
+   {0x6e, 0x62}, {0x6f, 0x63}, {0x70, 0x64}, {0x71, 0x65}, {0x72, 0x66},
+   {0x73, 0x67}, {0x74, 0x68}, {0x75, 0x69}, {0x76, 0x6a}, {0x77, 0x6b},
+   {0x78, 0x6c}, {0x79, 0x6d}, {0x7a, 0x6e}, {0x7b, 0x6f}, {0x7c, 0x70},
+   {0x7d, 0x71}, {0x7e, 0x72}, {0x7f, 0x73},
+};


What's this used for?



This ldi contains an internal memory and requires an appropriate VDD.
Each panel stores OTP value for this vddm, so reads this value, finds 
matching value with vddm_lut and writes the final value to avoid noise 
issues from an inappropriate VDD.



+static int s6e3fa0_dcs_read(struct s6e3fa0 *ctx, unsigned char cmd,
+   void *data, size_t len)
+{
+   struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+
+   return mipi_dsi_dcs_read

Re: [PATCH v7 0/6] cpufreq: use generic cpufreq drivers for exynos platforms

[Chanwoo Choi]

Hi Thomas,

On 07/17/2014 02:58 PM, Thomas Abraham wrote:
> Hi Mike,
> 
> On Tue, Jul 15, 2014 at 9:20 AM, Thomas Abraham  wrote:
>> Hi Tomasz,
>>
>> On Mon, Jul 14, 2014 at 7:08 PM, Thomas Abraham  
>> wrote:
>>> Changes since v6:
>>> - Fixes suggested by Amit Daniel .
>>>
>>> This patch series removes the use of Exynos4210 and Exynos5250 specific 
>>> cpufreq
>>> drivers and enables the use of cpufreq-cpu0 driver for these platforms. This
>>> series also enabled cpufreq support for Exynos5420 using arm_big_little 
>>> cpufreq
>>> driver.
>>>
>>> Thomas Abraham (6):
>>>   clk: samsung: add infrastructure to register cpu clocks
>>>   clk: samsung: register exynos5420 apll/kpll configuration data
>>>   clk: exynos: use cpu-clock provider type to represent arm clock
>>>   ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data
>>>   ARM: Exynos: switch to using generic cpufreq driver for exynos4210/5250
>>>   cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
>>
>> In this series, support for Exynos5420 has been included. If there are
>> any more changes required, could you please let me know.
> 
> This patch series migrates exynos cpufreq support to use generic
> cpufreq drivers. For this, cpu clock blocks are encapsulated into a
> cpu clock type and cpufreq driver operates the cpu clock type.
> 
> We had discussed in the [1] about using coordinated clocks. This
> series is not using the concept of coordinated clocks but the code in
> this series can be migrated to use coordinated clocks when it is
> available.
> 
> Is it okay to consider this series for v3.17-rc1. I will update this
> code to use coordinated clocks when it is available. This series helps
> with cpufreq support for newer Exynos SoCs such as Exynos5420/3250.
> 
> [1] http://www.spinics.net/lists/cpufreq/msg10042.html
> 

I tested this patchset with Exynos3250 cpufreq patchset[1] on Exynos3250 SoC.
 [1] https://lkml.org/lkml/2014/6/18/126

Tested-by: Chanwoo Choi 

Best Regards,
Chanwoo Choi

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Re: [PATCHv2] ARM: dts: Add I2S dt node for Exynos3250

[Chanwoo Choi]

On 07/09/2014 12:00 PM, Chanwoo Choi wrote:
> From: Tomasz Figa 
> 
> This patch add I2S (Inter-IC Sound) dt node which supports 1-port stereo
> (1 channels) IIS-bus for audio interface with DMA-based operation.
> 
> Signed-off-by: Tomasz Figa 
> Signed-off-by: Inha Song 
> Tested-by: Inha Song 
> Signed-off-by: Chanwoo Choi 
> Acked-by: Kyungmin Park 
> ---
> Changes from v1:
> - Fix wrong name of property (pinctrl-names)
> - Change phanle name (i2s->i2s2)
> 
>  arch/arm/boot/dts/exynos3250.dtsi | 13 +
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi 
> b/arch/arm/boot/dts/exynos3250.dtsi
> index 3e678fa..77a06df 100644
> --- a/arch/arm/boot/dts/exynos3250.dtsi
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -425,6 +425,19 @@
>   status = "disabled";
>   };
>  
> + i2s2: i2s@1397 {
> + compatible = "samsung,s3c6410-i2s";
> + reg = <0x1397 0x100>;
> + interrupts = <0 126 0>;
> + clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
> + clock-names = "iis", "i2s_opclk0";
> + dmas = <&pdma0 14>, <&pdma0 13>;
> + dma-names = "tx", "rx";
> + pinctrl-0 = <&i2s2_bus>;
> + pinctrl-names = "default";
> + status = "disabled";
> + };
> +
>   pwm: pwm@139D {
>   compatible = "samsung,exynos4210-pwm";
>   reg = <0x139D 0x1000>;
> 

Ping.

Best Regards,
Chanwoo Choi


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[RESEND PATCH] thermal: samsung: Add TMU support for Exynos3250 SoC

[Chanwoo Choi]

This patch adds the registers, bit fields and compatible strings
required to support for the 1 TMU channels on Exynos3250.

Signed-off-by: Chanwoo Choi 
[Add MUX address setting bits by Jonghwa Lee]
Signed-off-by: Jonghwa Lee 
Acked-by: Kyungmin Park 
Reviewed-by: Amit Daniel Kachhap
---
 .../devicetree/bindings/thermal/exynos-thermal.txt |  1 +
 drivers/thermal/samsung/exynos_tmu.c   |  7 +-
 drivers/thermal/samsung/exynos_tmu.h   |  3 +-
 drivers/thermal/samsung/exynos_tmu_data.c  | 89 ++
 drivers/thermal/samsung/exynos_tmu_data.h  |  7 ++
 5 files changed, 105 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt 
b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index c949092..ae738f5 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -3,6 +3,7 @@
 ** Required properties:
 
 - compatible : One of the following:
+  "samsung,exynos3250-tmu"
   "samsung,exynos4412-tmu"
   "samsung,exynos4210-tmu"
   "samsung,exynos5250-tmu"
diff --git a/drivers/thermal/samsung/exynos_tmu.c 
b/drivers/thermal/samsung/exynos_tmu.c
index d7ca9f4..a2a08ea 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -505,6 +505,10 @@ static irqreturn_t exynos_tmu_irq(int irq, void *id)
 
 static const struct of_device_id exynos_tmu_match[] = {
{
+   .compatible = "samsung,exynos3250-tmu",
+   .data = (void *)EXYNOS3250_TMU_DRV_DATA,
+   },
+   {
.compatible = "samsung,exynos4210-tmu",
.data = (void *)EXYNOS4210_TMU_DRV_DATA,
},
@@ -677,7 +681,8 @@ static int exynos_tmu_probe(struct platform_device *pdev)
goto err_clk_sec;
}
 
-   if (pdata->type == SOC_ARCH_EXYNOS4210 ||
+   if (pdata->type == SOC_ARCH_EXYNOS3250 ||
+   pdata->type == SOC_ARCH_EXYNOS4210 ||
pdata->type == SOC_ARCH_EXYNOS4412 ||
pdata->type == SOC_ARCH_EXYNOS5250 ||
pdata->type == SOC_ARCH_EXYNOS5260 ||
diff --git a/drivers/thermal/samsung/exynos_tmu.h 
b/drivers/thermal/samsung/exynos_tmu.h
index edd08cf..1b4a644 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -40,7 +40,8 @@ enum calibration_mode {
 };
 
 enum soc_type {
-   SOC_ARCH_EXYNOS4210 = 1,
+   SOC_ARCH_EXYNOS3250 = 1,
+   SOC_ARCH_EXYNOS4210,
SOC_ARCH_EXYNOS4412,
SOC_ARCH_EXYNOS5250,
SOC_ARCH_EXYNOS5260,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c 
b/drivers/thermal/samsung/exynos_tmu_data.c
index c1d81dc..aa8e0de 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -90,6 +90,95 @@ struct exynos_tmu_init_data const 
exynos4210_default_tmu_data = {
 };
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS3250)
+static const struct exynos_tmu_registers exynos3250_tmu_registers = {
+   .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+   .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+   .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+   .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+   .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
+   .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+   .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+   .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+   .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+   .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+   .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+   .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+   .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+   .tmu_status = EXYNOS_TMU_REG_STATUS,
+   .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+   .threshold_th0 = EXYNOS_THD_TEMP_RISE,
+   .threshold_th1 = EXYNOS_THD_TEMP_FALL,
+   .tmu_inten = EXYNOS_TMU_REG_INTEN,
+   .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+   .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+   .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+   .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+   .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+   .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+   .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
+   .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+   .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+   .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+   .emul_con = EXYNOS_EMUL_CON,
+   .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+   .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+   .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define EXYNOS3250_TMU_DATA \
+   .threshold_falling = 10, \
+   .trigger_levels[0] = 70, \
+   .trigger_levels[1] = 95, \
+   .trigger_

Re: [PATCH] ARM: config: update multi_v7_defconfig

[Javier Martinez Canillas]

Hello Russell,

On Fri, Jul 18, 2014 at 12:44 AM, Russell King - ARM Linux
 wrote:
> On Fri, Jul 18, 2014 at 12:31:48AM +0200, Javier Martinez Canillas wrote:
>> In the case of the MAX77686, the mfd, regulator and clock drivers use
>> subsys_initcall() instead of module_init() but I wonder which of these
>> really need to be initialized at subsys init call time and which one
>> can just be built as a module.
>
> I think you're making a frequently made mistake concerning module
> initialisation.
>
> Having code initialised by subsys_initcall() (or indeed any other level)
> does not preclude it being a module:
>
> #ifndef MODULE
> ...
> #define subsys_initcall(fn) __define_initcall(fn, 4)
> ...
> #else /* MODULE */
> ...
> #define subsys_initcall(fn) module_init(fn)
> ...
> #endif
>
> So, subsys_initcall() automagically becomes module_init() when built
> as a module.  There's no need to change anything here.
>

I was indeed confused, I should had looked at include/linux/init.h
before. Thanks a lot for the clarification.

Best regards,
Javier
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Re: [PATCH V5 05/12] Documentation: Add DT bindings for panel-lvds driver

[Thierry Reding]

On Fri, Jul 18, 2014 at 02:20:39AM +0530, Ajay kumar wrote:
> +devicet...@vger.kernel.org
> 
> On Fri, Jul 18, 2014 at 2:13 AM, Ajay Kumar  wrote:
> > Add DT binding documentation for panel-lvds driver.
> >
> > Signed-off-by: Ajay Kumar 
> > ---
> >  .../devicetree/bindings/panel/panel-lvds.txt   |   50 
> > 
> >  1 file changed, 50 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/panel/panel-lvds.txt
> >
> > diff --git a/Documentation/devicetree/bindings/panel/panel-lvds.txt 
> > b/Documentation/devicetree/bindings/panel/panel-lvds.txt
> > new file mode 100644
> > index 000..fdf91da2
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/panel/panel-lvds.txt
> > @@ -0,0 +1,50 @@
> > +panel interface for eDP/lvds panels
> > +
> > +Required properties:
> > +  - compatible: "panel-lvds"

I think I've said this before. I oppose the addition of this binding. We
need to list a device-specific compatible value here, wildcards like
this aren't a good choice. And then if we have that compatible value we
can move most of the optional properties below into a driver.

> > +Optional properties:

If all these properties are optional, then what happens if a device tree
node doesn't contain any of them? Doesn't that turn the driver into one
big no-op?

> > +   -lcd-enable-gpios:
> > +   panel LCD poweron GPIO.
> > +   Indicates which GPIO needs to be powered up as 
> > output
> > +   to powerup/enable the switch to the LCD panel.
> > +   -backlight-enable-gpios:
> > +   panel LED enable GPIO.
> > +   Indicates which GPIO needs to be powered up as 
> > output
> > +   to enable the backlight.

I've also said before that this really belongs in a backlight driver.
Chances are that you'll want to have a way to set the brightness of the
backlight as well, so simply an enable GPIO won't be good enough.

> > +   -panel-prepare-delay:
> > +   delay value in ms required for panel_prepare process
> > +   Delay in ms needed for the panel LCD unit to
> > +   powerup completely.
> > +   ex: delay needed till eDP panel throws HPD.
> > +   delay needed so that we cans tart reading edid.

If the panel signals HPD then we don't need this delay at all and we
should just wait for HPD instead.

> > +   -panel-enable-delay:
> > +   delay value in ms required for panel_enable process
> > +   Delay in ms needed for the panel backlight/LED unit
> > +   to powerup, and delay needed between video_enable 
> > and
> > +   backlight_enable.
> > +   -panel-disable-delay:
> > +   delay value in ms required for panel_disable process
> > +   Delay in ms needed for the panel backlight/LED unit
> > +   powerdown, and delay needed between 
> > backlight_disable
> > +   and video_disable.
> > +   -panel-unprepare-delay:
> > +   delay value in ms required for panel_post_disable process
> > +   Delay in ms needed for the panel LCD unit to
> > +   to powerdown completely, and the minimum delay 
> > needed
> > +   before powering it on again.

These delays are all panel specific and they don't vary per board, so
they shouldn't go into the device tree at all.

> > +   -panel-width-mm: physical panel width [mm]
> > +   -panel-height-mm: physical panel height [mm]

Same here.

Thierry


pgpACqAvTWT3G.pgp
Description: PGP signature

Re: [PATCH] ARM: config: update multi_v7_defconfig

[Russell King - ARM Linux]

On Fri, Jul 18, 2014 at 12:31:48AM +0200, Javier Martinez Canillas wrote:
> In the case of the MAX77686, the mfd, regulator and clock drivers use
> subsys_initcall() instead of module_init() but I wonder which of these
> really need to be initialized at subsys init call time and which one
> can just be built as a module.

I think you're making a frequently made mistake concerning module
initialisation.

Having code initialised by subsys_initcall() (or indeed any other level)
does not preclude it being a module:

#ifndef MODULE
...
#define subsys_initcall(fn) __define_initcall(fn, 4)
...
#else /* MODULE */
...
#define subsys_initcall(fn) module_init(fn)
...
#endif

So, subsys_initcall() automagically becomes module_init() when built
as a module.  There's no need to change anything here.

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Re: [PATCH v3] ARM: dts: Add cros_ec to exynos5420-peach-pit and exynos5800-peach-pi

[Javier Martinez Canillas]

Hello Kukjin,

On 06/24/2014 06:28 PM, Doug Anderson wrote:
> This adds cros_ec to exynos5420-peach-pit and exynos5800-peach-pi,
> including:
> * The keyboard
> * The i2c tunnel
> * The tps65090 under the i2c tunnel
> * The battery under the i2c tunnel
> 
> To add extra motivation, it should be noted that tps65090 is one of
> the things needed to get display-related FETs turned on for pit and
> pi.
> 
> Note that this relies on a few outstanding changes:
> * Needs (spi: s3c64xx: fix broken "cs_gpios" usage in the driver) and
>   (spi: s3c64xx: for DT platofrms always get the chipselect info from
>   DT node) to work properly and match the documented bindings.  See
>    and
>   
> 
> Signed-off-by: Doug Anderson 
> Tested-by: Javier Martinez Canillas 
> Tested-by: Tushar Behera 
> 

Mark Brown as already applied the SPI DT binding fix from Naveen [0] which was
the dependency for this patch and he said that will try to send the whole series
to Torvalds before the 3.16-rc cycle ends.

So I think that it's safe now if you want to pick this patch.

Thanks a lot!

Best regards,
Javier

[0]:
https://git.kernel.org/cgit/linux/kernel/git/broonie/spi.git/commit/?h=for-next&id=306972cedfdedc662dd8e32a6397d0e29f2ac90e
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Re: [PATCH] ARM: config: update multi_v7_defconfig

[Javier Martinez Canillas]

Hello,

On Tue, Jul 15, 2014 at 5:59 PM, Doug Anderson  wrote:
>
> Is there a reason not to add more of the max77686 configs?
>
> +CONFIG_RTC_DRV_MAX77686=y
> +CONFIG_COMMON_CLK_MAX77686=y

AFAIK for the multi-platform defconfig we should try to build as a
module as many config options as possible to keep the kernel binary
size to a minimum.

In the case of the MAX77686, the mfd, regulator and clock drivers use
subsys_initcall() instead of module_init() but I wonder which of these
really need to be initialized at subsys init call time and which one
can just be built as a module. The only MAX77686 driver that uses
module_platform_driver() so it's initialized at device initcall time
is the rtc-max77686 driver which ironically is the only MAX77686
driver that doesn't define a MODULE_DEVICE_TABLE() so the module won't
be autoloaded.

Best regards,
Javier
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Re: [PATCH 1/1] ARM: exynos_defconfig: Update exynos_defconfig

[Javier Martinez Canillas]

Hello,

On 07/14/2014 09:24 PM, Doug Anderson wrote:
> 
>> [WARN] [2.296011] tps65090-charger tps65090-charger: Unable to get
>> charger irq = -22
>> [WARN] [2.313705] tps65090-charger: probe of tps65090-charger
>> failed with error -22
> 
> I have resent the patch to fix this 4 times with no avail.  I'm
> getting a little tired of reposting.  I figure that I'll wait another
> month and try again--maybe the charger subsystem will be in better
> hands by then.

FYI, Sebastian Reichel has applied [0] Doug's patch.

Best regards,
Javier

[0]:
https://git.kernel.org/cgit/linux/kernel/git/sre/linux-power-supply.git/commit/?h=dev&id=5a3effdc8877132fd12f97fea0d4756614b911c7
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Re: [PATCH V5 11/12] Documentation: Add DT bindings for ps8622/ps8625 bridge driver

[Ajay kumar]

+devicet...@vger.kernel.org

On Fri, Jul 18, 2014 at 2:13 AM, Ajay Kumar  wrote:
> From: Vincent Palatin 
>
> Add DT binding documentation for ps8622/ps8625 bridge driver.
>
> Signed-off-by: Vincent Palatin 
> Signed-off-by: Ajay Kumar 
> ---
>  .../devicetree/bindings/drm/bridge/ps8622.txt  |   21 
> 
>  1 file changed, 21 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/drm/bridge/ps8622.txt
>
> diff --git a/Documentation/devicetree/bindings/drm/bridge/ps8622.txt 
> b/Documentation/devicetree/bindings/drm/bridge/ps8622.txt
> new file mode 100644
> index 000..1d154ac
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/drm/bridge/ps8622.txt
> @@ -0,0 +1,21 @@
> +ps8622-bridge bindings
> +
> +Required properties:
> +   - compatible: "parade,ps8622" or "parade,ps8625"
> +   - reg: first i2c address of the bridge
> +   - sleep-gpios: OF device-tree gpio specification
> +   - reset-gpios: OF device-tree gpio specification
> +
> +Optional properties:
> +   - lane-count: number of DP lanes to use
> +   - use-external-pwm: backlight will be controlled by an external PWM
> +
> +Example:
> +   ps8622-bridge@48 {
> +   compatible = "parade,ps8622";
> +   reg = <0x48>;
> +   sleep-gpios = <&gpc3 6 1 0 0>;
> +   reset-gpios = <&gpc3 1 1 0 0>;
> +   display-timings = <&lcd_display_timings>;
> +   lane-count = <1>
> +   };
> --
> 1.7.9.5
>
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Re: [PATCH V5 05/12] Documentation: Add DT bindings for panel-lvds driver

[Ajay kumar]

+devicet...@vger.kernel.org

On Fri, Jul 18, 2014 at 2:13 AM, Ajay Kumar  wrote:
> Add DT binding documentation for panel-lvds driver.
>
> Signed-off-by: Ajay Kumar 
> ---
>  .../devicetree/bindings/panel/panel-lvds.txt   |   50 
> 
>  1 file changed, 50 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/panel/panel-lvds.txt
>
> diff --git a/Documentation/devicetree/bindings/panel/panel-lvds.txt 
> b/Documentation/devicetree/bindings/panel/panel-lvds.txt
> new file mode 100644
> index 000..fdf91da2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/panel/panel-lvds.txt
> @@ -0,0 +1,50 @@
> +panel interface for eDP/lvds panels
> +
> +Required properties:
> +  - compatible: "panel-lvds"
> +
> +Optional properties:
> +   -lcd-enable-gpios:
> +   panel LCD poweron GPIO.
> +   Indicates which GPIO needs to be powered up as output
> +   to powerup/enable the switch to the LCD panel.
> +   -backlight-enable-gpios:
> +   panel LED enable GPIO.
> +   Indicates which GPIO needs to be powered up as output
> +   to enable the backlight.
> +   -panel-prepare-delay:
> +   delay value in ms required for panel_prepare process
> +   Delay in ms needed for the panel LCD unit to
> +   powerup completely.
> +   ex: delay needed till eDP panel throws HPD.
> +   delay needed so that we cans tart reading edid.
> +   -panel-enable-delay:
> +   delay value in ms required for panel_enable process
> +   Delay in ms needed for the panel backlight/LED unit
> +   to powerup, and delay needed between video_enable and
> +   backlight_enable.
> +   -panel-disable-delay:
> +   delay value in ms required for panel_disable process
> +   Delay in ms needed for the panel backlight/LED unit
> +   powerdown, and delay needed between backlight_disable
> +   and video_disable.
> +   -panel-unprepare-delay:
> +   delay value in ms required for panel_post_disable process
> +   Delay in ms needed for the panel LCD unit to
> +   to powerdown completely, and the minimum delay needed
> +   before powering it on again.
> +   -panel-width-mm: physical panel width [mm]
> +   -panel-height-mm: physical panel height [mm]
> +
> +Example:
> +
> +   panel-lvds {
> +   compatible = "panel-lvds";
> +   backlight-enable-gpios = <&gpx3 0 0>;
> +   panel-prepare-delay = <40>;
> +   panel-enable-delay = <20>;
> +   panel-disable-delay = <20>;
> +   panel-unprepare-delay = <30>;
> +   panel-width-mm = <256>;
> +   panel-height-mm = <144>;
> +   };
> --
> 1.7.9.5
>
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[PATCH V5 10/12] drm/bridge: Add ps8622/ps8625 bridge driver

[Ajay Kumar]

From: Vincent Palatin 

This patch adds drm_bridge driver for parade DisplayPort
to LVDS bridge chip.

Signed-off-by: Vincent Palatin 
Signed-off-by: Andrew Bresticker 
Signed-off-by: Sean Paul 
Signed-off-by: Rahul Sharma 
Signed-off-by: Ajay Kumar 
---
 drivers/gpu/drm/bridge/Kconfig  |8 +
 drivers/gpu/drm/bridge/Makefile |1 +
 drivers/gpu/drm/bridge/ps8622.c |  476 +++
 include/drm/bridge/ps8622.h |   41 
 4 files changed, 526 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/ps8622.c
 create mode 100644 include/drm/bridge/ps8622.h

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index e3fb487..7b843c8 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -10,3 +10,11 @@ config DRM_PANEL_BINDER
select DRM_KMS_HELPER
select DRM_PANEL
---help---
+
+config DRM_PS8622
+   tristate "Parade eDP/LVDS bridge"
+   depends on DRM
+   select DRM_KMS_HELPER
+   select BACKLIGHT_LCD_SUPPORT
+   select BACKLIGHT_CLASS_DEVICE
+   ---help---
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index ba8b5b8..b494d4b 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -2,3 +2,4 @@ ccflags-y := -Iinclude/drm
 
 obj-$(CONFIG_DRM_PTN3460) += ptn3460.o
 obj-$(CONFIG_DRM_PANEL_BINDER) += panel_binder.o
+obj-$(CONFIG_DRM_PS8622) += ps8622.o
diff --git a/drivers/gpu/drm/bridge/ps8622.c b/drivers/gpu/drm/bridge/ps8622.c
new file mode 100644
index 000..b5b7c31
--- /dev/null
+++ b/drivers/gpu/drm/bridge/ps8622.c
@@ -0,0 +1,476 @@
+/*
+ * Parade PS8622 eDP/LVDS bridge driver
+ *
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "drmP.h"
+#include "drm_crtc.h"
+#include "drm_crtc_helper.h"
+
+struct ps8622_bridge {
+   struct drm_bridge *bridge;
+   struct drm_encoder *encoder;
+   struct i2c_client *client;
+   struct regulator *v12;
+   struct backlight_device *bl;
+   struct mutex enable_mutex;
+
+   struct gpio_desc *gpio_slp_n;
+   struct gpio_desc *gpio_rst_n;
+
+   u8 max_lane_count;
+   u8 lane_count;
+
+   bool enabled;
+};
+
+struct ps8622_device_data {
+   u8 max_lane_count;
+};
+
+static const struct ps8622_device_data ps8622_data = {
+   .max_lane_count = 1,
+};
+
+static const struct ps8622_device_data ps8625_data = {
+   .max_lane_count = 2,
+};
+
+/* Brightness scale on the Parade chip */
+#define PS8622_MAX_BRIGHTNESS 0xff
+
+/* Timings taken from the version 1.7 datasheet for the PS8622/PS8625 */
+#define PS8622_POWER_RISE_T1_MIN_US 10
+#define PS8622_POWER_RISE_T1_MAX_US 1
+#define PS8622_RST_HIGH_T2_MIN_US 3000
+#define PS8622_RST_HIGH_T2_MAX_US 3
+#define PS8622_PWMO_END_T12_MS 200
+#define PS8622_POWER_FALL_T16_MAX_US 1
+#define PS8622_POWER_OFF_T17_MS 500
+
+#if ((PS8622_RST_HIGH_T2_MIN_US + PS8622_POWER_RISE_T1_MAX_US) > \
+   (PS8622_RST_HIGH_T2_MAX_US + PS8622_POWER_RISE_T1_MIN_US))
+#error "T2.min + T1.max must be less than T2.max + T1.min"
+#endif
+
+static int ps8622_set(struct i2c_client *client, u8 page, u8 reg, u8 val)
+{
+   int ret;
+   struct i2c_adapter *adap = client->adapter;
+   struct i2c_msg msg;
+   u8 data[] = {reg, val};
+
+   msg.addr = client->addr + page;
+   msg.flags = 0;
+   msg.len = sizeof(data);
+   msg.buf = data;
+
+   ret = i2c_transfer(adap, &msg, 1);
+   if (ret != 1)
+   pr_warn("PS8622 I2C write (0x%02x,0x%02x,0x%02x) failed: %d\n",
+   client->addr + page, reg, val, ret);
+   return !(ret == 1);
+}
+
+static int ps8622_send_config(struct ps8622_bridge *ps_bridge)
+{
+   struct i2c_client *cl = ps_bridge->client;
+   int err = 0;
+
+   /* wait 20ms after power ON */
+   usleep_range(2, 3);
+
+   err |= ps8622_set(cl, 0x02, 0xa1, 0x01); /* HPD low */
+   /* SW setting */
+   err |= ps8622_set(cl, 0x04, 0x14, 0x01); /* [1:0] SW output 1.2V voltage
+ * is lower to 96% */
+   /* RCO SS setting */
+   err |= ps8622_set(cl, 0x04, 0xe3, 0x20); /* [5:4] = b01 0.5%, b10 1%,
+ * b11 1.5% */
+   err |= ps8622_set(cl, 0x04, 0xe2, 0x80); /* [7] RCO SS enable */
+   /* RPHY Setting */
+   

[RESEND PATCH V5 09/12] drm/exynos: dp: create bridge chain using ptn3460 and panel_binder

[Ajay Kumar]

exynos_dp supports a simple bridge chain with ptn3460 bridge
and an LVDS panel attached to it.
This patch creates the bridge chain with ptn3460 as the head
of the list and panel_binder being the tail.

Signed-off-by: Ajay Kumar 
---
 drivers/gpu/drm/exynos/exynos_dp_core.c |   12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c 
b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 9d31296..0ca6256 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "exynos_drm_drv.h"
 #include "exynos_dp_core.h"
@@ -992,7 +993,7 @@ static int exynos_drm_attach_lcd_bridge(struct 
exynos_dp_device *dp,
struct drm_encoder *encoder)
 {
struct bridge_init bridge;
-   struct drm_bridge *bridge_chain = NULL;
+   struct drm_bridge *bridge_chain = NULL, *next = NULL;
bool connector_created = false;
 
if (find_bridge("nxp,ptn3460", &bridge)) {
@@ -1000,6 +1001,15 @@ static int exynos_drm_attach_lcd_bridge(struct 
exynos_dp_device *dp,
bridge.node);
}
 
+   if (bridge_chain && dp->edp_panel) {
+   next = panel_binder_init(dp->drm_dev, encoder, bridge.client,
+   bridge.node, dp->edp_panel, DRM_MODE_CONNECTOR_LVDS,
+   DRM_CONNECTOR_POLL_HPD);
+   if (next)
+   connector_created = true;
+   drm_bridge_add_to_chain(bridge_chain, next);
+   }
+
return connector_created;
 }
 
-- 
1.7.9.5

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[RESEND PATCH V5 12/12] drm/exynos: Add ps8622 lvds bridge discovery to DP driver

[Ajay Kumar]

From: Rahul Sharma 

This patch adds ps8622 lvds bridge discovery code to the dp driver.

Signed-off-by: Rahul Sharma 
Signed-off-by: Ajay Kumar 
---
 drivers/gpu/drm/exynos/exynos_dp_core.c |5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c 
b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 0ca6256..82e2942 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -31,6 +31,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "exynos_drm_drv.h"
 #include "exynos_dp_core.h"
@@ -999,6 +1000,10 @@ static int exynos_drm_attach_lcd_bridge(struct 
exynos_dp_device *dp,
if (find_bridge("nxp,ptn3460", &bridge)) {
bridge_chain = ptn3460_init(dp->drm_dev, encoder, bridge.client,
bridge.node);
+   } else if (find_bridge("parade,ps8622", &bridge) ||
+   find_bridge("parade,ps8625", &bridge)) {
+   bridge_chain = ps8622_init(dp->drm_dev, encoder, bridge.client,
+   bridge.node);
}
 
if (bridge_chain && dp->edp_panel) {
-- 
1.7.9.5

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[PATCH V5 11/12] Documentation: Add DT bindings for ps8622/ps8625 bridge driver

[Ajay Kumar]

From: Vincent Palatin 

Add DT binding documentation for ps8622/ps8625 bridge driver.

Signed-off-by: Vincent Palatin 
Signed-off-by: Ajay Kumar 
---
 .../devicetree/bindings/drm/bridge/ps8622.txt  |   21 
 1 file changed, 21 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/ps8622.txt

diff --git a/Documentation/devicetree/bindings/drm/bridge/ps8622.txt 
b/Documentation/devicetree/bindings/drm/bridge/ps8622.txt
new file mode 100644
index 000..1d154ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/ps8622.txt
@@ -0,0 +1,21 @@
+ps8622-bridge bindings
+
+Required properties:
+   - compatible: "parade,ps8622" or "parade,ps8625"
+   - reg: first i2c address of the bridge
+   - sleep-gpios: OF device-tree gpio specification
+   - reset-gpios: OF device-tree gpio specification
+
+Optional properties:
+   - lane-count: number of DP lanes to use
+   - use-external-pwm: backlight will be controlled by an external PWM
+
+Example:
+   ps8622-bridge@48 {
+   compatible = "parade,ps8622";
+   reg = <0x48>;
+   sleep-gpios = <&gpc3 6 1 0 0>;
+   reset-gpios = <&gpc3 1 1 0 0>;
+   display-timings = <&lcd_display_timings>;
+   lane-count = <1>
+   };
-- 
1.7.9.5

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[RESEND PATCH V5 08/12] drm/bridge: ptn3460: Support bridge chaining

[Ajay Kumar]

Modify the driver to invoke callbacks for the next bridge
in the bridge chain.
Also, remove the drm_connector implementation from ptn3460,
since the same is implemented using panel_binder.

Signed-off-by: Ajay Kumar 
---
 drivers/gpu/drm/bridge/ptn3460.c|  137 +--
 drivers/gpu/drm/exynos/exynos_dp_core.c |   16 ++--
 include/drm/bridge/ptn3460.h|   15 ++--
 3 files changed, 39 insertions(+), 129 deletions(-)

diff --git a/drivers/gpu/drm/bridge/ptn3460.c b/drivers/gpu/drm/bridge/ptn3460.c
index d466696..5fe16c6 100644
--- a/drivers/gpu/drm/bridge/ptn3460.c
+++ b/drivers/gpu/drm/bridge/ptn3460.c
@@ -34,37 +34,15 @@
 #define PTN3460_EDID_SRAM_LOAD_ADDR0x85
 
 struct ptn3460_bridge {
-   struct drm_connector connector;
struct i2c_client *client;
struct drm_encoder *encoder;
struct drm_bridge *bridge;
-   struct edid *edid;
int gpio_pd_n;
int gpio_rst_n;
u32 edid_emulation;
bool enabled;
 };
 
-static int ptn3460_read_bytes(struct ptn3460_bridge *ptn_bridge, char addr,
-   u8 *buf, int len)
-{
-   int ret;
-
-   ret = i2c_master_send(ptn_bridge->client, &addr, 1);
-   if (ret <= 0) {
-   DRM_ERROR("Failed to send i2c command, ret=%d\n", ret);
-   return ret;
-   }
-
-   ret = i2c_master_recv(ptn_bridge->client, buf, len);
-   if (ret <= 0) {
-   DRM_ERROR("Failed to recv i2c data, ret=%d\n", ret);
-   return ret;
-   }
-
-   return 0;
-}
-
 static int ptn3460_write_byte(struct ptn3460_bridge *ptn_bridge, char addr,
char val)
 {
@@ -126,6 +104,8 @@ static void ptn3460_pre_enable(struct drm_bridge *bridge)
gpio_set_value(ptn_bridge->gpio_rst_n, 1);
}
 
+   drm_next_bridge_pre_enable(bridge);
+
/*
 * There's a bug in the PTN chip where it falsely asserts hotplug before
 * it is fully functional. We're forced to wait for the maximum start up
@@ -142,6 +122,7 @@ static void ptn3460_pre_enable(struct drm_bridge *bridge)
 
 static void ptn3460_enable(struct drm_bridge *bridge)
 {
+   drm_next_bridge_enable(bridge);
 }
 
 static void ptn3460_disable(struct drm_bridge *bridge)
@@ -153,6 +134,8 @@ static void ptn3460_disable(struct drm_bridge *bridge)
 
ptn_bridge->enabled = false;
 
+   drm_next_bridge_disable(bridge);
+
if (gpio_is_valid(ptn_bridge->gpio_rst_n))
gpio_set_value(ptn_bridge->gpio_rst_n, 1);
 
@@ -162,6 +145,7 @@ static void ptn3460_disable(struct drm_bridge *bridge)
 
 static void ptn3460_post_disable(struct drm_bridge *bridge)
 {
+   drm_next_bridge_post_disable(bridge);
 }
 
 void ptn3460_bridge_destroy(struct drm_bridge *bridge)
@@ -173,6 +157,9 @@ void ptn3460_bridge_destroy(struct drm_bridge *bridge)
gpio_free(ptn_bridge->gpio_pd_n);
if (gpio_is_valid(ptn_bridge->gpio_rst_n))
gpio_free(ptn_bridge->gpio_rst_n);
+
+   drm_next_bridge_destroy(bridge);
+
/* Nothing else to free, we've got devm allocated memory */
 }
 
@@ -184,81 +171,10 @@ struct drm_bridge_funcs ptn3460_bridge_funcs = {
.destroy = ptn3460_bridge_destroy,
 };
 
-int ptn3460_get_modes(struct drm_connector *connector)
-{
-   struct ptn3460_bridge *ptn_bridge;
-   u8 *edid;
-   int ret, num_modes;
-   bool power_off;
-
-   ptn_bridge = container_of(connector, struct ptn3460_bridge, connector);
-
-   if (ptn_bridge->edid)
-   return drm_add_edid_modes(connector, ptn_bridge->edid);
-
-   power_off = !ptn_bridge->enabled;
-   ptn3460_pre_enable(ptn_bridge->bridge);
-
-   edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
-   if (!edid) {
-   DRM_ERROR("Failed to allocate edid\n");
-   return 0;
-   }
-
-   ret = ptn3460_read_bytes(ptn_bridge, PTN3460_EDID_ADDR, edid,
-   EDID_LENGTH);
-   if (ret) {
-   kfree(edid);
-   num_modes = 0;
-   goto out;
-   }
-
-   ptn_bridge->edid = (struct edid *)edid;
-   drm_mode_connector_update_edid_property(connector, ptn_bridge->edid);
-
-   num_modes = drm_add_edid_modes(connector, ptn_bridge->edid);
-
-out:
-   if (power_off)
-   ptn3460_disable(ptn_bridge->bridge);
-
-   return num_modes;
-}
-
-struct drm_encoder *ptn3460_best_encoder(struct drm_connector *connector)
-{
-   struct ptn3460_bridge *ptn_bridge;
-
-   ptn_bridge = container_of(connector, struct ptn3460_bridge, connector);
-
-   return ptn_bridge->encoder;
-}
-
-struct drm_connector_helper_funcs ptn3460_connector_helper_funcs = {
-   .get_modes = ptn3460_get_modes,
-   .best_encoder = ptn3460_best_encoder,
-};
-
-enum drm_connector_status ptn3460_detect(struct drm_connector *connector,
-   bool force)
-{
-   return connector_status_connected;
-}
-
-void ptn34

[PATCH V5 07/12] drm/bridge: Add a driver which binds drm_bridge with drm_panel

[Ajay Kumar]

Add a dummy bridge which binds all of the drm_bridge callbacks
to corresponding drm_panel callbacks.

In theory, this is just a glue layer for the last bridge and
the panel attached to it.

This driver also implements the required drm_connector ops
for the encoder(on which the entire bridge chain is hanging off).

Signed-off-by: Ajay Kumar 
---
 drivers/gpu/drm/bridge/Kconfig|7 ++
 drivers/gpu/drm/bridge/Makefile   |1 +
 drivers/gpu/drm/bridge/panel_binder.c |  193 +
 include/drm/bridge/panel_binder.h |   44 
 4 files changed, 245 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/panel_binder.c
 create mode 100644 include/drm/bridge/panel_binder.h

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 884923f..e3fb487 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -3,3 +3,10 @@ config DRM_PTN3460
depends on DRM
select DRM_KMS_HELPER
---help---
+
+config DRM_PANEL_BINDER
+   tristate "bridge panel binder"
+   depends on DRM
+   select DRM_KMS_HELPER
+   select DRM_PANEL
+   ---help---
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index b4733e1..ba8b5b8 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,3 +1,4 @@
 ccflags-y := -Iinclude/drm
 
 obj-$(CONFIG_DRM_PTN3460) += ptn3460.o
+obj-$(CONFIG_DRM_PANEL_BINDER) += panel_binder.o
diff --git a/drivers/gpu/drm/bridge/panel_binder.c 
b/drivers/gpu/drm/bridge/panel_binder.c
new file mode 100644
index 000..6160ed5
--- /dev/null
+++ b/drivers/gpu/drm/bridge/panel_binder.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+
+#include 
+
+#include "drmP.h"
+#include "drm_crtc.h"
+#include "drm_crtc_helper.h"
+
+#include "bridge/panel_binder.h"
+
+struct panel_binder {
+   struct drm_connectorconnector;
+   struct i2c_client   *client;
+   struct drm_encoder  *encoder;
+   struct drm_bridge   *bridge;
+   struct drm_panel*panel;
+};
+
+static void panel_binder_pre_enable(struct drm_bridge *bridge)
+{
+   struct panel_binder *panel_binder = bridge->driver_private;
+
+   drm_panel_prepare(panel_binder->panel);
+}
+
+static void panel_binder_enable(struct drm_bridge *bridge)
+{
+   struct panel_binder *panel_binder = bridge->driver_private;
+
+   drm_panel_enable(panel_binder->panel);
+}
+
+static void panel_binder_disable(struct drm_bridge *bridge)
+{
+   struct panel_binder *panel_binder = bridge->driver_private;
+
+   drm_panel_disable(panel_binder->panel);
+}
+
+static void panel_binder_post_disable(struct drm_bridge *bridge)
+{
+   struct panel_binder *panel_binder = bridge->driver_private;
+
+   drm_panel_unprepare(panel_binder->panel);
+}
+
+void panel_binder_destroy(struct drm_bridge *bridge)
+{
+   struct panel_binder *panel_binder = bridge->driver_private;
+
+   drm_panel_detach(panel_binder->panel);
+   drm_bridge_cleanup(bridge);
+}
+
+struct drm_bridge_funcs panel_binder_funcs = {
+   .pre_enable = panel_binder_pre_enable,
+   .enable = panel_binder_enable,
+   .disable = panel_binder_disable,
+   .post_disable = panel_binder_post_disable,
+   .destroy = panel_binder_destroy,
+};
+
+static int panel_binder_mode_valid(struct drm_connector *connector,
+struct drm_display_mode *mode)
+{
+   return MODE_OK;
+}
+
+static int panel_binder_get_modes(struct drm_connector *connector)
+{
+   struct panel_binder *panel_binder;
+
+   panel_binder = container_of(connector, struct panel_binder, connector);
+
+   return panel_binder->panel->funcs->get_modes(panel_binder->panel);
+}
+
+static struct drm_encoder *panel_binder_best_encoder(struct drm_connector
+   *connector)
+{
+   struct panel_binder *panel_binder;
+
+   panel_binder = container_of(connector, struct panel_binder, connector);
+
+   return panel_binder->encoder;
+}
+
+static const struct drm_connector_helper_funcs
+   panel_binder_connector_helper_funcs = {
+   .get_modes = panel_binder_get_modes,
+   .mode_valid = panel_binder_mode_valid,
+   .best_encoder = panel_binder_best_encoder,
+};
+
+static enum drm_connector_status panel_binder_detect(struct drm_connector
+

[PATCH V5 04/12] drm/panel: Add driver for lvds/edp based panels

[Ajay Kumar]

This patch adds a simple driver to handle all the LCD and LED
powerup/down routines needed to support eDP/LVDS panels.

The LCD and LED units are usually powered up via regulators,
and almost on all boards, we will have a BACKLIGHT_EN pin to
enable/ disable the backlight.
Sometimes, we can have LCD_EN switches as well.

The routines in this driver can be used to control
panel power sequence on such boards.

Signed-off-by: Ajay Kumar 
Signed-off-by: Rahul Sharma 
---
 drivers/gpu/drm/panel/Kconfig  |   10 ++
 drivers/gpu/drm/panel/Makefile |1 +
 drivers/gpu/drm/panel/panel-lvds.c |  268 
 3 files changed, 279 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-lvds.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 4ec874d..8fe7ee5 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -30,4 +30,14 @@ config DRM_PANEL_S6E8AA0
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS
 
+config DRM_PANEL_EDP_LVDS
+   tristate "support for eDP/LVDS panels"
+   depends on OF && DRM_PANEL
+   select VIDEOMODE_HELPERS
+   help
+ DRM panel driver for direct eDP panels or LVDS connected
+ via DP bridges, that need at most a regulator for LCD unit,
+ a regulator for LED unit and/or enable GPIOs for LCD or LED units.
+ Delay values can also be specified to support powerup and
+ powerdown process.
 endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 8b92921..eaafa01 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
 obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
+obj-$(CONFIG_DRM_PANEL_EDP_LVDS) += panel-lvds.o
diff --git a/drivers/gpu/drm/panel/panel-lvds.c 
b/drivers/gpu/drm/panel/panel-lvds.c
new file mode 100644
index 000..ce20587
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-lvds.c
@@ -0,0 +1,268 @@
+/*
+ * panel driver for lvds and eDP panels
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * Ajay Kumar 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+struct panel_lvds {
+   struct drm_panelbase;
+   struct regulator*backlight_fet;
+   struct regulator*lcd_fet;
+   struct gpio_desc*lcd_en_gpio;
+   struct gpio_desc*led_en_gpio;
+   struct videomodevm;
+   int width_mm;
+   int height_mm;
+   boolbacklight_fet_enabled;
+   boollcd_fet_enabled;
+   int panel_prepare_delay;
+   int panel_enable_delay;
+   int panel_disable_delay;
+   int panel_unprepare_delay;
+};
+
+static inline struct panel_lvds *to_panel(struct drm_panel *panel)
+{
+   return container_of(panel, struct panel_lvds, base);
+}
+
+static int panel_lvds_prepare(struct drm_panel *panel)
+{
+   struct panel_lvds *lvds_panel = to_panel(panel);
+
+   if (!lvds_panel->lcd_fet_enabled) {
+   if (regulator_enable(lvds_panel->lcd_fet)) {
+   DRM_ERROR("failed to enable LCD fet\n");
+   return -EAGAIN;
+   }
+   lvds_panel->lcd_fet_enabled = true;
+   }
+
+   if (lvds_panel->lcd_en_gpio)
+   gpiod_set_value(lvds_panel->lcd_en_gpio, 1);
+
+   msleep(lvds_panel->panel_prepare_delay);
+
+   return 0;
+}
+
+static int panel_lvds_enable(struct drm_panel *panel)
+{
+   struct panel_lvds *lvds_panel = to_panel(panel);
+
+   if (!lvds_panel->backlight_fet_enabled) {
+   if (regulator_enable(lvds_panel->backlight_fet)) {
+   DRM_ERROR("failed to enable LED fet\n");
+   return -EAGAIN;
+   }
+   lvds_panel->backlight_fet_enabled = true;
+   }
+
+   msleep(lvds_panel->panel_enable_delay);
+
+   if (lvds_panel->led_en_gpio)
+   gpiod_set_value(lvds_panel->led_en_gpio, 1);
+
+   return 0;
+}
+
+static int panel_lvds_disable(struct drm_panel *panel)
+{
+   struct panel_lvds *lvds_panel = to_panel(panel);
+
+   if (lvds_panel->led_en_gpio)
+   gpiod_set_value(lvds_panel->led_en_gpio, 0);
+
+   if (lvds_panel->backlight_fet_enabled) {
+   regulator_disable(lvds_panel->backlight_fet);
+   lvds_panel->backlight_fet_enabled = false;
+   }
+
+   msleep(lvds_panel->panel_disable_delay);
+
+   r

[RESEND PATCH V5 06/12] drm/bridge: add helper functions to support bridge chain

[Ajay Kumar]

Add helper functions to create bridge chain and to call the
corresponding next_bridge functions.

Signed-off-by: Ajay Kumar 
Suggested-by: Rob Clark 
---
 include/drm/drm_crtc.h |   72 
 1 file changed, 72 insertions(+)

diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index e529b68..0a6950a 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -652,6 +652,7 @@ struct drm_bridge_funcs {
 struct drm_bridge {
struct drm_device *dev;
struct list_head head;
+   struct drm_bridge *next_bridge;
 
struct drm_mode_object base;
 
@@ -1166,6 +1167,77 @@ drm_property_blob_find(struct drm_device *dev, uint32_t 
id)
return mo ? obj_to_blob(mo) : NULL;
 }
 
+static inline int drm_bridge_add_to_chain(struct drm_bridge *head,
+ struct drm_bridge *last)
+{
+   struct drm_bridge *temp = head;
+
+   if (head && last) {
+   while (temp->next_bridge)
+   temp = temp->next_bridge;
+
+   temp->next_bridge = last;
+   return 0;
+   }
+
+   return -EINVAL;
+}
+
+static inline void drm_next_bridge_mode_fixup(struct drm_bridge *bridge,
+   const struct drm_display_mode *mode,
+   struct drm_display_mode *adjusted_mode)
+{
+   if (bridge && bridge->next_bridge && bridge->next_bridge->funcs &&
+   bridge->next_bridge->funcs->mode_fixup)
+   bridge->next_bridge->funcs->mode_fixup(bridge->next_bridge,
+   mode, adjusted_mode);
+}
+
+static inline void drm_next_bridge_disable(struct drm_bridge *bridge)
+{
+   if (bridge && bridge->next_bridge && bridge->next_bridge->funcs &&
+   bridge->next_bridge->funcs->disable)
+   bridge->next_bridge->funcs->disable(bridge->next_bridge);
+}
+
+static inline void drm_next_bridge_post_disable(struct drm_bridge *bridge)
+{
+   if (bridge && bridge->next_bridge && bridge->next_bridge->funcs &&
+   bridge->next_bridge->funcs->post_disable)
+   bridge->next_bridge->funcs->post_disable(bridge->next_bridge);
+}
+
+static inline void drm_next_bridge_mode_set(struct drm_bridge *bridge,
+   struct drm_display_mode *mode,
+   struct drm_display_mode *adjusted_mode)
+{
+   if (bridge && bridge->next_bridge && bridge->next_bridge->funcs &&
+   bridge->next_bridge->funcs->mode_set)
+   bridge->next_bridge->funcs->mode_set(bridge->next_bridge,
+   mode, adjusted_mode);
+}
+
+static inline void drm_next_bridge_pre_enable(struct drm_bridge *bridge)
+{
+   if (bridge && bridge->next_bridge && bridge->next_bridge->funcs &&
+   bridge->next_bridge->funcs->pre_enable)
+   bridge->next_bridge->funcs->pre_enable(bridge->next_bridge);
+}
+
+static inline void drm_next_bridge_enable(struct drm_bridge *bridge)
+{
+   if (bridge && bridge->next_bridge && bridge->next_bridge->funcs &&
+   bridge->next_bridge->funcs->enable)
+   bridge->next_bridge->funcs->enable(bridge->next_bridge);
+}
+
+static inline void drm_next_bridge_destroy(struct drm_bridge *bridge)
+{
+   if (bridge && bridge->next_bridge && bridge->next_bridge->funcs &&
+   bridge->next_bridge->funcs->destroy)
+   bridge->next_bridge->funcs->destroy(bridge->next_bridge);
+}
+
 /* Plane list iterator for legacy (overlay only) planes. */
 #define drm_for_each_legacy_plane(plane, planelist) \
list_for_each_entry(plane, planelist, head) \
-- 
1.7.9.5

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[RESEND PATCH V5 03/12] drm/exynos: dp: modify driver to support drm_panel

[Ajay Kumar]

Add drm_panel controls to support powerup/down of the
eDP panel, if one is present at the sink side.

Signed-off-by: Ajay Kumar 
---
 .../devicetree/bindings/video/exynos_dp.txt|2 +
 drivers/gpu/drm/exynos/Kconfig |1 +
 drivers/gpu/drm/exynos/exynos_dp_core.c|   45 
 drivers/gpu/drm/exynos/exynos_dp_core.h|2 +
 4 files changed, 41 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt 
b/Documentation/devicetree/bindings/video/exynos_dp.txt
index 53dbccf..c029a09 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -51,6 +51,8 @@ Required properties for dp-controller:
LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
- display-timings: timings for the connected panel as described by
Documentation/devicetree/bindings/video/display-timing.txt
+   -edp-panel:
+   phandle for the edp/lvds drm_panel node.
 
 Optional properties for dp-controller:
-interlaced:
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 178d2a9..fd1c070 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -52,6 +52,7 @@ config DRM_EXYNOS_DP
bool "EXYNOS DRM DP driver support"
depends on DRM_EXYNOS_FIMD && ARCH_EXYNOS && (DRM_PTN3460=n || 
DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS)
default DRM_EXYNOS
+   select DRM_PANEL
help
  This enables support for DP device.
 
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c 
b/drivers/gpu/drm/exynos/exynos_dp_core.c
index a94b114..b3d0d9b 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "exynos_drm_drv.h"
@@ -1029,6 +1030,9 @@ static int exynos_dp_create_connector(struct 
exynos_drm_display *display,
drm_connector_register(connector);
drm_mode_connector_attach_encoder(connector, encoder);
 
+   if (dp->edp_panel)
+   drm_panel_attach(dp->edp_panel, &dp->connector);
+
return 0;
 }
 
@@ -1063,11 +1067,13 @@ static void exynos_dp_poweron(struct exynos_dp_device 
*dp)
if (dp->dpms_mode == DRM_MODE_DPMS_ON)
return;
 
+   drm_panel_prepare(dp->edp_panel);
clk_prepare_enable(dp->clock);
exynos_dp_phy_init(dp);
exynos_dp_init_dp(dp);
enable_irq(dp->irq);
exynos_dp_setup(dp);
+   drm_panel_enable(dp->edp_panel);
 }
 
 static void exynos_dp_poweroff(struct exynos_dp_device *dp)
@@ -1075,10 +1081,12 @@ static void exynos_dp_poweroff(struct exynos_dp_device 
*dp)
if (dp->dpms_mode != DRM_MODE_DPMS_ON)
return;
 
+   drm_panel_disable(dp->edp_panel);
disable_irq(dp->irq);
flush_work(&dp->hotplug_work);
exynos_dp_phy_exit(dp);
clk_disable_unprepare(dp->clock);
+   drm_panel_unprepare(dp->edp_panel);
 }
 
 static void exynos_dp_dpms(struct exynos_drm_display *display, int mode)
@@ -1209,8 +1217,17 @@ err:
 static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
 {
int ret;
+   struct device_node *videomode_parent;
+
+   /* Receive video timing info from panel node
+* if there is a panel node
+*/
+   if (dp->panel_node)
+   videomode_parent = dp->panel_node;
+   else
+   videomode_parent = dp->dev->of_node;
 
-   ret = of_get_videomode(dp->dev->of_node, &dp->panel.vm,
+   ret = of_get_videomode(videomode_parent, &dp->panel.vm,
OF_USE_NATIVE_MODE);
if (ret) {
DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
@@ -1224,16 +1241,10 @@ static int exynos_dp_bind(struct device *dev, struct 
device *master, void *data)
struct platform_device *pdev = to_platform_device(dev);
struct drm_device *drm_dev = data;
struct resource *res;
-   struct exynos_dp_device *dp;
+   struct exynos_dp_device *dp = exynos_dp_display.ctx;
unsigned int irq_flags;
-
int ret = 0;
 
-   dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
-   GFP_KERNEL);
-   if (!dp)
-   return -ENOMEM;
-
dp->dev = &pdev->dev;
dp->dpms_mode = DRM_MODE_DPMS_OFF;
 
@@ -1307,7 +1318,6 @@ static int exynos_dp_bind(struct device *dev, struct 
device *master, void *data)
disable_irq(dp->irq);
 
dp->drm_dev = drm_dev;
-   exynos_dp_display.ctx = dp;
 
platform_set_drvdata(pdev, &exynos_dp_display);
 
@@ -1334,6 +1344,8 @@ static const struct component_ops exynos_dp_ops = {
 
 static int exynos_dp_probe(struct platform_device *pdev)
 {
+   struct device *dev = &pdev->dev;
+   struct exynos_dp_device *dp;
 

[RESEND PATCH V5 01/12] drm/exynos: Move DP setup out of hotplug workqueue

[Ajay Kumar]

Move the DP training and video enable from the hotplug handler into
a seperate function and call the same during dpms ON.

With existing code, DP HPD should be generated just few ms before
calling enable_irq in dp_poweron.

This patch removes that stringent time constraint.

Signed-off-by: Ajay Kumar 
---
 drivers/gpu/drm/exynos/exynos_dp_core.c |   11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c 
b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 845d766..a94b114 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -875,10 +875,18 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void 
*arg)
 static void exynos_dp_hotplug(struct work_struct *work)
 {
struct exynos_dp_device *dp;
-   int ret;
 
dp = container_of(work, struct exynos_dp_device, hotplug_work);
 
+   if (dp->drm_dev)
+   drm_helper_hpd_irq_event(dp->drm_dev);
+}
+
+static void exynos_dp_setup(void *in_ctx)
+{
+   struct exynos_dp_device *dp = in_ctx;
+   int ret;
+
ret = exynos_dp_detect_hpd(dp);
if (ret) {
/* Cable has been disconnected, we're done */
@@ -1059,6 +1067,7 @@ static void exynos_dp_poweron(struct exynos_dp_device *dp)
exynos_dp_phy_init(dp);
exynos_dp_init_dp(dp);
enable_irq(dp->irq);
+   exynos_dp_setup(dp);
 }
 
 static void exynos_dp_poweroff(struct exynos_dp_device *dp)
-- 
1.7.9.5

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[RESEND PATCH V5 02/12] drm/panel: add prepare and unprepare routines

[Ajay Kumar]

Most of the panels need an init sequence as mentioned below:
-- poweron LCD unit/LCD_EN
-- start video data
-- poweron LED unit/BACKLIGHT_EN
And, a de-init sequence as mentioned below:
-- poweroff LED unit/BACKLIGHT_EN
-- stop video data
-- poweroff LCD unit/LCD_EN
With existing callbacks for drm panel, we cannot accomodate such panels,
since only two callbacks, i.e "panel_enable" and panel_disable are supported.

This patch adds:
-- "prepare" callback which can be called before
the actual video data is on, and then call the "enable"
callback after the video data is available.

-- "unprepare" callback which can be called after
the video data is off, and use "disable" callback
to do something before switching off the video data.

Now, we can easily map the above scenario as shown below:
poweron LCD unit/LCD_EN = "prepare" callback
poweron LED unit/BACKLIGHT_EN = "enable" callback
poweroff LED unit/BACKLIGHT_EN = "disable" callback
poweroff LCD unit/LCD_EN = "unprepare" callback

Signed-off-by: Ajay Kumar 
---
 include/drm/drm_panel.h |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index c2ab77a..9addc69 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -31,7 +31,9 @@ struct drm_device;
 struct drm_panel;
 
 struct drm_panel_funcs {
+   int (*unprepare)(struct drm_panel *panel);
int (*disable)(struct drm_panel *panel);
+   int (*prepare)(struct drm_panel *panel);
int (*enable)(struct drm_panel *panel);
int (*get_modes)(struct drm_panel *panel);
 };
@@ -46,6 +48,14 @@ struct drm_panel {
struct list_head list;
 };
 
+static inline int drm_panel_unprepare(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->unprepare)
+   return panel->funcs->unprepare(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+
 static inline int drm_panel_disable(struct drm_panel *panel)
 {
if (panel && panel->funcs && panel->funcs->disable)
@@ -54,6 +64,14 @@ static inline int drm_panel_disable(struct drm_panel *panel)
return panel ? -ENOSYS : -EINVAL;
 }
 
+static inline int drm_panel_prepare(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->prepare)
+   return panel->funcs->prepare(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+
 static inline int drm_panel_enable(struct drm_panel *panel)
 {
if (panel && panel->funcs && panel->funcs->enable)
-- 
1.7.9.5

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[PATCH V5 05/12] Documentation: Add DT bindings for panel-lvds driver

[Ajay Kumar]

Add DT binding documentation for panel-lvds driver.

Signed-off-by: Ajay Kumar 
---
 .../devicetree/bindings/panel/panel-lvds.txt   |   50 
 1 file changed, 50 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/panel/panel-lvds.txt

diff --git a/Documentation/devicetree/bindings/panel/panel-lvds.txt 
b/Documentation/devicetree/bindings/panel/panel-lvds.txt
new file mode 100644
index 000..fdf91da2
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/panel-lvds.txt
@@ -0,0 +1,50 @@
+panel interface for eDP/lvds panels
+
+Required properties:
+  - compatible: "panel-lvds"
+
+Optional properties:
+   -lcd-enable-gpios:
+   panel LCD poweron GPIO.
+   Indicates which GPIO needs to be powered up as output
+   to powerup/enable the switch to the LCD panel.
+   -backlight-enable-gpios:
+   panel LED enable GPIO.
+   Indicates which GPIO needs to be powered up as output
+   to enable the backlight.
+   -panel-prepare-delay:
+   delay value in ms required for panel_prepare process
+   Delay in ms needed for the panel LCD unit to
+   powerup completely.
+   ex: delay needed till eDP panel throws HPD.
+   delay needed so that we cans tart reading edid.
+   -panel-enable-delay:
+   delay value in ms required for panel_enable process
+   Delay in ms needed for the panel backlight/LED unit
+   to powerup, and delay needed between video_enable and
+   backlight_enable.
+   -panel-disable-delay:
+   delay value in ms required for panel_disable process
+   Delay in ms needed for the panel backlight/LED unit
+   powerdown, and delay needed between backlight_disable
+   and video_disable.
+   -panel-unprepare-delay:
+   delay value in ms required for panel_post_disable process
+   Delay in ms needed for the panel LCD unit to
+   to powerdown completely, and the minimum delay needed
+   before powering it on again.
+   -panel-width-mm: physical panel width [mm]
+   -panel-height-mm: physical panel height [mm]
+
+Example:
+
+   panel-lvds {
+   compatible = "panel-lvds";
+   backlight-enable-gpios = <&gpx3 0 0>;
+   panel-prepare-delay = <40>;
+   panel-enable-delay = <20>;
+   panel-disable-delay = <20>;
+   panel-unprepare-delay = <30>;
+   panel-width-mm = <256>;
+   panel-height-mm = <144>;
+   };
-- 
1.7.9.5

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[PATCH V5 00/12] drm/exynos: few patches to enhance bridge chip support

[Ajay Kumar]

This series is based on exynos-drm-next branch of Inki Dae's tree at:
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git

This patchset also consolidates various inputs from the drm community
regarding the bridge chaining concept:
(1) [RFC V2 0/3] drm/bridge: panel and chaining
http://www.spinics.net/lists/linux-samsung-soc/msg30160.html
(2) [RFC V3 0/3] drm/bridge: panel and chaining
http://www.spinics.net/lists/linux-samsung-soc/msg30507.html

I have tested this after adding few DT changes for exynos5250-snow,
exynos5420-peach-pit and exynos5800-peach-pi boards.

The V4 series of this particular patchset was also tested by:
Rahul Sharma 
Javier Martinez Canillas 

Changes since V2:
-- Address comments from Jingoo Han for ps8622 driver
-- Address comments from Daniel, Rob and Thierry regarding
   bridge chaining
-- Address comments from Thierry regarding the names for
   new drm_panel functions

Changes since V3:
-- Remove hotplug based initialization of exynos_dp
-- Make exynos_dp work directly with drm_panel, remove
   dependency on panel_binder
-- Minor cleanups in panel_binder and panel_lvds driver

Changes since V4:
-- Use gpiod interface for panel-lvds and ps8622 drivers.
-- Address comments from Javier.
-- Fix compilation issues when PANEL_BINDER is selected as module.
-- Split Documentation patches from driver patches.
-- Rebase on top of the tree.

Ajay Kumar (9):
  [RESEND PATCH V5 01/12] drm/exynos: Move DP setup out of hotplug workqueue
  [RESEND PATCH V5 02/12] drm/panel: add prepare and unprepare routines
  [RESEND PATCH V5 03/12] drm/exynos: dp: modify driver to support drm_panel
  [PATCH V5 04/12] drm/panel: Add driver for lvds/edp based panels
  [PATCH V5 05/12] Documentation: Add DT bindings for panel-lvds driver
  [RESEND PATCH V5 06/12] drm/bridge: add helper functions to support bridge 
chain
  [PATCH V5 07/12] drm/bridge: Add a driver which binds drm_bridge with 
drm_panel
  [RESEND PATCH V5 08/12] drm/bridge: ptn3460: Support bridge chaining
  [RESEND PATCH V5 09/12] drm/exynos: dp: create bridge chain using ptn3460 and 
panel_binder

Vincent Palatin (2):
  [PATCH V5 10/12] Documentation: Add DT bindings for ps8622/ps8625 bridge 
driver
  [PATCH V5 11/12] drm/bridge: Add ps8622/ps8625 bridge driver

Rahul Sharma (1):
  [RESEND PATCH V5 12/12] drm/exynos: Add ps8622 lvds bridge discovery to DP 
driver

 .../devicetree/bindings/drm/bridge/ps8622.txt  |   21 +
 .../devicetree/bindings/panel/panel-lvds.txt   |   50 ++
 .../devicetree/bindings/video/exynos_dp.txt|2 +
 drivers/gpu/drm/bridge/Kconfig |   15 +
 drivers/gpu/drm/bridge/Makefile|2 +
 drivers/gpu/drm/bridge/panel_binder.c  |  193 
 drivers/gpu/drm/bridge/ps8622.c|  476 
 drivers/gpu/drm/bridge/ptn3460.c   |  137 +-
 drivers/gpu/drm/exynos/Kconfig |1 +
 drivers/gpu/drm/exynos/exynos_dp_core.c|   87 +++-
 drivers/gpu/drm/exynos/exynos_dp_core.h|2 +
 drivers/gpu/drm/panel/Kconfig  |   10 +
 drivers/gpu/drm/panel/Makefile |1 +
 drivers/gpu/drm/panel/panel-lvds.c |  268 +++
 include/drm/bridge/panel_binder.h  |   44 ++
 include/drm/bridge/ps8622.h|   41 ++
 include/drm/bridge/ptn3460.h   |   15 +-
 include/drm/drm_crtc.h |   72 +++
 include/drm/drm_panel.h|   18 +
 19 files changed, 1316 insertions(+), 139 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/ps8622.txt
 create mode 100644 Documentation/devicetree/bindings/panel/panel-lvds.txt
 create mode 100644 drivers/gpu/drm/bridge/panel_binder.c
 create mode 100644 drivers/gpu/drm/bridge/ps8622.c
 create mode 100644 drivers/gpu/drm/panel/panel-lvds.c
 create mode 100644 include/drm/bridge/panel_binder.h
 create mode 100644 include/drm/bridge/ps8622.h

-- 
1.7.9.5

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Re: [RESEND PATCH v3] charger: tps65090: Allow charger module to be used when no irq

[Sebastian Reichel]

Hi,

On Fri, Jun 20, 2014 at 02:42:03PM -0700, Doug Anderson wrote:
> On the ARM Chromebook tps65090 has two masters: the AP (the main
> processor running linux) and the EC (the embedded controller).  The AP
> is allowed to mess with FETs but the EC is in charge of charge control.
> 
> The tps65090 interupt line is routed to both the AP and the EC, which
> can cause quite a headache.  Having two people adjusting masks and
> acking interrupts is a recipe for disaster.
> 
> In the shipping kernel we had a hack to have the AP pay attention to
> the IRQ but not to ack it.  It also wasn't supposed to configure the
> IRQ in any way.  That hack allowed us to detect when the device was
> charging without messing with the EC's state.
> 
> The current tps65090 infrastructure makes the above difficult, and it
> was a bit of a hack to begin with.  Rather than uglify the driver to
> support it, just extend the driver's existing notion of "no irq" to
> the charger.  This makes the charger code poll every 2 seconds for AC
> detect, which is sufficient.
> 
> For proper functioning, requires (mfd: tps65090: Don't tell child
> devices we have an IRQ if we don't).  If we don't have that patch
> we'll simply fail to probe on devices without an interrupt (just like
> we did before this patch).

Applied to the dev branch, which I use until I get access to the
official battery.git:

https://git.kernel.org/cgit/linux/kernel/git/sre/linux-power-supply.git/commit/?h=dev&id=5a3effdc8877132fd12f97fea0d4756614b911c7

-- Sebastian


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Re: [PATCH 1/4] Revert "spi: s3c64xx: Added provision for dedicated cs pin"

[Javier Martinez Canillas]

Hello Mark,

On 07/17/2014 08:46 PM, Mark Brown wrote:
> On Wed, Jul 16, 2014 at 05:19:07PM +0200, Javier Martinez Canillas wrote:
>> This reverts commit 3146beec21b64f4551fcf0ac148381d54dc41b1b.
> 
> For the benefit of those who haven't memorized the SHA1s of every commit
> that's "spi: s3c64xx: Added provision for dedicated cs pin" - please
> include the human readable format whenever you reference a SHA1.
> 

Ok, I'll take into account for the next time.

> I've applied this.
> 

Thanks a lot for your help and sorry for all the inconveniences that this series
caused to you.

Best regards,
Javier
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Re: [PATCH 4/4] ARM: DTS: fix the chip select gpios definition in the SPI nodes

[Mark Brown]

On Wed, Jul 16, 2014 at 05:19:10PM +0200, Javier Martinez Canillas wrote:
> From: Naveen Krishna Chatradhi 
> 
> This patch replaces the "cs-gpio" from "controller-data" node
> as was specified in the old binding and uses the standard
> "cs-gpios" property expected by the SPI core as is defined now
> in the spi-s3c64xx driver DT binding.

I've applied this one too since everything here really ought to go in
together and we should probably try to get this into v3.16 - Kukjin,
please say if this is an issue and I can revert.


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Re: [PATCH 3/4] spi: samsung: Update binding documentation

[Mark Brown]

On Wed, Jul 16, 2014 at 05:19:09PM +0200, Javier Martinez Canillas wrote:
> From: Naveen Krishna Chatradhi 
> 
> Samsung SPI driver now uses the generic SPI "cs-gpios"
> binding so update the documentation accordingly.

Applied, thanks.  Please do try to use changelogs that are consistent
with the general style, or at least consistent within a patch series.


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Re: [PATCH 2/4] spi: s3c64xx: use the generic SPI "cs-gpios" property

[Mark Brown]

On Wed, Jul 16, 2014 at 05:19:08PM +0200, Javier Martinez Canillas wrote:
> From: Naveen Krishna Chatradhi 
> 
> The s3c64xx SPI driver uses a custom DT binding to specify
> the GPIO used to drive the chip select (CS) line instead of
> using the generic "cs-gpios" property already defined in:
> Documentation/devicetree/bindings/spi/spi-bus.txt.

Applied, thanks.


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Re: [PATCH 1/4] Revert "spi: s3c64xx: Added provision for dedicated cs pin"

[Mark Brown]

On Wed, Jul 16, 2014 at 05:19:07PM +0200, Javier Martinez Canillas wrote:
> This reverts commit 3146beec21b64f4551fcf0ac148381d54dc41b1b.

For the benefit of those who haven't memorized the SHA1s of every commit
that's "spi: s3c64xx: Added provision for dedicated cs pin" - please
include the human readable format whenever you reference a SHA1.

I've applied this.


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Re: [PATCH v3 3/5] i2c: exynos5: Remove suspension check

[Bastian Hecht]

2014-07-17 16:48 GMT+02:00 Bastian Hecht :
> We now take care of suspension in the i2c core code. So we can remove this
> check here.
>
> Signed-off-by: Bastian Hecht 
> ---
> same as v1
>
>  drivers/i2c/busses/i2c-exynos5.c | 20 +---
>  1 file changed, 1 insertion(+), 19 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-exynos5.c 
> b/drivers/i2c/busses/i2c-exynos5.c
> index 63d2292..a80cf28 100644
> --- a/drivers/i2c/busses/i2c-exynos5.c
> +++ b/drivers/i2c/busses/i2c-exynos5.c
> @@ -145,7 +145,6 @@
>
>  struct exynos5_i2c {
> struct i2c_adapter  adap;
> -   unsigned intsuspended:1;
>
> struct i2c_msg  *msg;
> struct completion   msg_complete;
> @@ -610,11 +609,6 @@ static int exynos5_i2c_xfer(struct i2c_adapter *adap,
> struct exynos5_i2c *i2c = adap->algo_data;
> int i = 0, ret = 0, stop = 0;
>
> -   if (i2c->suspended) {
> -   dev_err(i2c->dev, "HS-I2C is not initialized.\n");
> -   return -EIO;
> -   }
> -
> clk_prepare_enable(i2c->clk);
>
> for (i = 0; i < num; i++, msgs++) {
> @@ -757,16 +751,6 @@ static int exynos5_i2c_remove(struct platform_device 
> *pdev)
>  }
>
>  #ifdef CONFIG_PM_SLEEP
> -static int exynos5_i2c_suspend_noirq(struct device *dev)
> -{
> -   struct platform_device *pdev = to_platform_device(dev);
> -   struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
> -
> -   i2c->suspended = 1;
> -
> -   return 0;
> -}
> -
>  static int exynos5_i2c_resume_noirq(struct device *dev)
>  {
> struct platform_device *pdev = to_platform_device(dev);
> @@ -783,14 +767,12 @@ static int exynos5_i2c_resume_noirq(struct device *dev)
>
> exynos5_i2c_init(i2c);
> clk_disable_unprepare(i2c->clk);
> -   i2c->suspended = 0;
>
> return 0;
>  }
>  #endif
>
> -static SIMPLE_DEV_PM_OPS(exynos5_i2c_dev_pm_ops, exynos5_i2c_suspend_noirq,
> -exynos5_i2c_resume_noirq);
> +static SIMPLE_DEV_PM_OPS(exynos5_i2c_dev_pm_ops, exynos5_i2c_resume_noirq);

This should be

+static SIMPLE_DEV_PM_OPS(exynos5_i2c_dev_pm_ops, NULL,
exynos5_i2c_resume_noirq);

And this is v2, not v3.

>  static struct platform_driver exynos5_i2c_driver = {
> .probe  = exynos5_i2c_probe,
> --
> 1.9.1
>
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[PATCH v3 3/7] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL

[Tomasz Figa]

Certain platforms (i.e. Exynos) might need to set .write_sec callback
from firmware initialization which is happenning in .init_early callback
of machine descriptor. However current code will overwrite the pointer
with whatever is present in machine descriptor, even though it can be
already set earlier. This patch fixes this by making the assignment
conditional, depending on whether current .write_sec callback is NULL.

Signed-off-by: Tomasz Figa 
---
 arch/arm/kernel/irq.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 2c42576..e7383b9 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -125,7 +125,8 @@ void __init init_IRQ(void)
 
if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) &&
(machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) {
-   outer_cache.write_sec = machine_desc->l2c_write_sec;
+   if (!outer_cache.write_sec)
+   outer_cache.write_sec = machine_desc->l2c_write_sec;
ret = l2x0_of_init(machine_desc->l2c_aux_val,
   machine_desc->l2c_aux_mask);
if (ret)
-- 
1.9.3

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[PATCH v3 5/7] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310

[Tomasz Figa]

Exynos4 SoCs equipped with an L2C-310 cache controller and running under
secure firmware require certain registers of aforementioned IP to be
accessed only from secure mode. This means that SMC calls are required
for certain register writes. To handle this, an implementation of
.write_sec and .configure callbacks is provided by this patch.

Signed-off-by: Tomasz Figa 
---
 arch/arm/mach-exynos/firmware.c | 38 ++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index f5e626d..554b350 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -120,6 +121,31 @@ static const struct firmware_ops exynos_firmware_ops = {
.resume = exynos_resume,
 };
 
+static void exynos_l2_write_sec(unsigned long val, unsigned reg)
+{
+   switch (reg) {
+   case L2X0_CTRL:
+   if (val & L2X0_CTRL_EN)
+   exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
+   exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
+   break;
+
+   case L2X0_DEBUG_CTRL:
+   exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
+   break;
+
+   default:
+   WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg);
+   }
+}
+
+static void exynos_l2_configure(const struct l2x0_regs *regs)
+{
+   exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
+   regs->prefetch_ctrl);
+   exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
+}
+
 void __init exynos_firmware_init(void)
 {
struct device_node *nd;
@@ -139,4 +165,16 @@ void __init exynos_firmware_init(void)
pr_info("Running under secure firmware.\n");
 
register_firmware_ops(&exynos_firmware_ops);
+
+   /*
+* Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
+* running under secure firmware, require certain registers of L2
+* cache controller to be written in secure mode. Here .write_sec
+* callback is provided to perform necessary SMC calls.
+*/
+   if (IS_ENABLED(CONFIG_CACHE_L2X0)
+   && read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
+   outer_cache.write_sec = exynos_l2_write_sec;
+   outer_cache.configure = exynos_l2_configure;
+   }
 }
-- 
1.9.3

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[PATCH v3 4/7] ARM: l2c: Add support for overriding prefetch settings

[Tomasz Figa]

Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
settings configured in registers leading to crashes if L2C is enabled
without overriding them. This patch introduces bindings to enable
prefetch settings to be specified from DT and necessary support in the
driver.

Signed-off-by: Tomasz Figa 
---
 Documentation/devicetree/bindings/arm/l2cc.txt | 10 +++
 arch/arm/mm/cache-l2x0.c   | 39 ++
 2 files changed, 49 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt 
b/Documentation/devicetree/bindings/arm/l2cc.txt
index af527ee..3443d2d 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -47,6 +47,16 @@ Optional properties:
 - cache-id-part: cache id part number to be used if it is not present
   on hardware
 - wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+  non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+  if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+  if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if 
non-zero,
+  disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+  0-7, 15, 23, and 31.
 
 Example:
 
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 21a625a0..6274803 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1055,6 +1055,8 @@ static void __init l2c310_of_parse(const struct 
device_node *np,
u32 data[3] = { 0, 0, 0 };
u32 tag[3] = { 0, 0, 0 };
u32 filter[2] = { 0, 0 };
+   u32 prefetch;
+   u32 val;
 
of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
if (tag[0] && tag[1] && tag[2])
@@ -1079,6 +1081,43 @@ static void __init l2c310_of_parse(const struct 
device_node *np,
l2x0_saved_regs.filter_start = (filter[0] & ~(SZ_1M - 1))
| L310_ADDR_FILTER_EN;
}
+
+   prefetch = l2x0_saved_regs.prefetch_ctrl;
+
+   if (!of_property_read_u32(np, "arm,double-linefill", &val)) {
+   if (val)
+   prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL;
+   else
+   prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL;
+   }
+
+   if (!of_property_read_u32(np, "arm,double-linefill-incr", &val)) {
+   if (val)
+   prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
+   else
+   prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
+   }
+
+   if (!of_property_read_u32(np, "arm,double-linefill-wrap", &val)) {
+   if (!val)
+   prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
+   else
+   prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
+   }
+
+   if (!of_property_read_u32(np, "arm,prefetch-drop", &val)) {
+   if (val)
+   prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP;
+   else
+   prefetch &= ~L310_PREFETCH_CTRL_PREFETCH_DROP;
+   }
+
+   if (!of_property_read_u32(np, "arm,prefetch-offset", &val)) {
+   prefetch &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
+   prefetch |= val & L310_PREFETCH_CTRL_OFFSET_MASK;
+   }
+
+   l2x0_saved_regs.prefetch_ctrl = prefetch;
 }
 
 static const struct l2c_init_data of_l2c310_data __initconst = {
-- 
1.9.3

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[PATCH v3 2/7] ARM: l2c: Add interface to ask hypervisor to configure L2C

[Tomasz Figa]

Because certain secure hypervisor do not allow writes to individual L2C
registers, but rather expect set of parameters to be passed as argument
to secure monitor calls, there is a need to provide an interface for the
L2C driver to ask the firmware to configure the hardware according to
specified parameters. This patch adds such.

Signed-off-by: Tomasz Figa 
---
 arch/arm/include/asm/outercache.h | 3 +++
 arch/arm/mm/cache-l2x0.c  | 5 +
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/include/asm/outercache.h 
b/arch/arm/include/asm/outercache.h
index 891a56b..563b92f 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -23,6 +23,8 @@
 
 #include 
 
+struct l2x0_regs;
+
 struct outer_cache_fns {
void (*inv_range)(unsigned long, unsigned long);
void (*clean_range)(unsigned long, unsigned long);
@@ -36,6 +38,7 @@ struct outer_cache_fns {
 
/* This is an ARM L2C thing */
void (*write_sec)(unsigned long, unsigned);
+   void (*configure)(const struct l2x0_regs *);
 };
 
 extern struct outer_cache_fns outer_cache;
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 385c047..21a625a0 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -109,6 +109,11 @@ static inline void l2c_unlock(void __iomem *base, unsigned 
num)
 
 static void l2c_configure(void __iomem *base)
 {
+   if (outer_cache.configure) {
+   outer_cache.configure(&l2x0_saved_regs);
+   return;
+   }
+
if (l2x0_data->configure)
l2x0_data->configure(base);
 
-- 
1.9.3

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[PATCH v3 1/7] ARM: l2c: Refactor the driver to use commit-like interface

[Tomasz Figa]

Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes the .write_sec()-based interface insufficient and
provoking ugly hacks.

This patch is first step to make the driver not rely on availability of
writes to individual registers. This is achieved by refactoring the
driver to use a commit-like operation scheme: all register values are
prepared first and stored in an instance of l2x0_regs struct and then a
single callback is responsible to flush those values to the hardware.

Signed-off-by: Tomasz Figa 
---
 arch/arm/mm/cache-l2x0.c | 201 ++-
 1 file changed, 110 insertions(+), 91 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5f2c988..385c047 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -40,12 +40,14 @@ struct l2c_init_data {
void (*enable)(void __iomem *, u32, unsigned);
void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
void (*save)(void __iomem *);
+   void (*configure)(void __iomem *);
struct outer_cache_fns outer_cache;
 };
 
 #define CACHE_LINE_SIZE32
 
 static void __iomem *l2x0_base;
+static const struct l2c_init_data *l2x0_data;
 static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;  /* Bitmask of active ways */
 static u32 l2x0_size;
@@ -105,6 +107,14 @@ static inline void l2c_unlock(void __iomem *base, unsigned 
num)
}
 }
 
+static void l2c_configure(void __iomem *base)
+{
+   if (l2x0_data->configure)
+   l2x0_data->configure(base);
+
+   l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
+}
+
 /*
  * Enable the L2 cache controller.  This function must only be
  * called when the cache controller is known to be disabled.
@@ -113,7 +123,12 @@ static void l2c_enable(void __iomem *base, u32 aux, 
unsigned num_lock)
 {
unsigned long flags;
 
-   l2c_write_sec(aux, base, L2X0_AUX_CTRL);
+   /* Do not touch the controller if already enabled. */
+   if (readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)
+   return;
+
+   l2x0_saved_regs.aux_ctrl = aux;
+   l2c_configure(base);
 
l2c_unlock(base, num_lock);
 
@@ -207,6 +222,12 @@ static void l2c_save(void __iomem *base)
l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 }
 
+static void l2c_resume(void)
+{
+   l2x0_data->enable(l2x0_base, l2x0_saved_regs.aux_ctrl,
+   l2x0_data->num_lock);
+}
+
 /*
  * L2C-210 specific code.
  *
@@ -287,14 +308,6 @@ static void l2c210_sync(void)
__l2c210_cache_sync(l2x0_base);
 }
 
-static void l2c210_resume(void)
-{
-   void __iomem *base = l2x0_base;
-
-   if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
-   l2c_enable(base, l2x0_saved_regs.aux_ctrl, 1);
-}
-
 static const struct l2c_init_data l2c210_data __initconst = {
.type = "L2C-210",
.way_size_0 = SZ_8K,
@@ -308,7 +321,7 @@ static const struct l2c_init_data l2c210_data __initconst = 
{
.flush_all = l2c210_flush_all,
.disable = l2c_disable,
.sync = l2c210_sync,
-   .resume = l2c210_resume,
+   .resume = l2c_resume,
},
 };
 
@@ -465,7 +478,7 @@ static const struct l2c_init_data l2c220_data = {
.flush_all = l2c220_flush_all,
.disable = l2c_disable,
.sync = l2c220_sync,
-   .resume = l2c210_resume,
+   .resume = l2c_resume,
},
 };
 
@@ -614,39 +627,29 @@ static void __init l2c310_save(void __iomem *base)
L310_POWER_CTRL);
 }
 
-static void l2c310_resume(void)
+static void l2c310_configure(void __iomem *base)
 {
-   void __iomem *base = l2x0_base;
+   unsigned revision;
 
-   if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
-   unsigned revision;
-
-   /* restore pl310 setup */
-   writel_relaxed(l2x0_saved_regs.tag_latency,
-  base + L310_TAG_LATENCY_CTRL);
-   writel_relaxed(l2x0_saved_regs.data_latency,
-  base + L310_DATA_LATENCY_CTRL);
-   writel_relaxed(l2x0_saved_regs.filter_end,
-  base + L310_ADDR_FILTER_END);
-   writel_relaxed(l2x0_saved_regs.filter_start,
-  base + L310_ADDR_FILTER_START);
-
-   revision = readl_relaxed(base + L2X0_CACHE_ID) &
-   L2X0_CACHE_ID_RTL_MASK;
-
-   if (revision >= L310_CACHE_ID_RTL_R2P0)
-   l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base,
- L310_PREFETCH_CTRL);
-   if (revision >= L310_CACHE_ID_RTL_R3P0)
-

[PATCH v3 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs

[Tomasz Figa]

This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which requires certain initialization steps
to be done with help of firmware, as selected registers are writable only
from secure mode.

First four patches extend existing support for secure write in L2C driver
to account for design of secure firmware running on Exynos. Namely:
 1) direct read access to certain registers is needed on Exynos, because
secure firmware calls set several registers at once,
 2) not all boards are running secure firmware, so .write_sec callback
needs to be installed in Exynos firmware ops initialization code,
 3) write access to {DATA,TAG}_LATENCY_CTRL registers fron non-secure world
is not allowed and so must use l2c_write_sec as well,
 4) on certain boards, default value of prefetch register is incorrect
and must be overridden at L2C initialization.
For boards running with firmware that provides access to individual
L2C registers this series should introduce no functional changes. However
since the driver is widely used on other platforms I'd like to kindly ask
any interested people for testing.

Further two patches add impelmentation of .write_sec for Exynos secure
firmware and necessary DT nodes to enable L2 cache.

Tested on Exynos4210-based Universal C210 and Trats (both without secure
firmware) and Exynos4412-based TRATS2 and ODROID-U3 boards (both with secure
firmware).

Depends on:
 - [PATCH] ARM: make it easier to check the CPU part number correctly
   (http://thread.gmane.org/gmane.linux.ports.arm.kernel/335126
already in linux-next)
 - [PATCH v2 0/2] Firmware-assisted suspend/resume of Exynos SoCs
   (https://lkml.org/lkml/2014/7/17/431)

Changes since v2:
(https://lkml.org/lkml/2014/6/25/416)
 - refactored L2C driver to use commit-like interface and make it no longer
   depend on availability of writes to individual registers,
 - moved L2C resume to assembly code, because doing it later makes some
   systems unstable - this is also needed for deeper cpuidle modes,
 - dropped unnecessary patch hacking around the .write_sec interface,
 - dropped patch making the driver use l2c_write_sec() for LATENCY_CTRL
   registers as Exynos is no longer affected and I'm not aware of any
   reports that this is also needed on other platforms (can be applied
   separately if it turns out to be so),
 - rebased onto next-20140717 tag of linux-next tree.

Changes since v1:
(https://www.mail-archive.com/linux-omap@vger.kernel.org/msg106323.html)
 - rebased onto for-next branch of linux-samsung tree,
 - changed argument order of outer_cache.write_sec() callback to match
   l2c_write_sec() function in cache-l2x0.c,
 - added support of overriding of prefetch settings to work around incorrect
   default settings on certain Exynos4x12-based boards,
 - added call to firmware to invalidate whole L2 cache before setting enable
   bit in L2C control register (required by Exynos secure firmware).

Tomasz Figa (7):
  ARM: l2c: Refactor the driver to use commit-like interface
  ARM: l2c: Add interface to ask hypervisor to configure L2C
  ARM: l2c: Get outer cache .write_sec callback from mach_desc only if
not NULL
  ARM: l2c: Add support for overriding prefetch settings
  ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310
  ARM: EXYNOS: Add support for non-secure L2X0 resume
  ARM: dts: exynos4: Add nodes for L2 cache controller

 Documentation/devicetree/bindings/arm/l2cc.txt |  10 +
 arch/arm/boot/dts/exynos4210.dtsi  |   9 +
 arch/arm/boot/dts/exynos4x12.dtsi  |  14 ++
 arch/arm/include/asm/outercache.h  |   3 +
 arch/arm/kernel/irq.c  |   3 +-
 arch/arm/mach-exynos/common.h  |   1 +
 arch/arm/mach-exynos/firmware.c|  40 
 arch/arm/mach-exynos/sleep.S   |  41 +
 arch/arm/mm/cache-l2x0.c   | 245 -
 9 files changed, 274 insertions(+), 92 deletions(-)

-- 
1.9.3

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[PATCH v3 6/7] ARM: EXYNOS: Add support for non-secure L2X0 resume

[Tomasz Figa]

On Exynos SoCs it is necessary to resume operation of L2C early in
assembly code, because otherwise certain systems will crash. This patch
adds necessary code to non-secure resume handler.

Signed-off-by: Tomasz Figa 
---
 arch/arm/mach-exynos/common.h   |  1 +
 arch/arm/mach-exynos/firmware.c |  2 ++
 arch/arm/mach-exynos/sleep.S| 41 +
 3 files changed, 44 insertions(+)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index a3f3061..2540827 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -113,6 +113,7 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, 
EXYNOS5_SOC_MASK)
 
 extern u32 cp15_save_diag;
 extern u32 cp15_save_power;
+extern unsigned long l2x0_regs_phys;
 
 extern void __iomem *sysram_ns_base_addr;
 extern void __iomem *sysram_base_addr;
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 554b350..09131d3 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -103,6 +103,8 @@ static int exynos_suspend(void)
writel(virt_to_phys(exynos_cpu_resume_ns),
sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
 
+   l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
+
return cpu_suspend(0, exynos_cpu_suspend);
 }
 
diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S
index e3c3730..b8ce8f0 100644
--- a/arch/arm/mach-exynos/sleep.S
+++ b/arch/arm/mach-exynos/sleep.S
@@ -16,6 +16,8 @@
  */
 
 #include 
+#include 
+#include 
 #include "smc.h"
 
 #define CPU_MASK   0xff00
@@ -74,6 +76,40 @@ ENTRY(exynos_cpu_resume_ns)
mov r0, #SMC_CMD_C15RESUME
dsb
smc #0
+#ifdef CONFIG_CACHE_L2X0
+   adr r0, l2x0_regs_phys
+   ldr r0, [r0]
+   cmp r0, #0
+   beq skip_l2x0
+
+   ldr r1, [r0, #L2X0_R_PHY_BASE]
+   ldr r2, [r1, #L2X0_CTRL]
+   tst r2, #0x1
+   bne skip_l2x0
+
+   ldr r1, [r0, #L2X0_R_TAG_LATENCY]
+   ldr r2, [r0, #L2X0_R_DATA_LATENCY]
+   ldr r3, [r0, #L2X0_R_PREFETCH_CTRL]
+   mov r0, #SMC_CMD_L2X0SETUP1
+   smc #0
+
+   /* Reload saved regs pointer because smc corrupts registers. */
+   adr r0, l2x0_regs_phys
+   ldr r0, [r0]
+
+   ldr r1, [r0, #L2X0_R_PWR_CTRL]
+   ldr r2, [r0, #L2X0_R_AUX_CTRL]
+   mov r0, #SMC_CMD_L2X0SETUP2
+   smc #0
+
+   mov r0, #SMC_CMD_L2X0INVALL
+   smc #0
+
+   mov r1, #1
+   mov r0, #SMC_CMD_L2X0CTRL
+   smc #0
+skip_l2x0:
+#endif /* CONFIG_CACHE_L2X0 */
 skip_cp15:
b   cpu_resume
 ENDPROC(exynos_cpu_resume_ns)
@@ -83,3 +119,8 @@ cp15_save_diag:
.globl cp15_save_power
 cp15_save_power:
.long   0   @ cp15 power control
+#ifdef CONFIG_CACHE_L2X0
+   .globl l2x0_regs_phys
+l2x0_regs_phys:
+   .long   0   @ phys address of l2x0 save struct
+#endif /* CONFIG_CACHE_L2X0 */
-- 
1.9.3

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[PATCH v3 7/7] ARM: dts: exynos4: Add nodes for L2 cache controller

[Tomasz Figa]

This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.

Signed-off-by: Tomasz Figa 
---
 arch/arm/boot/dts/exynos4210.dtsi |  9 +
 arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
 2 files changed, 23 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4210.dtsi 
b/arch/arm/boot/dts/exynos4210.dtsi
index ee3001f..99970ab 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -54,6 +54,15 @@
reg = <0x10023CA0 0x20>;
};
 
+   l2c: l2-cache-controller@10502000 {
+   compatible = "arm,pl310-cache";
+   reg = <0x10502000 0x1000>;
+   cache-unified;
+   cache-level = <2>;
+   arm,tag-latency = <2 2 1>;
+   arm,data-latency = <2 2 1>;
+   };
+
gic: interrupt-controller@1049 {
cpu-offset = <0x8000>;
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi 
b/arch/arm/boot/dts/exynos4x12.dtsi
index c5a943d..ddffefe 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -60,6 +60,20 @@
reg = <0x10023CA0 0x20>;
};
 
+   l2c: l2-cache-controller@10502000 {
+   compatible = "arm,pl310-cache";
+   reg = <0x10502000 0x1000>;
+   cache-unified;
+   cache-level = <2>;
+   arm,tag-latency = <2 2 1>;
+   arm,data-latency = <3 2 1>;
+   arm,double-linefill = <1>;
+   arm,double-linefill-incr = <0>;
+   arm,double-linefill-wrap = <1>;
+   arm,prefetch-drop = <1>;
+   arm,prefetch-offset = <7>;
+   };
+
clock: clock-controller@1003 {
compatible = "samsung,exynos4412-clock";
reg = <0x1003 0x2>;
-- 
1.9.3

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[PATCH v2 1/2] ARM: firmware: Introduce suspend and resume operations

[Tomasz Figa]

This patch extends the firmware_ops structure with two new callbacks:
.suspend() and .resume(). The former is intended to ask the firmware to
save all its volatile state and suspend the system, without returning
back to the kernel in between. The latter is to be called early by
very low level platform suspend code after waking up to restore low
level hardware state, which can't be restored in non-secure mode.

While at it, outdated version of the structure is removed from the
documentation and replaced with a reference to the header file.

Signed-off-by: Tomasz Figa 
Acked-by: Alexandre Courbot 
---
 Documentation/arm/firmware.txt  | 28 +---
 arch/arm/include/asm/firmware.h |  8 
 2 files changed, 13 insertions(+), 23 deletions(-)

diff --git a/Documentation/arm/firmware.txt b/Documentation/arm/firmware.txt
index c2e468f..da6713a 100644
--- a/Documentation/arm/firmware.txt
+++ b/Documentation/arm/firmware.txt
@@ -7,32 +7,14 @@ world, which changes the way some things have to be 
initialized. This makes
 a need to provide an interface for such platforms to specify available firmware
 operations and call them when needed.
 
-Firmware operations can be specified using struct firmware_ops
-
-   struct firmware_ops {
-   /*
-   * Enters CPU idle mode
-   */
-   int (*do_idle)(void);
-   /*
-   * Sets boot address of specified physical CPU
-   */
-   int (*set_cpu_boot_addr)(int cpu, unsigned long boot_addr);
-   /*
-   * Boots specified physical CPU
-   */
-   int (*cpu_boot)(int cpu);
-   /*
-   * Initializes L2 cache
-   */
-   int (*l2x0_init)(void);
-   };
-
-and then registered with register_firmware_ops function
+Firmware operations can be specified by filling in a struct firmware_ops
+with appropriate callbacks and then registering it with register_firmware_ops()
+function.
 
void register_firmware_ops(const struct firmware_ops *ops)
 
-the ops pointer must be non-NULL.
+The ops pointer must be non-NULL. More information about struct firmware_ops
+and its members can be found in arch/arm/include/asm/firmware.h header.
 
 There is a default, empty set of operations provided, so there is no need to
 set anything if platform does not require firmware operations.
diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h
index 2c9f10d..5904f59 100644
--- a/arch/arm/include/asm/firmware.h
+++ b/arch/arm/include/asm/firmware.h
@@ -41,6 +41,14 @@ struct firmware_ops {
 * Initializes L2 cache
 */
int (*l2x0_init)(void);
+   /*
+* Enter system-wide suspend.
+*/
+   int (*suspend)(void);
+   /*
+* Restore state of privileged hardware after system-wide suspend.
+*/
+   int (*resume)(void);
 };
 
 /* Global pointer for current firmware_ops structure, can't be NULL. */
-- 
1.9.3

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Re: [PATCH] irqchip: gic: Fix core ID calculation when topology is read from DT

[Tomasz Figa]

On 17.07.2014 17:51, Jason Cooper wrote:
> On Thu, Jul 17, 2014 at 05:40:50PM +0200, Tomasz Figa wrote:
>> Hi Jason,
>>
>> On 17.07.2014 17:32, Jason Cooper wrote:
>>> On Thu, Jul 17, 2014 at 05:23:44PM +0200, Tomasz Figa wrote:
 Certain GIC implementation, namely those found on earlier, single
 cluster, Exynos SoCs, have registers mapped without per-CPU banking,
 which means that the driver needs to use different offset for each CPU.

 Currently the driver calculates the offset by multiplying value returned
 by cpu_logical_map() by CPU offset parsed from DT. This is correct when
 CPU topology is not specified in DT and aforementioned function returns
 core ID alone. However when DT contains CPU topology, the function
 changes to return cluster ID as well, which is non-zero on mentioned
 SoCs and so breaks the calculation in GIC driver.

 This patch fixes this by masking out cluster ID in CPU offset
 calculation so that only core ID is considered. Multi-cluster Exynos
 SoCs already have banked GIC implementations, so this simple fix should
 be enough.

 Reported-by: Lorenzo Pieralisi 
 Reported-by: Bartlomiej Zolnierkiewicz 
 Signed-off-by: Tomasz Figa 
 ---
  drivers/irqchip/irq-gic.c | 5 -
  1 file changed, 4 insertions(+), 1 deletion(-)
>>>
>>> iiuc, this was introduced by:
>>>
>>>   db0d4db22a78d ARM: gic: allow GIC to support non-banked setups
>>>
>>> and so should be for v3.3 and up, correct?
>>
>> Could be, although there was and still is no topology data specified in
>> DT for affected Exynos SoCs. The need for it showed up just recently, so
>> I'm not sure this is a regression to fix in older kernels.
> 
> In my "the kernel and the dtb aren't tied together" quest, these are the
> kinds of things I like to see fixed in stable kernels.
> 
> If a user needs to update a dtb, say to fix a bug, it's reasonable to
> use the newest one for a given board.  After all, any new nodes won't
> change anything, since the driver in the kernel won't match the node.
> 
> However, in this case, without this fix, a user upgrading to the newest
> dtb would get a broken system.  So, this fix should be backported to
> prevent the breakage.  Or, have I missed something in my analysis?

This is correct when looking only at this issue. However I suspect such
move would cause a breakage anyway, because DT stuff isn't that stable
on Exynos side. I don't mind if this patch hits stable, though.

Best regards,
Tomasz
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[PATCH v2 2/2] ARM: EXYNOS: Add support for firmware-assisted suspend/resume

[Tomasz Figa]

On a numer of Exynos-based boards Linux kernel is running in non-secure
mode under a secure firmware. This means that certain operations need to
be handled in special way, with firmware assistance. System-wide
suspend/resume is an example of such operations.

This patch adds support for firmware-assisted suspend/resume by
leveraging recently introduced suspend and resume firmware operations
and modifying existing suspend/resume paths to account for presence of
secure firmware.

Signed-off-by: Tomasz Figa 
---
 arch/arm/mach-exynos/Makefile   |  1 +
 arch/arm/mach-exynos/common.h   |  4 
 arch/arm/mach-exynos/firmware.c | 45 +
 arch/arm/mach-exynos/pm.c   | 16 ++-
 arch/arm/mach-exynos/sleep.S| 28 +
 arch/arm/mach-exynos/smc.h  |  4 
 6 files changed, 93 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 788f26d..e7d1774 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -26,6 +26,7 @@ CFLAGS_hotplug.o  += -march=armv7-a
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_exynos-smc.o:=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_sleep.o :=-Wa,-march=armv7-a$(plus_sec)
 
 obj-$(CONFIG_EXYNOS5420_MCPM)  += mcpm-exynos.o
 CFLAGS_mcpm-exynos.o   += -march=armv7-a
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f8daa9c..a3f3061 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -111,6 +111,9 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, 
EXYNOS5_SOC_MASK)
 #define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
  soc_is_exynos5420() || soc_is_exynos5800())
 
+extern u32 cp15_save_diag;
+extern u32 cp15_save_power;
+
 extern void __iomem *sysram_ns_base_addr;
 extern void __iomem *sysram_base_addr;
 extern void __iomem *pmu_base_addr;
@@ -127,6 +130,7 @@ static inline void exynos_pm_init(void) {}
 #endif
 
 extern void exynos_cpu_resume(void);
+extern void exynos_cpu_resume_ns(void);
 
 extern struct smp_operations exynos_smp_ops;
 
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index e8797bb..f5e626d 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -14,13 +14,20 @@
 #include 
 #include 
 
+#include 
+#include 
 #include 
+#include 
 
 #include 
 
 #include "common.h"
 #include "smc.h"
 
+#define EXYNOS_SLEEP_MAGIC 0x0bad
+#define EXYNOS_BOOT_ADDR   0x8
+#define EXYNOS_BOOT_FLAG   0xc
+
 static int exynos_do_idle(void)
 {
exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
@@ -69,10 +76,48 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long 
boot_addr)
return 0;
 }
 
+static int exynos_cpu_suspend(unsigned long arg)
+{
+   flush_cache_all();
+   outer_flush_all();
+
+   exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
+
+   pr_info("Failed to suspend the system\n");
+   writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
+   return 1;
+}
+
+static int exynos_suspend(void)
+{
+   if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
+   /* Save Power control and Diagnostic registers */
+   asm ("mrc p15, 0, %0, c15, c0, 0\n"
+   "mrc p15, 0, %1, c15, c0, 1\n"
+   : "=r" (cp15_save_power), "=r" (cp15_save_diag)
+   : : "cc");
+   }
+
+   writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
+   writel(virt_to_phys(exynos_cpu_resume_ns),
+   sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
+
+   return cpu_suspend(0, exynos_cpu_suspend);
+}
+
+static int exynos_resume(void)
+{
+   writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
+
+   return 0;
+}
+
 static const struct firmware_ops exynos_firmware_ops = {
.do_idle= exynos_do_idle,
.set_cpu_boot_addr  = exynos_set_cpu_boot_addr,
.cpu_boot   = exynos_cpu_boot,
+   .suspend= exynos_suspend,
+   .resume = exynos_resume,
 };
 
 void __init exynos_firmware_init(void)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 63a1d6b..681e894 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -23,6 +23,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -354,12 +355,11 @@ static int exynos_pm_suspend(void)
 
 static void exynos_pm_resume(void)
 {
+   u32 cpuid = read_cpuid_part();
+
if (exynos_pm_central_resume())
goto early_wakeup;
 
-   if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
-   exynos_cpu_restore_register();
-
/* For release retention */
 
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
@@ -376,9 +376,13 @@ static void exynos_pm_resume(void)
 
s3c_pm_do_restor

[PATCH v2 0/2] Firmware-assisted suspend/resume of Exynos SoCs

[Tomasz Figa]

On Exynos-based boards running secure firmware the sequence of low level
operations to enter and leave system-wide sleep mode is different than
on those without the firmware. Namely:
 - CP15 power control and diagnostic registers cannot be written directly,
 - the way of setting boot address and boot flag is different,
 - different resume handler needs to be used,
 - dedicated SMC call needs to be performed instead of letting the CPU enter
   WFI.

This series introduces .suspend() and .resume() firmware operations to
perform low level firmware-specific suspend and resume and then leverages
them to provide suspend-resume path meeting the above requirements.

The series is based on Kgene's for-next branch and tested on:
 - Exynos4412-based Trats2 board running in non-secure mode (under secure
   firmware) with few board-specific fixes that will be sent separately soon,
 - Exynos4210-based Trats board running in secure mode,
 - Exynos4412-based ODROID-U3 board running in non-secure mode with one minor
   board-specific fix which will be send shortly.

Depends on:
 - [PATCH v3] ARM: save/restore Cortex-A9 CP15 registers on suspend/resume
   (http://www.spinics.net/lists/arm-kernel/msg346212.html)
 - [PATCH v3] ARM: EXYNOS: Fix suspend/resume sequences
   (https://lkml.org/lkml/2014/7/15/319)
 - [PATCH] ARM: make it easier to check the CPU part number correctly
   (http://thread.gmane.org/gmane.linux.ports.arm.kernel/335126
already in linux-next)

Changes since v1:
 - dropped outer_resume() - will be handled in assembly in further patches,
   as support for L2C in non-secure mode gets added,
 - moved CP15 resume to assembly as it needs to be done before MMU is enabled,
 - surrounded CP15 save with a check for cpuid part, because it is valid only
   on Cortex A9,
 - rebased on next-20140717 tag of linux-next tree.

Tomasz Figa (2):
  ARM: firmware: Introduce suspend and resume operations
  ARM: EXYNOS: Add support for firmware-assisted suspend/resume

 Documentation/arm/firmware.txt  | 28 +
 arch/arm/include/asm/firmware.h |  8 
 arch/arm/mach-exynos/Makefile   |  1 +
 arch/arm/mach-exynos/common.h   |  4 
 arch/arm/mach-exynos/firmware.c | 45 +
 arch/arm/mach-exynos/pm.c   | 16 ++-
 arch/arm/mach-exynos/sleep.S| 28 +
 arch/arm/mach-exynos/smc.h  |  4 
 8 files changed, 106 insertions(+), 28 deletions(-)

-- 
1.9.3

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Re: [PATCH] irqchip: gic: Fix core ID calculation when topology is read from DT

[Jason Cooper]

On Thu, Jul 17, 2014 at 05:40:50PM +0200, Tomasz Figa wrote:
> Hi Jason,
> 
> On 17.07.2014 17:32, Jason Cooper wrote:
> > On Thu, Jul 17, 2014 at 05:23:44PM +0200, Tomasz Figa wrote:
> >> Certain GIC implementation, namely those found on earlier, single
> >> cluster, Exynos SoCs, have registers mapped without per-CPU banking,
> >> which means that the driver needs to use different offset for each CPU.
> >>
> >> Currently the driver calculates the offset by multiplying value returned
> >> by cpu_logical_map() by CPU offset parsed from DT. This is correct when
> >> CPU topology is not specified in DT and aforementioned function returns
> >> core ID alone. However when DT contains CPU topology, the function
> >> changes to return cluster ID as well, which is non-zero on mentioned
> >> SoCs and so breaks the calculation in GIC driver.
> >>
> >> This patch fixes this by masking out cluster ID in CPU offset
> >> calculation so that only core ID is considered. Multi-cluster Exynos
> >> SoCs already have banked GIC implementations, so this simple fix should
> >> be enough.
> >>
> >> Reported-by: Lorenzo Pieralisi 
> >> Reported-by: Bartlomiej Zolnierkiewicz 
> >> Signed-off-by: Tomasz Figa 
> >> ---
> >>  drivers/irqchip/irq-gic.c | 5 -
> >>  1 file changed, 4 insertions(+), 1 deletion(-)
> > 
> > iiuc, this was introduced by:
> > 
> >   db0d4db22a78d ARM: gic: allow GIC to support non-banked setups
> > 
> > and so should be for v3.3 and up, correct?
> 
> Could be, although there was and still is no topology data specified in
> DT for affected Exynos SoCs. The need for it showed up just recently, so
> I'm not sure this is a regression to fix in older kernels.

In my "the kernel and the dtb aren't tied together" quest, these are the
kinds of things I like to see fixed in stable kernels.

If a user needs to update a dtb, say to fix a bug, it's reasonable to
use the newest one for a given board.  After all, any new nodes won't
change anything, since the driver in the kernel won't match the node.

However, in this case, without this fix, a user upgrading to the newest
dtb would get a broken system.  So, this fix should be backported to
prevent the breakage.  Or, have I missed something in my analysis?

thx,

Jason.
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Re: [PATCH] irqchip: gic: Fix core ID calculation when topology is read from DT

[Tomasz Figa]

Hi Jason,

On 17.07.2014 17:32, Jason Cooper wrote:
> On Thu, Jul 17, 2014 at 05:23:44PM +0200, Tomasz Figa wrote:
>> Certain GIC implementation, namely those found on earlier, single
>> cluster, Exynos SoCs, have registers mapped without per-CPU banking,
>> which means that the driver needs to use different offset for each CPU.
>>
>> Currently the driver calculates the offset by multiplying value returned
>> by cpu_logical_map() by CPU offset parsed from DT. This is correct when
>> CPU topology is not specified in DT and aforementioned function returns
>> core ID alone. However when DT contains CPU topology, the function
>> changes to return cluster ID as well, which is non-zero on mentioned
>> SoCs and so breaks the calculation in GIC driver.
>>
>> This patch fixes this by masking out cluster ID in CPU offset
>> calculation so that only core ID is considered. Multi-cluster Exynos
>> SoCs already have banked GIC implementations, so this simple fix should
>> be enough.
>>
>> Reported-by: Lorenzo Pieralisi 
>> Reported-by: Bartlomiej Zolnierkiewicz 
>> Signed-off-by: Tomasz Figa 
>> ---
>>  drivers/irqchip/irq-gic.c | 5 -
>>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> iiuc, this was introduced by:
> 
>   db0d4db22a78d ARM: gic: allow GIC to support non-banked setups
> 
> and so should be for v3.3 and up, correct?

Could be, although there was and still is no topology data specified in
DT for affected Exynos SoCs. The need for it showed up just recently, so
I'm not sure this is a regression to fix in older kernels.

Best regards,
Tomasz
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Re: [RESEND PATCH v3] charger: tps65090: Allow charger module to be used when no irq

[Javier Martinez Canillas]

Hello Doug,

On 06/20/2014 11:42 PM, Doug Anderson wrote:
> On the ARM Chromebook tps65090 has two masters: the AP (the main
> processor running linux) and the EC (the embedded controller).  The AP
> is allowed to mess with FETs but the EC is in charge of charge control.
> 
> The tps65090 interupt line is routed to both the AP and the EC, which
> can cause quite a headache.  Having two people adjusting masks and
> acking interrupts is a recipe for disaster.
> 
> In the shipping kernel we had a hack to have the AP pay attention to
> the IRQ but not to ack it.  It also wasn't supposed to configure the
> IRQ in any way.  That hack allowed us to detect when the device was
> charging without messing with the EC's state.
> 
> The current tps65090 infrastructure makes the above difficult, and it
> was a bit of a hack to begin with.  Rather than uglify the driver to
> support it, just extend the driver's existing notion of "no irq" to
> the charger.  This makes the charger code poll every 2 seconds for AC
> detect, which is sufficient.
> 
> For proper functioning, requires (mfd: tps65090: Don't tell child
> devices we have an IRQ if we don't).  If we don't have that patch
> we'll simply fail to probe on devices without an interrupt (just like
> we did before this patch).
> 
> Signed-off-by: Doug Anderson 
> ---
> Changes in v2:
> - Split noirq (polling mode) changes into MFD and charger
> 
> This patch has been sent up a number of times with no response.  It's
> needed to make the charger work on exynos5250-snow,
> exynos5420-peach-pit, and exynos5800-peach-pi.  It was originally part
> of a series as  and the
> rest of the series has long since landed.
> 

Looks good to me. Also since this patch makes optional to get an IRQ, the
following annoying message is not shown anymore:

[2.132944] tps65090-charger tps65090-charger: Unable to get charger irq = -6

Reviewed-by: Javier Martinez Canillas 
Tested-by: Javier Martinez Canillas 
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Re: [PATCH] irqchip: gic: Fix core ID calculation when topology is read from DT

[Jason Cooper]

On Thu, Jul 17, 2014 at 05:23:44PM +0200, Tomasz Figa wrote:
> Certain GIC implementation, namely those found on earlier, single
> cluster, Exynos SoCs, have registers mapped without per-CPU banking,
> which means that the driver needs to use different offset for each CPU.
> 
> Currently the driver calculates the offset by multiplying value returned
> by cpu_logical_map() by CPU offset parsed from DT. This is correct when
> CPU topology is not specified in DT and aforementioned function returns
> core ID alone. However when DT contains CPU topology, the function
> changes to return cluster ID as well, which is non-zero on mentioned
> SoCs and so breaks the calculation in GIC driver.
> 
> This patch fixes this by masking out cluster ID in CPU offset
> calculation so that only core ID is considered. Multi-cluster Exynos
> SoCs already have banked GIC implementations, so this simple fix should
> be enough.
> 
> Reported-by: Lorenzo Pieralisi 
> Reported-by: Bartlomiej Zolnierkiewicz 
> Signed-off-by: Tomasz Figa 
> ---
>  drivers/irqchip/irq-gic.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)

iiuc, this was introduced by:

  db0d4db22a78d ARM: gic: allow GIC to support non-banked setups

and so should be for v3.3 and up, correct?

thx,

Jason.
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[PATCH] irqchip: gic: Fix core ID calculation when topology is read from DT

[Tomasz Figa]

Certain GIC implementation, namely those found on earlier, single
cluster, Exynos SoCs, have registers mapped without per-CPU banking,
which means that the driver needs to use different offset for each CPU.

Currently the driver calculates the offset by multiplying value returned
by cpu_logical_map() by CPU offset parsed from DT. This is correct when
CPU topology is not specified in DT and aforementioned function returns
core ID alone. However when DT contains CPU topology, the function
changes to return cluster ID as well, which is non-zero on mentioned
SoCs and so breaks the calculation in GIC driver.

This patch fixes this by masking out cluster ID in CPU offset
calculation so that only core ID is considered. Multi-cluster Exynos
SoCs already have banked GIC implementations, so this simple fix should
be enough.

Reported-by: Lorenzo Pieralisi 
Reported-by: Bartlomiej Zolnierkiewicz 
Signed-off-by: Tomasz Figa 
---
 drivers/irqchip/irq-gic.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index ddee133..5c15a09 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -40,6 +40,7 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
@@ -901,7 +902,9 @@ void __init gic_init_bases(unsigned int gic_nr, int 
irq_start,
}
 
for_each_possible_cpu(cpu) {
-   unsigned long offset = percpu_offset * 
cpu_logical_map(cpu);
+   u32 mpidr = cpu_logical_map(cpu);
+   u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   unsigned long offset = percpu_offset * core_id;
*per_cpu_ptr(gic->dist_base.percpu_base, cpu) = 
dist_base + offset;
*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base 
+ offset;
}
-- 
1.9.3

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[PATCH v2 4/5] i2c: sc3c2410: Remove suspension check

[Bastian Hecht]

We now take care of suspension in the i2c core code. So we can remove this
check here.

Signed-off-by: Bastian Hecht 
---
same as v1

 drivers/i2c/busses/i2c-s3c2410.c | 16 
 1 file changed, 16 deletions(-)

diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index e828a1d..568b993 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -103,7 +103,6 @@ enum s3c24xx_i2c_state {
 struct s3c24xx_i2c {
wait_queue_head_t   wait;
kernel_ulong_t  quirks;
-   unsigned intsuspended:1;
 
struct i2c_msg  *msg;
unsigned intmsg_num;
@@ -714,9 +713,6 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
unsigned long timeout;
int ret;
 
-   if (i2c->suspended)
-   return -EIO;
-
ret = s3c24xx_i2c_set_master(i2c);
if (ret != 0) {
dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
@@ -1257,16 +1253,6 @@ static int s3c24xx_i2c_remove(struct platform_device 
*pdev)
 }
 
 #ifdef CONFIG_PM_SLEEP
-static int s3c24xx_i2c_suspend_noirq(struct device *dev)
-{
-   struct platform_device *pdev = to_platform_device(dev);
-   struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
-
-   i2c->suspended = 1;
-
-   return 0;
-}
-
 static int s3c24xx_i2c_resume(struct device *dev)
 {
struct platform_device *pdev = to_platform_device(dev);
@@ -1275,7 +1261,6 @@ static int s3c24xx_i2c_resume(struct device *dev)
clk_prepare_enable(i2c->clk);
s3c24xx_i2c_init(i2c);
clk_disable_unprepare(i2c->clk);
-   i2c->suspended = 0;
 
return 0;
 }
@@ -1284,7 +1269,6 @@ static int s3c24xx_i2c_resume(struct device *dev)
 #ifdef CONFIG_PM
 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
 #ifdef CONFIG_PM_SLEEP
-   .suspend_noirq = s3c24xx_i2c_suspend_noirq,
.resume = s3c24xx_i2c_resume,
 #endif
 };
-- 
1.9.1

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[PATCH v3 3/5] i2c: exynos5: Remove suspension check

[Bastian Hecht]

We now take care of suspension in the i2c core code. So we can remove this
check here.

Signed-off-by: Bastian Hecht 
---
same as v1

 drivers/i2c/busses/i2c-exynos5.c | 20 +---
 1 file changed, 1 insertion(+), 19 deletions(-)

diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index 63d2292..a80cf28 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -145,7 +145,6 @@
 
 struct exynos5_i2c {
struct i2c_adapter  adap;
-   unsigned intsuspended:1;
 
struct i2c_msg  *msg;
struct completion   msg_complete;
@@ -610,11 +609,6 @@ static int exynos5_i2c_xfer(struct i2c_adapter *adap,
struct exynos5_i2c *i2c = adap->algo_data;
int i = 0, ret = 0, stop = 0;
 
-   if (i2c->suspended) {
-   dev_err(i2c->dev, "HS-I2C is not initialized.\n");
-   return -EIO;
-   }
-
clk_prepare_enable(i2c->clk);
 
for (i = 0; i < num; i++, msgs++) {
@@ -757,16 +751,6 @@ static int exynos5_i2c_remove(struct platform_device *pdev)
 }
 
 #ifdef CONFIG_PM_SLEEP
-static int exynos5_i2c_suspend_noirq(struct device *dev)
-{
-   struct platform_device *pdev = to_platform_device(dev);
-   struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
-
-   i2c->suspended = 1;
-
-   return 0;
-}
-
 static int exynos5_i2c_resume_noirq(struct device *dev)
 {
struct platform_device *pdev = to_platform_device(dev);
@@ -783,14 +767,12 @@ static int exynos5_i2c_resume_noirq(struct device *dev)
 
exynos5_i2c_init(i2c);
clk_disable_unprepare(i2c->clk);
-   i2c->suspended = 0;
 
return 0;
 }
 #endif
 
-static SIMPLE_DEV_PM_OPS(exynos5_i2c_dev_pm_ops, exynos5_i2c_suspend_noirq,
-exynos5_i2c_resume_noirq);
+static SIMPLE_DEV_PM_OPS(exynos5_i2c_dev_pm_ops, exynos5_i2c_resume_noirq);
 
 static struct platform_driver exynos5_i2c_driver = {
.probe  = exynos5_i2c_probe,
-- 
1.9.1

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Re: [PATCH v3] ARM: EXYNOS: Fix suspend/resume sequences

[Tomasz Figa]

Hi Kukjin,

On 15.07.2014 16:26, Tomasz Figa wrote:
> Forgot to CC Daniel and linux-pm. Sorry for the noise.
> 
> On 15.07.2014 16:24, Tomasz Figa wrote:
>> Due to recent consolidation of Exynos suspend and cpuidle code, some
>> parts of suspend and resume sequences are executed two times, once from
>> exynos_pm_syscore_ops and then from exynos_cpu_pm_notifier() and thus it
>> breaks suspend, at least on Exynos4-based boards. In addition, simple
>> core power down from a cpuidle driver could, in case of CPU 0 could
>> result in calling functions that are specific to suspend and deeper idle
>> states.
>>
>> This patch fixes the issue by moving those operations outside the CPU PM
>> notifier into suspend and AFTR code paths. This leads to a bit of code
>> duplication, but allows additional code simplification, so in the end
>> more code is removed than added.
>>
>> Signed-off-by: Tomasz Figa 
>> ---
>>  arch/arm/mach-exynos/pm.c| 164 
>> ++-
>>  drivers/cpuidle/cpuidle-exynos.c |  25 +-
>>  2 files changed, 80 insertions(+), 109 deletions(-)
>>

Please consider this patch for next pull request with rc fixes. It
replaces following patches posted in this thread:

[PATCH 5/6] ARM: EXYNOS: Fix suspend/resume sequencies
[PATCH v2 5/6] ARM: EXYNOS: Fix suspend/resume sequences

and also similar patch by Chander:

[PATCH 2/2] cpuidle: Exynos: fix cpuidle for all states

Best regards,
Tomasz
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Re: [PATCH 0/4 v2] hwmon: ntc_thermistor: prepose vendor prefix change

[Javier Martinez Canillas]

Hello Naveen,

On Thu, Jul 17, 2014 at 6:21 AM, Naveen Krishna Ch
 wrote:
>
> Can you pull the 3/4 and 4/4 patches.
>

Patch 4/4 depends on the max77802 support series [0] since the ADC
uses the max77802 ldo9 regulator as its voltage supply. So that patch
can't be merged before the series land in mainline.

Best regards,
Javier

[0]: https://lkml.org/lkml/2014/7/14/273
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Re: [PATCH 1/4 v2] iio: exyno-adc: use syscon for PMU register access

[Bartlomiej Zolnierkiewicz]

Hi,

On Thursday, July 17, 2014 05:41:16 PM Naveen Krishna Ch wrote:
> Hello Sachin,
> 
> On 17 July 2014 17:24, Sachin Kamat  wrote:
> > Hi Naveen,
> >
> > On Thu, Jul 17, 2014 at 4:49 PM, Naveen Krishna Chatradhi
> >  wrote:
> >> This patch updates the IIO based ADC driver to use syscon and regmap
> >> APIs to access and use PMU registers instead of remapping the PMU
> >> registers in the driver.
> >>
> >> Signed-off-by: Naveen Krishna Chatradhi 
> >> To: linux-...@vger.kernel.org
> >
> > With only this patch applied, I believe the ADC functionality would be 
> > broken.
> > Perhaps the DT changes should be merged along with this patch?
> 
> Jonathan already mentioned that, he would wait for Ack from Kukjin.
> With out the dts changes ADC driver will fail to probe but it wont
> crash the system.
> git bisect should still work.

Unless someone bisects things related to ADC functionality..

Also patch #1 seems to break device tree ABI (the old dtb will no longer
work with the new kernel).

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

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Re: [PATCH 1/3] ARM: EXYNOS: Move code from hotplug.c to platsmp.c

[Tomasz Figa]

Hi Krzysztof,

On 16.07.2014 16:20, Krzysztof Kozlowski wrote:
> Cleanup a little the SMP/hotplug code for Exynos by:
> 1. Moving completely all functions from hotplug.c into the platsmp.c;
> 2. Deleting the hotplug.c file.
> 
> After recent cleanups (e.g. 75ad2ab28f0f "ARM: EXYNOS: use
> v7_exit_coherency_flush macro for cache disabling") there was only CPU
> power down related code in hotplug.c file. Keeping this file does not
> give any benefits.
> 
> The commit only moves code around with one additional observable change:
> the hotplug.c was compiled with custom CFLAGS (-march=armv7-a). These
> CFLAGS are not necessary any more.
> 
> Signed-off-by: Krzysztof Kozlowski 
> ---
>  arch/arm/mach-exynos/Makefile  |  3 --
>  arch/arm/mach-exynos/common.h  |  2 -
>  arch/arm/mach-exynos/hotplug.c | 92 
> --
>  arch/arm/mach-exynos/platsmp.c | 74 +
>  4 files changed, 74 insertions(+), 97 deletions(-)
>  delete mode 100644 arch/arm/mach-exynos/hotplug.c
> 

For this and remaining patches from this series:

Reviewed-by: Tomasz Figa 

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Re: [PATCH 1/4 v2] iio: exyno-adc: use syscon for PMU register access

[Naveen Krishna Ch]

Hello Sachin,

On 17 July 2014 17:24, Sachin Kamat  wrote:
> Hi Naveen,
>
> On Thu, Jul 17, 2014 at 4:49 PM, Naveen Krishna Chatradhi
>  wrote:
>> This patch updates the IIO based ADC driver to use syscon and regmap
>> APIs to access and use PMU registers instead of remapping the PMU
>> registers in the driver.
>>
>> Signed-off-by: Naveen Krishna Chatradhi 
>> To: linux-...@vger.kernel.org
>
> With only this patch applied, I believe the ADC functionality would be broken.
> Perhaps the DT changes should be merged along with this patch?

Jonathan already mentioned that, he would wait for Ack from Kukjin.
With out the dts changes ADC driver will fail to probe but it wont
crash the system.
git bisect should still work.

>
> --
> Regards,
> Sachin.



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Re: [PATCH 1/4 v2] iio: exyno-adc: use syscon for PMU register access

[Sachin Kamat]

Hi Naveen,

On Thu, Jul 17, 2014 at 4:49 PM, Naveen Krishna Chatradhi
 wrote:
> This patch updates the IIO based ADC driver to use syscon and regmap
> APIs to access and use PMU registers instead of remapping the PMU
> registers in the driver.
>
> Signed-off-by: Naveen Krishna Chatradhi 
> To: linux-...@vger.kernel.org

With only this patch applied, I believe the ADC functionality would be broken.
Perhaps the DT changes should be merged along with this patch?

-- 
Regards,
Sachin.
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Re: [PATCH 0/4] iio: exynos-adc: use syscon instead of ioremap

[Naveen Krishna Ch]

Hello Jonathan,

On 15 July 2014 23:45, Jonathan Cameron  wrote:
> On 15/07/14 19:13, Jonathan Cameron wrote:
>>
>> On 11/07/14 10:06, Naveen Krishna Chatradhi wrote:
>>>
>>> This patch does the following
>>> 1. Use the syscon and Regmap API instead of ioremappaing the
>>> ADC_PHY register from PMU.
>>> 2. Moves the exynos-adc.txt from bindings/arm/samsung/
>>> to bindings/iio/adc/.
>>> 3. Updates the Documentation in exynos-adc.txt with syscon phandle
>>> for the ADC nodes.
>>> 4. Updates the Dts files for Exynos3250, Exynos4x12, Exynos5250,
>>> Exynos5420 with the syscon phandle.
>>>
>>> Tested on Exynos5420 based Peach PIT and Exynos5800 based Peach PI
>>> by verifying sysfs entries provided by HWMON based NTC thermistors.
>>>
>>> Tested-By for Exynos3250, Exynos4x12 would be appreciated.
>>>
>> This series all looks fine to me.  Took me a minute to work out what the
>> point
>> of the syscon change was (perhaps a little description in the cover letter
>> would have been nice ;)
>>
>> Anyhow, with the device tree changes in here we'll have to let it sit for
>> a while.  I'll also definitely want an ack from
>> Kukjin Kim  for the device tree changes.
>
> Although I haven't tried it, I'd imagine this might cause a little bit
> of merging fun with the other exynos series waiting for Kukjin to
> ack...

I've tried to rebase on top of Chongwoo's v5 version changes for Exynos5320.
there is one conflict with Documentation. I've submitted the v2 version.

> [PATCHv5 0/4] iio: adc: exynos_adc: Support Exynos3250 ADC and code clean
>>
>>
>> Jonathan
>>>
>>> Naveen Krishna Chatradhi (4):
>>>iio: exyno-adc: use syscon for PMU register access
>>>Documentation: dt-bindings: move exynos-adc.txt to more iio/adc/
>>>Documentation: dt-bindings: update exynos-adc.txt with syscon handle
>>>ARM: dts: exynos: Add sysreg phandle to ADC node
>>>
>>>   .../devicetree/bindings/arm/samsung/exynos-adc.txt |   82
>>> --
>>>   .../devicetree/bindings/iio/adc/exynos-adc.txt |   87
>>> 
>>>   arch/arm/boot/dts/exynos3250.dtsi  |3 +-
>>>   arch/arm/boot/dts/exynos4x12.dtsi  |3 +-
>>>   arch/arm/boot/dts/exynos5250.dtsi  |3 +-
>>>   arch/arm/boot/dts/exynos5420.dtsi  |3 +-
>>>   drivers/iio/adc/exynos_adc.c   |   29 +--
>>>   7 files changed, 115 insertions(+), 95 deletions(-)
>>>   delete mode 100644
>>> Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
>>>   create mode 100644
>>> Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
>>>
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>



-- 
Regards,
(: Naveen :)
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[PATCH 1/4 v2] iio: exyno-adc: use syscon for PMU register access

[Naveen Krishna Chatradhi]

This patch updates the IIO based ADC driver to use syscon and regmap
APIs to access and use PMU registers instead of remapping the PMU
registers in the driver.

Signed-off-by: Naveen Krishna Chatradhi 
To: linux-...@vger.kernel.org
---
Changes since v1:
None

 drivers/iio/adc/exynos_adc.c |   29 -
 1 file changed, 20 insertions(+), 9 deletions(-)

diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index b63e882..60847ef 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -38,6 +38,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 /* EXYNOS4412/5250 ADC_V1 registers definitions */
 #define ADC_V1_CON(x)  ((x) + 0x00)
@@ -79,11 +81,14 @@
 
 #define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
 
+#define EXYNOS_ADCV1_PHY_OFFSET0x0718
+#define EXYNOS_ADCV2_PHY_OFFSET0x0720
+
 struct exynos_adc {
struct exynos_adc_data  *data;
struct device   *dev;
void __iomem*regs;
-   void __iomem*enable_reg;
+   struct regmap   *pmu_map;
struct clk  *clk;
struct clk  *sclk;
unsigned intirq;
@@ -98,6 +103,7 @@ struct exynos_adc {
 struct exynos_adc_data {
int num_channels;
bool needs_sclk;
+   int phy_offset;
 
void (*init_hw)(struct exynos_adc *info);
void (*exit_hw)(struct exynos_adc *info);
@@ -169,7 +175,7 @@ static void exynos_adc_v1_init_hw(struct exynos_adc *info)
 {
u32 con1;
 
-   writel(1, info->enable_reg);
+   regmap_write(info->pmu_map, info->data->phy_offset, 1);
 
/* set default prescaler values and Enable prescaler */
con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
@@ -183,7 +189,7 @@ static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
 {
u32 con;
 
-   writel(0, info->enable_reg);
+   regmap_write(info->pmu_map, info->data->phy_offset, 0);
 
con = readl(ADC_V1_CON(info->regs));
con |= ADC_V1_CON_STANDBY;
@@ -208,6 +214,7 @@ static void exynos_adc_v1_start_conv(struct exynos_adc 
*info,
 
 static struct exynos_adc_data const exynos_adc_v1_data = {
.num_channels   = MAX_ADC_V1_CHANNELS,
+   .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
 
.init_hw= exynos_adc_v1_init_hw,
.exit_hw= exynos_adc_v1_exit_hw,
@@ -219,7 +226,7 @@ static void exynos_adc_v2_init_hw(struct exynos_adc *info)
 {
u32 con1, con2;
 
-   writel(1, info->enable_reg);
+   regmap_write(info->pmu_map, info->data->phy_offset, 1);
 
con1 = ADC_V2_CON1_SOFT_RESET;
writel(con1, ADC_V2_CON1(info->regs));
@@ -236,7 +243,7 @@ static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
 {
u32 con;
 
-   writel(0, info->enable_reg);
+   regmap_write(info->pmu_map, info->data->phy_offset, 0);
 
con = readl(ADC_V2_CON1(info->regs));
con &= ~ADC_CON_EN_START;
@@ -271,10 +278,12 @@ static void exynos_adc_v2_start_conv(struct exynos_adc 
*info,
 
 static struct exynos_adc_data const exynos_adc_v2_data = {
__EXYNOS_ADC_V2_DATA
+   .phy_offset = EXYNOS_ADCV2_PHY_OFFSET,
 };
 
 static struct exynos_adc_data const exynos3250_adc_v2_data = {
__EXYNOS_ADC_V2_DATA
+   .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.needs_sclk = true,
 };
 
@@ -437,10 +446,12 @@ static int exynos_adc_probe(struct platform_device *pdev)
if (IS_ERR(info->regs))
return PTR_ERR(info->regs);
 
-   mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-   info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
-   if (IS_ERR(info->enable_reg))
-   return PTR_ERR(info->enable_reg);
+   info->pmu_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+   "samsung,syscon-phandle");
+   if (IS_ERR(info->pmu_map)) {
+   dev_err(&pdev->dev, "syscon regmap lookup failed.\n");
+   return PTR_ERR(info->pmu_map);
+   }
 
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
-- 
1.7.9.5

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[PATCH 3/4 v2] Documentation: dt-bindings: update exynos-adc.txt with syscon handle

[Naveen Krishna Chatradhi]

This patch updates the DT bindings in exynos-adc.txt with the
syscon phandle to the ADC nodes.

Also removes the 2nd "reg" property, which used to carry the
ADC_PHY regiser base from PMU.

Signed-off-by: Naveen Krishna Chatradhi 
To: devicet...@vger.kernel.org
---
Changes since v1:
rebased on top of Changwoo's v5 ADC patches for exynos3250

iio: adc: exynos_adc: Support Exynos3250 ADC and code clean
https://lkml.org/lkml/2014/6/27/16

 .../devicetree/bindings/iio/adc/exynos-adc.txt |   15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt 
b/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
index 0b0ed85..1634df3 100644
--- a/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
@@ -1,10 +1,11 @@
 Samsung Exynos Analog to Digital Converter bindings
 
 The devicetree bindings are for the new ADC driver written for
-Exynos4 and upward SoCs from Samsung.
+Exynos4 and Exynos5 series SoCs from Samsung.
+Now supports Exynos3250 too.
 
 New driver handles the following
-1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
+1. Supports ADC IF found on Exynos3250/EXYNOS4412/EXYNOS5 series
and future SoCs from Samsung
 2. Add ADC driver under iio/adc framework
 3. Also adds the Documentation for device tree bindings
@@ -18,7 +19,7 @@ Required properties:
for controllers compatible with ADC of
Exynos3250.
 - reg: Contains ADC register address range (base address and
-   length) and the address of the phy enable register.
+   length)
 - interrupts:  Contains the interrupt information for the timer. The
format is being dependent on which interrupt controller
the Samsung device uses.
@@ -31,6 +32,8 @@ Required properties:
- "sclk_adc" : ADC special clock (only for Exynos3250
   and compatible ADC block)
 - vdd-supply   VDD input supply.
+- samsung,syscon-phandle Contains the PMU system controller node
+   (To access the ADC_PHY register)
 
 Note: child nodes can be added for auto probing from device tree.
 
@@ -38,7 +41,7 @@ Example: adding device info in dtsi file
 
 adc: adc@12D1 {
compatible = "samsung,exynos-adc-v1";
-   reg = <0x12D1 0x100>, <0x10040718 0x4>;
+   reg = <0x12D1 0x100>;
interrupts = <0 106 0>;
#io-channel-cells = <1>;
io-channel-ranges;
@@ -47,13 +50,14 @@ adc: adc@12D1 {
clock-names = "adc";
 
vdd-supply = <&buck5_reg>;
+   samsung,syscon-phandle = <&pmu_system_controller>;
 };
 
 Example: adding device info in dtsi file for Exynos3250 with additional sclk
 
 adc: adc@126C {
compatible = "samsung,exynos3250-adc-v2";
-   reg = <0x126C 0x100>, <0x10020718 0x4>;
+   reg = <0x126C 0x100>;
interrupts = <0 137 0>;
#io-channel-cells = <1>;
io-channel-ranges;
@@ -62,6 +66,7 @@ adc: adc@126C {
clock-names = "adc", "sclk_adc";
 
vdd-supply = <&buck5_reg>;
+   samsung,syscon-phandle = <&pmu_system_controller>;
 };
 
 Example: Adding child nodes in dts file
-- 
1.7.9.5

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[PATCH 2/4 v2] Documentation: dt-bindings: move exynos-adc.txt to more iio/adc/

[Naveen Krishna Chatradhi]

The DT bindings in exynos-adc.txt applies to the ADC
driver (exynos-adc.c) developed based on IIO framework.

The bindings are more appropriate to be under
Documentation/devicetree/bindings/iio/adc/

Signed-off-by: Naveen Krishna Chatradhi 
To: devicet...@vger.kernel.org
---
Changes since v1:
Use git format-patch -M to reduce the patch size

 .../{arm/samsung => iio/adc}/exynos-adc.txt|0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename Documentation/devicetree/bindings/{arm/samsung => 
iio/adc}/exynos-adc.txt (100%)

diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt 
b/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
rename to Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
-- 
1.7.9.5

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[PATCH 4/4 v2] ARM: dts: exynos: Add sysreg phandle to ADC node

[Naveen Krishna Chatradhi]

Instead of using the ADC_PHY register base address, use sysreg phandle
in ADC node to control ADC_PHY configuration register.

This patch adds syscon node for Exynos3250, Exynos4x12, Exynos5250,
and Exynos5420, Exynos5800.

Signed-off-by: Naveen Krishna Chatradhi 
To: linux-samsung-soc@vger.kernel.org
---
Changes since v1:
None

 arch/arm/boot/dts/exynos3250.dtsi |3 ++-
 arch/arm/boot/dts/exynos4x12.dtsi |3 ++-
 arch/arm/boot/dts/exynos5250.dtsi |3 ++-
 arch/arm/boot/dts/exynos5420.dtsi |3 ++-
 4 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/exynos3250.dtsi 
b/arch/arm/boot/dts/exynos3250.dtsi
index c5e15db..51c9b0d 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -262,12 +262,13 @@
 
adc: adc@126C {
compatible = "samsung,exynos3250-adc-v2";
-   reg = <0x126C 0x100>, <0x10020718 0x4>;
+   reg = <0x126C 0x100>;
interrupts = <0 137 0>;
clock-names = "adc", "sclk_adc";
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
#io-channel-cells = <1>;
io-channel-ranges;
+   samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
};
 
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi 
b/arch/arm/boot/dts/exynos4x12.dtsi
index c5a943d..9a18d9b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -114,13 +114,14 @@
 
adc: adc@126C {
compatible = "samsung,exynos-adc-v1";
-   reg = <0x126C 0x100>, <0x10020718 0x4>;
+   reg = <0x126C 0x100>;
interrupt-parent = <&combiner>;
interrupts = <10 3>;
clocks = <&clock CLK_TSADC>;
clock-names = "adc";
#io-channel-cells = <1>;
io-channel-ranges;
+   samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
};
 
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 834fb5a..6003777 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -762,12 +762,13 @@
 
adc: adc@12D1 {
compatible = "samsung,exynos-adc-v1";
-   reg = <0x12D1 0x100>, <0x10040718 0x4>;
+   reg = <0x12D1 0x100>
interrupts = <0 106 0>;
clocks = <&clock CLK_ADC>;
clock-names = "adc";
#io-channel-cells = <1>;
io-channel-ranges;
+   samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
};
 
diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index e385322..6979da8 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -525,12 +525,13 @@
 
adc: adc@12D1 {
compatible = "samsung,exynos-adc-v2";
-   reg = <0x12D1 0x100>, <0x10040720 0x4>;
+   reg = <0x12D1 0x100>;
interrupts = <0 106 0>;
clocks = <&clock CLK_TSADC>;
clock-names = "adc";
#io-channel-cells = <1>;
io-channel-ranges;
+   samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
};
 
-- 
1.7.9.5

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[PATCH 0/4 v2] iio: exynos-adc: use syscon instead of ioremap

[Naveen Krishna Chatradhi]

Syscon is a regmap based framework to help various drivers access misc
bits in registers which does not belong to another module.
For example, Power Module, SYSREGs.

With syscon, ADC can use generic regmap API to access
registers of PMU which are registered into syscon.
 
This patch does the following
1. Use the syscon and Regmap API instead of ioremappaing the
   ADC_PHY register from PMU.
2. Moves the exynos-adc.txt from bindings/arm/samsung/
   to bindings/iio/adc/.
3. Updates the Documentation in exynos-adc.txt with syscon phandle
   for the ADC nodes.
4. Updates the Dts files for Exynos3250, Exynos4x12, Exynos5250,
   Exynos5420 with the syscon phandle.

Tested on Exynos5420 based Peach PIT and Exynos5800 based Peach PI
by verifying sysfs entries provided by HWMON based NTC thermistors.

Tested-By for Exynos3250, Exynos4x12 would be appreciated.

Changes since v1:
Adding syscon description in commit message

Rebased on top of v5 version of ADC for exynos3250 from Changwoo.
iio: adc: exynos_adc: Support Exynos3250 ADC and code clean
https://lkml.org/lkml/2014/6/27/16

Naveen Krishna Chatradhi (4):
  iio: exyno-adc: use syscon for PMU register access
  Documentation: dt-bindings: move exynos-adc.txt to more iio/adc/
  Documentation: dt-bindings: update exynos-adc.txt with syscon handle
  ARM: dts: exynos: Add sysreg phandle to ADC node

 .../devicetree/bindings/arm/samsung/exynos-adc.txt |   82 --
 .../devicetree/bindings/iio/adc/exynos-adc.txt |   87 
 arch/arm/boot/dts/exynos3250.dtsi  |3 +-
 arch/arm/boot/dts/exynos4x12.dtsi  |3 +-
 arch/arm/boot/dts/exynos5250.dtsi  |3 +-
 arch/arm/boot/dts/exynos5420.dtsi  |3 +-
 drivers/iio/adc/exynos_adc.c   |   29 +--
 7 files changed, 115 insertions(+), 95 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
 create mode 100644 Documentation/devicetree/bindings/iio/adc/exynos-adc.txt

-- 
1.7.9.5

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Re: [PATCH v6 10/14] drm/panel: add S6E3FA0 driver

[Thierry Reding]

On Thu, Jul 17, 2014 at 06:01:25PM +0900, YoungJun Cho wrote:
[...]
> diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c 
> b/drivers/gpu/drm/panel/panel-s6e3fa0.c
[...]
> +/* Manufacturer Command Set */
> +#define MCS_GLOBAL_PARAMETER 0xb0
> +#define MCS_AID  0xb2
> +#define MCS_ELVSSOPT 0xb6
> +#define MCS_TEMPERATURE_SET  0xb8
> +#define MCS_PENTILE_CTRL 0xc0
> +#define MCS_GAMMA_MODE   0xca
> +#define MCS_VDDM 0xd7
> +#define MCS_ALS  0xe3
> +#define MCS_ERR_FG   0xed
> +#define MCS_KEY_LEV1 0xf0
> +#define MCS_GAMMA_UPDATE 0xf7
> +#define MCS_KEY_LEV2 0xfc
> +#define MCS_RE   0xfe
> +#define MCS_TOUT2_HSYNC  0xff
> +
> +/* Content Adaptive Brightness Control */
> +#define DCS_WRITE_CABC   0x55

Is this not a manufacturer specific command? I couldn't find it in the
DSI or DCS specifications, but it sounds like something standard (also
indicated by the DCS_ prefix). Can you point out the specification for
this?

> +#define MTP_ID_LEN   3
> +#define GAMMA_LEVEL_NUM  30
> +
> +#define DEFAULT_VDDM_VAL 0x15
> +
> +struct s6e3fa0 {
> + struct device   *dev;
> + struct drm_panelpanel;
> +
> + struct regulator_bulk_data  supplies[2];
> + struct gpio_desc*reset_gpio;
> + struct videomodevm;
> +
> + unsigned intpower_on_delay;
> + unsigned intreset_delay;
> + unsigned intinit_delay;
> + unsigned intwidth_mm;
> + unsigned intheight_mm;
> +
> + unsigned char   id;
> + unsigned char   vddm;
> + unsigned intbrightness;
> +};

Please don't use this kind of artificial padding. A simple space will
do.

> +
> +#define panel_to_s6e3fa0(p) container_of(p, struct s6e3fa0, panel)

Please turn this into a function so we can get proper type checking.

> +
> +/* VDD Memory Lookup Table contains pairs of {ReadValue, WriteValue} */
> +static const unsigned char s6e3fa0_vddm_lut[][2] = {
> + {0x00, 0x0d}, {0x01, 0x0d}, {0x02, 0x0e}, {0x03, 0x0f}, {0x04, 0x10},
> + {0x05, 0x11}, {0x06, 0x12}, {0x07, 0x13}, {0x08, 0x14}, {0x09, 0x15},
> + {0x0a, 0x16}, {0x0b, 0x17}, {0x0c, 0x18}, {0x0d, 0x19}, {0x0e, 0x1a},
> + {0x0f, 0x1b}, {0x10, 0x1c}, {0x11, 0x1d}, {0x12, 0x1e}, {0x13, 0x1f},
> + {0x14, 0x20}, {0x15, 0x21}, {0x16, 0x22}, {0x17, 0x23}, {0x18, 0x24},
> + {0x19, 0x25}, {0x1a, 0x26}, {0x1b, 0x27}, {0x1c, 0x28}, {0x1d, 0x29},
> + {0x1e, 0x2a}, {0x1f, 0x2b}, {0x20, 0x2c}, {0x21, 0x2d}, {0x22, 0x2e},
> + {0x23, 0x2f}, {0x24, 0x30}, {0x25, 0x31}, {0x26, 0x32}, {0x27, 0x33},
> + {0x28, 0x34}, {0x29, 0x35}, {0x2a, 0x36}, {0x2b, 0x37}, {0x2c, 0x38},
> + {0x2d, 0x39}, {0x2e, 0x3a}, {0x2f, 0x3b}, {0x30, 0x3c}, {0x31, 0x3d},
> + {0x32, 0x3e}, {0x33, 0x3f}, {0x34, 0x3f}, {0x35, 0x3f}, {0x36, 0x3f},
> + {0x37, 0x3f}, {0x38, 0x3f}, {0x39, 0x3f}, {0x3a, 0x3f}, {0x3b, 0x3f},
> + {0x3c, 0x3f}, {0x3d, 0x3f}, {0x3e, 0x3f}, {0x3f, 0x3f}, {0x40, 0x0c},
> + {0x41, 0x0b}, {0x42, 0x0a}, {0x43, 0x09}, {0x44, 0x08}, {0x45, 0x07},
> + {0x46, 0x06}, {0x47, 0x05}, {0x48, 0x04}, {0x49, 0x03}, {0x4a, 0x02},
> + {0x4b, 0x01}, {0x4c, 0x40}, {0x4d, 0x41}, {0x4e, 0x42}, {0x4f, 0x43},
> + {0x50, 0x44}, {0x51, 0x45}, {0x52, 0x46}, {0x53, 0x47}, {0x54, 0x48},
> + {0x55, 0x49}, {0x56, 0x4a}, {0x57, 0x4b}, {0x58, 0x4c}, {0x59, 0x4d},
> + {0x5a, 0x4e}, {0x5b, 0x4f}, {0x5c, 0x50}, {0x5d, 0x51}, {0x5e, 0x52},
> + {0x5f, 0x53}, {0x60, 0x54}, {0x61, 0x55}, {0x62, 0x56}, {0x63, 0x57},
> + {0x64, 0x58}, {0x65, 0x59}, {0x66, 0x5a}, {0x67, 0x5b}, {0x68, 0x5c},
> + {0x69, 0x5d}, {0x6a, 0x5e}, {0x6b, 0x5f}, {0x6c, 0x60}, {0x6d, 0x61},
> + {0x6e, 0x62}, {0x6f, 0x63}, {0x70, 0x64}, {0x71, 0x65}, {0x72, 0x66},
> + {0x73, 0x67}, {0x74, 0x68}, {0x75, 0x69}, {0x76, 0x6a}, {0x77, 0x6b},
> + {0x78, 0x6c}, {0x79, 0x6d}, {0x7a, 0x6e}, {0x7b, 0x6f}, {0x7c, 0x70},
> + {0x7d, 0x71}, {0x7e, 0x72}, {0x7f, 0x73},
> +};

What's this used for?

> +static int s6e3fa0_dcs_read(struct s6e3fa0 *ctx, unsigned char cmd,
> + void *data, size_t len)
> +{
> + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> +
> + return mipi_dsi_dcs_read(dsi, dsi->channel, cmd, data, len);
> +}
> +
> +static void s6e3fa0_dcs_write(struct s6e3fa0 *ctx, const void *data, size_t 
> len)
> +{
> + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> +
> + mipi_dsi_dcs_write(dsi, dsi->channel, data, len);
> +}

Both mipi_dsi_dcs_read() and mipi_dsi_dcs_write() return error codes on
failure. Why are you silently ignoring them?

> +#define s6e3fa0_dcs_write_seq(ctx, seq...)   \
> +

Re: [PATCH v6 09/14] ARM: dts: s6e3fa0: add DT bindings

[Thierry Reding]

On Thu, Jul 17, 2014 at 06:01:24PM +0900, YoungJun Cho wrote:
> This patch adds DT bindings for s6e3fa0 panel.
> The bindings describes panel resources and display timings.

The commit message here should preferably say which platform this is
used on.

> Signed-off-by: YoungJun Cho 
> Acked-by: Inki Dae 
> Acked-by: Kyungmin Park 
> ---
>  .../devicetree/bindings/panel/samsung,s6e3fa0.txt  | 46 
> ++
>  1 file changed, 46 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
> 
> diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt 
> b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
> new file mode 100644
> index 000..2cd32f5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
> @@ -0,0 +1,46 @@
> +Samsung S6E3FA0 AMOLED LCD 5.7 inch panel
> +
> +Required properties:
> +  - compatible: "samsung,s6e3fa0"
> +  - reg: the virtual channel number of a DSI peripheral
> +  - vdd3-supply: core voltage supply
> +  - vci-supply: voltage supply for analog circuits
> +  - reset-gpios: a GPIO spec for the reset pin
> +  - det-gpios: a GPIO spec for the OLED detection pin
> +  - te-gpios: a GPIO spec for the TE pin
> +  - display-timings: timings for the connected panel as described by [1]

display-timings should be optional. The panel driver should provide a
default mode. And only if you really need to override the default mode
you should provide the option of getting an alternative set of values
from DT.

Thierry


pgpMb_h2g7UAy.pgp
Description: PGP signature

Re: [PATCH 0/3] Adds PMU and S2R support for exynos5800

[Vikas Sajjan]

On Wed, Jul 9, 2014 at 5:10 PM, Vikas Sajjan  wrote:
> Rebased on
> 1] Kukjin Kim's tree, for-next branch
> https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
> 2] My 5420 PMU Series :
> http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg33675.html
>
> Tested on Exynos5800 based chromebook (peach-pi board) with help of
>  1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html (modified to 
> support 5800)
>  2] http://www.spinics.net/lists/linux-samsung-soc/msg32923.html
>
> Below are steps followed to test S2R:
> 1. make multi_v7_defconfig
> 2  enable MCPM for 5420
> 3. enable S3C RTC
> 4. pass "no_console_suspend" in bootargs
> 5. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > 
> /sys/power/state
>
> Vikas Sajjan (3):
>   arm: dts: Add pmu node for exynos5800 SoC
>   arm: exynos: Add exynos5800-pmu compatible entry
>   arm: exynos: Add PMU and S2R support for exynos5800 SoC
>
>  .../devicetree/bindings/arm/samsung/pmu.txt|1 +
>  arch/arm/boot/dts/exynos5800.dtsi  |4 
>  arch/arm/mach-exynos/exynos.c  |1 +
>  arch/arm/mach-exynos/pm.c  |3 +++
>  arch/arm/mach-exynos/pmu.c |   22 
> 
>  arch/arm/mach-exynos/regs-pmu.h|3 ++-
>  6 files changed, 33 insertions(+), 1 deletion(-)


any comments on this series..


>
> --
> 1.7.9.5
>
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Re: [PATCH 18/19] ARM: SAMSUNG: Remove remaining legacy code

[Paul Bolle]

On Thu, 2014-07-17 at 12:10 +0200, Paul Bolle wrote:
> The strange thing is that it is dated "Jun 3 2104".
  2014
That must be my most common typo!


Paul Bolle


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Re: [PATCH 18/19] ARM: SAMSUNG: Remove remaining legacy code

[Paul Bolle]

Tomasz,

On Wed, 2014-07-16 at 14:56 +0200, Tomasz Figa wrote:
> On 16.07.2014 11:47, Paul Bolle wrote: 
> > So a second order effect is that SAMSUNG_GPIO_EXTRA can now be removed.
> > Which implies that SAMSUNG_GPIO_EXTRA64 and SAMSUNG_GPIO_EXTRA128 can
> > also be removed.
> > 
> > Should I submit the trivial patch to do that or is a patch already
> > queued somewhere?
> 
> Please do if you don't mind. That's one more thing I missed.

I got lucky! Commit ab275b132a79 ("ARM: s5p: cut the custom
ARCH_NR_GPIOS definition") was added to next-20140717 which does just
that.

The strange thing is that it is dated "Jun 3 2104". I don't know what
happened there but I have little reason to find that out.

Thanks,


Paul Bolle

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Re: [PATCH 2/2 v2] i2c: exynos5: remove extra line and fix an assignment

[Wolfram Sang]

On Thu, Jun 26, 2014 at 10:44:58AM +0530, Naveen Krishna Chatradhi wrote:
> This patch does the following in exynos5_i2c_message_start() function
> 1. Fixes an assignment
>As, "i2c_auto_conf" is initialized to '0' at the beginning of the
>function and HSI2C_READ_WRITE is defined as (1u << 16)
> 
>Using "|=" for the first assignment is more readable.
> 
> 2. Removes an extra line 
> 
> Signed-off-by: Naveen Krishna Chatradhi 

Applied to for-next, thanks!



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Description: Digital signature

Re: [PATCH 1/2 v2] i2c: exynos5: remove an unnecessary read of FIFO_STATUS register

[Wolfram Sang]

On Thu, Jun 26, 2014 at 10:44:57AM +0530, Naveen Krishna Chatradhi wrote:
> This patch removes an extra read of FIFO_STATUS register in the interrrupt
> service routine. Which is read again before the actual use.
> 
> Signed-off-by: Naveen Krishna Chatradhi 

Applied to for-next, thanks!



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[PATCH v6 10/14] drm/panel: add S6E3FA0 driver

[YoungJun Cho]

This patch adds MIPI DSI command mode based
S6E3FA0 AMOLED LCD Panel driver.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/panel/Kconfig |   7 +
 drivers/gpu/drm/panel/Makefile|   1 +
 drivers/gpu/drm/panel/panel-s6e3fa0.c | 541 ++
 3 files changed, 549 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 4ec874d..be1392e 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -30,4 +30,11 @@ config DRM_PANEL_S6E8AA0
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS
 
+config DRM_PANEL_S6E3FA0
+   tristate "S6E3FA0 DSI command mode panel"
+   depends on DRM && DRM_PANEL
+   depends on OF
+   select DRM_MIPI_DSI
+   select VIDEOMODE_HELPERS
+
 endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 8b92921..85c6738 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
 obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
+obj-$(CONFIG_DRM_PANEL_S6E3FA0) += panel-s6e3fa0.o
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c 
b/drivers/gpu/drm/panel/panel-s6e3fa0.c
new file mode 100644
index 000..811ec92
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e3fa0.c
@@ -0,0 +1,541 @@
+/*
+ * MIPI DSI command mode based s6e3fa0 AMOLED LCD 5.7 inch drm panel driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * YoungJun Cho 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+/* Manufacturer Command Set */
+#define MCS_GLOBAL_PARAMETER   0xb0
+#define MCS_AID0xb2
+#define MCS_ELVSSOPT   0xb6
+#define MCS_TEMPERATURE_SET0xb8
+#define MCS_PENTILE_CTRL   0xc0
+#define MCS_GAMMA_MODE 0xca
+#define MCS_VDDM   0xd7
+#define MCS_ALS0xe3
+#define MCS_ERR_FG 0xed
+#define MCS_KEY_LEV1   0xf0
+#define MCS_GAMMA_UPDATE   0xf7
+#define MCS_KEY_LEV2   0xfc
+#define MCS_RE 0xfe
+#define MCS_TOUT2_HSYNC0xff
+
+/* Content Adaptive Brightness Control */
+#define DCS_WRITE_CABC 0x55
+
+#define MTP_ID_LEN 3
+#define GAMMA_LEVEL_NUM30
+
+#define DEFAULT_VDDM_VAL   0x15
+
+struct s6e3fa0 {
+   struct device   *dev;
+   struct drm_panelpanel;
+
+   struct regulator_bulk_data  supplies[2];
+   struct gpio_desc*reset_gpio;
+   struct videomodevm;
+
+   unsigned intpower_on_delay;
+   unsigned intreset_delay;
+   unsigned intinit_delay;
+   unsigned intwidth_mm;
+   unsigned intheight_mm;
+
+   unsigned char   id;
+   unsigned char   vddm;
+   unsigned intbrightness;
+};
+
+#define panel_to_s6e3fa0(p) container_of(p, struct s6e3fa0, panel)
+
+/* VDD Memory Lookup Table contains pairs of {ReadValue, WriteValue} */
+static const unsigned char s6e3fa0_vddm_lut[][2] = {
+   {0x00, 0x0d}, {0x01, 0x0d}, {0x02, 0x0e}, {0x03, 0x0f}, {0x04, 0x10},
+   {0x05, 0x11}, {0x06, 0x12}, {0x07, 0x13}, {0x08, 0x14}, {0x09, 0x15},
+   {0x0a, 0x16}, {0x0b, 0x17}, {0x0c, 0x18}, {0x0d, 0x19}, {0x0e, 0x1a},
+   {0x0f, 0x1b}, {0x10, 0x1c}, {0x11, 0x1d}, {0x12, 0x1e}, {0x13, 0x1f},
+   {0x14, 0x20}, {0x15, 0x21}, {0x16, 0x22}, {0x17, 0x23}, {0x18, 0x24},
+   {0x19, 0x25}, {0x1a, 0x26}, {0x1b, 0x27}, {0x1c, 0x28}, {0x1d, 0x29},
+   {0x1e, 0x2a}, {0x1f, 0x2b}, {0x20, 0x2c}, {0x21, 0x2d}, {0x22, 0x2e},
+   {0x23, 0x2f}, {0x24, 0x30}, {0x25, 0x31}, {0x26, 0x32}, {0x27, 0x33},
+   {0x28, 0x34}, {0x29, 0x35}, {0x2a, 0x36}, {0x2b, 0x37}, {0x2c, 0x38},
+   {0x2d, 0x39}, {0x2e, 0x3a}, {0x2f, 0x3b}, {0x30, 0x3c}, {0x31, 0x3d},
+   {0x32, 0x3e}, {0x33, 0x3f}, {0x34, 0x3f}, {0x35, 0x3f}, {0x36, 0x3f},
+   {0x37, 0x3f}, {0x38, 0x3f}, {0x39, 0x3f}, {0x3a, 0x3f}, {0x3b, 0x3f},
+   {0x3c, 0x3f}, {0x3d, 0x3f}, {0x3e, 0x3f}, {0x3f, 0x3f}, {0x40, 0x0c},
+   {0x41, 0x0b}, {0x42, 0x0a}, {0x43, 0x09}, {0x44, 0x08}, {0x45, 0x07},
+   {0x46, 0x06}, {0x47, 0x05}, {0x48, 0x04}, {0x49, 0x03}, {0x4a, 0x02},
+   {0x4b, 0x01}, {0x4c, 0x40}, {0x4d, 0x41}, {0x4e, 0x42}, {0x4f, 0x43},
+   {0x50, 0x44}, {0x51, 0x45}, {0x52, 0x46}, {0x53, 0x47}, {0x54, 0x48},
+   {0x55, 0x49}, {0x56, 

[PATCH v6 09/14] ARM: dts: s6e3fa0: add DT bindings

[YoungJun Cho]

This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources and display timings.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 .../devicetree/bindings/panel/samsung,s6e3fa0.txt  | 46 ++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt

diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt 
b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
new file mode 100644
index 000..2cd32f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
@@ -0,0 +1,46 @@
+Samsung S6E3FA0 AMOLED LCD 5.7 inch panel
+
+Required properties:
+  - compatible: "samsung,s6e3fa0"
+  - reg: the virtual channel number of a DSI peripheral
+  - vdd3-supply: core voltage supply
+  - vci-supply: voltage supply for analog circuits
+  - reset-gpios: a GPIO spec for the reset pin
+  - det-gpios: a GPIO spec for the OLED detection pin
+  - te-gpios: a GPIO spec for the TE pin
+  - display-timings: timings for the connected panel as described by [1]
+
+Optional properties:
+
+The device node can contain one 'port' child node with one child 'endpoint'
+node, according to the bindings defined in [2]. This node should describe
+panel's video bus.
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+   panel@0 {
+   compatible = "samsung,s6e3fa0";
+   reg = <0>;
+   vdd3-supply = <&vcclcd_reg>;
+   vci-supply = <&vlcd_reg>;
+   reset-gpios = <&gpy7 4 0>;
+   det-gpios = <&gpg0 6 0>;
+   te-gpios = <&gpd1 7 0>;
+
+   display-timings {
+   timings0 {
+   clock-frequency = <0>;
+   hactive = <1080>;
+   vactive = <1920>;
+   hfront-porch = <2>;
+   hback-porch = <2>;
+   hsync-len = <1>;
+   vfront-porch = <1>;
+   vback-porch = <4>;
+   vsync-len = <1>;
+   };
+   };
+   };
-- 
1.9.0

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[PATCH v6 07/14] ARM: dts: exynos_dsim: add exynos5410 compatible to DT bindings

[YoungJun Cho]

This patch adds relevant to exynos5410 compatible
for exynos5410 / 5420 / 5440 SoCs support.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 Documentation/devicetree/bindings/video/exynos_dsim.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt 
b/Documentation/devicetree/bindings/video/exynos_dsim.txt
index 33b5730..31036c6 100644
--- a/Documentation/devicetree/bindings/video/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -1,7 +1,9 @@
 Exynos MIPI DSI Master
 
 Required properties:
-  - compatible: "samsung,exynos4210-mipi-dsi"
+  - compatible: value should be one of the following
+   "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
+   "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs 
*/
   - reg: physical base address and length of the registers set for the device
   - interrupts: should contain DSI interrupt
   - clocks: list of clock specifiers, must contain an entry for each required
-- 
1.9.0

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[PATCH v6 13/14] ARM: dts: exynos5420: add mipi-phy node

[YoungJun Cho]

This patch adds mipi-phy node for MIPI DSI device.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos5420.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index e385322..0b9d15d 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -517,6 +517,12 @@
phy-names = "dp";
};
 
+   mipi_phy: video-phy@10040714 {
+   compatible = "samsung,s5pv210-mipi-video-phy";
+   reg = <0x10040714 12>;
+   #phy-cells = <1>;
+   };
+
fimd: fimd@1440 {
samsung,power-domain = <&disp_pd>;
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
-- 
1.9.0

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[PATCH v6 11/14] ARM: dts: exynos4: add system register property

[YoungJun Cho]

This patch adds sysreg property to fimd device node
which is required to use I80 interface.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos4.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index fbaf426..3793881 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -608,6 +608,7 @@
clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
clock-names = "sclk_fimd", "fimd";
samsung,power-domain = <&pd_lcd0>;
+   samsung,sysreg = <&sys_reg>;
status = "disabled";
};
 };
-- 
1.9.0

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[PATCH v6 02/14] drm/exynos: use wait_event_timeout() for safety usage

[YoungJun Cho]

There could be the case that the page flip operation isn't finished correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip completion
infinitely.
And clears exynos_crtc->pending_flip in exynos_drm_crtc_page_flip()
when exynos_drm_crtc_mode_set_commit() is failed.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
Reviewed-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_drm_crtc.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c 
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 95c9435..3bf091d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -69,8 +69,10 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int 
mode)
 
if (mode > DRM_MODE_DPMS_ON) {
/* wait for the completion of page flip. */
-   wait_event(exynos_crtc->pending_flip_queue,
-   atomic_read(&exynos_crtc->pending_flip) == 0);
+   if (!wait_event_timeout(exynos_crtc->pending_flip_queue,
+   !atomic_read(&exynos_crtc->pending_flip),
+   HZ/20))
+   atomic_set(&exynos_crtc->pending_flip, 0);
drm_vblank_off(crtc->dev, exynos_crtc->pipe);
}
 
@@ -259,6 +261,7 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
spin_lock_irq(&dev->event_lock);
drm_vblank_put(dev, exynos_crtc->pipe);
list_del(&event->base.link);
+   atomic_set(&exynos_crtc->pending_flip, 0);
spin_unlock_irq(&dev->event_lock);
 
goto out;
-- 
1.9.0

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[PATCH v6 14/14] ARM: dts: exynos5420: add dsi node

[YoungJun Cho]

This patch adds common part of dsi node.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos5420.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 0b9d15d..3a7862b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -523,6 +523,20 @@
#phy-cells = <1>;
};
 
+   dsi@1450 {
+   compatible = "samsung,exynos5410-mipi-dsi";
+   reg = <0x1450 0x1>;
+   interrupts = <0 82 0>;
+   samsung,power-domain = <&disp_pd>;
+   phys = <&mipi_phy 1>;
+   phy-names = "dsim";
+   clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
+   clock-names = "bus_clk", "pll_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
fimd: fimd@1440 {
samsung,power-domain = <&disp_pd>;
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
-- 
1.9.0

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[PATCH v6 06/14] drm/exynos: fimd: support LCD I80 interface

[YoungJun Cho]

To support MIPI command mode based I80 interface panel,
FIMD should do followings:
- Sets LCD I80 interface timings configuration.
- Uses "lcd_sys" as an IRQ resource and sets relevant IRQ configuration.
- Sets LCD block configuration for I80 interface.
- Sets ideal(pixel) clock is 2 times faster than the original one
  to generate frame done IRQ prior to the next TE signal.
- Implements trigger feature that transfers image data if there is page
  flip request, and implements TE handler to call trigger function.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/Kconfig   |   1 +
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 276 ++-
 include/video/samsung_fimd.h |   3 +-
 3 files changed, 235 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 178d2a9..9ba1aae 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -28,6 +28,7 @@ config DRM_EXYNOS_FIMD
bool "Exynos DRM FIMD"
depends on DRM_EXYNOS && !FB_S3C
select FB_MODE_HELPERS
+   select MFD_SYSCON
help
  Choose this option if you want to use Exynos FIMD for DRM.
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 33161ad..28a3168 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -20,6 +20,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include 
 #include 
@@ -61,6 +63,24 @@
 /* color key value register for hardware window 1 ~ 4. */
 #define WKEYCON1_BASE(x)   ((WKEYCON1 + 0x140) + ((x - 1) * 8))
 
+/* I80 / RGB trigger control register */
+#define TRIGCON0x1A4
+#define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
+#define SWTRGCMD_I80_RGB_ENABLE(1 << 1)
+
+/* display mode change control register except exynos4 */
+#define VIDOUT_CON 0x000
+#define VIDOUT_CON_F_I80_LDI0  (0x2 << 8)
+
+/* I80 interface control for main LDI register */
+#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
+#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
+#define LCD_CS_SETUP(x)((x) << 16)
+#define LCD_WR_SETUP(x)((x) << 12)
+#define LCD_WR_ACTIVE(x)   ((x) << 8)
+#define LCD_WR_HOLD(x) ((x) << 4)
+#define I80IFEN_ENABLE (1 << 0)
+
 /* FIMD has totally five hardware windows. */
 #define WINDOWS_NR 5
 
@@ -68,10 +88,14 @@
 
 struct fimd_driver_data {
unsigned int timing_base;
+   unsigned int lcdblk_offset;
+   unsigned int lcdblk_vt_shift;
+   unsigned int lcdblk_bypass_shift;
 
unsigned int has_shadowcon:1;
unsigned int has_clksel:1;
unsigned int has_limited_fmt:1;
+   unsigned int has_vidoutcon:1;
 };
 
 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
@@ -82,12 +106,19 @@ static struct fimd_driver_data s3c64xx_fimd_driver_data = {
 
 static struct fimd_driver_data exynos4_fimd_driver_data = {
.timing_base = 0x0,
+   .lcdblk_offset = 0x210,
+   .lcdblk_vt_shift = 10,
+   .lcdblk_bypass_shift = 1,
.has_shadowcon = 1,
 };
 
 static struct fimd_driver_data exynos5_fimd_driver_data = {
.timing_base = 0x2,
+   .lcdblk_offset = 0x214,
+   .lcdblk_vt_shift = 24,
+   .lcdblk_bypass_shift = 15,
.has_shadowcon = 1,
+   .has_vidoutcon = 1,
 };
 
 struct fimd_win_data {
@@ -112,15 +143,22 @@ struct fimd_context {
struct clk  *bus_clk;
struct clk  *lcd_clk;
void __iomem*regs;
+   struct regmap   *sysreg;
struct drm_display_mode mode;
struct fimd_win_datawin_data[WINDOWS_NR];
unsigned intdefault_win;
unsigned long   irq_flags;
+   u32 vidcon0;
u32 vidcon1;
+   u32 vidout_con;
+   u32 i80ifcon;
+   booli80_if;
boolsuspended;
int pipe;
wait_queue_head_t   wait_vsync_queue;
atomic_twait_vsync_event;
+   atomic_twin_updated;
+   atomic_ttriggering;
 
struct exynos_drm_panel_info panel;
struct fimd_driver_data *driver_data;
@@ -243,6 +281,14 @@ static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
u32 clkdiv;
 
+   if (ctx->i80_if) {
+   /*
+* The frame done interrupt sho

[PATCH v6 05/14] drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface

[YoungJun Cho]

To support LCD I80 interface, the DSI host should register
TE interrupt handler from the TE GPIO of attached panel.
So the panel generates a tearing effect synchronization signal
then the DSI host calls the CRTC device manager to trigger
to transfer video image.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 95 -
 1 file changed, 93 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 58bfb2a..4997bfe 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -16,7 +16,9 @@
 #include 
 
 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -24,6 +26,7 @@
 #include 
 #include 
 
+#include "exynos_drm_crtc.h"
 #include "exynos_drm_drv.h"
 
 /* returns true iff both arguments logically differs */
@@ -247,6 +250,7 @@ struct exynos_dsi {
struct clk *bus_clk;
struct regulator_bulk_data supplies[2];
int irq;
+   int te_gpio;
 
u32 pll_clk_rate;
u32 burst_clk_rate;
@@ -954,17 +958,89 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
return IRQ_HANDLED;
 }
 
+static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
+{
+   struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
+   struct drm_encoder *encoder = dsi->encoder;
+
+   if (dsi->state & DSIM_STATE_ENABLED)
+   exynos_drm_crtc_te_handler(encoder->crtc);
+
+   return IRQ_HANDLED;
+}
+
+static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
+{
+   enable_irq(dsi->irq);
+
+   if (gpio_is_valid(dsi->te_gpio))
+   enable_irq(gpio_to_irq(dsi->te_gpio));
+}
+
+static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
+{
+   if (gpio_is_valid(dsi->te_gpio))
+   disable_irq(gpio_to_irq(dsi->te_gpio));
+
+   disable_irq(dsi->irq);
+}
+
 static int exynos_dsi_init(struct exynos_dsi *dsi)
 {
exynos_dsi_enable_clock(dsi);
exynos_dsi_reset(dsi);
-   enable_irq(dsi->irq);
+   exynos_dsi_enable_irq(dsi);
exynos_dsi_wait_for_reset(dsi);
exynos_dsi_init_link(dsi);
 
return 0;
 }
 
+static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
+{
+   int ret;
+
+   dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
+   if (!gpio_is_valid(dsi->te_gpio)) {
+   dev_err(dsi->dev, "no te-gpios specified\n");
+   ret = dsi->te_gpio;
+   goto out;
+   }
+
+   ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio");
+   if (ret) {
+   dev_err(dsi->dev, "gpio request failed with %d\n", ret);
+   goto out;
+   }
+
+   /*
+* This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel
+* calls drm_panel_init() first then calls mipi_dsi_attach() in probe().
+* It means that te_gpio is invalid when exynos_dsi_enable_irq() is
+* called by drm_panel_init() before panel is attached.
+*/
+   ret = request_threaded_irq(gpio_to_irq(dsi->te_gpio),
+   exynos_dsi_te_irq_handler, NULL,
+   IRQF_TRIGGER_RISING, "TE", dsi);
+   if (ret) {
+   dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
+   gpio_free(dsi->te_gpio);
+   goto out;
+   }
+
+out:
+   return ret;
+}
+
+static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
+{
+   if (gpio_is_valid(dsi->te_gpio)) {
+   free_irq(gpio_to_irq(dsi->te_gpio), dsi);
+   gpio_free(dsi->te_gpio);
+   dsi->te_gpio = -ENOENT;
+   }
+}
+
 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
  struct mipi_dsi_device *device)
 {
@@ -978,6 +1054,16 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host 
*host,
if (dsi->connector.dev)
drm_helper_hpd_irq_event(dsi->connector.dev);
 
+   /*
+* If attached panel device is for command mode one, dsi should
+* register TE interrupt handler.
+*/
+   if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
+   int ret = exynos_dsi_register_te_irq(dsi);
+   if (ret)
+   return ret;
+   }
+
return 0;
 }
 
@@ -986,6 +1072,8 @@ static int exynos_dsi_host_detach(struct mipi_dsi_host 
*host,
 {
struct exynos_dsi *dsi = host_to_dsi(host);
 
+   exynos_dsi_unregister_te_irq(dsi);
+
dsi->panel_node = NULL;
 
if (dsi->connector.dev)
@@ -1099,7 +1187,7 @@ static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
 
exynos_dsi_disable_clock(dsi);
 
-   disable_irq(dsi->irq);
+   exynos_dsi_disable_irq(dsi);
}
 
dsi->state &= ~DSIM_STA

[PATCH v6 00/14] drm/exynos: support LCD I80 interface display

[YoungJun Cho]

Hi,

This series adds LCD I80 interface display support for Exynos DRM driver.
The FIMD(display controller) specification describes it as "LCD I80 interface"
and the DSI specification describes it as "Command mode interface".

This is based on exynos-drm-next branch.

The previous patches,
RFC: http://www.spinics.net/lists/dri-devel/msg58898.html
V1: http://www.spinics.net/lists/dri-devel/msg59291.html
V2: http://www.spinics.net/lists/dri-devel/msg59867.html
V3: http://www.spinics.net/lists/dri-devel/msg60708.html
V4: http://www.spinics.net/lists/dri-devel/msg60943.html
V5: http://www.spinics.net/lists/dri-devel/msg62956.html

Changelog v2:
- Fixes typo and removes unnecessary error log. (commented by Andrzej Hazda)
- Adds missed pendlig_flip flag clear points. (commented by Daniel Kurtz)

Changelog v3:
- Removes generic command mode and command mode display timing interface.
- Moves I80 interface timings from panel DT to the FIMD(display controller) DT.

Changelog v4:
- Removes exynos5 sysreg(syscon) DT bindings and node from dtsi because
  it was already updated by linux-samsung-soc. (commented by Vivek Gautam)

Changelog v5:
- Fixes FIMD vidcon0 register relevant code.
- Fixes panel gamma table, disable sequence.
- Slitely updates for code cleanup.

Changelog v6:
- Removes pass TE host ops in dsi and exynos dsi uses TE irq handler instead,
  and it is related with the TE GPIO of panel. (commented by Thierry Reding)

Patches 1 and 2 fix trivial bugs.

Patches 3, 4, 5 and 6 implement FIMD(display controller) I80 interface.
The MIPI DSI command mode based panel generates Tearing Effect synchronization
signal between MCU and FB to display video image, and FIMD should trigger to
transfer video image at this signal.
So the panel generates it and the dsi should receive the TE IRQ and call TE
handler chains to notify it to the FIMD.

Patches 7 and 8 implement to use Exynos5410 / 5420 / 5440 SoC DSI driver
which is different from previous Exynos4 SoCs for some registers control.

Patches 9 and 10 introduce MIPI DSI command mode based Samsung S6E3FA0 AMOLED
5.7" LCD drm panel driver.

The ohters add DT property nodes to support MIPI DSI command mode.

I welcome any comments.

Thank you.
Best regards YJ

YoungJun Cho (14):
  drm/exynos: dsi: move the EoT packets configuration point
  drm/exynos: use wait_event_timeout() for safety usage
  ARM: dts: samsung-fimd: add LCD I80 interface specific properties
  drm/exynos: add TE handler to support LCD I80 interface
  drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface
  drm/exynos: fimd: support LCD I80 interface
  ARM: dts: exynos_dsim: add exynos5410 compatible to DT bindings
  drm/exynos: dsi: add driver data to support Exynos5410/5420/5440 SoCs
  ARM: dts: s6e3fa0: add DT bindings
  drm/panel: add S6E3FA0 driver
  ARM: dts: exynos4: add system register property
  ARM: dts: exynos5: add system register property
  ARM: dts: exynos5420: add mipi-phy node
  ARM: dts: exynos5420: add dsi node

 .../devicetree/bindings/panel/samsung,s6e3fa0.txt  |  46 ++
 .../devicetree/bindings/video/exynos_dsim.txt  |   4 +-
 .../devicetree/bindings/video/samsung-fimd.txt |  28 ++
 arch/arm/boot/dts/exynos4.dtsi |   1 +
 arch/arm/boot/dts/exynos5.dtsi |   1 +
 arch/arm/boot/dts/exynos5420.dtsi  |  20 +
 drivers/gpu/drm/exynos/Kconfig |   1 +
 drivers/gpu/drm/exynos/exynos_drm_crtc.c   |  15 +-
 drivers/gpu/drm/exynos/exynos_drm_crtc.h   |   7 +
 drivers/gpu/drm/exynos/exynos_drm_drv.h|   3 +
 drivers/gpu/drm/exynos/exynos_drm_dsi.c| 266 +-
 drivers/gpu/drm/exynos/exynos_drm_fimd.c   | 276 +--
 drivers/gpu/drm/panel/Kconfig  |   7 +
 drivers/gpu/drm/panel/Makefile |   1 +
 drivers/gpu/drm/panel/panel-s6e3fa0.c  | 541 +
 include/video/samsung_fimd.h   |   3 +-
 16 files changed, 1146 insertions(+), 74 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
 create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c

-- 
1.9.0

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[PATCH v6 08/14] drm/exynos: dsi: add driver data to support Exynos5410/5420/5440 SoCs

[YoungJun Cho]

The offset of register DSIM_PLLTMR_REG in Exynos5410 / 5420 / 5440
SoCs is different from the one in Exynos4 SoCs.

In case of Exynos5410 / 5420 / 5440 SoCs, there is no frequency
band bit in DSIM_PLLCTRL_REG, and it uses DSIM_PHYCTRL_REG and
DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 157 +++-
 1 file changed, 135 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 4997bfe..93ad4a2 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -57,9 +58,12 @@
 
 /* FIFO memory AC characteristic register */
 #define DSIM_PLLCTRL_REG   0x4c/* PLL control register */
-#define DSIM_PLLTMR_REG0x50/* PLL timer register */
 #define DSIM_PHYACCHR_REG  0x54/* D-PHY AC characteristic register */
 #define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1 */
+#define DSIM_PHYCTRL_REG   0x5c
+#define DSIM_PHYTIMING_REG 0x64
+#define DSIM_PHYTIMING1_REG0x68
+#define DSIM_PHYTIMING2_REG0x6c
 
 /* DSIM_STATUS */
 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
@@ -203,6 +207,24 @@
 #define DSIM_PLL_M(x)  ((x) << 4)
 #define DSIM_PLL_S(x)  ((x) << 1)
 
+/* DSIM_PHYCTRL */
+#define DSIM_PHYCTRL_ULPS_EXIT(x)  (((x) & 0x1ff) << 0)
+
+/* DSIM_PHYTIMING */
+#define DSIM_PHYTIMING_LPX(x)  ((x) << 8)
+#define DSIM_PHYTIMING_HS_EXIT(x)  ((x) << 0)
+
+/* DSIM_PHYTIMING1 */
+#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
+#define DSIM_PHYTIMING1_CLK_ZERO(x)((x) << 16)
+#define DSIM_PHYTIMING1_CLK_POST(x)((x) << 8)
+#define DSIM_PHYTIMING1_CLK_TRAIL(x)   ((x) << 0)
+
+/* DSIM_PHYTIMING2 */
+#define DSIM_PHYTIMING2_HS_PREPARE(x)  ((x) << 16)
+#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
+#define DSIM_PHYTIMING2_HS_TRAIL(x)((x) << 0)
+
 #define DSI_MAX_BUS_WIDTH  4
 #define DSI_NUM_VIRTUAL_CHANNELS   4
 #define DSI_TX_FIFO_SIZE   2048
@@ -236,6 +258,12 @@ struct exynos_dsi_transfer {
 #define DSIM_STATE_INITIALIZED BIT(1)
 #define DSIM_STATE_CMD_LPM BIT(2)
 
+struct exynos_dsi_driver_data {
+   unsigned int plltmr_reg;
+
+   unsigned int has_freqband:1;
+};
+
 struct exynos_dsi {
struct mipi_dsi_host dsi_host;
struct drm_connector connector;
@@ -266,11 +294,39 @@ struct exynos_dsi {
 
spinlock_t transfer_lock; /* protects transfer_list */
struct list_head transfer_list;
+
+   struct exynos_dsi_driver_data *driver_data;
 };
 
 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
 
+static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+   .plltmr_reg = 0x50,
+   .has_freqband = 1,
+};
+
+static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+   .plltmr_reg = 0x58,
+};
+
+static struct of_device_id exynos_dsi_of_match[] = {
+   { .compatible = "samsung,exynos4210-mipi-dsi",
+ .data = &exynos4_dsi_driver_data },
+   { .compatible = "samsung,exynos5410-mipi-dsi",
+ .data = &exynos5_dsi_driver_data },
+   { }
+};
+
+static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
+   struct platform_device *pdev)
+{
+   const struct of_device_id *of_id =
+   of_match_device(exynos_dsi_of_match, &pdev->dev);
+
+   return (struct exynos_dsi_driver_data *)of_id->data;
+}
+
 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
 {
if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
@@ -344,14 +400,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct 
exynos_dsi *dsi,
 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
unsigned long freq)
 {
-   static const unsigned long freq_bands[] = {
-   100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
-   270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
-   510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
-   770 * MHZ, 870 * MHZ, 950 * MHZ,
-   };
+   struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
unsigned long fin, fout;
-   int timeout, band;
+   int timeout;
u8 p, s;
u16 m;
u32 reg;
@@ -372,18 +423,30 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi 
*dsi,
"failed to find PLL PMS for requested frequency\n");
return -EFAULT;
}
+   dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n",

[PATCH v6 12/14] ARM: dts: exynos5: add system register property

[YoungJun Cho]

This patch adds sysreg property to fimd device node
which is required to use I80 interface.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos5.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 79d0608..fdead12 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -87,6 +87,7 @@
reg = <0x1440 0x4>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <18 4>, <18 5>, <18 6>;
+   samsung,sysreg = <&sysreg_system_controller>;
status = "disabled";
};
 
-- 
1.9.0

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[PATCH v6 04/14] drm/exynos: add TE handler to support LCD I80 interface

[YoungJun Cho]

To support LCD I80 interface, the panel should generate
Tearing Effect synchronization signal between MCU and FB
to display video images.
And the display controller should trigger to transfer
video image at this signal.
So the panel receives the TE IRQ, then calls these handler
chains to notify it to the display controller.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_crtc.c | 8 
 drivers/gpu/drm/exynos/exynos_drm_crtc.h | 7 +++
 drivers/gpu/drm/exynos/exynos_drm_drv.h  | 3 +++
 3 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c 
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 3bf091d..b68e58f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -511,3 +511,11 @@ int exynos_drm_crtc_get_pipe_from_type(struct drm_device 
*drm_dev,
 
return -EPERM;
 }
+
+void exynos_drm_crtc_te_handler(struct drm_crtc *crtc)
+{
+   struct exynos_drm_manager *manager = to_exynos_crtc(crtc)->manager;
+
+   if (manager->ops->te_handler)
+   manager->ops->te_handler(manager);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h 
b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index 9f74b10..690dcdd 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -36,4 +36,11 @@ void exynos_drm_crtc_plane_disable(struct drm_crtc *crtc, 
int zpos);
 int exynos_drm_crtc_get_pipe_from_type(struct drm_device *drm_dev,
unsigned int out_type);
 
+/*
+ * This function calls the crtc device(manager)'s te_handler() callback
+ * to trigger to transfer video image at the tearing effect synchronization
+ * signal.
+ */
+void exynos_drm_crtc_te_handler(struct drm_crtc *crtc);
+
 #endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h 
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 02f3b3d..13be498 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -186,6 +186,8 @@ struct exynos_drm_display {
  * @win_commit: apply hardware specific overlay data to registers.
  * @win_enable: enable hardware specific overlay.
  * @win_disable: disable hardware specific overlay.
+ * @te_handler: trigger to transfer video image at the tearing effect
+ * synchronization signal if there is a page flip request.
  */
 struct exynos_drm_manager;
 struct exynos_drm_manager_ops {
@@ -204,6 +206,7 @@ struct exynos_drm_manager_ops {
void (*win_commit)(struct exynos_drm_manager *mgr, int zpos);
void (*win_enable)(struct exynos_drm_manager *mgr, int zpos);
void (*win_disable)(struct exynos_drm_manager *mgr, int zpos);
+   void (*te_handler)(struct exynos_drm_manager *mgr);
 };
 
 /*
-- 
1.9.0

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[PATCH v6 03/14] ARM: dts: samsung-fimd: add LCD I80 interface specific properties

[YoungJun Cho]

In case of using MIPI DSI based I80 interface panel,
the relevant registers should be set.
So this patch adds relevant DT bindings.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 .../devicetree/bindings/video/samsung-fimd.txt | 28 ++
 1 file changed, 28 insertions(+)

diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt 
b/Documentation/devicetree/bindings/video/samsung-fimd.txt
index 2dad41b..59ff61e 100644
--- a/Documentation/devicetree/bindings/video/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
@@ -44,6 +44,34 @@ Optional Properties:
 - display-timings: timing settings for FIMD, as described in document [1].
Can be used in case timings cannot be provided otherwise
or to override timings provided by the panel.
+- samsung,sysreg: handle to syscon used to control the system registers
+- i80-if-timings: timing configuration for lcd i80 interface support.
+  - cs-setup: clock cycles for the active period of address signal is enabled
+  until chip select is enabled.
+  If not specified, the default value(0) will be used.
+  - wr-setup: clock cycles for the active period of CS signal is enabled until
+  write signal is enabled.
+  If not specified, the default value(0) will be used.
+  - wr-active: clock cycles for the active period of CS is enabled.
+   If not specified, the default value(1) will be used.
+  - wr-hold: clock cycles for the active period of CS is disabled until write
+ signal is disabled.
+ If not specified, the default value(0) will be used.
+
+  The parameters are defined as:
+
+VCLK(internal)  __|¯¯|_|¯¯|_|¯¯|_|¯¯|_|¯¯
+  :::::
+Address Output  --:|:::
+Chip Select ¯¯¯|::|¯¯
+   | wr-setup+1 || wr-hold+1  |
+   |<-->||<-->|
+Write Enable||¯¯¯
+| wr-active+1|
+|<-->|
+Video Data  --
 
 The device node can contain 'port' child nodes according to the bindings 
defined
 in [2]. The following are properties specific to those nodes:
-- 
1.9.0

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[PATCH v6 01/14] drm/exynos: dsi: move the EoT packets configuration point

[YoungJun Cho]

This configuration could be used in MIPI DSI command mode also.
And adds user manual description for display configuration.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
Reviewed-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 2df3592..58bfb2a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -468,13 +468,20 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
/* DSI configuration */
reg = 0;
 
+   /*
+* The first bit of mode_flags specifies display configuration.
+* If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
+* mode, otherwise it will support command mode.
+*/
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
reg |= DSIM_VIDEO_MODE;
 
+   /*
+* The user manual describes that following bits are ignored in
+* command mode.
+*/
if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
reg |= DSIM_MFLUSH_VS;
-   if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
-   reg |= DSIM_EOT_DISABLE;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
reg |= DSIM_SYNC_INFORM;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
@@ -491,6 +498,9 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
reg |= DSIM_HSA_MODE;
}
 
+   if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
+   reg |= DSIM_EOT_DISABLE;
+
switch (dsi->format) {
case MIPI_DSI_FMT_RGB888:
reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
-- 
1.9.0

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