Re: [PATCH v9 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
Hi Javier, On Sat, Aug 2, 2014 at 9:19 AM, Javier Martinez Canillas javier.marti...@collabora.co.uk wrote: Hello Thomas, On 07/30/2014 10:07 AM, Thomas Abraham wrote: For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU regulator supply properties for migrating from Exynos specific cpufreq driver to using generic cpufreq drivers. Cc: Kukjin Kim kgene@samsung.com Cc: Doug Anderson diand...@chromium.org Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk Cc: Andreas Faerber afaer...@suse.de Cc: Sachin Kamat sachin.ka...@linaro.org Signed-off-by: Thomas Abraham thomas...@samsung.com --- arch/arm/boot/dts/exynos4210-origen.dts |4 +++ arch/arm/boot/dts/exynos4210-trats.dts |4 +++ arch/arm/boot/dts/exynos4210-universal_c210.dts |4 +++ arch/arm/boot/dts/exynos4210.dtsi | 14 - arch/arm/boot/dts/exynos5250-arndale.dts|4 +++ arch/arm/boot/dts/exynos5250-smdk5250.dts |4 +++ arch/arm/boot/dts/exynos5250-snow.dts |4 +++ arch/arm/boot/dts/exynos5250.dtsi | 25 ++- arch/arm/boot/dts/exynos5420.dtsi | 38 +++ 9 files changed, 99 insertions(+), 2 deletions(-) Tested the series on a Exynos5420 based Peach Pit Chromebook by doing the following for CPU0-3: 1) Verified that the big.LITTLE CPUFreq (arm-big-little) driver was reported as used in /sys/devices/system/cpu/cpu*/cpufreq/scaling_driver. 2) Set all available governors (conservative, ondemand, userspace, powersave and performance). 3) Confirmed that cpuinfo_cur_freq and scaling_cur_freq values were fixed or changing according to the selected governor policy. 4) Verified that the statistics in /sys/devices/system/cpu/cpu*/cpufreq/stats/* were filled. Everything is working correctly so please feel free to add for the whole series: Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Thank you for using this series and the details of what has worked. This is very helpful. Regards, Thomas. Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
Hello Thomas, On 07/30/2014 10:07 AM, Thomas Abraham wrote: For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU regulator supply properties for migrating from Exynos specific cpufreq driver to using generic cpufreq drivers. Cc: Kukjin Kim kgene@samsung.com Cc: Doug Anderson diand...@chromium.org Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk Cc: Andreas Faerber afaer...@suse.de Cc: Sachin Kamat sachin.ka...@linaro.org Signed-off-by: Thomas Abraham thomas...@samsung.com --- arch/arm/boot/dts/exynos4210-origen.dts |4 +++ arch/arm/boot/dts/exynos4210-trats.dts |4 +++ arch/arm/boot/dts/exynos4210-universal_c210.dts |4 +++ arch/arm/boot/dts/exynos4210.dtsi | 14 - arch/arm/boot/dts/exynos5250-arndale.dts|4 +++ arch/arm/boot/dts/exynos5250-smdk5250.dts |4 +++ arch/arm/boot/dts/exynos5250-snow.dts |4 +++ arch/arm/boot/dts/exynos5250.dtsi | 25 ++- arch/arm/boot/dts/exynos5420.dtsi | 38 +++ 9 files changed, 99 insertions(+), 2 deletions(-) Tested the series on a Exynos5420 based Peach Pit Chromebook by doing the following for CPU0-3: 1) Verified that the big.LITTLE CPUFreq (arm-big-little) driver was reported as used in /sys/devices/system/cpu/cpu*/cpufreq/scaling_driver. 2) Set all available governors (conservative, ondemand, userspace, powersave and performance). 3) Confirmed that cpuinfo_cur_freq and scaling_cur_freq values were fixed or changing according to the selected governor policy. 4) Verified that the statistics in /sys/devices/system/cpu/cpu*/cpufreq/stats/* were filled. Everything is working correctly so please feel free to add for the whole series: Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
Am 30.07.2014 10:07, schrieb Thomas Abraham:
For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific cpufreq driver
to using generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Cc: Doug Anderson diand...@chromium.org
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Andreas Faerber afaer...@suse.de
Cc: Sachin Kamat sachin.ka...@linaro.org
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |4 +++
arch/arm/boot/dts/exynos4210-trats.dts |4 +++
arch/arm/boot/dts/exynos4210-universal_c210.dts |4 +++
arch/arm/boot/dts/exynos4210.dtsi | 14 -
arch/arm/boot/dts/exynos5250-arndale.dts|4 +++
arch/arm/boot/dts/exynos5250-smdk5250.dts |4 +++
arch/arm/boot/dts/exynos5250-snow.dts |4 +++
arch/arm/boot/dts/exynos5250.dtsi | 25 ++-
arch/arm/boot/dts/exynos5420.dtsi | 38
+++
9 files changed, 99 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f767c42..887dded 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -334,3 +334,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck1_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9..66119dd 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -446,3 +446,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = varm_breg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..bf0a39c 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -492,3 +492,7 @@
mdma1 {
reg = 0x1284 0x1000;
};
+
+cpu0 {
+ cpu0-supply = vdd_arm_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63..69bac07 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -35,10 +35,22 @@
#address-cells = 1;
#size-cells = 0;
- cpu@900 {
+ cpu0: cpu@900 {
device_type = cpu;
compatible = arm,cortex-a9;
reg = 0x900;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 16;
+
+ operating-points =
+ 120 125
+ 100 115
+ 80 1075000
+ 50 975000
+ 40 975000
+ 20 95
Nit: Here you left-align the columns ...
+ ;
};
cpu@901 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..3b12a97 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -575,3 +575,7 @@
usb-phy = usb2_phy;
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35ad..f07e834 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -414,3 +414,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index f2b8c41..91acca7 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -509,4 +509,8 @@
};
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
#include cros-ec-keyboard.dtsi
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1ef..97b282c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,11 +58,34 @@
#address-cells = 1;
#size-cells = 0;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 14;
+
+ operating-points =
+
Re: [PATCH v9 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
On Wed, Jul 30, 2014 at 4:58 PM, Andreas Färber afaer...@suse.de wrote:
Am 30.07.2014 10:07, schrieb Thomas Abraham:
For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific cpufreq driver
to using generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Cc: Doug Anderson diand...@chromium.org
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Andreas Faerber afaer...@suse.de
Cc: Sachin Kamat sachin.ka...@linaro.org
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |4 +++
arch/arm/boot/dts/exynos4210-trats.dts |4 +++
arch/arm/boot/dts/exynos4210-universal_c210.dts |4 +++
arch/arm/boot/dts/exynos4210.dtsi | 14 -
arch/arm/boot/dts/exynos5250-arndale.dts|4 +++
arch/arm/boot/dts/exynos5250-smdk5250.dts |4 +++
arch/arm/boot/dts/exynos5250-snow.dts |4 +++
arch/arm/boot/dts/exynos5250.dtsi | 25 ++-
arch/arm/boot/dts/exynos5420.dtsi | 38
+++
9 files changed, 99 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f767c42..887dded 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -334,3 +334,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck1_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9..66119dd 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -446,3 +446,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = varm_breg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..bf0a39c 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -492,3 +492,7 @@
mdma1 {
reg = 0x1284 0x1000;
};
+
+cpu0 {
+ cpu0-supply = vdd_arm_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63..69bac07 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -35,10 +35,22 @@
#address-cells = 1;
#size-cells = 0;
- cpu@900 {
+ cpu0: cpu@900 {
device_type = cpu;
compatible = arm,cortex-a9;
reg = 0x900;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 16;
+
+ operating-points =
+ 120 125
+ 100 115
+ 80 1075000
+ 50 975000
+ 40 975000
+ 20 95
Nit: Here you left-align the columns ...
+ ;
};
cpu@901 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..3b12a97 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -575,3 +575,7 @@
usb-phy = usb2_phy;
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35ad..f07e834 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -414,3 +414,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index f2b8c41..91acca7 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -509,4 +509,8 @@
};
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
#include cros-ec-keyboard.dtsi
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1ef..97b282c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,11 +58,34 @@
#address-cells = 1;
#size-cells = 0;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 14;
+
+
Re: [PATCH v9 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
Thomas,
On Wed, Jul 30, 2014 at 8:21 PM, Thomas Abraham ta.oma...@gmail.com wrote:
Hi Doug,
On Thu, Jul 31, 2014 at 6:07 AM, Doug Anderson diand...@chromium.org wrote:
Thomas,
On Wed, Jul 30, 2014 at 1:07 AM, Thomas Abraham thomas...@samsung.com
wrote:
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..3b12a97 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -575,3 +575,7 @@
usb-phy = usb2_phy;
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35ad..f07e834 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -414,3 +414,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index f2b8c41..91acca7 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -509,4 +509,8 @@
};
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
#include cros-ec-keyboard.dtsi
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1ef..97b282c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,11 +58,34 @@
#address-cells = 1;
#size-cells = 0;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 14;
Where did the 14 number come from? My old calculations show that
with lock time of 270 ad P up to 6 we were at 67.5us lock time.
I measured the time taken by clk_set_rate call in the cpufreq driver
using do_gettimeofday(). The time taken to change the clock speed was
between 87us to 134us for Exynos5420. So I just took the worst case
time of 140us. Also, the time taken to change the CPU clock speed
includes the settling time for changes to dividers and mux clock
blocks.
Interesting. I wonder why the difference between my earlier
calculations. It seems just about double. :-/
+ operating-points =
+ 170 130
+ 160 125
+ 150 1225000
+ 140 120
+ 130 115
+ 120 1125000
+ 110 110
+ 100 1075000
+90 105
+80 1025000
+70 1012500
+60 100
+50 975000
+40 95
+30 937500
+20 925000
+ ;
};
cpu@1 {
device_type = cpu;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index cb2b70e..3154b4c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -59,8 +59,26 @@
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0x0;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu-cluster.0;
clock-frequency = 18;
cci-control-port = cci_control1;
+ clock-latency = 14;
+
+ operating-points =
+ 180 125
+ 170 1212500
+ 160 1175000
+ 150 1137500
+ 140 1112500
+ 130 1062500
+ 120 1037500
+ 110 1012500
+ 100 987500
+90 962500
+80 937500
+70 912500
+ ;
};
cpu1: cpu@1 {
@@ -69,6 +87,7 @@
reg = 0x1;
clock-frequency = 18;
Re: [PATCH v9 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
On Thu, Jul 31, 2014 at 9:23 AM, Doug Anderson diand...@chromium.org wrote:
Thomas,
On Wed, Jul 30, 2014 at 8:21 PM, Thomas Abraham ta.oma...@gmail.com wrote:
Hi Doug,
On Thu, Jul 31, 2014 at 6:07 AM, Doug Anderson diand...@chromium.org wrote:
Thomas,
On Wed, Jul 30, 2014 at 1:07 AM, Thomas Abraham thomas...@samsung.com
wrote:
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..3b12a97 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -575,3 +575,7 @@
usb-phy = usb2_phy;
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35ad..f07e834 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -414,3 +414,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index f2b8c41..91acca7 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -509,4 +509,8 @@
};
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
#include cros-ec-keyboard.dtsi
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1ef..97b282c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,11 +58,34 @@
#address-cells = 1;
#size-cells = 0;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 14;
Where did the 14 number come from? My old calculations show that
with lock time of 270 ad P up to 6 we were at 67.5us lock time.
I measured the time taken by clk_set_rate call in the cpufreq driver
using do_gettimeofday(). The time taken to change the clock speed was
between 87us to 134us for Exynos5420. So I just took the worst case
time of 140us. Also, the time taken to change the CPU clock speed
includes the settling time for changes to dividers and mux clock
blocks.
Interesting. I wonder why the difference between my earlier
calculations. It seems just about double. :-/
In your calculation, only the PLL lock time is being considered. But
the 140us latency is for the whole clk_set_rate() call.
+ operating-points =
+ 170 130
+ 160 125
+ 150 1225000
+ 140 120
+ 130 115
+ 120 1125000
+ 110 110
+ 100 1075000
+90 105
+80 1025000
+70 1012500
+60 100
+50 975000
+40 95
+30 937500
+20 925000
+ ;
};
cpu@1 {
device_type = cpu;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index cb2b70e..3154b4c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -59,8 +59,26 @@
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0x0;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu-cluster.0;
clock-frequency = 18;
cci-control-port = cci_control1;
+ clock-latency = 14;
+
+ operating-points =
+ 180 125
+ 170 1212500
+ 160 1175000
+ 150 1137500
+ 140 1112500
+ 130 1062500
+ 120 1037500
+ 110 1012500
+ 100 987500
+90 962500
+80 937500
+70 912500
+
Re: [PATCH v9 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
Thomas,
On Wed, Jul 30, 2014 at 9:06 PM, Thomas Abraham ta.oma...@gmail.com wrote:
On Thu, Jul 31, 2014 at 9:23 AM, Doug Anderson diand...@chromium.org wrote:
Thomas,
On Wed, Jul 30, 2014 at 8:21 PM, Thomas Abraham ta.oma...@gmail.com wrote:
Hi Doug,
On Thu, Jul 31, 2014 at 6:07 AM, Doug Anderson diand...@chromium.org
wrote:
Thomas,
On Wed, Jul 30, 2014 at 1:07 AM, Thomas Abraham thomas...@samsung.com
wrote:
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..3b12a97 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -575,3 +575,7 @@
usb-phy = usb2_phy;
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35ad..f07e834 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -414,3 +414,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index f2b8c41..91acca7 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -509,4 +509,8 @@
};
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
#include cros-ec-keyboard.dtsi
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1ef..97b282c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,11 +58,34 @@
#address-cells = 1;
#size-cells = 0;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 14;
Where did the 14 number come from? My old calculations show that
with lock time of 270 ad P up to 6 we were at 67.5us lock time.
I measured the time taken by clk_set_rate call in the cpufreq driver
using do_gettimeofday(). The time taken to change the clock speed was
between 87us to 134us for Exynos5420. So I just took the worst case
time of 140us. Also, the time taken to change the CPU clock speed
includes the settling time for changes to dividers and mux clock
blocks.
Interesting. I wonder why the difference between my earlier
calculations. It seems just about double. :-/
In your calculation, only the PLL lock time is being considered. But
the 140us latency is for the whole clk_set_rate() call.
+ operating-points =
+ 170 130
+ 160 125
+ 150 1225000
+ 140 120
+ 130 115
+ 120 1125000
+ 110 110
+ 100 1075000
+90 105
+80 1025000
+70 1012500
+60 100
+50 975000
+40 95
+30 937500
+20 925000
+ ;
};
cpu@1 {
device_type = cpu;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index cb2b70e..3154b4c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -59,8 +59,26 @@
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0x0;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu-cluster.0;
clock-frequency = 18;
cci-control-port = cci_control1;
+ clock-latency = 14;
+
+ operating-points =
+ 180 125
+ 170 1212500
+ 160 1175000
+ 150 1137500
+ 140 1112500
+ 130 1062500
+ 120 1037500
+ 110 1012500
+ 100 987500
+90 962500
+
Re: [PATCH v9 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
On Thu, Jul 31, 2014 at 9:38 AM, Doug Anderson diand...@chromium.org wrote:
Thomas,
On Wed, Jul 30, 2014 at 9:06 PM, Thomas Abraham ta.oma...@gmail.com wrote:
On Thu, Jul 31, 2014 at 9:23 AM, Doug Anderson diand...@chromium.org wrote:
Thomas,
On Wed, Jul 30, 2014 at 8:21 PM, Thomas Abraham ta.oma...@gmail.com wrote:
Hi Doug,
On Thu, Jul 31, 2014 at 6:07 AM, Doug Anderson diand...@chromium.org
wrote:
Thomas,
On Wed, Jul 30, 2014 at 1:07 AM, Thomas Abraham thomas...@samsung.com
wrote:
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..3b12a97 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -575,3 +575,7 @@
usb-phy = usb2_phy;
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35ad..f07e834 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -414,3 +414,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index f2b8c41..91acca7 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -509,4 +509,8 @@
};
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
#include cros-ec-keyboard.dtsi
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1ef..97b282c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,11 +58,34 @@
#address-cells = 1;
#size-cells = 0;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 14;
Where did the 14 number come from? My old calculations show that
with lock time of 270 ad P up to 6 we were at 67.5us lock time.
I measured the time taken by clk_set_rate call in the cpufreq driver
using do_gettimeofday(). The time taken to change the clock speed was
between 87us to 134us for Exynos5420. So I just took the worst case
time of 140us. Also, the time taken to change the CPU clock speed
includes the settling time for changes to dividers and mux clock
blocks.
Interesting. I wonder why the difference between my earlier
calculations. It seems just about double. :-/
In your calculation, only the PLL lock time is being considered. But
the 140us latency is for the whole clk_set_rate() call.
+ operating-points =
+ 170 130
+ 160 125
+ 150 1225000
+ 140 120
+ 130 115
+ 120 1125000
+ 110 110
+ 100 1075000
+90 105
+80 1025000
+70 1012500
+60 100
+50 975000
+40 95
+30 937500
+20 925000
+ ;
};
cpu@1 {
device_type = cpu;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index cb2b70e..3154b4c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -59,8 +59,26 @@
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0x0;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu-cluster.0;
clock-frequency = 18;
cci-control-port = cci_control1;
+ clock-latency = 14;
+
+ operating-points =
+ 180 125
+ 170 1212500
+ 160 1175000
+ 150 1137500
+ 140 1112500
+ 130 1062500
+ 120 1037500
+ 110 1012500
+
