Re: [PATCH] cpufreq: exynos5440: Protect opp search calls with rcu lock
Hi Nishanth,
Thanks for reviewing this patch.
On Mon, Apr 15, 2013 at 7:40 PM, Nishanth Menon n...@ti.com wrote:
Daniel,
On Mon, Apr 15, 2013 at 1:24 AM, Amit Daniel Kachhap
amit.dan...@samsung.com wrote:
As per the OPP library documentation(Documentation/power/opp.txt) all
opp find/get calls should be protected by rcu locks.
Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---
This patch is created against linux-next tree and is suggested by
Nishanth Menon. (https://lkml.org/lkml/2013/4/12/119)
drivers/cpufreq/exynos5440-cpufreq.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/cpufreq/exynos5440-cpufreq.c
b/drivers/cpufreq/exynos5440-cpufreq.c
index ead7ed4..0c74018 100644
--- a/drivers/cpufreq/exynos5440-cpufreq.c
+++ b/drivers/cpufreq/exynos5440-cpufreq.c
@@ -120,11 +120,13 @@ static int init_div_table(void)
int i = 0;
struct opp *opp;
+ rcu_read_lock();
for (i = 0; freq_tbl[i].frequency != CPUFREQ_TABLE_END; i++) {
opp = opp_find_freq_exact(dvfs_info-dev,
freq_tbl[i].frequency * 1000, true);
if (IS_ERR(opp)) {
+ rcu_read_unlock();
dev_err(dvfs_info-dev,
failed to find valid OPP for %u KHZ\n,
freq_tbl[i].frequency);
@@ -159,6 +161,7 @@ static int init_div_table(void)
__raw_writel(tmp, dvfs_info-base + XMU_PMU_P0_7 + 4 * i);
}
+ rcu_read_unlock();
Is it not possible to reduce the amount of code protected by RCU lock?
something like this:
Yes it is possible but then this part of code is a loop of max 8
iteration so rcu_read_lock will be called those many times.
Also this code blocks are just register writes and not doing any time
consuming operations.
Thanks,
Amit Daniel
+ rcu_read_lock();
opp = opp_find_freq_exact(dvfs_info-dev,
freq_tbl[i].frequency * 1000, true);
if (IS_ERR(opp)) {
+ rcu_read_unlock();
dev_err(dvfs_info-dev,
failed to find valid OPP for %u KHZ\n,
freq_tbl[i].frequency);
return PTR_ERR(opp);
}
+ volt_id = opp_get_voltage(opp);
+ rcu_unlock();
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Re: [PATCH v6 0/3] of/pci: Provide common support for PCI DT parsing
On Mon, 2013-04-15 at 20:29 +0200, Linus Walleij wrote: As agreed with Rob Herring, series applied to mvebu/drivers to support mvebu pcie driver. Will this hit ARM SoC soon-ish so I can base a pull request for the Integrator on this stuff as well? Do not send this series upstream (or even in -next) until it has been at least build-tested and acked by the affected architectures. AFAIK it breaks microblaze build (simple missing #include) and isn't yet tested on powerpc (I'm on vacation, maybe somebody else on linuxppc-dev can do it though). Ben. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: dts: enable spi for EXYNOS5440 SOC
This patch enables the SPI in EXYNOS5440 SoC. The NOR
Flash can be accessed by enabling the spi interface
Signed-off-by: Girish K S ks.g...@samsung.com
---
arch/arm/boot/dts/exynos5440-ssdk5440.dts | 39 +++-
arch/arm/boot/dts/exynos5440.dtsi | 16 +++
2 files changed, 47 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042b..a85ac0e 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -20,8 +20,43 @@
bootargs = root=/dev/sda2 rw rootwait ignore_loglevel
early_printk no_console_suspend mem=2048M@0x8000 console=ttySAC0,115200;
};
- spi {
- status = disabled;
+ spi_0: spi@D {
+
+ flash: w25q128@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = winbond,w25q128;
+ spi-max-frequency = 15625000;
+ reg = 0;
+ controller-data {
+ samsung,spi-feedback-delay = 0;
+ };
+
+ partition@0 {
+ label = BootLoader;
+ reg = 0x6 0x8;
+ read-only;
+ };
+
+ partition@e {
+ label = Recovery-Kernel;
+ reg = 0xe 0x30;
+ read-only;
+ };
+
+ partition@3e {
+ label = CRAM-FS;
+ reg = 0x3e 0x70;
+ read-only;
+ };
+
+ partition@ae {
+ label = User-Data;
+ reg = 0xae 0x52;
+ };
+
+ };
+
};
fixed-rate-clocks {
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..7c5dc38 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -16,6 +16,10 @@
interrupt-parent = gic;
+ aliases {
+ spi0 = spi_0;
+ };
+
clock: clock-controller@0x16 {
compatible = samsung,exynos5440-clock;
reg = 0x16 0x1000;
@@ -101,15 +105,15 @@
clock-names = uart, clk_uart_baud0;
};
- spi {
- compatible = samsung,exynos4210-spi;
- reg = 0xD 0x1000;
+ spi_0: spi@D {
+ compatible = samsung,exynos5440-spi;
+ reg = 0xD 0x100;
interrupts = 0 4 0;
- tx-dma-channel = pdma0 5; /* preliminary */
- rx-dma-channel = pdma0 4; /* preliminary */
#address-cells = 1;
#size-cells = 0;
- clocks = clock 21, clock 16;
+ samsung,spi-src-clk = 0;
+ num-cs = 1;
+ clocks = clock 8, clock 3;
clock-names = spi, spi_busclk0;
};
--
1.7.5.4
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[PATCH 2/2] ARM: dts: add dts node for the ahci sata exynos5440
This patch adds dts support for the sata controller
Signed-off-by: Girish K S ks.g...@samsung.com
---
arch/arm/boot/dts/exynos5440.dtsi |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index 7c5dc38..2dc4ffa 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -220,4 +220,13 @@
clock-names = rtc;
status = disabled;
};
+
+ sata@21 {
+ compatible = samsung,exynos5440-ahci;
+ reg = 0x21 0x1;
+ interrupts = 0 30 0;
+ clocks = clock 10;
+ clock-names = sata;
+ };
+
};
--
1.7.5.4
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[PATCH V2 2/2] ARM: dts: add dts node for the ahci sata exynos5440
This patch adds dts support for the sata controller
Signed-off-by: Girish K S ks.g...@samsung.com
---
arch/arm/boot/dts/exynos5440.dtsi |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index 7c5dc38..2dc4ffa 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -220,4 +220,13 @@
clock-names = rtc;
status = disabled;
};
+
+ sata@21 {
+ compatible = snps,exynos5440-ahci;
+ reg = 0x21 0x1;
+ interrupts = 0 30 0;
+ clocks = clock 10;
+ clock-names = sata;
+ };
+
};
--
1.7.5.4
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[PATCH 2/3] clk: exynos5250: Staticize local symbols
These symbols are used only in this file and hence should
be static.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
drivers/clk/samsung/clk-exynos5250.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 7290faa..9cdee2b 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -191,24 +191,27 @@ PNAME(mout_spdif_p) = { sclk_audio0,
sclk_audio1, sclk_audio2,
spdif_extclk };
/* fixed rate clocks generated outside the soc */
-struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
+static struct
+samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
FRATE(fin_pll, fin_pll, NULL, CLK_IS_ROOT, 0),
};
/* fixed rate clocks generated inside the soc */
-struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
+static struct
+samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
FRATE(none, sclk_hdmiphy, NULL, CLK_IS_ROOT, 2400),
FRATE(none, sclk_hdmi27m, NULL, CLK_IS_ROOT, 2700),
FRATE(none, sclk_dptxphy, NULL, CLK_IS_ROOT, 2400),
FRATE(none, sclk_uhostphy, NULL, CLK_IS_ROOT, 4800),
};
-struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
+static struct
+samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
FFACTOR(none, fout_mplldiv2, fout_mpll, 1, 2, 0),
FFACTOR(none, fout_bplldiv2, fout_bpll, 1, 2, 0),
};
-struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
MUX(none, mout_apll, mout_apll_p, SRC_CPU, 0, 1),
MUX(none, mout_cpu, mout_cpu_p, SRC_CPU, 16, 1),
MUX(none, mout_mpll_fout, mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
@@ -254,7 +257,7 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata =
{
MUX(none, mout_spi2, mout_group1_p, SRC_PERIC1, 24, 4),
};
-struct samsung_div_clock exynos5250_div_clks[] __initdata = {
+static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
DIV(none, div_arm, mout_cpu, DIV_CPU0, 0, 3),
DIV(none, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
DIV(none, aclk66_pre, sclk_mpll_user, DIV_TOP1, 24, 3),
@@ -314,7 +317,7 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata =
{
DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
};
-struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
GATE(gscl0, gscl0, none, GATE_IP_GSCL, 0, 0, 0),
GATE(gscl1, gscl1, none, GATE_IP_GSCL, 1, 0, 0),
GATE(gscl2, gscl2, aclk266, GATE_IP_GSCL, 2, 0, 0),
@@ -471,7 +474,7 @@ static __initdata struct of_device_id ext_clk_match[] = {
};
/* register exynox5250 clocks */
-void __init exynos5250_clk_init(struct device_node *np)
+static void __init exynos5250_clk_init(struct device_node *np)
{
void __iomem *reg_base;
struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
--
1.7.9.5
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[PATCH 1/3] clk: exynos4: Staticize local symbols
These symbols are used only in this file and hence should be
static.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
drivers/clk/samsung/clk-exynos4.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 7104669..26f2a85 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -339,24 +339,26 @@ PNAME(mout_user_aclk200_p4x12) = {fin_pll,
div_aclk200, };
PNAME(mout_user_aclk266_gps_p4x12) = {fin_pll, div_aclk266_gps, };
/* fixed rate clocks generated outside the soc */
-struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
+static struct
+samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
FRATE(xxti, xxti, NULL, CLK_IS_ROOT, 0),
FRATE(xusbxti, xusbxti, NULL, CLK_IS_ROOT, 0),
};
/* fixed rate clocks generated inside the soc */
-struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
+static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
FRATE(none, sclk_hdmi24m, NULL, CLK_IS_ROOT, 2400),
FRATE(none, sclk_hdmiphy, NULL, CLK_IS_ROOT, 2700),
FRATE(none, sclk_usbphy0, NULL, CLK_IS_ROOT, 4800),
};
-struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
+static struct
+samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
FRATE(none, sclk_usbphy1, NULL, CLK_IS_ROOT, 4800),
};
/* list of mux clocks supported in all exynos4 soc's */
-struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
MUX_F(mout_apll, mout_apll, mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT, 0),
MUX(none, mout_hdmi, mout_hdmi_p, SRC_TV, 0, 1),
@@ -373,7 +375,7 @@ struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
};
/* list of mux clocks supported in exynos4210 soc */
-struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
MUX(none, mout_aclk200, sclk_ampll_p4210, SRC_TOP0, 12, 1),
MUX(none, mout_aclk100, sclk_ampll_p4210, SRC_TOP0, 16, 1),
MUX(none, mout_aclk160, sclk_ampll_p4210, SRC_TOP0, 20, 1),
@@ -424,7 +426,7 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata =
{
};
/* list of mux clocks supported in exynos4x12 soc */
-struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
MUX(mout_mpll_user_c, mout_mpll_user_c, mout_mpll_user_p4x12,
SRC_CPU, 24, 1),
MUX(none, mout_aclk266_gps, aclk_p4412, SRC_TOP1, 4, 1),
@@ -488,7 +490,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata =
{
};
/* list of divider clocks supported in all exynos4 soc's */
-struct samsung_div_clock exynos4_div_clks[] __initdata = {
+static struct samsung_div_clock exynos4_div_clks[] __initdata = {
DIV(none, div_core, mout_core, DIV_CPU0, 0, 3),
DIV(none, div_core2, div_core, DIV_CPU0, 28, 3),
DIV(none, div_fimc0, mout_fimc0, DIV_CAM, 0, 4),
@@ -551,7 +553,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
};
/* list of divider clocks supported in exynos4210 soc */
-struct samsung_div_clock exynos4210_div_clks[] __initdata = {
+static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
DIV(aclk200, aclk200, mout_aclk200, DIV_TOP, 0, 3),
DIV(none, div_g2d, mout_g2d, DIV_IMAGE, 0, 4),
DIV(none, div_fimd1, mout_fimd1, E4210_DIV_LCD1, 0, 4),
@@ -562,7 +564,7 @@ struct samsung_div_clock exynos4210_div_clks[] __initdata =
{
};
/* list of divider clocks supported in exynos4x12 soc */
-struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
+static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
DIV(none, div_mdnie0, mout_mdnie0, DIV_LCD0, 4, 4),
DIV(none, div_mdnie_pwm0, mout_mdnie_pwm0, DIV_LCD0, 8, 4),
DIV(none, div_mdnie_pwm_pre0, div_mdnie_pwm0, DIV_LCD0, 12, 4),
@@ -586,7 +588,7 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata =
{
};
/* list of gate clocks supported in all exynos4 soc's */
-struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
/*
* After all Exynos4 based platforms are migrated to use device tree,
* the device name and clock alias names specified below for some
@@ -778,7 +780,7 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
};
/* list of gate clocks supported in exynos4210 soc */
-struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
GATE(tvenc, tvenc, aclk160, GATE_IP_TV, 2, 0, 0),
[PATCH 3/3] clk: exynos5440: Staticize local symbols
These symbols are used only in this file and hence should be
static.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
drivers/clk/samsung/clk-exynos5440.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5440.c
b/drivers/clk/samsung/clk-exynos5440.c
index a0a094c..ac6c95f 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -42,12 +42,14 @@ PNAME(mout_armclk_p)= { cplla, cpllb };
PNAME(mout_spi_p) = { div125, div200 };
/* fixed rate clocks generated outside the soc */
-struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
+static struct
+samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
FRATE(none, xtal, NULL, CLK_IS_ROOT, 0),
};
/* fixed rate clocks */
-struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
+static struct
+samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
FRATE(none, ppll, NULL, CLK_IS_ROOT, 10),
FRATE(none, usb_phy0, NULL, CLK_IS_ROOT, 6000),
FRATE(none, usb_phy1, NULL, CLK_IS_ROOT, 6000),
@@ -56,26 +58,27 @@ struct samsung_fixed_rate_clock
exynos5440_fixed_rate_clks[] __initdata = {
};
/* fixed factor clocks */
-struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
+static struct
+samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
FFACTOR(none, div250, ppll, 1, 4, 0),
FFACTOR(none, div200, ppll, 1, 5, 0),
FFACTOR(none, div125, div250, 1, 2, 0),
};
/* mux clocks */
-struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
MUX(none, mout_spi, mout_spi_p, MISC_DOUT1, 5, 1),
MUX_A(arm_clk, arm_clk, mout_armclk_p,
CPU_CLK_STATUS, 0, 1, armclk),
};
/* divider clocks */
-struct samsung_div_clock exynos5440_div_clks[] __initdata = {
+static struct samsung_div_clock exynos5440_div_clks[] __initdata = {
DIV(spi_baud, div_spi, mout_spi, MISC_DOUT1, 3, 2),
};
/* gate clocks */
-struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
GATE(pb0_250, pb0_250, div250, CLKEN_OV_VAL, 3, 0, 0),
GATE(pr0_250, pr0_250, div250, CLKEN_OV_VAL, 4, 0, 0),
GATE(pr1_250, pr1_250, div250, CLKEN_OV_VAL, 5, 0, 0),
@@ -104,7 +107,7 @@ static __initdata struct of_device_id ext_clk_match[] = {
};
/* register exynos5440 clocks */
-void __init exynos5440_clk_init(struct device_node *np)
+static void __init exynos5440_clk_init(struct device_node *np)
{
void __iomem *reg_base;
--
1.7.9.5
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[PATCH v7 0/3] of/pci: Provide common support for PCI DT parsing
This patchset factors out duplicated code associated with parsing PCI DT ranges properties across the architectures and introduces a ranges parser. This parser of_pci_range_parser can be used directly by ARM host bridge drivers enabling them to obtain ranges from device trees. I've included the Reviewed-by and Tested-by's received from v5/v6 in this patchset, earlier versions of this patchset (v3) have been tested-by: Thierry Reding thierry.red...@avionic-design.de Jingoo Han jg1@samsung.com I've tested that this patchset builds and runs on ARM and that it builds on PowerPC and x86_64. Compared to the v6 sent by Andrew Murray, the following changes have been made in response to build errors/warnings: * Inclusion of linux/of_address.h in of_pci.c as suggested by Michal Simek to prevent compilation failures on Microblaze (and others) and his ack. * Use of externs, static inlines and a typo in linux/of_address.h in response to linker errors (multiple defination) on x86_64 as spotted by a kbuild test robot on (jcooper/linux.git mvebu/drivers) * Add EXPORT_SYMBOL_GPL to of_pci_range_parser function to be consistent with of_pci_process_ranges function Compared to the v5 sent by Andrew Murray, the following changes have been made: * Use of CONFIG_64BIT instead of CONFIG_[a32bitarch] as suggested by Rob Herring in drivers/of/of_pci.c * Added forward declaration of struct pci_controller in linux/of_pci.h to prevent compiler warning as suggested by Thomas Petazzoni * Improved error checking (!range check), removal of unnecessary be32_to_cpup call, improved formatting of struct of_pci_range_parser layout and replacement of macro with a static inline. All suggested by Rob Herring. Compared to the v4 (incorrectly labelled v3) sent by Andrew Murray, the following changes have been made: * Split the patch as suggested by Rob Herring Compared to the v3 sent by Andrew Murray, the following changes have been made: * Unify and move duplicate pci_process_bridge_OF_ranges functions to drivers/of/of_pci.c as suggested by Rob Herring * Fix potential build errors with Microblaze/MIPS Compared to [PATCH v5 01/17] of/pci: Provide support for parsing PCI DT ranges property, the following changes have been made: * Correct use of IORESOURCE_* as suggested by Russell King * Improved interface and naming as suggested by Thierry Reding Compared to the v2 sent by Andrew Murray, Thomas Petazzoni did: * Add a memset() on the struct of_pci_range_iter when starting the for loop in for_each_pci_range(). Otherwise, with an uninitialized of_pci_range_iter, of_pci_process_ranges() may crash. * Add parenthesis around 'res', 'np' and 'iter' in the for_each_of_pci_range macro definitions. Otherwise, passing something like foobar as 'res' didn't work. * Rebased on top of 3.9-rc2, which required fixing a few conflicts in the Microblaze code. v2: This follows on from suggestions made by Grant Likely (marc.info/?l=linux-kernelm=136079602806328) Andrew Murray (3): of/pci: Unify pci_process_bridge_OF_ranges from Microblaze and PowerPC of/pci: Provide support for parsing PCI DT ranges property of/pci: mips: convert to common of_pci_range_parser arch/microblaze/include/asm/pci-bridge.h |5 +- arch/microblaze/pci/pci-common.c | 192 -- arch/mips/pci/pci.c | 50 +++-- arch/powerpc/include/asm/pci-bridge.h|5 +- arch/powerpc/kernel/pci-common.c | 192 -- drivers/of/address.c | 67 +++ drivers/of/of_pci.c | 169 ++ include/linux/of_address.h | 46 +++ include/linux/of_pci.h |4 + 9 files changed, 304 insertions(+), 426 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 3/3] of/pci: mips: convert to common of_pci_range_parser
This patch converts the pci_load_of_ranges function to use the new common
of_pci_range_parser.
Signed-off-by: Andrew Murray andrew.mur...@arm.com
Signed-off-by: Liviu Dudau liviu.du...@arm.com
Reviewed-by: Rob Herring rob.herr...@calxeda.com
---
arch/mips/pci/pci.c | 50 --
1 files changed, 16 insertions(+), 34 deletions(-)
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 0872f12..bee49a4 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -122,51 +122,33 @@ static void pcibios_scanbus(struct pci_controller *hose)
#ifdef CONFIG_OF
void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
{
- const __be32 *ranges;
- int rlen;
- int pna = of_n_addr_cells(node);
- int np = pna + 5;
+ struct of_pci_range_range range;
+ struct of_pci_range_parser parser;
+ u32 res_type;
pr_info(PCI host bridge %s ranges:\n, node-full_name);
- ranges = of_get_property(node, ranges, rlen);
- if (ranges == NULL)
- return;
hose-of_node = node;
- while ((rlen -= np * 4) = 0) {
- u32 pci_space;
+ if (of_pci_range_parser(parser, node))
+ return;
+
+ for_each_of_pci_range(parser, range) {
struct resource *res = NULL;
- u64 addr, size;
-
- pci_space = be32_to_cpup(ranges[0]);
- addr = of_translate_address(node, ranges + 3);
- size = of_read_number(ranges + pna + 3, 2);
- ranges += np;
- switch ((pci_space 24) 0x3) {
- case 1: /* PCI IO space */
+
+ res_type = range.flags IORESOURCE_TYPE_BITS;
+ if (res_type == IORESOURCE_IO) {
pr_info( IO 0x%016llx..0x%016llx\n,
- addr, addr + size - 1);
+ range.addr, range.addr + range.size - 1);
hose-io_map_base =
- (unsigned long)ioremap(addr, size);
+ (unsigned long)ioremap(range.addr, range.size);
res = hose-io_resource;
- res-flags = IORESOURCE_IO;
- break;
- case 2: /* PCI Memory space */
- case 3: /* PCI 64 bits Memory space */
+ } else if (res_type == IORESOURCE_MEM) {
pr_info( MEM 0x%016llx..0x%016llx\n,
- addr, addr + size - 1);
+ range.addr, range.addr + range.size - 1);
res = hose-mem_resource;
- res-flags = IORESOURCE_MEM;
- break;
- }
- if (res != NULL) {
- res-start = addr;
- res-name = node-full_name;
- res-end = res-start + size - 1;
- res-parent = NULL;
- res-sibling = NULL;
- res-child = NULL;
}
+ if (res != NULL)
+ of_pci_range_to_resource(range, node, res);
}
}
#endif
--
1.7.0.4
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[PATCH v7 2/3] of/pci: Provide support for parsing PCI DT ranges property
This patch factors out common implementation patterns to reduce overall kernel
code and provide a means for host bridge drivers to directly obtain struct
resources from the DT's ranges property without relying on architecture specific
DT handling. This will make it easier to write archiecture independent host
bridge
drivers and mitigate against further duplication of DT parsing code.
This patch can be used in the following way:
struct of_pci_range_parser parser;
struct of_pci_range range;
if (of_pci_range_parser(parser, np))
; //no ranges property
for_each_of_pci_range(parser, range) {
/*
directly access properties of the address range, e.g.:
range.pci_space, range.pci_addr, range.cpu_addr,
range.size, range.flags
alternatively obtain a struct resource, e.g.:
struct resource res;
of_pci_range_to_resource(range, np, res);
*/
}
Additionally the implementation takes care of adjacent ranges and merges them
into a single range (as was the case with powerpc and microblaze).
Signed-off-by: Andrew Murray andrew.mur...@arm.com
Signed-off-by: Liviu Dudau liviu.du...@arm.com
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Reviewed-by: Rob Herring rob.herr...@calxeda.com
Tested-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Tested-by: Linus Walleij linus.wall...@linaro.org
---
drivers/of/address.c | 67 ++
drivers/of/of_pci.c| 113
include/linux/of_address.h | 46 ++
3 files changed, 154 insertions(+), 72 deletions(-)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 04da786..6eec70c 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -227,6 +227,73 @@ int of_pci_address_to_resource(struct device_node *dev,
int bar,
return __of_address_to_resource(dev, addrp, size, flags, NULL, r);
}
EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
+
+int of_pci_range_parser(struct of_pci_range_parser *parser,
+ struct device_node *node)
+{
+ const int na = 3, ns = 2;
+ int rlen;
+
+ parser-node = node;
+ parser-pna = of_n_addr_cells(node);
+ parser-np = parser-pna + na + ns;
+
+ parser-range = of_get_property(node, ranges, rlen);
+ if (parser-range == NULL)
+ return -ENOENT;
+
+ parser-end = parser-range + rlen / sizeof(__be32);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(of_pci_range_parser);
+
+struct of_pci_range *of_pci_process_ranges(struct of_pci_range_parser *parser,
+ struct of_pci_range *range)
+{
+ const int na = 3, ns = 2;
+
+ if (!range)
+ return NULL;
+
+ if (!parser-range || parser-range + parser-np parser-end)
+ return NULL;
+
+ range-pci_space = parser-range[0];
+ range-flags = of_bus_pci_get_flags(parser-range);
+ range-pci_addr = of_read_number(parser-range + 1, ns);
+ range-cpu_addr = of_translate_address(parser-node,
+ parser-range + na);
+ range-size = of_read_number(parser-range + parser-pna + na, ns);
+
+ parser-range += parser-np;
+
+ /* Now consume following elements while they are contiguous */
+ while (parser-range + parser-np = parser-end) {
+ u32 flags, pci_space;
+ u64 pci_addr, cpu_addr, size;
+
+ pci_space = be32_to_cpup(parser-range);
+ flags = of_bus_pci_get_flags(parser-range);
+ pci_addr = of_read_number(parser-range + 1, ns);
+ cpu_addr = of_translate_address(parser-node,
+ parser-range + na);
+ size = of_read_number(parser-range + parser-pna + na, ns);
+
+ if (flags != range-flags)
+ break;
+ if (pci_addr != range-pci_addr + range-size ||
+ cpu_addr != range-cpu_addr + range-size)
+ break;
+
+ range-size += size;
+ parser-range += parser-np;
+ }
+
+ return range;
+}
+EXPORT_SYMBOL_GPL(of_pci_process_ranges);
+
#endif /* CONFIG_PCI */
/*
diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 1626172..e5ab604 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -2,6 +2,7 @@
#include linux/export.h
#include linux/of.h
#include linux/of_pci.h
+#include linux/of_address.h
#include asm/prom.h
#if defined(CONFIG_PPC32) || defined(CONFIG_PPC64) ||
defined(CONFIG_MICROBLAZE)
@@ -82,67 +83,43 @@ EXPORT_SYMBOL_GPL(of_pci_find_child_device);
void pci_process_bridge_OF_ranges(struct pci_controller *hose,
struct device_node *dev, int primary)
[PATCH v7 1/3] of/pci: Unify pci_process_bridge_OF_ranges from Microblaze and PowerPC
The pci_process_bridge_OF_ranges function, used to parse the ranges
property of a PCI host device, is found in both Microblaze and PowerPC
architectures. These implementations are nearly identical. This patch
moves this common code to a common place.
Signed-off-by: Andrew Murray andrew.mur...@arm.com
Signed-off-by: Liviu Dudau liviu.du...@arm.com
Reviewed-by: Rob Herring rob.herr...@calxeda.com
Tested-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Tested-by: Linus Walleij linus.wall...@linaro.org
Acked-by: Michal Simek mon...@monstr.eu
---
arch/microblaze/include/asm/pci-bridge.h |5 +-
arch/microblaze/pci/pci-common.c | 192
arch/powerpc/include/asm/pci-bridge.h|5 +-
arch/powerpc/kernel/pci-common.c | 192
drivers/of/of_pci.c | 200 ++
include/linux/of_pci.h |4 +
6 files changed, 206 insertions(+), 392 deletions(-)
diff --git a/arch/microblaze/include/asm/pci-bridge.h
b/arch/microblaze/include/asm/pci-bridge.h
index cb5d397..5783cd6 100644
--- a/arch/microblaze/include/asm/pci-bridge.h
+++ b/arch/microblaze/include/asm/pci-bridge.h
@@ -10,6 +10,7 @@
#include linux/pci.h
#include linux/list.h
#include linux/ioport.h
+#include linux/of_pci.h
struct device_node;
@@ -132,10 +133,6 @@ extern void setup_indirect_pci(struct pci_controller *hose,
extern struct pci_controller *pci_find_hose_for_OF_device(
struct device_node *node);
-/* Fill up host controller resources from the OF node */
-extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
- struct device_node *dev, int primary);
-
/* Allocate free a PCI host bridge structure */
extern struct pci_controller *pcibios_alloc_controller(struct device_node
*dev);
extern void pcibios_free_controller(struct pci_controller *phb);
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 9ea521e..2735ad9 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -622,198 +622,6 @@ void pci_resource_to_user(const struct pci_dev *dev, int
bar,
*end = rsrc-end - offset;
}
-/**
- * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
- * @hose: newly allocated pci_controller to be setup
- * @dev: device node of the host bridge
- * @primary: set if primary bus (32 bits only, soon to be deprecated)
- *
- * This function will parse the ranges property of a PCI host bridge device
- * node and setup the resource mapping of a pci controller based on its
- * content.
- *
- * Life would be boring if it wasn't for a few issues that we have to deal
- * with here:
- *
- * - We can only cope with one IO space range and up to 3 Memory space
- * ranges. However, some machines (thanks Apple !) tend to split their
- * space into lots of small contiguous ranges. So we have to coalesce.
- *
- * - We can only cope with all memory ranges having the same offset
- * between CPU addresses and PCI addresses. Unfortunately, some bridges
- * are setup for a large 1:1 mapping along with a small window which
- * maps PCI address 0 to some arbitrary high address of the CPU space in
- * order to give access to the ISA memory hole.
- * The way out of here that I've chosen for now is to always set the
- * offset based on the first resource found, then override it if we
- * have a different offset and the previous was set by an ISA hole.
- *
- * - Some busses have IO space not starting at 0, which causes trouble with
- * the way we do our IO resource renumbering. The code somewhat deals with
- * it for 64 bits but I would expect problems on 32 bits.
- *
- * - Some 32 bits platforms such as 4xx can have physical space larger than
- * 32 bits so we need to use 64 bits values for the parsing
- */
-void pci_process_bridge_OF_ranges(struct pci_controller *hose,
- struct device_node *dev, int primary)
-{
- const u32 *ranges;
- int rlen;
- int pna = of_n_addr_cells(dev);
- int np = pna + 5;
- int memno = 0, isa_hole = -1;
- u32 pci_space;
- unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
- unsigned long long isa_mb = 0;
- struct resource *res;
-
- pr_info(PCI host bridge %s %s ranges:\n,
- dev-full_name, primary ? (primary) : );
-
- /* Get ranges property */
- ranges = of_get_property(dev, ranges, rlen);
- if (ranges == NULL)
- return;
-
- /* Parse it */
- pr_debug(Parsing ranges property...\n);
- while ((rlen -= np * 4) = 0) {
- /* Read next ranges element */
- pci_space = ranges[0];
- pci_addr = of_read_number(ranges + 1, 2);
- cpu_addr = of_translate_address(dev, ranges + 3);
-
Re: [REPOST PATCH] spi: s3c64xx: let device core setup the default pin configuration
On Mon, 15 Apr 2013 20:42:57 -0700, Doug Anderson diand...@chromium.org wrote: From: Thomas Abraham thomas.abra...@linaro.org With device core now able to setup the default pin configuration, the pin configuration code based on the deprecated Samsung specific gpio bindings is removed. Signed-off-by: Thomas Abraham thomas.abra...@linaro.org Signed-off-by: Doug Anderson diand...@chromium.org Acked-by: Linus Walleij linus.wall...@linaro.org Reviewed-by: Doug Anderson diand...@chromium.org Tested-by: Doug Anderson diand...@chromium.org Applied, thanks. g. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7] i2c: exynos5: add High Speed I2C controller driver
Hi,
thanks for the submission.
On Thu, Apr 04, 2013 at 09:52:01PM -0700, Naveen Krishna Chatradhi wrote:
From: Naveen Krishna Chatradhi ch.nav...@samsung.com
Adds support for High Speed I2C driver found in Exynos5 and
later SoCs from Samsung.
This driver currently supports Auto mode.
Either explain the limitation of this mode or just leave this sentence.
Driver only supports Device Tree method.
Note: Added debugfs support for registers view, not tested.
Then leave it out, please.
Signed-off-by: Taekgyun Ko taeggyun...@samsung.com
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Reviewed-by: Simon Glass s...@google.com
Tested-by: Andrew Bresticker abres...@google.com
---
change since v6:
1. clock divisor function hs split to handle the error cases
2. Other irq types are handled
3. FIFO are handled more efficiently in TX and RX
4. More function description added
5. handled the return cases in xfer_msg function
.../devicetree/bindings/i2c/i2c-exynos5.txt| 50 ++
drivers/i2c/busses/Kconfig |7 +
drivers/i2c/busses/Makefile|1 +
drivers/i2c/busses/i2c-exynos5.c | 934
4 files changed, 992 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
create mode 100644 drivers/i2c/busses/i2c-exynos5.c
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
new file mode 100644
index 000..0bc9347
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@@ -0,0 +1,50 @@
+* Samsung's High Speed I2C controller
+
+The Samsung's High Speed I2C controller is used to interface with I2C devices
+at various speeds ranging from 100khz to 3.4Mhz.
+
+Required properties:
+ - compatible: value should be.
+ (a) samsung,exynos5-hsi2c, for i2c compatible with exynos5 hsi2c.
+ - reg: physical base address of the controller and length of memory mapped
+region.
+ - interrupts: interrupt number to the cpu.
+
+ - Samsung GPIO variant (deprecated):
+- gpios: The order of the gpios should be the following: SDA, SCL.
+ The gpio specifier depends on the gpio controller.
Huh? Why should we support a deprecated method with a new driver?
+ - Pinctrl variant (preferred, if available):
+- pinctrl-0: Pin control group to be used for this controller.
+- pinctrl-names: Should contain only one value - default.
+
+Optional properties:
+ - samsung,hs-mode: Mode of operation, High speed or Fast speed mode. If not
+specified, default value is 0.
+ - samsung,hs-clock-freq: Desired operating frequency in Hz of the bus.
+If not specified, the default value in Hz is 10.
+ - samsung,fs-clock-freq: Desired operarting frequency in Hz of the bus.
+If not specified, the default value in Hz is 10.
NACK! We have a generic binding for defining the bus speed. And
shouldn't hs-mode be set depending on the bus speed?
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index adfee98..9fbfa01 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -434,6 +434,13 @@ config I2C_EG20T
ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
+config I2C_EXYNOS5
+ tristate Exynos5 high-speed I2C driver
+ depends on ARCH_EXYNOS5 OF
+ help
+ Say Y here to include support for High-speed I2C controller in the
+ Exynos5 based Samsung SoCs.
s/High/high/
+struct exynos5_i2c {
+ struct i2c_adapter adap;
+ unsigned intsuspended:1;
+
+ struct i2c_msg *msg;
+ struct completion msg_complete;
+ unsigned intmsg_ptr;
+ unsigned intmsg_len;
+
+ unsigned intirq;
+
+ void __iomem*regs;
+ struct clk *clk;
+ struct device *dev;
+ int state;
+
+ /* GPIO lines for SDA/SCL*/
+ int gpios[2];
+
+ /* Controller operating frequency */
+ unsigned intclock;
+ unsigned intclk_cycle;
+ unsigned intclk_div;
+
+ /* HSI2C Controller can operate in
+ * 1. High speed upto 3.4Mbps
+ * 2. Fast speed upto 1Mbps
+ */
+ int speed_mode;
+};
Only one space as indentation after the type, please.
+
+static const struct of_device_id exynos5_i2c_match[] = {
+ { .compatible = samsung,exynos5-hsi2c },
+ {},
+};
+MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
+
+static inline void exynos5_i2c_stop(struct exynos5_i2c *i2c)
+{
+ writel(0, i2c-regs + HSI2C_INT_ENABLE);
+
+ complete(i2c-msg_complete);
+}
I wonder if this needs to be a seperate
Re: [PATCH v6 0/3] of/pci: Provide common support for PCI DT parsing
On Tue, Apr 16, 2013 at 01:31:40PM +0200, Thomas Petazzoni wrote: Dear Jason Cooper, On Tue, 16 Apr 2013 07:29:51 -0400, Jason Cooper wrote: Do not send this series upstream (or even in -next) until it has been at least build-tested and acked by the affected architectures. AFAIK it breaks microblaze build (simple missing #include) and isn't yet tested on powerpc (I'm on vacation, maybe somebody else on linuxppc-dev can do it though). I added the missing include reference by Michal Simek for the branch at mvebu/drivers. Some other build issues were reported on x86 during the night (thanks to automated build tests), and Andrew Murray has just sent a new version v7 of the patch set addressing those issues, as well as the missing include. Also, please note that Andrew's patch set contains three patches, but the Marvell PCIe driver only requires PATCH 1/3 and PATCH 2/3. Ok. Thanks Andrew! Do you (AndrewM) want me to keep the series together? Or drop 3/3 from my tree? I can do either, I just need to know. thx, Jason. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 5/6] ARM: dts: Add basic dts include files for Samsung S3C64xx SoCs
On 04/15/2013 04:14 PM, Tomasz Figa wrote:
This patch adds basic device tree definitions for Samsung S3C64xx SoCs.
Since all the SoCs in the series are very similar, the files are created
hierarchically - one file for the whole series and then separate files
for particular SoCs including the common one.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
arch/arm/boot/dts/s3c6400.dtsi | 33 ++
arch/arm/boot/dts/s3c6410.dtsi | 33 ++
arch/arm/boot/dts/s3c64xx-pinctrl.dtsi | 683
+
arch/arm/boot/dts/s3c64xx.dtsi | 136 +++
4 files changed, 885 insertions(+)
create mode 100644 arch/arm/boot/dts/s3c6400.dtsi
create mode 100644 arch/arm/boot/dts/s3c6410.dtsi
create mode 100644 arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/s3c64xx.dtsi
[...]
+
+ vic0: interrupt-controller@7120 {
These nodes should be off a simple-bus node.
Rob
+ compatible = arm,pl192-vic;
+ interrupt-controller;
+ reg = 0x7120 0x1000;
+ #interrupt-cells = 1;
+ };
+
+ vic1: interrupt-controller@7130 {
+ compatible = arm,pl192-vic;
+ interrupt-controller;
+ reg = 0x7130 0x1000;
+ #interrupt-cells = 1;
+ };
+
+ pinctrl0: pinctrl@7f008000 {
+ compatible = samsung,s3c64xx-pinctrl;
+ reg = 0x7f008000 0x1000;
+ interrupt-parent = vic1;
+ interrupts = 21;
+
+ pctrl_int_map: pinctrl-interrupt-map {
+ interrupt-map = 0 vic0 0,
+ 1 vic0 1,
+ 2 vic1 0,
+ 3 vic1 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 1;
+ };
+
+ wakeup-interrupt-controller {
+ compatible = samsung,s3c64xx-wakeup-eint;
+ interrupts = 0, 1, 2, 3;
+ interrupt-parent = pctrl_int_map;
+ };
+ };
+
+ pwm: pwm@7f006000 {
+ compatible = samsung,s3c6400-pwm;
+ reg = 0x7f006000 0x1000;
+ interrupt-parent = vic0;
+ interrupts = 23, 24, 25, 27, 28;
+ samsung,pwm-outputs = 0, 1;
+ #pwm-cells = 3;
+ status = disabled;
+ };
+
+ uart0: serial@7f005000 {
+ compatible = samsung,s3c6400-uart;
+ reg = 0x7f005000 0x100;
+ interrupt-parent = vic1;
+ interrupts = 5;
+ status = disabled;
+ };
+
+ uart1: serial@7f005400 {
+ compatible = samsung,s3c6400-uart;
+ reg = 0x7f005400 0x100;
+ interrupt-parent = vic1;
+ interrupts = 6;
+ status = disabled;
+ };
+
+ uart2: serial@7f005800 {
+ compatible = samsung,s3c6400-uart;
+ reg = 0x7f005800 0x100;
+ interrupt-parent = vic1;
+ interrupts = 7;
+ status = disabled;
+ };
+
+ uart3: serial@7f005c00 {
+ compatible = samsung,s3c6400-uart;
+ reg = 0x7f005c00 0x100;
+ interrupt-parent = vic1;
+ interrupts = 8;
+ status = disabled;
+ };
+
+ sdhci0: sdhci@7c20 {
+ compatible = samsung,s3c6410-sdhci;
+ reg = 0x7c20 0x100;
+ interrupt-parent = vic1;
+ interrupts = 24;
+ status = disabled;
+ };
+
+ sdhci1: sdhci@7c30 {
+ compatible = samsung,s3c6410-sdhci;
+ reg = 0x7c30 0x100;
+ interrupt-parent = vic1;
+ interrupts = 25;
+ status = disabled;
+ };
+
+ sdhci2: sdhci@7c40 {
+ compatible = samsung,s3c6410-sdhci;
+ reg = 0x7c40 0x100;
+ interrupt-parent = vic1;
+ interrupts = 17;
+ status = disabled;
+ };
+};
+
+/include/ s3c64xx-pinctrl.dtsi
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Re: [PATCH v5 5/6] ARM: dts: Add basic dts include files for Samsung S3C64xx SoCs
On Tuesday 16 of April 2013 08:09:10 Rob Herring wrote:
On 04/15/2013 04:14 PM, Tomasz Figa wrote:
This patch adds basic device tree definitions for Samsung S3C64xx SoCs.
Since all the SoCs in the series are very similar, the files are created
hierarchically - one file for the whole series and then separate files
for particular SoCs including the common one.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
arch/arm/boot/dts/s3c6400.dtsi | 33 ++
arch/arm/boot/dts/s3c6410.dtsi | 33 ++
arch/arm/boot/dts/s3c64xx-pinctrl.dtsi | 683
+ arch/arm/boot/dts/s3c64xx.dtsi
| 136 +++
4 files changed, 885 insertions(+)
create mode 100644 arch/arm/boot/dts/s3c6400.dtsi
create mode 100644 arch/arm/boot/dts/s3c6410.dtsi
create mode 100644 arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/s3c64xx.dtsi
[...]
+
+ vic0: interrupt-controller@7120 {
These nodes should be off a simple-bus node.
Hmm, is there any reason behind it?
I thought simple bus was just a convenient helper to represent hierarchical
bus structures if one has a need to do so.
Best regards,
Tomasz
Rob
+ compatible = arm,pl192-vic;
+ interrupt-controller;
+ reg = 0x7120 0x1000;
+ #interrupt-cells = 1;
+ };
+
+ vic1: interrupt-controller@7130 {
+ compatible = arm,pl192-vic;
+ interrupt-controller;
+ reg = 0x7130 0x1000;
+ #interrupt-cells = 1;
+ };
+
+ pinctrl0: pinctrl@7f008000 {
+ compatible = samsung,s3c64xx-pinctrl;
+ reg = 0x7f008000 0x1000;
+ interrupt-parent = vic1;
+ interrupts = 21;
+
+ pctrl_int_map: pinctrl-interrupt-map {
+ interrupt-map = 0 vic0 0,
+ 1 vic0 1,
+ 2 vic1 0,
+ 3 vic1 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 1;
+ };
+
+ wakeup-interrupt-controller {
+ compatible = samsung,s3c64xx-wakeup-eint;
+ interrupts = 0, 1, 2, 3;
+ interrupt-parent = pctrl_int_map;
+ };
+ };
+
+ pwm: pwm@7f006000 {
+ compatible = samsung,s3c6400-pwm;
+ reg = 0x7f006000 0x1000;
+ interrupt-parent = vic0;
+ interrupts = 23, 24, 25, 27, 28;
+ samsung,pwm-outputs = 0, 1;
+ #pwm-cells = 3;
+ status = disabled;
+ };
+
+ uart0: serial@7f005000 {
+ compatible = samsung,s3c6400-uart;
+ reg = 0x7f005000 0x100;
+ interrupt-parent = vic1;
+ interrupts = 5;
+ status = disabled;
+ };
+
+ uart1: serial@7f005400 {
+ compatible = samsung,s3c6400-uart;
+ reg = 0x7f005400 0x100;
+ interrupt-parent = vic1;
+ interrupts = 6;
+ status = disabled;
+ };
+
+ uart2: serial@7f005800 {
+ compatible = samsung,s3c6400-uart;
+ reg = 0x7f005800 0x100;
+ interrupt-parent = vic1;
+ interrupts = 7;
+ status = disabled;
+ };
+
+ uart3: serial@7f005c00 {
+ compatible = samsung,s3c6400-uart;
+ reg = 0x7f005c00 0x100;
+ interrupt-parent = vic1;
+ interrupts = 8;
+ status = disabled;
+ };
+
+ sdhci0: sdhci@7c20 {
+ compatible = samsung,s3c6410-sdhci;
+ reg = 0x7c20 0x100;
+ interrupt-parent = vic1;
+ interrupts = 24;
+ status = disabled;
+ };
+
+ sdhci1: sdhci@7c30 {
+ compatible = samsung,s3c6410-sdhci;
+ reg = 0x7c30 0x100;
+ interrupt-parent = vic1;
+ interrupts = 25;
+ status = disabled;
+ };
+
+ sdhci2: sdhci@7c40 {
+ compatible = samsung,s3c6410-sdhci;
+ reg = 0x7c40 0x100;
+ interrupt-parent = vic1;
+ interrupts = 17;
+ status = disabled;
+ };
+};
+
+/include/ s3c64xx-pinctrl.dtsi
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--
Tomasz Figa
Samsung Poland RD Center
SW Solution Development, Kernel and System Framework
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Re: [PATCH v5 00/14] ARM: samsung-time: Prepare for multiplatform support
On Fri, Apr 12, 2013 at 09:17:16PM +0200, Tomasz Figa wrote: This series is an attempt to make the samsung-time clocksource driver ready for multiplatform kernels. It moves the driver to drivers/clocksource, cleans it up from uses of static platform-specific definitions, simplifies timer interrupt handling and adds Device Tree support. Tested-by: Mark Brown broo...@opensource.wolfsonmicro.com signature.asc Description: Digital signature
Re: [PATCH v5 2/6] ARM: s3c64xx: Skip legacy EINT setup if pinctrl-s3c64xx driver is present
On Mon, Apr 15, 2013 at 11:14:39PM +0200, Tomasz Figa wrote: + * This gpio driver includes support for device tree support and there + * are platforms using it. In order to maintain compatibility with those + * platforms, and to allow non-dt Exynos4210 platforms to use this + * gpiolib support, a check is added to find out if there is a active Cut'n'paste error here. signature.asc Description: Digital signature
Re: [PATCH v5 3/6] gpio: samsung: Skip legacy GPIO registration if pinctrl-s3c64xx is present
On Mon, Apr 15, 2013 at 11:14:40PM +0200, Tomasz Figa wrote:
{ .compatible = samsung,exynos4x12-pinctrl, },
{ .compatible = samsung,exynos5250-pinctrl, },
{ .compatible = samsung,exynos5440-pinctrl, },
+ { },
Strictly speaking this is a separate bug fix (though I see that's
already in -next separately anyway so whatever).
signature.asc
Description: Digital signature
[PATCH 0/3] drm/exynos: Add device tree support for IPP driver
Hi Inki, This small patch series adds device tree support for the DRM FIMC driver. The binding documentation can be found in -next at Documentation/devicetree/ bindings/media/samsung-fimc.txt. It will make the driver dependent on OF. This patch series is needed in 3.10 to ensure simultaneous operation of the DRM FIMC and the camera ISP on Exynos4x12. Thanks, Sylwester Sylwester Nawrocki (3): drm/exynos: Remove redundant devm_kfree() drm/exynos: Rework fimc clocks handling drm/exynos: Add device tree support for fimc ipp driver drivers/gpu/drm/exynos/Kconfig |2 +- drivers/gpu/drm/exynos/exynos_drm_fimc.c | 263 -- drivers/gpu/drm/exynos/regs-fimc.h |7 +- 3 files changed, 147 insertions(+), 125 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] drm/exynos: Remove redundant devm_kfree()
There is no need for explicit calls of devm_kfree(), as the allocated memory will be freed during driver's detach. Remove the redundant devm_kfree() calls from probe() and remove() callbacks. Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_fimc.c |2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c index 411f69b7..d812c57 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c @@ -1843,7 +1843,6 @@ static int fimc_probe(struct platform_device *pdev) return 0; err_ippdrv_register: - devm_kfree(dev, ippdrv-prop_list); pm_runtime_disable(dev); err_get_irq: free_irq(ctx-irq, ctx); @@ -1857,7 +1856,6 @@ static int fimc_remove(struct platform_device *pdev) struct fimc_context *ctx = get_fimc_context(dev); struct exynos_drm_ippdrv *ippdrv = ctx-ippdrv; - devm_kfree(dev, ippdrv-prop_list); exynos_drm_ippdrv_unregister(ippdrv); mutex_destroy(ctx-lock); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] drm/exynos: Rework fimc clocks handling
The clocks handling is refactored and a mux clock handling is
added to account for changes in the clocks driver. After switching
to the common clock framework the sclk_fimc clock is now split
into two clocks: a gate and a mux clock. In order to retain the
exisiting functionality two additional consumer clocks are passed
to the driver from device tree: mux and parent. Then the driver
sets parent clock as a parent clock of the mux clock. These two
additional clocks are optional, and should go away when there is a
standard way of setting up parent clocks on DT platforms.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_fimc.c | 168 +-
1 file changed, 98 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
index d812c57..9bea585 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
@@ -76,6 +76,27 @@ enum fimc_wb {
FIMC_WB_B,
};
+enum {
+ FIMC_CLK_LCLK,
+ FIMC_CLK_GATE,
+ FIMC_CLK_WB_A,
+ FIMC_CLK_WB_B,
+ FIMC_CLK_MUX,
+ FIMC_CLK_PARENT,
+ FIMC_CLKS_MAX
+};
+
+static const char * fimc_clock_names[] = {
+ [FIMC_CLK_LCLK] = sclk_fimc,
+ [FIMC_CLK_GATE] = fimc,
+ [FIMC_CLK_WB_A] = pxl_async0,
+ [FIMC_CLK_WB_B] = pxl_async1,
+ [FIMC_CLK_MUX]= mux,
+ [FIMC_CLK_PARENT] = parent,
+};
+
+#define FIMC_DEFAULT_LCLK_FREQUENCY 13300UL
+
/*
* A structure of scaler.
*
@@ -132,15 +153,12 @@ struct fimc_driverdata {
*
* @ippdrv: prepare initialization using ippdrv.
* @regs_res: register resources.
+ * @dev: pointer to the fimc device structure.
* @regs: memory mapped io registers.
* @lock: locking of operations.
- * @sclk_fimc_clk: fimc source clock.
- * @fimc_clk: fimc clock.
- * @wb_clk: writeback a clock.
- * @wb_b_clk: writeback b clock.
+ * @clocks: fimc clocks.
+ * @clk_frequency: LCLK clock frequency.
* @sc: scaler infomations.
- * @odr: ordering of YUV.
- * @ver: fimc version.
* @pol: porarity of writeback.
* @id: fimc id.
* @irq: irq number.
@@ -148,13 +166,12 @@ struct fimc_driverdata {
*/
struct fimc_context {
struct exynos_drm_ippdrvippdrv;
+ struct device *dev;
struct resource *regs_res;
void __iomem*regs;
struct mutexlock;
- struct clk *sclk_fimc_clk;
- struct clk *fimc_clk;
- struct clk *wb_clk;
- struct clk *wb_b_clk;
+ struct clk *clocks[FIMC_CLKS_MAX];
+ u32 clk_frequency;
struct fimc_scaler sc;
struct fimc_driverdata *ddata;
struct exynos_drm_ipp_pol pol;
@@ -1301,14 +1318,12 @@ static int fimc_clk_ctrl(struct fimc_context *ctx, bool
enable)
DRM_DEBUG_KMS(%s:enable[%d]\n, __func__, enable);
if (enable) {
- clk_enable(ctx-sclk_fimc_clk);
- clk_enable(ctx-fimc_clk);
- clk_enable(ctx-wb_clk);
+ clk_prepare_enable(ctx-clocks[FIMC_CLK_GATE]);
+ clk_prepare_enable(ctx-clocks[FIMC_CLK_WB_A]);
ctx-suspended = false;
} else {
- clk_disable(ctx-sclk_fimc_clk);
- clk_disable(ctx-fimc_clk);
- clk_disable(ctx-wb_clk);
+ clk_disable_unprepare(ctx-clocks[FIMC_CLK_GATE]);
+ clk_disable_unprepare(ctx-clocks[FIMC_CLK_WB_A]);
ctx-suspended = true;
}
@@ -1713,11 +1728,66 @@ static void fimc_ippdrv_stop(struct device *dev, enum
drm_exynos_ipp_cmd cmd)
fimc_write(cfg, EXYNOS_CIGCTRL);
}
+static void fimc_put_clocks(struct fimc_context *ctx)
+{
+ int i;
+
+ for (i = 0; i FIMC_CLKS_MAX; i++) {
+ if (IS_ERR(ctx-clocks[i]))
+ continue;
+ clk_put(ctx-clocks[i]);
+ ctx-clocks[i] = ERR_PTR(-EINVAL);
+ }
+}
+
+static int fimc_setup_clocks(struct fimc_context *ctx)
+{
+ struct device *dev;
+ int ret, i;
+
+ for (i = 0; i FIMC_CLKS_MAX; i++)
+ ctx-clocks[i] = ERR_PTR(-EINVAL);
+
+ for (i = 0; i FIMC_CLKS_MAX; i++) {
+ if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B)
+ dev = ctx-dev-parent;
+ else
+ dev = ctx-dev;
+
+ ctx-clocks[i] = clk_get(dev, fimc_clock_names[i]);
+ if (IS_ERR(ctx-clocks[i])) {
+ if (i = FIMC_CLK_MUX)
+ break;
+ ret = PTR_ERR(ctx-clocks[i]);
+ goto e_clk_free;
+ }
+ }
+
+ if (!IS_ERR(ctx-clocks[FIMC_CLK_PARENT])) {
+ ret = clk_set_parent(ctx-clocks[FIMC_CLK_MUX],
+
[PATCH 3/3] drm/exynos: Add device tree support for fimc ipp driver
This patch adds OF initialization support for the FIMC driver.
The binding documentation can be found at Documentation/devicetree/
bindings/media/samsung-fimc.txt.
The syscon regmap interface is used to serialize access to the
shared CAMBLK registers from within the V4L2 FIMC-IS and the DRM
FIMC drivers. The DRM driver uses this interface for setting up
the FIFO data link between FIMD and FIMC IP blocks, while the V4L2
one for setting up a data link between the camera ISP and FIMC for
camera capture. The CAMBLK registers are not accessed any more
through a statically mapped IO. Synchronized access to these
registers is required for simultaneous operation of the camera
ISP and the DRM IPP on Exynos4x12.
Exynos4 is going to be a dt-only platform since 3.10, thus the
driver data and driver_ids static data structures are removed.
Camera input signal polarities are not currently parsed from the
device tree.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/Kconfig |2 +-
drivers/gpu/drm/exynos/exynos_drm_fimc.c | 101 +++---
drivers/gpu/drm/exynos/regs-fimc.h |7 +--
3 files changed, 53 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 406f32a..5c4be2a 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -56,7 +56,7 @@ config DRM_EXYNOS_IPP
config DRM_EXYNOS_FIMC
bool Exynos DRM FIMC
- depends on DRM_EXYNOS_IPP
+ depends on DRM_EXYNOS_IPP MFD_SYSCON OF
help
Choose this option if you want to use Exynos FIMC for DRM.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
index 9bea585..f25801e 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
@@ -12,11 +12,12 @@
*
*/
#include linux/kernel.h
+#include linux/mfd/syscon.h
#include linux/module.h
#include linux/platform_device.h
+#include linux/regmap.h
#include linux/clk.h
#include linux/pm_runtime.h
-#include plat/map-base.h
#include drm/drmP.h
#include drm/exynos_drm.h
@@ -140,15 +141,6 @@ struct fimc_capability {
};
/*
- * A structure of fimc driver data.
- *
- * @parent_clk: name of parent clock.
- */
-struct fimc_driverdata {
- char*parent_clk;
-};
-
-/*
* A structure of fimc context.
*
* @ippdrv: prepare initialization using ippdrv.
@@ -158,6 +150,7 @@ struct fimc_driverdata {
* @lock: locking of operations.
* @clocks: fimc clocks.
* @clk_frequency: LCLK clock frequency.
+ * @sysreg: handle to SYSREG block regmap.
* @sc: scaler infomations.
* @pol: porarity of writeback.
* @id: fimc id.
@@ -172,8 +165,8 @@ struct fimc_context {
struct mutexlock;
struct clk *clocks[FIMC_CLKS_MAX];
u32 clk_frequency;
+ struct regmap *sysreg;
struct fimc_scaler sc;
- struct fimc_driverdata *ddata;
struct exynos_drm_ipp_pol pol;
int id;
int irq;
@@ -217,17 +210,13 @@ static void fimc_sw_reset(struct fimc_context *ctx)
fimc_write(0x0, EXYNOS_CIFCNTSEQ);
}
-static void fimc_set_camblk_fimd0_wb(struct fimc_context *ctx)
+static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx)
{
- u32 camblk_cfg;
-
DRM_DEBUG_KMS(%s\n, __func__);
- camblk_cfg = readl(SYSREG_CAMERA_BLK);
- camblk_cfg = ~(SYSREG_FIMD0WB_DEST_MASK);
- camblk_cfg |= ctx-id (SYSREG_FIMD0WB_DEST_SHIFT);
-
- writel(camblk_cfg, SYSREG_CAMERA_BLK);
+ return regmap_update_bits(ctx-sysreg, SYSREG_CAMERA_BLK,
+ SYSREG_FIMD0WB_DEST_MASK,
+ ctx-id SYSREG_FIMD0WB_DEST_SHIFT);
}
static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb)
@@ -1628,7 +1617,9 @@ static int fimc_ippdrv_start(struct device *dev, enum
drm_exynos_ipp_cmd cmd)
fimc_handle_lastend(ctx, true);
/* setup FIMD */
- fimc_set_camblk_fimd0_wb(ctx);
+ ret = fimc_set_camblk_fimd0_wb(ctx);
+ if (ret 0)
+ return ret;
set_wb.enable = 1;
set_wb.refresh = property-refresh_rate;
@@ -1784,26 +1775,50 @@ e_clk_free:
return ret;
}
+static int fimc_parse_dt(struct fimc_context *ctx)
+{
+ struct device_node *node = ctx-dev-of_node;
+
+ if (!of_property_read_bool(node, samsung,lcd-wb))
+ return -ENODEV;
+
+ if (of_property_read_u32(node, clock-frequency,
+ ctx-clk_frequency))
+ ctx-clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY;
+
+ ctx-id = of_alias_get_id(node, fimc);
+ if (ctx-id 0)
+ return -EINVAL;
+
+ return 0;
+}
+
static int fimc_probe(struct
Re: [PATCH v5 00/14] ARM: samsung-time: Prepare for multiplatform support
On 04/12/2013 09:17 PM, Tomasz Figa wrote: This series is an attempt to make the samsung-time clocksource driver ready for multiplatform kernels. It moves the driver to drivers/clocksource, cleans it up from uses of static platform-specific definitions, simplifies timer interrupt handling and adds Device Tree support. The samsung_pwm clocksource driver is made the master driver, which exposes a single function to the PWM driver to get required data. Only samsung-time driver is reworked to use the master driver at this time, since the PWM driver can be already considered broken at the moment and needs separate series of several patches to fix and clean it up, which I am already working on. Tested on Universal C210 board with Device Tree. Not tested without Device Tree, since it has been already broken before this series. Compile tested for other related SoCs. On s3c2440 based board Tested-by: Sylwester Nawrocki s.nawro...@samsung.com -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] pinctrl: s3c64xx: Fix build error caused by undefined chained_irq_enter
Commit de88cbb7 moved definitions of chained_irq_enter and chained_irq_exit to a generic header, which must be now included instead of the legacy arch-specific one. This patch fixes build error caused by including the legacy header leading to undefined chained_irq_enter and chained_irq_exit symbols. Signed-off-by: Tomasz Figa tomasz.f...@gmail.com --- drivers/pinctrl/pinctrl-s3c64xx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-s3c64xx.c b/drivers/pinctrl/pinctrl-s3c64xx.c index b5d1c4a..89143c9 100644 --- a/drivers/pinctrl/pinctrl-s3c64xx.c +++ b/drivers/pinctrl/pinctrl-s3c64xx.c @@ -22,11 +22,10 @@ #include linux/irq.h #include linux/of_irq.h #include linux/io.h +#include linux/irqchip/chained_irq.h #include linux/slab.h #include linux/err.h -#include asm/mach/irq.h - #include pinctrl-samsung.h #define NUM_EINT0 28 -- 1.8.1.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] pinctrl: samsung: Fix link error with CONFIG_PINCTRL_EXYNOS disabled
Commit f67faf487 added driver data for Exynos5250, which is available
only if CONFIG_PINCTRL_EXYNOS is enabled. However probably due to merge
error, the reference to this driver data structure was located outside
of relevant ifdef and compiled unconditionally, leading to link error
with CONFIG_PINCTRL_EXYNOS.
This patch fixes mentioned link error by moving driver data entry under
ifdef CONFIG_PINCTRL_EXYNOS.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
drivers/pinctrl/pinctrl-samsung.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-
samsung.c
index f95dd69..9763668 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -970,13 +970,13 @@ static const struct of_device_id
samsung_pinctrl_dt_match[] = {
.data = (void *)exynos4210_pin_ctrl },
{ .compatible = samsung,exynos4x12-pinctrl,
.data = (void *)exynos4x12_pin_ctrl },
+ { .compatible = samsung,exynos5250-pinctrl,
+ .data = (void *)exynos5250_pin_ctrl },
#endif
#ifdef CONFIG_PINCTRL_S3C64XX
{ .compatible = samsung,s3c64xx-pinctrl,
.data = s3c64xx_pin_ctrl },
#endif
- { .compatible = samsung,exynos5250-pinctrl,
- .data = (void *)exynos5250_pin_ctrl },
{},
};
MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match);
--
1.8.1.5
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[PATCH RESEND 2/2] pinctrl: samsung: Fix link error with CONFIG_PINCTRL_EXYNOS disabled
Commit f67faf487 added driver data for Exynos5250, which is available
only if CONFIG_PINCTRL_EXYNOS is enabled. However probably due to merge
error, the reference to this driver data structure was located outside
of relevant ifdef and compiled unconditionally, leading to link error
with CONFIG_PINCTRL_EXYNOS.
This patch fixes mentioned link error by moving driver data entry under
ifdef CONFIG_PINCTRL_EXYNOS.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
drivers/pinctrl/pinctrl-samsung.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-samsung.c
b/drivers/pinctrl/pinctrl-samsung.c
index f95dd69..9763668 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -970,13 +970,13 @@ static const struct of_device_id
samsung_pinctrl_dt_match[] = {
.data = (void *)exynos4210_pin_ctrl },
{ .compatible = samsung,exynos4x12-pinctrl,
.data = (void *)exynos4x12_pin_ctrl },
+ { .compatible = samsung,exynos5250-pinctrl,
+ .data = (void *)exynos5250_pin_ctrl },
#endif
#ifdef CONFIG_PINCTRL_S3C64XX
{ .compatible = samsung,s3c64xx-pinctrl,
.data = s3c64xx_pin_ctrl },
#endif
- { .compatible = samsung,exynos5250-pinctrl,
- .data = (void *)exynos5250_pin_ctrl },
{},
};
MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match);
--
1.8.1.5
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Re: [PATCH v5 2/6] ARM: s3c64xx: Skip legacy EINT setup if pinctrl-s3c64xx driver is present
On Tuesday 16 of April 2013 17:26:43 Mark Brown wrote: On Mon, Apr 15, 2013 at 11:14:39PM +0200, Tomasz Figa wrote: + * This gpio driver includes support for device tree support and there + * are platforms using it. In order to maintain compatibility with those + * platforms, and to allow non-dt Exynos4210 platforms to use this + * gpiolib support, a check is added to find out if there is a active Cut'n'paste error here. blushed Thanks for catching this. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 3/6] gpio: samsung: Skip legacy GPIO registration if pinctrl-s3c64xx is present
On Tuesday 16 of April 2013 17:27:50 Mark Brown wrote:
On Mon, Apr 15, 2013 at 11:14:40PM +0200, Tomasz Figa wrote:
{ .compatible = samsung,exynos4x12-pinctrl, },
{ .compatible = samsung,exynos5250-pinctrl, },
{ .compatible = samsung,exynos5440-pinctrl, },
+ { },
Strictly speaking this is a separate bug fix (though I see that's
already in -next separately anyway so whatever).
Right. But this fix is so small that I thought it would be a major waste
of mail server processing power to send it as a separate patch.
Best regards,
Tomasz
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Re: [PATCH 2/3] drm/exynos: Rework fimc clocks handling
Hi Sylwester,
On 16 April 2013 23:01, Sylwester Nawrocki s.nawro...@samsung.com wrote:
@@ -1835,16 +1859,19 @@ static int fimc_probe(struct platform_device *pdev)
ret = exynos_drm_ippdrv_register(ippdrv);
if (ret 0) {
dev_err(dev, failed to register drm fimc device.\n);
- goto err_ippdrv_register;
+ goto err_pm_dis;
}
dev_info(pdev-dev, drm fimc registered successfully.\n);
return 0;
-err_ippdrv_register:
+err_pm_dis:
+ devm_kfree(dev, ippdrv-prop_list);
devm_kfree was removed in patch1 of this series. Do we need it back?
--
With warm regards,
Sachin
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