RE: Mersenne: Pentium III
On Sun, 28 Feb 1999, Paul Derbyshire wrote: ...minimize possible cache hits on cacheless Celeron chips... Isn't that a vacuous statement? :-) (Say, I never heard of any cacheless Celeron chips, or any other cacheless chip since the late eighties...) Eh? All the original Celeron chips were sans cache, only after the customers started screaming about a 300 performing like a 200mhz pentium did the 300A and later come out with a reduced size cache (instead of none). As folks might have suspected, not much survives except roaches, and they don't carry large enough packets fast enough... --About the Internet and nuclear war. Unsubscribe list info -- http://www.scruz.net/~luke/signup.htm
RE: Mersenne: Pentium III
At 12:06 AM 2/28/99 -0900, you wrote: Eh? All the original Celeron chips were sans cache, only after the customers started screaming about a 300 performing like a 200mhz pentium did the 300A and later come out with a reduced size cache (instead of none). Really??? Hm. Silly buggers. Never ever ever ever release a chip without a cache. I don't suppose they were reasonable and charitable and gave everyone who got a chip from the bum batch a free upgrade to a 300A? And "minimize possible cache hits on cacheless Celeron chips" is still a vacuous condition... -- .*. "Clouds are not spheres, mountains are not cones, coastlines are not -()circles, and bark is not smooth, nor does lightning travel in a `*' straight line."- -- B. Mandelbrot |http://surf.to/pgd.net _ | Paul Derbyshire [EMAIL PROTECTED] Programmer Humanist|ICQ: 10423848| Unsubscribe list info -- http://www.scruz.net/~luke/signup.htm
Mersenne: Spike - demonstrating calculating prowess
I think the idea of demonstrating our calculating prowess is illogical. Even a typical insect brain has many times the computing power of our best PCs. Consider that it takes one PC to run a robot arm at Chrysler; a fly has six much more complicated legs. George Unsubscribe list info -- http://www.scruz.net/~luke/signup.htm
Re: Mersenne: Pentium III
(Say, I never heard of any cacheless Celeron chips, or any other cacheless chip since the late eighties...) Eh? All the original Celeron chips were sans cache, only after the customers started screaming about a 300 performing like a 200mhz pentium did the 300A and later come out with a reduced size cache (instead of none). You're *both* half right. *ALL* Intel P6 family CPUs (PPro, PII, Celeron, Xeon, PIII) have 32KB Level 1 cache, divided into 16KB of instruction cache and 16KB of data cache. The Level 1 cache always runs at core speed. Where the products differ is in the amount and speed of the Level 2 cache. PPro had 256KB, 512KB or 1024KB of L2 cache fabricated into the chip package running at core speed. Almost all PPros were the 256KB version, the 512KB version was extortionately expensive, and the 1024KB version so dear that very few people ever saw one. Xeon has 512KB, 1024KB or 2048KB of L2 cache, running at core speed, somewhere in the Slot 2 cartridge. Probably on seperate chips. +/- the same comments about pricing apply as to the PPro with half as much L2 cache. PII and PIII both have 512KB of L2 cache running at half core speed, on a seperate chip mounted inside the Slot 1 cartridge. The original Celeron (266 and 300) had no (OKB) L2 cache. These may be repackaged PII components with duff L2 cache disabled. In any case, they are obsolete, you can't seem to buy new ones from "normal" retail outlets any more. Later Celerons (300A, 333 and above) have 128KB of L2 cache, integrated onto the CPU chip and running at core speed. I believe that mobile PII processors (the "Tillamook" package, not the Slot 1 cartridge) have only 256KB L2 cache, but running at full core speed. But I don't claim ever to have seen one. If you have a BIOS which allows you to mess with the cache settings then you can experiment. My Supermicro BX chipset motherboard with AMI BIOS allows you to turn on or off the level 2 cache, and also to enable or disable the ECC mode in the cache memory (if your CPU supports it - the "Klamath" PIIs, 233/266/300 MHz, didn't have ECC cache capability). On a dual PII-350 system, I found (a) having the ECC turned on or off made no difference at all to any benchmark - reccomendation, if your system supports ECC, enable it, it costs nothing should aid reliability; (b) having the L2 cache disabled slowed the system down by approx. 10% so far as "normal" benchmarks are concerned, but made little if any difference to the speed of Prime95. There may be more effect on systems that do not have PC100 SDRAM. This finding is corroborated by other personal experience, I found that the Celeron 266 system my employers (stingy so-and-so's) bought for me to use at work ran Prime95 at pretty much the same speed as my own PII-266, which quite honestly surprised me at the time. The cache tuning which has been done in Prime95 appears to be aimed to optimizing the use of the L1 cache, I don't see anything which the L2 cache helps out much. Corroborative evidence for this comes from my PII-266 system, the Pheonix BIOS on the Intel LX motherboard on this system allows you to disable L1 and L2 cache (but not seperately), if you disable the cache then Prime95 runs several times slower! (This may be the source of the fable about original Celerons being dead slow - systems integrators turned off the cache in the BIOS, not realizing that the L1 cache was being shut down, too) The point is that the amount and speed of Level 2 cache, on Intel P6 family CPUs, appears not to have a large effect in the performance of Prime95 - certainly not enough to justify paying 10x the price for a Xeon 450 2MB as opposed to a PII-450! So far as Pentium III is concerned, call me a cynical old f*** if you must, but I think it's marketing hype. I would have thought that the "signal processing" and "rendering" type applications, at which the KNI instructions seem to be targeted, would be better done in dedicated hardware outside the CPU. After all, it isn't the CPU that connects to the Internet, it's the modem or network adapter - and what you see on the screen is an image of the contents of the memory in the graphics adapter. Sorry, Intel, but Katmai looks more like a version upgrade (in a strange direction) than a quantum leap in technology. Nevertheless, no doubt, lots of people with newish PII systems and more money than sense will upgrade to a PIII with little increase in clock speed - which means there may shortly be a surplus of second-user PII CPUs on the market at ridiculously low prices. Cheap upgrades for some of us? (Check that the idiot who had the CPU before you didn't put his thumb through the fragile fan housing when he was removing the cartridge from its mounting!) Now, if what we read about the forthcoming AMD K7 is true (256KB L1 cache, FPU capable of executing 2 double-precision operations per clock, bus speeds 133MHz initially, 200 MHz later),
Re: Mersenne: Re: Chronons
Hold fast everyone! I realize that the odds are seemingly very against the formation of cellular material during the early days but the odds were not so bad that a cell couldn't form little by little, step by step. The odds that a modern day eukaryote (animal) cell could form on it's own are probably similar to the chance of a working engine, constructed by our familiar insensible monkeys. Arron Blosser, I don't think I understood you properly; you seemed to imply that a whole cellular system came together soon after the formation of left-handed amino acid molecules? The amino acids that could, did bond. They were able to create a functioning system known as a cellular membrane. This simple membrane was a perfect net to catch and retain the chemical energy that the 'life' entity used to 'grow'. This existed for a while as a simple cellular membrane system, but not yet a cell as we now know it. A lot of bonding took hold at this time. Granted, the other amino acid molecules probably failed to bond or to form a circular cellular membrane that could easily retain an energy source to continue 'living'. Their fuel sources drifted away from them, leaving them naked and unprotected from the violating elements. Over time, the safety of the cellular membrane gave energy and protection to spend on more random events (more steps) leading up to the creation simple organelles which formed and began functioning to improve the 'cell's' competitive edges. A plethora of variation in organelles formed, but evolution allowed only the smoothly working systems to continue. The rest of the variety found that they could not get an energy source easily enough since it was being quickly taken up and away by the other competitive organelle systems. The new competitive blob had time to haphazardly develop a genetic system (thanks to the membrane and organelles working together) and it became a kind of real cell. These membrane systems were like our modern cells but behaved more like mitochondria and chloroplasts. These cells began to need each other in a kind of symbiosis or codependence-based relationship. One produced something that the other needed, so the kinds of evolutionarily different cells merged together and formed a better kind of cell. By the way, original DNA is still found in these mitochondria and chloroplasts today (found as tenets in today's prokaryotic cells) which is acceptable evidence of this ancient merge. This was the formation of early prokaryote (plant) cells. These cells formed things like bacteria, which were later eaten by the more advanced euyarkote (animal) cells after they had developed. Now, what are the odds of enough of these amazingly rare proteins existing close enough to each other and magically combining to form a self-replicating cell? Even more staggeringly impossible. It does seem impossible yet there are billions of trillions of cells in your body suggesting otherwise. Perhaps you meant that it was impossible for a modern cell to be formed in one swoop from nothing before, much like the impossibility of a Pentium II chip being the first chip ever made. There have to be prototypes in the beginning. The original system is created, tested and then improvements are made. This makes the odds for a completed system much better since the process is taken more slowly, and fewer steps are taken at each interval. If a cell had to cover lots of steps in once giant leap to become alive, then this would surely be too excessive and the mass of protein would not become a cell. However, if a developing cell only had to work on small improvements in little strides, succession is easily granted. People behave in the same way. What are the odds that you'll spend all your time and effort revamping the family house in one month? You wouldn't do all that improving in such a short time. You would divide up the work over a longer time so as not to make the work too taxing and exhausting. By taking smaller steps at a time, the odds that you'll complete your task are much improved. The odds of a cell being developed over the course of a long time from little intervals of development are much more optimistic than those chances of a cell becoming aloft from nothing and with no prototype. This small step process is therefore very possible and plausible. Given all the obstacles to a single protein forming, much less a single cell, I'm amazed that some kids didn't find it interesting enough to pay attention in class. I guess I'm just one of those unfortunate people that learned this biology stuff at school and studied it at university, I never had much interest in television. ___ You don't need to buy Internet access to use free Internet e-mail. Get completely free e-mail from Juno at http://www.juno.com/getjuno.html or call Juno at (800) 654-JUNO [654-5866]
RE: Mersenne: Pentium III
On Sun, 28 Feb 1999, Paul Derbyshire wrote: At 12:06 AM 2/28/99 -0900, you wrote: Eh? All the original Celeron chips were sans cache, only after the customers started screaming about a 300 performing like a 200mhz pentium did the 300A and later come out with a reduced size cache (instead of none). Really??? Hm. Silly buggers. Never ever ever ever release a chip without a cache. I don't suppose they were reasonable and charitable and gave everyone who got a chip from the bum batch a free upgrade to a 300A? And "minimize possible cache hits on cacheless Celeron chips" is still a vacuous condition... I think that when the Celeron first came out it was a Pentium II whose high-speed *external* cache was broken. The on-chip cache was still fine, otherwise a cached 386 could probably outrun it. jasonp Unsubscribe list info -- http://www.scruz.net/~luke/signup.htm
RE: Mersenne: Pentium III
...minimize possible cache hits on cacheless Celeron chips... Isn't that a vacuous statement? :-) (Say, I never heard of any cacheless Celeron chips, or any other cacheless chip since the late eighties...) It is a bit confusing, yes? :-) I'm referring to the L2 cache, for which the first Celerons had none. You can get Celeron's now with 128k (or maybe 256k also?) now. Those ones have the distinct advantage that the L2 cache runs at CPU speed, not CPU/2 speed like the PII/Xeon/etc. By keeping the code small, you'll hope to keep the program's main bits in the L1 cache. BTW, here's the press release URL I got from Intel today: http://www.intel.com/tech/work/desktop/unleash.htm?iid=mail+tw11 You'll notice that it *does* mention an improvement in FPU speeds due to the addition of a 3rd register, enhancing parallel instruction execution, making the PIII capable of 4 floating point instructions in a single instruction. That oughta help Prime95, yes? Plus, seperate registers now for FP and MMX means better performance when you're actually doing other stuff on the machine, like playing a game or whatever, since it won't have to store the registry, then swap back in later. Plus, you could use the SIMD stuff to *specifically* load stuff into the L2 cache ahead of time, so when the code needs it, it'll be waiting in the fast ram for ya. Smaller improvement than the FPU stuff, but could be a few percent. Not bad. And of course, when it hits 600MHz, that'll be pretty nice too. Aaron Unsubscribe list info -- http://www.scruz.net/~luke/signup.htm
Re: Mersenne: Fabs.
Re: PIII speed: ...don't expect a speed improvement beyond the obvious boost to 500MHz (and faster once .18 fabs come online). Fabs? What are those? I found a fabs in my float.h once, never did see it again. I think it was for finding absolute values. :-) At the risk of stating the obvious (and for the sake of those less technical in our audience): In chipmaking terminology, a "Fab" is a chip fabricating plant, the .18 refers to 0.18 micron line widths, which is the next benchmark in the ever-smaller spiral of chip feature-sizes. And to think it wasn't that long ago when sub-micron was a wonderous new goal [chips at the time were mostly 1.2-2.0u lines, and the new 0.8 stuff was boggling]. Current stuff is mostly .35-.20u -jrp Unsubscribe list info -- http://www.scruz.net/~luke/signup.htm
Mersenne: Some diagrams
Hi all! I've downloaded Top Producers Awards list from the PrimeNet and have prepared three figures showing No of accounts vs P90 CPU hours/day. One of account had 0.0 CPU hours so I've changed it to 0.01. Accounts are grouped into intervals satisfying the condition a = ln (x+1) a + 0.1 (first diagram) and a-0.1 = ln x a+0.1 For each `a' a number of accounts in the corresponding region is plotted vs `a'. If you are intersting in these plots browse to my page http://main.amu.edu.pl/~florek You can download pictures in *.gif *.ps and *.tex format. I don't know why, but *.ps file cannot be viewed by gs under Linux (but xv displays them). Comments, questions, requests etc send to [EMAIL PROTECTED] Wojciech Florek (WF) Adam Mickiewicz University, Institute of Physics ul. Umultowska 85, 61-614 Poznan, Poland phone: (++48-61) 8273033 fax: (++48-61) 8257758 email: [EMAIL PROTECTED] www: http://main.amu.edu.pl/~florek Unsubscribe list info -- http://www.scruz.net/~luke/signup.htm
Re: Mersenne: Some diagrams
http://main.amu.edu.pl/~florek I gotta 'cannot reach server' error on this a traceroute dies after 12 hops (last response was from tni-sto3-rc01-fe00.telenordia.se, 195.163.70.34 ) -jrp Unsubscribe list info -- http://www.scruz.net/~luke/signup.htm
Mersenne: Re: Mersenne Digest V1 #515
How about sweetening the pot for anyone who is doing double checking that discovers a mistake in the first LL analysis? Hrm. A small reward would be an incentive. Of course, any mistakes found would have to be TRIPLE-checked, so that no one fakes an error (easy) to get the incentive. Of course, anyone who did such a thing would have to be branded a liar and not allowed to participate in GIMPS any more. Double-checking finds errors 1/400 of the time, if I remember correctly. But the execution of the instructions themselves are probably about the same. I have heard that FP speeds would go up some though... Prime95 may run slower on a Merced at the same clock speed as a Xeon, at least until it's recompiled. Sigh... The Merced, if I remember correctly, does NOT have native x86 processing capability, only through emulation. Pentium III Xeons will remain the fastest processors for x86 instructions. But Prime95 written in Merced assembler *begins to drool* Earlier I posted the notion that Mersenne primes might be used to impress extraterrestrial civilizations. After thinking it thru, I think we can make a stronger arguement than that: Mersenne primes might be the *best* yardstick to *prove* a certain level of technological achievement, perhaps the most logical yardstick. Interesting. I like it. But there is one way that it could be a nonreliable indicator of technological achievement. If an exoculture receives our Mersenne prime message, they will know that other life exists in the universe. Assuming we know more Mersenne primes than they do, they will have stumbled onto new "free" primes, at no computational cost. (Verification is easy, if they have a Lucas-Lehmer test and can wait long enough, even with slow computers.) If they're anything like us, one of them will raise the question if WE have heard other civilizations with 37 Mersenne primes and simply repeated the primes out ourselves. That would be a method of faking it. They can, however, definitively put an UPPER limit on our technological achievement. If the other society knows more Mersenne primes than we do, then they may or may not realize the way of "faking" it, while if they know less Mersenne primes, they'll probably realize my point. Nope, they will just wonder what they have overlooked that makes Mersenne Primes so basic to a culture. Imagine if some exoculture sees our Mersenne prime message, and they feel that THEIR culture is inferior because they only know the first four. And, there is always Myxlptlk's Theorem to consider. Except that it might have an unintended effect. Suppose we send out a list of Mersenne primes, and the receiving civilization realizes from the list that we do not know the Theorem of Myxlptlk, which, as every young Golurdian knows, gives an explicit formula for all Mersenne primes. What about the following scenario: We send the Mersenne prime message. The friendly Aeraibvca civilization receives it, and notices that we know far fewer Mersenne primes than they do. Of course, they have existed for much longer, and have known about Mersenne primes for hundreds of millennia. Thus, they're surprised that we have found 37 in just a couple of millenia, and most in the last century. We advance at a much faster rate than them. They don't know Myxlptlk's Theorem (from the Golurdians), but they do know a few more interesting facts about Mersenne primes. They even learn a couple of things from us (General Relativity is unknown to them - they only have Ntromdukian gravity), so they send us everything they know about Mersenne primes, and even send us all the primes that they know. Our comparatively primitive Terran mathematicians looks at the new facts, conjectures, and all the new primes, and see some sort of a pattern. Hrm. Separately, the Aeraibvcas and the Terrans couldn't have thought of Myxlptlk's Theorem, but together, they derive an even-easier-to-compute- with version of it (ha ha, Golurdians). Interesting. On further thought, if we're willing to wait long enough, it could be a sort of interstellar game we could play, even if we can't physically get there in a reasonable amount of time. Send the first 10 Mersenne primes to an alien civilization, including enough (hahaha) information for them to deduce our language, or a special LinguaCode specifically designed to be easy for alien civilizations to understand (why make them deal with declensions and conjugations if they don't have to? Here's what a few sentences might look like: Ted picked up a book yesterday, and he quickly read it. Ted thought that the book was very informative. Ted before-pick book before-day. Ted fast before-read book. Ted before-think book before-is very informative. Or something like that.) Then ask them how many Mersenne primes they know. Then send them a couple, and they can send us a couple, so forth. It could be a race. Can we find the 137th Mersenne prime before the Aeraibvcas do? Our superiority as a race is at stake!
Mersenne: Double-checking (was Chronons)
Hi, At 07:35 PM 2/26/99 -0800, Spike Jones wrote: How about sweetening the pot for anyone who is doing double checking that discovers a mistake in the first LL analysis? How does this work? The first LL test returns a residual, then the double checking routine takes that residual and... what? How often is a result overturned by double checking? From your point of view a double-check is just like a first time test. You run a Lucas-Lehmer test and when done send in your 64-bit residue. I compare that residue to the first run and if they match, the exponent is declared double-checked. If they don't match, a third test is run to properly double-check the number. Finding an error in the first LL test is not rare. I've said about 1 in 200 are incorrect. When the entire 1,400,000 - 2,000,000 range has been double-checked I'll perform some more rigorous analysis of the reliability of first-time LL results. Best regards, George Unsubscribe list info -- http://www.scruz.net/~luke/signup.htm
Mersenne: Spike - demonstrating calculating prowess
George Strohschein wrote:Even a typical insect brain has many times the
computing power of our best PCs.
Perhaps, but the bugs are using their brains for such mundane things,
such as building anthills and buzzing manure, whereas our PCs are
calculating and accumulating knowledge. Besides, our PCs are getting
better every year, whereas modern bugs are no smarter than their
amber-encased distant ancestors.
Consider that it takes one PC to run a robot arm at Chrysler; a fly
has six much more complicated legs.
But the Chrysler arm is making something useful to humans and our
idle PCs are too. Nowthen, someone mentioned the SETI suggestion
of sending out a list of the first 100 primes as a proof of intelligent
origen. Would it not be a far more impressive display to send out
the first 37 Mersennes? The first hundred primes were known back
who knows how long ago. Yawn. Ah, but a list of the first 37 Mersennes
demonstrates that we, as a species, are advanced and are to be treated
with respect, even by more advanced exosocieties.
Secondly, how many human endevours really include the entire human
species? GIMPS cares not your color, age, race, gender, where you
live or who/what you pray to. Mathematics transcends the boundaries
that we have built that divide us.
This characteristic leads me to extend a previous argument about using
primes to communicate with exos: is there any better way to break the
interstellar ice than to send out a list of primes? I have pondered this
for years, and have thought of none, except a related concept: sending
out a list of Mersenne primes.
Now George, if we could only teach flies to do Lucas Lehmer tests in
their idle moments {8^D spike
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Re: Mersenne: Some diagrams
Wojciech Florek wrote: If you are intersting in these plots browse to my page http://main.amu.edu.pl/~florek You can download pictures in *.gif *.ps and *.tex format. Wow thanks Wojciek! Great web site. I know that we have many active GIMPSers all over the U.S., Australia and Europe. Are there GIMPSers from China? From Africa? I surely hope so, for GIMPS is a rare example of an entire planet working together on a project. spike Unsubscribe list info -- http://www.scruz.net/~luke/signup.htm
