[Mesa-dev] [Bug 90264] [Regression, bisected] Tooltip corruption in Chrome

2015-10-24 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=90264

--- Comment #51 from pavi...@yahoo.fr ---
I'm on Fedora 22 x64 with Nouveau and I have this tooltip corruption in
Chromium too. I hope that can be fixed.
Thank you

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[Mesa-dev] [PATCH 3/3] radeonsi: add debug flags that disable DCC and DCC fast clear

2015-10-24 Thread Marek Olšák 
From: Marek Olšák 

For debugging, bug reports, etc.
This is not in the radeonsi directory, but it is about radeonsi.
---
 src/gallium/drivers/radeon/r600_pipe_common.c | 2 ++
 src/gallium/drivers/radeon/r600_pipe_common.h | 2 ++
 src/gallium/drivers/radeon/r600_texture.c | 6 ++
 3 files changed, 10 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 4ce0c6a..0ad3684 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -360,6 +360,8 @@ static const struct debug_named_value 
common_debug_options[] = {
{ "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader 
creation." },
{ "nowc", DBG_NO_WC, "Disable GTT write combining" },
{ "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
+   { "nodcc", DBG_NO_DCC, "Disable DCC." },
+   { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
 
DEBUG_NAMED_VALUE_END /* must be last */
 };
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index f21a0b3..c300c0b 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -99,6 +99,8 @@
 #define DBG_INFO   (1llu << 40)
 #define DBG_NO_WC  (1llu << 41)
 #define DBG_CHECK_VM   (1llu << 42)
+#define DBG_NO_DCC (1llu << 43)
+#define DBG_NO_DCC_CLEAR   (1llu << 44)
 
 #define R600_MAP_BUFFER_ALIGNMENT 64
 
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 40075ae..789c66f 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -486,6 +486,9 @@ static void r600_texture_alloc_cmask_separate(struct 
r600_common_screen *rscreen
 static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
  struct r600_texture *rtex)
 {
+   if (rscreen->debug_flags & DBG_NO_DCC)
+   return;
+
rtex->dcc_buffer = (struct r600_resource *)
r600_aligned_buffer_create(>b, PIPE_BIND_CUSTOM,
   PIPE_USAGE_DEFAULT, rtex->surface.dcc_size, 
rtex->surface.dcc_alignment);
@@ -1371,6 +1374,9 @@ void evergreen_do_fast_color_clear(struct 
r600_common_context *rctx,
uint32_t reset_value;
bool clear_words_needed;
 
+   if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
+   continue;
+
vi_get_fast_clear_parameters(fb->cbufs[i]->format, 
color, _value, _words_needed);
 
rctx->clear_buffer(>b, >dcc_buffer->b.b,
-- 
2.1.4

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[Mesa-dev] [PATCH 1/3] radeonsi: simplify DCC handling in si_initialize_color_surface

2015-10-24 Thread Marek Olšák 
From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_state.c | 10 +++---
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 384c8e2..c87f661 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1926,8 +1926,9 @@ static void si_initialize_color_surface(struct si_context 
*sctx,
surf->cb_color_info = color_info;
surf->cb_color_attrib = color_attrib;
 
-   if (sctx->b.chip_class >= VI) {
+   if (sctx->b.chip_class >= VI && rtex->surface.dcc_enabled) {
unsigned max_uncompressed_block_size = 2;
+   uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;
 
if (rtex->surface.nsamples > 1) {
if (rtex->surface.bpe == 1)
@@ -1938,12 +1939,7 @@ static void si_initialize_color_surface(struct 
si_context *sctx,
 
surf->cb_dcc_control = 
S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
   S_028C78_INDEPENDENT_64B_BLOCKS(1);
-
-   if (rtex->surface.dcc_enabled) {
-   uint64_t dcc_offset = 
rtex->surface.level[level].dcc_offset;
-
-   surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + 
dcc_offset) >> 8;
-   }
+   surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + 
dcc_offset) >> 8;
}
 
if (rtex->fmask.size) {
-- 
2.1.4

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[Mesa-dev] [PATCH 2/3] radeonsi: properly check if DCC is enabled and allocated

2015-10-24 Thread Marek Olšák 
From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_texture.c | 2 +-
 src/gallium/drivers/radeonsi/cik_sdma.c   | 2 +-
 src/gallium/drivers/radeonsi/si_blit.c| 6 +++---
 src/gallium/drivers/radeonsi/si_dma.c | 2 +-
 src/gallium/drivers/radeonsi/si_state.c   | 4 ++--
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index f7a11a2..40075ae 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1367,7 +1367,7 @@ void evergreen_do_fast_color_clear(struct 
r600_common_context *rctx,
continue;
}
 
-   if (tex->surface.dcc_enabled) {
+   if (tex->dcc_buffer) {
uint32_t reset_value;
bool clear_words_needed;
 
diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c 
b/src/gallium/drivers/radeonsi/cik_sdma.c
index 25fd09a..e53af1d 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -243,7 +243,7 @@ void cik_sdma_copy(struct pipe_context *ctx,
if (src->format != dst->format ||
rdst->surface.nsamples > 1 || rsrc->surface.nsamples > 1 ||
(rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << 
dst_level) ||
-   rdst->surface.dcc_enabled || rsrc->surface.dcc_enabled) {
+   rdst->dcc_buffer || rsrc->dcc_buffer) {
goto fallback;
}
 
diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index a226436..302b75c 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -326,7 +326,7 @@ void si_decompress_color_textures(struct si_context *sctx,
assert(view);
 
tex = (struct r600_texture *)view->texture;
-   assert(tex->cmask.size || tex->fmask.size || 
tex->surface.dcc_enabled);
+   assert(tex->cmask.size || tex->fmask.size || tex->dcc_buffer);
 
si_blit_decompress_color(>b.b, tex,
 view->u.tex.first_level, 
view->u.tex.last_level,
@@ -455,7 +455,7 @@ static void si_decompress_subresource(struct pipe_context 
*ctx,
si_blit_decompress_depth_in_place(sctx, rtex, true,
  level, level,
  first_layer, 
last_layer);
-   } else if (rtex->fmask.size || rtex->cmask.size || 
rtex->surface.dcc_enabled) {
+   } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_buffer) {
si_blit_decompress_color(ctx, rtex, level, level,
 first_layer, last_layer);
}
@@ -676,7 +676,7 @@ static bool do_hardware_msaa_resolve(struct pipe_context 
*ctx,
dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
!(dst->surface.flags & RADEON_SURF_SCANOUT) &&
(!dst->cmask.size || !dst->dirty_level_mask) && /* dst cannot be 
fast-cleared */
-   !dst->surface.dcc_enabled) {
+   !dst->dcc_buffer) {
si_blitter_begin(ctx, SI_COLOR_RESOLVE |
 (info->render_condition_enable ? 0 : 
SI_DISABLE_RENDER_COND));
util_blitter_custom_resolve_color(sctx->blitter,
diff --git a/src/gallium/drivers/radeonsi/si_dma.c 
b/src/gallium/drivers/radeonsi/si_dma.c
index 73c026c..581e89f 100644
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -249,7 +249,7 @@ void si_dma_copy(struct pipe_context *ctx,
(rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << 
dst_level) ||
rdst->cmask.size || rdst->fmask.size ||
rsrc->cmask.size || rsrc->fmask.size ||
-   rdst->surface.dcc_enabled || rsrc->surface.dcc_enabled) {
+   rdst->dcc_buffer || rsrc->dcc_buffer) {
goto fallback;
}
 
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index c87f661..18b6405 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1926,7 +1926,7 @@ static void si_initialize_color_surface(struct si_context 
*sctx,
surf->cb_color_info = color_info;
surf->cb_color_attrib = color_attrib;
 
-   if (sctx->b.chip_class >= VI && rtex->surface.dcc_enabled) {
+   if (sctx->b.chip_class >= VI && rtex->dcc_buffer) {
unsigned max_uncompressed_block_size = 2;
uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;
 
@@ -2655,7 +2655,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |

[Mesa-dev] [PATCH 5/7] nir: support to clone shaders

2015-10-24 Thread Rob Clark 
Signed-off-by: Rob Clark 
---
 src/glsl/Makefile.sources |1 +
 src/glsl/nir/nir.c|8 +
 src/glsl/nir/nir.h|2 +
 src/glsl/nir/nir_clone.c  | 1012 +
 4 files changed, 1023 insertions(+)
 create mode 100644 src/glsl/nir/nir_clone.c

diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
index ca87036..25e3801 100644
--- a/src/glsl/Makefile.sources
+++ b/src/glsl/Makefile.sources
@@ -26,6 +26,7 @@ NIR_FILES = \
nir/nir.h \
nir/nir_array.h \
nir/nir_builder.h \
+   nir/nir_clone.c \
nir/nir_constant_expressions.h \
nir/nir_control_flow.c \
nir/nir_control_flow.h \
diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c
index 0cbe4e1..2defa36 100644
--- a/src/glsl/nir/nir.c
+++ b/src/glsl/nir/nir.c
@@ -316,6 +316,14 @@ nir_block_create(nir_shader *shader)
block->predecessors = _mesa_set_create(block, _mesa_hash_pointer,
   _mesa_key_pointer_equal);
block->imm_dom = NULL;
+   /* XXX maybe it would be worth it to defer allocation?  This
+* way it doesn't get allocated for shader ref's that never run
+* nir_calc_dominance?  For example, state-tracker creates an
+* initial IR, clones that, runs appropriate lowering pass, passes
+* to driver which does common lowering/opt, and then stores ref
+* which is later used to do state specific lowering and futher
+* opt.  Do any of the references not need dominance metadata?
+*/
block->dom_frontier = _mesa_set_create(block, _mesa_hash_pointer,
   _mesa_key_pointer_equal);
 
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 2d9c94c..926747c 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1892,6 +1892,8 @@ void nir_index_blocks(nir_function_impl *impl);
 void nir_print_shader(nir_shader *shader, FILE *fp);
 void nir_print_instr(const nir_instr *instr, FILE *fp);
 
+nir_shader * nir_shader_clone(void *mem_ctx, const nir_shader *s);
+
 #ifdef DEBUG
 void nir_validate_shader(nir_shader *shader);
 #else
diff --git a/src/glsl/nir/nir_clone.c b/src/glsl/nir/nir_clone.c
new file mode 100644
index 000..0125f71
--- /dev/null
+++ b/src/glsl/nir/nir_clone.c
@@ -0,0 +1,1012 @@
+/*
+ * Copyright © 2015 Red Hat
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "nir_control_flow_private.h"
+
+// TODO move these:
+#define exec_list_head(type, list, node) \
+   exec_node_data(type, exec_list_get_head(list), node)
+#define exec_list_next(type, nodeptr, node) \
+   exec_node_data(type, exec_node_get_next(nodeptr), node)
+
+/* Secret Decoder Ring:
+ *   clone_foo() - allocate and clone a foo
+ *   __clone_foo() - clone body of foo (ie. parent class, embedded
+ *struct, etc)
+ *   __clone_foo_v2() - clone body of foo, pass 2.. since in first
+ *pass we can have fwd references to embedded structs,
+ *some ptrs (and things that depend on them) must be
+ *resolved in 2nd pass
+ */
+
+typedef struct {
+   struct hash_table *ptr_table;
+   /* memctx for new toplevel shader object: */
+   void *mem_ctx;
+   /* new shader object, used as memctx for just about everything else: */
+   nir_shader *ns;
+} clone_state;
+
+typedef void *(*clone_fxn)(clone_state *state, const void *ptr);
+
+static void
+init_clone_state(clone_state *state, void *mem_ctx)
+{
+   state->ptr_table = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
+  _mesa_key_pointer_equal);
+   state->mem_ctx = mem_ctx;
+}
+
+static void
+free_clone_state(clone_state *state)
+{
+   _mesa_hash_table_destroy(state->ptr_table, NULL);
+}
+
+static void *
+clone_ptr(clone_state *state, const void *ptr, clone_fxn clone)
+{
+   struct hash_entry *entry;
+   void *nptr;
+
+   if (!ptr)

[Mesa-dev] [PATCH 0/7] nir_shader_clone() and few bits

2015-10-24 Thread Rob Clark 
From: Rob Clark 

Mostly the implementation of nir_shader_clone() for copying a NIR
shader IR, plus couple cleanups, reference counting, and helper
macros.  The reference counting will be useful for mesa-st (and
perhaps other state trackers), since there are cases when both
mesa-st and the driver need to hold on to copies to do their own
variant management.

Couple small TODO's still..  The clone-test (NIR_TEST_CLONE=1, which
clones/revalidates/replaces the shader between each opt/lowering pass)
survives glmark2.  I need still to subject it to a piglit run.

I was originally going to use nir_cf_node_insert()/nir_instr_insert()
with the plan that they'd update the uses/defs/etc.  But that turned
out to be awkward, do to the order things get cloned if I use the
clone_ptr() aproach for blocks/etc (in particular w/ predecessor and
successor ptrs).  Instead it was easier to just export a fxn which
did the important (for us) bits of cf_node_insert()/instr_insert()

Rob Clark (7):
  nir: add nir_var_all enum
  nir: some small cleanups
  nir: export update_if_uses() and add_def_uses()
  nir: add couple array length fields
  nir: support to clone shaders
  nir: add shader reference counting
  nir: add helper macros for running NIR passes

 src/gallium/drivers/vc4/vc4_program.c   |2 +-
 src/glsl/Makefile.sources   |1 +
 src/glsl/nir/glsl_to_nir.cpp|6 +
 src/glsl/nir/nir.c  |   45 +-
 src/glsl/nir/nir.h  |  102 +++-
 src/glsl/nir/nir_clone.c| 1012 +++
 src/glsl/nir/nir_control_flow.c |6 +-
 src/glsl/nir/nir_control_flow_private.h |1 +
 src/glsl/nir/nir_lower_io.c |2 +-
 src/mesa/drivers/dri/i965/brw_nir.c |  127 ++--
 src/mesa/program/program.c  |3 +-
 11 files changed, 1202 insertions(+), 105 deletions(-)
 create mode 100644 src/glsl/nir/nir_clone.c

-- 
2.5.0

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[Mesa-dev] [PATCH 7/7] nir: add helper macros for running NIR passes

2015-10-24 Thread Rob Clark 
From: Rob Clark 

Convenient place to put in some extra sanity checking, without making
things messy for the drivers running the passes.

TODO: convert ir3/vc4..

Signed-off-by: Rob Clark 
---
 src/glsl/nir/nir.h  |  33 ++
 src/mesa/drivers/dri/i965/brw_nir.c | 126 
 2 files changed, 76 insertions(+), 83 deletions(-)

diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 3ab720b..053420d 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1939,10 +1939,43 @@ nir_shader_mutable(nir_shader *shader)
 
 #ifdef DEBUG
 void nir_validate_shader(nir_shader *shader);
+static inline bool
+__nir_test_clone(void)
+{
+   static int enable = -1;
+   if (enable == -1) {
+  enable = (getenv("NIR_TEST_CLONE") == NULL) ? 0 : 1;
+   }
+   return enable == 1;
+}
 #else
 static inline void nir_validate_shader(nir_shader *shader) { (void) shader; }
+static inline bool __nir_test_clone(void) { return false; }
 #endif /* DEBUG */
 
+
+#define NIR_PASS(pass, nir, ...) ({\
+  assert(nir_shader_is_mutable(nir));  \
+  pass(nir, ##__VA_ARGS__);\
+  nir_validate_shader(nir);\
+  if (__nir_test_clone()) {\
+ nir = nir_shader_clone(ralloc_parent(nir), nir);  \
+ nir_validate_shader(nir); \
+  }\
+   })
+
+#define NIR_PASS_PROGRESS(pass, nir, ...) ({   \
+  assert(nir_shader_is_mutable(nir));  \
+  bool __ret = pass(nir, ##__VA_ARGS__);   \
+  nir_validate_shader(nir);\
+  if (__nir_test_clone()) {\
+ nir = nir_shader_clone(ralloc_parent(nir), nir);  \
+ nir_validate_shader(nir); \
+  }\
+  __ret;   \
+   })
+
+
 void nir_calc_dominance_impl(nir_function_impl *impl);
 void nir_calc_dominance(nir_shader *shader);
 
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
b/src/mesa/drivers/dri/i965/brw_nir.c
index 8f09165..bc42fea 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -136,47 +136,34 @@ brw_nir_lower_outputs(nir_shader *nir, bool is_scalar)
}
 }
 
-static void
+static nir_shader *
 nir_optimize(nir_shader *nir, bool is_scalar)
 {
bool progress;
do {
   progress = false;
-  nir_lower_vars_to_ssa(nir);
-  nir_validate_shader(nir);
 
-  if (is_scalar) {
- nir_lower_alu_to_scalar(nir);
- nir_validate_shader(nir);
-  }
+  NIR_PASS(nir_lower_vars_to_ssa, nir);
 
-  progress |= nir_copy_prop(nir);
-  nir_validate_shader(nir);
+  if (is_scalar)
+ NIR_PASS(nir_lower_alu_to_scalar, nir);
 
-  if (is_scalar) {
- nir_lower_phis_to_scalar(nir);
- nir_validate_shader(nir);
-  }
+  progress |= NIR_PASS_PROGRESS(nir_copy_prop, nir);
+
+  if (is_scalar)
+ NIR_PASS(nir_lower_phis_to_scalar, nir);
 
-  progress |= nir_copy_prop(nir);
-  nir_validate_shader(nir);
-  progress |= nir_opt_dce(nir);
-  nir_validate_shader(nir);
-  progress |= nir_opt_cse(nir);
-  nir_validate_shader(nir);
-  progress |= nir_opt_peephole_select(nir);
-  nir_validate_shader(nir);
-  progress |= nir_opt_algebraic(nir);
-  nir_validate_shader(nir);
-  progress |= nir_opt_constant_folding(nir);
-  nir_validate_shader(nir);
-  progress |= nir_opt_dead_cf(nir);
-  nir_validate_shader(nir);
-  progress |= nir_opt_remove_phis(nir);
-  nir_validate_shader(nir);
-  progress |= nir_opt_undef(nir);
-  nir_validate_shader(nir);
+  progress |= NIR_PASS_PROGRESS(nir_copy_prop, nir);
+  progress |= NIR_PASS_PROGRESS(nir_opt_dce, nir);
+  progress |= NIR_PASS_PROGRESS(nir_opt_cse, nir);
+  progress |= NIR_PASS_PROGRESS(nir_opt_peephole_select, nir);
+  progress |= NIR_PASS_PROGRESS(nir_opt_algebraic, nir);
+  progress |= NIR_PASS_PROGRESS(nir_opt_constant_folding, nir);
+  progress |= NIR_PASS_PROGRESS(nir_opt_dead_cf, nir);
+  progress |= NIR_PASS_PROGRESS(nir_opt_remove_phis, nir);
+  progress |= NIR_PASS_PROGRESS(nir_opt_undef, nir);
} while (progress);
+   return nir;
 }
 
 nir_shader *
@@ -204,75 +191,52 @@ brw_create_nir(struct brw_context *brw,
}
nir_validate_shader(nir);
 
-   if (stage == MESA_SHADER_GEOMETRY) {
-  nir_lower_gs_intrinsics(nir);
-  nir_validate_shader(nir);
-   }
+   if (stage == MESA_SHADER_GEOMETRY)
+  NIR_PASS(nir_lower_gs_intrinsics, nir);
 
-   nir_lower_global_vars_to_local(nir);
-   nir_validate_shader(nir);
-
-   nir_lower_tex(nir, _options);
-

[Mesa-dev] [PATCH 3/7] nir: export update_if_uses() and add_def_uses()

2015-10-24 Thread Rob Clark 
From: Rob Clark 

Add it to the private interface, since we'll need it for nir_clone().

Signed-off-by: Rob Clark 
---
 src/glsl/nir/nir.c  | 13 +++--
 src/glsl/nir/nir.h  |  2 ++
 src/glsl/nir/nir_control_flow.c |  6 +++---
 src/glsl/nir/nir_control_flow_private.h |  1 +
 4 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c
index 300e43f..0cbe4e1 100644
--- a/src/glsl/nir/nir.c
+++ b/src/glsl/nir/nir.c
@@ -728,11 +728,20 @@ add_reg_def_cb(nir_dest *dest, void *state)
return true;
 }
 
-static void
-add_defs_uses(nir_instr *instr)
+/* TODO better name.. for nir_clone we want to do add_use_cb and
+ * add_reg_def_cb (as part of the 2nd pass), but not add_ssa_def_cb.
+ */
+void
+nir_add_defs_uses(nir_instr *instr)
 {
nir_foreach_src(instr, add_use_cb, instr);
nir_foreach_dest(instr, add_reg_def_cb, instr);
+}
+
+static void
+add_defs_uses(nir_instr *instr)
+{
+   nir_add_defs_uses(instr);
nir_foreach_ssa_def(instr, add_ssa_def_cb, instr);
 }
 
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 097d65b..a09c2a6 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1771,6 +1771,8 @@ nir_after_cf_list(struct exec_list *cf_list)
return nir_after_cf_node(last_node);
 }
 
+void nir_add_defs_uses(nir_instr *instr);
+
 /**
  * Insert a NIR instruction at the given cursor.
  *
diff --git a/src/glsl/nir/nir_control_flow.c b/src/glsl/nir/nir_control_flow.c
index 7f51c4f..2c2ef7c 100644
--- a/src/glsl/nir/nir_control_flow.c
+++ b/src/glsl/nir/nir_control_flow.c
@@ -599,8 +599,8 @@ nir_handle_remove_jump(nir_block *block, nir_jump_type type)
nir_metadata_preserve(impl, nir_metadata_none);
 }
 
-static void
-update_if_uses(nir_cf_node *node)
+void
+nir_update_if_uses(nir_cf_node *node)
 {
if (node->type != nir_cf_node_if)
   return;
@@ -673,7 +673,7 @@ nir_cf_node_insert(nir_cursor cursor, nir_cf_node *node)
   stitch_blocks(block, after);
   stitch_blocks(before, block);
} else {
-  update_if_uses(node);
+  nir_update_if_uses(node);
   insert_non_block(before, node, after);
}
 }
diff --git a/src/glsl/nir/nir_control_flow_private.h 
b/src/glsl/nir/nir_control_flow_private.h
index f32b57a..c03c9ca 100644
--- a/src/glsl/nir/nir_control_flow_private.h
+++ b/src/glsl/nir/nir_control_flow_private.h
@@ -35,3 +35,4 @@
 
 void nir_handle_add_jump(nir_block *block);
 void nir_handle_remove_jump(nir_block *block, nir_jump_type type);
+void nir_update_if_uses(nir_cf_node *node);
-- 
2.5.0

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[Mesa-dev] [PATCH 6/7] nir: add shader reference counting

2015-10-24 Thread Rob Clark 
From: Rob Clark 

For gallium, at least, we'll need this to manage shader's lifetimes,
since in some cases both the driver and the state tracker will need
to hold on to a reference for variant managing.

Use nir_shader_mutable() before doing any IR opt/lowering/etc, to
ensure you are not modifying a copy someone else is also holding a
reference to.  In this way, unnecessary nir_shader_clone()s are
avoided whenever possible.

TODO: Any places missed to s/ralloc_free()/nir_shader_unref()/ outside
of freedreno/ir3?

Signed-off-by: Rob Clark 
---
 src/gallium/drivers/vc4/vc4_program.c |  2 +-
 src/glsl/nir/nir.c|  2 ++
 src/glsl/nir/nir.h| 43 +++
 src/mesa/program/program.c|  3 ++-
 4 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_program.c 
b/src/gallium/drivers/vc4/vc4_program.c
index 5d7564b..9a055df 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -1723,7 +1723,7 @@ vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
 c->num_uniforms);
 }
 
-ralloc_free(c->s);
+nir_shader_unref(c->s);
 
 return c;
 }
diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c
index 2defa36..53a11f5 100644
--- a/src/glsl/nir/nir.c
+++ b/src/glsl/nir/nir.c
@@ -36,6 +36,8 @@ nir_shader_create(void *mem_ctx,
 {
nir_shader *shader = ralloc(mem_ctx, nir_shader);
 
+   p_atomic_set(>refcount, 1);
+
exec_list_make_empty(>uniforms);
exec_list_make_empty(>inputs);
exec_list_make_empty(>outputs);
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 926747c..3ab720b 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -34,6 +34,7 @@
 #include "util/ralloc.h"
 #include "util/set.h"
 #include "util/bitset.h"
+#include "util/u_atomic.h"
 #include "nir_types.h"
 #include "shader_enums.h"
 #include 
@@ -1546,6 +1547,8 @@ typedef struct nir_shader_info {
 } nir_shader_info;
 
 typedef struct nir_shader {
+   int refcount;
+
/** list of uniforms (nir_variable) */
struct exec_list uniforms;
 
@@ -1894,6 +1897,46 @@ void nir_print_instr(const nir_instr *instr, FILE *fp);
 
 nir_shader * nir_shader_clone(void *mem_ctx, const nir_shader *s);
 
+static inline void
+nir_shader_ref(nir_shader *shader)
+{
+   p_atomic_inc(>refcount);
+}
+
+static inline void
+nir_shader_unref(nir_shader *shader)
+{
+   if (p_atomic_dec_zero(>refcount)) {
+  ralloc_free(shader);
+   }
+}
+
+/* A shader with only a single reference is mutable: */
+static inline bool
+nir_shader_is_mutable(nir_shader *shader)
+{
+   return p_atomic_read(>refcount) == 1;
+}
+
+/* Convert a shader reference into a mutable shader reference.  Ie. if
+ * there is only a single reference to the shader, then return that,
+ * otherwise clone and drop reference to existing shader.
+ *
+ * TODO maybe an assert that shader->refcnt == 1 in the various opt/
+ * lowering passes?  If only there was a good central place to put it.
+ */
+static inline nir_shader *
+nir_shader_mutable(nir_shader *shader)
+{
+   if (nir_shader_is_mutable(shader)) {
+  return shader;
+   } else {
+  nir_shader *ns = nir_shader_clone(ralloc_parent(shader), shader);
+  nir_shader_unref(shader);
+  return ns;
+   }
+}
+
 #ifdef DEBUG
 void nir_validate_shader(nir_shader *shader);
 #else
diff --git a/src/mesa/program/program.c b/src/mesa/program/program.c
index 0e78e6a..c2da66e 100644
--- a/src/mesa/program/program.c
+++ b/src/mesa/program/program.c
@@ -38,6 +38,7 @@
 #include "prog_parameter.h"
 #include "prog_instruction.h"
 #include "util/ralloc.h"
+#include "nir.h"
 
 
 /**
@@ -273,7 +274,7 @@ _mesa_delete_program(struct gl_context *ctx, struct 
gl_program *prog)
}
 
if (prog->nir) {
-  ralloc_free(prog->nir);
+  nir_shader_unref(prog->nir);
}
 
mtx_destroy(>Mutex);
-- 
2.5.0

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[Mesa-dev] [PATCH 2/7] nir: some small cleanups

2015-10-24 Thread Rob Clark 
The various cf nodes all get allocated w/ shader as their ralloc_parent,
so lets make this more explicit.  Plus couple other corrections/
clarifications.

Signed-off-by: Rob Clark 
---
 src/glsl/nir/nir.c | 18 +-
 src/glsl/nir/nir.h | 10 +-
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c
index caa9ffc..300e43f 100644
--- a/src/glsl/nir/nir.c
+++ b/src/glsl/nir/nir.c
@@ -306,9 +306,9 @@ nir_function_impl_create(nir_function_overload *overload)
 }
 
 nir_block *
-nir_block_create(void *mem_ctx)
+nir_block_create(nir_shader *shader)
 {
-   nir_block *block = ralloc(mem_ctx, nir_block);
+   nir_block *block = ralloc(shader, nir_block);
 
cf_init(>cf_node, nir_cf_node_block);
 
@@ -334,19 +334,19 @@ src_init(nir_src *src)
 }
 
 nir_if *
-nir_if_create(void *mem_ctx)
+nir_if_create(nir_shader *shader)
 {
-   nir_if *if_stmt = ralloc(mem_ctx, nir_if);
+   nir_if *if_stmt = ralloc(shader, nir_if);
 
cf_init(_stmt->cf_node, nir_cf_node_if);
src_init(_stmt->condition);
 
-   nir_block *then = nir_block_create(mem_ctx);
+   nir_block *then = nir_block_create(shader);
exec_list_make_empty(_stmt->then_list);
exec_list_push_tail(_stmt->then_list, >cf_node.node);
then->cf_node.parent = _stmt->cf_node;
 
-   nir_block *else_stmt = nir_block_create(mem_ctx);
+   nir_block *else_stmt = nir_block_create(shader);
exec_list_make_empty(_stmt->else_list);
exec_list_push_tail(_stmt->else_list, _stmt->cf_node.node);
else_stmt->cf_node.parent = _stmt->cf_node;
@@ -355,13 +355,13 @@ nir_if_create(void *mem_ctx)
 }
 
 nir_loop *
-nir_loop_create(void *mem_ctx)
+nir_loop_create(nir_shader *shader)
 {
-   nir_loop *loop = ralloc(mem_ctx, nir_loop);
+   nir_loop *loop = ralloc(shader, nir_loop);
 
cf_init(>cf_node, nir_cf_node_loop);
 
-   nir_block *body = nir_block_create(mem_ctx);
+   nir_block *body = nir_block_create(shader);
exec_list_make_empty(>body);
exec_list_push_tail(>body, >cf_node.node);
body->cf_node.parent = >cf_node;
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 79c0666..097d65b 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -395,10 +395,10 @@ typedef struct {
 */
bool is_packed;
 
-   /** set of nir_instr's where this register is used (read from) */
+   /** set of nir_src's where this register is used (read from) */
struct list_head uses;
 
-   /** set of nir_instr's where this register is defined (written to) */
+   /** set of nir_dest's where this register is defined (written to) */
struct list_head defs;
 
/** set of nir_if's where this register is used as a condition */
@@ -1622,9 +1622,9 @@ nir_function_overload 
*nir_function_overload_create(nir_function *func);
 
 nir_function_impl *nir_function_impl_create(nir_function_overload *func);
 
-nir_block *nir_block_create(void *mem_ctx);
-nir_if *nir_if_create(void *mem_ctx);
-nir_loop *nir_loop_create(void *mem_ctx);
+nir_block *nir_block_create(nir_shader *shader);
+nir_if *nir_if_create(nir_shader *shader);
+nir_loop *nir_loop_create(nir_shader *shader);
 
 nir_function_impl *nir_cf_node_get_function(nir_cf_node *node);
 
-- 
2.5.0

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[Mesa-dev] [PATCH 4/7] nir: add couple array length fields

2015-10-24 Thread Rob Clark 
From: Rob Clark 

This will simplify things somewhat in clone.

Signed-off-by: Rob Clark 
---
 src/glsl/nir/glsl_to_nir.cpp |  6 ++
 src/glsl/nir/nir.h   | 11 +++
 2 files changed, 17 insertions(+)

diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index 9b50a93..8f83012 100644
--- a/src/glsl/nir/glsl_to_nir.cpp
+++ b/src/glsl/nir/glsl_to_nir.cpp
@@ -238,6 +238,8 @@ constant_copy(ir_constant *ir, void *mem_ctx)
 
unsigned total_elems = ir->type->components();
unsigned i;
+
+   ret->num_elements = 0;
switch (ir->type->base_type) {
case GLSL_TYPE_UINT:
   for (i = 0; i < total_elems; i++)
@@ -262,6 +264,8 @@ constant_copy(ir_constant *ir, void *mem_ctx)
case GLSL_TYPE_STRUCT:
   ret->elements = ralloc_array(mem_ctx, nir_constant *,
ir->type->length);
+  ret->num_elements = ir->type->length;
+
   i = 0;
   foreach_in_list(ir_constant, field, >components) {
  ret->elements[i] = constant_copy(field, mem_ctx);
@@ -272,6 +276,7 @@ constant_copy(ir_constant *ir, void *mem_ctx)
case GLSL_TYPE_ARRAY:
   ret->elements = ralloc_array(mem_ctx, nir_constant *,
ir->type->length);
+  ret->num_elements = ir->type->length;
 
   for (i = 0; i < ir->type->length; i++)
  ret->elements[i] = constant_copy(ir->array_elements[i], mem_ctx);
@@ -293,6 +298,7 @@ nir_visitor::visit(ir_variable *ir)
 
if (ir->is_interface_instance() && ir->get_max_ifc_array_access() != NULL) {
   unsigned size = ir->get_interface_type()->length;
+  var->num_max_ifc_array_access = size;
   var->max_ifc_array_access = ralloc_array(var, unsigned, size);
   memcpy(var->max_ifc_array_access, ir->get_max_ifc_array_access(),
  size * sizeof(unsigned));
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index a09c2a6..2d9c94c 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -112,6 +112,11 @@ typedef struct nir_constant {
 */
union nir_constant_data value;
 
+   /* we could get this from the var->type but makes clone *much* easier to
+* not have to care about the type.
+*/
+   unsigned num_elements;
+
/* Array elements / Structure Fields */
struct nir_constant **elements;
 } nir_constant;
@@ -148,6 +153,12 @@ typedef struct {
 */
char *name;
 
+   /* we could figure this out from interface_type but it isn't exposed
+* cleanly outside of c++ and just having the length here simplifies
+* clone:
+*/
+   unsigned num_max_ifc_array_access;
+
/**
 * For variables which satisfy the is_interface_instance() predicate, this
 * points to an array of integers such that if the ith member of the
-- 
2.5.0

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[Mesa-dev] [PATCH 1/7] nir: add nir_var_all enum

2015-10-24 Thread Rob Clark 
Otherwise, passing -1 gets you:

  error: invalid conversion from 'int' to 'nir_variable_mode' [-fpermissive]

Signed-off-by: Rob Clark 
---
 src/glsl/nir/nir.c  | 4 
 src/glsl/nir/nir.h  | 1 +
 src/glsl/nir/nir_lower_io.c | 2 +-
 src/mesa/drivers/dri/i965/brw_nir.c | 3 ++-
 4 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c
index 793bdaf..caa9ffc 100644
--- a/src/glsl/nir/nir.c
+++ b/src/glsl/nir/nir.c
@@ -107,6 +107,10 @@ void
 nir_shader_add_variable(nir_shader *shader, nir_variable *var)
 {
switch (var->data.mode) {
+   case nir_var_all:
+  assert(!"invalid mode");
+  break;
+
case nir_var_local:
   assert(!"nir_shader_add_variable cannot be used for local variables");
   break;
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index e3777f9..79c0666 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -82,6 +82,7 @@ typedef struct {
 } nir_state_slot;
 
 typedef enum {
+   nir_var_all = -1,
nir_var_shader_in,
nir_var_shader_out,
nir_var_global,
diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c
index 688b48f..b4ed857 100644
--- a/src/glsl/nir/nir_lower_io.c
+++ b/src/glsl/nir/nir_lower_io.c
@@ -176,7 +176,7 @@ nir_lower_io_block(nir_block *block, void *void_state)
 
   nir_variable_mode mode = intrin->variables[0]->var->data.mode;
 
-  if (state->mode != -1 && state->mode != mode)
+  if (state->mode != nir_var_all && state->mode != mode)
  continue;
 
   switch (intrin->intrinsic) {
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
b/src/mesa/drivers/dri/i965/brw_nir.c
index 1b4dace..8f09165 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -235,7 +235,8 @@ brw_create_nir(struct brw_context *brw,
nir_assign_var_locations(>uniforms,
 >num_uniforms,
 is_scalar ? type_size_scalar : type_size_vec4);
-   nir_lower_io(nir, -1, is_scalar ? type_size_scalar : type_size_vec4);
+   nir_lower_io(nir, nir_var_all,
+is_scalar ? type_size_scalar : type_size_vec4);
nir_validate_shader(nir);
 
nir_remove_dead_variables(nir);
-- 
2.5.0

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Re: [Mesa-dev] [PATCH] gallivm: disable f16c when not using AVX

2015-10-24 Thread Nicolai Hähnle 

On 23.10.2015 23:26, srol...@vmware.com wrote:

From: Roland Scheidegger 

f16c intrinsic can only be emitted when AVX is used. So when we disable AVX
due to forcing 128bit vectors we must not use this intrinsic (depending on
llvm version, this worked previously because llvm used AVX even when we didn't
tell it to, however I've seen this fail with llvm 3.3 since
718249843b915decf8fccec92e466ac1a6219934 which seems to have the side effect
of disabling avx in llvm albeit it only touches sse flags really).
Possibly one day should actually try to use avx even with 128bit vectors...


Reviewed-by: Nicolai Hähnle 


---
  src/gallium/auxiliary/gallivm/lp_bld_init.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c 
b/src/gallium/auxiliary/gallivm/lp_bld_init.c
index 017d075..e6eede8 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
@@ -427,6 +427,7 @@ lp_build_init(void)
 */
util_cpu_caps.has_avx = 0;
util_cpu_caps.has_avx2 = 0;
+  util_cpu_caps.has_f16c = 0;
 }

  #ifdef PIPE_ARCH_PPC_64



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Re: [Mesa-dev] [PATCH 1/3] radeonsi: simplify DCC handling in si_initialize_color_surface

2015-10-24 Thread Nicolai Hähnle 
With the remark on patch 2 (radeonsi: properly check if DCC is enabled 
and allocated), the series is


Reviewed-by: Nicolai Hähnle 

On 24.10.2015 17:49, Marek Olšák wrote:

From: Marek Olšák 

---
  src/gallium/drivers/radeonsi/si_state.c | 10 +++---
  1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 384c8e2..c87f661 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1926,8 +1926,9 @@ static void si_initialize_color_surface(struct si_context 
*sctx,
surf->cb_color_info = color_info;
surf->cb_color_attrib = color_attrib;

-   if (sctx->b.chip_class >= VI) {
+   if (sctx->b.chip_class >= VI && rtex->surface.dcc_enabled) {
unsigned max_uncompressed_block_size = 2;
+   uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;

if (rtex->surface.nsamples > 1) {
if (rtex->surface.bpe == 1)
@@ -1938,12 +1939,7 @@ static void si_initialize_color_surface(struct 
si_context *sctx,

surf->cb_dcc_control = 
S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
   S_028C78_INDEPENDENT_64B_BLOCKS(1);
-
-   if (rtex->surface.dcc_enabled) {
-   uint64_t dcc_offset = 
rtex->surface.level[level].dcc_offset;
-
-   surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + 
dcc_offset) >> 8;
-   }
+   surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + dcc_offset) 
>> 8;
}

if (rtex->fmask.size) {



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Re: [Mesa-dev] [PATCH 2/3] radeonsi: properly check if DCC is enabled and allocated

2015-10-24 Thread Nicolai Hähnle 

On 24.10.2015 17:49, Marek Olšák wrote:

From: Marek Olšák 

---
  src/gallium/drivers/radeon/r600_texture.c | 2 +-
  src/gallium/drivers/radeonsi/cik_sdma.c   | 2 +-
  src/gallium/drivers/radeonsi/si_blit.c| 6 +++---
  src/gallium/drivers/radeonsi/si_dma.c | 2 +-
  src/gallium/drivers/radeonsi/si_state.c   | 4 ++--
  5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index f7a11a2..40075ae 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1367,7 +1367,7 @@ void evergreen_do_fast_color_clear(struct 
r600_common_context *rctx,
continue;
}

-   if (tex->surface.dcc_enabled) {
+   if (tex->dcc_buffer) {
uint32_t reset_value;
bool clear_words_needed;

diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c 
b/src/gallium/drivers/radeonsi/cik_sdma.c
index 25fd09a..e53af1d 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -243,7 +243,7 @@ void cik_sdma_copy(struct pipe_context *ctx,
if (src->format != dst->format ||
rdst->surface.nsamples > 1 || rsrc->surface.nsamples > 1 ||
(rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << 
dst_level) ||
-   rdst->surface.dcc_enabled || rsrc->surface.dcc_enabled) {
+   rdst->dcc_buffer || rsrc->dcc_buffer) {
goto fallback;
}

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index a226436..302b75c 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -326,7 +326,7 @@ void si_decompress_color_textures(struct si_context *sctx,
assert(view);

tex = (struct r600_texture *)view->texture;
-   assert(tex->cmask.size || tex->fmask.size || 
tex->surface.dcc_enabled);
+   assert(tex->cmask.size || tex->fmask.size || tex->dcc_buffer);

si_blit_decompress_color(>b.b, tex,
 view->u.tex.first_level, 
view->u.tex.last_level,
@@ -455,7 +455,7 @@ static void si_decompress_subresource(struct pipe_context 
*ctx,
si_blit_decompress_depth_in_place(sctx, rtex, true,
  level, level,
  first_layer, 
last_layer);
-   } else if (rtex->fmask.size || rtex->cmask.size || 
rtex->surface.dcc_enabled) {
+   } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_buffer) {
si_blit_decompress_color(ctx, rtex, level, level,
 first_layer, last_layer);
}
@@ -676,7 +676,7 @@ static bool do_hardware_msaa_resolve(struct pipe_context 
*ctx,
dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
!(dst->surface.flags & RADEON_SURF_SCANOUT) &&
(!dst->cmask.size || !dst->dirty_level_mask) && /* dst cannot be 
fast-cleared */
-   !dst->surface.dcc_enabled) {
+   !dst->dcc_buffer) {
si_blitter_begin(ctx, SI_COLOR_RESOLVE |
 (info->render_condition_enable ? 0 : 
SI_DISABLE_RENDER_COND));
util_blitter_custom_resolve_color(sctx->blitter,
diff --git a/src/gallium/drivers/radeonsi/si_dma.c 
b/src/gallium/drivers/radeonsi/si_dma.c
index 73c026c..581e89f 100644
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -249,7 +249,7 @@ void si_dma_copy(struct pipe_context *ctx,
(rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << 
dst_level) ||
rdst->cmask.size || rdst->fmask.size ||
rsrc->cmask.size || rsrc->fmask.size ||
-   rdst->surface.dcc_enabled || rsrc->surface.dcc_enabled) {
+   rdst->dcc_buffer || rsrc->dcc_buffer) {
goto fallback;
}

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index c87f661..18b6405 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1926,7 +1926,7 @@ static void si_initialize_color_surface(struct si_context 
*sctx,
surf->cb_color_info = color_info;
surf->cb_color_attrib = color_attrib;

-   if (sctx->b.chip_class >= VI && rtex->surface.dcc_enabled) {
+   if (sctx->b.chip_class >= VI && rtex->dcc_buffer) {
unsigned max_uncompressed_block_size = 2;
uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;

@@ -2655,7 +2655,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |

[Mesa-dev] [PATCH 2/2] i965/vec4: Drop brw_set_default_* before popping insn state.

2015-10-24 Thread Matt Turner 
---
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index d50184a..cd8eb0e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -367,7 +367,6 @@ generate_gs_urb_write_allocate(struct brw_codegen *p, 
vec4_instruction *inst)
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, get_element_ud(inst->dst.fixed_hw_reg, 0),
get_element_ud(inst->src[0].fixed_hw_reg, 0));
-   brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_pop_insn_state(p);
 }
 
@@ -424,7 +423,6 @@ generate_gs_set_write_offset(struct brw_codegen *p,
   brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
   retype(src1, BRW_REGISTER_TYPE_UW));
}
-   brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_pop_insn_state(p);
 }
 
@@ -458,7 +456,6 @@ generate_gs_set_vertex_count(struct brw_codegen *p,
   brw_MOV(p,
   suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
   stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
-  brw_set_default_access_mode(p, BRW_ALIGN_16);
}
brw_pop_insn_state(p);
 }
-- 
2.4.9

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[Mesa-dev] [PATCH 1/2] i965/vec4: Remove unnecessary #includes from the generator.

2015-10-24 Thread Matt Turner 
---
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 8 
 1 file changed, 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 6569d81..d50184a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -20,18 +20,10 @@
  * IN THE SOFTWARE.
  */
 
-#include 
 #include "glsl/glsl_parser_extras.h"
 #include "brw_vec4.h"
 #include "brw_cfg.h"
 
-extern "C" {
-#include "brw_eu.h"
-#include "main/macros.h"
-#include "program/prog_print.h"
-#include "program/prog_parameter.h"
-};
-
 using namespace brw;
 
 static void
-- 
2.4.9

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[Mesa-dev] [PATCH] r600: Fix special negative immediate constants when using ABS modifier.

2015-10-24 Thread Ivan Kalvachev 
Some constants (like 1.0 and 0.5) could be inlined as immediate inputs
without using their literal value. The r600_bytecode_special_constants()
function emulates the negative of these constants by using NEG modifier.

However some shaders define -1.0 constant and want to use it as 1.0.
They do so by using ABS modifier. But r600_bytecode_special_constants()
set NEG in addition to ABS. Since NEG modifier have priority over ABS one,
we get -|1.0| as result, instead of |1.0|.

The patch simply prevents the additional switching of NEG when ABS is set.

Signed-off-by: Ivan Kalvachev 
---
 src/gallium/drivers/r600/r600_asm.c| 9 +
 src/gallium/drivers/r600/r600_shader.c | 2 +-
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index bc69806..8fc622c 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -635,8 +635,9 @@ static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
return 0;
 }

-void r600_bytecode_special_constants(uint32_t value, unsigned *sel,
unsigned *neg)
+void r600_bytecode_special_constants(uint32_t value, unsigned *sel,
unsigned *neg, unsigned abs)
 {
+
switch(value) {
case 0:
*sel = V_SQ_ALU_SRC_0;
@@ -655,11 +656,11 @@ void r600_bytecode_special_constants(uint32_t
value, unsigned *sel, unsigned *ne
break;
case 0xBF80: /* -1.0f */
*sel = V_SQ_ALU_SRC_1;
-   *neg ^= 1;
+   *neg ^= !abs;
break;
case 0xBF00: /* -0.5f */
*sel = V_SQ_ALU_SRC_0_5;
-   *neg ^= 1;
+   *neg ^= !abs;
break;
default:
*sel = V_SQ_ALU_SRC_LITERAL;
@@ -1208,7 +1209,7 @@ int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
}
if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
r600_bytecode_special_constants(nalu->src[i].value,
-   >src[i].sel, >src[i].neg);
+   >src[i].sel, >src[i].neg,
nalu->src[i].abs);
}
if (nalu->dst.sel >= bc->ngpr) {
bc->ngpr = nalu->dst.sel + 1;
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 8efe902..50c0329 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1008,7 +1008,7 @@ static void tgsi_src(struct r600_shader_ctx *ctx,
(tgsi_src->Register.SwizzleX ==
tgsi_src->Register.SwizzleW)) {

index = tgsi_src->Register.Index * 4 +
tgsi_src->Register.SwizzleX;
-
r600_bytecode_special_constants(ctx->literals[index], _src->sel,
_src->neg);
+
r600_bytecode_special_constants(ctx->literals[index], _src->sel,
_src->neg, r600_src->abs);
if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
return;
}
-- 
2.5.1
From b768c789d74fad611c9065a2a9520ec60fa41bd9 Mon Sep 17 00:00:00 2001
From: Ivan Kalvachev 
Date: Sun, 25 Oct 2015 01:16:58 +0300
Subject: [PATCH] r600: Fix special negative immediate constants when using ABS
 modifier.

Some constants (like 1.0 and 0.5) could be inlined as immediate inputs
without using their literal value. The r600_bytecode_special_constants()
function emulates the negative of these constants by using NEG modifier.

However some shaders define -1.0 constant and want to use it as 1.0.
They do so by using ABS modifier. But r600_bytecode_special_constants()
set NEG in addition to ABS. Since NEG modifier have priority over ABS one,
we get -|1.0| as result, instead of |1.0|.

The patch simply prevents the additional switching of NEG when ABS is set.

Signed-off-by: Ivan Kalvachev 
---
 src/gallium/drivers/r600/r600_asm.c| 9 +
 src/gallium/drivers/r600/r600_shader.c | 2 +-
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index bc69806..8fc622c 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -635,8 +635,9 @@ static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
 	return 0;
 }
 
-void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
+void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg, unsigned abs)
 {
+
 	switch(value) {
 	case 0:
 		*sel = V_SQ_ALU_SRC_0;
@@ -655,11 +656,11 @@ void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *ne
 		break;
 	case 0xBF80: /* -1.0f */
 		*sel = V_SQ_ALU_SRC_1;
-		*neg ^= 1;
+		*neg ^= !abs;
 		break;
 	case 0xBF00: /* -0.5f */
 		*sel = V_SQ_ALU_SRC_0_5;
-		*neg ^= 1;
+		*neg ^= !abs;
 		break;
 	default:
 		*sel = V_SQ_ALU_SRC_LITERAL;
@@ -1208,7 +1209,7 @@

Re: [Mesa-dev] [PATCH 1/4] i965/vec4: Convert src_reg/dst_reg to brw_reg at the end of the visitor.

2015-10-24 Thread Matt Turner 
Nice. All four are

Reviewed-by: Matt Turner 

I'll send two trivial clean ups as well.
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[Mesa-dev] [PATCH] glsl: Convert TES gl_PatchVerticesIn into a constant when using a TCS.

2015-10-24 Thread Kenneth Graunke 
When a TCS is present, the TES input gl_PatchVerticesIn is actually a
constant - it's simply the # of output vertices specified by the TCS
layout qualifiers.  So, we can replace the system value with a constant,
which may allow further optimization, and will likely be more efficient.

If the TCS is absent, we can't do this optimization.

Cc: Ilia Mirkin 
Cc: Marek Olšák 
Signed-off-by: Kenneth Graunke 
---
 src/glsl/linker.cpp | 16 
 1 file changed, 16 insertions(+)

Works for me on i965, but I haven't set up other drivers to test
them (sorry...)

diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 424b92a..cfd8f81 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -2282,6 +2282,22 @@ resize_tes_inputs(struct gl_context *ctx,
foreach_in_list(ir_instruction, ir, tes->ir) {
   ir->accept(_resize_visitor);
}
+
+   if (tcs) {
+  /* Convert the gl_PatchVerticesIn system value into a constant, since
+   * the value is known at this point.
+   */
+  foreach_in_list(ir_instruction, ir, tes->ir) {
+ ir_variable *var = ir->as_variable();
+ if (var && var->data.mode == ir_var_system_value &&
+ var->data.location == SYSTEM_VALUE_VERTICES_IN) {
+void *mem_ctx = ralloc_parent(var);
+var->data.mode = ir_var_auto;
+var->data.location = 0;
+var->constant_value = new(mem_ctx) ir_constant(num_vertices);
+ }
+  }
+   }
 }
 
 /**
-- 
2.6.2

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