[Mesa-dev] [Bug 95190] Tomb Raider with PostProcessing enable and Depth of Field set to Ultra has white stuff in the foreground

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=95190

--- Comment #9 from Ilia Mirkin  ---
(In reply to Timothy Arceri from comment #8)
> My thinking at the time was that we need to convert the 'const foo[]' to
> 'uniform foo[]' before other optimisations passes such as constant
> propagation start messing with it.

We need to be careful to only do that for indirect accesses though - otherwise
we'll end up sticking things into uniforms that could have been
const-propagated.

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[Mesa-dev] [Bug 95190] Tomb Raider with PostProcessing enable and Depth of Field set to Ultra has white stuff in the foreground

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=95190

--- Comment #8 from Timothy Arceri  ---
I noticed and attempted to fix this a couple of weeks ago as it was giving me
problems with my shader cache work. In the end I dropped it in the too hard
basket and did this work around for my issue:
https://github.com/tarceri/Mesa_arrays_of_arrays/commit/1cd0191635ad3a0d775077493b4ee28875280fa0

The problem as Ilia points out is that a new unidentifiable ir_constant array
is propagated to each reference of the const array, this means we end up with a
new uniform array of the entire array each time we access a single element.

My thinking at the time was that we need to convert the 'const foo[]' to
'uniform foo[]' before other optimisations passes such as constant propagation
start messing with it.

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Re: [Mesa-dev] [PATCH 02/13] nir/builder: Add bit_size info to nir_build_imm()

[Samuel Iglesias Gonsálvez]

On 28/04/16 19:40, Mark Janes wrote:
> Hi Samuel,
> 
> When this patch was pushed, it broke the vulkan build.  Can you please
> add "--with-vulkan-drivers=intel" to the build-test that you run before
> pushing?
> 

I'm sorry for the inconveniences caused. I didn't notice this change
would break vulkan build.

I have just added that argument to my build.

Thanks,

Sam

> thanks,
> 
> Mark
> 
> Samuel Iglesias Gonsálvez  writes:
> 
>> Signed-off-by: Samuel Iglesias Gonsálvez 
>> ---
>>  src/compiler/nir/nir_builder.h | 15 ---
>>  src/compiler/nir/nir_lower_system_values.c |  2 +-
>>  src/compiler/nir/nir_lower_tex.c   |  2 +-
>>  3 files changed, 10 insertions(+), 9 deletions(-)
>>
>> diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
>> index 38a1cf7..84fc9bf 100644
>> --- a/src/compiler/nir/nir_builder.h
>> +++ b/src/compiler/nir/nir_builder.h
>> @@ -89,10 +89,11 @@ nir_ssa_undef(nir_builder *build, unsigned 
>> num_components, unsigned bit_size)
>>  }
>>  
>>  static inline nir_ssa_def *
>> -nir_build_imm(nir_builder *build, unsigned num_components, nir_const_value 
>> value)
>> +nir_build_imm(nir_builder *build, unsigned num_components,
>> +  nir_const_value value, unsigned bit_size)
>>  {
>> nir_load_const_instr *load_const =
>> -  nir_load_const_instr_create(build->shader, num_components, 32);
>> +  nir_load_const_instr_create(build->shader, num_components, bit_size);
>> if (!load_const)
>>return NULL;
>>  
>> @@ -111,7 +112,7 @@ nir_imm_float(nir_builder *build, float x)
>> memset(, 0, sizeof(v));
>> v.f32[0] = x;
>>  
>> -   return nir_build_imm(build, 1, v);
>> +   return nir_build_imm(build, 1, v, 32);
>>  }
>>  
>>  static inline nir_ssa_def *
>> @@ -125,7 +126,7 @@ nir_imm_vec4(nir_builder *build, float x, float y, float 
>> z, float w)
>> v.f32[2] = z;
>> v.f32[3] = w;
>>  
>> -   return nir_build_imm(build, 4, v);
>> +   return nir_build_imm(build, 4, v, 32);
>>  }
>>  
>>  static inline nir_ssa_def *
>> @@ -136,7 +137,7 @@ nir_imm_int(nir_builder *build, int x)
>> memset(, 0, sizeof(v));
>> v.i32[0] = x;
>>  
>> -   return nir_build_imm(build, 1, v);
>> +   return nir_build_imm(build, 1, v, 32);
>>  }
>>  
>>  static inline nir_ssa_def *
>> @@ -150,14 +151,14 @@ nir_imm_ivec4(nir_builder *build, int x, int y, int z, 
>> int w)
>> v.i32[2] = z;
>> v.i32[3] = w;
>>  
>> -   return nir_build_imm(build, 4, v);
>> +   return nir_build_imm(build, 4, v, 32);
>>  }
>>  
>>  static inline nir_ssa_def *
>>  nir_imm_uint(nir_builder *build, unsigned x)
>>  {
>> nir_const_value v = { { .u32 = {x, 0, 0, 0} } };
>> -   return nir_build_imm(build, 1, v);
>> +   return nir_build_imm(build, 1, v, 32);
>>  }
>>  
>>  static inline nir_ssa_def *
>> diff --git a/src/compiler/nir/nir_lower_system_values.c 
>> b/src/compiler/nir/nir_lower_system_values.c
>> index 2d3ccd7..8362619 100644
>> --- a/src/compiler/nir/nir_lower_system_values.c
>> +++ b/src/compiler/nir/nir_lower_system_values.c
>> @@ -75,7 +75,7 @@ convert_block(nir_block *block, void *void_state)
>>  nir_load_system_value(b, 
>> nir_intrinsic_load_local_invocation_id, 0);
>>  
>>   sysval = nir_iadd(b, nir_imul(b, group_id,
>> -  nir_build_imm(b, 3, local_size)),
>> +  nir_build_imm(b, 3, local_size, 
>> 32)),
>>local_id);
>>   break;
>>}
>> diff --git a/src/compiler/nir/nir_lower_tex.c 
>> b/src/compiler/nir/nir_lower_tex.c
>> index 4999603..47a3786 100644
>> --- a/src/compiler/nir/nir_lower_tex.c
>> +++ b/src/compiler/nir/nir_lower_tex.c
>> @@ -232,7 +232,7 @@ get_zero_or_one(nir_builder *b, nir_alu_type type, 
>> uint8_t swizzle_val)
>>   v.u32[0] = v.u32[1] = v.u32[2] = v.u32[3] = 1;
>> }
>>  
>> -   return nir_build_imm(b, 4, v);
>> +   return nir_build_imm(b, 4, v, 32);
>>  }
>>  
>>  static void
>> -- 
>> 2.5.0
>>
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[Mesa-dev] [PATCH demos] egl: Add es2eglkms demo

[Dongseong Hwang]

This demo shows how ChromeOS renders OpenGL ES2 via kms, drm and gbm.
This demo consists of
1. kms modesetting and vsync
2. EGL and GLES2 context creation
3. gbm bo creation and EGL Image binding

drm connection code is copied from eglkms.
ES2 rendering code is copied from es2tri.

Signed-off-by: Dongseong Hwang 
---
 src/egl/opengles2/Makefile.am |   9 +
 src/egl/opengles2/es2eglkms.c | 608 ++
 2 files changed, 617 insertions(+)
 create mode 100644 src/egl/opengles2/es2eglkms.c

diff --git a/src/egl/opengles2/Makefile.am b/src/egl/opengles2/Makefile.am
index b80ba50..2564a74 100644
--- a/src/egl/opengles2/Makefile.am
+++ b/src/egl/opengles2/Makefile.am
@@ -45,6 +45,11 @@ endif
 if HAVE_WAYLAND
 bin_PROGRAMS += es2gears_wayland
 endif
+if HAVE_DRM
+if HAVE_GBM
+bin_PROGRAMS += es2eglkms
+endif
+endif
 endif
 endif
 
@@ -57,3 +62,7 @@ es2gears_x11_LDADD = ../eglut/libeglut_x11.la
 
 es2gears_wayland_SOURCES = es2gears.c
 es2gears_wayland_LDADD = ../eglut/libeglut_wayland.la
+
+es2eglkms_SOURCES = es2eglkms.c
+es2eglkms_CFLAGS = $(AM_CFLAGS) $(DRM_CFLAGS) $(GBM_CFLAGS)
+es2eglkms_LDADD = $(AM_LDFLAGS) $(DRM_LIBS) $(GBM_LIBS)
\ No newline at end of file
diff --git a/src/egl/opengles2/es2eglkms.c b/src/egl/opengles2/es2eglkms.c
new file mode 100644
index 000..95b3ade
--- /dev/null
+++ b/src/egl/opengles2/es2eglkms.c
@@ -0,0 +1,608 @@
+/*
+ * Copyright © 2016 Dongseong Hwang
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission.  The copyright holders make no representations
+ * about the suitability of this software for any purpose.  It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define EGL_EGLEXT_PROTOTYPES
+#define GL_GLEXT_PROTOTYPES
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+// double buffering
+#define NUM_BUFFERS 2
+
+struct framebuffer {
+   struct gbm_bo *bo;
+   int fd;
+   uint32_t fb_id;
+   EGLImageKHR image;
+   GLuint gl_tex;
+   GLuint gl_fb;
+};
+
+struct kms {
+   drmModeConnector *connector;
+   drmModeEncoder *encoder;
+   drmModeModeInfo mode;
+};
+
+struct gl {
+   GLuint program;
+   GLfloat view_rotz;
+   GLint u_matrix;
+   GLint attr_pos;
+   GLint attr_color;
+
+   PFNEGLCREATESYNCKHRPROC eglCreateSyncKHR;
+   PFNEGLCLIENTWAITSYNCKHRPROC eglClientWaitSyncKHR;
+};
+
+static void make_z_rot_matrix(GLfloat angle, GLfloat *m)
+{
+   float c = cos(angle * M_PI / 180.0);
+   float s = sin(angle * M_PI / 180.0);
+   int i;
+   for (i = 0; i < 16; i++)
+  m[i] = 0.0;
+   m[0] = m[5] = m[10] = m[15] = 1.0;
+
+   m[0] = c;
+   m[1] = s;
+   m[4] = -s;
+   m[5] = c;
+}
+
+static void make_scale_matrix(GLfloat xs, GLfloat ys, GLfloat zs, GLfloat *m)
+{
+   int i;
+   for (i = 0; i < 16; i++)
+  m[i] = 0.0;
+   m[0] = xs;
+   m[5] = ys;
+   m[10] = zs;
+   m[15] = 1.0;
+}
+
+static void mul_matrix(GLfloat *prod, const GLfloat *a, const GLfloat *b)
+{
+#define A(row, col) a[(col << 2) + row]
+#define B(row, col) b[(col << 2) + row]
+#define P(row, col) p[(col << 2) + row]
+   GLfloat p[16];
+   GLint i;
+   for (i = 0; i < 4; i++) {
+  const GLfloat ai0 = A(i, 0), ai1 = A(i, 1), ai2 = A(i, 2), ai3 = A(i, 3);
+  P(i, 0) = ai0 * B(0, 0) + ai1 * B(1, 0) + ai2 * B(2, 0) + ai3 * B(3, 0);
+  P(i, 1) = ai0 * B(0, 1) + ai1 * B(1, 1) + ai2 * B(2, 1) + ai3 * B(3, 1);
+  P(i, 2) = ai0 * B(0, 2) + ai1 * B(1, 2) + ai2 * B(2, 2) + ai3 * B(3, 2);
+  P(i, 3) = ai0 * B(0, 3) + ai1 * B(1, 3) + ai2 * B(2, 3) + ai3 * B(3, 3);
+   }
+   memcpy(prod, p, sizeof(p));
+#undef A
+#undef B
+#undef PROD
+}
+
+static EGLBoolean setup_kms(int fd, struct kms *kms)
+{
+   drmModeRes *resources;
+   drmModeConnector *connector;
+   drmModeEncoder *encoder;
+   int i;
+
+   resources = drmModeGetResources(fd);
+   if (!resources) {
+  fprintf(stderr, "drmModeGetResources failed\n");
+  return EGL_FALSE;
+   }
+
+   for (i = 0; i < 

[Mesa-dev] [Bug 95190] Tomb Raider with PostProcessing enable and Depth of Field set to Ultra has white stuff in the foreground

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=95190

--- Comment #7 from Ilia Mirkin  ---
OK, so the issue is that it's a different(ish) constant array every time. Code
that's like

const foo[] = bar

foo[]
foo[]
foo[]

becomes

bar[]
bar[]
bar[]

And so in essence we have 3 arrays, each of which is becoming its own uniform.
I tried adding a hash table on ir_constant*, but that was useless, since
they're different ir_constant* pointers each time. This is going to be a bit
tricky... I guess we could hash the actual data. Probably other solutions I'm
neglecting, too.

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Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: reduce stack explosion in recursive expression visitor

[Ilia Mirkin]

On Tue, Apr 26, 2016 at 11:25 AM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> In optimized builds, visit(ir_expression *) experiences inlining with gcc that
> leads the function to have a roughly 32KB stack frame. This is a problem given
> that the function is called recursively. In non-optimized builds, the stack
> frame is much smaller, hence one gets crashes that happen only in optimized
> builds.
>
> Arguably there is a compiler bug or at least severe misfeature here. In any
> case, the easy thing to do for now seems to be moving the bulk of the
> non-recursive code into a separate function. This is sufficient to convince my
> version of gcc not to blow up the stack frame of the recursive part. Just to 
> be
> sure, add the gcc-specific noinline attribute to prevent this bug from
> reoccuring if inliner heuristics change.
>
> Cc: "11.1 11.2" 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95133
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95026
> ---
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 24 
>  1 file changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index ad818a8..958b2c0 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -450,6 +450,12 @@ public:
> virtual void visit(ir_barrier *);
> /*@}*/
>
> +   void visit_expression(ir_expression *, st_src_reg *)
> +#if defined(__GNUC__)
> +  __attribute__((noinline))
> +#endif

As mentioned on IRC, there's something of a precedent for sticking
these things into src/util/macros.h and
src/gallium/include/pipe/p_compiler.h (although the src one appears
more appropriate. There's even a

src/mapi/glapi/gen/gl_XML.py:#define NOINLINE __attribute__((noinline))

However you choose to resolve this,

Reviewed-by: Ilia Mirkin 

> +  ;
> +
> void visit_atomic_counter_intrinsic(ir_call *);
> void visit_ssbo_intrinsic(ir_call *);
> void visit_membar_intrinsic(ir_call *);
> @@ -1535,10 +1541,7 @@ glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction 
> *ir,
>  void
>  glsl_to_tgsi_visitor::visit(ir_expression *ir)
>  {
> -   unsigned int operand;
> st_src_reg op[ARRAY_SIZE(ir->operands)];
> -   st_src_reg result_src;
> -   st_dst_reg result_dst;
>
> /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
>  */
> @@ -1561,7 +1564,7 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
> if (ir->operation == ir_quadop_vector)
>assert(!"ir_quadop_vector should have been lowered");
>
> -   for (operand = 0; operand < ir->get_num_operands(); operand++) {
> +   for (unsigned int operand = 0; operand < ir->get_num_operands(); 
> operand++) {
>this->result.file = PROGRAM_UNDEFINED;
>ir->operands[operand]->accept(this);
>if (this->result.file == PROGRAM_UNDEFINED) {
> @@ -1578,6 +1581,19 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
>assert(!ir->operands[operand]->type->is_matrix());
> }
>
> +   visit_expression(ir, op);
> +}
> +
> +/* The non-recursive part of the expression visitor lives in a separate
> + * function and should be prevented from being inlined, to avoid a stack
> + * explosion when deeply nested expressions are visited.
> + */
> +void
> +glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
> +{
> +   st_src_reg result_src;
> +   st_dst_reg result_dst;
> +
> int vector_elements = ir->operands[0]->type->vector_elements;
> if (ir->operands[1]) {
>vector_elements = MAX2(vector_elements,
> --
> 2.5.0
>
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[Mesa-dev] [PATCH] gallium/radeon: fix crash in r600_set_streamout_targets

[Nicolai Hähnle]

From: Nicolai Hähnle 

Protect against dereferencing a gap in the targets array. This was triggered
by a test in the Khronos CTS.

Cc: "11.1 11.2" 
---
 src/gallium/drivers/r600/r600_state_common.c |  3 ++-
 src/gallium/drivers/radeon/r600_streamout.c  | 13 +++--
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_state_common.c 
b/src/gallium/drivers/r600/r600_state_common.c
index 5317de0..cac240e 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -2802,7 +2802,8 @@ static void r600_invalidate_buffer(struct pipe_context 
*ctx, struct pipe_resourc
}
/* Streamout buffers. */
for (i = 0; i < rctx->b.streamout.num_targets; i++) {
-   if (rctx->b.streamout.targets[i]->b.buffer == >b.b) {
+   if (rctx->b.streamout.targets[i] &&
+   rctx->b.streamout.targets[i]->b.buffer == >b.b) {
if (rctx->b.streamout.begin_emitted) {
r600_emit_streamout_end(>b);
}
diff --git a/src/gallium/drivers/radeon/r600_streamout.c 
b/src/gallium/drivers/radeon/r600_streamout.c
index fc9ec48..a001700 100644
--- a/src/gallium/drivers/radeon/r600_streamout.c
+++ b/src/gallium/drivers/radeon/r600_streamout.c
@@ -116,7 +116,7 @@ void r600_set_streamout_targets(struct pipe_context *ctx,
 {
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
unsigned i;
-unsigned append_bitmask = 0;
+unsigned enabled_mask = 0, append_bitmask = 0;
 
/* Stop streamout. */
if (rctx->streamout.num_targets && rctx->streamout.begin_emitted) {
@@ -126,18 +126,19 @@ void r600_set_streamout_targets(struct pipe_context *ctx,
/* Set the new targets. */
for (i = 0; i < num_targets; i++) {
pipe_so_target_reference((struct 
pipe_stream_output_target**)>streamout.targets[i], targets[i]);
+   if (!targets[i])
+   continue;
+
r600_context_add_resource_size(ctx, targets[i]->buffer);
+   enabled_mask |= 1 << i;
if (offsets[i] == ((unsigned)-1))
-   append_bitmask |=  1 << i;
+   append_bitmask |= 1 << i;
}
for (; i < rctx->streamout.num_targets; i++) {
pipe_so_target_reference((struct 
pipe_stream_output_target**)>streamout.targets[i], NULL);
}
 
-   rctx->streamout.enabled_mask = (num_targets >= 1 && targets[0] ? 1 : 0) 
|
-  (num_targets >= 2 && targets[1] ? 2 : 0) 
|
-  (num_targets >= 3 && targets[2] ? 4 : 0) 
|
-  (num_targets >= 4 && targets[3] ? 8 : 0);
+   rctx->streamout.enabled_mask = enabled_mask;
 
rctx->streamout.num_targets = num_targets;
rctx->streamout.append_bitmask = append_bitmask;
-- 
2.5.0

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Re: [Mesa-dev] [PATCH 6/6] tgsi/text: fix parsing of memory instructions

[Dave Airlie]

On 29 April 2016 at 08:56, Ilia Mirkin  wrote:
> Patches 3-6 are Reviewed-by: Ilia Mirkin 

All 6 are Reviewed-by: Dave Airlie 
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[Mesa-dev] [PATCH 1/9] nir/lower_outputs_to_temporaries: fixup for new foreach_block()

[Jason Ekstrand]

From: Connor Abbott 

Reviewed-by: Jason Ekstrand 
---
 .../nir/nir_lower_outputs_to_temporaries.c | 28 ++
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/src/compiler/nir/nir_lower_outputs_to_temporaries.c 
b/src/compiler/nir/nir_lower_outputs_to_temporaries.c
index d5a0737..21bc15b 100644
--- a/src/compiler/nir/nir_lower_outputs_to_temporaries.c
+++ b/src/compiler/nir/nir_lower_outputs_to_temporaries.c
@@ -58,21 +58,6 @@ emit_output_copies(nir_cursor cursor, struct 
lower_outputs_state *state)
}
 }
 
-static bool
-emit_output_copies_block(nir_block *block, void *state)
-{
-   nir_foreach_instr(instr, block) {
-  if (instr->type != nir_instr_type_intrinsic)
- continue;
-
-  nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
-  if (intrin->intrinsic == nir_intrinsic_emit_vertex)
- emit_output_copies(nir_before_instr(>instr), state);
-   }
-
-   return true;
-}
-
 void
 nir_lower_outputs_to_temporaries(nir_shader *shader, nir_function *entrypoint)
 {
@@ -116,7 +101,18 @@ nir_lower_outputs_to_temporaries(nir_shader *shader, 
nir_function *entrypoint)
  /* For geometry shaders, we have to emit the output copies right
   * before each EmitVertex call.
   */
- nir_foreach_block_call(function->impl, emit_output_copies_block, 
);
+ nir_foreach_block(block, function->impl) {
+nir_foreach_instr(instr, block) {
+   if (instr->type != nir_instr_type_intrinsic)
+  continue;
+
+   nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
+   if (intrin->intrinsic == nir_intrinsic_emit_vertex) {
+  emit_output_copies(nir_before_instr(>instr),
+ );
+   }
+}
+ }
   } else if (function == entrypoint) {
  /* For all other shader types, we need to do the copies right before
   * the jumps to the end block.
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 8/9] vc4: fixup for new nir_foreach_block()

[Jason Ekstrand]

From: Connor Abbott 

---
 src/gallium/drivers/vc4/vc4_nir_lower_blend.c  |  9 -
 src/gallium/drivers/vc4/vc4_nir_lower_io.c | 20 +---
 src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c | 24 +++-
 src/gallium/drivers/vc4/vc4_program.c  | 15 ---
 4 files changed, 20 insertions(+), 48 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_nir_lower_blend.c 
b/src/gallium/drivers/vc4/vc4_nir_lower_blend.c
index c616122..8cad4b7 100644
--- a/src/gallium/drivers/vc4/vc4_nir_lower_blend.c
+++ b/src/gallium/drivers/vc4/vc4_nir_lower_blend.c
@@ -674,10 +674,8 @@ vc4_nir_lower_blend_instr(struct vc4_compile *c, 
nir_builder *b,
 }
 
 static bool
-vc4_nir_lower_blend_block(nir_block *block, void *state)
+vc4_nir_lower_blend_block(nir_block *block, struct vc4_compile *c)
 {
-struct vc4_compile *c = state;
-
 nir_foreach_instr_safe(instr, block) {
 if (instr->type != nir_instr_type_intrinsic)
 continue;
@@ -714,8 +712,9 @@ vc4_nir_lower_blend(nir_shader *s, struct vc4_compile *c)
 {
 nir_foreach_function(function, s) {
 if (function->impl) {
-nir_foreach_block_call(function->impl,
-  vc4_nir_lower_blend_block, c);
+nir_foreach_block(block, function->impl) {
+vc4_nir_lower_blend_block(block, c);
+}
 
 nir_metadata_preserve(function->impl,
   nir_metadata_block_index |
diff --git a/src/gallium/drivers/vc4/vc4_nir_lower_io.c 
b/src/gallium/drivers/vc4/vc4_nir_lower_io.c
index 3598268..261c00d 100644
--- a/src/gallium/drivers/vc4/vc4_nir_lower_io.c
+++ b/src/gallium/drivers/vc4/vc4_nir_lower_io.c
@@ -428,25 +428,15 @@ vc4_nir_lower_io_instr(struct vc4_compile *c, nir_builder 
*b,
 }
 
 static bool
-vc4_nir_lower_io_block(nir_block *block, void *arg)
+vc4_nir_lower_io_impl(struct vc4_compile *c, nir_function_impl *impl)
 {
-struct vc4_compile *c = arg;
-nir_function_impl *impl =
-nir_cf_node_get_function(>cf_node);
-
 nir_builder b;
 nir_builder_init(, impl);
 
-nir_foreach_instr_safe(instr, block)
-vc4_nir_lower_io_instr(c, , instr);
-
-return true;
-}
-
-static bool
-vc4_nir_lower_io_impl(struct vc4_compile *c, nir_function_impl *impl)
-{
-nir_foreach_block_call(impl, vc4_nir_lower_io_block, c);
+nir_foreach_block(block, impl) {
+nir_foreach_instr_safe(instr, block)
+vc4_nir_lower_io_instr(c, , instr);
+}
 
 nir_metadata_preserve(impl, nir_metadata_block_index |
   nir_metadata_dominance);
diff --git a/src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c 
b/src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c
index 958a06a..1085243 100644
--- a/src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c
+++ b/src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c
@@ -130,30 +130,20 @@ vc4_nir_lower_txf_ms_instr(struct vc4_compile *c, 
nir_builder *b,
 }
 
 static bool
-vc4_nir_lower_txf_ms_block(nir_block *block, void *arg)
+vc4_nir_lower_txf_ms_impl(struct vc4_compile *c, nir_function_impl *impl)
 {
-struct vc4_compile *c = arg;
-nir_function_impl *impl =
-nir_cf_node_get_function(>cf_node);
-
 nir_builder b;
 nir_builder_init(, impl);
 
-nir_foreach_instr_safe(instr, block) {
-if (instr->type == nir_instr_type_tex) {
-vc4_nir_lower_txf_ms_instr(c, ,
-   nir_instr_as_tex(instr));
+nir_foreach_block(block, impl) {
+nir_foreach_instr_safe(instr, block) {
+if (instr->type == nir_instr_type_tex) {
+vc4_nir_lower_txf_ms_instr(c, ,
+nir_instr_as_tex(instr));
+}
 }
 }
 
-return true;
-}
-
-static bool
-vc4_nir_lower_txf_ms_impl(struct vc4_compile *c, nir_function_impl *impl)
-{
-nir_foreach_block_call(impl, vc4_nir_lower_txf_ms_block, c);
-
 nir_metadata_preserve(impl,
   nir_metadata_block_index |
   nir_metadata_dominance);
diff --git a/src/gallium/drivers/vc4/vc4_program.c 
b/src/gallium/drivers/vc4/vc4_program.c
index b1c8b00..44ea08c 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -1777,16 +1777,6 @@ static const nir_shader_compiler_options nir_options = {
 .lower_negate = true,
 };
 
-static bool
-count_nir_instrs_in_block(nir_block *block, void *state)
-{
-int *count = (int *) state;
-nir_foreach_instr(instr, block) {
-

[Mesa-dev] [PATCH 4/9] nir/gather_info: fixup for new foreach_block()

[Jason Ekstrand]

Signed-off-by: Jason Ekstrand 
---
 src/compiler/nir/nir_gather_info.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/compiler/nir/nir_gather_info.c 
b/src/compiler/nir/nir_gather_info.c
index 180cecc..d45b1a2 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -68,8 +68,8 @@ gather_tex_info(nir_tex_instr *instr, nir_shader *shader)
   shader->info.uses_texture_gather = true;
 }
 
-static bool
-gather_info_block(nir_block *block, void *shader)
+static void
+gather_info_block(nir_block *block, nir_shader *shader)
 {
nir_foreach_instr(instr, block) {
   switch (instr->type) {
@@ -86,8 +86,6 @@ gather_info_block(nir_block *block, void *shader)
  break;
   }
}
-
-   return true;
 }
 
 /**
@@ -157,5 +155,7 @@ nir_shader_gather_info(nir_shader *shader, 
nir_function_impl *entrypoint)
   }
}
 
-   nir_foreach_block_call(entrypoint, gather_info_block, shader);
+   nir_foreach_block(block, entrypoint) {
+  gather_info_block(block, shader);
+   }
 }
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 7/9] ir3: fixup for new nir_foreach_block()

[Jason Ekstrand]

From: Connor Abbott 

---
 .../drivers/freedreno/ir3/ir3_nir_lower_if_else.c  | 51 +-
 1 file changed, 21 insertions(+), 30 deletions(-)

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir_lower_if_else.c 
b/src/gallium/drivers/freedreno/ir3/ir3_nir_lower_if_else.c
index 12f7ccf..262f490 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_nir_lower_if_else.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_nir_lower_if_else.c
@@ -58,12 +58,6 @@
  *then we should prefer to not flatten the if/else..
  */
 
-struct lower_state {
-   nir_builder b;
-   void *mem_ctx;
-   bool progress;
-};
-
 static bool
 valid_dest(nir_block *block, nir_dest *dest)
 {
@@ -213,23 +207,21 @@ flatten_block(nir_builder *bld, nir_block *if_block, 
nir_block *prev_block,
 }
 
 static bool
-lower_if_else_block(nir_block *block, void *void_state)
+lower_if_else_block(nir_block *block, nir_builder *b, void *mem_ctx)
 {
-   struct lower_state *state = void_state;
-
/* If the block is empty, then it certainly doesn't have any phi nodes,
 * so we can skip it.  This also ensures that we do an early skip on the
 * end block of the function which isn't actually attached to the CFG.
 */
if (exec_list_is_empty(>instr_list))
-   return true;
+   return false;
 
if (nir_cf_node_is_first(>cf_node))
-   return true;
+   return false;
 
nir_cf_node *prev_node = nir_cf_node_prev(>cf_node);
if (prev_node->type != nir_cf_node_if)
-   return true;
+   return false;
 
nir_if *if_stmt = nir_cf_node_as_if(prev_node);
nir_cf_node *then_node = nir_if_first_then_node(if_stmt);
@@ -238,7 +230,7 @@ lower_if_else_block(nir_block *block, void *void_state)
/* We can only have one block in each side ... */
if (nir_if_last_then_node(if_stmt) != then_node ||
nir_if_last_else_node(if_stmt) != else_node)
-   return true;
+   return false;
 
nir_block *then_block = nir_cf_node_as_block(then_node);
nir_block *else_block = nir_cf_node_as_block(else_node);
@@ -246,11 +238,11 @@ lower_if_else_block(nir_block *block, void *void_state)
/* ... and those blocks must only contain "allowed" instructions. */
if (!block_check_for_allowed_instrs(then_block) ||
!block_check_for_allowed_instrs(else_block))
-   return true;
+   return false;
 
/* condition should be ssa too, which simplifies flatten_block: */
if (!if_stmt->condition.is_ssa)
-   return true;
+   return false;
 
/* At this point, we know that the previous CFG node is an if-then
 * statement containing only moves to phi nodes in this block.  We can
@@ -265,9 +257,9 @@ lower_if_else_block(nir_block *block, void *void_state)
 * block before.  There are a few things that need handling specially
 * like discard/discard_if.
 */
-   flatten_block(>b, then_block, prev_block,
+   flatten_block(b, then_block, prev_block,
if_stmt->condition.ssa, false);
-   flatten_block(>b, else_block, prev_block,
+   flatten_block(b, else_block, prev_block,
if_stmt->condition.ssa, true);
 
nir_foreach_instr_safe(instr, block) {
@@ -275,8 +267,8 @@ lower_if_else_block(nir_block *block, void *void_state)
break;
 
nir_phi_instr *phi = nir_instr_as_phi(instr);
-   nir_alu_instr *sel = nir_alu_instr_create(state->mem_ctx, 
nir_op_bcsel);
-   nir_src_copy(>src[0].src, _stmt->condition, 
state->mem_ctx);
+   nir_alu_instr *sel = nir_alu_instr_create(mem_ctx, 
nir_op_bcsel);
+   nir_src_copy(>src[0].src, _stmt->condition, mem_ctx);
/* Splat the condition to all channels */
memset(sel->src[0].swizzle, 0, sizeof sel->src[0].swizzle);
 
@@ -286,7 +278,7 @@ lower_if_else_block(nir_block *block, void *void_state)
assert(src->src.is_ssa);
 
unsigned idx = src->pred == then_block ? 1 : 2;
-   nir_src_copy(>src[idx].src, >src, 
state->mem_ctx);
+   nir_src_copy(>src[idx].src, >src, mem_ctx);
}
 
nir_ssa_dest_init(>instr, >dest.dest,
@@ -301,26 +293,25 @@ lower_if_else_block(nir_block *block, void *void_state)
}
 
nir_cf_node_remove(_stmt->cf_node);
-   state->progress = true;
-
return true;
 }
 
 static bool
 lower_if_else_impl(nir_function_impl *impl)
 {
-   struct lower_state state;
-
-   state.mem_ctx = ralloc_parent(impl);
-   state.progress = false;
-   nir_builder_init(, impl);
+   void *mem_ctx = ralloc_parent(impl);
+   nir_builder b;
+   nir_builder_init(, impl);

[Mesa-dev] [PATCH 3/9] nir/lower_two_sided_color: fixup for new foreach_block()

[Jason Ekstrand]

From: Connor Abbott 

Reviewed-by: Jason Ekstrand 
---
 src/compiler/nir/nir_lower_two_sided_color.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/compiler/nir/nir_lower_two_sided_color.c 
b/src/compiler/nir/nir_lower_two_sided_color.c
index ea432c1..5d8779e 100644
--- a/src/compiler/nir/nir_lower_two_sided_color.c
+++ b/src/compiler/nir/nir_lower_two_sided_color.c
@@ -133,9 +133,9 @@ setup_inputs(lower_2side_state *state)
 }
 
 static bool
-nir_lower_two_sided_color_block(nir_block *block, void *void_state)
+nir_lower_two_sided_color_block(nir_block *block,
+lower_2side_state *state)
 {
-   lower_2side_state *state = void_state;
nir_builder *b = >b;
 
nir_foreach_instr_safe(instr, block) {
@@ -185,7 +185,9 @@ nir_lower_two_sided_color_impl(nir_function_impl *impl,
 
nir_builder_init(b, impl);
 
-   nir_foreach_block_call(impl, nir_lower_two_sided_color_block, state);
+   nir_foreach_block(block, impl) {
+  nir_lower_two_sided_color_block(block, state);
+   }
 
nir_metadata_preserve(impl, nir_metadata_block_index |
nir_metadata_dominance);
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 5/9] nir/lower_double_pack: fixup for new nir_foreach_block()

[Jason Ekstrand]

Signed-off-by: Jason Ekstrand 
---
 src/compiler/nir/nir_lower_double_packing.c | 47 +
 1 file changed, 21 insertions(+), 26 deletions(-)

diff --git a/src/compiler/nir/nir_lower_double_packing.c 
b/src/compiler/nir/nir_lower_double_packing.c
index 22092a2..046e213 100644
--- a/src/compiler/nir/nir_lower_double_packing.c
+++ b/src/compiler/nir/nir_lower_double_packing.c
@@ -46,44 +46,39 @@ lower_unpack_double(nir_builder *b, nir_ssa_def *src)
   nir_unpack_double_2x32_split_y(b, src));
 }
 
-static bool
-lower_double_pack_block(nir_block *block, void *ctx)
+static void
+lower_double_pack_impl(nir_function_impl *impl)
 {
-   nir_builder *b = (nir_builder *) ctx;
+   nir_builder b;
+   nir_builder_init(, impl);
 
-   nir_foreach_instr_safe(instr, block) {
-  if (instr->type != nir_instr_type_alu)
- continue;
+   nir_foreach_block(block, impl) {
+  nir_foreach_instr_safe(instr, block) {
+ if (instr->type != nir_instr_type_alu)
+continue;
 
-  nir_alu_instr *alu_instr = (nir_alu_instr *) instr;
+ nir_alu_instr *alu_instr = (nir_alu_instr *) instr;
 
-  if (alu_instr->op != nir_op_pack_double_2x32 &&
-  alu_instr->op != nir_op_unpack_double_2x32)
- continue;
+ if (alu_instr->op != nir_op_pack_double_2x32 &&
+ alu_instr->op != nir_op_unpack_double_2x32)
+continue;
 
-  b->cursor = nir_before_instr(_instr->instr);
+ b.cursor = nir_before_instr(_instr->instr);
 
-  nir_ssa_def *src = nir_ssa_for_alu_src(b, alu_instr, 0);
-  nir_ssa_def *dest =
- alu_instr->op == nir_op_pack_double_2x32 ?
- lower_pack_double(b, src) :
- lower_unpack_double(b, src);
+ nir_ssa_def *src = nir_ssa_for_alu_src(, alu_instr, 0);
+ nir_ssa_def *dest =
+alu_instr->op == nir_op_pack_double_2x32 ?
+lower_pack_double(, src) :
+lower_unpack_double(, src);
 
-  nir_ssa_def_rewrite_uses(_instr->dest.dest.ssa, 
nir_src_for_ssa(dest));
-  nir_instr_remove(_instr->instr);
+ nir_ssa_def_rewrite_uses(_instr->dest.dest.ssa, 
nir_src_for_ssa(dest));
+ nir_instr_remove(_instr->instr);
+  }
}
 
return true;
 }
 
-static void
-lower_double_pack_impl(nir_function_impl *impl)
-{
-   nir_builder b;
-   nir_builder_init(, impl);
-   nir_foreach_block_call(impl, lower_double_pack_block, );
-}
-
 void
 nir_lower_double_pack(nir_shader *shader)
 {
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 2/9] nir/lower_tex: fixup for new foreach_block()

[Jason Ekstrand]

From: Connor Abbott 

Reviewed-by: Jason Ekstrand 
---
 src/compiler/nir/nir_lower_tex.c | 47 +++-
 1 file changed, 22 insertions(+), 25 deletions(-)

diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c
index d75e455..a080475 100644
--- a/src/compiler/nir/nir_lower_tex.c
+++ b/src/compiler/nir/nir_lower_tex.c
@@ -38,12 +38,6 @@
 #include "nir.h"
 #include "nir_builder.h"
 
-typedef struct {
-   nir_builder b;
-   const nir_lower_tex_options *options;
-   bool progress;
-} lower_tex_state;
-
 static void
 project_src(nir_builder *b, nir_tex_instr *tex)
 {
@@ -315,11 +309,10 @@ linearize_srgb_result(nir_builder *b, nir_tex_instr *tex)
 }
 
 static bool
-nir_lower_tex_block(nir_block *block, void *void_state)
+nir_lower_tex_block(nir_block *block, nir_builder *b,
+const nir_lower_tex_options *options)
 {
-   lower_tex_state *state = void_state;
-   const nir_lower_tex_options *options = state->options;
-   nir_builder *b = >b;
+   bool progress = false;
 
nir_foreach_instr_safe(instr, block) {
   if (instr->type != nir_instr_type_tex)
@@ -343,59 +336,63 @@ nir_lower_tex_block(nir_block *block, void *void_state)
*/
   if (lower_txp || sat_mask) {
  project_src(b, tex);
- state->progress = true;
+ progress = true;
   }
 
   if ((tex->sampler_dim == GLSL_SAMPLER_DIM_RECT) && options->lower_rect) {
  lower_rect(b, tex);
- state->progress = true;
+ progress = true;
   }
 
   if (sat_mask) {
  saturate_src(b, tex, sat_mask);
- state->progress = true;
+ progress = true;
   }
 
   if (((1 << tex->texture_index) & options->swizzle_result) &&
   !nir_tex_instr_is_query(tex) &&
   !(tex->is_shadow && tex->is_new_style_shadow)) {
  swizzle_result(b, tex, options->swizzles[tex->texture_index]);
- state->progress = true;
+ progress = true;
   }
 
   /* should be after swizzle so we know which channels are rgb: */
   if (((1 << tex->texture_index) & options->lower_srgb) &&
   !nir_tex_instr_is_query(tex) && !tex->is_shadow) {
  linearize_srgb_result(b, tex);
- state->progress = true;
+ progress = true;
   }
}
 
-   return true;
+   return progress;
 }
 
-static void
-nir_lower_tex_impl(nir_function_impl *impl, lower_tex_state *state)
+static bool
+nir_lower_tex_impl(nir_function_impl *impl,
+   const nir_lower_tex_options *options)
 {
-   nir_builder_init(>b, impl);
+   bool progress = false;
+   nir_builder builder;
+   nir_builder_init(, impl);
 
-   nir_foreach_block_call(impl, nir_lower_tex_block, state);
+   nir_foreach_block(block, impl) {
+  progress |= nir_lower_tex_block(block, , options);
+   }
 
nir_metadata_preserve(impl, nir_metadata_block_index |
nir_metadata_dominance);
+   return progress;
 }
 
 bool
 nir_lower_tex(nir_shader *shader, const nir_lower_tex_options *options)
 {
-   lower_tex_state state;
-   state.options = options;
-   state.progress = false;
+   bool progress = false;
 
nir_foreach_function(function, shader) {
   if (function->impl)
- nir_lower_tex_impl(function->impl, );
+ progress |= nir_lower_tex_impl(function->impl, options);
}
 
-   return state.progress;
+   return progress;
 }
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 9/9] nir: remove now-unused nir_foreach_block*_call()

[Jason Ekstrand]

From: Connor Abbott 

Reviewed-by: Jason Ekstrand 
---
 src/compiler/nir/nir.h | 38 --
 1 file changed, 38 deletions(-)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index f5f4144..c00124f 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2179,44 +2179,6 @@ nir_block *nir_cf_node_cf_tree_next(nir_cf_node *node);
 block != nir_cf_node_cf_tree_next(node); \
 block = nir_block_cf_tree_next(block))
 
-typedef bool (*nir_foreach_block_cb)(nir_block *block, void *state);
-
-static inline bool
-nir_foreach_block_call(nir_function_impl *impl, nir_foreach_block_cb cb,
-   void *state)
-{
-   nir_foreach_block_safe(block, impl) {
-  if (!cb(block, state))
- return false;
-   }
-
-   return true;
-}
-
-static inline bool
-nir_foreach_block_reverse_call(nir_function_impl *impl, nir_foreach_block_cb 
cb,
-   void *state)
-{
-   nir_foreach_block_reverse_safe(block, impl) {
-  if (!cb(block, state))
- return false;
-   }
-
-   return true;
-}
-
-static inline bool
-nir_foreach_block_in_cf_node_call(nir_cf_node *node, nir_foreach_block_cb cb,
-  void *state)
-{
-   nir_foreach_block_in_cf_node(block, node) {
-  if (!cb(block, state))
- return false;
-   }
-
-   return true;
-}
-
 /* If the following CF node is an if, this function returns that if.
  * Otherwise, it returns NULL.
  */
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 6/9] nir/lower_double_ops: fixup for new nir_foreach_block()

[Jason Ekstrand]

---
 src/compiler/nir/nir_lower_double_ops.c | 32 +---
 1 file changed, 9 insertions(+), 23 deletions(-)

diff --git a/src/compiler/nir/nir_lower_double_ops.c 
b/src/compiler/nir/nir_lower_double_ops.c
index e5cf094..33c20d2 100644
--- a/src/compiler/nir/nir_lower_double_ops.c
+++ b/src/compiler/nir/nir_lower_double_ops.c
@@ -533,32 +533,18 @@ lower_doubles_instr(nir_alu_instr *instr, 
nir_lower_doubles_options options)
nir_instr_remove(>instr);
 }
 
-static bool
-lower_doubles_block(nir_block *block, void *ctx)
-{
-   nir_lower_doubles_options options = *((nir_lower_doubles_options *) ctx);
-
-   nir_foreach_instr_safe(instr, block) {
-  if (instr->type != nir_instr_type_alu)
- continue;
-
-  lower_doubles_instr(nir_instr_as_alu(instr), options);
-   }
-
-   return true;
-}
-
-static void
-lower_doubles_impl(nir_function_impl *impl, nir_lower_doubles_options options)
-{
-   nir_foreach_block_call(impl, lower_doubles_block, );
-}
-
 void
 nir_lower_doubles(nir_shader *shader, nir_lower_doubles_options options)
 {
nir_foreach_function(function, shader) {
-  if (function->impl)
- lower_doubles_impl(function->impl, options);
+  if (!function->impl)
+ continue;
+
+  nir_foreach_block(block, function->impl) {
+ nir_foreach_instr_safe(instr, block) {
+if (instr->type == nir_instr_type_alu)
+   lower_doubles_instr(nir_instr_as_alu(instr), options);
+ }
+  }
}
 }
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 0/9] nir: Finsh fixing up nir_foreach_block()

[Jason Ekstrand]

I've pushed most of Connor's nir_foreach_block() patches as well as the
patches to fix up the other foreach helpers.  This series contains patches
that are either from me and need review or interact with things that other
people are actively working on.

Connor Abbott (6):
  nir/lower_outputs_to_temporaries: fixup for new foreach_block()
  nir/lower_tex: fixup for new foreach_block()
  nir/lower_two_sided_color: fixup for new foreach_block()
  ir3: fixup for new nir_foreach_block()
  vc4: fixup for new nir_foreach_block()
  nir: remove now-unused nir_foreach_block*_call()

Jason Ekstrand (3):
  nir/gather_info: fixup for new foreach_block()
  nir/lower_double_pack: fixup for new nir_foreach_block()
  nir/lower_double_ops: fixup for new nir_foreach_block()

 src/compiler/nir/nir.h | 38 
 src/compiler/nir/nir_gather_info.c | 10 ++---
 src/compiler/nir/nir_lower_double_ops.c| 32 --
 src/compiler/nir/nir_lower_double_packing.c| 47 +---
 .../nir/nir_lower_outputs_to_temporaries.c | 28 +---
 src/compiler/nir/nir_lower_tex.c   | 47 ++--
 src/compiler/nir/nir_lower_two_sided_color.c   |  8 ++--
 .../drivers/freedreno/ir3/ir3_nir_lower_if_else.c  | 51 +-
 src/gallium/drivers/vc4/vc4_nir_lower_blend.c  |  9 ++--
 src/gallium/drivers/vc4/vc4_nir_lower_io.c | 20 +++--
 src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c | 24 +++---
 src/gallium/drivers/vc4/vc4_program.c  | 15 ++-
 12 files changed, 115 insertions(+), 214 deletions(-)

-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH v2 8/9] i965: Implement ARB_query_buffer_object for HSW+

[Kenneth Graunke]

On Wednesday, April 27, 2016 11:01:47 PM PDT Jordan Justen wrote:
> v2:
>  * Declare loop index variable at loop site (idr)
>  * Make arrays of MI_MATH instructions 'static const' (idr)
>  * Remove commented debug code (idr)
>  * Updated comment in set_query_availability (Ken)
>  * Replace switch with if/else in hsw_result_to_gpr0 (Ken)
>  * Only divide GL_FRAGMENT_SHADER_INVOCATIONS_ARB by 4 on
>hsw and gen8 (Ken)
> 
> Signed-off-by: Jordan Justen 
> Cc: Ian Romanick 
> Cc: Kristian Høgsberg 

Nice work!

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH] mesa: Fix indirect draw buffer size check on 32-bit systems.

[Mark Janes]

Reviewed-by: Mark Janes 

Kenneth Graunke  writes:

> Fixes dEQP-GLES31.functional subtests:
> draw_indirect.negative.command_offset_not_in_buffer_signed32_wrap
> draw_indirect.negative.command_offset_not_in_buffer_unsigned32_wrap
>
> These tests use really large values that overflow GLsizeiptr, at
> which point the buffer size isn't less than "end".
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95138
> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/main/api_validate.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c
> index 2b62997..688408f 100644
> --- a/src/mesa/main/api_validate.c
> +++ b/src/mesa/main/api_validate.c
> @@ -696,7 +696,7 @@ valid_draw_indirect(struct gl_context *ctx,
>  GLenum mode, const GLvoid *indirect,
>  GLsizei size, const char *name)
>  {
> -   const GLsizeiptr end = (GLsizeiptr)indirect + size;
> +   const uint64_t end = (uint64_t) (uintptr_t) indirect + size;
>  
> /* OpenGL ES 3.1 spec. section 10.5:
>  *
> -- 
> 2.8.0
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Re: [Mesa-dev] [PATCH 5/5] i965: Write a scalar TCS backend that runs in SINGLE_PATCH mode.

[Jordan Justen]

On 2016-04-21 22:32:09, Kenneth Graunke wrote:
> Unlike most shader stages, the Hull Shader hardware makes us explicitly
> tell it how many threads to dispatch and manually configure the channel
> mask.  One perk of this is that we have a lot of flexibility - we can
> run it in either SIMD4x2 or SIMD8 mode.
> 
> Treating it as SIMD8 means that shaders with 8 or fewer output vertices
> (which is overwhemingly the common case) can be handled by a single
> thread.  This has several intriguing properties:
> 
> - Accessing input arrays with gl_InvocationID as the index is a simple
>   SIMD8 URB read with g1 as the header.  No indirect addressing required.
> - Barriers are no-ops.
> - We could potentially do output shadowing to combine writes, as the
>   concurrency concerns are gone.  (We don't do this yet, though.)
> 
> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/brw_compiler.c |   4 +-
>  src/mesa/drivers/dri/i965/brw_fs.cpp |  97 
>  src/mesa/drivers/dri/i965/brw_fs.h   |   5 +
>  src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 356 
> +++
>  src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |   3 +
>  src/mesa/drivers/dri/i965/brw_tcs.c  |   3 +-
>  src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp   |  59 -
>  7 files changed, 512 insertions(+), 15 deletions(-)
> 
> Shockingly, this appears to cut instruction counts in Unigine Heaven
> (-2.5 to 5.5%), Synmark (-31%), and Tessmark (-37%).  It increases
> instruction counts in Shadow of Mordor (up to +57%) - but again, this
> is running in scalar mode, so larger instruction counts are expected :)
> I also have a bunch of optimizations in progress that will help those.
> 
> Cycle counts look pretty good too.
> 
> This patch leaves it off by default because I haven't properly benchmarked
> it yet.  I fully expect we'll turn it on by default.
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c 
> b/src/mesa/drivers/dri/i965/brw_compiler.c
> index 4496699..93a30a5 100644
> --- a/src/mesa/drivers/dri/i965/brw_compiler.c
> +++ b/src/mesa/drivers/dri/i965/brw_compiler.c
> @@ -152,7 +152,8 @@ brw_compiler_create(void *mem_ctx, const struct 
> brw_device_info *devinfo)
>  
> compiler->scalar_stage[MESA_SHADER_VERTEX] =
>devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
> -   compiler->scalar_stage[MESA_SHADER_TESS_CTRL] = false;
> +   compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
> +  devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", false);
> compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
>devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
> compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
> @@ -194,6 +195,7 @@ brw_compiler_create(void *mem_ctx, const struct 
> brw_device_info *devinfo)
>  
> 
> compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = 
> false;
> 
> compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = 
> false;
> +   
> compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = 
> false;
>  
> if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
>
> compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = 
> false;
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 5d6a107..be5edb8 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -1758,6 +1758,21 @@ fs_visitor::assign_vs_urb_setup()
>  }
>  
>  void
> +fs_visitor::assign_tcs_single_patch_urb_setup()
> +{
> +   assert(stage == MESA_SHADER_TESS_CTRL);
> +
> +   brw_vue_prog_data *vue_prog_data = (brw_vue_prog_data *) prog_data;
> +
> +   first_non_payload_grf += 8 * vue_prog_data->urb_read_length;

We talked about this bit of code offline. This is just a reminder that
you were going to check to see if it is used currently.

Patches 3-5 Reviewed-by: Jordan Justen 

> +
> +   /* Rewrite all ATTR file references to HW_REGs. */
> +   foreach_block_and_inst(block, fs_inst, inst, cfg) {
> +  convert_attr_sources_to_hw_regs(inst);
> +   }
> +}
> +
> +void
>  fs_visitor::assign_tes_urb_setup()
>  {
> assert(stage == MESA_SHADER_TESS_EVAL);
> @@ -5463,6 +5478,88 @@ fs_visitor::run_vs(gl_clip_plane *clip_planes)
>  }
>  
>  bool
> +fs_visitor::run_tcs_single_patch()
> +{
> +   assert(stage == MESA_SHADER_TESS_CTRL);
> +
> +   struct brw_tcs_prog_data *tcs_prog_data =
> +  (struct brw_tcs_prog_data *) prog_data;
> +
> +   /* r1-r4 contain the ICP handles. */
> +   payload.num_regs = 5;
> +
> +   if (shader_time_index >= 0)
> +  emit_shader_time_begin();
> +
> +   /* Initialize gl_InvocationID */
> +   fs_reg channels_uw = bld.vgrf(BRW_REGISTER_TYPE_UW);
> +   fs_reg channels_ud = bld.vgrf(BRW_REGISTER_TYPE_UD);
> +   bld.MOV(channels_uw, fs_reg(brw_imm_uv(0x76543210)));
> +   bld.MOV(channels_ud, 

Re: [Mesa-dev] [PATCH 1/2] i965/vec4: Lower integer multiplication after optimizations.

[Francisco Jerez]

Matt Turner  writes:

> On Mon, Apr 18, 2016 at 5:18 PM, Matt Turner  wrote:
>> On Mon, Apr 18, 2016 at 5:08 PM, Ian Romanick  wrote:
>>> On 04/18/2016 04:14 PM, Matt Turner wrote:
 Analogous to commit 1e4e17fbd in the i965/fs backend.

 Because the copy propagation pass in the vec4 backend is strictly local,
 we look at the immediate values coming from NIR and emit the multiplies
 we need directly. If the copy propagation pass becomes smarter in the
 future, we can reduce the nir_op_imul case in brw_vec4_nir.cpp to a
 single multiply.

 total instructions in shared programs: 7082311 -> 7081953 (-0.01%)
 instructions in affected programs: 59581 -> 59223 (-0.60%)
 helped: 293

 total cycles in shared programs: 65765712 -> 65764796 (-0.00%)
 cycles in affected programs: 854112 -> 853196 (-0.11%)
 helped: 154
 HURT: 73
 ---
  src/mesa/drivers/dri/i965/brw_vec4.cpp | 67 
 ++
  src/mesa/drivers/dri/i965/brw_vec4.h   |  1 +
  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 48 +
  3 files changed, 88 insertions(+), 28 deletions(-)

 diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
 b/src/mesa/drivers/dri/i965/brw_vec4.cpp
 index b9cf3f6..1644d4d 100644
 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
 +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
 @@ -1671,6 +1671,71 @@ vec4_visitor::lower_minmax()
 return progress;
  }

 +bool
 +vec4_visitor::lower_integer_multiplication()
 +{
 +   bool progress = false;
 +
 +   foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
 +  const vec4_builder ibld(this, block, inst);
 +
 +  if (inst->opcode == BRW_OPCODE_MUL) {
 + if (inst->dst.is_accumulator() ||
 + (inst->src[1].type != BRW_REGISTER_TYPE_D &&
 +  inst->src[1].type != BRW_REGISTER_TYPE_UD))
 +continue;
 +
 + /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
 +  * operation directly, but CHV/BXT cannot.
 +  */
 + if (devinfo->gen >= 8 &&
 + !devinfo->is_cherryview && !devinfo->is_broxton)
 +continue;
>>>
>>> Shouldn't this whole method just bail if we're Gen >= 8 and !CHV and
>>> !BXT?  Or does this structure simplify future changes?
>>
>> Oh, I hadn't noticed.
>>
>> The FS code was originally as you suggest, with the function returning
>> early under those conditions. Curro changed that in commit 2e731264382
>> in order to add lowering support for the multiply-high instruction on
>> all platforms. We may want to do that in the vec4 backend as well.
>>
>> The other thing I need to fix is Cherryview multiplications, where we
>> need to change the type of src1 to UW. I'm not sure if it's better to
>> do that here, or at a lower level. Maybe in brw_MUL itself since
>> that's called in a few places...
>>
>> Depending on whether people think that code should go here or
>> elsewhere, I'll move the block to the beginning of the function.
>
> Ken, Curro: any opinion where we should change src1's type to UW on CHV/BXT?

I guess it would make sense to change the types as soon as the multiply
by UD is lowered to multiplies by UW?  It may still make sense to assert
in the generator that the types coming in are supported by the hardware.


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Re: [Mesa-dev] [PATCH 6/6] tgsi/text: fix parsing of memory instructions

[Ilia Mirkin]

Patches 3-6 are Reviewed-by: Ilia Mirkin 

On Thu, Apr 28, 2016 at 6:50 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> Properly handle Target and Format parameters when present.
> ---
>  src/gallium/auxiliary/tgsi/tgsi_text.c | 40 
> +++---
>  1 file changed, 27 insertions(+), 13 deletions(-)
>
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c 
> b/src/gallium/auxiliary/tgsi/tgsi_text.c
> index a707a6f..14956df 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_text.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
> @@ -1134,23 +1134,37 @@ parse_instruction(
>
> cur = ctx->cur;
> eat_opt_white();
> -   for (i = 0; inst.Instruction.Memory && *cur == ','; i++) {
> -  uint j;
> +
> +   for (; inst.Instruction.Memory && *cur == ',';
> +ctx->cur = cur, eat_opt_white()) {
> +  int j;
> +
>cur++;
>eat_opt_white();
> -  ctx->cur = cur;
> -  for (j = 0; j < 3; j++) {
> - if (str_match_nocase_whole(>cur, tgsi_memory_names[j])) {
> -inst.Memory.Qualifier |= 1U << j;
> -break;
> - }
> +
> +  j = str_match_name_from_array(, tgsi_memory_names,
> +ARRAY_SIZE(tgsi_memory_names));
> +  if (j >= 0) {
> + inst.Memory.Qualifier |= 1U << j;
> + continue;
>}
> -  if (j == 3) {
> - report_error(ctx, "Expected memory qualifier");
> - return FALSE;
> +
> +  j = str_match_name_from_array(, tgsi_texture_names,
> +ARRAY_SIZE(tgsi_texture_names));
> +  if (j >= 0) {
> + inst.Memory.Texture = j;
> + continue;
>}
> -  cur = ctx->cur;
> -  eat_opt_white();
> +
> +  j = str_match_format();
> +  if (j >= 0) {
> + inst.Memory.Format = j;
> + continue;
> +  }
> +
> +  ctx->cur = cur;
> +  report_error(ctx, "Expected memory qualifier, texture target, or 
> format\n");
> +  return FALSE;
> }
>
> cur = ctx->cur;
> --
> 2.5.0
>
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Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: fix potential crash when allocating temporaries

[Nicolai Hähnle]

Reviewed-by: Nicolai Hähnle 

On 28.04.2016 14:09, Samuel Pitoiset wrote:

When index - t->temps_size is greater than 4096, allocating space for
temporaries on demand will miserably crash. This can happen when a game
uses a lot of temporaries like the recent released Tomb raider.

Signed-off-by: Samuel Pitoiset 
---
  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index ad818a8..7ba9856 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -5348,7 +5348,7 @@ dst_register(struct st_translate *t, gl_register_file 
file, unsigned index,
 case PROGRAM_TEMPORARY:
/* Allocate space for temporaries on demand. */
if (index >= t->temps_size) {
- const int inc = 4096;
+ const int inc = align(index - t->temps_size + 1, 4096);

   t->temps = (struct ureg_dst*)
  realloc(t->temps,


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[Mesa-dev] [PATCH 6/6] tgsi/text: fix parsing of memory instructions

[Nicolai Hähnle]

From: Nicolai Hähnle 

Properly handle Target and Format parameters when present.
---
 src/gallium/auxiliary/tgsi/tgsi_text.c | 40 +++---
 1 file changed, 27 insertions(+), 13 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c 
b/src/gallium/auxiliary/tgsi/tgsi_text.c
index a707a6f..14956df 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_text.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
@@ -1134,23 +1134,37 @@ parse_instruction(
 
cur = ctx->cur;
eat_opt_white();
-   for (i = 0; inst.Instruction.Memory && *cur == ','; i++) {
-  uint j;
+
+   for (; inst.Instruction.Memory && *cur == ',';
+ctx->cur = cur, eat_opt_white()) {
+  int j;
+
   cur++;
   eat_opt_white();
-  ctx->cur = cur;
-  for (j = 0; j < 3; j++) {
- if (str_match_nocase_whole(>cur, tgsi_memory_names[j])) {
-inst.Memory.Qualifier |= 1U << j;
-break;
- }
+
+  j = str_match_name_from_array(, tgsi_memory_names,
+ARRAY_SIZE(tgsi_memory_names));
+  if (j >= 0) {
+ inst.Memory.Qualifier |= 1U << j;
+ continue;
   }
-  if (j == 3) {
- report_error(ctx, "Expected memory qualifier");
- return FALSE;
+
+  j = str_match_name_from_array(, tgsi_texture_names,
+ARRAY_SIZE(tgsi_texture_names));
+  if (j >= 0) {
+ inst.Memory.Texture = j;
+ continue;
   }
-  cur = ctx->cur;
-  eat_opt_white();
+
+  j = str_match_format();
+  if (j >= 0) {
+ inst.Memory.Format = j;
+ continue;
+  }
+
+  ctx->cur = cur;
+  report_error(ctx, "Expected memory qualifier, texture target, or 
format\n");
+  return FALSE;
}
 
cur = ctx->cur;
-- 
2.5.0

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[Mesa-dev] [PATCH 5/6] tgsi/text: add str_match_name_from_array

[Nicolai Hähnle]

From: Nicolai Hähnle 

---
 src/gallium/auxiliary/tgsi/tgsi_text.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c 
b/src/gallium/auxiliary/tgsi/tgsi_text.c
index 8a6645f..a707a6f 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_text.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
@@ -119,6 +119,24 @@ static boolean str_match_nocase_whole( const char **pcur, 
const char *str )
return FALSE;
 }
 
+/* Return the array index that matches starting at *pcur, where the string at
+ * *pcur is terminated by a non-digit non-letter non-underscore.
+ * Returns -1 if no match is found.
+ *
+ * On success, the pointer to the first string is moved to the end of the read
+ * word.
+ */
+static int str_match_name_from_array(const char **pcur,
+ const char * const *array,
+ unsigned array_size)
+{
+   for (unsigned j = 0; j < array_size; ++j) {
+  if (str_match_nocase_whole(pcur, array[j]))
+ return j;
+   }
+   return -1;
+}
+
 /* Return the format corresponding to the name at *pcur.
  * Returns -1 if there is no format name.
  *
-- 
2.5.0

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[Mesa-dev] [PATCH 4/6] tgsi/text: add str_match_format helper function

[Nicolai Hähnle]

From: Nicolai Hähnle 

---
 src/gallium/auxiliary/tgsi/tgsi_text.c | 31 ++-
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c 
b/src/gallium/auxiliary/tgsi/tgsi_text.c
index 114e6e5..8a6645f 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_text.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
@@ -119,6 +119,24 @@ static boolean str_match_nocase_whole( const char **pcur, 
const char *str )
return FALSE;
 }
 
+/* Return the format corresponding to the name at *pcur.
+ * Returns -1 if there is no format name.
+ *
+ * On success, the pointer to the string is moved to the end of the read format
+ * name.
+ */
+static int str_match_format(const char **pcur)
+{
+   for (unsigned i = 0; i < PIPE_FORMAT_COUNT; i++) {
+  const struct util_format_description *desc =
+ util_format_description(i);
+  if (desc && str_match_nocase_whole(pcur, desc->name)) {
+ return i;
+  }
+   }
+   return -1;
+}
+
 /* Eat zero or more whitespaces.
  */
 static void eat_opt_white( const char **pcur )
@@ -1302,16 +1320,11 @@ static boolean parse_declaration( struct translate_ctx 
*ctx )
decl.Image.Writable = 1;
 
 } else {
-   for (i = 0; i < PIPE_FORMAT_COUNT; i++) {
-  const struct util_format_description *desc =
- util_format_description(i);
-  if (desc && str_match_nocase_whole(, desc->name)) {
- decl.Image.Format = i;
- break;
-  }
-   }
-   if (i == PIPE_FORMAT_COUNT)
+   int format = str_match_format();
+   if (format < 0)
   break;
+
+   decl.Image.Format = format;
 }
 cur = cur2;
 eat_opt_white();
-- 
2.5.0

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[Mesa-dev] [PATCH 3/6] tgsi/build: pass Memory.Texture and .Format through tgsi_build_full_instruction

[Nicolai Hähnle]

From: Nicolai Hähnle 

---
 src/gallium/auxiliary/tgsi/tgsi_build.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.c 
b/src/gallium/auxiliary/tgsi/tgsi_build.c
index 7e30bb6..d525c8f 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_build.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_build.c
@@ -791,6 +791,8 @@ tgsi_default_instruction_memory( void )
 static struct tgsi_instruction_memory
 tgsi_build_instruction_memory(
unsigned qualifier,
+   unsigned texture,
+   unsigned format,
struct tgsi_token *prev_token,
struct tgsi_instruction *instruction,
struct tgsi_header *header )
@@ -798,8 +800,8 @@ tgsi_build_instruction_memory(
struct tgsi_instruction_memory instruction_memory;
 
instruction_memory.Qualifier = qualifier;
-   instruction_memory.Texture = 0;
-   instruction_memory.Format = 0;
+   instruction_memory.Texture = texture;
+   instruction_memory.Format = format;
instruction_memory.Padding = 0;
instruction->Memory = 1;
 
@@ -1177,6 +1179,8 @@ tgsi_build_full_instruction(
 
   *instruction_memory = tgsi_build_instruction_memory(
  full_inst->Memory.Qualifier,
+ full_inst->Memory.Texture,
+ full_inst->Memory.Format,
  prev_token,
  instruction,
  header );
-- 
2.5.0

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[Mesa-dev] [PATCH 2/6] tgsi/dump: signal nospace when the last print exceeded the size

[Nicolai Hähnle]

From: Nicolai Hähnle 

Previously, there was a bug where nospace wasn't signalled if it just so
happened that the very last print exceeded the available space.
---
 src/gallium/auxiliary/tgsi/tgsi_dump.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_dump.c 
b/src/gallium/auxiliary/tgsi/tgsi_dump.c
index 9482644..473fed1 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_dump.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_dump.c
@@ -753,7 +753,7 @@ str_dump_ctx_printf(struct dump_ctx *ctx, const char 
*format, ...)
 {
struct str_dump_ctx *sctx = (struct str_dump_ctx *)ctx;

-   if(sctx->left > 1) {
+   if (!sctx->nospace) {
   int written;
   va_list ap;
   va_start(ap, format);
@@ -764,12 +764,14 @@ str_dump_ctx_printf(struct dump_ctx *ctx, const char 
*format, ...)
* vsnprintf:
*/
   if (written > 0) {
- written = MIN2(sctx->left, written);
+ if (written >= sctx->left) {
+sctx->nospace = true;
+written = sctx->left;
+ }
  sctx->ptr += written;
  sctx->left -= written;
   }
-   } else
-  sctx->nospace = true;
+   }
 }
 
 bool
-- 
2.5.0

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[Mesa-dev] [PATCH 1/6] tgsi/dump: shared dump_ctx initialization

[Nicolai Hähnle]

From: Nicolai Hähnle 

---
 src/gallium/auxiliary/tgsi/tgsi_dump.c | 48 --
 1 file changed, 17 insertions(+), 31 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_dump.c 
b/src/gallium/auxiliary/tgsi/tgsi_dump.c
index f57f2bb..9482644 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_dump.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_dump.c
@@ -705,30 +705,31 @@ prolog(
return TRUE;
 }
 
+static void
+init_dump_ctx(struct dump_ctx *ctx, uint flags)
+{
+   memset(ctx, 0, sizeof(*ctx));
+
+   ctx->iter.prolog = prolog;
+   ctx->iter.iterate_instruction = iter_instruction;
+   ctx->iter.iterate_declaration = iter_declaration;
+   ctx->iter.iterate_immediate = iter_immediate;
+   ctx->iter.iterate_property = iter_property;
+
+   if (flags & TGSI_DUMP_FLOAT_AS_HEX)
+  ctx->dump_float_as_hex = TRUE;
+}
+
 void
 tgsi_dump_to_file(const struct tgsi_token *tokens, uint flags, FILE *file)
 {
struct dump_ctx ctx;
 
-   ctx.iter.prolog = prolog;
-   ctx.iter.iterate_instruction = iter_instruction;
-   ctx.iter.iterate_declaration = iter_declaration;
-   ctx.iter.iterate_immediate = iter_immediate;
-   ctx.iter.iterate_property = iter_property;
-   ctx.iter.epilog = NULL;
+   init_dump_ctx(, flags);
 
-   ctx.instno = 0;
-   ctx.immno = 0;
-   ctx.indent = 0;
ctx.dump_printf = dump_ctx_printf;
-   ctx.indentation = 0;
ctx.file = file;
 
-   if (flags & TGSI_DUMP_FLOAT_AS_HEX)
-  ctx.dump_float_as_hex = TRUE;
-   else
-  ctx.dump_float_as_hex = FALSE;
-
tgsi_iterate_shader( tokens,  );
 }
 
@@ -780,19 +781,9 @@ tgsi_dump_str(
 {
struct str_dump_ctx ctx;
 
-   ctx.base.iter.prolog = prolog;
-   ctx.base.iter.iterate_instruction = iter_instruction;
-   ctx.base.iter.iterate_declaration = iter_declaration;
-   ctx.base.iter.iterate_immediate = iter_immediate;
-   ctx.base.iter.iterate_property = iter_property;
-   ctx.base.iter.epilog = NULL;
+   init_dump_ctx(, flags);
 
-   ctx.base.instno = 0;
-   ctx.base.immno = 0;
-   ctx.base.indent = 0;
ctx.base.dump_printf = _dump_ctx_printf;
-   ctx.base.indentation = 0;
-   ctx.base.file = NULL;
 
ctx.str = str;
ctx.str[0] = 0;
@@ -800,11 +791,6 @@ tgsi_dump_str(
ctx.left = (int)size;
ctx.nospace = false;
 
-   if (flags & TGSI_DUMP_FLOAT_AS_HEX)
-  ctx.base.dump_float_as_hex = TRUE;
-   else
-  ctx.base.dump_float_as_hex = FALSE;
-
tgsi_iterate_shader( tokens,  );
 
return !ctx.nospace;
-- 
2.5.0

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[Mesa-dev] [Bug 95190] Tomb Raider with PostProcessing enable and Depth of Field set to Ultra has white stuff in the foreground

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=95190

--- Comment #6 from Samuel Pitoiset  ---
Err, drop the 'k', it's just the number of elements. But you get the idea. :)

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[Mesa-dev] [Bug 95190] Tomb Raider with PostProcessing enable and Depth of Field set to Ultra has white stuff in the foreground

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=95190

Ilia Mirkin  changed:

   What|Removed |Added

 QA Contact|intel-3d-bugs@lists.freedes |mesa-dev@lists.freedesktop.
   |ktop.org|org

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[Mesa-dev] [Bug 95088] src/intel/vulkan/anv_entrypoints.h:162:69: error: unknown type name ‘VkXcbSurfaceCreateInfoKHR’

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=95088

--- Comment #2 from Vinson Lee  ---
Build fails with clang too.

  CC   block_pool_no_free.o
In file included from block_pool_no_free.c:26:
In file included from ../../../../src/intel/vulkan/anv_private.h:60:
../../../../src/intel/vulkan/anv_entrypoints.h:162:69: error: unknown type name
'VkXcbSurfaceCreateInfoKHR'; did you mean 'VkDisplaySurfaceCreateInfoKHR'?
 VkResult (*CreateXcbSurfaceKHR)(VkInstance instance, const
VkXcbSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks*
pAllocator, VkSurfaceKHR* pSurface);
   
^
   
VkDisplaySurfaceCreateInfoKHR
../../../../include/vulkan/vulkan.h:3397:3: note:
'VkDisplaySurfaceCreateInfoKHR' declared here
} VkDisplaySurfaceCreateInfoKHR;
  ^

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[Mesa-dev] [PATCH 1/2] glsl: Convert lower_vec_index_to_swizzle to a rvalue visitor.

[Kenneth Graunke]

The old visitor missed some cases.  For example, it wouldn't handle
an ir_dereference_array with a vector_extract as the index.

Rather than trying to add the missing cases, just rewrite it as an
ir_rvalue_visitor.  This makes it easy to replace any expression,
and is much less code.

Cc: mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95164
Signed-off-by: Kenneth Graunke 
---
 src/compiler/glsl/lower_vec_index_to_swizzle.cpp | 96 
 1 file changed, 13 insertions(+), 83 deletions(-)

diff --git a/src/compiler/glsl/lower_vec_index_to_swizzle.cpp 
b/src/compiler/glsl/lower_vec_index_to_swizzle.cpp
index 8b18e95..b49255e 100644
--- a/src/compiler/glsl/lower_vec_index_to_swizzle.cpp
+++ b/src/compiler/glsl/lower_vec_index_to_swizzle.cpp
@@ -30,18 +30,14 @@
  */
 
 #include "ir.h"
-#include "ir_visitor.h"
+#include "ir_rvalue_visitor.h"
 #include "ir_optimization.h"
 #include "compiler/glsl_types.h"
 #include "main/macros.h"
 
-/**
- * Visitor class for replacing expressions with ir_constant values.
- */
-
 namespace {
 
-class ir_vec_index_to_swizzle_visitor : public ir_hierarchical_visitor {
+class ir_vec_index_to_swizzle_visitor : public ir_rvalue_visitor {
 public:
ir_vec_index_to_swizzle_visitor()
{
@@ -50,30 +46,28 @@ public:
 
ir_rvalue *convert_vector_extract_to_swizzle(ir_rvalue *val);
 
-   virtual ir_visitor_status visit_enter(ir_expression *);
-   virtual ir_visitor_status visit_enter(ir_swizzle *);
-   virtual ir_visitor_status visit_enter(ir_assignment *);
-   virtual ir_visitor_status visit_enter(ir_return *);
-   virtual ir_visitor_status visit_enter(ir_call *);
-   virtual ir_visitor_status visit_enter(ir_if *);
+   virtual void handle_rvalue(ir_rvalue **);
 
bool progress;
 };
 
 } /* anonymous namespace */
 
-ir_rvalue *
-ir_vec_index_to_swizzle_visitor::convert_vector_extract_to_swizzle(ir_rvalue 
*ir)
+void
+ir_vec_index_to_swizzle_visitor::handle_rvalue(ir_rvalue **rv)
 {
-   ir_expression *const expr = ir->as_expression();
+   if (*rv == NULL)
+  return;
+
+   ir_expression *const expr = (*rv)->as_expression();
if (expr == NULL || expr->operation != ir_binop_vector_extract)
-  return ir;
+  return;
 
ir_constant *const idx = expr->operands[1]->constant_expression_value();
if (idx == NULL)
-  return ir;
+  return;
 
-   void *ctx = ralloc_parent(ir);
+   void *ctx = ralloc_parent(expr);
this->progress = true;
 
/* Page 40 of the GLSL 1.20 spec says:
@@ -93,71 +87,7 @@ 
ir_vec_index_to_swizzle_visitor::convert_vector_extract_to_swizzle(ir_rvalue *ir
const int i = CLAMP(idx->value.i[0], 0,
(int) expr->operands[0]->type->vector_elements - 1);
 
-   return new(ctx) ir_swizzle(expr->operands[0], i, 0, 0, 0, 1);
-}
-
-ir_visitor_status
-ir_vec_index_to_swizzle_visitor::visit_enter(ir_expression *ir)
-{
-   unsigned int i;
-
-   for (i = 0; i < ir->get_num_operands(); i++) {
-  ir->operands[i] = convert_vector_extract_to_swizzle(ir->operands[i]);
-   }
-
-   return visit_continue;
-}
-
-ir_visitor_status
-ir_vec_index_to_swizzle_visitor::visit_enter(ir_swizzle *ir)
-{
-   /* Can't be hit from normal GLSL, since you can't swizzle a scalar (which
-* the result of indexing a vector is.  But maybe at some point we'll end up
-* using swizzling of scalars for vector construction.
-*/
-   ir->val = convert_vector_extract_to_swizzle(ir->val);
-
-   return visit_continue;
-}
-
-ir_visitor_status
-ir_vec_index_to_swizzle_visitor::visit_enter(ir_assignment *ir)
-{
-   ir->rhs = convert_vector_extract_to_swizzle(ir->rhs);
-
-   return visit_continue;
-}
-
-ir_visitor_status
-ir_vec_index_to_swizzle_visitor::visit_enter(ir_call *ir)
-{
-   foreach_in_list_safe(ir_rvalue, param, >actual_parameters) {
-  ir_rvalue *new_param = convert_vector_extract_to_swizzle(param);
-
-  if (new_param != param) {
-param->replace_with(new_param);
-  }
-   }
-
-   return visit_continue;
-}
-
-ir_visitor_status
-ir_vec_index_to_swizzle_visitor::visit_enter(ir_return *ir)
-{
-   if (ir->value) {
-  ir->value = convert_vector_extract_to_swizzle(ir->value);
-   }
-
-   return visit_continue;
-}
-
-ir_visitor_status
-ir_vec_index_to_swizzle_visitor::visit_enter(ir_if *ir)
-{
-   ir->condition = convert_vector_extract_to_swizzle(ir->condition);
-
-   return visit_continue;
+   *rv = new(ctx) ir_swizzle(expr->operands[0], i, 0, 0, 0, 1);
 }
 
 bool
-- 
2.8.0

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[Mesa-dev] [PATCH 2/2] glsl: Lower vector_extracts to swizzles after lower_vector_derefs.

[Kenneth Graunke]

lower_vector_derefs can produce new vector_extract operations.
Neither i965 nor st_glsl_to_tgsi can handle them, so we'd best
convert them to swizzles.

Cc: mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95164
Signed-off-by: Kenneth Graunke 
---
 src/compiler/glsl/linker.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index dcc8a57..7bd795c 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -4813,6 +4813,7 @@ link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
 >Comp.SharedSize);
 
   lower_vector_derefs(prog->_LinkedShaders[i]);
+  do_vec_index_to_swizzle(prog->_LinkedShaders[i]->ir);
}
 
 done:
-- 
2.8.0

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[Mesa-dev] [PATCH v2 1/4] egl: android: disable __DRI_DRI2_LOADER support on render nodes

[Rob Herring]

Use of __DRI_DRI2_LOADER extension is only supported for card nodes. In
order to support dmabufs, Android will be moving to using render nodes and
we need to disable the DRI2 loader extension.

This is based on the Wayland EGL code.

Cc: Rob Clark 
Cc: Emil Velikov 
Signed-off-by: Rob Herring 
---
 src/egl/drivers/dri2/egl_dri2.h |  3 ++-
 src/egl/drivers/dri2/platform_android.c | 31 ---
 2 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index ef79939..82b912e 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -212,9 +212,9 @@ struct dri2_egl_display
int  authenticated;
int  formats;
uint32_t  capabilities;
-   int  is_render_node;
 #endif
 
+   int  is_render_node;
int  is_different_gpu;
 };
 
@@ -285,6 +285,7 @@ struct dri2_egl_surface
 #ifdef HAVE_ANDROID_PLATFORM
struct ANativeWindow *window;
struct ANativeWindowBuffer *buffer;
+   __DRIimage *dri_image;
 
/* EGL-owned buffers */
__DRIbuffer   *local_buffers[__DRI_BUFFER_COUNT];
diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index c00b2c2..02122e3 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -29,6 +29,7 @@
 
 #include 
 #include 
+#include 
 
 #if ANDROID_VERSION >= 0x402
 #include 
@@ -694,17 +695,25 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *dpy)
   goto cleanup_driver_name;
}
 
-   dri2_dpy->dri2_loader_extension.base.name = __DRI_DRI2_LOADER;
-   dri2_dpy->dri2_loader_extension.base.version = 3;
-   dri2_dpy->dri2_loader_extension.getBuffers = NULL;
-   dri2_dpy->dri2_loader_extension.flushFrontBuffer = droid_flush_front_buffer;
-   dri2_dpy->dri2_loader_extension.getBuffersWithFormat =
-  droid_get_buffers_with_format;
-
-   dri2_dpy->extensions[0] = _dpy->dri2_loader_extension.base;
-   dri2_dpy->extensions[1] = _lookup_extension.base;
-   dri2_dpy->extensions[2] = _invalidate.base;
-   dri2_dpy->extensions[3] = NULL;
+   dri2_dpy->is_render_node = drmGetNodeTypeFromFd(dri2_dpy->fd) == 
DRM_NODE_RENDER;
+
+   dri2_dpy->extensions[0] = _lookup_extension.base;
+   dri2_dpy->extensions[1] = _invalidate.base;
+
+   /* render nodes cannot use Gem names, and thus do not support
+* the __DRI_DRI2_LOADER extension */
+   if (!dri2_dpy->is_render_node) {
+  dri2_dpy->dri2_loader_extension.base.name = __DRI_DRI2_LOADER;
+  dri2_dpy->dri2_loader_extension.base.version = 3;
+  dri2_dpy->dri2_loader_extension.getBuffers = NULL;
+  dri2_dpy->dri2_loader_extension.flushFrontBuffer = 
droid_flush_front_buffer;
+  dri2_dpy->dri2_loader_extension.getBuffersWithFormat =
+droid_get_buffers_with_format;
+  dri2_dpy->extensions[2] = _dpy->dri2_loader_extension.base;
+  dri2_dpy->extensions[3] = NULL;
+   } else
+  dri2_dpy->extensions[2] = NULL;
+
 
if (!dri2_create_screen(dpy)) {
   err = "DRI2: failed to create screen";
-- 
2.7.4

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[Mesa-dev] [PATCH v2 4/4] egl: android: add dma-buf fd support

[Rob Herring]

Add support for creating images from Android native buffers with dma-buf
fd. As dma-buf support also requires DRI image loader extension, add
that as well.

This is based on several originally patches written by Varad Gautam.
I've collapsed them into logical changes and done a bit of reformatting.
Using dma-bufs vs. GEM handles is now a runtime decision similar to the
wayland EGL instead of being compile time selection. The dma-buf support
is also re-written to use common dri2_create_image_dma_buf function in
egl_dri2.c.

Cc: Varad Gautam 
Cc: Rob Clark 
Cc: Emil Velikov 
Signed-off-by: Rob Herring 
---
 src/egl/drivers/dri2/platform_android.c | 124 ++--
 1 file changed, 117 insertions(+), 7 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index a922f01..9747338 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -65,6 +65,19 @@ get_format_bpp(int native)
return bpp;
 }
 
+/* createImageFromFds requires fourcc format */
+static int get_fourcc(int format)
+{
+   switch(format) {
+   case __DRI_IMAGE_FORMAT_RGB565:   return __DRI_IMAGE_FOURCC_RGB565;
+   case __DRI_IMAGE_FORMAT_ARGB: return __DRI_IMAGE_FOURCC_ARGB;
+   case __DRI_IMAGE_FORMAT_XRGB: return __DRI_IMAGE_FOURCC_XRGB;
+   case __DRI_IMAGE_FORMAT_ABGR: return __DRI_IMAGE_FOURCC_ABGR;
+   case __DRI_IMAGE_FORMAT_XBGR: return __DRI_IMAGE_FOURCC_XBGR;
+   }
+   return -1;
+}
+
 static int get_format(int format)
 {
switch (format) {
@@ -80,6 +93,18 @@ static int get_format(int format)
return -1;
 }
 static int
+get_native_buffer_fd(struct ANativeWindowBuffer *buf)
+{
+   native_handle_t *handle = (native_handle_t *)buf->handle;
+   /*
+* Various gralloc implementations exist, but the dma-buf fd tends
+* to be first. Access it directly to avoid a dependency on specific
+* gralloc versions.
+*/
+   return (handle && handle->numFds) ? handle->data[0] : -1;
+}
+
+static int
 get_native_buffer_name(struct ANativeWindowBuffer *buf)
 {
return gralloc_drm_get_gem_handle(buf->handle);
@@ -333,6 +358,66 @@ update_buffers(struct dri2_egl_surface *dri2_surf)
return 0;
 }
 
+static int
+get_back_bo(struct dri2_egl_surface *dri2_surf)
+{
+   struct dri2_egl_display *dri2_dpy =
+  dri2_egl_display(dri2_surf->base.Resource.Display);
+   int format, stride;
+   int offset = 0, fd;
+
+   if (!dri2_surf->buffer)
+  return -1;
+
+   fd = get_native_buffer_fd(dri2_surf->buffer);
+   if (fd < 0)
+  return -1;
+
+   format = get_format(dri2_surf->buffer->format);
+
+   stride = dri2_surf->buffer->stride *
+  get_format_bpp(dri2_surf->buffer->format);
+
+   dri2_surf->dri_image =
+  dri2_dpy->image->createImageFromFds(dri2_dpy->dri_screen,
+  dri2_surf->base.Width,
+  dri2_surf->base.Height,
+  get_fourcc(format),
+  ,
+  1,
+  ,
+  ,
+  dri2_surf);
+   if (!dri2_surf->dri_image)
+  return -1;
+
+   return 0;
+}
+
+static int
+droid_image_get_buffers(__DRIdrawable *driDrawable,
+  unsigned int format,
+  uint32_t *stamp,
+  void *loaderPrivate,
+  uint32_t buffer_mask,
+  struct __DRIimageList *images)
+{
+   struct dri2_egl_surface *dri2_surf = loaderPrivate;
+
+   if (update_buffers(dri2_surf) < 0)
+  return 0;
+
+   if (get_back_bo(dri2_surf) < 0) {
+  _eglError(EGL_BAD_PARAMETER, "get_back_bo");
+  return 0;
+   }
+
+   images->image_mask = __DRI_IMAGE_BUFFER_BACK;
+   images->back = dri2_surf->dri_image;
+
+   return 1;
+}
+
 static EGLBoolean
 droid_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *draw)
 {
@@ -361,12 +446,13 @@ droid_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, 
_EGLSurface *draw)
 }
 
 static _EGLImage *
-dri2_create_image_android_native_buffer(_EGLDisplay *disp, _EGLContext *ctx,
+dri2_create_image_android_native_buffer(_EGLDriver *drv, _EGLDisplay *disp,
+_EGLContext *ctx,
 struct ANativeWindowBuffer *buf)
 {
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
struct dri2_egl_image *dri2_img;
-   int name;
+   int name, fd;
 
if (ctx != NULL) {
   /* From the EGL_ANDROID_image_native_buffer spec:
@@ -386,6 +472,22 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp, 
_EGLContext *ctx,
   return NULL;
}
 
+   fd = get_native_buffer_fd(buf);
+   if (fd >= 0) {
+  const EGLint attr_list[14] = {

[Mesa-dev] [PATCH v2 3/4] egl: android: factor out back buffer handling code

[Rob Herring]

In preparation to use the same code for dma-bufs, factor out the code to a
separate function.

Signed-off-by: Rob Herring 
---
 src/egl/drivers/dri2/platform_android.c | 36 +
 1 file changed, 23 insertions(+), 13 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 204931b..a922f01 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -312,6 +312,27 @@ droid_destroy_surface(_EGLDriver *drv, _EGLDisplay *disp, 
_EGLSurface *surf)
return EGL_TRUE;
 }
 
+static int
+update_buffers(struct dri2_egl_surface *dri2_surf)
+{
+   if (dri2_surf->base.Type != EGL_WINDOW_BIT)
+  return 0;
+
+   /* try to dequeue the next back buffer */
+   if (!dri2_surf->buffer && !droid_window_dequeue_buffer(dri2_surf))
+  return -1;
+
+   /* free outdated buffers and update the surface size */
+   if (dri2_surf->base.Width != dri2_surf->buffer->width ||
+   dri2_surf->base.Height != dri2_surf->buffer->height) {
+  droid_free_local_buffers(dri2_surf);
+  dri2_surf->base.Width = dri2_surf->buffer->width;
+  dri2_surf->base.Height = dri2_surf->buffer->height;
+   }
+
+   return 0;
+}
+
 static EGLBoolean
 droid_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *draw)
 {
@@ -485,19 +506,8 @@ droid_get_buffers_with_format(__DRIdrawable * driDrawable,
   dri2_egl_display(dri2_surf->base.Resource.Display);
int i;
 
-   if (dri2_surf->base.Type == EGL_WINDOW_BIT) {
-  /* try to dequeue the next back buffer */
-  if (!dri2_surf->buffer && !droid_window_dequeue_buffer(dri2_surf))
- return NULL;
-
-  /* free outdated buffers and update the surface size */
-  if (dri2_surf->base.Width != dri2_surf->buffer->width ||
-  dri2_surf->base.Height != dri2_surf->buffer->height) {
- droid_free_local_buffers(dri2_surf);
- dri2_surf->base.Width = dri2_surf->buffer->width;
- dri2_surf->base.Height = dri2_surf->buffer->height;
-  }
-   }
+   if (update_buffers(dri2_surf) < 0)
+  return NULL;
 
dri2_surf->buffer_count =
   droid_get_buffers_parse_attachments(dri2_surf, attachments, count);
-- 
2.7.4

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[Mesa-dev] [PATCH v2 0/4] Android EGL dma-buf support

[Rob Herring]

This series adds dma-buf support for the Android EGL. This is based on
earlier work by Varad Gautam.

I've tried to maintain existing GEM handle support primarily for 
android-x86, but have not tested that path. So any testing would be 
helpful. A git branch is here[1].

Changes in v2:
- Split out refactoring patches
- Copied wayland EGL handling of dri2 loader with render nodes making 
image loader to be mutually exclusive
- factored out back buffer handling code to separate function

Rob

[1] https://github.com/robherring/mesa.git android-dma-buf-testing

Rob Herring (4):
  egl: android: disable __DRI_DRI2_LOADER support on render nodes
  egl: android: factor out format conversion code to a function
  egl: android: factor out back buffer handling code
  egl: android: add dma-buf fd support

 src/egl/drivers/dri2/egl_dri2.h |   3 +-
 src/egl/drivers/dri2/platform_android.c | 219 +---
 2 files changed, 172 insertions(+), 50 deletions(-)

-- 
2.7.4

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[Mesa-dev] [PATCH v2 2/4] egl: android: factor out format conversion code to a function

[Rob Herring]

Signed-off-by: Rob Herring 
---
 src/egl/drivers/dri2/platform_android.c | 38 +
 1 file changed, 15 insertions(+), 23 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 02122e3..204931b 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -65,6 +65,20 @@ get_format_bpp(int native)
return bpp;
 }
 
+static int get_format(int format)
+{
+   switch (format) {
+   case HAL_PIXEL_FORMAT_BGRA_: return __DRI_IMAGE_FORMAT_ARGB;
+   case HAL_PIXEL_FORMAT_RGB_565:   return __DRI_IMAGE_FORMAT_RGB565;
+   case HAL_PIXEL_FORMAT_RGBA_: return __DRI_IMAGE_FORMAT_ABGR;
+   case HAL_PIXEL_FORMAT_RGBX_: return __DRI_IMAGE_FORMAT_XBGR;
+   case HAL_PIXEL_FORMAT_RGB_888:
+  /* unsupported */
+   default:
+  _eglLog(_EGL_WARNING, "unsupported native buffer format 0x%x", format);
+   }
+   return -1;
+}
 static int
 get_native_buffer_name(struct ANativeWindowBuffer *buf)
 {
@@ -332,7 +346,6 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp, 
_EGLContext *ctx,
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
struct dri2_egl_image *dri2_img;
int name;
-   EGLint format;
 
if (ctx != NULL) {
   /* From the EGL_ANDROID_image_native_buffer spec:
@@ -358,27 +371,6 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp, 
_EGLContext *ctx,
   return NULL;
}
 
-   /* see the table in droid_add_configs_for_visuals */
-   switch (buf->format) {
-   case HAL_PIXEL_FORMAT_BGRA_:
-  format = __DRI_IMAGE_FORMAT_ARGB;
-  break;
-   case HAL_PIXEL_FORMAT_RGB_565:
-  format = __DRI_IMAGE_FORMAT_RGB565;
-  break;
-   case HAL_PIXEL_FORMAT_RGBA_:
-  format = __DRI_IMAGE_FORMAT_ABGR;
-  break;
-   case HAL_PIXEL_FORMAT_RGBX_:
-  format = __DRI_IMAGE_FORMAT_XBGR;
-  break;
-   case HAL_PIXEL_FORMAT_RGB_888:
-  /* unsupported */
-   default:
-  _eglLog(_EGL_WARNING, "unsupported native buffer format 0x%x", 
buf->format);
-  return NULL;
-  break;
-   }
 
dri2_img = calloc(1, sizeof(*dri2_img));
if (!dri2_img) {
@@ -395,7 +387,7 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp, 
_EGLContext *ctx,
   dri2_dpy->image->createImageFromName(dri2_dpy->dri_screen,
   buf->width,
   buf->height,
-  format,
+  get_format(buf->format),
   name,
   buf->stride,
   dri2_img);
-- 
2.7.4

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Re: [Mesa-dev] [android-x86-devel] [RFC 0/7] android: enable llvmpipe for software rendering

[Jose Fonseca]

On 28/04/16 20:53, Rob Herring wrote:

On Thu, Apr 28, 2016 at 1:57 PM, Jose Fonseca  wrote:

On 28/04/16 19:50, Rob Herring wrote:


On Thu, Apr 28, 2016 at 12:35 PM, Roland Scheidegger 
wrote:


Am 28.04.2016 um 17:52 schrieb Chih-Wei Huang:


I clearly understand this point.
Actually I've spent several days to try to
make it work on the master branch.
That's why it was delayed -- I supposed to send them
in the last week.


However, the master branch is always broken for android.


There are a lot of build break I need to fix and workaround
or I can't test it. After fixed all the errors and built it OK,
however, it didn't work as expected.
The system boots to Home but all display is garbled.
I'm not sure if I made some mistakes on
fixing the building errors or there are some changes
that really broke these patches.
(the latest commit I've tried in the master is 32cb7d61)
I finally decide to give it up and send them as the current status.
(otherwise it will take too much of my time and delay
my other pending tasks)

Unfortunately the situation is most mesa developers
don't care android so they usually break android build
or functions. Unless the situation is changed it's very hard
for us to follow the master branch closely.



I suppose if it's possible to set up some build bot for it which sends
out emails complaining when it breaks that would help with the build
failures.



I have that in my plans, but it is not there yet. I'm updating to
master at least weekly and fixing things, but new breakage seems to
happen faster than getting fixes committed. I'm usually the one fixing
the breakage. Given most people don't have an Android tree, having
them fix build problems is not all that realistic. I'll happily test
the fixes though.

BTW, the latest break is from "i965/fs_surface_builder: Add a helper
for converting GL to ISL formats."

Rob



Is using autotools or SCons for Android really impossible?


I looked into autotools and there are some tools to help with using
them for Android builds. They don't look too active and I'd guess
you'd replace screwing with the Android.mk with screwing with the
tool. I know nothing about SCons, but had the impression it breaks
frequently too.


SCons might break now and then, but the difference is that it's not left 
broken for long periods.


Anyway, the more overlap with the existing build systems the less likely 
it breaks.


For example, sharing Makefiles.sources between SCons and autotools 
greatly reduced the breakage (on both directions.)



Seems like the Google folks are up to something with the autotools, so
may be they have some solution in the works.


Let's hope so.

Jose
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Re: [Mesa-dev] [PATCH 4/4] gbm: Add map/unmap functions

[Eric Anholt]

Rob Herring  writes:

> On Wed, Apr 27, 2016 at 5:01 PM, Emil Velikov  
> wrote:
>> On 27 April 2016 at 19:51, Eric Anholt  wrote:
>>> Rob Herring  writes:
>>>
 On Mon, Apr 25, 2016 at 7:53 PM, Eric Anholt  wrote:
> Rob Herring  writes:
>
>> On Fri, Apr 22, 2016 at 9:08 PM, Rob Herring  wrote:
>>> On Fri, Apr 22, 2016 at 6:32 PM, Emil Velikov 
>>>  wrote:
 Hi Rob,

 On 22 April 2016 at 16:50, Rob Herring  wrote:
> This adds map and unmap functions to GBM utilizing the DRIimage 
> extension
> mapImage/unmapImage functions or existing internal mapping for dumb
> buffers.
 Ftr that this is quite sensitive and apart from the obvious breakage
 (coming in a second) it will need some testing on a gnome-continuous
 setup (iirc some used to hand out in #xorg-devel)

> Unlike prior attempts, this version provides a region to map and
> usage flags for the mapping. The operation follows the same semantics 
> as
> the gallium transfer_map() function.
>
> This was tested with GBM based gralloc on Android.
>
> This still creates a context, but I've moved it into gbm_create_device
> rather than in the map function. This should remove any need for 
> reference
> counting and problems with memory leaks.
>
> Signed-off-by: Rob Herring 
>>>
>>> [...]
>>>
>>
> @@ -1004,6 +1058,10 @@ dri_device_create(int fd)
> if (ret)
>goto err_dri;
>
> +   if (dri->image->base.version >= 12)
> +  dri->context = dri->dri2->createNewContext(dri->screen, NULL,
> + NULL, NULL);
> +
 Have you measured how much this costs us (cpu time and/or memory) ?
>>>
>>> No, will do.
>>
>> On Android (x86_64 + virgl), it is 2ms and ~2MB (out of 20). A
>> standalone test with swrast is 4ms and ~4MB. I measured with
>> getrusage().
>
> Given that existing clients of GBM don't use this API, it's not OK to
> add this cost to all of them.

 Agreed.

> If you need pthreads to protect the allocation check at map time,

 I do...

> there's this bit of configure.ac from libdrm so that you don't need to
> force libgbm to pull in real pthreads and its overhead:
>
> PKG_CHECK_MODULES(PTHREADSTUBS, pthread-stubs)
> AC_SUBST(PTHREADSTUBS_CFLAGS)
> AC_SUBST(PTHREADSTUBS_LIBS)

>> Side note: pthread-stubs expands to a single .pc file on GLIBC (Linux
>> in general ?) platforms. That's because libc.so already has these
>> stubs.
>>
 GBM requires DRI which already pulls in pthreads, so I don't think
 this is needed. Or am I missing something?
>>>
>>> I'm fine with that, just noting that my libgbm currently doesn't link
>>> pthreads, and providing a solution if people didn't want to force
>>> linking pthreads for libgbm.so.
>> Not only yours - libgbm does not link against pthreads.so. Period.
>> The DRI modules on the other hand (amongst others) do.
>
> Okay, with Emil's patch I have it just using the stub. However, it
> seems I don't really need the above configure.ac hunk. Is that only
> needed for non-Linux/glibc builds?

Yeah, it's the tool that hides that nastiness of other platforms for
us.


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Re: [Mesa-dev] [android-x86-devel] [RFC 0/7] android: enable llvmpipe for software rendering

[Rob Herring]

On Thu, Apr 28, 2016 at 1:57 PM, Jose Fonseca  wrote:
> On 28/04/16 19:50, Rob Herring wrote:
>>
>> On Thu, Apr 28, 2016 at 12:35 PM, Roland Scheidegger 
>> wrote:
>>>
>>> Am 28.04.2016 um 17:52 schrieb Chih-Wei Huang:

 I clearly understand this point.
 Actually I've spent several days to try to
 make it work on the master branch.
 That's why it was delayed -- I supposed to send them
 in the last week.
>
> However, the master branch is always broken for android.

 There are a lot of build break I need to fix and workaround
 or I can't test it. After fixed all the errors and built it OK,
 however, it didn't work as expected.
 The system boots to Home but all display is garbled.
 I'm not sure if I made some mistakes on
 fixing the building errors or there are some changes
 that really broke these patches.
 (the latest commit I've tried in the master is 32cb7d61)
 I finally decide to give it up and send them as the current status.
 (otherwise it will take too much of my time and delay
 my other pending tasks)

 Unfortunately the situation is most mesa developers
 don't care android so they usually break android build
 or functions. Unless the situation is changed it's very hard
 for us to follow the master branch closely.
>>>
>>>
>>> I suppose if it's possible to set up some build bot for it which sends
>>> out emails complaining when it breaks that would help with the build
>>> failures.
>>
>>
>> I have that in my plans, but it is not there yet. I'm updating to
>> master at least weekly and fixing things, but new breakage seems to
>> happen faster than getting fixes committed. I'm usually the one fixing
>> the breakage. Given most people don't have an Android tree, having
>> them fix build problems is not all that realistic. I'll happily test
>> the fixes though.
>>
>> BTW, the latest break is from "i965/fs_surface_builder: Add a helper
>> for converting GL to ISL formats."
>>
>> Rob
>
>
> Is using autotools or SCons for Android really impossible?

I looked into autotools and there are some tools to help with using
them for Android builds. They don't look too active and I'd guess
you'd replace screwing with the Android.mk with screwing with the
tool. I know nothing about SCons, but had the impression it breaks
frequently too.

Seems like the Google folks are up to something with the autotools, so
may be they have some solution in the works.

Rob
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Re: [Mesa-dev] [PATCH 7/7] i965: Remove inst_info table from brw_eu_validate.

[Francisco Jerez]

Matt Turner  writes:

> On Thu, Apr 28, 2016 at 12:19 AM, Francisco Jerez  
> wrote:
>> At this point this doesn't contain any information not already in the
>> opcode_desc tables, the validation code can just call
>> brw_opcode_desc() in order to find out whether an instruction is
>> supported by the device.
>
> NAK. This table is intended to handle things other than the supported
> generation -- I sent patches that add more fields but they're in some
> review limbo state.

But you notice that this is kind of the killer feature you get from this
series (even though it wasn't its original motivation)?

The fact that we currently have to update twenty different places any
time a new instruction is introduced is quite terrible.  If you need to
add additional per-instruction metadata please just put them into the
same table -- If there is some reason why you can't I'm afraid that the
current approach used in the validator won't work either and may have to
be reworked because of overlapping opcodes, but it seems better in the
long term and less work to just remove it.


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Re: [Mesa-dev] [PATCH 4/7] i965/disasm: Split opcode tables by the generation they were introduced in.

[Francisco Jerez]

Matt Turner  writes:

> On Thu, Apr 28, 2016 at 12:19 AM, Francisco Jerez  
> wrote:
>> ---
>>  src/mesa/drivers/dri/i965/brw_disasm.c | 90 
>> ++
>>  1 file changed, 69 insertions(+), 21 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
>> b/src/mesa/drivers/dri/i965/brw_disasm.c
>> index 15d9383..0125434 100644
>> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
>> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
>> @@ -30,9 +30,8 @@
>>  #include "brw_inst.h"
>>  #include "brw_eu.h"
>>
>> -static const struct opcode_desc opcode_descs[128] = {
>> +static const struct opcode_desc gen4_opcode_descs[128] = {
>> [BRW_OPCODE_MOV]  = { .name = "mov", .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_MOVI] = { .name = "movi",.nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_FRC]  = { .name = "frc", .nsrc = 1, .ndst = 1 },
>> [BRW_OPCODE_RNDU] = { .name = "rndu",.nsrc = 1, .ndst = 1 },
>> [BRW_OPCODE_RNDD] = { .name = "rndd",.nsrc = 1, .ndst = 1 },
>> @@ -40,27 +39,17 @@ static const struct opcode_desc opcode_descs[128] = {
>> [BRW_OPCODE_RNDZ] = { .name = "rndz",.nsrc = 1, .ndst = 1 },
>> [BRW_OPCODE_NOT]  = { .name = "not", .nsrc = 1, .ndst = 1 },
>> [BRW_OPCODE_LZD]  = { .name = "lzd", .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_F32TO16]  = { .name = "f32to16", .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_F16TO32]  = { .name = "f16to32", .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_BFREV]= { .name = "bfrev",   .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_FBH]  = { .name = "fbh", .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_FBL]  = { .name = "fbl", .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_CBIT] = { .name = "cbit",.nsrc = 1, .ndst = 1 },
>>
>> [BRW_OPCODE_MUL]  = { .name = "mul", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_MAC]  = { .name = "mac", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_MACH] = { .name = "mach",.nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_LINE] = { .name = "line",.nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_PLN]  = { .name = "pln", .nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_MAD]  = { .name = "mad", .nsrc = 3, .ndst = 1 },
>> -   [BRW_OPCODE_LRP]  = { .name = "lrp", .nsrc = 3, .ndst = 1 },
>> [BRW_OPCODE_SAD2] = { .name = "sad2",.nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_SADA2]= { .name = "sada2",   .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_DP4]  = { .name = "dp4", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_DPH]  = { .name = "dph", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_DP3]  = { .name = "dp3", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_DP2]  = { .name = "dp2", .nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_MATH] = { .name = "math",.nsrc = 2, .ndst = 1 },
>>
>> [BRW_OPCODE_AVG]  = { .name = "avg", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_ADD]  = { .name = "add", .nsrc = 2, .ndst = 1 },
>> @@ -73,17 +62,9 @@ static const struct opcode_desc opcode_descs[128] = {
>> [BRW_OPCODE_ASR]  = { .name = "asr", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_CMP]  = { .name = "cmp", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_CMPN] = { .name = "cmpn",.nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_CSEL] = { .name = "csel",.nsrc = 3, .ndst = 1 },
>> -   [BRW_OPCODE_BFE]  = { .name = "bfe", .nsrc = 3, .ndst = 1 },
>> -   [BRW_OPCODE_BFI1] = { .name = "bfi1",.nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_BFI2] = { .name = "bfi2",.nsrc = 3, .ndst = 1 },
>> -   [BRW_OPCODE_ADDC] = { .name = "addc",.nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_SUBB] = { .name = "subb",.nsrc = 2, .ndst = 1 },
>>
>> [BRW_OPCODE_SEND] = { .name = "send",.nsrc = 1, .ndst = 1 },
>> [BRW_OPCODE_SENDC]= { .name = "sendc",   .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_SENDS]= { .name = "sends",   .nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_SENDSC]   = { .name = "sendsc",  .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_ILLEGAL]  = { .name = "illegal", .nsrc = 0, .ndst = 0 },
>> [BRW_OPCODE_NOP]  = { .name = "nop", .nsrc = 0, .ndst = 0 },
>> [BRW_OPCODE_NENOP]= { .name = "nenop",   .nsrc = 0, .ndst = 0 },
>> @@ -104,6 +85,70 @@ static const struct opcode_desc opcode_descs[128] = {
>> [BRW_OPCODE_ENDIF]= { .name = "endif",   .nsrc = 0, .ndst = 0 },
>>  };
>>
>> +static const struct opcode_desc g45_opcode_descs[128] = {
>> +   [BRW_OPCODE_MOVI] = { .name = "movi",.nsrc = 2, .ndst = 1 },
>> +   [BRW_OPCODE_PLN]  = { .name = "pln", .nsrc = 2, .ndst = 1 },
>> +};
>> +
>> +static const struct opcode_desc gen6_opcode_descs[128] = {
>> +   [BRW_OPCODE_MATH] = { .name = "math",.nsrc = 2, .ndst = 1 },
>> +   [BRW_OPCODE_MAD]  = { .name = "mad", .nsrc = 3, .ndst = 1 },
>> +   [BRW_OPCODE_LRP]  = { 

Re: [Mesa-dev] [PATCH 1/4] nir: Avoid C99 field initializers.

[Jason Ekstrand]

On Thu, Apr 28, 2016 at 11:55 AM, Jose Fonseca  wrote:

> On 28/04/16 18:43, Jason Ekstrand wrote:
>
>> On Thu, Apr 28, 2016 at 8:49 AM, Jose Fonseca > > wrote:
>>
>> On 28/04/16 15:37, Connor Abbott wrote:
>>
>> For the series:
>>
>> Reviewed-by: Connor Abbott > >
>>
>> For the zero-sized array thing... we could make it a
>> statically-sized
>> array, since we never have more than 4 arguments to an ALU
>> instruction, but that would be wasteful of memory. Also, we always
>> have at least 1 argument, so we could make the size 1 to shut up
>> the
>> warning, but that would be more confusing and introduce undefined
>> behavior in C99 that the compiler is likely to actually take
>> advantage
>> of. I don't see any options better than just accepting the warning
>> and/or shutting that specific warning off.
>>
>>
>> I feared so.  Thanks for looking into it though.
>>
>>
>> Can you be a bit more specific about the issues that MSVC has with
>> zero-length arrays?  Can it "accept nir_src src[0]" instead of "src[]"?
>>
>
>
> To be clear, MSVC doesn't really have a problem with zero length arrays.
> (I haven't actually tested the code, but at least MSVC compiles it without
> errors.)
>
>
> MSVC does have a problem with C99 field initializers -- it will throw an
> error.
>
>
> So I'd like to GCC to warn about C99 field initializers.  But
> unfortunately it's not possible to only warn about that: -Wpedantic warns
> about all non-standard extensions, including C99 zero-length arrays.
>
>
> So, if we could avoid zero-length arrays and other stuff that -Wpedantic
> warngs, that would make things simpler.  But no biggie.
>
>
> The key thing here is avoid C99 struct field initializers on the NIR
> headers that are mean to be used from C++.
>

Thanks for the clarification!  I'll try and keep my eye out for that.
--Jason
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Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: fix potential crash when allocating temporaries

[Ilia Mirkin]

Cc: "11.1 11.2" 
Reviewed-by: Ilia Mirkin 

On Thu, Apr 28, 2016 at 3:09 PM, Samuel Pitoiset
 wrote:
> When index - t->temps_size is greater than 4096, allocating space for
> temporaries on demand will miserably crash. This can happen when a game
> uses a lot of temporaries like the recent released Tomb raider.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index ad818a8..7ba9856 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -5348,7 +5348,7 @@ dst_register(struct st_translate *t, gl_register_file 
> file, unsigned index,
> case PROGRAM_TEMPORARY:
>/* Allocate space for temporaries on demand. */
>if (index >= t->temps_size) {
> - const int inc = 4096;
> + const int inc = align(index - t->temps_size + 1, 4096);
>
>   t->temps = (struct ureg_dst*)
>  realloc(t->temps,
> --
> 2.8.0
>
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[Mesa-dev] [PATCH] st/glsl_to_tgsi: fix potential crash when allocating temporaries

[Samuel Pitoiset]

When index - t->temps_size is greater than 4096, allocating space for
temporaries on demand will miserably crash. This can happen when a game
uses a lot of temporaries like the recent released Tomb raider.

Signed-off-by: Samuel Pitoiset 
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index ad818a8..7ba9856 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -5348,7 +5348,7 @@ dst_register(struct st_translate *t, gl_register_file 
file, unsigned index,
case PROGRAM_TEMPORARY:
   /* Allocate space for temporaries on demand. */
   if (index >= t->temps_size) {
- const int inc = 4096;
+ const int inc = align(index - t->temps_size + 1, 4096);
 
  t->temps = (struct ureg_dst*)
 realloc(t->temps,
-- 
2.8.0

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[Mesa-dev] [Bug 92850] Segfault loading War Thunder

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=92850

--- Comment #70 from bellamort...@gmail.com ---
Understood.  Thank you for putting in the extra work to make this happen, it's
much appreciated.

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[Mesa-dev] [PATCH] Android: fix build ordering of subdirectories

[Rob Herring]

Different versions of make behave differently in whether $(wildcard) sorts
the results or not. The Android build now explicitly sorts
all-named-subdir-makefiles which breaks the build because src/gallium
must be included after src/mesa/drivers/dri.

The Android build system doesn't support doing "include $(call
all-named-subdir-makefiles,...)" twice, so rework things by generating
the included makefile list and including them in 2 steps.

Signed-off-by: Rob Herring 
---
 Android.mk | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Android.mk b/Android.mk
index aa4350f..bd42bc6 100644
--- a/Android.mk
+++ b/Android.mk
@@ -96,10 +96,12 @@ SUBDIRS := \
src/egl \
src/mesa/drivers/dri
 
+INC_DIRS := $(call all-named-subdir-makefiles,$(SUBDIRS))
+
 ifeq ($(strip $(MESA_BUILD_GALLIUM)),true)
-SUBDIRS += src/gallium
+INC_DIRS += $(call all-named-subdir-makefiles,src/gallium)
 endif
 
-include $(call all-named-subdir-makefiles,$(SUBDIRS))
+include $(INC_DIRS)
 
 endif
-- 
2.7.4

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Re: [Mesa-dev] [android-x86-devel] [RFC 0/7] android: enable llvmpipe for software rendering

[Jose Fonseca]

On 28/04/16 19:50, Rob Herring wrote:

On Thu, Apr 28, 2016 at 12:35 PM, Roland Scheidegger  wrote:

Am 28.04.2016 um 17:52 schrieb Chih-Wei Huang:

I clearly understand this point.
Actually I've spent several days to try to
make it work on the master branch.
That's why it was delayed -- I supposed to send them
in the last week.

However, the master branch is always broken for android.

There are a lot of build break I need to fix and workaround
or I can't test it. After fixed all the errors and built it OK,
however, it didn't work as expected.
The system boots to Home but all display is garbled.
I'm not sure if I made some mistakes on
fixing the building errors or there are some changes
that really broke these patches.
(the latest commit I've tried in the master is 32cb7d61)
I finally decide to give it up and send them as the current status.
(otherwise it will take too much of my time and delay
my other pending tasks)

Unfortunately the situation is most mesa developers
don't care android so they usually break android build
or functions. Unless the situation is changed it's very hard
for us to follow the master branch closely.


I suppose if it's possible to set up some build bot for it which sends
out emails complaining when it breaks that would help with the build
failures.


I have that in my plans, but it is not there yet. I'm updating to
master at least weekly and fixing things, but new breakage seems to
happen faster than getting fixes committed. I'm usually the one fixing
the breakage. Given most people don't have an Android tree, having
them fix build problems is not all that realistic. I'll happily test
the fixes though.

BTW, the latest break is from "i965/fs_surface_builder: Add a helper
for converting GL to ISL formats."

Rob


Is using autotools or SCons for Android really impossible?

Jose

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Re: [Mesa-dev] [PATCH 4/7] i965/disasm: Split opcode tables by the generation they were introduced in.

[Matt Turner]

On Thu, Apr 28, 2016 at 11:45 AM, Matt Turner  wrote:
> On Thu, Apr 28, 2016 at 12:19 AM, Francisco Jerez  
> wrote:
>> ---
>>  src/mesa/drivers/dri/i965/brw_disasm.c | 90 
>> ++
>>  1 file changed, 69 insertions(+), 21 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
>> b/src/mesa/drivers/dri/i965/brw_disasm.c
>> index 15d9383..0125434 100644
>> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
>> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
>> @@ -30,9 +30,8 @@
>>  #include "brw_inst.h"
>>  #include "brw_eu.h"
>>
>> -static const struct opcode_desc opcode_descs[128] = {
>> +static const struct opcode_desc gen4_opcode_descs[128] = {
>> [BRW_OPCODE_MOV]  = { .name = "mov", .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_MOVI] = { .name = "movi",.nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_FRC]  = { .name = "frc", .nsrc = 1, .ndst = 1 },
>> [BRW_OPCODE_RNDU] = { .name = "rndu",.nsrc = 1, .ndst = 1 },
>> [BRW_OPCODE_RNDD] = { .name = "rndd",.nsrc = 1, .ndst = 1 },
>> @@ -40,27 +39,17 @@ static const struct opcode_desc opcode_descs[128] = {
>> [BRW_OPCODE_RNDZ] = { .name = "rndz",.nsrc = 1, .ndst = 1 },
>> [BRW_OPCODE_NOT]  = { .name = "not", .nsrc = 1, .ndst = 1 },
>> [BRW_OPCODE_LZD]  = { .name = "lzd", .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_F32TO16]  = { .name = "f32to16", .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_F16TO32]  = { .name = "f16to32", .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_BFREV]= { .name = "bfrev",   .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_FBH]  = { .name = "fbh", .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_FBL]  = { .name = "fbl", .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_CBIT] = { .name = "cbit",.nsrc = 1, .ndst = 1 },
>>
>> [BRW_OPCODE_MUL]  = { .name = "mul", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_MAC]  = { .name = "mac", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_MACH] = { .name = "mach",.nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_LINE] = { .name = "line",.nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_PLN]  = { .name = "pln", .nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_MAD]  = { .name = "mad", .nsrc = 3, .ndst = 1 },
>> -   [BRW_OPCODE_LRP]  = { .name = "lrp", .nsrc = 3, .ndst = 1 },
>> [BRW_OPCODE_SAD2] = { .name = "sad2",.nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_SADA2]= { .name = "sada2",   .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_DP4]  = { .name = "dp4", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_DPH]  = { .name = "dph", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_DP3]  = { .name = "dp3", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_DP2]  = { .name = "dp2", .nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_MATH] = { .name = "math",.nsrc = 2, .ndst = 1 },
>>
>> [BRW_OPCODE_AVG]  = { .name = "avg", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_ADD]  = { .name = "add", .nsrc = 2, .ndst = 1 },
>> @@ -73,17 +62,9 @@ static const struct opcode_desc opcode_descs[128] = {
>> [BRW_OPCODE_ASR]  = { .name = "asr", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_CMP]  = { .name = "cmp", .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_CMPN] = { .name = "cmpn",.nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_CSEL] = { .name = "csel",.nsrc = 3, .ndst = 1 },
>> -   [BRW_OPCODE_BFE]  = { .name = "bfe", .nsrc = 3, .ndst = 1 },
>> -   [BRW_OPCODE_BFI1] = { .name = "bfi1",.nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_BFI2] = { .name = "bfi2",.nsrc = 3, .ndst = 1 },
>> -   [BRW_OPCODE_ADDC] = { .name = "addc",.nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_SUBB] = { .name = "subb",.nsrc = 2, .ndst = 1 },
>>
>> [BRW_OPCODE_SEND] = { .name = "send",.nsrc = 1, .ndst = 1 },
>> [BRW_OPCODE_SENDC]= { .name = "sendc",   .nsrc = 1, .ndst = 1 },
>> -   [BRW_OPCODE_SENDS]= { .name = "sends",   .nsrc = 2, .ndst = 1 },
>> -   [BRW_OPCODE_SENDSC]   = { .name = "sendsc",  .nsrc = 2, .ndst = 1 },
>> [BRW_OPCODE_ILLEGAL]  = { .name = "illegal", .nsrc = 0, .ndst = 0 },
>> [BRW_OPCODE_NOP]  = { .name = "nop", .nsrc = 0, .ndst = 0 },
>> [BRW_OPCODE_NENOP]= { .name = "nenop",   .nsrc = 0, .ndst = 0 },
>> @@ -104,6 +85,70 @@ static const struct opcode_desc opcode_descs[128] = {
>> [BRW_OPCODE_ENDIF]= { .name = "endif",   .nsrc = 0, .ndst = 0 },
>>  };
>>
>> +static const struct opcode_desc g45_opcode_descs[128] = {
>> +   [BRW_OPCODE_MOVI] = { .name = "movi",.nsrc = 2, .ndst = 1 },
>> +   [BRW_OPCODE_PLN]  = { .name = "pln", .nsrc = 2, .ndst = 1 },
>> +};
>> +
>> +static const struct opcode_desc gen6_opcode_descs[128] = {
>> +   [BRW_OPCODE_MATH] = { .name = "math",.nsrc = 2, .ndst = 1 },
>> +   [BRW_OPCODE_MAD]  = { .name = "mad", .nsrc = 3, .ndst = 1 },

Re: [Mesa-dev] [PATCH 1/4] nir: Avoid C99 field initializers.

[Jose Fonseca]

On 28/04/16 18:43, Jason Ekstrand wrote:

On Thu, Apr 28, 2016 at 8:49 AM, Jose Fonseca > wrote:

On 28/04/16 15:37, Connor Abbott wrote:

For the series:

Reviewed-by: Connor Abbott >

For the zero-sized array thing... we could make it a
statically-sized
array, since we never have more than 4 arguments to an ALU
instruction, but that would be wasteful of memory. Also, we always
have at least 1 argument, so we could make the size 1 to shut up the
warning, but that would be more confusing and introduce undefined
behavior in C99 that the compiler is likely to actually take
advantage
of. I don't see any options better than just accepting the warning
and/or shutting that specific warning off.


I feared so.  Thanks for looking into it though.


Can you be a bit more specific about the issues that MSVC has with
zero-length arrays?  Can it "accept nir_src src[0]" instead of "src[]"?



To be clear, MSVC doesn't really have a problem with zero length arrays. 
 (I haven't actually tested the code, but at least MSVC compiles it 
without errors.)



MSVC does have a problem with C99 field initializers -- it will throw an 
error.



So I'd like to GCC to warn about C99 field initializers.  But 
unfortunately it's not possible to only warn about that: -Wpedantic 
warns about all non-standard extensions, including C99 zero-length arrays.



So, if we could avoid zero-length arrays and other stuff that -Wpedantic 
warngs, that would make things simpler.  But no biggie.



The key thing here is avoid C99 struct field initializers on the NIR 
headers that are mean to be used from C++.



Jose
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Re: [Mesa-dev] [PATCH 7/7] i965: Remove inst_info table from brw_eu_validate.

[Matt Turner]

On Thu, Apr 28, 2016 at 11:35 AM, Matt Turner  wrote:
> On Thu, Apr 28, 2016 at 12:19 AM, Francisco Jerez  
> wrote:
>> At this point this doesn't contain any information not already in the
>> opcode_desc tables, the validation code can just call
>> brw_opcode_desc() in order to find out whether an instruction is
>> supported by the device.
>
> NAK. This table is intended to handle things other than the supported
> generation -- I sent patches that add more fields but they're in some
> review limbo state.

I think I actually like this if you take my feedback on 4/7. Since you
have to add a gen field, if you integrate the field used here into the
opcode_descs table, I'm in favor of combining the tables.
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Re: [Mesa-dev] [android-x86-devel] [RFC 0/7] android: enable llvmpipe for software rendering

[Rob Herring]

On Thu, Apr 28, 2016 at 12:35 PM, Roland Scheidegger  wrote:
> Am 28.04.2016 um 17:52 schrieb Chih-Wei Huang:
>> I clearly understand this point.
>> Actually I've spent several days to try to
>> make it work on the master branch.
>> That's why it was delayed -- I supposed to send them
>> in the last week.
>> > However, the master branch is always broken for android.
>> There are a lot of build break I need to fix and workaround
>> or I can't test it. After fixed all the errors and built it OK,
>> however, it didn't work as expected.
>> The system boots to Home but all display is garbled.
>> I'm not sure if I made some mistakes on
>> fixing the building errors or there are some changes
>> that really broke these patches.
>> (the latest commit I've tried in the master is 32cb7d61)
>> I finally decide to give it up and send them as the current status.
>> (otherwise it will take too much of my time and delay
>> my other pending tasks)
>>
>> Unfortunately the situation is most mesa developers
>> don't care android so they usually break android build
>> or functions. Unless the situation is changed it's very hard
>> for us to follow the master branch closely.
>
> I suppose if it's possible to set up some build bot for it which sends
> out emails complaining when it breaks that would help with the build
> failures.

I have that in my plans, but it is not there yet. I'm updating to
master at least weekly and fixing things, but new breakage seems to
happen faster than getting fixes committed. I'm usually the one fixing
the breakage. Given most people don't have an Android tree, having
them fix build problems is not all that realistic. I'll happily test
the fixes though.

BTW, the latest break is from "i965/fs_surface_builder: Add a helper
for converting GL to ISL formats."

Rob
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Re: [Mesa-dev] [PATCH 4/7] i965/disasm: Split opcode tables by the generation they were introduced in.

[Matt Turner]

On Thu, Apr 28, 2016 at 12:19 AM, Francisco Jerez  wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 90 
> ++
>  1 file changed, 69 insertions(+), 21 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 15d9383..0125434 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -30,9 +30,8 @@
>  #include "brw_inst.h"
>  #include "brw_eu.h"
>
> -static const struct opcode_desc opcode_descs[128] = {
> +static const struct opcode_desc gen4_opcode_descs[128] = {
> [BRW_OPCODE_MOV]  = { .name = "mov", .nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_MOVI] = { .name = "movi",.nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_FRC]  = { .name = "frc", .nsrc = 1, .ndst = 1 },
> [BRW_OPCODE_RNDU] = { .name = "rndu",.nsrc = 1, .ndst = 1 },
> [BRW_OPCODE_RNDD] = { .name = "rndd",.nsrc = 1, .ndst = 1 },
> @@ -40,27 +39,17 @@ static const struct opcode_desc opcode_descs[128] = {
> [BRW_OPCODE_RNDZ] = { .name = "rndz",.nsrc = 1, .ndst = 1 },
> [BRW_OPCODE_NOT]  = { .name = "not", .nsrc = 1, .ndst = 1 },
> [BRW_OPCODE_LZD]  = { .name = "lzd", .nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_F32TO16]  = { .name = "f32to16", .nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_F16TO32]  = { .name = "f16to32", .nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_BFREV]= { .name = "bfrev",   .nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_FBH]  = { .name = "fbh", .nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_FBL]  = { .name = "fbl", .nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_CBIT] = { .name = "cbit",.nsrc = 1, .ndst = 1 },
>
> [BRW_OPCODE_MUL]  = { .name = "mul", .nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_MAC]  = { .name = "mac", .nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_MACH] = { .name = "mach",.nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_LINE] = { .name = "line",.nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_PLN]  = { .name = "pln", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_MAD]  = { .name = "mad", .nsrc = 3, .ndst = 1 },
> -   [BRW_OPCODE_LRP]  = { .name = "lrp", .nsrc = 3, .ndst = 1 },
> [BRW_OPCODE_SAD2] = { .name = "sad2",.nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_SADA2]= { .name = "sada2",   .nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_DP4]  = { .name = "dp4", .nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_DPH]  = { .name = "dph", .nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_DP3]  = { .name = "dp3", .nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_DP2]  = { .name = "dp2", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_MATH] = { .name = "math",.nsrc = 2, .ndst = 1 },
>
> [BRW_OPCODE_AVG]  = { .name = "avg", .nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_ADD]  = { .name = "add", .nsrc = 2, .ndst = 1 },
> @@ -73,17 +62,9 @@ static const struct opcode_desc opcode_descs[128] = {
> [BRW_OPCODE_ASR]  = { .name = "asr", .nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_CMP]  = { .name = "cmp", .nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_CMPN] = { .name = "cmpn",.nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_CSEL] = { .name = "csel",.nsrc = 3, .ndst = 1 },
> -   [BRW_OPCODE_BFE]  = { .name = "bfe", .nsrc = 3, .ndst = 1 },
> -   [BRW_OPCODE_BFI1] = { .name = "bfi1",.nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_BFI2] = { .name = "bfi2",.nsrc = 3, .ndst = 1 },
> -   [BRW_OPCODE_ADDC] = { .name = "addc",.nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_SUBB] = { .name = "subb",.nsrc = 2, .ndst = 1 },
>
> [BRW_OPCODE_SEND] = { .name = "send",.nsrc = 1, .ndst = 1 },
> [BRW_OPCODE_SENDC]= { .name = "sendc",   .nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_SENDS]= { .name = "sends",   .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_SENDSC]   = { .name = "sendsc",  .nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_ILLEGAL]  = { .name = "illegal", .nsrc = 0, .ndst = 0 },
> [BRW_OPCODE_NOP]  = { .name = "nop", .nsrc = 0, .ndst = 0 },
> [BRW_OPCODE_NENOP]= { .name = "nenop",   .nsrc = 0, .ndst = 0 },
> @@ -104,6 +85,70 @@ static const struct opcode_desc opcode_descs[128] = {
> [BRW_OPCODE_ENDIF]= { .name = "endif",   .nsrc = 0, .ndst = 0 },
>  };
>
> +static const struct opcode_desc g45_opcode_descs[128] = {
> +   [BRW_OPCODE_MOVI] = { .name = "movi",.nsrc = 2, .ndst = 1 },
> +   [BRW_OPCODE_PLN]  = { .name = "pln", .nsrc = 2, .ndst = 1 },
> +};
> +
> +static const struct opcode_desc gen6_opcode_descs[128] = {
> +   [BRW_OPCODE_MATH] = { .name = "math",.nsrc = 2, .ndst = 1 },
> +   [BRW_OPCODE_MAD]  = { .name = "mad", .nsrc = 3, .ndst = 1 },
> +   [BRW_OPCODE_LRP]  = { .name = "lrp", .nsrc = 3, .ndst = 1 },
> +};
> +
> +static const struct opcode_desc gen7_opcode_descs[128] = {
> +   

Re: [Mesa-dev] [PATCH 7/7] i965: Remove inst_info table from brw_eu_validate.

[Matt Turner]

On Thu, Apr 28, 2016 at 12:19 AM, Francisco Jerez  wrote:
> At this point this doesn't contain any information not already in the
> opcode_desc tables, the validation code can just call
> brw_opcode_desc() in order to find out whether an instruction is
> supported by the device.

NAK. This table is intended to handle things other than the supported
generation -- I sent patches that add more fields but they're in some
review limbo state.
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Re: [Mesa-dev] [PATCH v2 mesa] vk/intel: use negative VK_NO_PROTOTYPES scheme

[Eric Engestrom]

On Mon, Apr 25, 2016 at 05:08:18PM +0100, Emil Velikov wrote:
> On 21 April 2016 at 11:24, Eric Engestrom  wrote:
> > Commit 3d0fac7aca237bbe8ed8e2a362d3b42d0ef8c46c changed all the
> > VK_PROTOTYPES to VK_NO_PROTOTYPES
> > This brings the Intel header in line with the rest of the Vulkan code.
> >
> > Signed-off-by: Eric Engestrom 
> Reviewed-by: Emil Velikov 
> 
> > ---
> >
> > This might break code that was using the old guard scheme (not sure how
> > that could've worked anyway).
> > What the policy on this?
> >
> > v2: rebase on top of 3caf2e89aa1711e80db80d2056e0a44663d9c7d2
> > ("anv: fix build without Wayland platform"). Should've done that the
> > first time around, sorry :]
> >
> >  include/vulkan/vulkan_intel.h  | 2 +-
> >  src/intel/vulkan/anv_private.h | 1 -
> >  2 files changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/include/vulkan/vulkan_intel.h b/include/vulkan/vulkan_intel.h
> > index 1f77128..8ede61b 100644
> > --- a/include/vulkan/vulkan_intel.h
> > +++ b/include/vulkan/vulkan_intel.h
> > @@ -44,7 +44,7 @@ typedef struct VkDmaBufImageCreateInfo_
> >
> >  typedef VkResult (VKAPI_PTR *PFN_vkCreateDmaBufImageINTEL)(VkDevice 
> > device, const VkDmaBufImageCreateInfo* pCreateInfo, const 
> > VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage);
> >
> > -#ifdef VK_PROTOTYPES
> > +#ifndef VK_NO_PROTOTYPES
> >
> Would be great to hear from the Intel guys, if there is a another
> Cannonical repo where this change should land first ?

CC'ing intel-gfx even though this isn't X-related, because I don't know
of any other way to contact you guys :]

> 
> Thanks
> Emil
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Re: [Mesa-dev] [PATCH 1/2] winsys/radeon: enlarge buffer_indices_hashlist

[Alex Deucher]

On Thu, Apr 28, 2016 at 2:05 PM, Marek Olšák  wrote:
> From: Bas Nieuwenhuizen 
>
> Enlarge the buffer hashlist to prevent large numbers of misses
> due to adding more buffers than can be cached in the hashlist.
>
> Ported from winsys/amdgpu: 6373845d985d65c00f7c62b793e67ae5106eabff

Series is:
Reviewed-by: Alex Deucher 

> ---
>  src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h 
> b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
> index c643b76..8056e72 100644
> --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
> +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
> @@ -51,7 +51,7 @@ struct radeon_cs_context {
>  struct drm_radeon_cs_reloc  *relocs;
>  uint64_t*priority_usage;
>
> -int reloc_indices_hashlist[512];
> +int reloc_indices_hashlist[4096];
>
>  uint64_tused_vram;
>  uint64_tused_gart;
> --
> 2.5.0
>
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Re: [Mesa-dev] [PATCH] swr: remove duplicated constant update code

[Cherniak, Bruce]

Reviewed-by: Bruce Cherniak   

> On Apr 28, 2016, at 11:18 AM, Tim Rowley  wrote:
> 
> ---
> src/gallium/drivers/swr/swr_state.cpp | 91 ++-
> 1 file changed, 47 insertions(+), 44 deletions(-)
> 
> diff --git a/src/gallium/drivers/swr/swr_state.cpp 
> b/src/gallium/drivers/swr/swr_state.cpp
> index 12916f6..a7ae9df 100644
> --- a/src/gallium/drivers/swr/swr_state.cpp
> +++ b/src/gallium/drivers/swr/swr_state.cpp
> @@ -724,6 +724,51 @@ swr_update_sampler_state(struct swr_context *ctx,
>}
> }
> 
> +static void
> +swr_update_constants(struct swr_context *ctx, enum pipe_shader_type 
> shaderType)
> +{
> +   swr_draw_context *pDC = >swrDC;
> +
> +   const float **constant;
> +   uint32_t *num_constants;
> +   struct swr_scratch_space *scratch;
> +
> +   switch (shaderType) {
> +   case PIPE_SHADER_VERTEX:
> +  constant = pDC->constantVS;
> +  num_constants = pDC->num_constantsVS;
> +  scratch = >scratch->vs_constants;
> +  break;
> +   case PIPE_SHADER_FRAGMENT:
> +  constant = pDC->constantFS;
> +  num_constants = pDC->num_constantsFS;
> +  scratch = >scratch->fs_constants;
> +  break;
> +   default:
> +  debug_printf("Unsupported shader type constants\n");
> +  return;
> +   }
> +
> +   for (UINT i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
> +  const pipe_constant_buffer *cb = >constants[shaderType][i];
> +  num_constants[i] = cb->buffer_size;
> +  if (cb->buffer) {
> + constant[i] =
> +(const float *)(swr_resource_data(cb->buffer) +
> +cb->buffer_offset);
> +  } else {
> + /* Need to copy these constants to scratch space */
> + if (cb->user_buffer && cb->buffer_size) {
> +const void *ptr =
> +   ((const uint8_t *)cb->user_buffer + cb->buffer_offset);
> +uint32_t size = AlignUp(cb->buffer_size, 4);
> +ptr = swr_copy_to_scratch_space(ctx, scratch, ptr, size);
> +constant[i] = (const float *)ptr;
> + }
> +  }
> +   }
> +}
> +
> void
> swr_update_derived(struct pipe_context *pipe,
>const struct pipe_draw_info *p_draw_info)
> @@ -1126,54 +1171,12 @@ swr_update_derived(struct pipe_context *pipe,
> 
>/* VertexShader Constants */
>if (ctx->dirty & SWR_NEW_VSCONSTANTS) {
> -  swr_draw_context *pDC = >swrDC;
> -
> -  for (UINT i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
> - const pipe_constant_buffer *cb =
> ->constants[PIPE_SHADER_VERTEX][i];
> - pDC->num_constantsVS[i] = cb->buffer_size;
> - if (cb->buffer)
> -pDC->constantVS[i] =
> -   (const float *)(swr_resource_data(cb->buffer) +
> -   cb->buffer_offset);
> - else {
> -/* Need to copy these constants to scratch space */
> -if (cb->user_buffer && cb->buffer_size) {
> -   const void *ptr =
> -  ((const uint8_t *)cb->user_buffer + cb->buffer_offset);
> -   uint32_t size = AlignUp(cb->buffer_size, 4);
> -   ptr = swr_copy_to_scratch_space(
> -  ctx, >scratch->vs_constants, ptr, size);
> -   pDC->constantVS[i] = (const float *)ptr;
> -}
> - }
> -  }
> +  swr_update_constants(ctx, PIPE_SHADER_VERTEX);
>}
> 
>/* FragmentShader Constants */
>if (ctx->dirty & SWR_NEW_FSCONSTANTS) {
> -  swr_draw_context *pDC = >swrDC;
> -
> -  for (UINT i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
> - const pipe_constant_buffer *cb =
> ->constants[PIPE_SHADER_FRAGMENT][i];
> - pDC->num_constantsFS[i] = cb->buffer_size;
> - if (cb->buffer)
> -pDC->constantFS[i] =
> -   (const float *)(swr_resource_data(cb->buffer) +
> -   cb->buffer_offset);
> - else {
> -/* Need to copy these constants to scratch space */
> -if (cb->user_buffer && cb->buffer_size) {
> -   const void *ptr =
> -  ((const uint8_t *)cb->user_buffer + cb->buffer_offset);
> -   uint32_t size = AlignUp(cb->buffer_size, 4);
> -   ptr = swr_copy_to_scratch_space(
> -  ctx, >scratch->fs_constants, ptr, size);
> -   pDC->constantFS[i] = (const float *)ptr;
> -}
> - }
> -  }
> +  swr_update_constants(ctx, PIPE_SHADER_FRAGMENT);
>}
> 
>/* Depth/stencil state */
> -- 
> 1.9.1
> 
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[Mesa-dev] [PATCH 1/2] winsys/radeon: enlarge buffer_indices_hashlist

[Marek Olšák]

From: Bas Nieuwenhuizen 

Enlarge the buffer hashlist to prevent large numbers of misses
due to adding more buffers than can be cached in the hashlist.

Ported from winsys/amdgpu: 6373845d985d65c00f7c62b793e67ae5106eabff
---
 src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h 
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
index c643b76..8056e72 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
@@ -51,7 +51,7 @@ struct radeon_cs_context {
 struct drm_radeon_cs_reloc  *relocs;
 uint64_t*priority_usage;
 
-int reloc_indices_hashlist[512];
+int reloc_indices_hashlist[4096];
 
 uint64_tused_vram;
 uint64_tused_gart;
-- 
2.5.0

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[Mesa-dev] [PATCH 2/2] gallium/radeon: add the size only once in r600_context_add_resource_size

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_pipe_common.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 929fecb..8649bbc 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -353,12 +353,10 @@ void r600_context_add_resource_size(struct pipe_context 
*ctx, struct pipe_resour
 * In practice this gave very good estimate (+/- 10% of the target
 * memory limit).
 */
-   if (rr->domains & RADEON_DOMAIN_GTT) {
-   rctx->gtt += rr->buf->size;
-   }
-   if (rr->domains & RADEON_DOMAIN_VRAM) {
+   if (rr->domains & RADEON_DOMAIN_VRAM)
rctx->vram += rr->buf->size;
-   }
+   else if (rr->domains & RADEON_DOMAIN_GTT)
+   rctx->gtt += rr->buf->size;
 }
 
 /*
-- 
2.5.0

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[Mesa-dev] [Bug 92850] Segfault loading War Thunder

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=92850

--- Comment #69 from Nicolai Hähnle  ---
bellamorte, feel free to bring this issue to the attention of the gcc and Clang
people. It's kind of borderline between a bug and a misfeature.

The ::visit method was really huge and got a lot of functions inlined, and it's
possible that gcc could do a better job at aliasing the additional stack
variables, though I didn't bother to investigate in detail.

For Mesa, the pragmatic thing is clearly to just work around it :)

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Re: [Mesa-dev] [RFC PATCH] winsys/radeon: drop support for kernels lacking tile mode array queries

[Nicolai Hähnle]

Given Emil's tentative release plan, 3.13 will be almost two and half 
years old by the time this is released - seems fair to me.


Reviewed-by: Nicolai Hähnle 

On 28.04.2016 08:21, Marek Olšák wrote:

From: Marek Olšák 

This will allow us to simplify a lot of code around tiling.

Kernel 3.10 is required for SI.
Kernel 3.13 is required for CIK.
---
  src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 20 ++--
  1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 2d9ec8c..702d073 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -504,14 +504,22 @@ static boolean do_winsys_init(struct radeon_drm_winsys 
*ws)
  return FALSE;
  }

-if (radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
- ws->info.si_tile_mode_array)) {
-ws->info.si_tile_mode_array_valid = TRUE;
+if (ws->info.chip_class == CIK) {
+if (!radeon_get_drm_value(ws->fd, 
RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
+  ws->info.cik_macrotile_mode_array)) {
+fprintf(stderr, "radeon: Kernel 3.13 is required for CIK 
support.\n");
+return FALSE;
+}
+ws->info.cik_macrotile_mode_array_valid = TRUE;
  }

-if (radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, 
NULL,
- ws->info.cik_macrotile_mode_array)) {
-ws->info.cik_macrotile_mode_array_valid = TRUE;
+if (ws->info.chip_class >= SI) {
+if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
+  ws->info.si_tile_mode_array)) {
+fprintf(stderr, "radeon: Kernel 3.10 is required for SI 
support.\n");
+return FALSE;
+}
+ws->info.si_tile_mode_array_valid = TRUE;
  }

  /* Hawaii with old firmware needs type2 nop packet.


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Re: [Mesa-dev] [PATCH] radeonsi: rework clear_buffer flags

[Nicolai Hähnle]

LGTM.

Reviewed-by: Nicolai Hähnle 

On 28.04.2016 07:54, Marek Olšák wrote:

From: Marek Olšák 

Changes:
- don't flush DB for fast color clears
- don't flush any caches for initial clears
- remove the flag from si_copy_buffer, always assume shader coherency
---
  src/gallium/drivers/r600/r600_blit.c  |  2 +-
  src/gallium/drivers/radeon/r600_pipe_common.c |  4 +--
  src/gallium/drivers/radeon/r600_pipe_common.h | 10 +--
  src/gallium/drivers/radeon/r600_texture.c | 11 
  src/gallium/drivers/radeon/radeon_video.c |  2 +-
  src/gallium/drivers/radeonsi/si_blit.c|  5 ++--
  src/gallium/drivers/radeonsi/si_cp_dma.c  | 38 ---
  src/gallium/drivers/radeonsi/si_pipe.c|  3 ++-
  src/gallium/drivers/radeonsi/si_pipe.h|  3 +--
  9 files changed, 46 insertions(+), 32 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_blit.c 
b/src/gallium/drivers/r600/r600_blit.c
index 2d30807..ed67cb8 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -582,7 +582,7 @@ static void r600_copy_global_buffer(struct pipe_context 
*ctx,

  static void r600_clear_buffer(struct pipe_context *ctx, struct pipe_resource 
*dst,
  uint64_t offset, uint64_t size, unsigned value,
- bool is_framebuffer)
+ enum r600_coherency coher)
  {
struct r600_context *rctx = (struct r600_context*)ctx;

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 929fecb..823ba46 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -984,12 +984,12 @@ bool r600_can_dump_shader(struct r600_common_screen 
*rscreen,

  void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct 
pipe_resource *dst,
  uint64_t offset, uint64_t size, unsigned value,
- bool is_framebuffer)
+ enum r600_coherency coher)
  {
struct r600_common_context *rctx = (struct 
r600_common_context*)rscreen->aux_context;

pipe_mutex_lock(rscreen->aux_context_lock);
-   rctx->clear_buffer(>b, dst, offset, size, value, is_framebuffer);
+   rctx->clear_buffer(>b, dst, offset, size, value, coher);
rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
pipe_mutex_unlock(rscreen->aux_context_lock);
  }
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index d7478ef..74eefbb 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -100,6 +100,12 @@
  #define R600_MAP_BUFFER_ALIGNMENT 64
  #define R600_MAX_VIEWPORTS16

+enum r600_coherency {
+   R600_COHERENCY_NONE, /* no cache flushes needed */
+   R600_COHERENCY_SHADER,
+   R600_COHERENCY_CB_META,
+};
+
  #ifdef PIPE_ARCH_BIG_ENDIAN
  #define R600_BIG_ENDIAN 1
  #else
@@ -513,7 +519,7 @@ struct r600_common_context {

void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource 
*dst,
 uint64_t offset, uint64_t size, unsigned value,
-bool is_framebuffer);
+enum r600_coherency coher);

void (*blit_decompress_depth)(struct pipe_context *ctx,
  struct r600_texture *texture,
@@ -584,7 +590,7 @@ bool r600_can_dump_shader(struct r600_common_screen 
*rscreen,
  unsigned processor);
  void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct 
pipe_resource *dst,
  uint64_t offset, uint64_t size, unsigned value,
- bool is_framebuffer);
+ enum r600_coherency coher);
  struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
  const struct pipe_resource 
*templ);
  const char *r600_get_llvm_processor_name(enum radeon_family family);
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 7e58490..41bc48a 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -717,7 +717,7 @@ static void r600_texture_allocate_htile(struct 
r600_common_screen *rscreen,
R600_ERR("Failed to create buffer object for htile buffer.\n");
} else {
r600_screen_clear_buffer(rscreen, >htile_buffer->b.b, 0,
-htile_size, 0, true);
+htile_size, 0, R600_COHERENCY_NONE);
}
  }

@@ -892,13 +892,13 @@ r600_texture_create_object(struct pipe_screen *screen,
/* Initialize the cmask to 

Re: [Mesa-dev] [PATCH 1/4] nir: Avoid C99 field initializers.

[Jason Ekstrand]

On Thu, Apr 28, 2016 at 8:49 AM, Jose Fonseca  wrote:

> On 28/04/16 15:37, Connor Abbott wrote:
>
>> For the series:
>>
>> Reviewed-by: Connor Abbott 
>>
>> For the zero-sized array thing... we could make it a statically-sized
>> array, since we never have more than 4 arguments to an ALU
>> instruction, but that would be wasteful of memory. Also, we always
>> have at least 1 argument, so we could make the size 1 to shut up the
>> warning, but that would be more confusing and introduce undefined
>> behavior in C99 that the compiler is likely to actually take advantage
>> of. I don't see any options better than just accepting the warning
>> and/or shutting that specific warning off.
>>
>
> I feared so.  Thanks for looking into it though.
>

Can you be a bit more specific about the issues that MSVC has with
zero-length arrays?  Can it "accept nir_src src[0]" instead of "src[]"?


> Jose
>
>
>
>>
>> On Thu, Apr 28, 2016 at 7:27 AM, Jose Fonseca 
>> wrote:
>>
>>> As they are not standard C++ and are not supported by MSVC C++ compiler.
>>>
>>> Just have nir_imm_double match nir_imm_float above.
>>> ---
>>>   src/compiler/nir/nir_builder.h | 9 ++---
>>>   1 file changed, 6 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/src/compiler/nir/nir_builder.h
>>> b/src/compiler/nir/nir_builder.h
>>> index a14f9ef..4fa9779 100644
>>> --- a/src/compiler/nir/nir_builder.h
>>> +++ b/src/compiler/nir/nir_builder.h
>>> @@ -117,9 +117,12 @@ nir_imm_float(nir_builder *build, float x)
>>>   static inline nir_ssa_def *
>>>   nir_imm_double(nir_builder *build, double x)
>>>   {
>>> -   nir_const_value v = { { .f64 = {x, 0, 0, 0} } };
>>> -   nir_ssa_def *def = nir_build_imm(build, 1, 64, v);
>>> -   return def;
>>> +   nir_const_value v;
>>> +
>>> +   memset(, 0, sizeof(v));
>>> +   v.f64[0] = x;
>>> +
>>> +   return nir_build_imm(build, 1, 64, v);
>>>   }
>>>
>>>   static inline nir_ssa_def *
>>> --
>>> 2.5.0
>>>
>>>
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Re: [Mesa-dev] [PATCH 02/13] nir/builder: Add bit_size info to nir_build_imm()

[Mark Janes]

Hi Samuel,

When this patch was pushed, it broke the vulkan build.  Can you please
add "--with-vulkan-drivers=intel" to the build-test that you run before
pushing?

thanks,

Mark

Samuel Iglesias Gonsálvez  writes:

> Signed-off-by: Samuel Iglesias Gonsálvez 
> ---
>  src/compiler/nir/nir_builder.h | 15 ---
>  src/compiler/nir/nir_lower_system_values.c |  2 +-
>  src/compiler/nir/nir_lower_tex.c   |  2 +-
>  3 files changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
> index 38a1cf7..84fc9bf 100644
> --- a/src/compiler/nir/nir_builder.h
> +++ b/src/compiler/nir/nir_builder.h
> @@ -89,10 +89,11 @@ nir_ssa_undef(nir_builder *build, unsigned 
> num_components, unsigned bit_size)
>  }
>  
>  static inline nir_ssa_def *
> -nir_build_imm(nir_builder *build, unsigned num_components, nir_const_value 
> value)
> +nir_build_imm(nir_builder *build, unsigned num_components,
> +  nir_const_value value, unsigned bit_size)
>  {
> nir_load_const_instr *load_const =
> -  nir_load_const_instr_create(build->shader, num_components, 32);
> +  nir_load_const_instr_create(build->shader, num_components, bit_size);
> if (!load_const)
>return NULL;
>  
> @@ -111,7 +112,7 @@ nir_imm_float(nir_builder *build, float x)
> memset(, 0, sizeof(v));
> v.f32[0] = x;
>  
> -   return nir_build_imm(build, 1, v);
> +   return nir_build_imm(build, 1, v, 32);
>  }
>  
>  static inline nir_ssa_def *
> @@ -125,7 +126,7 @@ nir_imm_vec4(nir_builder *build, float x, float y, float 
> z, float w)
> v.f32[2] = z;
> v.f32[3] = w;
>  
> -   return nir_build_imm(build, 4, v);
> +   return nir_build_imm(build, 4, v, 32);
>  }
>  
>  static inline nir_ssa_def *
> @@ -136,7 +137,7 @@ nir_imm_int(nir_builder *build, int x)
> memset(, 0, sizeof(v));
> v.i32[0] = x;
>  
> -   return nir_build_imm(build, 1, v);
> +   return nir_build_imm(build, 1, v, 32);
>  }
>  
>  static inline nir_ssa_def *
> @@ -150,14 +151,14 @@ nir_imm_ivec4(nir_builder *build, int x, int y, int z, 
> int w)
> v.i32[2] = z;
> v.i32[3] = w;
>  
> -   return nir_build_imm(build, 4, v);
> +   return nir_build_imm(build, 4, v, 32);
>  }
>  
>  static inline nir_ssa_def *
>  nir_imm_uint(nir_builder *build, unsigned x)
>  {
> nir_const_value v = { { .u32 = {x, 0, 0, 0} } };
> -   return nir_build_imm(build, 1, v);
> +   return nir_build_imm(build, 1, v, 32);
>  }
>  
>  static inline nir_ssa_def *
> diff --git a/src/compiler/nir/nir_lower_system_values.c 
> b/src/compiler/nir/nir_lower_system_values.c
> index 2d3ccd7..8362619 100644
> --- a/src/compiler/nir/nir_lower_system_values.c
> +++ b/src/compiler/nir/nir_lower_system_values.c
> @@ -75,7 +75,7 @@ convert_block(nir_block *block, void *void_state)
>  nir_load_system_value(b, nir_intrinsic_load_local_invocation_id, 
> 0);
>  
>   sysval = nir_iadd(b, nir_imul(b, group_id,
> -  nir_build_imm(b, 3, local_size)),
> +  nir_build_imm(b, 3, local_size, 
> 32)),
>local_id);
>   break;
>}
> diff --git a/src/compiler/nir/nir_lower_tex.c 
> b/src/compiler/nir/nir_lower_tex.c
> index 4999603..47a3786 100644
> --- a/src/compiler/nir/nir_lower_tex.c
> +++ b/src/compiler/nir/nir_lower_tex.c
> @@ -232,7 +232,7 @@ get_zero_or_one(nir_builder *b, nir_alu_type type, 
> uint8_t swizzle_val)
>   v.u32[0] = v.u32[1] = v.u32[2] = v.u32[3] = 1;
> }
>  
> -   return nir_build_imm(b, 4, v);
> +   return nir_build_imm(b, 4, v, 32);
>  }
>  
>  static void
> -- 
> 2.5.0
>
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Re: [Mesa-dev] [android-x86-devel] [RFC 0/7] android: enable llvmpipe for software rendering

[Roland Scheidegger]

Am 28.04.2016 um 17:52 schrieb Chih-Wei Huang:
> I clearly understand this point.
> Actually I've spent several days to try to
> make it work on the master branch.
> That's why it was delayed -- I supposed to send them
> in the last week.
> > However, the master branch is always broken for android.
> There are a lot of build break I need to fix and workaround
> or I can't test it. After fixed all the errors and built it OK,
> however, it didn't work as expected.
> The system boots to Home but all display is garbled.
> I'm not sure if I made some mistakes on
> fixing the building errors or there are some changes
> that really broke these patches.
> (the latest commit I've tried in the master is 32cb7d61)
> I finally decide to give it up and send them as the current status.
> (otherwise it will take too much of my time and delay
> my other pending tasks)
> 
> Unfortunately the situation is most mesa developers
> don't care android so they usually break android build
> or functions. Unless the situation is changed it's very hard
> for us to follow the master branch closely.

I suppose if it's possible to set up some build bot for it which sends
out emails complaining when it breaks that would help with the build
failures.
That wouldn't of course help with bugs which aren't build breaking -
you'd have to use master branch for your testing (because as you noted,
noone else will, so if you don't you will always notice bugs too late
making them much harder to track down).

Roland

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[Mesa-dev] [PATCH] swr: Remove stall waiting for core query counters.

[BruceCherniak]

When gathering query results, swr_gather_stats was
unnecessarily stalling the entire pipeline.  Results are now
collected asynchronously, with a fence marking completion.
---
 src/gallium/drivers/swr/swr_fence.cpp |6 -
 src/gallium/drivers/swr/swr_fence.h   |8 ++
 src/gallium/drivers/swr/swr_query.cpp |  180 -
 src/gallium/drivers/swr/swr_query.h   |   11 ++-
 4 files changed, 81 insertions(+), 124 deletions(-)

diff --git a/src/gallium/drivers/swr/swr_fence.cpp 
b/src/gallium/drivers/swr/swr_fence.cpp
index 2e95b39..8a8e864 100644
--- a/src/gallium/drivers/swr/swr_fence.cpp
+++ b/src/gallium/drivers/swr/swr_fence.cpp
@@ -105,12 +105,6 @@ swr_fence_reference(struct pipe_screen *screen,
   swr_fence_destroy(old);
 }
 
-static INLINE boolean
-swr_is_fence_done(struct pipe_fence_handle *fence_handle)
-{
-   struct swr_fence *fence = swr_fence(fence_handle);
-   return (fence->read == fence->write);
-}
 
 /*
  * Wait for the fence to finish.
diff --git a/src/gallium/drivers/swr/swr_fence.h 
b/src/gallium/drivers/swr/swr_fence.h
index df3776e..47f4d2e 100644
--- a/src/gallium/drivers/swr/swr_fence.h
+++ b/src/gallium/drivers/swr/swr_fence.h
@@ -45,6 +45,14 @@ swr_fence(struct pipe_fence_handle *fence)
return (struct swr_fence *)fence;
 }
 
+
+static INLINE boolean
+swr_is_fence_done(struct pipe_fence_handle *fence_handle)
+{
+   struct swr_fence *fence = swr_fence(fence_handle);
+   return (fence->read == fence->write);
+}
+
 static INLINE boolean
 swr_is_fence_pending(struct pipe_fence_handle *fence_handle)
 {
diff --git a/src/gallium/drivers/swr/swr_query.cpp 
b/src/gallium/drivers/swr/swr_query.cpp
index f038a6e..5c59965 100644
--- a/src/gallium/drivers/swr/swr_query.cpp
+++ b/src/gallium/drivers/swr/swr_query.cpp
@@ -62,10 +62,8 @@ swr_destroy_query(struct pipe_context *pipe, struct 
pipe_query *q)
struct swr_query *pq = swr_query(q);
 
if (pq->fence) {
-  if (!swr_is_fence_pending(pq->fence)) {
- swr_fence_submit(swr_context(pipe), pq->fence);
+  if (swr_is_fence_pending(pq->fence))
  swr_fence_finish(pipe->screen, pq->fence, 0);
-  }
   swr_fence_reference(pipe->screen, >fence, NULL);
}
 
@@ -73,100 +71,45 @@ swr_destroy_query(struct pipe_context *pipe, struct 
pipe_query *q)
 }
 
 
-// XXX Create a fence callback, rather than stalling SwrWaitForIdle
 static void
 swr_gather_stats(struct pipe_context *pipe, struct swr_query *pq)
 {
struct swr_context *ctx = swr_context(pipe);
 
assert(pq->result);
-   union pipe_query_result *result = pq->result;
+   struct swr_query_result *result = pq->result;
boolean enable_stats = pq->enable_stats;
-   SWR_STATS swr_stats = {0};
-
-   if (pq->fence) {
-  if (!swr_is_fence_pending(pq->fence)) {
- swr_fence_submit(ctx, pq->fence);
- swr_fence_finish(pipe->screen, pq->fence, 0);
-  }
-  swr_fence_reference(pipe->screen, >fence, NULL);
-   }
 
-   /*
-* These queries don't need SWR Stats enabled in the core
-* Set and return.
-*/
+   /* A few results don't require the core, so don't involve it */
switch (pq->type) {
case PIPE_QUERY_TIMESTAMP:
case PIPE_QUERY_TIME_ELAPSED:
-  result->u64 = swr_get_timestamp(pipe->screen);
-  return;
+  result->timestamp = swr_get_timestamp(pipe->screen);
   break;
case PIPE_QUERY_TIMESTAMP_DISJOINT:
-  /* nothing to do here */
-  return;
-  break;
case PIPE_QUERY_GPU_FINISHED:
-  result->b = TRUE; /* XXX TODO Add an api func to SWR to compare drawId
-   vs LastRetiredId? */
-  return;
+  /* nothing to do here */
   break;
default:
-  /* Any query that needs SwrCore stats */
-  break;
-   }
-
-   /*
-* All other results are collected from SwrCore counters
-*/
+  /*
+   * All other results are collected from SwrCore counters via
+   * SwrGetStats. This returns immediately, but results are later filled
+   * in by the backend.  Fence status is the only indication of
+   * completion.  */
+  SwrGetStats(ctx->swrContext, >core);
+
+  if (!pq->fence) {
+ struct swr_screen *screen = swr_screen(pipe->screen);
+ swr_fence_reference(pipe->screen, >fence, screen->flush_fence);
+  }
+  swr_fence_submit(ctx, pq->fence);
 
-   /* XXX, Should turn this into a fence callback and skip the stall */
-   SwrGetStats(ctx->swrContext, _stats);
-   /* SwrGetStats returns immediately, wait for collection */
-   SwrWaitForIdle(ctx->swrContext);
+  /* Only change stat collection if there are no active queries */
+  if (ctx->active_queries == 0)
+ SwrEnableStats(ctx->swrContext, enable_stats);
 
-   switch (pq->type) {
-   case PIPE_QUERY_OCCLUSION_PREDICATE:
-   case PIPE_QUERY_OCCLUSION_COUNTER:
-  result->u64 = swr_stats.DepthPassCount;
-  break;
-   case PIPE_QUERY_PRIMITIVES_GENERATED:
-  result->u64 = swr_stats.IaPrimitives;
-  

Re: [Mesa-dev] [PATCH 2/6] nir: Switch the arguments to nir_foreach_phi_src

[Jason Ekstrand]

On Thu, Apr 28, 2016 at 12:10 AM, Ian Romanick  wrote:

> On 04/27/2016 07:39 PM, Jason Ekstrand wrote:
> > On Wed, Apr 27, 2016 at 12:54 AM, Ian Romanick  > > wrote:
> >
> > On 04/27/2016 05:41 AM, Jason Ekstrand wrote:
> > > This matches the "foreach x in container" pattern found in many
> other
> > > programming languages.  Generated by the following regular
> expression:
> > >
> > >
> >
>  s/nir_foreach_phi_src(\([^,]*\),\s*\([^,]*\))/nir_foreach_phi_src(\2, \1)/
> > >
> > > and a similar expression for nir_foreach_phi_src_safe.
> > > ---
> > >  src/compiler/nir/nir.c| 2 +-
> > >  src/compiler/nir/nir.h| 8
> > 
> > >  src/compiler/nir/nir_control_flow.c   | 4 ++--
> > >  src/compiler/nir/nir_from_ssa.c   | 4 ++--
> > >  src/compiler/nir/nir_instr_set.c  | 6
> +++---
> > >  src/compiler/nir/nir_liveness.c   | 2 +-
> > >  src/compiler/nir/nir_lower_phis_to_scalar.c   | 4 ++--
> > >  src/compiler/nir/nir_opt_dead_cf.c| 2 +-
> > >  src/compiler/nir/nir_opt_gcm.c| 2 +-
> > >  src/compiler/nir/nir_opt_peephole_select.c| 2 +-
> > >  src/compiler/nir/nir_opt_remove_phis.c| 2 +-
> > >  src/compiler/nir/nir_print.c  | 2 +-
> > >  src/compiler/nir/nir_to_ssa.c | 2 +-
> > >  src/compiler/nir/nir_validate.c   | 2 +-
> > >  src/gallium/drivers/freedreno/ir3/ir3_nir_lower_if_else.c | 2 +-
> > >  15 files changed, 23 insertions(+), 23 deletions(-)
> > >
> > > diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
> > > index 6c1b129..4c283ef 100644
> > > --- a/src/compiler/nir/nir.c
> > > +++ b/src/compiler/nir/nir.c
> > > @@ -1162,7 +1162,7 @@ visit_load_const_src(nir_load_const_instr
> > *instr, nir_foreach_src_cb cb,
> > >  static bool
> > >  visit_phi_src(nir_phi_instr *instr, nir_foreach_src_cb cb, void
> > *state)
> > >  {
> > > -   nir_foreach_phi_src(instr, src) {
> > > +   nir_foreach_phi_src(src, instr) {
> > >if (!visit_src(>src, cb, state))
> > >   return false;
> > > }
> > > diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> > > index 113073f..ee6abdd 100644
> > > --- a/src/compiler/nir/nir.h
> > > +++ b/src/compiler/nir/nir.h
> > > @@ -1304,10 +1304,10 @@ typedef struct {
> > > nir_src src;
> > >  } nir_phi_src;
> > >
> > > -#define nir_foreach_phi_src(phi, entry) \
> > > -   foreach_list_typed(nir_phi_src, entry, node, &(phi)->srcs)
> > > -#define nir_foreach_phi_src_safe(phi, entry) \
> > > -   foreach_list_typed_safe(nir_phi_src, entry, node, &(phi)->srcs)
> >
> > Should the macro be renamed nir_foreach_src_phi?  That way the words
> in
> > the name match the order of the parameters.  That also makes the name
> > (almost) short for "for each source in phi".  Maybe
> > nir_foreach_src_in_phi?  I think Matt previously nixed having "in" in
> > these macro names, so I don't want to reopen a previously closed can
> of
> > worms.
> >
> >
> > That's a good question and I'm glad you asked it.  Short version: I
> > don't know.  I'll give it some thought.
> >
> > Slightly longer version:  The current naming scheme for the foreach
> > macros is that nir_foreach_foo iterates over things of type nir_foo so
> > nir_foreach_variable is for nir_variable, nir_foreach_block is for
> > nir_block, and nir_foreach_phi_src is for nir_phi_src.  The fact that
> > it's called nir_foreach_phi_src and walks over every source in a phi is
> > kind of an accident.
>
> Ah.  I didn't realize it was iterating a phi_src.  I was just looking at
> the names of the parameters.  Maybe changing the parameter names to
> (phi_src, phi) would make it more obvious to newbs.


Consider it done.


>   *shrug*  Now that
> you've explained it, the macro name is fine with me as is.
>
> > On the other hand, you're absolutely write that it does look a lot like
> > "foreach src in phi" which would also be perfectly sensible.  To be
> > honest, I've never thought about it that way; I've always read it as
> > "foreach phi_src" so this is a thought that has never occured to me.
> >
> > I'll give it a bit more thought.  I think I still have a very slight
> > leaning towards keeping it named the way it is but I'll think about it a
> > bit more.  I could also be easily swayed by someone with a strong
> > opinion. ;-)
> >
> >
> > > +#define nir_foreach_phi_src(src, phi) \
> > > +   foreach_list_typed(nir_phi_src, src, node, &(phi)->srcs)
> > > +#define 

Re: [Mesa-dev] [PATCH] gallium/radeon: drop support for LINEAR_GENERAL layout

[Alex Deucher]

On Thu, Apr 28, 2016 at 8:58 AM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> Unused. All texture imports use LINEAR_ALIGNED regardless of what
> the DDX does.

Reviewed-by: Alex Deucher 

> ---
>  src/gallium/drivers/r600/evergreen_state.c | 33 
> +-
>  src/gallium/drivers/r600/r600_state.c  | 33 
> ++
>  src/gallium/drivers/radeon/radeon_winsys.h |  1 -
>  src/gallium/drivers/radeonsi/cik_sdma.c| 12 +++---
>  src/gallium/drivers/radeonsi/si_dma.c  |  8 +--
>  src/gallium/drivers/radeonsi/si_state.c| 18 +++---
>  src/gallium/winsys/amdgpu/drm/amdgpu_surface.c |  6 -
>  7 files changed, 20 insertions(+), 91 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/evergreen_state.c 
> b/src/gallium/drivers/r600/evergreen_state.c
> index eec567c..5224e42 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -35,13 +35,12 @@
>  static inline unsigned evergreen_array_mode(unsigned mode)
>  {
> switch (mode) {
> +   default:
> case RADEON_SURF_MODE_LINEAR_ALIGNED:   return 
> V_028C70_ARRAY_LINEAR_ALIGNED;
> break;
> case RADEON_SURF_MODE_1D:   return 
> V_028C70_ARRAY_1D_TILED_THIN1;
> break;
> case RADEON_SURF_MODE_2D:   return 
> V_028C70_ARRAY_2D_TILED_THIN1;
> -   default:
> -   case RADEON_SURF_MODE_LINEAR:   return 
> V_028C70_ARRAY_LINEAR_GENERAL;
> }
>  }
>
> @@ -758,6 +757,7 @@ evergreen_create_sampler_view_custom(struct pipe_context 
> *ctx,
> non_disp_tiling = tmp->non_disp_tiling;
>
> switch (surflevel[base_level].mode) {
> +   default:
> case RADEON_SURF_MODE_LINEAR_ALIGNED:
> array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
> break;
> @@ -767,10 +767,6 @@ evergreen_create_sampler_view_custom(struct pipe_context 
> *ctx,
> case RADEON_SURF_MODE_1D:
> array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
> break;
> -   case RADEON_SURF_MODE_LINEAR:
> -   default:
> -   array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
> -   break;
> }
> macro_aspect = tmp->surface.mtilea;
> bankw = tmp->surface.bankw;
> @@ -1006,14 +1002,8 @@ void evergreen_init_color_surface(struct r600_context 
> *rctx,
> bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
>
> offset = rtex->surface.level[level].offset;
> -   if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
> -   assert(surf->base.u.tex.first_layer == 
> surf->base.u.tex.last_layer);
> -   offset += rtex->surface.level[level].slice_size *
> - surf->base.u.tex.first_layer;
> -   color_view = 0;
> -   } else
> -   color_view = 
> S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
> -S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
> +   color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
> +S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
>
> pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
> slice = (rtex->surface.level[level].nblk_x * 
> rtex->surface.level[level].nblk_y) / 64;
> @@ -1022,6 +1012,7 @@ void evergreen_init_color_surface(struct r600_context 
> *rctx,
> }
> color_info = 0;
> switch (rtex->surface.level[level].mode) {
> +   default:
> case RADEON_SURF_MODE_LINEAR_ALIGNED:
> color_info = 
> S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
> non_disp_tiling = 1;
> @@ -1034,11 +1025,6 @@ void evergreen_init_color_surface(struct r600_context 
> *rctx,
> color_info = 
> S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
> non_disp_tiling = rtex->non_disp_tiling;
> break;
> -   case RADEON_SURF_MODE_LINEAR:
> -   default:
> -   color_info = 
> S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
> -   non_disp_tiling = 1;
> -   break;
> }
> tile_split = rtex->surface.tile_split;
> macro_aspect = rtex->surface.mtilea;
> @@ -1201,7 +1187,6 @@ static void evergreen_init_depth_surface(struct 
> r600_context *rctx,
> break;
> case RADEON_SURF_MODE_1D:
> case RADEON_SURF_MODE_LINEAR_ALIGNED:
> -   case RADEON_SURF_MODE_LINEAR:
> default:
> array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
> break;
> @@ -3391,9 +3376,6 @@ static void evergreen_dma_copy_tile(struct r600_context 
> *rctx,
>
> dst_mode = rdst->surface.level[dst_level].mode;
> src_mode = rsrc->surface.level[src_level].mode;
> -   /* downcast 

[Mesa-dev] [AppVeyor] mesa master #1093 completed

[AppVeyor]

Build mesa 1093 completed



Commit 99474dc29b by Jose Fonseca on 4/28/2016 11:25 AM:

nir: Try to warn when C99 extensions are used in nir headers.\n\nIdeally we'd have nir.h being included with -Wpedantic too, but it fails\nwith:\n\nsrc/compiler/nir/nir.h:754:20: warning: ISO C++ forbids zero-size array ‘src’ [-Wpedantic]\nnir_alu_src src[];\n^\nIn file included from src/compiler/nir/glsl_to_nir.cpp:42:0:\nsrc/compiler/nir/nir.h:919:16: warning: ISO C++ forbids zero-size array ‘src’ [-Wpedantic]\nnir_src src[];\n\nReviewed-by: Connor Abbott 


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Re: [Mesa-dev] [RFC 3/7] gallium/swrast: fix dri_sw_dt->data free func not matching alloc func

[Jose Fonseca]

On 28/04/16 08:34, Chih-Wei Huang wrote:

From: WuZhen 

The old code causes crashes when using software rendering.

NO_REF_TASK
tested: local run

Change-Id: Ib1d7f36b9f25ccc13afdd28d1e34f76162d3
Signed-off-by: Chih-Wei Huang 
---
  src/gallium/winsys/sw/dri/dri_sw_winsys.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/winsys/sw/dri/dri_sw_winsys.c 
b/src/gallium/winsys/sw/dri/dri_sw_winsys.c
index 5c98f26..94d5092 100644
--- a/src/gallium/winsys/sw/dri/dri_sw_winsys.c
+++ b/src/gallium/winsys/sw/dri/dri_sw_winsys.c
@@ -125,7 +125,7 @@ dri_sw_displaytarget_destroy(struct sw_winsys *ws,
  {
 struct dri_sw_displaytarget *dri_sw_dt = dri_sw_displaytarget(dt);

-   FREE(dri_sw_dt->data);
+   align_free(dri_sw_dt->data);

 FREE(dri_sw_dt);
  }



Reviewed-by: Jose Fonseca 

It doesn't affect Android, but 
src/gallium/winsys/sw/xlib/xlib_sw_winsys.c has the same FREE  / 
align_free mismatch:


diff --git a/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c 
b/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c

index cc2a3de..8753139 100644
--- a/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c
+++ b/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c
@@ -268,7 +268,7 @@ xlib_displaytarget_destroy(struct sw_winsys *ws,
 xlib_dt->tempImage->data = NULL;
   }
   else {
- FREE(xlib_dt->data);
+ align_free(xlib_dt->data);
  if (xlib_dt->tempImage && xlib_dt->tempImage->data == 
xlib_dt->data) {

 xlib_dt->tempImage->data = NULL;
  }


I didn't spot others.

Changes to both files should be cross ported to stable branches.

Jose
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Re: [Mesa-dev] [android-x86-devel] [RFC 0/7] android: enable llvmpipe for software rendering

[Chih-Wei Huang]

2016-04-28 22:22 GMT+08:00 Emil Velikov :
> Hi Chih-Wei,
>
> Thanks for getting these out to the community.
>
> On 28 April 2016 at 08:34, Chih-Wei Huang  wrote:
>> This is a series of patches developed by Jide Technolody to enable
>> the llvmpipe for software rendering of Android.
>> It makes a device without a Mesa supported GPU could run most modern
>> Android apps.
>>
> Afaict one should only need the extra Android.mk files to get llvmpipe
> considering that softpipe already works.
> Have you/the Jide folks tried the latter already ? Does it work
> without these patches ?

Hmm, interesting point.
Did you mean just adding Android.mk for llvmpipe
is enough?

>> These patches are mainly developed and tested on the 11.0 and 11.2
>> branches. They might not work with the Mesa master branch.
>>
> Humble request - please always aim for master. Doing this will get you
> the latest stable branch for free.
> If you're targeting some old stable branch then you'll will have to
> duplicate the effort to land things in master. And new functionality
> goes _only_ in master

I clearly understand this point.
Actually I've spent several days to try to
make it work on the master branch.
That's why it was delayed -- I supposed to send them
in the last week.

However, the master branch is always broken for android.
There are a lot of build break I need to fix and workaround
or I can't test it. After fixed all the errors and built it OK,
however, it didn't work as expected.
The system boots to Home but all display is garbled.
I'm not sure if I made some mistakes on
fixing the building errors or there are some changes
that really broke these patches.
(the latest commit I've tried in the master is 32cb7d61)
I finally decide to give it up and send them as the current status.
(otherwise it will take too much of my time and delay
my other pending tasks)

Unfortunately the situation is most mesa developers
don't care android so they usually break android build
or functions. Unless the situation is changed it's very hard
for us to follow the master branch closely.

>> The patches depend on some patches developed by Varad Gautam which
>> have not been merged in Mesa master yet, say
>>
>> fc40946 egl: fixup: define droid_image_loader_extension
>> d15901d egl: android: populate dri2_surf->window early
>> cff1928 egl: android: use __DRI_IMAGE_LOADER to get color buffers
>> b556be4 egl: android: experimental dma-buf fd support
>>
>> The dependency may be removed but we haven't tested that yet.
>>
> Afaict none of Varad's work should be required here. It adds an
> alternative (better) method of the already existing functionality.

I also guess that but it need more time to verify that.

> Related: iirc things have gone wrong during the rebase of Varad's work
> in Android-x86. Rob H recently sent some patches (based of Android-x86
> ?) which has some strange/extra code in them.

Yes I notice that but again it need time
to figure what patches are really needed.
However due to the master branch status is horrible
for android so I gave up.

If possible, I'll ask Mauro to follow the master branch
and work with others to fix android stuff
for future android release (i.e., N).
For marshmallow-x86 we will stay in mesa 11.2
and I'll move my time to other pending tasks
for a stable release.

>> WuZhen (7):
>>   st/dri: fix double free of dri_drawable
>>   tgsi: fix stack allocated struct may not be initialized
>>   gallium/swrast: fix dri_sw_dt->data free func not matching alloc func
>>   android: print debug info to logcat
>>   android: enable dlopen
>>   android: enable x86 asm and sse4 for x86 and x86_64
>>   android: support swrast
>
> A couple of high level suggestions:
>  - Please split patches appropriately (more). Some patches are great
> while others should become 3-4 separate ones.

Actually I think the first 6 patches are already good.
The 7th patch is bigger and could probably be split.
Could you suggest how to do it?

>  - Drop the NO_REF_TASK, tested and Change-Id tags. Sadly these don't
> bring much, plus non-Jide people are unlikely to have access to the
> Gerrit and other instances where these are used.

These are Jide's internal comments I just kept it as.
I've no opinion to keep or remove them.
Let WuZhen decide.

> I'll try to look into the individual patches shortly.

Thanks!

-- 
Chih-Wei
Android-x86 project
http://www.android-x86.org
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[Mesa-dev] [PATCH] swr: remove duplicated constant update code

[Tim Rowley]

---
 src/gallium/drivers/swr/swr_state.cpp | 91 ++-
 1 file changed, 47 insertions(+), 44 deletions(-)

diff --git a/src/gallium/drivers/swr/swr_state.cpp 
b/src/gallium/drivers/swr/swr_state.cpp
index 12916f6..a7ae9df 100644
--- a/src/gallium/drivers/swr/swr_state.cpp
+++ b/src/gallium/drivers/swr/swr_state.cpp
@@ -724,6 +724,51 @@ swr_update_sampler_state(struct swr_context *ctx,
}
 }
 
+static void
+swr_update_constants(struct swr_context *ctx, enum pipe_shader_type shaderType)
+{
+   swr_draw_context *pDC = >swrDC;
+
+   const float **constant;
+   uint32_t *num_constants;
+   struct swr_scratch_space *scratch;
+
+   switch (shaderType) {
+   case PIPE_SHADER_VERTEX:
+  constant = pDC->constantVS;
+  num_constants = pDC->num_constantsVS;
+  scratch = >scratch->vs_constants;
+  break;
+   case PIPE_SHADER_FRAGMENT:
+  constant = pDC->constantFS;
+  num_constants = pDC->num_constantsFS;
+  scratch = >scratch->fs_constants;
+  break;
+   default:
+  debug_printf("Unsupported shader type constants\n");
+  return;
+   }
+
+   for (UINT i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
+  const pipe_constant_buffer *cb = >constants[shaderType][i];
+  num_constants[i] = cb->buffer_size;
+  if (cb->buffer) {
+ constant[i] =
+(const float *)(swr_resource_data(cb->buffer) +
+cb->buffer_offset);
+  } else {
+ /* Need to copy these constants to scratch space */
+ if (cb->user_buffer && cb->buffer_size) {
+const void *ptr =
+   ((const uint8_t *)cb->user_buffer + cb->buffer_offset);
+uint32_t size = AlignUp(cb->buffer_size, 4);
+ptr = swr_copy_to_scratch_space(ctx, scratch, ptr, size);
+constant[i] = (const float *)ptr;
+ }
+  }
+   }
+}
+
 void
 swr_update_derived(struct pipe_context *pipe,
const struct pipe_draw_info *p_draw_info)
@@ -1126,54 +1171,12 @@ swr_update_derived(struct pipe_context *pipe,
 
/* VertexShader Constants */
if (ctx->dirty & SWR_NEW_VSCONSTANTS) {
-  swr_draw_context *pDC = >swrDC;
-
-  for (UINT i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
- const pipe_constant_buffer *cb =
->constants[PIPE_SHADER_VERTEX][i];
- pDC->num_constantsVS[i] = cb->buffer_size;
- if (cb->buffer)
-pDC->constantVS[i] =
-   (const float *)(swr_resource_data(cb->buffer) +
-   cb->buffer_offset);
- else {
-/* Need to copy these constants to scratch space */
-if (cb->user_buffer && cb->buffer_size) {
-   const void *ptr =
-  ((const uint8_t *)cb->user_buffer + cb->buffer_offset);
-   uint32_t size = AlignUp(cb->buffer_size, 4);
-   ptr = swr_copy_to_scratch_space(
-  ctx, >scratch->vs_constants, ptr, size);
-   pDC->constantVS[i] = (const float *)ptr;
-}
- }
-  }
+  swr_update_constants(ctx, PIPE_SHADER_VERTEX);
}
 
/* FragmentShader Constants */
if (ctx->dirty & SWR_NEW_FSCONSTANTS) {
-  swr_draw_context *pDC = >swrDC;
-
-  for (UINT i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
- const pipe_constant_buffer *cb =
->constants[PIPE_SHADER_FRAGMENT][i];
- pDC->num_constantsFS[i] = cb->buffer_size;
- if (cb->buffer)
-pDC->constantFS[i] =
-   (const float *)(swr_resource_data(cb->buffer) +
-   cb->buffer_offset);
- else {
-/* Need to copy these constants to scratch space */
-if (cb->user_buffer && cb->buffer_size) {
-   const void *ptr =
-  ((const uint8_t *)cb->user_buffer + cb->buffer_offset);
-   uint32_t size = AlignUp(cb->buffer_size, 4);
-   ptr = swr_copy_to_scratch_space(
-  ctx, >scratch->fs_constants, ptr, size);
-   pDC->constantFS[i] = (const float *)ptr;
-}
- }
-  }
+  swr_update_constants(ctx, PIPE_SHADER_FRAGMENT);
}
 
/* Depth/stencil state */
-- 
1.9.1

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Re: [Mesa-dev] [PATCH 1/4] nir: Avoid C99 field initializers.

[Jose Fonseca]

On 28/04/16 15:37, Connor Abbott wrote:

For the series:

Reviewed-by: Connor Abbott 

For the zero-sized array thing... we could make it a statically-sized
array, since we never have more than 4 arguments to an ALU
instruction, but that would be wasteful of memory. Also, we always
have at least 1 argument, so we could make the size 1 to shut up the
warning, but that would be more confusing and introduce undefined
behavior in C99 that the compiler is likely to actually take advantage
of. I don't see any options better than just accepting the warning
and/or shutting that specific warning off.


I feared so.  Thanks for looking into it though.

Jose




On Thu, Apr 28, 2016 at 7:27 AM, Jose Fonseca  wrote:

As they are not standard C++ and are not supported by MSVC C++ compiler.

Just have nir_imm_double match nir_imm_float above.
---
  src/compiler/nir/nir_builder.h | 9 ++---
  1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index a14f9ef..4fa9779 100644
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -117,9 +117,12 @@ nir_imm_float(nir_builder *build, float x)
  static inline nir_ssa_def *
  nir_imm_double(nir_builder *build, double x)
  {
-   nir_const_value v = { { .f64 = {x, 0, 0, 0} } };
-   nir_ssa_def *def = nir_build_imm(build, 1, 64, v);
-   return def;
+   nir_const_value v;
+
+   memset(, 0, sizeof(v));
+   v.f64[0] = x;
+
+   return nir_build_imm(build, 1, 64, v);
  }

  static inline nir_ssa_def *
--
2.5.0



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Re: [Mesa-dev] [PATCH] nir: mark dsqrt/drsqrt/drcp implementation as exact

[Connor Abbott]

On Thu, Apr 28, 2016 at 11:26 AM, Ilia Mirkin  wrote:
> On Thu, Apr 28, 2016 at 11:21 AM, Connor Abbott  wrote:
>> On Thu, Apr 28, 2016 at 11:20 AM, Ilia Mirkin  wrote:
>>> What if the existing operations were already exact?
>>
>> They aren't -- the builder makes them non-exact by default, and we
>> initialize the builder ourselves in this pass.
>
> Hmm... OK. I'm just thinking of the case
>
> precise c  = op(a, b)
>
> And op gets lowered. The resulting operations should also be exact. If
> that's what's happening, then all's well.

The resulting operations should be exact regardless of whether the
original one was exact -- they're relying on the extra precision that
fma() gives us in order to get the right precision in the result, and
like in GLSL, there's no guarantee that a non-exact fma won't be split
into multiply + add. Once we lower the operation, the compiler can't
really apply any optimizations to the operation as a whole (except
maybe constant folding) so it basically becomes exact anyways.

>
>   -ilia
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Re: [Mesa-dev] [android-x86-devel] [RFC 0/7] android: enable llvmpipe for software rendering

[Rob Herring]

On Thu, Apr 28, 2016 at 9:22 AM, Emil Velikov  wrote:
> Hi Chih-Wei,
>
> Thanks for getting these out to the community.
>
> On 28 April 2016 at 08:34, Chih-Wei Huang  wrote:
>> This is a series of patches developed by Jide Technolody to enable
>> the llvmpipe for software rendering of Android.
>> It makes a device without a Mesa supported GPU could run most modern
>> Android apps.
>>
> Afaict one should only need the extra Android.mk files to get llvmpipe
> considering that softpipe already works.
> Have you/the Jide folks tried the latter already ? Does it work
> without these patches ?
>
>> These patches are mainly developed and tested on the 11.0 and 11.2
>> branches. They might not work with the Mesa master branch.
>>
> Humble request - please always aim for master. Doing this will get you
> the latest stable branch for free.
> If you're targeting some old stable branch then you'll will have to
> duplicate the effort to land things in master. And new functionality
> goes _only_ in master
>
>> The patches depend on some patches developed by Varad Gautam which
>> have not been merged in Mesa master yet, say
>>
>> fc40946 egl: fixup: define droid_image_loader_extension
>> d15901d egl: android: populate dri2_surf->window early

This one we have confirmed is not needed for sure.

>> cff1928 egl: android: use __DRI_IMAGE_LOADER to get color buffers
>> b556be4 egl: android: experimental dma-buf fd support
>>
>> The dependency may be removed but we haven't tested that yet.
>>
> Afaict none of Varad's work should be required here. It adds an
> alternative (better) method of the already existing functionality.

For an Android-x86 build, that should be true. That requires using the
older drm_gralloc implementation that works on the card node (and does
KMS) rather than the render node. For my setup, I don't think it works
to use GEM handles.

> Related: iirc things have gone wrong during the rebase of Varad's work
> in Android-x86. Rob H recently sent some patches (based of Android-x86
> ?) which has some strange/extra code in them.

Based originally on Android-x86 as that was what Varad based his work
on, but the strangeness was both in Varad's original work or I
introduced it. Should have a new version out soon.

Rob
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Re: [Mesa-dev] [PATCH] nir: mark dsqrt/drsqrt/drcp implementation as exact

[Ilia Mirkin]

On Thu, Apr 28, 2016 at 11:21 AM, Connor Abbott  wrote:
> On Thu, Apr 28, 2016 at 11:20 AM, Ilia Mirkin  wrote:
>> What if the existing operations were already exact?
>
> They aren't -- the builder makes them non-exact by default, and we
> initialize the builder ourselves in this pass.

Hmm... OK. I'm just thinking of the case

precise c  = op(a, b)

And op gets lowered. The resulting operations should also be exact. If
that's what's happening, then all's well.

  -ilia
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Re: [Mesa-dev] [PATCH] nir: mark dsqrt/drsqrt/drcp implementation as exact

[Connor Abbott]

On Thu, Apr 28, 2016 at 11:20 AM, Ilia Mirkin  wrote:
> What if the existing operations were already exact?

They aren't -- the builder makes them non-exact by default, and we
initialize the builder ourselves in this pass.

>
> On Thu, Apr 28, 2016 at 11:17 AM, Connor Abbott  wrote:
>> The floating-point operations used to implement these have been
>> carefully chosen to minimize rounding error while still getting decent
>> performance. We don't want any optimizations to mess with them. While
>> this shouldn't affect anything now, it seems like a good idea.
>>
>> Signed-off-by: Connor Abbott 
>> ---
>>  src/compiler/nir/nir_lower_double_ops.c | 4 
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/src/compiler/nir/nir_lower_double_ops.c 
>> b/src/compiler/nir/nir_lower_double_ops.c
>> index 7505fa3..42b94bb 100644
>> --- a/src/compiler/nir/nir_lower_double_ops.c
>> +++ b/src/compiler/nir/nir_lower_double_ops.c
>> @@ -142,8 +142,10 @@ lower_rcp(nir_builder *b, nir_ssa_def *src)
>>  * See https://en.wikipedia.org/wiki/Division_algorithm for more details.
>>  */
>>
>> +   b->exact = true;
>> ra = nir_ffma(b, ra, nir_ffma(b, ra, src, nir_imm_double(b, -1)), ra);
>> ra = nir_ffma(b, ra, nir_ffma(b, ra, src, nir_imm_double(b, -1)), ra);
>> +   b->exact = false;
>>
>> return fix_inv_result(b, ra, src, new_exp);
>>  }
>> @@ -267,6 +269,7 @@ lower_sqrt_rsq(nir_builder *b, nir_ssa_def *src, bool 
>> sqrt)
>>  * (https://en.wikipedia.org/wiki/Methods_of_computing_square_roots).
>>  */
>>
>> +b->exact = true;
>>  nir_ssa_def *one_half = nir_imm_double(b, 0.5);
>>  nir_ssa_def *h_0 = nir_fmul(b, one_half, ra);
>>  nir_ssa_def *g_0 = nir_fmul(b, src, ra);
>> @@ -283,6 +286,7 @@ lower_sqrt_rsq(nir_builder *b, nir_ssa_def *src, bool 
>> sqrt)
>> one_half);
>> res = nir_ffma(b, y_1, r_1, y_1);
>>  }
>> +b->exact = false;
>>
>>  if (sqrt) {
>> /* Here, the special cases we need to handle are
>> --
>> 2.5.0
>>
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Re: [Mesa-dev] [PATCH] nir: mark dsqrt/drsqrt/drcp implementation as exact

[Ilia Mirkin]

What if the existing operations were already exact?

On Thu, Apr 28, 2016 at 11:17 AM, Connor Abbott  wrote:
> The floating-point operations used to implement these have been
> carefully chosen to minimize rounding error while still getting decent
> performance. We don't want any optimizations to mess with them. While
> this shouldn't affect anything now, it seems like a good idea.
>
> Signed-off-by: Connor Abbott 
> ---
>  src/compiler/nir/nir_lower_double_ops.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/src/compiler/nir/nir_lower_double_ops.c 
> b/src/compiler/nir/nir_lower_double_ops.c
> index 7505fa3..42b94bb 100644
> --- a/src/compiler/nir/nir_lower_double_ops.c
> +++ b/src/compiler/nir/nir_lower_double_ops.c
> @@ -142,8 +142,10 @@ lower_rcp(nir_builder *b, nir_ssa_def *src)
>  * See https://en.wikipedia.org/wiki/Division_algorithm for more details.
>  */
>
> +   b->exact = true;
> ra = nir_ffma(b, ra, nir_ffma(b, ra, src, nir_imm_double(b, -1)), ra);
> ra = nir_ffma(b, ra, nir_ffma(b, ra, src, nir_imm_double(b, -1)), ra);
> +   b->exact = false;
>
> return fix_inv_result(b, ra, src, new_exp);
>  }
> @@ -267,6 +269,7 @@ lower_sqrt_rsq(nir_builder *b, nir_ssa_def *src, bool 
> sqrt)
>  * (https://en.wikipedia.org/wiki/Methods_of_computing_square_roots).
>  */
>
> +b->exact = true;
>  nir_ssa_def *one_half = nir_imm_double(b, 0.5);
>  nir_ssa_def *h_0 = nir_fmul(b, one_half, ra);
>  nir_ssa_def *g_0 = nir_fmul(b, src, ra);
> @@ -283,6 +286,7 @@ lower_sqrt_rsq(nir_builder *b, nir_ssa_def *src, bool 
> sqrt)
> one_half);
> res = nir_ffma(b, y_1, r_1, y_1);
>  }
> +b->exact = false;
>
>  if (sqrt) {
> /* Here, the special cases we need to handle are
> --
> 2.5.0
>
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[Mesa-dev] [PATCH] nir: mark dsqrt/drsqrt/drcp implementation as exact

[Connor Abbott]

The floating-point operations used to implement these have been
carefully chosen to minimize rounding error while still getting decent
performance. We don't want any optimizations to mess with them. While
this shouldn't affect anything now, it seems like a good idea.

Signed-off-by: Connor Abbott 
---
 src/compiler/nir/nir_lower_double_ops.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/compiler/nir/nir_lower_double_ops.c 
b/src/compiler/nir/nir_lower_double_ops.c
index 7505fa3..42b94bb 100644
--- a/src/compiler/nir/nir_lower_double_ops.c
+++ b/src/compiler/nir/nir_lower_double_ops.c
@@ -142,8 +142,10 @@ lower_rcp(nir_builder *b, nir_ssa_def *src)
 * See https://en.wikipedia.org/wiki/Division_algorithm for more details.
 */
 
+   b->exact = true;
ra = nir_ffma(b, ra, nir_ffma(b, ra, src, nir_imm_double(b, -1)), ra);
ra = nir_ffma(b, ra, nir_ffma(b, ra, src, nir_imm_double(b, -1)), ra);
+   b->exact = false;
 
return fix_inv_result(b, ra, src, new_exp);
 }
@@ -267,6 +269,7 @@ lower_sqrt_rsq(nir_builder *b, nir_ssa_def *src, bool sqrt)
 * (https://en.wikipedia.org/wiki/Methods_of_computing_square_roots).
 */
 
+b->exact = true;
 nir_ssa_def *one_half = nir_imm_double(b, 0.5);
 nir_ssa_def *h_0 = nir_fmul(b, one_half, ra);
 nir_ssa_def *g_0 = nir_fmul(b, src, ra);
@@ -283,6 +286,7 @@ lower_sqrt_rsq(nir_builder *b, nir_ssa_def *src, bool sqrt)
one_half);
res = nir_ffma(b, y_1, r_1, y_1);
 }
+b->exact = false;
 
 if (sqrt) {
/* Here, the special cases we need to handle are
-- 
2.5.0

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Re: [Mesa-dev] [PATCH] glsl: Checks for interpolation into its own function.

[Andres Gomez]

On Tue, 2016-04-26 at 12:16 +0200, Samuel Iglesias Gonsálvez wrote:
> On 04/04/16 18:50, Andres Gomez wrote:
> > 
> > This generalizes the validation also to be done for variables
> > inside
> > interface blocks, which, for some cases, was missing.
> > 
> > For a discussion about the additional validation cases included see
> > https://lists.freedesktop.org/archives/mesa-dev/2016-March/109117.h
> > tml
> > and Khronos bug #15671.
> > 
> Do we have news about this Khronos bug? Are the piglit tests pushed
> upstream?

About Khronos' bug, no idea since I don't have access to the bugzilla.

The piglit tests are landing shortly since they have been already
reviewed (I hope in a matter of hours).

> Assuming no piglit/dEQP regressions, this patch is:

I run piglit/dEQP before sending for review and didn't observe any
regressions.


> Reviewed-by: Samuel Iglesias Gonsálvez 

Thanks!

> 
> Sam
> 
> > 
> > Signed-off-by: Andres Gomez 
> > ---
> >  src/compiler/glsl/ast_to_hir.cpp | 316 +
> > --
> >  1 file changed, 171 insertions(+), 145 deletions(-)
> > 
> > diff --git a/src/compiler/glsl/ast_to_hir.cpp
> > b/src/compiler/glsl/ast_to_hir.cpp
> > index 7c9be81..e4ebc6b 100644
> > --- a/src/compiler/glsl/ast_to_hir.cpp
> > +++ b/src/compiler/glsl/ast_to_hir.cpp
> > @@ -2792,8 +2792,164 @@ apply_explicit_binding(struct
> > _mesa_glsl_parse_state *state,
> >  }
> >  
> >  
> > +static void
> > +validate_interpolation_qualifier(struct _mesa_glsl_parse_state
> > *state,
> > + YYLTYPE *loc,
> > + const glsl_interp_qualifier
> > interpolation,
> > + const struct ast_type_qualifier
> > *qual,
> > + const struct glsl_type *var_type,
> > + ir_variable_mode mode)
> > +{
> > +   /* Interpolation qualifiers can only apply to shader inputs or
> > outputs, but
> > +* not to vertex shader inputs nor fragment shader outputs.
> > +*
> > +* From section 4.3 ("Storage Qualifiers") of the GLSL 1.30
> > spec:
> > +*"Outputs from a vertex shader (out) and inputs to a
> > fragment
> > +*shader (in) can be further qualified with one or more of
> > these
> > +*interpolation qualifiers"
> > +*...
> > +*"These interpolation qualifiers may only precede the
> > qualifiers in,
> > +*centroid in, out, or centroid out in a declaration. They
> > do not apply
> > +*to the deprecated storage qualifiers varying or centroid
> > +*varying. They also do not apply to inputs into a vertex
> > shader or
> > +*outputs from a fragment shader."
> > +*
> > +* From section 4.3 ("Storage Qualifiers") of the GLSL ES 3.00
> > spec:
> > +*"Outputs from a shader (out) and inputs to a shader (in)
> > can be
> > +*further qualified with one of these interpolation
> > qualifiers."
> > +*...
> > +*"These interpolation qualifiers may only precede the
> > qualifiers
> > +*in, centroid in, out, or centroid out in a declaration.
> > They do
> > +*not apply to inputs into a vertex shader or outputs from
> > a
> > +*fragment shader."
> > +*/
> > +   if (state->is_version(130, 300)
> > +   && interpolation != INTERP_QUALIFIER_NONE) {
> > +  const char *i = interpolation_string(interpolation);
> > +  if (mode != ir_var_shader_in && mode != ir_var_shader_out)
> > + _mesa_glsl_error(loc, state,
> > +  "interpolation qualifier `%s' can only
> > be applied to "
> > +  "shader inputs or outputs.", i);
> > +
> > +  switch (state->stage) {
> > +  case MESA_SHADER_VERTEX:
> > + if (mode == ir_var_shader_in) {
> > +_mesa_glsl_error(loc, state,
> > + "interpolation qualifier '%s' cannot
> > be applied to "
> > + "vertex shader inputs", i);
> > + }
> > + break;
> > +  case MESA_SHADER_FRAGMENT:
> > + if (mode == ir_var_shader_out) {
> > +_mesa_glsl_error(loc, state,
> > + "interpolation qualifier '%s' cannot
> > be applied to "
> > + "fragment shader outputs", i);
> > + }
> > + break;
> > +  default:
> > + break;
> > +  }
> > +   }
> > +
> > +   /* Interpolation qualifiers cannot be applied to 'centroid' and
> > +* 'centroid varying'.
> > +*
> > +* From section 4.3 ("Storage Qualifiers") of the GLSL 1.30
> > spec:
> > +*"interpolation qualifiers may only precede the qualifiers
> > in,
> > +*centroid in, out, or centroid out in a declaration. They
> > do not apply
> > +*to the deprecated storage qualifiers varying or centroid
> > varying."
> > +*
> > +* These deprecated storage qualifiers 

[Mesa-dev] Mesa 11.3.0/12.0.0 release plan

[Emil Velikov]

Hi all,

Here is the current tentative 11.3.0/12.0.0 release schedule.

May 20th 2016 - Feature freeze/Release candidate 1
May 27th 2016 - Release candidate 2
June 03rd 2016 - Release candidate 3
June 10th 2016 - Release candidate 4/final release

With the above in mind we have three weeks to get new features.

Do we have some serious work that we want to squeeze in and the time
is not enough. Does the proposed dates align with distributions
needs/expectations ?

Kindly let me know.

Thanks
Emil
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[Mesa-dev] Results of the 2016 Election to the X.Org BoD & Vote on the By-Law Changes

[Peter Hutterer]

The 2016 Election is now over and the results are in. Two questions were up
for voting, 4 seats on the Board of Directors and approval of the amended
By-Laws to join SPI.

The Results of the Board of Director elections:
Candidates and their respective points:
Egbert Eich  205
Alex Deucher 195
Keith Packard152
Bryce Harrington 142
Lucas Stach  129

Therefore the following candidates have been elected to the board:
Egbert Eich, Alex Deucher, Keith Packard, Bryce Harrington


The results on the vote to change the By-Laws to join SPI:
Do you agree to the changed By-Laws?
Yes 54/65 (83.1%)
No  4/65 (6.2%)
Abstain 3/65 (4.6%)

We have 65 members and 61 votes were recorded.

According to Article 7 of the Oct. 29, 2006 By-Laws the following
provision is made for changes to the By-Laws:

 "AMENDMENT These By-law may be altered, amended or repealed by
  an affirmative vote of at least two-thirds (2/3) of the Members
  of X.Org."

We have reached quorum and have a 2/3 majority in favour of the change. The
changes to the By-Laws are thus accepted.

Cheers,
   The X.Org 2016 Election Committee
Peter Hutterer
Daniel Vetter
Martin Peres
Rob Clark


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Re: [Mesa-dev] [PATCH 2/2] mesa: dri: Add shared glapi to LIBADD on Android

[Emil Velikov]

On 28 April 2016 at 11:41, Nicolas Boichat  wrote:
> /system/vendor/lib/dri/*_dri.so actually depend on libglapi: without
> this, loading the so file fails with:
> cannot locate symbol "__emutls_v._glapi_tls_Context"
>
> On non-Android (non-bionic) platform, EGL uses the following
> workflow, which works fine:
>   dlopen("libglapi.so", RTLD_LAZY | RTLD_GLOBAL);
>   dlopen("dri/_dri.so", RTLD_NOW | RTLD_GLOBAL);
>
> However, bionic does not respect the RTLD_GLOBAL flag, and the dri
> library cannot find symbols in libglapi.so, so we need to link
> to libglapi.so explicitly. Android.mk already does this.
>
Ideally we'll soon be able to do a similar thing for the Linux binaries.

> Signed-off-by: Nicolas Boichat 
> ---
>  src/mesa/drivers/dri/Makefile.am | 8 
>  1 file changed, 8 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/Makefile.am 
> b/src/mesa/drivers/dri/Makefile.am
> index 08a8e64..0589bac 100644
> --- a/src/mesa/drivers/dri/Makefile.am
> +++ b/src/mesa/drivers/dri/Makefile.am
> @@ -6,6 +6,13 @@ MEGADRIVERS_DEPS =
>
>  SUBDIRS+=common
>
> +# On Android, we need to explicitely link to libglapi.so.
Typo "explicitly" - I can fix that before pushing.

We want a similar patch for the gallium dri modules, correct ?
(The ones in src/gallium/targets/dri/Makefile.am)

Both patches look good and are
Reviewed-by: Emil Velikov 

-Emil
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[Mesa-dev] [Bug 95180] rasterizer/memory/Convert.h:170:9: error: ‘__builtin_isnan’ is not a member of ‘std’

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=95180

--- Comment #3 from Ilia Mirkin  ---
>From the sounds of it, there's a

#define isnan __builtin_isnan

somewhere which is converting

std::isnan

into

std::__builtin_isnan

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Re: [Mesa-dev] [PATCH 1/4] nir: Avoid C99 field initializers.

[Connor Abbott]

For the series:

Reviewed-by: Connor Abbott 

For the zero-sized array thing... we could make it a statically-sized
array, since we never have more than 4 arguments to an ALU
instruction, but that would be wasteful of memory. Also, we always
have at least 1 argument, so we could make the size 1 to shut up the
warning, but that would be more confusing and introduce undefined
behavior in C99 that the compiler is likely to actually take advantage
of. I don't see any options better than just accepting the warning
and/or shutting that specific warning off.


On Thu, Apr 28, 2016 at 7:27 AM, Jose Fonseca  wrote:
> As they are not standard C++ and are not supported by MSVC C++ compiler.
>
> Just have nir_imm_double match nir_imm_float above.
> ---
>  src/compiler/nir/nir_builder.h | 9 ++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
> index a14f9ef..4fa9779 100644
> --- a/src/compiler/nir/nir_builder.h
> +++ b/src/compiler/nir/nir_builder.h
> @@ -117,9 +117,12 @@ nir_imm_float(nir_builder *build, float x)
>  static inline nir_ssa_def *
>  nir_imm_double(nir_builder *build, double x)
>  {
> -   nir_const_value v = { { .f64 = {x, 0, 0, 0} } };
> -   nir_ssa_def *def = nir_build_imm(build, 1, 64, v);
> -   return def;
> +   nir_const_value v;
> +
> +   memset(, 0, sizeof(v));
> +   v.f64[0] = x;
> +
> +   return nir_build_imm(build, 1, 64, v);
>  }
>
>  static inline nir_ssa_def *
> --
> 2.5.0
>
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Re: [Mesa-dev] [PATCH 1/2] configure.ac: Add support for Android builds

[Emil Velikov]

Hi Nicolas,

On 28 April 2016 at 11:41, Nicolas Boichat  wrote:
> Add support for EGL android platform.
>
> Also, detect when --host finishes with -android. In that case, we
> do not set _GNU_SOURCE, and define autoconf symbol HAVE_ANDROID, so
> that Android-specific workarounds can be applied.
>
I'm quite happy to see patches from Android/CrOS people although I'm a
bit confused here.
Are these are based for CrOS or Android ? I thought Android had it's
own build system.

Is there any documentation on how one can get things going on your platform ?

> Signed-off-by: Nicolas Boichat 
> ---
>  configure.ac| 10 ++
>  src/egl/Makefile.am |  5 +
>  2 files changed, 15 insertions(+)
>
> diff --git a/configure.ac b/configure.ac
> index 5f75c60..6ee978c 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -248,7 +248,11 @@ _SAVE_CPPFLAGS="$CPPFLAGS"
>  dnl Compiler macros
>  DEFINES="-D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS"
>  AC_SUBST([DEFINES])
> +android=no
>  case "$host_os" in
> +*-android)
> +android=yes
> +;;
>  linux*|*-gnu*|gnu*)
>  DEFINES="$DEFINES -D_GNU_SOURCE"
>  ;;
> @@ -260,6 +264,8 @@ cygwin*)
>  ;;
>  esac
>
> +AM_CONDITIONAL(HAVE_ANDROID, test "x$android" = xyes)
> +
>  dnl Add flags for gcc and g++
>  if test "x$GCC" = xyes; then
>  CFLAGS="$CFLAGS -Wall"
> @@ -1959,6 +1965,9 @@ for plat in $egl_platforms; do
> AC_MSG_ERROR([EGL platform surfaceless requires 
> libdrm >= $LIBDRM_REQUIRED])
> ;;
>
> +   android)
Can you update the documentation in docs/egl.html as well please. Feel
free to do that as follow-up patch.

Do you guys have X related libraries on the host_os ? Or you
explicitly disable those mesa features that depend on it ?

Thanks
Emil
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Re: [Mesa-dev] [PATCH 1/7] i965: Pass devinfo pointer to brw_instruction_name().

[Iago Toral]

I made a couple of very minor comments to some patches but do with them
as you wish. The series is:

Reviewed-by: Iago Toral Quiroga 

On Thu, 2016-04-28 at 00:19 -0700, Francisco Jerez wrote:
> A future series will implement support for an instruction that happens
> to have the same opcode number as another instruction we support
> already on a disjoint set of hardware generations.  In order to
> disambiguate which instruction it is brw_instruction_name() will need
> some way to find out which device we are generating code for.
> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
>  src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +-
>  src/mesa/drivers/dri/i965/brw_shader.h   | 3 ++-
>  src/mesa/drivers/dri/i965/brw_vec4.cpp   | 2 +-
>  4 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 78f7d40..c7c7a45 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -4796,7 +4796,7 @@ fs_visitor::dump_instruction(backend_instruction 
> *be_inst, FILE *file)
>   inst->flag_subreg);
> }
>  
> -   fprintf(file, "%s", brw_instruction_name(inst->opcode));
> +   fprintf(file, "%s", brw_instruction_name(devinfo, inst->opcode));
> if (inst->saturate)
>fprintf(file, ".sat");
> if (inst->conditional_mod) {
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
> b/src/mesa/drivers/dri/i965/brw_shader.cpp
> index 80fddfc..a2281a7 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
> @@ -163,7 +163,7 @@ brw_texture_offset(int *offsets, unsigned num_components)
>  }
>  
>  const char *
> -brw_instruction_name(enum opcode op)
> +brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
>  {
> switch (op) {
> case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
> b/src/mesa/drivers/dri/i965/brw_shader.h
> index fc228f6..8ab8d5b 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.h
> +++ b/src/mesa/drivers/dri/i965/brw_shader.h
> @@ -235,7 +235,8 @@ struct backend_shader;
>  enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
>  enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
>  uint32_t brw_math_function(enum opcode op);
> -const char *brw_instruction_name(enum opcode op);
> +const char *brw_instruction_name(const struct brw_device_info *devinfo,
> + enum opcode op);
>  bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
>  bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
>  bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> index a2b3560..599e45e 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> @@ -1393,7 +1393,7 @@ vec4_visitor::dump_instruction(backend_instruction 
> *be_inst, FILE *file)
>pred_ctrl_align16[inst->predicate]);
> }
>  
> -   fprintf(file, "%s", brw_instruction_name(inst->opcode));
> +   fprintf(file, "%s", brw_instruction_name(devinfo, inst->opcode));
> if (inst->saturate)
>fprintf(file, ".sat");
> if (inst->conditional_mod) {


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Re: [Mesa-dev] [android-x86-devel] [RFC 0/7] android: enable llvmpipe for software rendering

[Emil Velikov]

Hi Chih-Wei,

Thanks for getting these out to the community.

On 28 April 2016 at 08:34, Chih-Wei Huang  wrote:
> This is a series of patches developed by Jide Technolody to enable
> the llvmpipe for software rendering of Android.
> It makes a device without a Mesa supported GPU could run most modern
> Android apps.
>
Afaict one should only need the extra Android.mk files to get llvmpipe
considering that softpipe already works.
Have you/the Jide folks tried the latter already ? Does it work
without these patches ?

> These patches are mainly developed and tested on the 11.0 and 11.2
> branches. They might not work with the Mesa master branch.
>
Humble request - please always aim for master. Doing this will get you
the latest stable branch for free.
If you're targeting some old stable branch then you'll will have to
duplicate the effort to land things in master. And new functionality
goes _only_ in master

> The patches depend on some patches developed by Varad Gautam which
> have not been merged in Mesa master yet, say
>
> fc40946 egl: fixup: define droid_image_loader_extension
> d15901d egl: android: populate dri2_surf->window early
> cff1928 egl: android: use __DRI_IMAGE_LOADER to get color buffers
> b556be4 egl: android: experimental dma-buf fd support
>
> The dependency may be removed but we haven't tested that yet.
>
Afaict none of Varad's work should be required here. It adds an
alternative (better) method of the already existing functionality.
Related: iirc things have gone wrong during the rebase of Varad's work
in Android-x86. Rob H recently sent some patches (based of Android-x86
?) which has some strange/extra code in them.


> WuZhen (7):
>   st/dri: fix double free of dri_drawable
>   tgsi: fix stack allocated struct may not be initialized
>   gallium/swrast: fix dri_sw_dt->data free func not matching alloc func
>   android: print debug info to logcat
>   android: enable dlopen
>   android: enable x86 asm and sse4 for x86 and x86_64
>   android: support swrast
>

A couple of high level suggestions:
 - Please split patches appropriately (more). Some patches are great
while others should become 3-4 separate ones.
 - Drop the NO_REF_TASK, tested and Change-Id tags. Sadly these don't
bring much, plus non-Jide people are unlikely to have access to the
Gerrit and other instances where these are used.

I'll try to look into the individual patches shortly.

Thanks
Emil
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Re: [Mesa-dev] [PATCH 6/7] i965: Move opcode_desc tables into brw_eu.c.

[Iago Toral]

On Thu, 2016-04-28 at 00:19 -0700, Francisco Jerez wrote:
> The opcode_desc tables are useful for several purposes other than
> disassembling the program: Finding out whether an instruction is
> three-source in the optimizer and instruction compaction code,
> printing out instructions at the IR level and validating assembled
> programs -- It seems like brw_eu.c next to other EU ISA auxiliary code
> is a better fit than the disassembler.

Yeah, I was thinking the same thing while I was reading the series :)

> ---
>  src/mesa/drivers/dri/i965/brw_context.h |   6 --
>  src/mesa/drivers/dri/i965/brw_disasm.c  | 147 
> 
>  src/mesa/drivers/dri/i965/brw_eu.c  | 147 
> 
>  src/mesa/drivers/dri/i965/brw_eu.h  |   6 ++
>  4 files changed, 153 insertions(+), 153 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
> b/src/mesa/drivers/dri/i965/brw_context.h
> index c001c6a..7468dfa 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -1794,12 +1794,6 @@ bool brw_lower_texture_gradients(struct brw_context 
> *brw,
>   struct exec_list *instructions);
>  bool brw_do_lower_unnormalized_offset(struct exec_list *instructions);
>  
> -struct opcode_desc {
> -char*name;
> -int  nsrc;
> -int  ndst;
> -};
> -
>  extern const char * const conditional_modifier[16];
>  extern const char *const pred_ctrl_align16[16];
>  
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 5c6f3e2..1778419 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -30,153 +30,6 @@
>  #include "brw_inst.h"
>  #include "brw_eu.h"
>  
> -/**
> - * Special opcode_desc entry that marks the instruction as no longer 
> existing.
> - * Unless explicitly specified using this marker a hardware generation is
> - * assumed to have inherited all opcodes defined and not removed by previous
> - * generations.
> - */
> -#define REMOVED { .name = "***removed***", .nsrc = ~0, .ndst = ~0 }
> -
> -static const struct opcode_desc gen4_opcode_descs[128] = {
> -   [BRW_OPCODE_MOV]  = { .name = "mov", .nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_FRC]  = { .name = "frc", .nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_RNDU] = { .name = "rndu",.nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_RNDD] = { .name = "rndd",.nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_RNDE] = { .name = "rnde",.nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_RNDZ] = { .name = "rndz",.nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_NOT]  = { .name = "not", .nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_LZD]  = { .name = "lzd", .nsrc = 1, .ndst = 1 },
> -
> -   [BRW_OPCODE_MUL]  = { .name = "mul", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_MAC]  = { .name = "mac", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_MACH] = { .name = "mach",.nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_LINE] = { .name = "line",.nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_SAD2] = { .name = "sad2",.nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_SADA2]= { .name = "sada2",   .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_DP4]  = { .name = "dp4", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_DPH]  = { .name = "dph", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_DP3]  = { .name = "dp3", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_DP2]  = { .name = "dp2", .nsrc = 2, .ndst = 1 },
> -
> -   [BRW_OPCODE_AVG]  = { .name = "avg", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_ADD]  = { .name = "add", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_SEL]  = { .name = "sel", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_AND]  = { .name = "and", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_OR]   = { .name = "or",  .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_XOR]  = { .name = "xor", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_SHR]  = { .name = "shr", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_SHL]  = { .name = "shl", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_ASR]  = { .name = "asr", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_CMP]  = { .name = "cmp", .nsrc = 2, .ndst = 1 },
> -   [BRW_OPCODE_CMPN] = { .name = "cmpn",.nsrc = 2, .ndst = 1 },
> -
> -   [BRW_OPCODE_SEND] = { .name = "send",.nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_SENDC]= { .name = "sendc",   .nsrc = 1, .ndst = 1 },
> -   [BRW_OPCODE_ILLEGAL]  = { .name = "illegal", .nsrc = 0, .ndst = 0 },
> -   [BRW_OPCODE_NOP]  = { .name = "nop", .nsrc = 0, .ndst = 0 },
> -   [BRW_OPCODE_NENOP]= { .name = "nenop",   .nsrc = 0, .ndst = 0 },
> -   [BRW_OPCODE_JMPI] = { .name = "jmpi",.nsrc = 0, .ndst = 0 },
> -   [BRW_OPCODE_IF]   = { .name = "if",  .nsrc = 0, .ndst = 0 },
> -   [BRW_OPCODE_IFF]  = { .name = 

Re: [Mesa-dev] [PATCH 3/3] nouveau: Add support for SV_WORK_DIM

[Samuel Pitoiset]

On 04/28/2016 04:12 PM, Samuel Pitoiset wrote:



On 04/28/2016 04:05 PM, Hans de Goede wrote:

Add support for SV_WORK_DIM for nvc0 and nve4.

Signed-off-by: Hans de Goede 
---
Changes in v1 (first non RFC posting):
-Adjust NVC0_CB_AUX_GRID_SIZE for the extra value in grid-info
-Use NVC0_CB_AUX_GRID_SIZE instead of a hardcoded value when
 uploading the grid info
-Also implement SV_WORK_DIM for nvc0
---
 src/gallium/drivers/nouveau/codegen/nv50_ir.h  |  1 +
 .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp  |  1 +
 .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  |  2 ++
 .../nouveau/codegen/nv50_ir_target_nvc0.cpp|  1 +
 src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 24
--
 src/gallium/drivers/nouveau/nvc0/nvc0_context.h|  4 ++--
 src/gallium/drivers/nouveau/nvc0/nvc0_program.c|  2 +-
 src/gallium/drivers/nouveau/nvc0/nve4_compute.c|  7 ---
 8 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 94e54bb..41804b6 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -461,6 +461,7 @@ enum SVSemantic
SV_BASEVERTEX,
SV_BASEINSTANCE,
SV_DRAWID,
+   SV_WORK_DIM,
SV_UNDEFINED,
SV_LAST
 };
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 3708f37..f75f480 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -408,6 +408,7 @@ static nv50_ir::SVSemantic translateSysVal(uint
sysval)
case TGSI_SEMANTIC_BASEVERTEX: return nv50_ir::SV_BASEVERTEX;
case TGSI_SEMANTIC_BASEINSTANCE: return nv50_ir::SV_BASEINSTANCE;
case TGSI_SEMANTIC_DRAWID: return nv50_ir::SV_DRAWID;
+   case TGSI_SEMANTIC_WORK_DIM:   return nv50_ir::SV_WORK_DIM;
default:
   assert(0);
   return nv50_ir::SV_CLOCK;
diff --git
a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 3bce962..1785623 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -2178,6 +2178,8 @@ NVC0LoweringPass::handleRDSV(Instruction *i)
  i->setSrc(0, bld.mkImm(sv == SV_GRIDID ? 0 : 1));
  return true;
   }
+  // Fallthrough
+   case SV_WORK_DIM:
   addr += prog->driver->prop.cp.gridInfoBase;
   bld.mkLoad(TYPE_U32, i->getDef(0),
  bld.mkSymbol(FILE_MEMORY_CONST,
prog->driver->io.auxCBSlot,
diff --git
a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
index 9e1e7bf..80cb9fd 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
@@ -293,6 +293,7 @@ TargetNVC0::getSVAddress(DataFile shaderFile,
const Symbol *sym) const
case SV_NTID:   return kepler ? (0x00 + idx * 4) : ~0;
case SV_NCTAID: return kepler ? (0x0c + idx * 4) : ~0;
case SV_GRIDID: return kepler ? 0x18 : ~0;
+   case SV_WORK_DIM:   return 0x1c;
case SV_SAMPLE_INDEX:   return 0;
case SV_SAMPLE_POS: return 0;
case SV_SAMPLE_MASK:return 0;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
index bbc8edb..9f85ead 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
@@ -284,7 +284,8 @@ nvc0_state_validate_cp(struct nvc0_context *nvc0,
uint32_t mask)
 }

 static void
-nvc0_compute_upload_input(struct nvc0_context *nvc0, const void *input)
+nvc0_compute_upload_input(struct nvc0_context *nvc0,
+  const struct pipe_grid_info *info)
 {
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
struct nvc0_screen *screen = nvc0->screen;
@@ -303,11 +304,22 @@ nvc0_compute_upload_input(struct nvc0_context
*nvc0, const void *input)
   /* NOTE: size is limited to 4 KiB, which is <
NV04_PFIFO_MAX_PACKET_LEN */
   BEGIN_1IC0(push, NVC0_CP(CB_POS), 1 + cp->parm_size / 4);
   PUSH_DATA (push, 0);
-  PUSH_DATAp(push, input, cp->parm_size / 4);
-
-  BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
-  PUSH_DATA (push, NVC0_COMPUTE_FLUSH_CB);
+  PUSH_DATAp(push, info->input, cp->parm_size / 4);
}
+
+   BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
+   PUSH_DATA (push, 2048);
+   PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5));
+   PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5));
+   BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
+   PUSH_DATA (push, (15 << 8) | 1);
+   BEGIN_1IC0(push, NVC0_CP(CB_POS), 1 + 1);
+   /* + 0x1c as we only upload work_dim on nvc0, the rest 

Re: [Mesa-dev] [PATCH 1/4] nir: Avoid C99 field initializers.

[Sinclair Yeh]

Maybe add a short commit message for 3/4

Reviewed-by: Sinclair Yeh 

On Thu, Apr 28, 2016 at 12:27:05PM +0100, Jose Fonseca wrote:
> As they are not standard C++ and are not supported by MSVC C++ compiler.
> 
> Just have nir_imm_double match nir_imm_float above.
> ---
>  src/compiler/nir/nir_builder.h | 9 ++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
> index a14f9ef..4fa9779 100644
> --- a/src/compiler/nir/nir_builder.h
> +++ b/src/compiler/nir/nir_builder.h
> @@ -117,9 +117,12 @@ nir_imm_float(nir_builder *build, float x)
>  static inline nir_ssa_def *
>  nir_imm_double(nir_builder *build, double x)
>  {
> -   nir_const_value v = { { .f64 = {x, 0, 0, 0} } };
> -   nir_ssa_def *def = nir_build_imm(build, 1, 64, v);
> -   return def;
> +   nir_const_value v;
> +
> +   memset(, 0, sizeof(v));
> +   v.f64[0] = x;
> +
> +   return nir_build_imm(build, 1, 64, v);
>  }
>  
>  static inline nir_ssa_def *
> -- 
> 2.5.0
> 
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Re: [Mesa-dev] [PATCH 3/3] nouveau: Add support for SV_WORK_DIM

[Samuel Pitoiset]

On 04/28/2016 04:05 PM, Hans de Goede wrote:

Add support for SV_WORK_DIM for nvc0 and nve4.

Signed-off-by: Hans de Goede 
---
Changes in v1 (first non RFC posting):
-Adjust NVC0_CB_AUX_GRID_SIZE for the extra value in grid-info
-Use NVC0_CB_AUX_GRID_SIZE instead of a hardcoded value when
 uploading the grid info
-Also implement SV_WORK_DIM for nvc0
---
 src/gallium/drivers/nouveau/codegen/nv50_ir.h  |  1 +
 .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp  |  1 +
 .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  |  2 ++
 .../nouveau/codegen/nv50_ir_target_nvc0.cpp|  1 +
 src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 24 --
 src/gallium/drivers/nouveau/nvc0/nvc0_context.h|  4 ++--
 src/gallium/drivers/nouveau/nvc0/nvc0_program.c|  2 +-
 src/gallium/drivers/nouveau/nvc0/nve4_compute.c|  7 ---
 8 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 94e54bb..41804b6 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -461,6 +461,7 @@ enum SVSemantic
SV_BASEVERTEX,
SV_BASEINSTANCE,
SV_DRAWID,
+   SV_WORK_DIM,
SV_UNDEFINED,
SV_LAST
 };
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 3708f37..f75f480 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -408,6 +408,7 @@ static nv50_ir::SVSemantic translateSysVal(uint sysval)
case TGSI_SEMANTIC_BASEVERTEX: return nv50_ir::SV_BASEVERTEX;
case TGSI_SEMANTIC_BASEINSTANCE: return nv50_ir::SV_BASEINSTANCE;
case TGSI_SEMANTIC_DRAWID: return nv50_ir::SV_DRAWID;
+   case TGSI_SEMANTIC_WORK_DIM:   return nv50_ir::SV_WORK_DIM;
default:
   assert(0);
   return nv50_ir::SV_CLOCK;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 3bce962..1785623 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -2178,6 +2178,8 @@ NVC0LoweringPass::handleRDSV(Instruction *i)
  i->setSrc(0, bld.mkImm(sv == SV_GRIDID ? 0 : 1));
  return true;
   }
+  // Fallthrough
+   case SV_WORK_DIM:
   addr += prog->driver->prop.cp.gridInfoBase;
   bld.mkLoad(TYPE_U32, i->getDef(0),
  bld.mkSymbol(FILE_MEMORY_CONST, prog->driver->io.auxCBSlot,
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
index 9e1e7bf..80cb9fd 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
@@ -293,6 +293,7 @@ TargetNVC0::getSVAddress(DataFile shaderFile, const Symbol 
*sym) const
case SV_NTID:   return kepler ? (0x00 + idx * 4) : ~0;
case SV_NCTAID: return kepler ? (0x0c + idx * 4) : ~0;
case SV_GRIDID: return kepler ? 0x18 : ~0;
+   case SV_WORK_DIM:   return 0x1c;
case SV_SAMPLE_INDEX:   return 0;
case SV_SAMPLE_POS: return 0;
case SV_SAMPLE_MASK:return 0;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
index bbc8edb..9f85ead 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
@@ -284,7 +284,8 @@ nvc0_state_validate_cp(struct nvc0_context *nvc0, uint32_t 
mask)
 }

 static void
-nvc0_compute_upload_input(struct nvc0_context *nvc0, const void *input)
+nvc0_compute_upload_input(struct nvc0_context *nvc0,
+  const struct pipe_grid_info *info)
 {
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
struct nvc0_screen *screen = nvc0->screen;
@@ -303,11 +304,22 @@ nvc0_compute_upload_input(struct nvc0_context *nvc0, 
const void *input)
   /* NOTE: size is limited to 4 KiB, which is < NV04_PFIFO_MAX_PACKET_LEN 
*/
   BEGIN_1IC0(push, NVC0_CP(CB_POS), 1 + cp->parm_size / 4);
   PUSH_DATA (push, 0);
-  PUSH_DATAp(push, input, cp->parm_size / 4);
-
-  BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
-  PUSH_DATA (push, NVC0_COMPUTE_FLUSH_CB);
+  PUSH_DATAp(push, info->input, cp->parm_size / 4);
}
+
+   BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
+   PUSH_DATA (push, 2048);
+   PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5));
+   PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5));
+   BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
+   PUSH_DATA (push, (15 << 8) | 1);
+   BEGIN_1IC0(push, NVC0_CP(CB_POS), 1 + 1);
+   /* + 0x1c as we only upload work_dim on nvc0, the rest uses special regs */
+   PUSH_DATA (push, 

Re: [Mesa-dev] [PATCH 5/7] i965/disasm: Mark instructions that no longer exist in the opcode_desc tables.

[Iago Toral]

On Thu, 2016-04-28 at 00:19 -0700, Francisco Jerez wrote:
> With this small addition we can now easily determine on which
> generations a given instruction is supported from the opcode_desc
> tables alone.
> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 16 ++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 0125434..5c6f3e2 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -30,6 +30,14 @@
>  #include "brw_inst.h"
>  #include "brw_eu.h"
>  
> +/**
> + * Special opcode_desc entry that marks the instruction as no longer 
> existing.
> + * Unless explicitly specified using this marker a hardware generation is
> + * assumed to have inherited all opcodes defined and not removed by previous
> + * generations.
> + */
> +#define REMOVED { .name = "***removed***", .nsrc = ~0, .ndst = ~0 }
> +
>  static const struct opcode_desc gen4_opcode_descs[128] = {
> [BRW_OPCODE_MOV]  = { .name = "mov", .nsrc = 1, .ndst = 1 },
> [BRW_OPCODE_FRC]  = { .name = "frc", .nsrc = 1, .ndst = 1 },
> @@ -94,6 +102,8 @@ static const struct opcode_desc gen6_opcode_descs[128] = {
> [BRW_OPCODE_MATH] = { .name = "math",.nsrc = 2, .ndst = 1 },
> [BRW_OPCODE_MAD]  = { .name = "mad", .nsrc = 3, .ndst = 1 },
> [BRW_OPCODE_LRP]  = { .name = "lrp", .nsrc = 3, .ndst = 1 },
> +   [BRW_OPCODE_IFF]  = REMOVED,
> +   [BRW_OPCODE_DO]   = REMOVED,
>  };
>  
>  static const struct opcode_desc gen7_opcode_descs[128] = {
> @@ -111,6 +121,8 @@ static const struct opcode_desc gen7_opcode_descs[128] = {
>  };
>  
>  static const struct opcode_desc gen8_opcode_descs[128] = {
> +   [BRW_OPCODE_F32TO16]  = REMOVED,
> +   [BRW_OPCODE_F16TO32]  = REMOVED,
> [BRW_OPCODE_CSEL] = { .name = "csel",.nsrc = 3, .ndst = 1 },
>  };
>  
> @@ -151,7 +163,6 @@ opcode_desc_table_for(const struct brw_device_info 
> *devinfo, enum opcode opcode)
>  
>  /* Return the matching opcode_desc for the specified opcode number and
>   * hardware generation, or NULL if the opcode is not supported by the device.
> - * XXX -- Actually check whether the opcode is supported.
>   */
>  const struct opcode_desc *
>  brw_opcode_desc(const struct brw_device_info *devinfo, enum opcode opcode)
> @@ -159,7 +170,8 @@ brw_opcode_desc(const struct brw_device_info *devinfo, 
> enum opcode opcode)
> const struct opcode_desc *opcode_descs =
>opcode_desc_table_for(devinfo, opcode);
>  
> -   if (opcode_descs)
> +   if (opcode_descs && (opcode_descs[opcode].nsrc != ~0 &&
> +opcode_descs[opcode].ndst != ~0))

This is a nitpick so feel free to ignore it if you want:

Since you encode special removed entries in a macro I think it would be
nicer if the check for whether an entry has been removed is also done
through a similar macro so callers don't need to know how these special
entries are encoded:

#define IS_REMOVED(entry) (entry.nsrc != ~0 && entry.ndst != ~0)

>return _descs[opcode];
> else
>return NULL;


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[Mesa-dev] [PATCH 2/3] clover: Pass work_dim parameter of clEnqueueNDRangeKernel() to driver

[Hans de Goede]

In order to implement get_work_dim() the driver may need to know the
clEnqueueNDRangeKernel() work_dim parameter, so pass it to the driver.

Signed-off-by: Hans de Goede 
---
 src/gallium/include/pipe/p_state.h| 7 +++
 src/gallium/state_trackers/clover/core/kernel.cpp | 1 +
 2 files changed, 8 insertions(+)

diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index 9e466ce..0558348 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -703,6 +703,13 @@ struct pipe_grid_info
void *input;
 
/**
+* Grid number of dimensions, 1-3, e.g. the work_dim parameter passed to
+* clEnqueueNDRangeKernel. Note block[] and grid[] must be padded with
+* 1 for non-used dimensions.
+*/
+   uint work_dim;
+
+   /**
 * Determine the layout of the working block (in thread units) to be used.
 */
uint block[3];
diff --git a/src/gallium/state_trackers/clover/core/kernel.cpp 
b/src/gallium/state_trackers/clover/core/kernel.cpp
index 266d50e..555275c 100644
--- a/src/gallium/state_trackers/clover/core/kernel.cpp
+++ b/src/gallium/state_trackers/clover/core/kernel.cpp
@@ -76,6 +76,7 @@ kernel::launch(command_queue ,
   exec.g_buffers.data(), g_handles.data());
 
// Fill information for the launch_grid() call.
+   info.work_dim = grid_size.size();
copy(pad_vector(q, block_size, 1), info.block);
copy(pad_vector(q, reduced_grid_size, 1), info.grid);
info.pc = find(name_equals(_name), m.syms).offset;
-- 
2.7.4

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[Mesa-dev] [PATCH 3/3] nouveau: Add support for SV_WORK_DIM

[Hans de Goede]

Add support for SV_WORK_DIM for nvc0 and nve4.

Signed-off-by: Hans de Goede 
---
Changes in v1 (first non RFC posting):
-Adjust NVC0_CB_AUX_GRID_SIZE for the extra value in grid-info
-Use NVC0_CB_AUX_GRID_SIZE instead of a hardcoded value when
 uploading the grid info
-Also implement SV_WORK_DIM for nvc0
---
 src/gallium/drivers/nouveau/codegen/nv50_ir.h  |  1 +
 .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp  |  1 +
 .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  |  2 ++
 .../nouveau/codegen/nv50_ir_target_nvc0.cpp|  1 +
 src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 24 --
 src/gallium/drivers/nouveau/nvc0/nvc0_context.h|  4 ++--
 src/gallium/drivers/nouveau/nvc0/nvc0_program.c|  2 +-
 src/gallium/drivers/nouveau/nvc0/nve4_compute.c|  7 ---
 8 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 94e54bb..41804b6 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -461,6 +461,7 @@ enum SVSemantic
SV_BASEVERTEX,
SV_BASEINSTANCE,
SV_DRAWID,
+   SV_WORK_DIM,
SV_UNDEFINED,
SV_LAST
 };
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 3708f37..f75f480 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -408,6 +408,7 @@ static nv50_ir::SVSemantic translateSysVal(uint sysval)
case TGSI_SEMANTIC_BASEVERTEX: return nv50_ir::SV_BASEVERTEX;
case TGSI_SEMANTIC_BASEINSTANCE: return nv50_ir::SV_BASEINSTANCE;
case TGSI_SEMANTIC_DRAWID: return nv50_ir::SV_DRAWID;
+   case TGSI_SEMANTIC_WORK_DIM:   return nv50_ir::SV_WORK_DIM;
default:
   assert(0);
   return nv50_ir::SV_CLOCK;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 3bce962..1785623 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -2178,6 +2178,8 @@ NVC0LoweringPass::handleRDSV(Instruction *i)
  i->setSrc(0, bld.mkImm(sv == SV_GRIDID ? 0 : 1));
  return true;
   }
+  // Fallthrough
+   case SV_WORK_DIM:
   addr += prog->driver->prop.cp.gridInfoBase;
   bld.mkLoad(TYPE_U32, i->getDef(0),
  bld.mkSymbol(FILE_MEMORY_CONST, prog->driver->io.auxCBSlot,
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
index 9e1e7bf..80cb9fd 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
@@ -293,6 +293,7 @@ TargetNVC0::getSVAddress(DataFile shaderFile, const Symbol 
*sym) const
case SV_NTID:   return kepler ? (0x00 + idx * 4) : ~0;
case SV_NCTAID: return kepler ? (0x0c + idx * 4) : ~0;
case SV_GRIDID: return kepler ? 0x18 : ~0;
+   case SV_WORK_DIM:   return 0x1c;
case SV_SAMPLE_INDEX:   return 0;
case SV_SAMPLE_POS: return 0;
case SV_SAMPLE_MASK:return 0;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
index bbc8edb..9f85ead 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
@@ -284,7 +284,8 @@ nvc0_state_validate_cp(struct nvc0_context *nvc0, uint32_t 
mask)
 }
 
 static void
-nvc0_compute_upload_input(struct nvc0_context *nvc0, const void *input)
+nvc0_compute_upload_input(struct nvc0_context *nvc0,
+  const struct pipe_grid_info *info)
 {
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
struct nvc0_screen *screen = nvc0->screen;
@@ -303,11 +304,22 @@ nvc0_compute_upload_input(struct nvc0_context *nvc0, 
const void *input)
   /* NOTE: size is limited to 4 KiB, which is < NV04_PFIFO_MAX_PACKET_LEN 
*/
   BEGIN_1IC0(push, NVC0_CP(CB_POS), 1 + cp->parm_size / 4);
   PUSH_DATA (push, 0);
-  PUSH_DATAp(push, input, cp->parm_size / 4);
-
-  BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
-  PUSH_DATA (push, NVC0_COMPUTE_FLUSH_CB);
+  PUSH_DATAp(push, info->input, cp->parm_size / 4);
}
+
+   BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
+   PUSH_DATA (push, 2048);
+   PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5));
+   PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5));
+   BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
+   PUSH_DATA (push, (15 << 8) | 1);
+   BEGIN_1IC0(push, NVC0_CP(CB_POS), 1 + 1);
+   /* + 0x1c as we only upload work_dim on nvc0, the rest uses special regs */
+   PUSH_DATA (push, NVC0_CB_AUX_GRID_INFO + 0x1c);
+   PUSH_DATA 

[Mesa-dev] [PATCH 1/3] tgsi: Add WORK_DIM System Value

[Hans de Goede]

Add a new WORK_DIM SV type, this is will return the grid dimensions
(1-4) for compute (opencl) kernels.

This is necessary to implement the opencl get_work_dim() function.

Signed-off-by: Hans de Goede 
---
Changes in v1 (first non RFC):
-Document TGSI_SEMANTIC_WORK_DIM in src/gallium/docs/source/tgsi.rst
---
 src/gallium/auxiliary/tgsi/tgsi_strings.c  | 1 +
 src/gallium/docs/source/tgsi.rst   | 8 
 src/gallium/include/pipe/p_shader_tokens.h | 1 +
 3 files changed, 10 insertions(+)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.c 
b/src/gallium/auxiliary/tgsi/tgsi_strings.c
index 894d475..f65d7b4 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_strings.c
@@ -100,6 +100,7 @@ const char *tgsi_semantic_names[TGSI_SEMANTIC_COUNT] =
"HELPER_INVOCATION",
"BASEINSTANCE",
"DRAWID",
+   "WORK_DIM",
 };
 
 const char *tgsi_texture_names[TGSI_TEXTURE_COUNT] =
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index 4315707..8ae5c63 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -3015,6 +3015,14 @@ For vertex shaders, the zero-based index of the current 
draw in a
 component is used.
 
 
+TGSI_SEMANTIC_WORK_DIM
+""
+
+For compute shaders started via opencl this retrieves the work_dim
+parameter to the clEnqueueNDRangeKernel call with which the shader
+was started.
+
+
 Declaration Interpolate
 ^^^
 
diff --git a/src/gallium/include/pipe/p_shader_tokens.h 
b/src/gallium/include/pipe/p_shader_tokens.h
index 514b339..d8ded50 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -200,6 +200,7 @@ enum tgsi_semantic {
TGSI_SEMANTIC_HELPER_INVOCATION,  /**< current invocation is helper */
TGSI_SEMANTIC_BASEINSTANCE,
TGSI_SEMANTIC_DRAWID,
+   TGSI_SEMANTIC_WORK_DIM,/**< opencl get_work_dim value */
TGSI_SEMANTIC_COUNT,   /**< number of semantic values */
 };
 
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 1/4] gbm: Add Android build support

[Emil Velikov]

On 28 April 2016 at 14:34, Rob Herring  wrote:
> On Fri, Apr 22, 2016 at 5:57 PM, Emil Velikov  
> wrote:
>> Hi Rob,
>>
>> On 22 April 2016 at 16:50, Rob Herring  wrote:
>>
>>> --- /dev/null
>>> +++ b/src/gbm/Android.mk
>>
>>> +LOCAL_EXPORT_C_INCLUDE_DIRS := \
>>> +   $(LOCAL_PATH)/main
>>> +
>> You don't need this.
>>
>>> +LOCAL_C_INCLUDES := \
>>> +   $(LOCAL_PATH)/main
>>> +
>>> +ifeq ($(MESA_LOLLIPOP_BUILD),true)
>>> +LOCAL_CFLAGS_32 := 
>>> -DDEFAULT_DRIVER_DIR=\"/system/lib/$(MESA_DRI_MODULE_REL_PATH)\"
>>> +LOCAL_CFLAGS_64 := 
>>> -DDEFAULT_DRIVER_DIR=\"/system/lib64/$(MESA_DRI_MODULE_REL_PATH)\"
>>> +else
>>> +LOCAL_CFLAGS += 
>>> -DDEFAULT_DRIVER_DIR=\"/system/lib/$(MESA_DRI_MODULE_REL_PATH)\"
>>> +endif
>>> +
>> Can you factor out the existing copy from src/egl/Android.mk to
>> $(top)/Android.mk.
>> The following should work ... I think.
>
> It doesn't. AFAICT, defines can either be rules to run or return a
> value for assignment. The only way to do this that I can see is
> including a makefile as $(CLEAR_VARS) is done. I don't think that's
> really worth it. Really, I think the dynamic linker should be fixed
> handle the path difference.
>
> I could just set this for the whole build in Android.common.mk. The
> define would be set everywhere, but that shouldn't really matter.
>
Either one (fixing the dynamic linker or adding it to
Android.common.mk) sounds great imho. The latter is obviously
faster/easier ;-)

Thanks for the extra efford consolidating these !
Emil
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