[Mesa-dev] [Bug 101656] Invalid signal timestamps with EGL_SYNC_NATIVE_FENCE_ANDROID on android

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101656

Gary Wang  changed:

   What|Removed |Added

 CC||gary.c.w...@intel.com

-- 
You are receiving this mail because:
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 101656] Invalid signal timestamps with EGL_SYNC_NATIVE_FENCE_ANDROID on android

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101656

Bug ID: 101656
   Summary: Invalid signal timestamps with
EGL_SYNC_NATIVE_FENCE_ANDROID on android
   Product: Mesa
   Version: 17.1
  Hardware: x86-64 (AMD64)
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: EGL
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: yogesh.mara...@intel.com
QA Contact: mesa-dev@lists.freedesktop.org

Description: I'm using EGL_SYNC_NATIVE_FENCE_ANDROID to create a fence fd in
producer consumer situation. I'm doing this for every buffer, I see that I'm
getting a valid fd every time, I pass that to consumer and on consumer side I
call getSingalTime() on this. This uses SYNC_IOC_FILE_INFO ioctl though libsync
to get time 64 bit timestamp of when fence was signaled. The observation is
sometimes I'm getting lower timestamp for newer fences! 

e.g. fd1 is with Buffer1 later created fd2 is with buffer2, getSignalTime of
fd2 is lower than fd1, glFulsh is called before both fds were obtained (force
signal).

Expectation - timestamps of newer fds should be higher than older fds always.

Some Code

Producer side

EGLDisplay dpy = eglGetCurrentDisplay(); 
EGLSyncKHR sync = eglCreateSyncKHR(dpy,
EGL_SYNC_NATIVE_FENCE_ANDROID, NULL);
if (sync == EGL_NO_SYNC_KHR) {
return UNKNOWN_ERROR;
}
glFlush();
fenceFd = eglDupNativeFenceFDANDROID(dpy, sync);

   eglDestroySyncKHR(dpy, sync);
   if (fenceFd == EGL_NO_NATIVE_FENCE_FD_ANDROID) {
return UNKNOWN_ERROR;
}

Consumer side

if (item->mFence->isValid()) {
status_t err = item->mFence->waitForever("acquireBufferLocked");
if (err != NO_ERROR) {
return err;
}
 }

Is EGL_SYNC_NATIVE_FENCE_ANDROID tested in multiple create, dup, destroy
sequence?

-- 
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 101655] Explicit sync support for android

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101655

Bug ID: 101655
   Summary: Explicit sync support for android
   Product: Mesa
   Version: 17.1
  Hardware: Other
OS: other
Status: NEW
  Severity: normal
  Priority: medium
 Component: EGL
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: yogesh.mara...@intel.com
QA Contact: mesa-dev@lists.freedesktop.org

Description: The explicit sync was introduced in android to have sync fds
passed between user space processes and let user insert waits for buffer
transcations as appropriate. In android, if there is a producer-consumer
scenario in framework and if mesa is being used underneath this explicit sync
wouldn't work because the fence_fd is being forced to -1 before enqueue. The
comments above this assignment clearly state why its doing so, although it
seems old and assumes that consumer will never want use that fd to get a signal
timestamp using libsync apis or wait on that fd. Acquire fence on consumer side
remains always invalid due to this.

File: platform_android.c

Function: droid_window_enqueue_buffer()
...
int fence_fd = -1;
   dri2_surf->window->queueBuffer(dri2_surf->window, dri2_surf->buffer,
  fence_fd);
...


Test case: flatland - provided though aosp under
framworks/native/cmds/flatland is an app that tests explicit functionality on
android. 

Symptoms and Cause: flatland hangs because it tries to do getSignalTime() for
this acquire fence_fd on consumer side and uses that to calculate time elapsed
for doing one frame of particular resolution.

Expectations: 
1. Flatland should work as standalone test case with mesa.
2. To support explicit sync, it should forward a valid fence for a buffer being
enqueued (it can also be a signaled one if buffer is immediately available for
consumption).


I tried, if a sync fence can be created before buffer is enqueued but didnt
find a way because all sync functions seem to be static in nature and exposed
only though egl apis. I don't know if there is any other way to call those
functions (e.g. dri2_create_sync etc.) from platform_android.c directly.

-- 
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 3/3] glsl: disable array splitting for AoA

[Timothy Arceri]

On 30/06/17 12:45, Timothy Arceri wrote:

While it produces functioning code the pass creates worse code
for arrays of arrays. See the comment added in this patch for more
detail.
---
  src/compiler/glsl/opt_array_splitting.cpp | 26 ++
  1 file changed, 26 insertions(+)

diff --git a/src/compiler/glsl/opt_array_splitting.cpp 
b/src/compiler/glsl/opt_array_splitting.cpp
index fb6d77b..b3d4599 100644
--- a/src/compiler/glsl/opt_array_splitting.cpp
+++ b/src/compiler/glsl/opt_array_splitting.cpp
@@ -140,6 +140,32 @@ ir_array_reference_visitor::get_variable_entry(ir_variable 
*var)
 if (var->type->is_unsized_array())
return NULL;
  
+   /* FIXME: arrays of arrays are not handled correctly by this pass so we

+* skip it for now. While the pass will create functioning code it actually
+* produces worse code.
+*
+* For example the array:
+*
+*int[3][2] a;
+*
+* ends up being split up into:
+*
+*int[3][2] a_0;
+*int[3][2] a_1;
+*int[3][2] a_2;
+*
+* And we end up referencing each of these new arrays for example:
+*
+*a[0][1] will be turned into a_0[0][1]
+*a[1][0] will be turned into a_1[1][0]
+*a[2][0] will be turned into a_2[2][0]
+*
+* For now we continue to split AoA of matrices to avoid CTS regressions.
+*/
+   if (var->type->is_array() && var->type->fields.array->is_array() &&
+   !var->type->without_array()->is_matrix())


Actually with the previous patch it can be disabled for AoA of matrices 
too. I've made this change locally.




+  return NULL;
+
 foreach_in_list(variable_entry, entry, >variable_list) {
if (entry->var == var)
   return entry;


___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 25/27] i965: Pretend that CCS modified images are two planes

[Jason Ekstrand]

From: Ben Widawsky 

v2: move is_aux into if block. (Jason)
Use else block instead of goto (Jason)

v3: Fix up logic for is_aux (Ben)
Fix up size calculations and add FIXME (Ben)

v4 (Jason Ekstrand):
Use the aux_pitch in the image instead of calculating it

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 54 +++-
 1 file changed, 33 insertions(+), 21 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 66fd99a..323cd5a 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -757,7 +757,7 @@ intel_query_image(__DRIimage *image, int attrib, int *value)
case __DRI_IMAGE_ATTRIB_FOURCC:
   return intel_lookup_fourcc(image->dri_format, value);
case __DRI_IMAGE_ATTRIB_NUM_PLANES:
-  *value = 1;
+  *value = image->aux_offset ? 2 : 1;
   return true;
case __DRI_IMAGE_ATTRIB_OFFSET:
   *value = image->offset;
@@ -1149,31 +1149,43 @@ intel_from_planar(__DRIimage *parent, int plane, void 
*loaderPrivate)
 struct intel_image_format *f;
 __DRIimage *image;
 
-if (parent == NULL || parent->planar_format == NULL)
-return NULL;
-
-f = parent->planar_format;
-
-if (plane >= f->nplanes)
-return NULL;
-
-width = parent->width >> f->planes[plane].width_shift;
-height = parent->height >> f->planes[plane].height_shift;
-dri_format = f->planes[plane].dri_format;
-index = f->planes[plane].buffer_index;
-offset = parent->offsets[index];
-stride = parent->strides[index];
+if (parent == NULL) {
+   return NULL;
+} else if (parent->planar_format == NULL) {
+   const bool is_aux = parent->aux_offset && plane == 1;
+   if (!is_aux)
+  return NULL;
+
+   width = parent->width;
+   height = parent->height;
+   dri_format = parent->dri_format;
+   offset = parent->aux_offset;
+   stride = parent->aux_pitch;
+} else {
+   /* Planar formats don't support aux buffers/images */
+   assert(!parent->aux_offset);
+   f = parent->planar_format;
+
+   if (plane >= f->nplanes)
+  return NULL;
+
+   width = parent->width >> f->planes[plane].width_shift;
+   height = parent->height >> f->planes[plane].height_shift;
+   dri_format = f->planes[plane].dri_format;
+   index = f->planes[plane].buffer_index;
+   offset = parent->offsets[index];
+   stride = parent->strides[index];
+
+   if (offset + height * stride > parent->bo->size) {
+  _mesa_warning(NULL, "intel_create_sub_image: subimage out of 
bounds");
+  return NULL;
+   }
+}
 
 image = intel_allocate_image(parent->screen, dri_format, loaderPrivate);
 if (image == NULL)
return NULL;
 
-if (offset + height * stride > parent->bo->size) {
-   _mesa_warning(NULL, "intel_create_sub_image: subimage out of bounds");
-   free(image);
-   return NULL;
-}
-
 image->bo = parent->bo;
 brw_bo_reference(parent->bo);
 image->modifier = parent->modifier;
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 19/27] i965/screen: Drop get_tiled_height

[Jason Ekstrand]

It's no longer used.

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 20 +++-
 1 file changed, 3 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index e607e8e..03226af 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -296,14 +296,13 @@ static const struct {
uint32_t tiling;
uint64_t modifier;
unsigned since_gen;
-   unsigned height_align;
 } tiling_modifier_map[] = {
{ .tiling = I915_TILING_NONE, .modifier = DRM_FORMAT_MOD_LINEAR,
- .since_gen = 1, .height_align = 1 },
+ .since_gen = 1 },
{ .tiling = I915_TILING_X, .modifier = I915_FORMAT_MOD_X_TILED,
- .since_gen = 1, .height_align = 8 },
+ .since_gen = 1 },
{ .tiling = I915_TILING_Y, .modifier = I915_FORMAT_MOD_Y_TILED,
- .since_gen = 6, .height_align = 32 },
+ .since_gen = 6 },
 };
 
 static bool
@@ -332,19 +331,6 @@ tiling_to_modifier(uint32_t tiling)
unreachable("tiling_to_modifier received unknown tiling mode");
 }
 
-static unsigned
-get_tiled_height(uint64_t modifier, unsigned height)
-{
-   int i;
-
-   for (i = 0; i < ARRAY_SIZE(tiling_modifier_map); i++) {
-  if (tiling_modifier_map[i].modifier == modifier)
- return ALIGN(height, tiling_modifier_map[i].height_align);
-   }
-
-   unreachable("get_tiled_height received unknown tiling mode");
-}
-
 static void
 intel_image_warn_if_unaligned(__DRIimage *image, const char *func)
 {
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 17/27] i965/screen: Use ISL for allocating image BOs

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 51 ++--
 1 file changed, 29 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 8c0e366..106da55 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -37,6 +37,7 @@
 #include "swrast/s_renderbuffer.h"
 #include "util/ralloc.h"
 #include "brw_defines.h"
+#include "brw_state.h"
 #include "compiler/nir/nir.h"
 
 #include "utils.h"
@@ -318,19 +319,6 @@ modifier_is_supported(uint64_t modifier)
return false;
 }
 
-static uint32_t
-modifier_to_tiling(uint64_t modifier)
-{
-   int i;
-
-   for (i = 0; i < ARRAY_SIZE(tiling_modifier_map); i++) {
-  if (tiling_modifier_map[i].modifier == modifier)
- return tiling_modifier_map[i].tiling;
-   }
-
-   unreachable("modifier_to_tiling should only receive known modifiers");
-}
-
 static uint64_t
 tiling_to_modifier(uint32_t tiling)
 {
@@ -638,10 +626,8 @@ intel_create_image_common(__DRIscreen *dri_screen,
 {
__DRIimage *image;
struct intel_screen *screen = dri_screen->driverPrivate;
-   uint32_t tiling;
uint64_t modifier = DRM_FORMAT_MOD_INVALID;
-   unsigned tiled_height;
-   int cpp;
+   bool ok;
 
/* Callers of this may specify a modifier, or a dri usage, but not both. The
 * newer modifier interface deprecates the older usage flags newer modifier
@@ -671,23 +657,44 @@ intel_create_image_common(__DRIscreen *dri_screen,
  modifier = I915_FORMAT_MOD_X_TILED;
   }
}
-   tiling = modifier_to_tiling(modifier);
-   tiled_height = get_tiled_height(modifier, height);
 
image = intel_allocate_image(screen, format, loaderPrivate);
if (image == NULL)
   return NULL;
 
-   cpp = _mesa_get_format_bytes(image->format);
-   image->bo = brw_bo_alloc_tiled_2d(screen->bufmgr, "image",
- width, tiled_height, cpp, tiling,
- >pitch, 0);
+   const struct isl_drm_modifier_info *mod_info =
+  isl_drm_modifier_get_info(modifier);
+
+   struct isl_surf surf;
+   ok = isl_surf_init(>isl_dev, ,
+  .dim = ISL_SURF_DIM_2D,
+  .format = brw_isl_format_for_mesa_format(image->format),
+  .width = width,
+  .height = height,
+  .depth = 1,
+  .levels = 1,
+  .array_len = 1,
+  .samples = 1,
+  .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
+   ISL_SURF_USAGE_TEXTURE_BIT |
+   ISL_SURF_USAGE_STORAGE_BIT,
+  .tiling_flags = (1 << mod_info->tiling));
+   assert(ok);
+   if (!ok) {
+  free(image);
+  return NULL;
+   }
+
+   image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image", surf.size,
+  isl_tiling_to_i915_tiling(mod_info->tiling),
+  surf.row_pitch, 0);
if (image->bo == NULL) {
   free(image);
   return NULL;
}
image->width = width;
image->height = height;
+   image->pitch = surf.row_pitch;
image->modifier = modifier;
 
return image;
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 24/27] i965/screen: Support import and export of surfaces with CCS

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 55 +---
 1 file changed, 50 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 03226af..66fd99a 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -671,7 +671,21 @@ intel_create_image_common(__DRIscreen *dri_screen,
   return NULL;
}
 
-   image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image", surf.size,
+   struct isl_surf aux_surf;
+   if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
+  ok = isl_surf_get_ccs_surf(>isl_dev, , _surf, 0);
+  assert(ok);
+  if (!ok) {
+ free(image);
+ return NULL;
+  }
+   } else {
+  assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
+  aux_surf.size = 0;
+   }
+
+   image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image",
+  surf.size + aux_surf.size,
   isl_tiling_to_i915_tiling(mod_info->tiling),
   surf.row_pitch, 0);
if (image->bo == NULL) {
@@ -683,6 +697,11 @@ intel_create_image_common(__DRIscreen *dri_screen,
image->pitch = surf.row_pitch;
image->modifier = modifier;
 
+   if (aux_surf.size) {
+  image->aux_offset = surf.size;
+  image->aux_pitch = aux_surf.row_pitch;
+   }
+
return image;
 }
 
@@ -896,18 +915,18 @@ intel_create_image_from_fds_common(__DRIscreen 
*dri_screen,
else
   image->modifier = tiling_to_modifier(image->bo->tiling_mode);
 
+   const struct isl_drm_modifier_info *mod_info =
+  isl_drm_modifier_get_info(image->modifier);
+
int size = 0;
+   struct isl_surf surf;
for (i = 0; i < f->nplanes; i++) {
   index = f->planes[i].buffer_index;
   image->offsets[index] = offsets[index];
   image->strides[index] = strides[index];
 
-  const struct isl_drm_modifier_info *mod_info =
- isl_drm_modifier_get_info(image->modifier);
-
   mesa_format format = driImageFormatToGLFormat(f->planes[i].dri_format);
 
-  struct isl_surf surf;
   ok = isl_surf_init(>isl_dev, ,
  .dim = ISL_SURF_DIM_2D,
  .format = brw_isl_format_for_mesa_format(format),
@@ -933,6 +952,32 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen,
  size = end;
}
 
+   if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
+  /* Even though we initialize surf in the loop above, we know that
+   * anything with CCS_E will have exactly one plane so surf is properly
+   * initialized when we get here.
+   */
+  assert(f->nplanes == 1);
+
+  image->aux_offset = offsets[1];
+  image->aux_pitch = strides[1];
+
+  struct isl_surf aux_surf;
+  ok = isl_surf_get_ccs_surf(>isl_dev, , _surf,
+ image->aux_pitch);
+  if (!ok) {
+ brw_bo_unreference(image->bo);
+ free(image);
+ return NULL;
+  }
+
+  const int end = image->aux_offset + aux_surf.size;
+  if (size < end)
+ size = end;
+   } else {
+  assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
+   }
+
/* Check that the requested image actually fits within the BO. 'size'
 * is already relative to the offsets, so we don't need to add that. */
if (image->bo->size == 0) {
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 13/27] i965/miptree: Move CCS allocation into create_for_dri_image

[Jason Ekstrand]

Any form of CCS on gen9+ only works on Y-tiled images.  The only caller
of create_for_bo which uses Y-tiled BOs is create_for_dri_image.

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 25 -
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 3c37fe3..575f04f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -979,21 +979,9 @@ intel_miptree_create_for_bo(struct brw_context *brw,
mt->offset = offset;
mt->tiling = tiling;
 
-   if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX)) {
+   if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
   intel_miptree_choose_aux_usage(brw, mt);
 
-  /* Since CCS_E can compress more than just clear color, we create the
-   * CCS for it up-front.  For CCS_D which only compresses clears, we
-   * create the CCS on-demand when a clear occurs that wants one.
-   */
-  if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
- if (!intel_miptree_alloc_ccs(brw, mt)) {
-intel_miptree_release();
-return NULL;
- }
-  }
-   }
-
return mt;
 }
 
@@ -1129,6 +1117,17 @@ intel_miptree_create_for_dri_image(struct brw_context 
*brw,
   }
}
 
+   /* Since CCS_E can compress more than just clear color, we create the CCS
+* for it up-front.  For CCS_D which only compresses clears, we create the
+* CCS on-demand when a clear occurs that wants one.
+*/
+   if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
+  if (!intel_miptree_alloc_ccs(brw, mt)) {
+ intel_miptree_release();
+ return NULL;
+  }
+   }
+
return mt;
 }
 
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 23/27] intel/isl: Add a row_pitch parameter to surf_get_ccs_surf

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/intel/isl/isl.c   | 4 +++-
 src/intel/isl/isl.h   | 3 ++-
 src/intel/vulkan/anv_image.c  | 2 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 --
 4 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index bbbdb19..8d20e1d 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1688,7 +1688,8 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
 bool
 isl_surf_get_ccs_surf(const struct isl_device *dev,
   const struct isl_surf *surf,
-  struct isl_surf *ccs_surf)
+  struct isl_surf *ccs_surf,
+  uint32_t row_pitch)
 {
assert(surf->samples == 1 && surf->msaa_layout == ISL_MSAA_LAYOUT_NONE);
assert(ISL_DEV_GEN(dev) >= 7);
@@ -1750,6 +1751,7 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
 .levels = levels,
 .array_len = array_len,
 .samples = 1,
+.row_pitch = row_pitch,
 .usage = ISL_SURF_USAGE_CCS_BIT,
 .tiling_flags = ISL_TILING_CCS_BIT);
 }
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index dd550c3..d81df31 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1630,7 +1630,8 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
 bool
 isl_surf_get_ccs_surf(const struct isl_device *dev,
   const struct isl_surf *surf,
-  struct isl_surf *ccs_surf);
+  struct isl_surf *ccs_surf,
+  uint32_t row_pitch /**< Ignored if 0 */);
 
 #define isl_surf_fill_state(dev, state, ...) \
isl_surf_fill_state_s((dev), (state), \
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index c84fc8d..953dbb0 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -211,7 +211,7 @@ make_surface(const struct anv_device *dev,
   if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC)) {
  assert(image->aux_surface.isl.size == 0);
  ok = isl_surf_get_ccs_surf(>isl_dev, _surf->isl,
->aux_surface.isl);
+>aux_surface.isl, 0);
  if (ok) {
 add_surface(image, >aux_surface);
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 7a22cbf..d15dd06 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1061,7 +1061,8 @@ create_ccs_buf_for_image(struct brw_context *brw,
assert(!mt->mcs_buf);
 
intel_miptree_get_isl_surf(brw, mt, _main_surf);
-   if (!isl_surf_get_ccs_surf(>isl_dev, _main_surf, _ccs_surf))
+   if (!isl_surf_get_ccs_surf(>isl_dev, _main_surf,
+  _ccs_surf, 0))
   return false;
 
assert(temp_ccs_surf.size <= image->bo->size - image->aux_offset);
@@ -1986,7 +1987,8 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
 * calculate equivalent CCS surface against it.
 */
intel_miptree_get_isl_surf(brw, mt, _main_surf);
-   if (!isl_surf_get_ccs_surf(>isl_dev, _main_surf, _ccs_surf))
+   if (!isl_surf_get_ccs_surf(>isl_dev, _main_surf,
+  _ccs_surf, 0))
   return false;
 
assert(temp_ccs_surf.size &&
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 27/27] i965: Advertise the CCS modifier

[Jason Ekstrand]

From: Ben Widawsky 

v2: Rename modifier to be more smart (Jason)

FINISHME: Use the kernel's final choice for the fb modifier

bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) 
~/scripts/measure_bandwidth.sh ./kmscube none
Read bandwidth: 603.91 MiB/s
Write bandwidth: 615.28 MiB/s
bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) 
~/scripts/measure_bandwidth.sh ./kmscube ytile
Read bandwidth: 571.13 MiB/s
Write bandwidth: 555.51 MiB/s
bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) 
~/scripts/measure_bandwidth.sh ./kmscube ccs
Read bandwidth: 259.34 MiB/s
Write bandwidth: 337.83 MiB/s

v2: Move all references to the new fourcc code(s) to this patch.
v3: Rebase, remove Yf_CCS (Daniel)

Cc: Jason Ekstrand 
Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 323cd5a..1729f6a 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -51,6 +51,10 @@
 #define DRM_FORMAT_MOD_LINEAR 0
 #endif
 
+#ifndef I915_FORMAT_MOD_Y_TILED_CCS
+#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
+#endif
+
 static const __DRIconfigOptionsExtension brw_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
.xml =
@@ -303,6 +307,8 @@ static const struct {
  .since_gen = 1 },
{ .tiling = I915_TILING_Y, .modifier = I915_FORMAT_MOD_Y_TILED,
  .since_gen = 6 },
+   { .tiling = I915_TILING_Y, .modifier = I915_FORMAT_MOD_Y_TILED_CCS,
+ .since_gen = 9 },
 };
 
 static bool
@@ -566,6 +572,7 @@ enum modifier_priority {
MODIFIER_PRIORITY_LINEAR,
MODIFIER_PRIORITY_X,
MODIFIER_PRIORITY_Y,
+   MODIFIER_PRIORITY_Y_CCS,
 };
 
 const uint64_t priority_to_modifier[] = {
@@ -573,6 +580,7 @@ const uint64_t priority_to_modifier[] = {
[MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
[MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
[MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
+   [MODIFIER_PRIORITY_Y_CCS] =  /* I915_FORMAT_MOD_Y_TILED_CCS */ 
fourcc_mod_code(INTEL, 4),
 };
 
 static uint64_t
@@ -584,6 +592,9 @@ select_best_modifier(struct gen_device_info *devinfo,
 
for (int i = 0; i < count; i++) {
   switch (modifiers[i]) {
+  case /* I915_FORMAT_MOD_Y_TILED_CCS */ fourcc_mod_code(INTEL, 4):
+ prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
+ break;
   case I915_FORMAT_MOD_Y_TILED:
  prio = MAX2(prio, MODIFIER_PRIORITY_Y);
  break;
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 26/27] i965/miptree: More conservatively resolve external images

[Jason Ekstrand]

Instead of always doing a full resolve, only resolve the bits that are
needed.  This means that we only do a partial resolve when the miptree
modifier is I915_FORMAT_MOD_Y_TILED_CCS.

Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_context.c   |  2 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 37 +++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  9 +++
 3 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 2525320..f086ed1 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1338,7 +1338,7 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
   if (rb->mt->num_samples <= 1) {
  assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
 rb->layer_count == 1);
- intel_miptree_prepare_access(brw, rb->mt, 0, 1, 0, 1, false, false);
+ intel_miptree_prepare_external(brw, rb->mt);
   } else {
  intel_renderbuffer_downsample(brw, rb);
   }
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d15dd06..8b5ac9f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -48,6 +48,10 @@
 
 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
 
+#ifndef DRM_FORMAT_MOD_INVALID
+#define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
+#endif
+
 static void *intel_miptree_map_raw(struct brw_context *brw,
struct intel_mipmap_tree *mt,
GLbitfield mode);
@@ -365,6 +369,7 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
mt->is_scanout = (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) != 0;
+   mt->drm_modifier = DRM_FORMAT_MOD_INVALID;
mt->aux_usage = ISL_AUX_USAGE_NONE;
mt->supports_fast_clear = false;
mt->aux_state = NULL;
@@ -1028,6 +1033,8 @@ miptree_create_for_planar_image(struct brw_context *brw,
  planar_mt->plane[i - 1] = mt;
}
 
+   planar_mt->drm_modifier = image->modifier;
+
return planar_mt;
 }
 
@@ -1179,6 +1186,7 @@ intel_miptree_create_for_dri_image(struct brw_context 
*brw,
mt->level[0].slice[0].y_offset = image->tile_y;
mt->total_width += image->tile_x;
mt->total_height += image->tile_y;
+   mt->drm_modifier = image->modifier;
 
/* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier 
which has
@@ -2808,6 +2816,35 @@ intel_miptree_finish_depth(struct brw_context *brw,
}
 }
 
+void
+intel_miptree_prepare_external(struct brw_context *brw,
+   struct intel_mipmap_tree *mt)
+{
+   bool supports_aux = false, supports_fast_clear = false;
+
+   const struct isl_drm_modifier_info *mod_info =
+  isl_drm_modifier_get_info(mt->drm_modifier);
+
+   if (mod_info && mod_info->aux_usage != ISL_AUX_USAGE_NONE) {
+  /* CCS_E is the only supported aux for external images and it's only
+   * supported on very simple images.
+   */
+  assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
+  assert(_mesa_is_format_color_format(mt->format));
+  assert(mt->first_level == mt->last_level);
+  assert(mt->logical_depth0 == 1);
+  assert(mt->num_samples <= 1);
+  assert(mt->mcs_buf != NULL);
+
+  supports_aux = true;
+  supports_fast_clear = mod_info->supports_clear_color;
+   }
+
+   intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS,
+0, INTEL_REMAINING_LAYERS,
+supports_aux, supports_fast_clear);
+}
+
 /**
  * Make it possible to share the BO backing the given miptree with another
  * process or another miptree.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index c4ed525..c1bd3af 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -636,6 +636,12 @@ struct intel_mipmap_tree
 */
bool is_scanout;
 
+   /**
+* For external surfaces, this is DRM format modifier that was used to
+* create or import the surface.
+*/
+   uint64_t drm_modifier;
+
/* These are also refcounted:
 */
GLuint refcount;
@@ -957,6 +963,9 @@ intel_miptree_finish_depth(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
bool depth_written);
+void
+intel_miptree_prepare_external(struct brw_context *brw,
+   struct intel_mipmap_tree *mt);
 
 void
 intel_miptree_make_shareable(struct brw_context *brw,
-- 
2.5.0.400.gff86faf

[Mesa-dev] [PATCH v2 21/27] i965: Support images with aux buffers

[Jason Ekstrand]

From: Ben Widawsky 

Previously images did not support any auxiliary compression surfaces
(CCS, MCS, or HiZ).  That's about to change.  This patch just adds the
fields to __DRIimageRec to make auxiliary surfaces possible.

v2 (Jason Ekstrand):
 - Add an aux_pitch parameter as well as aux_offset

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_image.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_image.h 
b/src/mesa/drivers/dri/i965/intel_image.h
index cf06105..5ac5c31 100644
--- a/src/mesa/drivers/dri/i965/intel_image.h
+++ b/src/mesa/drivers/dri/i965/intel_image.h
@@ -92,6 +92,12 @@ struct __DRIimageRec {
/** The image was created with EGL_EXT_image_dma_buf_import. */
bool dma_buf_imported;
 
+   /** Offset of the auxiliary compression surface in the bo. */
+   uint32_t aux_offset;
+
+   /** Pitch of the auxiliary compression surface. */
+   uint32_t aux_pitch;
+
/**
 * Provided by EGL_EXT_image_dma_buf_import.
 * \{
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 12/27] i965: Use create_for_dri_image in intel_update_image_buffer

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/mesa/drivers/dri/i965/brw_context.c | 23 ++-
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 53e1a85..1c7cf90 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1702,16 +1702,21 @@ intel_update_image_buffer(struct brw_context *intel,
if (last_mt && last_mt->bo == buffer->bo)
   return;
 
+   enum isl_colorspace colorspace;
+   switch (_mesa_get_format_color_encoding(intel_rb_format(rb))) {
+   case GL_SRGB:
+  colorspace = ISL_COLORSPACE_SRGB;
+  break;
+   case GL_LINEAR:
+  colorspace = ISL_COLORSPACE_LINEAR;
+  break;
+   default:
+  unreachable("Invalid color encoding");
+   }
+
struct intel_mipmap_tree *mt =
-  intel_miptree_create_for_bo(intel,
-  buffer->bo,
-  intel_rb_format(rb),
-  0,
-  buffer->width,
-  buffer->height,
-  1,
-  buffer->pitch,
-  MIPTREE_LAYOUT_FOR_SCANOUT);
+  intel_miptree_create_for_dri_image(intel, buffer, GL_TEXTURE_2D,
+ colorspace, true);
if (!mt)
   return;
 
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 22/27] i965/miptree: Allocate mcs_buf for an image's CCS

[Jason Ekstrand]

From: Ben Widawsky 

This code will disable actually creating these buffers for the scanout,
but it puts the allocation in place.

Primarily this patch is split out for review, it can be squashed in
later if preferred.

v2:
assert(mt->offset == 0) in ccs creation (as requested by Topi)
Remove bogus is_scanout check in miptree_release

v3:
Remove is_scanout assert in intel_miptree_create. It doesn't work with
latest codebase - not sure it ever should have worked.

v4:
assert(mt->last_level == 0) and assert(mt->first_level == 0) in ccs setup
(Topi)

v5 (Jason Ekstrand):
 - Base the decision to allocate a CCS on the image modifier

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 123 +++---
 1 file changed, 113 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 575f04f..7a22cbf 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -59,6 +59,11 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
 struct intel_mipmap_tree *mt,
 GLuint num_samples);
 
+static void
+intel_miptree_init_mcs(struct brw_context *brw,
+   struct intel_mipmap_tree *mt,
+   int init_value);
+
 /**
  * Determine which MSAA layout should be used by the MSAA surface being
  * created, based on the chip generation and the surface type.
@@ -1026,6 +1031,67 @@ miptree_create_for_planar_image(struct brw_context *brw,
return planar_mt;
 }
 
+static bool
+create_ccs_buf_for_image(struct brw_context *brw,
+ __DRIimage *image,
+ struct intel_mipmap_tree *mt,
+ enum isl_aux_state initial_state)
+{
+   struct isl_surf temp_main_surf, temp_ccs_surf;
+
+   /* There isn't anything specifically wrong with there being an offset, in
+* which case, the CCS miptree's offset should be mt->offset +
+* image->aux_offset. However, the code today only will have an offset when
+* this miptree is pointing to a slice from another miptree, and in that 
case
+* we'd need to offset within the AUX CCS buffer properly. It's questionable
+* whether our code handles that case properly, and since it can never 
happen
+* for scanout, just use the assertion to prevent it.
+*/
+   assert(mt->offset == 0);
+
+   /* CCS is only supported for very simple miptrees */
+   assert(image->aux_offset && image->aux_pitch);
+   assert(image->tile_x == 0 && image->tile_y == 0);
+   assert(mt->num_samples <= 1);
+   assert(mt->first_level == 0);
+   assert(mt->last_level == 0);
+   assert(mt->logical_depth0 == 1);
+
+   /* We shouldn't already have a CCS */
+   assert(!mt->mcs_buf);
+
+   intel_miptree_get_isl_surf(brw, mt, _main_surf);
+   if (!isl_surf_get_ccs_surf(>isl_dev, _main_surf, _ccs_surf))
+  return false;
+
+   assert(temp_ccs_surf.size <= image->bo->size - image->aux_offset);
+   assert(temp_ccs_surf.row_pitch <= image->aux_pitch);
+
+   mt->mcs_buf = calloc(sizeof(*mt->mcs_buf), 1);
+   if (mt->mcs_buf == NULL)
+  return false;
+
+   mt->aux_state = create_aux_state_map(mt, initial_state);
+   if (!mt->aux_state) {
+  free(mt->mcs_buf);
+  mt->mcs_buf = NULL;
+  return false;
+   }
+
+   mt->mcs_buf->bo = image->bo;
+   brw_bo_reference(image->bo);
+
+   mt->mcs_buf->offset = image->aux_offset;
+   mt->mcs_buf->size = image->bo->size - image->aux_offset;
+   mt->mcs_buf->pitch = image->aux_pitch;
+   mt->mcs_buf->qpitch = 0;
+
+   intel_miptree_init_mcs(brw, mt, 0);
+   mt->msaa_layout = INTEL_MSAA_LAYOUT_CMS;
+
+   return true;
+}
+
 struct intel_mipmap_tree *
 intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image, GLenum target,
@@ -1072,15 +1138,26 @@ intel_miptree_create_for_dri_image(struct brw_context 
*brw,
if (!brw->ctx.TextureFormatSupported[format])
   return NULL;
 
+   const struct isl_drm_modifier_info *mod_info =
+  isl_drm_modifier_get_info(image->modifier);
+
+   uint32_t mt_layout_flags = 0;
+
+   /* If this image comes in from a window system, then it may get promoted to
+* scanout at any time so we need to set the flag accordingly.
+*/
+   if (is_winsys_image)
+  mt_layout_flags |= MIPTREE_LAYOUT_FOR_SCANOUT;
+
/* If this image comes in from a window system, we have different
 * requirements than if it comes in via an EGL import operation.  Window
 * system images can use any form of auxiliary compression we wish because
 * they get "flushed" before being handed off to the window system and we
-* have the opportunity to do resolves.  Window system buffers also may be
-* used for scanout so we 

[Mesa-dev] [PATCH v2 20/27] intel/isl: Add support for I915_FORMAT_MOD_Y_TILED_CCS

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/intel/isl/isl_drm.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
index b7a4997..db72a34 100644
--- a/src/intel/isl/isl_drm.c
+++ b/src/intel/isl/isl_drm.c
@@ -54,6 +54,10 @@ isl_tiling_to_i915_tiling(enum isl_tiling tiling)
unreachable("Invalid ISL tiling");
 }
 
+#ifndef I915_FORMAT_MOD_Y_TILED_CCS
+#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
+#endif
+
 struct isl_drm_modifier_info modifier_info[] = {
{
   .modifier = DRM_FORMAT_MOD_NONE,
@@ -70,6 +74,13 @@ struct isl_drm_modifier_info modifier_info[] = {
   .name = "I915_FORMAT_MOD_Y_TILED",
   .tiling = ISL_TILING_Y0,
},
+   {
+  .modifier = I915_FORMAT_MOD_Y_TILED_CCS,
+  .name = "I915_FORMAT_MOD_Y_TILED_CCS",
+  .tiling = ISL_TILING_Y0,
+  .aux_usage = ISL_AUX_USAGE_CCS_E,
+  .supports_clear_color = false,
+   },
 };
 
 const struct isl_drm_modifier_info *
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 18/27] i965/screen: Use ISL for doing image import checks

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 32 
 1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 106da55..e607e8e 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -857,8 +857,8 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen,
struct intel_screen *screen = dri_screen->driverPrivate;
struct intel_image_format *f;
__DRIimage *image;
-   unsigned tiled_height;
int i, index;
+   bool ok;
 
if (fds == NULL || num_fds < 1)
   return NULL;
@@ -909,7 +909,6 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen,
   image->modifier = modifier;
else
   image->modifier = tiling_to_modifier(image->bo->tiling_mode);
-   tiled_height = get_tiled_height(image->modifier, height);
 
int size = 0;
for (i = 0; i < f->nplanes; i++) {
@@ -917,8 +916,33 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen,
   image->offsets[index] = offsets[index];
   image->strides[index] = strides[index];
 
-  const int plane_height = tiled_height >> f->planes[i].height_shift;
-  const int end = offsets[index] + plane_height * strides[index];
+  const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(image->modifier);
+
+  mesa_format format = driImageFormatToGLFormat(f->planes[i].dri_format);
+
+  struct isl_surf surf;
+  ok = isl_surf_init(>isl_dev, ,
+ .dim = ISL_SURF_DIM_2D,
+ .format = brw_isl_format_for_mesa_format(format),
+ .width = image->width >> f->planes[i].width_shift,
+ .height = image->height >> f->planes[i].height_shift,
+ .depth = 1,
+ .levels = 1,
+ .array_len = 1,
+ .samples = 1,
+ .row_pitch = strides[index],
+ .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
+  ISL_SURF_USAGE_TEXTURE_BIT |
+  ISL_SURF_USAGE_STORAGE_BIT,
+ .tiling_flags = (1 << mod_info->tiling));
+  if (!ok) {
+ brw_bo_unreference(image->bo);
+ free(image);
+ return NULL;
+  }
+
+  const int end = offsets[index] + surf.size;
   if (size < end)
  size = end;
}
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 07/27] i965/miptree: Allocate mt earlier in update winsys

[Jason Ekstrand]

From: Ben Widawsky 

Later commits require intel_update_image_buffer() to have control over
the miptree creation.   However, intel_update_winsys_renderbuffer_miptree()
currently  creates it based on the given buffer object. This patch moves
the creation to the caller side.

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/mesa/drivers/dri/i965/brw_context.c   | 37 ---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16 ++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  2 +-
 3 files changed, 37 insertions(+), 18 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 5fb2964..53e1a85 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1625,10 +1625,26 @@ intel_process_dri2_buffer(struct brw_context *brw,
   return;
}
 
-   if (!intel_update_winsys_renderbuffer_miptree(brw, rb, bo,
+   struct intel_mipmap_tree *mt =
+  intel_miptree_create_for_bo(brw,
+  bo,
+  intel_rb_format(rb),
+  0,
+  drawable->w,
+  drawable->h,
+  1,
+  buffer->pitch,
+  MIPTREE_LAYOUT_FOR_SCANOUT);
+   if (!mt) {
+  brw_bo_unreference(bo);
+  return;
+   }
+
+   if (!intel_update_winsys_renderbuffer_miptree(brw, rb, mt,
  drawable->w, drawable->h,
  buffer->pitch)) {
   brw_bo_unreference(bo);
+  intel_miptree_release();
   return;
}
 
@@ -1686,10 +1702,25 @@ intel_update_image_buffer(struct brw_context *intel,
if (last_mt && last_mt->bo == buffer->bo)
   return;
 
-   if (!intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
+   struct intel_mipmap_tree *mt =
+  intel_miptree_create_for_bo(intel,
+  buffer->bo,
+  intel_rb_format(rb),
+  0,
+  buffer->width,
+  buffer->height,
+  1,
+  buffer->pitch,
+  MIPTREE_LAYOUT_FOR_SCANOUT);
+   if (!mt)
+  return;
+
+   if (!intel_update_winsys_renderbuffer_miptree(intel, rb, mt,
  buffer->width, buffer->height,
- buffer->pitch))
+ buffer->pitch)) {
+  intel_miptree_release();
   return;
+   }
 
if (_mesa_is_front_buffer_drawing(fb) &&
buffer_type == __DRI_IMAGE_BUFFER_FRONT &&
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c018c7f..f1ac074 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1115,11 +1115,10 @@ intel_miptree_create_for_dri_image(struct brw_context 
*brw,
 bool
 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
  struct intel_renderbuffer *irb,
- struct brw_bo *bo,
+ struct intel_mipmap_tree 
*singlesample_mt,
  uint32_t width, uint32_t height,
  uint32_t pitch)
 {
-   struct intel_mipmap_tree *singlesample_mt = NULL;
struct intel_mipmap_tree *multisample_mt = NULL;
struct gl_renderbuffer *rb = >Base.Base;
mesa_format format = rb->Format;
@@ -1131,17 +1130,7 @@ intel_update_winsys_renderbuffer_miptree(struct 
brw_context *intel,
assert(_mesa_get_format_base_format(format) == GL_RGB ||
   _mesa_get_format_base_format(format) == GL_RGBA);
 
-   singlesample_mt = intel_miptree_create_for_bo(intel,
- bo,
- format,
- 0,
- width,
- height,
- 1,
- pitch,
- MIPTREE_LAYOUT_FOR_SCANOUT);
-   if (!singlesample_mt)
-  goto fail;
+   assert(singlesample_mt);
 
if (num_samples == 0) {
   intel_miptree_release(>mt);
@@ -1171,7 +1160,6 

[Mesa-dev] [PATCH v2 16/27] intel/isl: Add a helper to convert tilings from ISL to i915

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/intel/isl/isl.h |  3 +++
 src/intel/isl/isl_drm.c | 25 +
 2 files changed, 28 insertions(+)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 563bcfb..dd550c3 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1513,6 +1513,9 @@ isl_tiling_is_std_y(enum isl_tiling tiling)
return (1u << tiling) & ISL_TILING_STD_Y_MASK;
 }
 
+uint32_t
+isl_tiling_to_i915_tiling(enum isl_tiling tiling);
+
 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
 isl_drm_modifier_get_info(uint64_t modifier);
 
diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
index 8fccc40..b7a4997 100644
--- a/src/intel/isl/isl_drm.c
+++ b/src/intel/isl/isl_drm.c
@@ -25,10 +25,35 @@
 #include 
 
 #include 
+#include 
 
 #include "isl.h"
 #include "common/gen_device_info.h"
 
+uint32_t
+isl_tiling_to_i915_tiling(enum isl_tiling tiling)
+{
+   switch (tiling) {
+   case ISL_TILING_LINEAR:
+  return I915_TILING_NONE;
+
+   case ISL_TILING_X:
+  return I915_TILING_X;
+
+   case ISL_TILING_Y0:
+  return I915_TILING_Y;
+
+   case ISL_TILING_W:
+   case ISL_TILING_Yf:
+   case ISL_TILING_Ys:
+   case ISL_TILING_HIZ:
+   case ISL_TILING_CCS:
+  return I915_TILING_NONE;
+   }
+
+   unreachable("Invalid ISL tiling");
+}
+
 struct isl_drm_modifier_info modifier_info[] = {
{
   .modifier = DRM_FORMAT_MOD_NONE,
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 08/27] main/formats: Autogenerate _mesa_get_srgb_format_linear

[Jason Ekstrand]

---
 src/mesa/main/format_fallback.py |  46 +++
 src/mesa/main/formats.c  | 117 ---
 2 files changed, 46 insertions(+), 117 deletions(-)

diff --git a/src/mesa/main/format_fallback.py b/src/mesa/main/format_fallback.py
index e3b9916..ec86938 100644
--- a/src/mesa/main/format_fallback.py
+++ b/src/mesa/main/format_fallback.py
@@ -38,6 +38,34 @@ def parse_args():
 p.add_argument("out")
 return p.parse_args()
 
+def get_unorm_to_srgb_map(formats):
+names = {fmt.name for fmt in formats}
+
+for fmt in formats:
+if fmt.colorspace != 'srgb':
+continue;
+
+replacements = [
+('SRGB', 'RGB'),
+('SRGB', 'UNORM'),
+('SRGB8_ALPHA8', 'RGBA'),
+('SRGB8_ALPHA8', 'RGBA8'),
+('SRGB_ALPHA_UNORM', 'RGBA_UNORM'),
+]
+found_unorm_name = False
+for rep in replacements:
+if fmt.name.find(rep[0]) == -1:
+continue
+
+unorm_name = fmt.name.replace(rep[0], rep[1])
+if unorm_name in names:
+yield unorm_name, fmt.name
+found_unorm_name = True
+break
+
+# Every sRGB format MUST have a UNORM equivalent
+assert found_unorm_name
+
 def get_rgbx_to_rgba_map(formats):
 names = {fmt.name for fmt in formats}
 
@@ -61,6 +89,23 @@ TEMPLATE = Template(COPYRIGHT + """
 #include "formats.h"
 
 /**
+ * For an sRGB format, return the corresponding linear color space format.
+ * For non-sRGB formats, return the format as-is.
+ */
+mesa_format
+_mesa_get_srgb_format_linear(mesa_format format)
+{
+   switch (format) {
+%for unorm, srgb in unorm_to_srgb_map:
+   case ${srgb}:
+  return ${unorm};
+%endfor
+   default:
+  return format;
+   }
+}
+
+/**
  * If the format has an alpha channel, and there exists a non-alpha
  * variant of the format with an identical bit layout, then return
  * the non-alpha format. Otherwise return the original format.
@@ -94,6 +139,7 @@ def main():
 formats = list(format_parser.parse(pargs.csv))
 
 template_env = {
+'unorm_to_srgb_map': list(get_unorm_to_srgb_map(formats)),
 'rgbx_to_rgba_map': list(get_rgbx_to_rgba_map(formats)),
 }
 
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 9d9830f..5c29d37 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -622,123 +622,6 @@ _mesa_is_format_etc2(mesa_format format)
 
 
 /**
- * For an sRGB format, return the corresponding linear color space format.
- * For non-sRGB formats, return the format as-is.
- */
-mesa_format
-_mesa_get_srgb_format_linear(mesa_format format)
-{
-   switch (format) {
-   case MESA_FORMAT_BGR_SRGB8:
-  format = MESA_FORMAT_BGR_UNORM8;
-  break;
-   case MESA_FORMAT_A8B8G8R8_SRGB:
-  format = MESA_FORMAT_A8B8G8R8_UNORM;
-  break;
-   case MESA_FORMAT_B8G8R8A8_SRGB:
-  format = MESA_FORMAT_B8G8R8A8_UNORM;
-  break;
-   case MESA_FORMAT_A8R8G8B8_SRGB:
-  format = MESA_FORMAT_A8R8G8B8_UNORM;
-  break;
-   case MESA_FORMAT_R8G8B8A8_SRGB:
-  format = MESA_FORMAT_R8G8B8A8_UNORM;
-  break;
-   case MESA_FORMAT_L_SRGB8:
-  format = MESA_FORMAT_L_UNORM8;
-  break;
-   case MESA_FORMAT_L8A8_SRGB:
-  format = MESA_FORMAT_L8A8_UNORM;
-  break;
-   case MESA_FORMAT_A8L8_SRGB:
-  format = MESA_FORMAT_A8L8_UNORM;
-  break;
-   case MESA_FORMAT_SRGB_DXT1:
-  format = MESA_FORMAT_RGB_DXT1;
-  break;
-   case MESA_FORMAT_SRGBA_DXT1:
-  format = MESA_FORMAT_RGBA_DXT1;
-  break;
-   case MESA_FORMAT_SRGBA_DXT3:
-  format = MESA_FORMAT_RGBA_DXT3;
-  break;
-   case MESA_FORMAT_SRGBA_DXT5:
-  format = MESA_FORMAT_RGBA_DXT5;
-  break;
-   case MESA_FORMAT_R8G8B8X8_SRGB:
-  format = MESA_FORMAT_R8G8B8X8_UNORM;
-  break;
-   case MESA_FORMAT_X8B8G8R8_SRGB:
-  format = MESA_FORMAT_X8B8G8R8_UNORM;
-  break;
-   case MESA_FORMAT_ETC2_SRGB8:
-  format = MESA_FORMAT_ETC2_RGB8;
-  break;
-   case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC:
-  format = MESA_FORMAT_ETC2_RGBA8_EAC;
-  break;
-   case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1:
-  format = MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1;
-  break;
-   case MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM:
-  format = MESA_FORMAT_BPTC_RGBA_UNORM;
-  break;
-   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4:
-  format = MESA_FORMAT_RGBA_ASTC_4x4;
-  break;
-   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4:
-  format = MESA_FORMAT_RGBA_ASTC_5x4;
-  break;
-   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5:
-  format = MESA_FORMAT_RGBA_ASTC_5x5;
-  break;
-   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5:
-  format = MESA_FORMAT_RGBA_ASTC_6x5;
-  break;
-   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6:
-  format = MESA_FORMAT_RGBA_ASTC_6x6;
-  break;
-   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x5:
-  format = MESA_FORMAT_RGBA_ASTC_8x5;
-  

[Mesa-dev] [PATCH v2 11/27] i965/miptree: Add support for window system images to create_for_dri_image

[Jason Ekstrand]

We want to start using create_for_dri_image for all miptrees created
from __DRIimage, including those which come from a window system.  In
order to allow for fast clears to still work on window system buffers,
we need to allow for creating aux surfaces.

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/mesa/drivers/dri/i965/intel_fbo.c |  2 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16 +---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  3 ++-
 src/mesa/drivers/dri/i965/intel_tex_image.c   |  2 +-
 4 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 3670c2a..03427e8 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -363,7 +363,7 @@ intel_image_target_renderbuffer_storage(struct gl_context 
*ctx,
 * content.
 */
irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D,
-ISL_COLORSPACE_NONE);
+ISL_COLORSPACE_NONE, false);
if (!irb->mt)
   return;
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 6159fb3..3c37fe3 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1041,7 +1041,8 @@ miptree_create_for_planar_image(struct brw_context *brw,
 struct intel_mipmap_tree *
 intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image, GLenum target,
-   enum isl_colorspace colorspace)
+   enum isl_colorspace colorspace,
+   bool is_winsys_image)
 {
if (image->planar_format && image->planar_format->nplanes > 0) {
   assert(colorspace == ISL_COLORSPACE_NONE ||
@@ -1083,6 +1084,16 @@ intel_miptree_create_for_dri_image(struct brw_context 
*brw,
if (!brw->ctx.TextureFormatSupported[format])
   return NULL;
 
+   /* If this image comes in from a window system, we have different
+* requirements than if it comes in via an EGL import operation.  Window
+* system images can use any form of auxiliary compression we wish because
+* they get "flushed" before being handed off to the window system and we
+* have the opportunity to do resolves.  Window system buffers also may be
+* used for scanout so we need to flag that appropriately.
+*/
+   const uint32_t mt_layout_flags =
+  is_winsys_image ? MIPTREE_LAYOUT_FOR_SCANOUT : 
MIPTREE_LAYOUT_DISABLE_AUX;
+
/* Disable creation of the texture's aux buffers because the driver exposes
 * no EGL API to manage them. That is, there is no API for resolving the aux
 * buffer's content to the main buffer nor for invalidating the aux buffer's
@@ -1091,8 +1102,7 @@ intel_miptree_create_for_dri_image(struct brw_context 
*brw,
struct intel_mipmap_tree *mt =
   intel_miptree_create_for_bo(brw, image->bo, format,
   image->offset, image->width, image->height, 
1,
-  image->pitch,
-  MIPTREE_LAYOUT_DISABLE_AUX);
+  image->pitch, mt_layout_flags);
if (mt == NULL)
   return NULL;
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 6668d31..c4ed525 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -690,7 +690,8 @@ struct intel_mipmap_tree *
 intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image,
GLenum target,
-   enum isl_colorspace colorspace);
+   enum isl_colorspace colorspace,
+   bool is_winsys_image);
 
 bool
 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c 
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 7765d1b..68d0a57 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -357,7 +357,7 @@ intel_image_target_texture_2d(struct gl_context *ctx, 
GLenum target,
}
 
mt = intel_miptree_create_for_dri_image(brw, image, target,
-   ISL_COLORSPACE_NONE);
+   ISL_COLORSPACE_NONE, false);
if (mt == NULL)
   return;
 
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 15/27] intel/isl: Add basic modifier introspection

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/intel/Makefile.am  |  1 +
 src/intel/Makefile.sources |  1 +
 src/intel/isl/isl.h| 22 +
 src/intel/isl/isl_drm.c| 59 ++
 4 files changed, 83 insertions(+)
 create mode 100644 src/intel/isl/isl_drm.c

diff --git a/src/intel/Makefile.am b/src/intel/Makefile.am
index dad54b7..e142300 100644
--- a/src/intel/Makefile.am
+++ b/src/intel/Makefile.am
@@ -38,6 +38,7 @@ AM_CPPFLAGS = \
-I$(top_srcdir)/src/gallium/auxiliary \
-I$(top_srcdir)/src/gallium/include \
$(VALGRIND_CFLAGS) \
+   $(LIBDRM_CFLAGS) \
$(DEFINES)
 
 AM_CFLAGS = \
diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index b672e61..2972cf0 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -153,6 +153,7 @@ GENXML_GENERATED_FILES = \
 ISL_FILES = \
isl/isl.c \
isl/isl.h \
+   isl/isl_drm.c \
isl/isl_format.c \
isl/isl_priv.h \
isl/isl_storage_image.c
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 07ff01a..563bcfb 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1032,6 +1032,25 @@ struct isl_tile_info {
 };
 
 /**
+ * Metadata about a DRM format modifier.
+ */
+struct isl_drm_modifier_info {
+   uint64_t modifier;
+
+   /** Text name of the modifier */
+   const char *name;
+
+   /** ISL tiling implied by this modifier */
+   enum isl_tiling tiling;
+
+   /** ISL aux usage implied by this modifier */
+   enum isl_aux_usage aux_usage;
+
+   /** Whether or not this modifier supports clear color */
+   bool supports_clear_color;
+};
+
+/**
  * @brief Input to surface initialization
  *
  * @invariant width >= 1
@@ -1494,6 +1513,9 @@ isl_tiling_is_std_y(enum isl_tiling tiling)
return (1u << tiling) & ISL_TILING_STD_Y_MASK;
 }
 
+const struct isl_drm_modifier_info * ATTRIBUTE_CONST
+isl_drm_modifier_get_info(uint64_t modifier);
+
 struct isl_extent2d ATTRIBUTE_CONST
 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
 
diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
new file mode 100644
index 000..8fccc40
--- /dev/null
+++ b/src/intel/isl/isl_drm.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2017 Intel Corporation
+ *
+ *  Permission is hereby granted, free of charge, to any person obtaining a
+ *  copy of this software and associated documentation files (the "Software"),
+ *  to deal in the Software without restriction, including without limitation
+ *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ *  Software is furnished to do so, subject to the following conditions:
+ *
+ *  The above copyright notice and this permission notice (including the next
+ *  paragraph) shall be included in all copies or substantial portions of the
+ *  Software.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
DEALINGS
+ *  IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+
+#include 
+
+#include "isl.h"
+#include "common/gen_device_info.h"
+
+struct isl_drm_modifier_info modifier_info[] = {
+   {
+  .modifier = DRM_FORMAT_MOD_NONE,
+  .name = "DRM_FORMAT_MOD_NONE",
+  .tiling = ISL_TILING_LINEAR,
+   },
+   {
+  .modifier = I915_FORMAT_MOD_X_TILED,
+  .name = "I915_FORMAT_MOD_X_TILED",
+  .tiling = ISL_TILING_X,
+   },
+   {
+  .modifier = I915_FORMAT_MOD_Y_TILED,
+  .name = "I915_FORMAT_MOD_Y_TILED",
+  .tiling = ISL_TILING_Y0,
+   },
+};
+
+const struct isl_drm_modifier_info *
+isl_drm_modifier_get_info(uint64_t modifier)
+{
+   for (unsigned i = 0; i < ARRAY_SIZE(modifier_info); i++) {
+  if (modifier_info[i].modifier == modifier)
+ return _info[i];
+   }
+
+   return NULL;
+}
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 09/27] main/formats: Add a get_linear_format_srgb helper

[Jason Ekstrand]

---
 src/mesa/main/format_fallback.py | 22 ++
 src/mesa/main/formats.h  |  3 +++
 2 files changed, 25 insertions(+)

diff --git a/src/mesa/main/format_fallback.py b/src/mesa/main/format_fallback.py
index ec86938..e797a7d 100644
--- a/src/mesa/main/format_fallback.py
+++ b/src/mesa/main/format_fallback.py
@@ -106,6 +106,28 @@ _mesa_get_srgb_format_linear(mesa_format format)
 }
 
 /**
+ * For a linear format, return the corresponding sRGB color space format.
+ * For an sRGB format, return the format as-is.
+ * Assert-fails if the format is not sRGB and does not have an sRGB equivalent.
+ */
+mesa_format
+_mesa_get_linear_format_srgb(mesa_format format)
+{
+   switch (format) {
+%for unorm, srgb in unorm_to_srgb_map:
+   case ${unorm}:
+  return ${srgb};
+%endfor
+%for unorm, srgb in unorm_to_srgb_map:
+   case ${srgb}:
+%endfor
+  return format;
+   default:
+  unreachable("Given format does not have an sRGB equivalent");
+   }
+}
+
+/**
  * If the format has an alpha channel, and there exists a non-alpha
  * variant of the format with an identical bit layout, then return
  * the non-alpha format. Otherwise return the original format.
diff --git a/src/mesa/main/formats.h b/src/mesa/main/formats.h
index 62b5e0c..fbcbe36 100644
--- a/src/mesa/main/formats.h
+++ b/src/mesa/main/formats.h
@@ -749,6 +749,9 @@ extern mesa_format
 _mesa_get_srgb_format_linear(mesa_format format);
 
 extern mesa_format
+_mesa_get_linear_format_srgb(mesa_format format);
+
+extern mesa_format
 _mesa_get_uncompressed_format(mesa_format format);
 
 extern GLuint
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 10/27] i965/miptree: Add a colorspace parameter to create_for_dri_image

[Jason Ekstrand]

The __DRI_FORMAT enums are all UNORM but we will frequently want sRGB
when creating miptrees for renderbuffers.  This lets us specify.
---
 src/mesa/drivers/dri/i965/intel_fbo.c |  3 ++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 24 ++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  3 ++-
 src/mesa/drivers/dri/i965/intel_tex_image.c   |  3 ++-
 4 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 4003e28..3670c2a 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -362,7 +362,8 @@ intel_image_target_renderbuffer_storage(struct gl_context 
*ctx,
 * buffer's content to the main buffer nor for invalidating the aux buffer's
 * content.
 */
-   irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D);
+   irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D,
+ISL_COLORSPACE_NONE);
if (!irb->mt)
   return;
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f1ac074..6159fb3 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1040,12 +1040,32 @@ miptree_create_for_planar_image(struct brw_context *brw,
 
 struct intel_mipmap_tree *
 intel_miptree_create_for_dri_image(struct brw_context *brw,
-   __DRIimage *image, GLenum target)
+   __DRIimage *image, GLenum target,
+   enum isl_colorspace colorspace)
 {
-   if (image->planar_format && image->planar_format->nplanes > 0)
+   if (image->planar_format && image->planar_format->nplanes > 0) {
+  assert(colorspace == ISL_COLORSPACE_NONE ||
+ colorspace == ISL_COLORSPACE_YUV);
   return miptree_create_for_planar_image(brw, image, target);
+   }
 
mesa_format format = image->format;
+   switch (colorspace) {
+   case ISL_COLORSPACE_NONE:
+  /* Keep the image format unmodified */
+  break;
+
+   case ISL_COLORSPACE_LINEAR:
+  format =_mesa_get_srgb_format_linear(format);
+  break;
+
+   case ISL_COLORSPACE_SRGB:
+  format =_mesa_get_linear_format_srgb(format);
+  break;
+
+   default:
+  unreachable("Inalid colorspace for non-planar image");
+   }
 
if (!brw->ctx.TextureFormatSupported[format]) {
   /* The texture storage paths in core Mesa detect if the driver does not
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 4cc5c35..6668d31 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -689,7 +689,8 @@ intel_miptree_create_for_bo(struct brw_context *brw,
 struct intel_mipmap_tree *
 intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image,
-   GLenum target);
+   GLenum target,
+   enum isl_colorspace colorspace);
 
 bool
 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c 
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index abeb245..7765d1b 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -356,7 +356,8 @@ intel_image_target_texture_2d(struct gl_context *ctx, 
GLenum target,
   return;
}
 
-   mt = intel_miptree_create_for_dri_image(brw, image, target);
+   mt = intel_miptree_create_for_dri_image(brw, image, target,
+   ISL_COLORSPACE_NONE);
if (mt == NULL)
   return;
 
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 14/27] i965: Add an isl_device to intel_screen

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/mesa/drivers/dri/i965/brw_context.c  | 2 +-
 src/mesa/drivers/dri/i965/intel_screen.c | 3 +++
 src/mesa/drivers/dri/i965/intel_screen.h | 4 
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 1c7cf90..2525320 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -974,7 +974,7 @@ brwCreateContext(gl_api api,
brw->must_use_separate_stencil = devinfo->must_use_separate_stencil;
brw->has_swizzling = screen->hw_has_swizzling;
 
-   isl_device_init(>isl_dev, devinfo, screen->hw_has_swizzling);
+   brw->isl_dev = screen->isl_dev;
 
brw->vs.base.stage = MESA_SHADER_VERTEX;
brw->tcs.base.stage = MESA_SHADER_TESS_CTRL;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 0e03c56..8c0e366 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2118,6 +2118,9 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
screen->hw_has_swizzling = intel_detect_swizzling(screen);
screen->hw_has_timestamp = intel_detect_timestamp(screen);
 
+   isl_device_init(>isl_dev, >devinfo,
+   screen->hw_has_swizzling);
+
/* GENs prior to 8 do not support EU/Subslice info */
if (devinfo->gen >= 8) {
   intel_detect_sseu(screen);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h 
b/src/mesa/drivers/dri/i965/intel_screen.h
index f78b3e8..0980c8f 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -38,6 +38,8 @@
 #include "i915_drm.h"
 #include "xmlconfig.h"
 
+#include "isl/isl.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -60,6 +62,8 @@ struct intel_screen
 
int hw_has_timestamp;
 
+   struct isl_device isl_dev;
+
/**
 * Does the kernel support context reset notifications?
 */
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 04/27] i965/miptree: Set level_x/h in create_for_dri_image

[Jason Ekstrand]

Reviewed-by: Chad Versace 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 077e2ab..0d989d5 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1077,6 +1077,8 @@ intel_miptree_create_for_dri_image(struct brw_context 
*brw,
   return NULL;
 
mt->target = target;
+   mt->level[0].level_x = image->tile_x;
+   mt->level[0].level_y = image->tile_y;
mt->level[0].slice[0].x_offset = image->tile_x;
mt->level[0].slice[0].y_offset = image->tile_y;
mt->total_width += image->tile_x;
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 05/27] i965: Use miptree_create_for_dri_image in image_target_renderbuffer_storage

[Jason Ekstrand]

This does make a tiny functional change in that we now also test for
whether or not the format supports texturing and not just rendering.
However, this should have no practical effect as all renderbuffers use
texturable formats.

Reviewed-by: Chad Versace 
---
 src/mesa/drivers/dri/i965/intel_fbo.c | 23 +--
 1 file changed, 1 insertion(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index b59fc1f..4003e28 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -362,31 +362,10 @@ intel_image_target_renderbuffer_storage(struct gl_context 
*ctx,
 * buffer's content to the main buffer nor for invalidating the aux buffer's
 * content.
 */
-   irb->mt = intel_miptree_create_for_bo(brw,
- image->bo,
- image->format,
- image->offset,
- image->width,
- image->height,
- 1,
- image->pitch,
- MIPTREE_LAYOUT_DISABLE_AUX);
+   irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D);
if (!irb->mt)
   return;
 
-   /* Adjust the miptree's upper-left coordinate.
-*
-* FIXME: Adjusting the miptree's layout outside of
-* intel_miptree_create_layout() is fragile. Plumb the adjustment through
-* intel_miptree_create_layout() and brw_tex_layout().
-*/
-   irb->mt->level[0].level_x = image->tile_x;
-   irb->mt->level[0].level_y = image->tile_y;
-   irb->mt->level[0].slice[0].x_offset = image->tile_x;
-   irb->mt->level[0].slice[0].y_offset = image->tile_y;
-   irb->mt->total_width += image->tile_x;
-   irb->mt->total_height += image->tile_y;
-
rb->InternalFormat = image->internal_format;
rb->Width = image->width;
rb->Height = image->height;
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 06/27] i965/miptree: Add a return for updating of winsys

[Jason Ekstrand]

From: Ben Widawsky 

There is nothing particularly useful to do currently if the update
fails, but there is no point carrying on either. As a result, this has a
behavior change.

v2: Make the return type a bool (Topi)

v3: Don't leak the bo if update_winsys_renderbuffer fails. (Jason)

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Reviewed-by: Topi Pohjolainen  (v2)
Reviewed-by: Jason Ekstrand 
Reviewed-by: Chad Versace 
---
 src/mesa/drivers/dri/i965/brw_context.c   | 16 ++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  6 +++---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  2 +-
 3 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index e921a41..5fb2964 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1625,9 +1625,12 @@ intel_process_dri2_buffer(struct brw_context *brw,
   return;
}
 
-   intel_update_winsys_renderbuffer_miptree(brw, rb, bo,
-drawable->w, drawable->h,
-buffer->pitch);
+   if (!intel_update_winsys_renderbuffer_miptree(brw, rb, bo,
+ drawable->w, drawable->h,
+ buffer->pitch)) {
+  brw_bo_unreference(bo);
+  return;
+   }
 
if (_mesa_is_front_buffer_drawing(fb) &&
(buffer->attachment == __DRI_BUFFER_FRONT_LEFT ||
@@ -1683,9 +1686,10 @@ intel_update_image_buffer(struct brw_context *intel,
if (last_mt && last_mt->bo == buffer->bo)
   return;
 
-   intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
-buffer->width, buffer->height,
-buffer->pitch);
+   if (!intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
+ buffer->width, buffer->height,
+ buffer->pitch))
+  return;
 
if (_mesa_is_front_buffer_drawing(fb) &&
buffer_type == __DRI_IMAGE_BUFFER_FRONT &&
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0d989d5..c018c7f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1112,7 +1112,7 @@ intel_miptree_create_for_dri_image(struct brw_context 
*brw,
  * that will contain the actual rendering (which is lazily resolved to
  * irb->singlesample_mt).
  */
-void
+bool
 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
  struct intel_renderbuffer *irb,
  struct brw_bo *bo,
@@ -1168,12 +1168,12 @@ intel_update_winsys_renderbuffer_miptree(struct 
brw_context *intel,
  irb->mt = multisample_mt;
   }
}
-   return;
+   return true;
 
 fail:
intel_miptree_release(>singlesample_mt);
intel_miptree_release(>mt);
-   return;
+   return false;
 }
 
 struct intel_mipmap_tree*
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index cb1dcc1..c588f25 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -691,7 +691,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image,
GLenum target);
 
-void
+bool
 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
  struct intel_renderbuffer *irb,
  struct brw_bo *bo,
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 00/27] i965: i965: Add support for I915_FORMAT_MOD_Y_TILED_CCS

[Jason Ekstrand]

This is mostly a re-send of my earlier series:

https://lists.freedesktop.org/archives/mesa-dev/2017-June/159724.html

The first 5 or so patches from the original series have been pushed and are
not included in this re-seend.  There are two new patches (8 and 9) which
are new.  Also, 10 is a significantly reworked version of patch 13 in the
original series.  Those should be the only significant changes.

Ben Widawsky (6):
  i965/miptree: Add a return for updating of winsys
  i965/miptree: Allocate mt earlier in update winsys
  i965: Support images with aux buffers
  i965/miptree: Allocate mcs_buf for an image's CCS
  i965: Pretend that CCS modified images are two planes
  i965: Advertise the CCS modifier

Jason Ekstrand (21):
  i965: Move the DRIimage -> miptree code to intel_mipmap_tree.c
  i965/miptree: Pass the offset into create_for_bo in
create_for_dri_image
  i965/miptree: Add tile_x/y to total_width/height
  i965/miptree: Set level_x/h in create_for_dri_image
  i965: Use miptree_create_for_dri_image in
image_target_renderbuffer_storage
  main/formats: Autogenerate _mesa_get_srgb_format_linear
  main/formats: Add a get_linear_format_srgb helper
  i965/miptree: Add a colorspace parameter to create_for_dri_image
  i965/miptree: Add support for window system images to
create_for_dri_image
  i965: Use create_for_dri_image in intel_update_image_buffer
  i965/miptree: Move CCS allocation into create_for_dri_image
  i965: Add an isl_device to intel_screen
  intel/isl: Add basic modifier introspection
  intel/isl: Add a helper to convert tilings from ISL to i915
  i965/screen: Use ISL for allocating image BOs
  i965/screen: Use ISL for doing image import checks
  i965/screen: Drop get_tiled_height
  intel/isl: Add support for I915_FORMAT_MOD_Y_TILED_CCS
  intel/isl: Add a row_pitch parameter to surf_get_ccs_surf
  i965/screen: Support import and export of surfaces with CCS
  i965/miptree: More conservatively resolve external images

 src/intel/Makefile.am |   1 +
 src/intel/Makefile.sources|   1 +
 src/intel/isl/isl.c   |   4 +-
 src/intel/isl/isl.h   |  28 ++-
 src/intel/isl/isl_drm.c   |  95 
 src/intel/vulkan/anv_image.c  |   2 +-
 src/mesa/drivers/dri/i965/brw_context.c   |  56 -
 src/mesa/drivers/dri/i965/intel_fbo.c |  24 +-
 src/mesa/drivers/dri/i965/intel_image.h   |   6 +
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 303 --
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  20 +-
 src/mesa/drivers/dri/i965/intel_screen.c  | 216 --
 src/mesa/drivers/dri/i965/intel_screen.h  |   4 +
 src/mesa/drivers/dri/i965/intel_tex_image.c   | 112 +-
 src/mesa/main/format_fallback.py  |  68 ++
 src/mesa/main/formats.c   | 117 --
 src/mesa/main/formats.h   |   3 +
 17 files changed, 715 insertions(+), 345 deletions(-)
 create mode 100644 src/intel/isl/isl_drm.c

-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 01/27] i965: Move the DRIimage -> miptree code to intel_mipmap_tree.c

[Jason Ekstrand]

This is mostly a direct port.  The only bit of refactoring that was done
was to make creating a planar miptree be an early return from the
non-planar case.  Alternatively, we could have three functions: two
helpers and a main function to just call the right helper.  Making the
planar case an early return seemed cleaner.

Reviewed-by: Chad Versace 
Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 106 
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |   5 ++
 src/mesa/drivers/dri/i965/intel_tex_image.c   | 111 +-
 3 files changed, 112 insertions(+), 110 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f5391a4..9dcf5be 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -27,6 +27,7 @@
 #include 
 
 #include "intel_batchbuffer.h"
+#include "intel_image.h"
 #include "intel_mipmap_tree.h"
 #include "intel_tex.h"
 #include "intel_blit.h"
@@ -996,6 +997,111 @@ intel_miptree_create_for_bo(struct brw_context *brw,
return mt;
 }
 
+static struct intel_mipmap_tree *
+miptree_create_for_planar_image(struct brw_context *brw,
+__DRIimage *image, GLenum target)
+{
+   struct intel_image_format *f = image->planar_format;
+   struct intel_mipmap_tree *planar_mt;
+
+   for (int i = 0; i < f->nplanes; i++) {
+  const int index = f->planes[i].buffer_index;
+  const uint32_t dri_format = f->planes[i].dri_format;
+  const mesa_format format = driImageFormatToGLFormat(dri_format);
+  const uint32_t width = image->width >> f->planes[i].width_shift;
+  const uint32_t height = image->height >> f->planes[i].height_shift;
+
+  /* Disable creation of the texture's aux buffers because the driver
+   * exposes no EGL API to manage them. That is, there is no API for
+   * resolving the aux buffer's content to the main buffer nor for
+   * invalidating the aux buffer's content.
+   */
+  struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_bo(brw, image->bo, format,
+ image->offsets[index],
+ width, height, 1,
+ image->strides[index],
+ MIPTREE_LAYOUT_DISABLE_AUX);
+  if (mt == NULL)
+ return NULL;
+
+  mt->target = target;
+  mt->total_width = width;
+  mt->total_height = height;
+
+  if (i == 0)
+ planar_mt = mt;
+  else
+ planar_mt->plane[i - 1] = mt;
+   }
+
+   return planar_mt;
+}
+
+struct intel_mipmap_tree *
+intel_miptree_create_for_dri_image(struct brw_context *brw,
+   __DRIimage *image, GLenum target)
+{
+   if (image->planar_format && image->planar_format->nplanes > 0)
+  return miptree_create_for_planar_image(brw, image, target);
+
+   mesa_format format = image->format;
+
+   if (!brw->ctx.TextureFormatSupported[format]) {
+  /* The texture storage paths in core Mesa detect if the driver does not
+   * support the user-requested format, and then searches for a
+   * fallback format. The DRIimage code bypasses core Mesa, though. So we
+   * do the fallbacks here for important formats.
+   *
+   * We must support DRM_FOURCC_XBGR textures because the Android
+   * framework produces HAL_PIXEL_FORMAT_RGBX winsys surfaces, which
+   * the Chrome OS compositor consumes as dma_buf EGLImages.
+   */
+  format = _mesa_format_fallback_rgbx_to_rgba(format);
+   }
+
+   if (!brw->ctx.TextureFormatSupported[format])
+  return NULL;
+
+   /* Disable creation of the texture's aux buffers because the driver exposes
+* no EGL API to manage them. That is, there is no API for resolving the aux
+* buffer's content to the main buffer nor for invalidating the aux buffer's
+* content.
+*/
+   struct intel_mipmap_tree *mt =
+  intel_miptree_create_for_bo(brw, image->bo, format,
+  0, image->width, image->height, 1,
+  image->pitch,
+  MIPTREE_LAYOUT_DISABLE_AUX);
+   if (mt == NULL)
+  return NULL;
+
+   mt->target = target;
+   mt->total_width = image->width;
+   mt->total_height = image->height;
+   mt->level[0].slice[0].x_offset = image->tile_x;
+   mt->level[0].slice[0].y_offset = image->tile_y;
+
+   /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
+* for EGL images from non-tile aligned sufaces in gen4 hw and earlier 
which has
+* trouble resolving back to destination image due to alignment issues.
+*/
+   if (!brw->has_surface_tile_offset) {
+  uint32_t draw_x, draw_y;
+  intel_miptree_get_tile_offsets(mt, 0, 0, _x, _y);
+
+  if (draw_x != 

[Mesa-dev] [PATCH v2 02/27] i965/miptree: Pass the offset into create_for_bo in create_for_dri_image

[Jason Ekstrand]

Reviewed-by: Chad Versace 
Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 9dcf5be..bdd0cd5 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1070,7 +1070,7 @@ intel_miptree_create_for_dri_image(struct brw_context 
*brw,
 */
struct intel_mipmap_tree *mt =
   intel_miptree_create_for_bo(brw, image->bo, format,
-  0, image->width, image->height, 1,
+  image->offset, image->width, image->height, 
1,
   image->pitch,
   MIPTREE_LAYOUT_DISABLE_AUX);
if (mt == NULL)
@@ -1097,8 +1097,6 @@ intel_miptree_create_for_dri_image(struct brw_context 
*brw,
   }
}
 
-   mt->offset = image->offset;
-
return mt;
 }
 
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 03/27] i965/miptree: Add tile_x/y to total_width/height

[Jason Ekstrand]

This is what we do in intel_image_target_renderbuffer_storage and it
makes more sense than stomping them.  Because the image gets created as
a 2D image with one miplevel, they should already be equal to the
provided width/height.  Adding the tile offset makes some sense
depending on how you interpret the fields.

The only place these fields are used for in state setup is to set up the
image parameters we pass into shaders.  There may be issues here if you
try to use image_load_store on something pulled in from EGL but that's
probably broken already.  This just makes it consistently broken.

Reviewed-by: Chad Versace 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index bdd0cd5..077e2ab 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1077,10 +1077,10 @@ intel_miptree_create_for_dri_image(struct brw_context 
*brw,
   return NULL;
 
mt->target = target;
-   mt->total_width = image->width;
-   mt->total_height = image->height;
mt->level[0].slice[0].x_offset = image->tile_x;
mt->level[0].slice[0].y_offset = image->tile_y;
+   mt->total_width += image->tile_x;
+   mt->total_height += image->tile_y;
 
/* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier 
which has
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/3] spirv: fix OpBitcast when the src and dst bitsize are different

[Jason Ekstrand]

On Thu, Jun 8, 2017 at 3:05 PM, Connor Abbott 
wrote:

> From: Connor Abbott 
>
> Before, we were just implementing it with a move, which is incorrect
> when the source and destination have different bitsizes. To implement
> it properly, we need to use the 64-bit pack/unpack opcodes. Since
> glslang uses OpBitcast to implement packInt2x32 and unpackInt2x32, this
> should fix them on anv (and radv once we enable the int64 capability).
>
> Fixes: b3135c3c ("anv: Advertise shaderInt64 on Broadwell and above")
> Signed-off-by: Connor Abbott 
> ---
>  src/compiler/spirv/vtn_alu.c | 68 ++
> +-
>  1 file changed, 67 insertions(+), 1 deletion(-)
>
> diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
> index 9e4beed..cd9569b 100644
> --- a/src/compiler/spirv/vtn_alu.c
> +++ b/src/compiler/spirv/vtn_alu.c
> @@ -210,6 +210,69 @@ vtn_handle_matrix_alu(struct vtn_builder *b, SpvOp
> opcode,
> }
>  }
>
> +static void
> +vtn_handle_bitcast(struct vtn_builder *b, struct vtn_ssa_value *dest,
> +   struct nir_ssa_def *src)
> +{
> +   if (glsl_get_vector_elements(dest->type) == src->num_components) {
> +  /* From the definition of OpBitcast in the SPIR-V 1.2 spec:
> +   *
> +   * "If Result Type has the same number of components as Operand,
> they
> +   * must also have the same component width, and results are
> computed per
> +   * component."
> +   */
> +  dest->def = nir_imov(>nb, src);
> +  return;
> +   }
> +
> +   /* From the definition of OpBitcast in the SPIR-V 1.2 spec:
> +*
> +* "If Result Type has a different number of components than Operand,
> the
> +* total number of bits in Result Type must equal the total number of
> bits
> +* in Operand. Let L be the type, either Result Type or Operand’s
> type, that
> +* has the larger number of components. Let S be the other type, with
> the
> +* smaller number of components. The number of components in L must be
> an
> +* integer multiple of the number of components in S. The first
> component
> +* (that is, the only or lowest-numbered component) of S maps to the
> first
> +* components of L, and so on, up to the last component of S mapping
> to the
> +* last components of L. Within this mapping, any single component of S
> +* (mapping to multiple components of L) maps its lower-ordered bits
> to the
> +* lower-numbered components of L."
> +*
> +* Since booleans are a separate type without a width, presumably they
> can't
> +* be bitcasted. So we only have to deal with 32 vs. 64 bit right now,
> which
> +* we handle using the pack/unpack opcodes.
>

This won't last long The Igalia guys already have patches in the works
to add 16-bit support.  Also, I'm guessing 8-bit ints are going to be a
thing at some point.  I think we can make this more general and make their
lives easier...


> +*/
> +   unsigned src_bit_size = src->bit_size;
> +   unsigned dest_bit_size = glsl_get_bit_size(dest->type);
> +   unsigned src_components = src->num_components;
> +   unsigned dest_components = glsl_get_vector_elements(dest->type);
>

How about something like this:

unsigned size = src_components * src_bit_size;
assert(size == dest_components * dest_bit_size);
unsigned min_bit_size = MIN2(src_bit_size, dest_bit_size);
unsigned total_comps = size / min_bit_size;

NIR_VLA(nir_ssa_def *, unpacked);

for (unsigned idx = 0, i = 0; i < src_comps; i++) {
   nir_ssa_def *chan = nir_channel(>nb, src, i);
   if (src_bit_size == min_bit_size) {
  total_comps[idx++] = chan;
   } else {
  assert(min_bit_size == 32 && src_bit_size == 64);
  nir_ssa_def *split =
 nir_unpack_64_2x32(>nb, nir_channel(>nb, src, comp));
  unpacked[idx++] = nir_channel(>nb, split, 0);
  unpacked[idx++] = nir_channel(>nb, split, 1);
   }
}

nir_ssa_def *vec_src[4];
for (unsigned idx = 0, i = 0; i < dest_comps; i++) {
   if (dest_bit_size == min_bit_size) {
  vec_src[i] = unpacked[idx++];
   } else {
  assert(min_bit_size == 32 && dest_bit_size == 64);
  nir_ssa_def *src0 = unpacked[idx++];
  nir_ssa_def *src1 = unpacked[idx++];
  vec_src[i] = nir_pack_64_2x32(>nb, nir_vec2(>nb, src0, src1));
   }
}

dest->def = nir_vec(>nb, vec_src, dest_components);

What do you think?  Another thought: Should this go in nir_builder?

--Jason


> +   if (src_bit_size > dest_bit_size) {
> +  assert(src_bit_size == 64);
> +  assert(dest_bit_size == 32);
> +  assert(dest_components == 2 * src_components);
> +  nir_ssa_def *dest_chan[4];
> +  for (unsigned comp = 0; comp < src_components; comp++) {
> + nir_ssa_def *split =
> +nir_unpack_64_2x32(>nb, nir_channel(>nb, src, comp));
>
+ dest_chan[2 * comp + 0] = nir_channel(>nb, split, 0);
> + dest_chan[2 * comp + 1] = nir_channel(>nb, split, 1);

Re: [Mesa-dev] [PATCH 07/14] gallium/radeon: remove RADEON_FLAG_CPU_ACCESS

[Michel Dänzer]

On 30/06/17 04:47 AM, Marek Olšák wrote:
> From: Marek Olšák 
> 
> https://lists.freedesktop.org/archives/amd-gfx/2017-June/010591.html

This is premature. The discussion on amd-gfx hasn't concluded yet.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 3/3] glsl: disable array splitting for AoA

[Timothy Arceri]

While it produces functioning code the pass creates worse code
for arrays of arrays. See the comment added in this patch for more
detail.
---
 src/compiler/glsl/opt_array_splitting.cpp | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/src/compiler/glsl/opt_array_splitting.cpp 
b/src/compiler/glsl/opt_array_splitting.cpp
index fb6d77b..b3d4599 100644
--- a/src/compiler/glsl/opt_array_splitting.cpp
+++ b/src/compiler/glsl/opt_array_splitting.cpp
@@ -140,6 +140,32 @@ ir_array_reference_visitor::get_variable_entry(ir_variable 
*var)
if (var->type->is_unsized_array())
   return NULL;
 
+   /* FIXME: arrays of arrays are not handled correctly by this pass so we
+* skip it for now. While the pass will create functioning code it actually
+* produces worse code.
+*
+* For example the array:
+*
+*int[3][2] a;
+*
+* ends up being split up into:
+*
+*int[3][2] a_0;
+*int[3][2] a_1;
+*int[3][2] a_2;
+*
+* And we end up referencing each of these new arrays for example:
+*
+*a[0][1] will be turned into a_0[0][1]
+*a[1][0] will be turned into a_1[1][0]
+*a[2][0] will be turned into a_2[2][0]
+*
+* For now we continue to split AoA of matrices to avoid CTS regressions.
+*/
+   if (var->type->is_array() && var->type->fields.array->is_array() &&
+   !var->type->without_array()->is_matrix())
+  return NULL;
+
foreach_in_list(variable_entry, entry, >variable_list) {
   if (entry->var == var)
  return entry;
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/3] nir: fix nir_opt_copy_prop_vars() for arrays of arrays

[Timothy Arceri]

Previous we only incremented the guide for a single
dimension/wildcard.
---
 src/compiler/nir/nir_opt_copy_prop_vars.c | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/compiler/nir/nir_opt_copy_prop_vars.c 
b/src/compiler/nir/nir_opt_copy_prop_vars.c
index 7f17469..06ce257 100644
--- a/src/compiler/nir/nir_opt_copy_prop_vars.c
+++ b/src/compiler/nir/nir_opt_copy_prop_vars.c
@@ -469,8 +469,8 @@ specialize_wildcards(nir_deref_var *deref,
nir_deref_var *ret = nir_deref_var_create(mem_ctx, deref->var);
 
nir_deref *deref_tail = deref->deref.child;
-   nir_deref *guide_tail = guide->deref.child;
-   nir_deref *spec_tail = specific->deref.child;
+   nir_deref *guide_tail = >deref;
+   nir_deref *spec_tail = >deref;
nir_deref *ret_tail = >deref;
while (deref_tail) {
   switch (deref_tail->deref_type) {
@@ -495,9 +495,9 @@ specialize_wildcards(nir_deref_var *deref,
  * the entry deref to find its corresponding wildcard and fill
  * this slot in with the value from the src.
  */
-while (guide_tail) {
-   if (guide_tail->deref_type == nir_deref_type_array &&
-   nir_deref_as_array(guide_tail)->deref_array_type ==
+while (guide_tail->child) {
+   if (guide_tail->child->deref_type == nir_deref_type_array &&
+   nir_deref_as_array(guide_tail->child)->deref_array_type ==
nir_deref_array_type_wildcard)
   break;
 
@@ -505,6 +505,11 @@ specialize_wildcards(nir_deref_var *deref,
spec_tail = spec_tail->child;
 }
 
+if (guide_tail->child) {
+guide_tail = guide_tail->child;
+spec_tail = spec_tail->child;
+}
+
 nir_deref_array *spec_arr = nir_deref_as_array(spec_tail);
 ret_arr->deref_array_type = spec_arr->deref_array_type;
 ret_arr->base_offset = spec_arr->base_offset;
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/3] nir: NULL check lower_copies_to_load_store()

[Timothy Arceri]

Allows us to disable array spliting for arrays of arrays without
regressing tests such as:

ES31-CTS.functional.shaders.arrays_of_arrays.return.explicit.struct_3x1x3_fragment
---
 src/compiler/nir/nir_lower_vars_to_ssa.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c 
b/src/compiler/nir/nir_lower_vars_to_ssa.c
index e5a12eb..31f7e7a 100644
--- a/src/compiler/nir/nir_lower_vars_to_ssa.c
+++ b/src/compiler/nir/nir_lower_vars_to_ssa.c
@@ -441,7 +441,7 @@ static bool
 lower_copies_to_load_store(struct deref_node *node,
struct lower_variables_state *state)
 {
-   if (!node->copies)
+   if (!node || !node->copies)
   return true;
 
struct set_entry *copy_entry;
-- 
2.9.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 07/18] nir/spirv: Use the correct stride for non-32-bit vectors

[Connor Abbott]

Fixup the comment above this?

On Thu, Jun 29, 2017 at 10:33 AM, Jason Ekstrand  wrote:
> ---
>  src/compiler/spirv/spirv_to_nir.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/compiler/spirv/spirv_to_nir.c 
> b/src/compiler/spirv/spirv_to_nir.c
> index 18e3734..7a98843 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -744,7 +744,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
> * is always 4 bytes.  This will have to change if we want to start
> * supporting doubles or half-floats.
> */
> -  val->type->stride = 4;
> +  val->type->stride = glsl_get_bit_size(base->type) / 8;
>val->type->array_element = base;
>break;
> }
> --
> 2.5.0.400.gff86faf
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 07/18] nir/spirv: Use the correct stride for non-32-bit vectors

[Jason Ekstrand]

On Thu, Jun 29, 2017 at 6:51 PM, Connor Abbott  wrote:

> Fixup the comment above this?
>

Yup.  Fixed locally.


> On Thu, Jun 29, 2017 at 10:33 AM, Jason Ekstrand 
> wrote:
> > ---
> >  src/compiler/spirv/spirv_to_nir.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/src/compiler/spirv/spirv_to_nir.c
> b/src/compiler/spirv/spirv_to_nir.c
> > index 18e3734..7a98843 100644
> > --- a/src/compiler/spirv/spirv_to_nir.c
> > +++ b/src/compiler/spirv/spirv_to_nir.c
> > @@ -744,7 +744,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
> > * is always 4 bytes.  This will have to change if we want to
> start
> > * supporting doubles or half-floats.
> > */
> > -  val->type->stride = 4;
> > +  val->type->stride = glsl_get_bit_size(base->type) / 8;
> >val->type->array_element = base;
> >break;
> > }
> > --
> > 2.5.0.400.gff86faf
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] anv: Advertise support for VK_FORMAT_R8_SRGB

[Jason Ekstrand]

Unreal Engine 4 seems to really like this format for some reason.  We
don't technically have the hardware format but we do have L8_SRGB.  It's
easy enough to fake with that and a swizzle.
---
 src/intel/vulkan/anv_formats.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 0bc81d1..3535c09 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -74,7 +74,8 @@ static const struct anv_format anv_formats[] = {
fmt(VK_FORMAT_R8_SSCALED,  ISL_FORMAT_R8_SSCALED),
fmt(VK_FORMAT_R8_UINT, ISL_FORMAT_R8_UINT),
fmt(VK_FORMAT_R8_SINT, ISL_FORMAT_R8_SINT),
-   fmt(VK_FORMAT_R8_SRGB, ISL_FORMAT_UNSUPPORTED),
+   swiz_fmt(VK_FORMAT_R8_SRGB,ISL_FORMAT_L8_UNORM_SRGB,
+  _ISL_SWIZZLE(RED, ZERO, ZERO, ONE)),
fmt(VK_FORMAT_R8G8_UNORM,  ISL_FORMAT_R8G8_UNORM),
fmt(VK_FORMAT_R8G8_SNORM,  ISL_FORMAT_R8G8_SNORM),
fmt(VK_FORMAT_R8G8_USCALED,ISL_FORMAT_R8G8_USCALED),
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 16/30] i965/miptree: Move CCS allocation into create_for_dri_image

[Jason Ekstrand]

On Wed, Jun 28, 2017 at 2:15 PM, Chad Versace 
wrote:

> On Fri 16 Jun 2017, Jason Ekstrand wrote:
> > Any form of CCS on gen9+ only works on Y-tiled images.  The only caller
> > of create_for_bo which uses Y-tiled BOs is create_for_dri_image.
>
> If I understand ARC++ correctly, then intel_update_image_buffer() also
> calls intel_miptree_create_for_bo() for Android Y-tiled winsys buffers.
> (I've confirmed it with code inspection, but not with actual debug
> logging). That should be noted in the commit message.
>
> This patch shouldn't degrade ARC++ performance, though, because ARC++ is
> still using an old Mesa that never allocated CCS for Android winsys
> buffers.
>

No, it shouldn't degrade ARC++ performance because patch 15 (the previous
one) makes intel_update_image_buffer() call
intel_miptree_create_for_dri_image().  :-)

--Jason


> At the end of the patch series, will Android's Y-tiled winsys buffers
> get the benefit of a private CCS?
>
> > +   /* Since CCS_E can compress more than just clear color, we create the
> > +* CCS for it up-front.  For CCS_D which only compresses clears, we
> > +* create the CCS on-demand when a clear occurs that wants one.
> > +*/
> > +   if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
> > +  if (!intel_miptree_alloc_ccs(brw, mt)) {
> > + intel_miptree_release();
> > + return NULL;
> > +  }
> > +   }
> > +
>
> The above hunk is a duplicate. The same 'if' tree appears immediately
> above it.
>

It wasn't duplicated so much as rebased into the wrong hunk.  It should
have ended up in create_for_dri_image.  I've moved it.


> With the hunk de-duplicated, this patch is
> Reviewed-by: Chad Versace 
>

Thanks!


>
> > return mt;
> >  }
> >
> > --
> > 2.5.0.400.gff86faf
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] glthread: get rid of unmarshal dispatch enum/table

[Grigori Goronzy]

Use function pointers to identify the unmarshalling function, which
is simpler and gets rid of a lot generated code.

This removes an indirection and possibly results in a slight speedup
as well.
---
 src/mapi/glapi/gen/Makefile.am |  4 --
 src/mapi/glapi/gen/gl_marshal.py   | 36 ++--
 src/mapi/glapi/gen/gl_marshal_h.py | 86 --
 src/mesa/Android.gen.mk|  7 
 src/mesa/Makefile.sources  |  1 -
 src/mesa/SConscript|  8 
 src/mesa/main/.gitignore   |  1 -
 src/mesa/main/glthread.c   |  9 +++-
 src/mesa/main/glthread.h   |  2 -
 src/mesa/main/marshal.c| 19 -
 src/mesa/main/marshal.h| 14 +++
 11 files changed, 26 insertions(+), 161 deletions(-)
 delete mode 100644 src/mapi/glapi/gen/gl_marshal_h.py

diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am
index bd04519..62007a4 100644
--- a/src/mapi/glapi/gen/Makefile.am
+++ b/src/mapi/glapi/gen/Makefile.am
@@ -76,7 +76,6 @@ EXTRA_DIST= \
gl_genexec.py \
gl_gentable.py \
gl_marshal.py \
-   gl_marshal_h.py \
gl_procs.py \
gl_SPARC_asm.py \
gl_table.py \
@@ -297,9 +296,6 @@ $(MESA_DIR)/main/api_exec.c: gl_genexec.py apiexec.py 
$(COMMON)
 $(MESA_DIR)/main/marshal_generated.c: gl_marshal.py marshal_XML.py $(COMMON)
$(PYTHON_GEN) $(srcdir)/gl_marshal.py -f $(srcdir)/gl_and_es_API.xml > 
$@
 
-$(MESA_DIR)/main/marshal_generated.h: gl_marshal_h.py marshal_XML.py $(COMMON)
-   $(PYTHON_GEN) $(srcdir)/gl_marshal_h.py -f $(srcdir)/gl_and_es_API.xml 
> $@
-
 $(MESA_DIR)/main/dispatch.h: gl_table.py $(COMMON)
$(PYTHON_GEN) $(srcdir)/gl_table.py -f $(srcdir)/gl_and_es_API.xml -m 
remap_table > $@
 
diff --git a/src/mapi/glapi/gen/gl_marshal.py b/src/mapi/glapi/gen/gl_marshal.py
index efa4d9e..e71ede3 100644
--- a/src/mapi/glapi/gen/gl_marshal.py
+++ b/src/mapi/glapi/gen/gl_marshal.py
@@ -34,7 +34,6 @@ header = """
 #include "dispatch.h"
 #include "glthread.h"
 #include "marshal.h"
-#include "marshal_generated.h"
 """
 
 
@@ -106,7 +105,7 @@ class PrintCode(gl_XML.gl_print_base):
 
 def print_async_dispatch(self, func):
 out('cmd = _mesa_glthread_allocate_command(ctx, '
-'DISPATCH_CMD_{0}, cmd_size);'.format(func.name))
+'(unmarshal_func)_mesa_unmarshal_{0}, 
cmd_size);'.format(func.name))
 for p in func.fixed_params:
 if p.count:
 out('memcpy(cmd->{0}, {0}, {1});'.format(
@@ -166,7 +165,7 @@ class PrintCode(gl_XML.gl_print_base):
 out('};')
 
 def print_async_unmarshal(self, func):
-out('static inline void')
+out('static void')
 out(('_mesa_unmarshal_{0}(struct gl_context *ctx, '
  'const struct marshal_cmd_{0} *cmd)').format(func.name))
 out('{')
@@ -205,6 +204,7 @@ class PrintCode(gl_XML.gl_print_base):
 else:
 out('variable_data += 
{0};'.format(p.size_string(False)))
 
+out('debug_print_unmarshal("{0}");'.format(func.name))
 self.print_sync_call(func)
 out('}')
 
@@ -276,35 +276,6 @@ class PrintCode(gl_XML.gl_print_base):
 out('')
 out('')
 
-def print_unmarshal_dispatch_cmd(self, api):
-out('size_t')
-out('_mesa_unmarshal_dispatch_cmd(struct gl_context *ctx, '
-'const void *cmd)')
-out('{')
-with indent():
-out('const struct marshal_cmd_base *cmd_base = cmd;')
-out('switch (cmd_base->cmd_id) {')
-for func in api.functionIterateAll():
-flavor = func.marshal_flavor()
-if flavor in ('skip', 'sync'):
-continue
-out('case DISPATCH_CMD_{0}:'.format(func.name))
-with indent():
-out('debug_print_unmarshal("{0}");'.format(func.name))
-out(('_mesa_unmarshal_{0}(ctx, (const struct 
marshal_cmd_{0} *)'
- ' cmd);').format(func.name))
-out('break;')
-out('default:')
-with indent():
-out('assert(!"Unrecognized command ID");')
-out('break;')
-out('}')
-out('')
-out('return cmd_base->cmd_size;')
-out('}')
-out('')
-out('')
-
 def print_create_marshal_table(self, api):
 out('struct _glapi_table *')
 out('_mesa_create_marshal_table(const struct gl_context *ctx)')
@@ -338,7 +309,6 @@ class PrintCode(gl_XML.gl_print_base):
 async_funcs.append(func)
 elif flavor == 'sync':
 self.print_sync_body(func)
-self.print_unmarshal_dispatch_cmd(api)
 self.print_create_marshal_table(api)
 
 
diff --git a/src/mapi/glapi/gen/gl_marshal_h.py 
b/src/mapi/glapi/gen/gl_marshal_h.py
deleted file mode 100644

Re: [Mesa-dev] [PATCH 13/30] i965/miptree: Add an explicit format parameter to create_for_dri_image

[Jason Ekstrand]

On Wed, Jun 28, 2017 at 11:09 AM, Jason Ekstrand 
wrote:

> On Wed, Jun 28, 2017 at 10:59 AM, Daniel Stone 
> wrote:
>
>> Hi,
>>
>> On 28 June 2017 at 16:35, Jason Ekstrand  wrote:
>> > On Wed, Jun 28, 2017 at 4:06 AM, Daniel Stone 
>> wrote:
>> >> On 28 June 2017 at 02:05, Jason Ekstrand  wrote:
>> >> > The long answer is that the DRI formats do not specify a colorspace.
>> >>
>> >> Also, strictly speaking, the DRI_IMAGE_FORMAT_* tokens don't specify a
>> >> colourspace, nor do the DRM FourCC tokens. DRI_IMAGE_FOURCC_* is
>> >> equivalent to the latter, bar the addition of a special and unique
>> >> SARGB8 token, i.e. ARGB with the sRGB transfer function (and
>> >> presumably primaries?). The rest are presumed UNORM.
>> >
>> > Wha?  What's the difference between SARGB8 and ARGB then?  My
>> > understanding was that scanout basically treats everything as sRGB
>> anyway.
>> > Clearly, my sRGB knowledge is imperfect.
>>
>> GBM_FORMAT_ARGB (aka DRI_IMAGE_FOURCC_ARGB), gets mapped to
>> DRI_IMAGE_FORMAT_ARGB, which gets mapped to
>> MESA_FORMAT_B8G8R8X8_UNORM (dri_util.c). Only
>> DRI_IMAGE_{FORMAT,FOURCC}_SARGB8 (no defined GBM token, but you can
>> pass it through the GBM API and it'll work sometimes) gets mapped to a
>> MESA_FORMAT_*_SRGB. So AFAICT, to get an sRGB scanout buffer from
>> Mesa/GBM, you'd need to allocate UNORM and do inverse-gamma in your
>> frag shader.
>>
>> Wayland similarly never maps anything to sRGB.
>>
>> X11 always imports EGLImages as UNORM, so blending would be broken in
>> a composited environment if we were actually allocating sRGB.
>>
>
> Blending *is* broken.  I had a long chat with Owen Taylor about this some
> time ago.  Everything comes into X11 sRGB encoded and scanout treats it's
> buffer as sRGB.  X11 then stomps everything to UNORM and blends in the
> wrong colorspace.
>
>
>> i965 tries pretty hard to allocate sRGB images in the pre-DRIImage,
>> DRI2 (as in the X11 protocol named 'DRI2') codepath, but this isn't
>> used by Wayland, GBM, or DRI3.
>>
>
> Except that whether you get an sRGB renderbuffer or not is governed by GLX
> and EGL and not Wayland/DRI2/DRI3.  In one of them (I think it's ES), the
> default is to get an sRGB renderbuffer but either is possible with both
> independent of how the image comes in.  We *do* see it on DRI3 and Wayland
> which is why this patch exists in the first place.
>

Inserting some asserts and running through CI confirms this.  There are
piles of times when we take a nominally UNORM DRI format and interpret it
as sRGB.


> So no, not for pretty much any externally-visible images AFAICT. Even
>> if it were true for scanout, the client would need to tell KMS, so KMS
>> could send a HDMI infoframe telling the display.
>>
>
> But scanout always does sRGB.  If you want real UNORM, then you'll have to
> add kernel API.
>
>
>> Colourspaces \_o_/
>>
>> > As for enums, sure, that can probably happen.  GL and ISL both have
>> enums
>> > for colorspace that we could re-use.
>>
>> Yes, having too few format tokens is not a problem we have. We seem to
>> have about as many of those as we have things called 'DRI2'.
>>
>
> Heh
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 01/18] nir/spirv: Move a "}"

[Jason Ekstrand]

On Thu, Jun 29, 2017 at 2:26 PM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> How did this even compile?
>

Because aparently C lets you put switch cases anywhere.


> Should we cc stable?
>

I debated that.  I don't think it's needed as this isn't actually a
functional change.


> Reviewed-by: Lionel Landwerlin 
>

Thanks!


> On 29/06/17 18:33, Jason Ekstrand wrote:
>
>> It's closing a "{" at the begining of a switch case.
>> ---
>>   src/compiler/spirv/vtn_variables.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/compiler/spirv/vtn_variables.c
>> b/src/compiler/spirv/vtn_variables.c
>> index 974adb5..31d1d76 100644
>> --- a/src/compiler/spirv/vtn_variables.c
>> +++ b/src/compiler/spirv/vtn_variables.c
>> @@ -1490,10 +1490,10 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp
>> opcode,
>> */
>>vtn_foreach_decoration(b, interface_type->val,
>> var_decoration_cb, var);
>>break;
>> +  }
>>   case vtn_variable_mode_param:
>>unreachable("Not created through OpVariable");
>> -  }
>>   case vtn_variable_mode_ubo:
>> case vtn_variable_mode_ssbo:
>>
>
>
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus.

[Clint Taylor]

Reviewed-by: Clinton Taylor 

-Clint



On 06/29/2017 02:34 PM, Rodrigo Vivi wrote:

By the Spec all CNL Y skus are 2+2, i.e. GT2.

This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")

v2: Add kernel commit id for reference.

Cc: Anusha Srivatsa 
Cc: Clinton Taylor 
Signed-off-by: Rodrigo Vivi 
---
  intel/intel_chipset.h | 16 +++-
  1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index e6b49d7..37579c6 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -237,6 +237,12 @@
  #define PCI_CHIP_CANNONLAKE_U_GT2_1   0x5A5A
  #define PCI_CHIP_CANNONLAKE_U_GT2_2   0x5A42
  #define PCI_CHIP_CANNONLAKE_U_GT2_3   0x5A4A
+#define PCI_CHIP_CANNONLAKE_Y_GT2_00x5A51
+#define PCI_CHIP_CANNONLAKE_Y_GT2_10x5A59
+#define PCI_CHIP_CANNONLAKE_Y_GT2_20x5A41
+#define PCI_CHIP_CANNONLAKE_Y_GT2_30x5A49
+#define PCI_CHIP_CANNONLAKE_Y_GT2_40x5A71
+#define PCI_CHIP_CANNONLAKE_Y_GT2_50x5A79
  
  #define IS_MOBILE(devid)	((devid) == PCI_CHIP_I855_GM || \

 (devid) == PCI_CHIP_I915_GM || \
@@ -501,12 +507,20 @@
 IS_GEN8(dev) || \
 IS_GEN9(dev))
  
+#define IS_CNL_Y(devid)		((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \

+(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
+(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \
+(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \
+(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \
+(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5)
+
  #define IS_CNL_U(devid)   ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 
|| \
 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
  
-#define IS_CANNONLAKE(devid)	(IS_CNL_U(devid))

+#define IS_CANNONLAKE(devid)   (IS_CNL_U(devid) || \
+IS_CNL_Y(devid))
  
  #define IS_GEN10(devid)		(IS_CANNONLAKE(devid))
  


___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus.

[Clint Taylor]

Reviewed-by: Clinton Taylor 

-Clint



On 06/29/2017 02:34 PM, Rodrigo Vivi wrote:

Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.

This is a copy of merged i915's
commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.")

v2: Remove PCI IDs for SKU not mentioned in spec.
v3: Add kernel commit id for reference.

Cc: Anusha Srivatsa 
Cc: Clinton Taylor 
Signed-off-by: Rodrigo Vivi 
---
  intel/intel_chipset.h | 13 +
  1 file changed, 13 insertions(+)

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 891b50f..e6b49d7 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -233,6 +233,11 @@
  #define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
  #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
  
+#define PCI_CHIP_CANNONLAKE_U_GT2_0	0x5A52

+#define PCI_CHIP_CANNONLAKE_U_GT2_10x5A5A
+#define PCI_CHIP_CANNONLAKE_U_GT2_20x5A42
+#define PCI_CHIP_CANNONLAKE_U_GT2_30x5A4A
+
  #define IS_MOBILE(devid)  ((devid) == PCI_CHIP_I855_GM || \
 (devid) == PCI_CHIP_I915_GM || \
 (devid) == PCI_CHIP_I945_GM || \
@@ -496,5 +501,13 @@
 IS_GEN8(dev) || \
 IS_GEN9(dev))
  
+#define IS_CNL_U(devid)		((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \

+(devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
+(devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
+(devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
+
+#define IS_CANNONLAKE(devid)   (IS_CNL_U(devid))
+
+#define IS_GEN10(devid)(IS_CANNONLAKE(devid))
  
  #endif /* _INTEL_CHIPSET_H */


___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] radeonsi: use a bitfield for tracking which shaders use bindless

[Timothy Arceri]

On 30/06/17 05:59, Samuel Pitoiset wrote:

This will allow to skip few partial flushes when bindless
descriptors have to be re-uploaded.

Signed-off-by: Samuel Pitoiset 
---
  src/gallium/drivers/radeonsi/si_blit.c  |  4 +--
  src/gallium/drivers/radeonsi/si_pipe.h  |  4 +--
  src/gallium/drivers/radeonsi/si_state_shaders.c | 38 +
  3 files changed, 30 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 631676bcd79..45a023d4e2c 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -795,9 +795,9 @@ static void si_decompress_textures(struct si_context *sctx, 
unsigned shader_mask
}
  
  	if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {

-   if (sctx->uses_bindless_samplers)
+   if (sctx->shader_uses_bindless_samplers_mask)
si_decompress_resident_textures(sctx);
-   if (sctx->uses_bindless_images)
+   if (sctx->shader_uses_bindless_images_mask)
si_decompress_resident_images(sctx);
} else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
if (sctx->cs_shader_state.program->uses_bindless_samplers)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index bd724e80a06..507635e7576 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -439,8 +439,8 @@ struct si_context {
struct util_dynarrayresident_tex_needs_depth_decompress;
  
  	/* Bindless state */

-   booluses_bindless_samplers;
-   booluses_bindless_images;
+   unsignedshader_uses_bindless_samplers_mask;
+   unsignedshader_uses_bindless_images_mask;


Probably doesn't make much difference here, but you could use uint8_t 
here. Or even uint16_t to leave some room for future stages.



  };
  
  /* cik_sdma.c */

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index af3f2a90e2a..1dd01b36c8f 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2221,20 +2221,34 @@ static void si_update_clip_regs(struct si_context *sctx,
si_mark_atom_dirty(sctx, >clip_regs);
  }
  
+static void si_update_shader_uses_bindless_masks(struct si_context *sctx,

+struct si_shader_selector *sel,
+enum pipe_shader_type type)
+{
+   if (si_shader_uses_bindless_samplers(sel))
+   sctx->shader_uses_bindless_samplers_mask |= 1u << type;
+   else
+   sctx->shader_uses_bindless_samplers_mask &= ~(1u << type);
+
+   if (si_shader_uses_bindless_images(sel))
+   sctx->shader_uses_bindless_images_mask |= 1u << type;
+   else
+   sctx->shader_uses_bindless_images_mask &= ~(1u << type);
+}
+
  static void si_update_common_shader_state(struct si_context *sctx)
  {
-   sctx->uses_bindless_samplers =
-   si_shader_uses_bindless_samplers(sctx->vs_shader.cso)  ||
-   si_shader_uses_bindless_samplers(sctx->gs_shader.cso)  ||
-   si_shader_uses_bindless_samplers(sctx->ps_shader.cso)  ||
-   si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
-   si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
-   sctx->uses_bindless_images =
-   si_shader_uses_bindless_images(sctx->vs_shader.cso)  ||
-   si_shader_uses_bindless_images(sctx->gs_shader.cso)  ||
-   si_shader_uses_bindless_images(sctx->ps_shader.cso)  ||
-   si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
-   si_shader_uses_bindless_images(sctx->tes_shader.cso);
+   si_update_shader_uses_bindless_masks(sctx, sctx->vs_shader.cso,
+PIPE_SHADER_VERTEX);
+   si_update_shader_uses_bindless_masks(sctx, sctx->ps_shader.cso,
+PIPE_SHADER_FRAGMENT);
+   si_update_shader_uses_bindless_masks(sctx, sctx->gs_shader.cso,
+PIPE_SHADER_GEOMETRY);
+   si_update_shader_uses_bindless_masks(sctx, sctx->tcs_shader.cso,
+PIPE_SHADER_TESS_CTRL);
+   si_update_shader_uses_bindless_masks(sctx, sctx->tes_shader.cso,
+PIPE_SHADER_TESS_EVAL);
+
sctx->do_update_shaders = true;
  }
  


___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] mesa: Avoid set comprehension.

[Dylan Baker]

Gahh, we're seriously still supporting 2.6 for builds? 2.6 was EOL in 2013, and
2.7 was shiny and new in 2010. It's also going to make hybridizing for 3.x
incredibly painful. If possible I'd really like to not support 2.6, though I'm
sure that will cause pain for the RHEL guys...

Quoting Vinson Lee (2017-06-28 23:20:14)
> Fix build error on CentOS 6.9 with Python 2.6.
> 
>   GENmain/format_fallback.c
>   File "./main/format_fallback.py", line 42
> names = {fmt.name for fmt in formats}
> ^
> SyntaxError: invalid syntax
> 
> Fixes: a1983223d883 ("mesa: Add _mesa_format_fallback_rgbx_to_rgba() [v2]")
> Signed-off-by: Vinson Lee 
> ---
>  src/mesa/main/format_fallback.py |2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/src/mesa/main/format_fallback.py 
> b/src/mesa/main/format_fallback.py
> index e3b9916..da88bd5 100644
> --- a/src/mesa/main/format_fallback.py
> +++ b/src/mesa/main/format_fallback.py
> @@ -39,7 +39,7 @@ def parse_args():
>  return p.parse_args()
>  
>  def get_rgbx_to_rgba_map(formats):
> -names = {fmt.name for fmt in formats}
> +names = set([fmt.name for fmt in formats])

Either way, this is the wrong way to implement this, this should be:

names = set(fmt.name for fmt in formats)

Which avoids building an intermediate list, and then converting to a set.

Dylan


signature.asc
Description: signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/4] i965/miptree: Tighten up finish_mcs_write

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

On 06/26/2017 11:49 AM, Jason Ekstrand wrote:
> Multisample surfaces only have a single miplevel so there's no reason to
> be passing the extra parameters around.  It only leads to confusion.
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15 ---
>  1 file changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index f5391a4..75e192a 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -2149,18 +2149,18 @@ intel_miptree_finish_ccs_write(struct brw_context 
> *brw,
>  static void
>  intel_miptree_finish_mcs_write(struct brw_context *brw,
> struct intel_mipmap_tree *mt,
> -   uint32_t level, uint32_t layer,
> -   bool written_with_aux)
> +   uint32_t layer,
> +   bool written_with_mcs)
>  {
> -   switch (intel_miptree_get_aux_state(mt, level, layer)) {
> +   switch (intel_miptree_get_aux_state(mt, 0, layer)) {
> case ISL_AUX_STATE_CLEAR:
> -  assert(written_with_aux);
> -  intel_miptree_set_aux_state(brw, mt, level, layer, 1,
> +  assert(written_with_mcs);
> +  intel_miptree_set_aux_state(brw, mt, 0, layer, 1,
>ISL_AUX_STATE_COMPRESSED_CLEAR);
>break;
>  
> case ISL_AUX_STATE_COMPRESSED_CLEAR:
> -  assert(written_with_aux);
> +  assert(written_with_mcs);
>break; /* Nothing to do */
>  
> case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
> @@ -2365,8 +2365,9 @@ intel_miptree_finish_write(struct brw_context *brw,
>   return;
>  
>if (mt->num_samples > 1) {
> + assert(level == 0);
>   for (uint32_t a = 0; a < num_layers; a++) {
> -intel_miptree_finish_mcs_write(brw, mt, level, start_layer + a,
> +intel_miptree_finish_mcs_write(brw, mt, start_layer + a,
> written_with_aux);
>   }
>} else {
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 4/4] i965/miptree: Partially resolve MCS for texture views

[Ian Romanick]

On 06/26/2017 11:49 AM, Jason Ekstrand wrote:
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 +++---
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index c94fb4f..829a4c5 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -2511,14 +2511,14 @@ intel_miptree_prepare_texture_slices(struct 
> brw_context *brw,
>   aux_supported = clear_supported = true;

Should this be changed to

  aux_supported = true;

And if that's the case, then maybe the whole thing should be

  aux_supported = (mt->num_samples > 1) ||
  can_texture_with_ccs(brw, mt, view_format);

>} else {
>   aux_supported = can_texture_with_ccs(brw, mt, view_format);
> -
> - /* Clear color is specified as ints or floats and the conversion is
> -  * done by the sampler.  If we have a texture view, we would have to
> -  * perform the clear color conversion manually.  Just disable clear
> -  * color.
> -  */
> - clear_supported = aux_supported && (mt->format == view_format);
>}
> +
> +  /* Clear color is specified as ints or floats and the conversion is
> +   * done by the sampler.  If we have a texture view, we would have to
> +   * perform the clear color conversion manually.  Just disable clear
> +   * color.
> +   */
> +  clear_supported = aux_supported && (mt->format == view_format);
> } else if (mt->format == MESA_FORMAT_S_UINT8) {
>aux_supported = clear_supported = false;
> } else {
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 4/4] intel: add GEN10 to IS_9XX.

[Rodrigo Vivi]

From: Paulo Zanoni 

As far as I understand, IS_9XX should return true for it.

Signed-off-by: Paulo Zanoni 
---
 intel/intel_chipset.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 37579c6..770d21f 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -505,7 +505,8 @@
 IS_GEN6(dev) || \
 IS_GEN7(dev) || \
 IS_GEN8(dev) || \
-IS_GEN9(dev))
+IS_GEN9(dev) || \
+IS_GEN10(dev))
 
 #define IS_CNL_Y(devid)((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 
|| \
 (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
-- 
1.9.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 3/4] intel/gen10: Add missed gen10 stuff

[Rodrigo Vivi]

From: Ben Widawsky 

This got lost on rebase, I believe

Signed-off-by: Ben Widawsky 
---
 intel/intel_bufmgr_gem.c | 2 ++
 intel/intel_decode.c | 4 +++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 45a26da..71f140f 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3662,6 +3662,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
bufmgr_gem->gen = 8;
else if (IS_GEN9(bufmgr_gem->pci_device))
bufmgr_gem->gen = 9;
+   else if (IS_GEN10(bufmgr_gem->pci_device))
+   bufmgr_gem->gen = 10;
else {
free(bufmgr_gem);
bufmgr_gem = NULL;
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 2721ffd..3a81500 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -3827,7 +3827,9 @@ drm_intel_decode_context_alloc(uint32_t devid)
ctx->devid = devid;
ctx->out = stdout;
 
-   if (IS_GEN9(devid))
+   if (IS_GEN10(devid))
+   ctx->gen = 10;
+   else if (IS_GEN9(devid))
ctx->gen = 9;
else if (IS_GEN8(devid))
ctx->gen = 8;
-- 
1.9.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus.

[Rodrigo Vivi]

Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.

This is a copy of merged i915's
commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.")

v2: Remove PCI IDs for SKU not mentioned in spec.
v3: Add kernel commit id for reference.

Cc: Anusha Srivatsa 
Cc: Clinton Taylor 
Signed-off-by: Rodrigo Vivi 
---
 intel/intel_chipset.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 891b50f..e6b49d7 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -233,6 +233,11 @@
 #define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
 #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
 
+#define PCI_CHIP_CANNONLAKE_U_GT2_00x5A52
+#define PCI_CHIP_CANNONLAKE_U_GT2_10x5A5A
+#define PCI_CHIP_CANNONLAKE_U_GT2_20x5A42
+#define PCI_CHIP_CANNONLAKE_U_GT2_30x5A4A
+
 #define IS_MOBILE(devid)   ((devid) == PCI_CHIP_I855_GM || \
 (devid) == PCI_CHIP_I915_GM || \
 (devid) == PCI_CHIP_I945_GM || \
@@ -496,5 +501,13 @@
 IS_GEN8(dev) || \
 IS_GEN9(dev))
 
+#define IS_CNL_U(devid)((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 
|| \
+(devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
+(devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
+(devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
+
+#define IS_CANNONLAKE(devid)   (IS_CNL_U(devid))
+
+#define IS_GEN10(devid)(IS_CANNONLAKE(devid))
 
 #endif /* _INTEL_CHIPSET_H */
-- 
1.9.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus.

[Rodrigo Vivi]

By the Spec all CNL Y skus are 2+2, i.e. GT2.

This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")

v2: Add kernel commit id for reference.

Cc: Anusha Srivatsa 
Cc: Clinton Taylor 
Signed-off-by: Rodrigo Vivi 
---
 intel/intel_chipset.h | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index e6b49d7..37579c6 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -237,6 +237,12 @@
 #define PCI_CHIP_CANNONLAKE_U_GT2_10x5A5A
 #define PCI_CHIP_CANNONLAKE_U_GT2_20x5A42
 #define PCI_CHIP_CANNONLAKE_U_GT2_30x5A4A
+#define PCI_CHIP_CANNONLAKE_Y_GT2_00x5A51
+#define PCI_CHIP_CANNONLAKE_Y_GT2_10x5A59
+#define PCI_CHIP_CANNONLAKE_Y_GT2_20x5A41
+#define PCI_CHIP_CANNONLAKE_Y_GT2_30x5A49
+#define PCI_CHIP_CANNONLAKE_Y_GT2_40x5A71
+#define PCI_CHIP_CANNONLAKE_Y_GT2_50x5A79
 
 #define IS_MOBILE(devid)   ((devid) == PCI_CHIP_I855_GM || \
 (devid) == PCI_CHIP_I915_GM || \
@@ -501,12 +507,20 @@
 IS_GEN8(dev) || \
 IS_GEN9(dev))
 
+#define IS_CNL_Y(devid)((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 
|| \
+(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
+(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \
+(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \
+(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \
+(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5)
+
 #define IS_CNL_U(devid)((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 
|| \
 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
 
-#define IS_CANNONLAKE(devid)   (IS_CNL_U(devid))
+#define IS_CANNONLAKE(devid)   (IS_CNL_U(devid) || \
+IS_CNL_Y(devid))
 
 #define IS_GEN10(devid)(IS_CANNONLAKE(devid))
 
-- 
1.9.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 01/18] nir/spirv: Move a "}"

[Lionel Landwerlin]

How did this even compile?

Should we cc stable?

Reviewed-by: Lionel Landwerlin 

On 29/06/17 18:33, Jason Ekstrand wrote:

It's closing a "{" at the begining of a switch case.
---
  src/compiler/spirv/vtn_variables.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 974adb5..31d1d76 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1490,10 +1490,10 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp 
opcode,
*/
   vtn_foreach_decoration(b, interface_type->val, var_decoration_cb, 
var);
   break;
+  }
  
case vtn_variable_mode_param:

   unreachable("Not created through OpVariable");
-  }
  
case vtn_variable_mode_ubo:

case vtn_variable_mode_ssbo:



___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/2] radv: lways set depthbuffer using image format instead of iview format.

[Bas Nieuwenhuizen]

We have some cases where changing between depth and stencil only aspect
was causing hangs.

Signed-off-by: Bas Nieuwenhuizen 
---
 src/amd/vulkan/radv_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 427d35769d9..169968e228e 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2876,7 +2876,7 @@ radv_initialise_ds_surface(struct radv_device *device,
uint64_t va, s_offs, z_offs;
bool stencil_only = false;
memset(ds, 0, sizeof(*ds));
-   switch (iview->vk_format) {
+   switch (iview->image->vk_format) {
case VK_FORMAT_D24_UNORM_S8_UINT:
case VK_FORMAT_X8_D24_UNORM_PACK32:
ds->pa_su_poly_offset_db_fmt_cntl = 
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
@@ -2900,7 +2900,7 @@ radv_initialise_ds_surface(struct radv_device *device,
break;
}
 
-   format = radv_translate_dbformat(iview->vk_format);
+   format = radv_translate_dbformat(iview->image->vk_format);
stencil_format = iview->image->surface.flags & RADEON_SURF_SBUFFER ?
V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
 
-- 
2.13.2

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/2] radv: Disable depth & stencil tests when the depthbuffer doesn't support it.

[Bas Nieuwenhuizen]

Signed-off-by: Bas Nieuwenhuizen 
---
 src/amd/vulkan/radv_meta_blit.c   |  4 ++--
 src/amd/vulkan/radv_meta_blit2d.c |  4 ++--
 src/amd/vulkan/radv_meta_clear.c  |  2 +-
 src/amd/vulkan/radv_meta_decompress.c |  2 +-
 src/amd/vulkan/radv_pipeline.c| 22 +-
 src/amd/vulkan/vk_format.h| 13 +
 6 files changed, 36 insertions(+), 11 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c
index 89ff82ec68d..718e9c50e6e 100644
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -881,7 +881,7 @@ radv_device_init_meta_blit_depth(struct radv_device *device,
   .sType = 
VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
   .attachmentCount = 1,
   .pAttachments = 
&(VkAttachmentDescription) {
-  .format = 0,
+  .format = 
VK_FORMAT_D32_SFLOAT,
   .loadOp = 
VK_ATTACHMENT_LOAD_OP_LOAD,
   .storeOp = 
VK_ATTACHMENT_STORE_OP_STORE,
   .initialLayout = 
VK_IMAGE_LAYOUT_GENERAL,
@@ -1039,7 +1039,7 @@ radv_device_init_meta_blit_stencil(struct radv_device 
*device,
   .sType = 
VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
   .attachmentCount = 1,
   .pAttachments = 
&(VkAttachmentDescription) {
-  .format = 0,
+  .format = 
VK_FORMAT_S8_UINT,
   .loadOp = 
VK_ATTACHMENT_LOAD_OP_LOAD,
   .storeOp = 
VK_ATTACHMENT_STORE_OP_STORE,
   .initialLayout = 
VK_IMAGE_LAYOUT_GENERAL,
diff --git a/src/amd/vulkan/radv_meta_blit2d.c 
b/src/amd/vulkan/radv_meta_blit2d.c
index fb14cfbcdda..2f18350fd71 100644
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -858,7 +858,7 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
   .sType = 
VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
   .attachmentCount 
= 1,
   .pAttachments = 
&(VkAttachmentDescription) {
-  .format = 0,
+  .format = 
VK_FORMAT_D32_SFLOAT,
   .loadOp = 
VK_ATTACHMENT_LOAD_OP_LOAD,
   .storeOp = 
VK_ATTACHMENT_STORE_OP_STORE,
   .initialLayout = 
VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
@@ -1013,7 +1013,7 @@ blit2d_init_stencil_only_pipeline(struct radv_device 
*device,
   .sType = 
VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
   .attachmentCount 
= 1,
   .pAttachments = 
&(VkAttachmentDescription) {
-  .format = 0,
+  .format = 
VK_FORMAT_S8_UINT,
   .loadOp = 
VK_ATTACHMENT_LOAD_OP_LOAD,
   .storeOp = 
VK_ATTACHMENT_STORE_OP_STORE,
   .initialLayout = 
VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 06485137fc7..bd979973e71 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -455,7 +455,7 @@ create_depthstencil_renderpass(struct radv_device *device,
   .sType = 
VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
   .attachmentCount = 1,
   .pAttachments = 
&(VkAttachmentDescription) {
-  .format = 
VK_FORMAT_UNDEFINED,
+  .format = 
VK_FORMAT_D32_SFLOAT_S8_UINT,
   .samples = 

Re: [Mesa-dev] [PATCH 05/14] gallium/radeon: clean up r600_texture_get_handle

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 06/29/2017 09:47 PM, Marek Olšák wrote:

From: Marek Olšák 

---
  src/gallium/drivers/radeon/r600_texture.c | 47 +++
  1 file changed, 23 insertions(+), 24 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index c811d6a..e21dc37 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -530,28 +530,27 @@ static boolean r600_texture_get_handle(struct 
pipe_screen* screen,
struct r600_common_context *rctx;
struct r600_resource *res = (struct r600_resource*)resource;
struct r600_texture *rtex = (struct r600_texture*)resource;
struct radeon_bo_metadata metadata;
bool update_metadata = false;
unsigned stride, offset, slice_size;
  
  	ctx = threaded_context_unwrap_sync(ctx);

rctx = (struct r600_common_context*)(ctx ? ctx : rscreen->aux_context);
  
-	/* This is not supported now, but it might be required for OpenCL

-* interop in the future.
-*/
-   if (resource->target != PIPE_BUFFER &&
-   (resource->nr_samples > 1 || rtex->is_depth))
-   return false;
-
if (resource->target != PIPE_BUFFER) {
+   /* This is not supported now, but it might be required for 
OpenCL
+* interop in the future.
+*/
+   if (resource->nr_samples > 1 || rtex->is_depth)
+   return false;
+
/* Since shader image stores don't support DCC on VI,
 * disable it for external clients that want write
 * access.
 */
if (usage & PIPE_HANDLE_USAGE_WRITE && rtex->dcc_offset) {
if (r600_texture_disable_dcc(rctx, rtex))
update_metadata = true;
}
  
  		if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&

@@ -568,51 +567,51 @@ static boolean r600_texture_get_handle(struct 
pipe_screen* screen,
  
  		/* Set metadata. */

if (!res->b.is_shared || update_metadata) {
r600_texture_init_metadata(rscreen, rtex, );
if (rscreen->query_opaque_metadata)
rscreen->query_opaque_metadata(rscreen, rtex,
   );
  
  			rscreen->ws->buffer_set_metadata(res->buf, );

}
+
+   if (rscreen->chip_class >= GFX9) {
+   offset = rtex->surface.u.gfx9.surf_offset;
+   stride = rtex->surface.u.gfx9.surf_pitch *
+rtex->surface.bpe;
+   slice_size = rtex->surface.u.gfx9.surf_slice_size;
+   } else {
+   offset = rtex->surface.u.legacy.level[0].offset;
+   stride = rtex->surface.u.legacy.level[0].nblk_x *
+rtex->surface.bpe;
+   slice_size = rtex->surface.u.legacy.level[0].slice_size;
+   }
+   } else {
+   /* Buffers */
+   offset = 0;
+   stride = 0;
+   slice_size = 0;
}
  
  	if (res->b.is_shared) {

/* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
 * doesn't set it.
 */
res->external_usage |= usage & 
~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
res->external_usage &= 
~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
} else {
res->b.is_shared = true;
res->external_usage = usage;
}
  
-	if (res->b.b.target == PIPE_BUFFER) {

-   offset = 0;
-   stride = 0;
-   slice_size = 0;
-   } else {
-   if (rscreen->chip_class >= GFX9) {
-   offset = rtex->surface.u.gfx9.surf_offset;
-   stride = rtex->surface.u.gfx9.surf_pitch *
-rtex->surface.bpe;
-   slice_size = rtex->surface.u.gfx9.surf_slice_size;
-   } else {
-   offset = rtex->surface.u.legacy.level[0].offset;
-   stride = rtex->surface.u.legacy.level[0].nblk_x *
-rtex->surface.bpe;
-   slice_size = rtex->surface.u.legacy.level[0].slice_size;
-   }
-   }
return rscreen->ws->buffer_get_handle(res->buf, stride, offset,
  slice_size, whandle);
  }
  
  static void r600_texture_destroy(struct pipe_screen *screen,

 struct pipe_resource *ptex)
  {
struct r600_texture *rtex = (struct r600_texture*)ptex;

Re: [Mesa-dev] [PATCH 04/14] gallium/radeon: rename RADEON_FLAG_HANDLE -> RADEON_FLAG_NO_SUBALLOC

[Samuel Pitoiset]

Looks better.

Reviewed-by: Samuel Pitoiset 

On 06/29/2017 09:47 PM, Marek Olšák wrote:

From: Marek Olšák 

---
  src/gallium/drivers/r300/r300_texture.c   | 2 +-
  src/gallium/drivers/radeon/r600_texture.c | 2 +-
  src/gallium/drivers/radeon/radeon_winsys.h| 2 +-
  src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 6 +++---
  src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 4 ++--
  src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 2 +-
  6 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/r300/r300_texture.c 
b/src/gallium/drivers/r300/r300_texture.c
index c202fbe..cdf9ccb 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -1112,21 +1112,21 @@ r300_texture_create_object(struct r300_screen *rscreen,
  tex->domain &= ~RADEON_DOMAIN_GTT;
  }
  /* Just fail if the texture is too large. */
  if (!tex->domain) {
  goto fail;
  }
  
  /* Create the backing buffer if needed. */

  if (!tex->buf) {
  tex->buf = rws->buffer_create(rws, tex->tex.size_in_bytes, 2048,
-  tex->domain, RADEON_FLAG_HANDLE);
+  tex->domain, RADEON_FLAG_NO_SUBALLOC);
  
  if (!tex->buf) {

  goto fail;
  }
  }
  
  if (SCREEN_DBG_ON(rscreen, DBG_MSAA) && base->nr_samples > 1) {

  fprintf(stderr, "r300: %ix MSAA %s buffer created\n",
  base->nr_samples,
  util_format_is_depth_or_stencil(base->format) ? "depth" : 
"color");
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 139ab13..c811d6a 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1199,21 +1199,21 @@ r600_texture_create_object(struct pipe_screen *screen,
rtex->dcc_offset = align64(rtex->size, 
rtex->surface.dcc_alignment);
rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
}
}
  
  	/* Now create the backing buffer. */

if (!buf) {
r600_init_resource_fields(rscreen, resource, rtex->size,
  rtex->surface.surf_alignment);
  
-		resource->flags |= RADEON_FLAG_HANDLE;

+   resource->flags |= RADEON_FLAG_NO_SUBALLOC;
  
  		if (!r600_alloc_resource(rscreen, resource)) {

FREE(rtex);
return NULL;
}
} else {
resource->buf = buf;
resource->gpu_address = 
rscreen->ws->buffer_get_virtual_address(resource->buf);
resource->bo_size = buf->size;
resource->bo_alignment = buf->alignment;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 247fff0..706188f 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -46,21 +46,21 @@ enum radeon_bo_layout {
  enum radeon_bo_domain { /* bitfield */
  RADEON_DOMAIN_GTT  = 2,
  RADEON_DOMAIN_VRAM = 4,
  RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  };
  
  enum radeon_bo_flag { /* bitfield */

  RADEON_FLAG_GTT_WC =(1 << 0),
  RADEON_FLAG_CPU_ACCESS =(1 << 1),
  RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
-RADEON_FLAG_HANDLE =(1 << 3), /* the buffer must not be 
suballocated */
+RADEON_FLAG_NO_SUBALLOC =   (1 << 3),
  RADEON_FLAG_SPARSE =(1 << 4),
  };
  
  enum radeon_bo_usage { /* bitfield */

  RADEON_USAGE_READ = 2,
  RADEON_USAGE_WRITE = 4,
  RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  
  /* The winsys ensures that the CS submission will be scheduled after

   * previously flushed CSs referencing this BO in a conflicting way.
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 4017411..a86cc2c 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -683,21 +683,21 @@ sparse_backing_alloc(struct amdgpu_winsys_bo *bo, 
uint32_t *pstart_page, uint32_
  
assert(bo->u.sparse.num_backing_pages < DIV_ROUND_UP(bo->base.size, RADEON_SPARSE_PAGE_SIZE));
  
size = MIN3(bo->base.size / 16,

8 * 1024 * 1024,
bo->base.size - (uint64_t)bo->u.sparse.num_backing_pages * 
RADEON_SPARSE_PAGE_SIZE);
size = MAX2(size, RADEON_SPARSE_PAGE_SIZE);
  
buf = amdgpu_bo_create(>ws->base, size, RADEON_SPARSE_PAGE_SIZE,

   bo->initial_domain,
- bo->u.sparse.flags | RADEON_FLAG_HANDLE);
+ bo->u.sparse.flags | RADEON_FLAG_NO_SUBALLOC);
if (!buf) {
   

Re: [Mesa-dev] [PATCH 01/14] radeonsi: add a HUD query for getting an average GFX BO list size

[Samuel Pitoiset]

On 06/29/2017 09:47 PM, Marek Olšák wrote:

From: Marek Olšák 

---
  src/gallium/drivers/radeon/r600_query.c   | 18 ++
  src/gallium/drivers/radeon/r600_query.h   |  1 +
  src/gallium/drivers/radeon/radeon_winsys.h|  1 +
  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c |  3 +++
  src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |  2 ++
  src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h |  1 +
  src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |  1 +
  7 files changed, 27 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_query.c 
b/src/gallium/drivers/radeon/r600_query.c
index 3308ad8..db70878 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -64,20 +64,21 @@ static enum radeon_value_id winsys_id_from_type(unsigned 
type)
  {
switch (type) {
case R600_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
case R600_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
case R600_QUERY_MAPPED_VRAM: return RADEON_MAPPED_VRAM;
case R600_QUERY_MAPPED_GTT: return RADEON_MAPPED_GTT;
case R600_QUERY_BUFFER_WAIT_TIME: return RADEON_BUFFER_WAIT_TIME_NS;
case R600_QUERY_NUM_MAPPED_BUFFERS: return RADEON_NUM_MAPPED_BUFFERS;
case R600_QUERY_NUM_GFX_IBS: return RADEON_NUM_GFX_IBS;
case R600_QUERY_NUM_SDMA_IBS: return RADEON_NUM_SDMA_IBS;
+   case R600_QUERY_GFX_BO_LIST_SIZE: return RADEON_GFX_BO_LIST_COUNTER;
case R600_QUERY_NUM_BYTES_MOVED: return RADEON_NUM_BYTES_MOVED;
case R600_QUERY_NUM_EVICTIONS: return RADEON_NUM_EVICTIONS;
case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: return 
RADEON_NUM_VRAM_CPU_PAGE_FAULTS;
case R600_QUERY_VRAM_USAGE: return RADEON_VRAM_USAGE;
case R600_QUERY_VRAM_VIS_USAGE: return RADEON_VRAM_VIS_USAGE;
case R600_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
case R600_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
case R600_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
case R600_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
case R600_QUERY_CS_THREAD_BUSY: return RADEON_CS_THREAD_TIME;
@@ -166,20 +167,26 @@ static bool r600_query_sw_begin(struct 
r600_common_context *rctx,
case R600_QUERY_BUFFER_WAIT_TIME:
case R600_QUERY_NUM_GFX_IBS:
case R600_QUERY_NUM_SDMA_IBS:
case R600_QUERY_NUM_BYTES_MOVED:
case R600_QUERY_NUM_EVICTIONS:
case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
break;
}
+   case R600_QUERY_GFX_BO_LIST_SIZE:
+   ws_id = winsys_id_from_type(query->b.type);
+   query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
+   query->begin_time = rctx->ws->query_value(rctx->ws,
+ RADEON_NUM_GFX_IBS);


begin_time for counting the number of graphics IBs is confusing, but 
either way, it's debug code. :)


Reviewed-by: Samuel Pitoiset 


+   break;
case R600_QUERY_CS_THREAD_BUSY:
ws_id = winsys_id_from_type(query->b.type);
query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
query->begin_time = os_time_get_nano();
break;
case R600_QUERY_GALLIUM_THREAD_BUSY:
query->begin_result =
rctx->tc ? 
util_queue_get_thread_time_nano(>tc->queue, 0) : 0;
query->begin_time = os_time_get_nano();
break;
@@ -311,20 +318,26 @@ static bool r600_query_sw_end(struct r600_common_context 
*rctx,
case R600_QUERY_NUM_MAPPED_BUFFERS:
case R600_QUERY_NUM_GFX_IBS:
case R600_QUERY_NUM_SDMA_IBS:
case R600_QUERY_NUM_BYTES_MOVED:
case R600_QUERY_NUM_EVICTIONS:
case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
break;
}
+   case R600_QUERY_GFX_BO_LIST_SIZE:
+   ws_id = winsys_id_from_type(query->b.type);
+   query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
+   query->end_time = rctx->ws->query_value(rctx->ws,
+   RADEON_NUM_GFX_IBS);
+   break;
case R600_QUERY_CS_THREAD_BUSY:
ws_id = winsys_id_from_type(query->b.type);
query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
query->end_time = os_time_get_nano();
break;
case R600_QUERY_GALLIUM_THREAD_BUSY:
query->end_result =

Re: [Mesa-dev] [PATCH 0/9] glsl: misc cleanups and improvements

[Ian Romanick]

Patches 1, 2, 3, and 8 are

Reviewed-by: Ian Romanick 

I sent some comments on 5, and I'm still thinking about 4.  The rest are
in areas that I don't know well.

On 06/26/2017 02:40 AM, Nicolai Hähnle wrote:
> Hi all,
> 
> This is a bit of a random collection of small patches. What ties them 
> together is that they're all vaguely related to the glsl code, and that they 
> accumulated while I was working on ARB_gl_spirv. They do make sense 
> individually though. I see no regressions here with assertions enabled on a 
> piglit all run.
> 
> Please review!
> 
> Cheers,
> Nicolai
> --
>  src/compiler/Makefile.am   |   2 +
>  src/compiler/glsl/blob.c   |  12 +++
>  src/compiler/glsl/ir_print_visitor.cpp |   2 +-
>  src/compiler/glsl/linker.cpp   | 118 ---
>  src/mesa/main/mtypes.h |   2 +
>  src/mesa/program/ir_to_mesa.cpp|  20 ++--
>  src/mesa/state_tracker/st_program.h|   1 -
>  src/util/disk_cache.h  |   2 +-
>  8 files changed, 88 insertions(+), 71 deletions(-)
> 
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 5/9] glsl: explicitly zero out padding to gl_shader_variable bitfield

[Ian Romanick]

On 06/26/2017 02:40 AM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle 
> 
> Otherwise, the padding bits remain undefined, which leads to valgrind
> errors when storing the gl_shader_variable in the disk cache.

libdrm used to use VG_CLEAR() for things like this.  Having explicitly
sized padding fields is, as Timothy points out, difficult to maintain.
Could we just memset() the whole thing first and let GCC optimize?

> ---
>  src/compiler/glsl/linker.cpp | 1 +
>  src/mesa/main/mtypes.h   | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
> index cfda263..691c4cb 100644
> --- a/src/compiler/glsl/linker.cpp
> +++ b/src/compiler/glsl/linker.cpp
> @@ -3755,20 +3755,21 @@ create_shader_variable(struct gl_shader_program 
> *shProg,
> out->type = type;
> out->outermost_struct_type = outermost_struct_type;
> out->interface_type = interface_type;
> out->component = in->data.location_frac;
> out->index = in->data.index;
> out->patch = in->data.patch;
> out->mode = in->data.mode;
> out->interpolation = in->data.interpolation;
> out->explicit_location = in->data.explicit_location;
> out->precision = in->data.precision;
> +   out->padding = 0;
>  
> return out;
>  }
>  
>  static bool
>  add_shader_variable(const struct gl_context *ctx,
>  struct gl_shader_program *shProg,
>  struct set *resource_set,
>  unsigned stage_mask,
>  GLenum programInterface, ir_variable *var,
> diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
> index 0cb0024..a1fc743 100644
> --- a/src/mesa/main/mtypes.h
> +++ b/src/mesa/main/mtypes.h
> @@ -2813,20 +2813,22 @@ struct gl_shader_variable
>  * If the location is explicitly set in the shader, it \b cannot be 
> changed
>  * by the linker or by the API (e.g., calls to \c glBindAttribLocation 
> have
>  * no effect).
>  */
> unsigned explicit_location:1;
>  
> /**
>  * Precision qualifier.
>  */
> unsigned precision:2;
> +
> +   unsigned padding:19;
>  };
>  
>  /**
>   * Active resource in a gl_shader_program
>   */
>  struct gl_program_resource
>  {
> GLenum Type; /** Program interface type. */
> const void *Data; /** Pointer to resource associated data structure. */
> uint8_t StageReferences; /** Bitmask of shader stage references. */
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] dri2: Sync i965_pci_ids.h from Mesa.

[Rodrigo Vivi]

Copied from Mesa with no modifications.

Gives us Coffee Lake and Cannon Lake PCI IDs.

Cc: Kenneth Graunke 
Cc: Eric Anholt 
Signed-off-by: Rodrigo Vivi 
---
 hw/xfree86/dri2/pci_ids/i965_pci_ids.h | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/hw/xfree86/dri2/pci_ids/i965_pci_ids.h 
b/hw/xfree86/dri2/pci_ids/i965_pci_ids.h
index 17504f5..57e70b7 100644
--- a/hw/xfree86/dri2/pci_ids/i965_pci_ids.h
+++ b/hw/xfree86/dri2/pci_ids/i965_pci_ids.h
@@ -165,3 +165,26 @@ CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 
(Kaby Lake GT3)")
 CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
 CHIPSET(0x3184, glk, "Intel(R) HD Graphics (Geminilake)")
 CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
+CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E91, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E92, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E9B, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E94, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3EA6, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x3EA7, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x3EA8, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
+CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
+CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A42, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A44, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A59, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A5A, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A5C, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
-- 
1.9.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/2] radeonsi: drop few partial flushes when uploading bindless descriptors

[Samuel Pitoiset]

Only emit partial flushes when the underlying shader stages
are using bindless samplers or images.

This gets rid of 4% of partial flushes in the DOW3 benchmark.

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/drivers/radeonsi/si_descriptors.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 88f7dcee959..7d8b3670887 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1934,14 +1934,28 @@ static void si_upload_bindless_descriptor(struct 
si_context *sctx,
 
 static void si_upload_bindless_descriptors(struct si_context *sctx)
 {
+   unsigned shader_uses_bindless_mask;
+
if (!sctx->bindless_descriptors_dirty)
return;
 
/* Wait for graphics/compute to be idle before updating the resident
 * descriptors directly in memory, in case the GPU is using them.
 */
-   sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
-SI_CONTEXT_CS_PARTIAL_FLUSH;
+   sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
+
+   /* To avoid unnecessary partial flushes, check which shader stages are
+* using bindless samplers or images.
+*/
+   shader_uses_bindless_mask = sctx->shader_uses_bindless_samplers_mask |
+   sctx->shader_uses_bindless_images_mask;
+
+   if (shader_uses_bindless_mask & (1 << PIPE_SHADER_FRAGMENT)) {
+   sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
+   } else if (shader_uses_bindless_mask) {
+   sctx->b.flags |= SI_CONTEXT_VS_PARTIAL_FLUSH;
+   }
+
si_emit_cache_flush(sctx);
 
util_dynarray_foreach(>resident_tex_handles,
-- 
2.13.2

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/2] radeonsi: use a bitfield for tracking which shaders use bindless

[Samuel Pitoiset]

This will allow to skip few partial flushes when bindless
descriptors have to be re-uploaded.

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/drivers/radeonsi/si_blit.c  |  4 +--
 src/gallium/drivers/radeonsi/si_pipe.h  |  4 +--
 src/gallium/drivers/radeonsi/si_state_shaders.c | 38 +
 3 files changed, 30 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 631676bcd79..45a023d4e2c 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -795,9 +795,9 @@ static void si_decompress_textures(struct si_context *sctx, 
unsigned shader_mask
}
 
if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
-   if (sctx->uses_bindless_samplers)
+   if (sctx->shader_uses_bindless_samplers_mask)
si_decompress_resident_textures(sctx);
-   if (sctx->uses_bindless_images)
+   if (sctx->shader_uses_bindless_images_mask)
si_decompress_resident_images(sctx);
} else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
if (sctx->cs_shader_state.program->uses_bindless_samplers)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index bd724e80a06..507635e7576 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -439,8 +439,8 @@ struct si_context {
struct util_dynarrayresident_tex_needs_depth_decompress;
 
/* Bindless state */
-   booluses_bindless_samplers;
-   booluses_bindless_images;
+   unsignedshader_uses_bindless_samplers_mask;
+   unsignedshader_uses_bindless_images_mask;
 };
 
 /* cik_sdma.c */
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index af3f2a90e2a..1dd01b36c8f 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2221,20 +2221,34 @@ static void si_update_clip_regs(struct si_context *sctx,
si_mark_atom_dirty(sctx, >clip_regs);
 }
 
+static void si_update_shader_uses_bindless_masks(struct si_context *sctx,
+struct si_shader_selector *sel,
+enum pipe_shader_type type)
+{
+   if (si_shader_uses_bindless_samplers(sel))
+   sctx->shader_uses_bindless_samplers_mask |= 1u << type;
+   else
+   sctx->shader_uses_bindless_samplers_mask &= ~(1u << type);
+
+   if (si_shader_uses_bindless_images(sel))
+   sctx->shader_uses_bindless_images_mask |= 1u << type;
+   else
+   sctx->shader_uses_bindless_images_mask &= ~(1u << type);
+}
+
 static void si_update_common_shader_state(struct si_context *sctx)
 {
-   sctx->uses_bindless_samplers =
-   si_shader_uses_bindless_samplers(sctx->vs_shader.cso)  ||
-   si_shader_uses_bindless_samplers(sctx->gs_shader.cso)  ||
-   si_shader_uses_bindless_samplers(sctx->ps_shader.cso)  ||
-   si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
-   si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
-   sctx->uses_bindless_images =
-   si_shader_uses_bindless_images(sctx->vs_shader.cso)  ||
-   si_shader_uses_bindless_images(sctx->gs_shader.cso)  ||
-   si_shader_uses_bindless_images(sctx->ps_shader.cso)  ||
-   si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
-   si_shader_uses_bindless_images(sctx->tes_shader.cso);
+   si_update_shader_uses_bindless_masks(sctx, sctx->vs_shader.cso,
+PIPE_SHADER_VERTEX);
+   si_update_shader_uses_bindless_masks(sctx, sctx->ps_shader.cso,
+PIPE_SHADER_FRAGMENT);
+   si_update_shader_uses_bindless_masks(sctx, sctx->gs_shader.cso,
+PIPE_SHADER_GEOMETRY);
+   si_update_shader_uses_bindless_masks(sctx, sctx->tcs_shader.cso,
+PIPE_SHADER_TESS_CTRL);
+   si_update_shader_uses_bindless_masks(sctx, sctx->tes_shader.cso,
+PIPE_SHADER_TESS_EVAL);
+
sctx->do_update_shaders = true;
 }
 
-- 
2.13.2

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] vc4: Introduce XML-based packet header generation like Intel's.

[Rob Herring]

On Wed, Jun 28, 2017 at 1:18 PM, Eric Anholt  wrote:
> I really liked this idea, as it should help with management of packet
> parsing tools like the CL dump.  The python script is forked off of theirs
> because our packets are byte-based instead of dwords, and the changes to
> do so while avoiding performance regressions due to unaligned accesses
> were quite invasive.
> ---
>
> I'm hoping for an ack from Jason or Kenneth on the genxml script fork
> to the new location, and an Android test from Rob.  Full branch using
> the XML stuff is at vc4-xml of my Mesa tree.
>
>  Android.mk |   1 +
>  configure.ac   |   1 +
>  src/Makefile.am|   4 +
>  src/broadcom/.gitignore|   1 +
>  .../Android.genxml.mk} |  43 +-
>  src/{intel => broadcom}/Android.mk |   5 -
>  src/{amd => broadcom}/Makefile.am  |  22 +-
>  .../Makefile.genxml.am}|  18 +-
>  src/broadcom/Makefile.sources  |  12 +
>  src/broadcom/cle/gen_pack_header.py| 547 
> +
>  src/broadcom/cle/v3d_packet_helpers.h  | 189 +++
>  src/broadcom/cle/v3d_packet_v21.xml| 220 +
>  src/gallium/drivers/vc4/Android.mk |   5 +-
>  13 files changed, 1035 insertions(+), 33 deletions(-)
>  create mode 100644 src/broadcom/.gitignore
>  copy src/{mesa/Android.libmesa_git_sha1.mk => broadcom/Android.genxml.mk} 
> (60%)
>  copy src/{intel => broadcom}/Android.mk (86%)
>  copy src/{amd => broadcom}/Makefile.am (75%)
>  copy src/{intel/Makefile.common.am => broadcom/Makefile.genxml.am} (74%)
>  create mode 100644 src/broadcom/Makefile.sources
>  create mode 100644 src/broadcom/cle/gen_pack_header.py
>  create mode 100644 src/broadcom/cle/v3d_packet_helpers.h
>  create mode 100644 src/broadcom/cle/v3d_packet_v21.xml
>
> diff --git a/Android.mk b/Android.mk
> index 418570e607bb..9203c87a4e35 100644
> --- a/Android.mk
> +++ b/Android.mk
> @@ -112,6 +112,7 @@ SUBDIRS := \
> src/util \
> src/egl \
> src/amd \
> +   src/broadcom \
> src/intel \
> src/mesa/drivers/dri \
> src/vulkan
> diff --git a/configure.ac b/configure.ac
> index c9dc51bc0d86..cb5d6683afe6 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -2734,6 +2734,7 @@ AC_CONFIG_FILES([Makefile
> src/Makefile
> src/amd/Makefile
> src/amd/vulkan/Makefile
> +   src/broadcom/Makefile
> src/compiler/Makefile
> src/egl/Makefile
> src/egl/main/egl.pc
> diff --git a/src/Makefile.am b/src/Makefile.am
> index df912c442af1..1f18cb65699a 100644
> --- a/src/Makefile.am
> +++ b/src/Makefile.am
> @@ -93,6 +93,10 @@ if HAVE_INTEL_DRIVERS
>  SUBDIRS += intel
>  endif
>
> +if HAVE_GALLIUM_VC4
> +SUBDIRS += broadcom
> +endif
> +
>  if NEED_OPENGL_COMMON
>  SUBDIRS += mesa
>  endif
> diff --git a/src/broadcom/.gitignore b/src/broadcom/.gitignore
> new file mode 100644
> index ..fcc603f0cf01
> --- /dev/null
> +++ b/src/broadcom/.gitignore
> @@ -0,0 +1 @@
> +cle/*_pack.h
> diff --git a/src/mesa/Android.libmesa_git_sha1.mk 
> b/src/broadcom/Android.genxml.mk
> similarity index 60%
> copy from src/mesa/Android.libmesa_git_sha1.mk
> copy to src/broadcom/Android.genxml.mk

This is a strange diff.

> index 0fd176bf7d5d..461efd61085f 100644
> --- a/src/mesa/Android.libmesa_git_sha1.mk
> +++ b/src/broadcom/Android.genxml.mk
> @@ -1,6 +1,5 @@
> -# Mesa 3-D graphics library
> -#
> -# Copyright (C) 2017 Mauro Rossi 
> +# Copyright © 2016 Intel Corporation
> +# Copyright © 2016 Mauro Rossi 
>  #
>  # Permission is hereby granted, free of charge, to any person obtaining a
>  # copy of this software and associated documentation files (the "Software"),
> @@ -19,18 +18,18 @@
>  # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>  # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>  # DEALINGS IN THE SOFTWARE.
> +#
>
> -# --
> -# libmesa_git_sha1
> -# --
> -
> -LOCAL_PATH := $(call my-dir)
> +# ---
> +# Build libmesa_genxml
> +# ---
>
>  include $(CLEAR_VARS)
>
> -LOCAL_MODULE := libmesa_git_sha1
> +LOCAL_MODULE := libmesa_broadcom_genxml
>
>  LOCAL_MODULE_CLASS := STATIC_LIBRARIES
> +
>  intermediates := $(call local-generated-sources-dir)
>
>  # dummy.c source file is generated to meet the build system's rules.
> @@ -41,19 +40,23 @@ $(intermediates)/dummy.c:
> @echo "Gen Dummy: $(PRIVATE_MODULE) <= $(notdir $(@))"
> $(hide) touch 

[Mesa-dev] [PATCH 13/14] gallium/radeon: allow suballocating textures

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_buffer_common.c |  3 +++
 src/gallium/drivers/radeon/r600_texture.c   | 13 -
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c 
b/src/gallium/drivers/radeon/r600_buffer_common.c
index 262fe1d..766f083 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -175,20 +175,23 @@ void r600_init_resource_fields(struct r600_common_screen 
*rscreen,
 * placements even with a low amount of stolen VRAM.
 */
if (!rscreen->info.has_dedicated_vram &&
(rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
res->domains == RADEON_DOMAIN_VRAM)
res->domains = RADEON_DOMAIN_VRAM_GTT;
 
if (rscreen->debug_flags & DBG_NO_WC)
res->flags &= ~RADEON_FLAG_GTT_WC;
 
+   if (res->b.b.bind & PIPE_BIND_SHARED)
+   res->flags |= RADEON_FLAG_NO_SUBALLOC;
+
/* Set expected VRAM and GART usage for the buffer. */
res->vram_usage = 0;
res->gart_usage = 0;
 
if (res->domains & RADEON_DOMAIN_VRAM)
res->vram_usage = size;
else if (res->domains & RADEON_DOMAIN_GTT)
res->gart_usage = size;
 }
 
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 40cb8c0..2deb56a 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -558,20 +558,29 @@ static boolean r600_texture_get_handle(struct 
pipe_screen* screen,
ctx = threaded_context_unwrap_sync(ctx);
rctx = (struct r600_common_context*)(ctx ? ctx : rscreen->aux_context);
 
if (resource->target != PIPE_BUFFER) {
/* This is not supported now, but it might be required for 
OpenCL
 * interop in the future.
 */
if (resource->nr_samples > 1 || rtex->is_depth)
return false;
 
+   /* Move a suballocated texture into a non-suballocated 
allocation. */
+   if (rscreen->ws->buffer_is_suballocated(res->buf)) {
+   assert(!res->b.is_shared);
+   r600_reallocate_texture_inplace(rctx, rtex,
+   PIPE_BIND_SHARED, 
false);
+   assert(res->b.b.bind & PIPE_BIND_SHARED);
+   assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
+   }
+
/* Since shader image stores don't support DCC on VI,
 * disable it for external clients that want write
 * access.
 */
if (usage & PIPE_HANDLE_USAGE_WRITE && rtex->dcc_offset) {
if (r600_texture_disable_dcc(rctx, rtex))
update_metadata = true;
}
 
if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
@@ -1219,21 +1228,23 @@ r600_texture_create_object(struct pipe_screen *screen,
rtex->dcc_offset = align64(rtex->size, 
rtex->surface.dcc_alignment);
rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
}
}
 
/* Now create the backing buffer. */
if (!buf) {
r600_init_resource_fields(rscreen, resource, rtex->size,
  rtex->surface.surf_alignment);
 
-   resource->flags |= RADEON_FLAG_NO_SUBALLOC;
+   /* Displayable surfaces are not suballocated. */
+   if (resource->b.b.bind & PIPE_BIND_SCANOUT)
+   resource->flags |= RADEON_FLAG_NO_SUBALLOC;
 
if (!r600_alloc_resource(rscreen, resource)) {
FREE(rtex);
return NULL;
}
} else {
resource->buf = buf;
resource->gpu_address = 
rscreen->ws->buffer_get_virtual_address(resource->buf);
resource->bo_size = buf->size;
resource->bo_alignment = buf->alignment;
-- 
2.7.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 11/14] gallium/radeon: add radeon_winsys::buffer_is_suballocated

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/radeon_winsys.h| 3 +++
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 8 
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 6 ++
 3 files changed, 17 insertions(+)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 239b6ab..b37af91 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -353,20 +353,23 @@ struct radeon_winsys {
  void *pointer, uint64_t size);
 
 /**
  * Whether the buffer was created from a user pointer.
  *
  * \param buf   A winsys buffer object
  * \return  whether \p buf was created via buffer_from_ptr
  */
 bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 
+/** Whether the buffer was suballocated. */
+bool (*buffer_is_suballocated)(struct pb_buffer *buf);
+
 /**
  * Get a winsys handle from a winsys buffer. The internal structure
  * of the handle is platform-specific and only a winsys should access it.
  *
  * \param buf   A winsys buffer object to get the handle from.
  * \param whandle   A winsys handle pointer.
  * \param strideA stride of the buffer in bytes, for texturing.
  * \return  true on success.
  */
 bool (*buffer_get_handle)(struct pb_buffer *buf,
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index d512f7b..5943576 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -1404,31 +1404,39 @@ error_va_alloc:
 error:
 FREE(bo);
 return NULL;
 }
 
 static bool amdgpu_bo_is_user_ptr(struct pb_buffer *buf)
 {
return ((struct amdgpu_winsys_bo*)buf)->user_ptr != NULL;
 }
 
+static bool amdgpu_bo_is_suballocated(struct pb_buffer *buf)
+{
+   struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
+
+   return !bo->bo && !bo->sparse;
+}
+
 static uint64_t amdgpu_bo_get_va(struct pb_buffer *buf)
 {
return ((struct amdgpu_winsys_bo*)buf)->va;
 }
 
 void amdgpu_bo_init_functions(struct amdgpu_winsys *ws)
 {
ws->base.buffer_set_metadata = amdgpu_buffer_set_metadata;
ws->base.buffer_get_metadata = amdgpu_buffer_get_metadata;
ws->base.buffer_map = amdgpu_bo_map;
ws->base.buffer_unmap = amdgpu_bo_unmap;
ws->base.buffer_wait = amdgpu_bo_wait;
ws->base.buffer_create = amdgpu_bo_create;
ws->base.buffer_from_handle = amdgpu_bo_from_handle;
ws->base.buffer_from_ptr = amdgpu_bo_from_ptr;
ws->base.buffer_is_user_ptr = amdgpu_bo_is_user_ptr;
+   ws->base.buffer_is_suballocated = amdgpu_bo_is_suballocated;
ws->base.buffer_get_handle = amdgpu_bo_get_handle;
ws->base.buffer_commit = amdgpu_bo_sparse_commit;
ws->base.buffer_get_virtual_address = amdgpu_bo_get_va;
ws->base.buffer_get_initial_domain = amdgpu_bo_get_initial_domain;
 }
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index bbdb60d..b82b984 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -1282,20 +1282,25 @@ static bool radeon_winsys_bo_get_handle(struct 
pb_buffer *buffer,
 whandle->offset += slice_size * whandle->layer;
 
 return true;
 }
 
 static bool radeon_winsys_bo_is_user_ptr(struct pb_buffer *buf)
 {
return ((struct radeon_bo*)buf)->user_ptr != NULL;
 }
 
+static bool radeon_winsys_bo_is_suballocated(struct pb_buffer *buf)
+{
+   return !((struct radeon_bo*)buf)->handle;
+}
+
 static uint64_t radeon_winsys_bo_va(struct pb_buffer *buf)
 {
 return ((struct radeon_bo*)buf)->va;
 }
 
 static unsigned radeon_winsys_bo_get_reloc_offset(struct pb_buffer *buf)
 {
 struct radeon_bo *bo = radeon_bo(buf);
 
 if (bo->handle)
@@ -1308,15 +1313,16 @@ void radeon_drm_bo_init_functions(struct 
radeon_drm_winsys *ws)
 {
 ws->base.buffer_set_metadata = radeon_bo_set_metadata;
 ws->base.buffer_get_metadata = radeon_bo_get_metadata;
 ws->base.buffer_map = radeon_bo_map;
 ws->base.buffer_unmap = radeon_bo_unmap;
 ws->base.buffer_wait = radeon_bo_wait;
 ws->base.buffer_create = radeon_winsys_bo_create;
 ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
 ws->base.buffer_from_ptr = radeon_winsys_bo_from_ptr;
 ws->base.buffer_is_user_ptr = radeon_winsys_bo_is_user_ptr;
+ws->base.buffer_is_suballocated = radeon_winsys_bo_is_suballocated;
 ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;
 ws->base.buffer_get_virtual_address = radeon_winsys_bo_va;
 ws->base.buffer_get_reloc_offset = radeon_winsys_bo_get_reloc_offset;
 ws->base.buffer_get_initial_domain = radeon_bo_get_initial_domain;
 }
-- 
2.7.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org

[Mesa-dev] [PATCH 10/14] gallium/radeon: clean up pb_cache bucket/usage determination

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/radeon_winsys.h| 20 
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 21 +
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 21 +
 3 files changed, 30 insertions(+), 32 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 4ecd73f..239b6ab 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -658,20 +658,21 @@ static inline void radeon_emit_array(struct 
radeon_winsys_cs *cs,
 cs->current.cdw += count;
 }
 
 enum radeon_heap {
 RADEON_HEAP_VRAM_NO_CPU_ACCESS,
 RADEON_HEAP_VRAM,
 RADEON_HEAP_VRAM_GTT, /* combined heaps */
 RADEON_HEAP_GTT_WC,
 RADEON_HEAP_GTT,
 RADEON_MAX_SLAB_HEAPS,
+RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
 };
 
 static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap 
heap)
 {
 switch (heap) {
 case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 case RADEON_HEAP_VRAM:
 return RADEON_DOMAIN_VRAM;
 case RADEON_HEAP_VRAM_GTT:
 return RADEON_DOMAIN_VRAM_GTT;
@@ -692,20 +693,39 @@ static inline unsigned radeon_flags_from_heap(enum 
radeon_heap heap)
 case RADEON_HEAP_VRAM:
 case RADEON_HEAP_VRAM_GTT:
 case RADEON_HEAP_GTT_WC:
 return RADEON_FLAG_GTT_WC;
 case RADEON_HEAP_GTT:
 default:
 return 0;
 }
 }
 
+/* The pb cache bucket is chosen to minimize pb_cache misses.
+ * It must be between 0 and 3 inclusive.
+ */
+static inline unsigned radeon_get_pb_cache_bucket_index(enum radeon_heap heap)
+{
+switch (heap) {
+case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
+return 0;
+case RADEON_HEAP_VRAM:
+case RADEON_HEAP_VRAM_GTT:
+return 1;
+case RADEON_HEAP_GTT_WC:
+return 2;
+case RADEON_HEAP_GTT:
+default:
+return 3;
+}
+}
+
 /* Return the heap index for winsys allocators, or -1 on failure. */
 static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
 enum radeon_bo_flag flags)
 {
 /* VRAM implies WC (write combining) */
 assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
 /* NO_CPU_ACCESS implies VRAM only. */
 assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == 
RADEON_DOMAIN_VRAM);
 
 /* Unsupported flags: NO_SUBALLOC, SPARSE. */
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 38aaa89..d512f7b 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -1182,36 +1182,25 @@ no_slab:
/* This flag is irrelevant for the cache. */
flags &= ~RADEON_FLAG_NO_SUBALLOC;
 
/* Align size to page size. This is the minimum alignment for normal
 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
 * like constant/uniform buffers, can benefit from better and more reuse.
 */
size = align64(size, ws->info.gart_page_size);
alignment = align(alignment, ws->info.gart_page_size);
 
-   /* Only set one usage bit each for domains and flags, or the cache manager
-* might consider different sets of domains / flags compatible
-*/
-   if (domain == RADEON_DOMAIN_VRAM_GTT)
-  usage = 1 << 2;
-   else
-  usage = domain >> 1;
-   assert(flags < sizeof(usage) * 8 - 3);
-   usage |= 1 << (flags + 3);
-
-   /* Determine the pb_cache bucket for minimizing pb_cache misses. */
-   pb_cache_bucket = 0;
-   if (domain & RADEON_DOMAIN_VRAM) /* VRAM or VRAM+GTT */
-  pb_cache_bucket += 1;
-   if (flags == RADEON_FLAG_GTT_WC) /* WC */
-  pb_cache_bucket += 2;
+   int heap = radeon_get_heap_index(domain, flags);
+   assert(heap >= 0 && heap < RADEON_MAX_CACHED_HEAPS);
+   usage = 1 << heap; /* Only set one usage bit for each heap. */
+
+   pb_cache_bucket = radeon_get_pb_cache_bucket_index(heap);
assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets));
 
/* Get a buffer from the cache. */
bo = (struct amdgpu_winsys_bo*)
 pb_cache_reclaim_buffer(>bo_cache, size, alignment, usage,
 pb_cache_bucket);
if (bo)
   return >base;
 
/* Create a new one. */
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index cef88a6..bbdb60d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -962,36 +962,25 @@ no_slab:
 /* This flag is irrelevant for the cache. */
 flags &= ~RADEON_FLAG_NO_SUBALLOC;
 
 /* Align size to page size. This is the minimum alignment for normal
  * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
  * like constant/uniform buffers, can benefit from better and more reuse.
  */
 size = align(size, 

[Mesa-dev] [PATCH 14/14] winsys/amdgpu: use 128KB BOs for suballocations of up to 64KB BOs

[Marek Olšák]

From: Marek Olšák 

This decreases the number of BOs, but might also increase memory usage.
It's better for small textures.

The gameplay is on the far right:
https://people.freedesktop.org/~mareko/suballoc.svg
---
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 3 ++-
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h | 5 +++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 5943576..9690afd 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -495,22 +495,23 @@ struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned 
heap,
 {
struct amdgpu_winsys *ws = priv;
struct amdgpu_slab *slab = CALLOC_STRUCT(amdgpu_slab);
enum radeon_bo_domain domains = radeon_domain_from_heap(heap);
enum radeon_bo_flag flags = radeon_flags_from_heap(heap);
uint32_t base_id;
 
if (!slab)
   return NULL;
 
+   unsigned slab_size = 1 << AMDGPU_SLAB_BO_SIZE_LOG2;
slab->buffer = amdgpu_winsys_bo(amdgpu_bo_create(>base,
-64 * 1024, 64 * 1024,
+slab_size, slab_size,
 domains, flags));
if (!slab->buffer)
   goto fail;
 
assert(slab->buffer->bo);
 
slab->base.num_entries = slab->buffer->base.size / entry_size;
slab->base.num_free = slab->base.num_entries;
slab->entries = CALLOC(slab->base.num_entries, sizeof(*slab->entries));
if (!slab->entries)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
index f011b8e..7cd2f20 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
@@ -34,22 +34,23 @@
 
 #include "pipebuffer/pb_cache.h"
 #include "pipebuffer/pb_slab.h"
 #include "gallium/drivers/radeon/radeon_winsys.h"
 #include "addrlib/addrinterface.h"
 #include "util/u_queue.h"
 #include 
 
 struct amdgpu_cs;
 
-#define AMDGPU_SLAB_MIN_SIZE_LOG2 9
-#define AMDGPU_SLAB_MAX_SIZE_LOG2 14
+#define AMDGPU_SLAB_MIN_SIZE_LOG2   9  /* 512 bytes */
+#define AMDGPU_SLAB_MAX_SIZE_LOG2   16 /* 64 KB */
+#define AMDGPU_SLAB_BO_SIZE_LOG217 /* 128 KB */
 
 struct amdgpu_winsys {
struct radeon_winsys base;
struct pipe_reference reference;
struct pb_cache bo_cache;
struct pb_slabs bo_slabs;
 
amdgpu_device_handle dev;
 
mtx_t bo_fence_lock;
-- 
2.7.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 12/14] gallium/radeon: generalize the function for in-place texture reallocation

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_texture.c | 64 +--
 1 file changed, 43 insertions(+), 21 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index e21dc37..40cb8c0 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -441,86 +441,107 @@ bool r600_texture_disable_dcc(struct r600_common_context 
*rctx,
/* Decompress DCC. */
rctx->decompress_dcc(>b, rtex);
rctx->b.flush(>b, NULL, 0);
 
if (>b == rscreen->aux_context)
mtx_unlock(>aux_context_lock);
 
return r600_texture_discard_dcc(rscreen, rtex);
 }
 
-static void r600_degrade_tile_mode_to_linear(struct r600_common_context *rctx,
-struct r600_texture *rtex,
-bool invalidate_storage)
+static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
+   struct r600_texture *rtex,
+   unsigned new_bind_flag,
+   bool invalidate_storage)
 {
struct pipe_screen *screen = rctx->b.screen;
struct r600_texture *new_tex;
struct pipe_resource templ = rtex->resource.b.b;
unsigned i;
 
-   templ.bind |= PIPE_BIND_LINEAR;
+   templ.bind |= new_bind_flag;
 
/* r600g doesn't react to dirty_tex_descriptor_counter */
if (rctx->chip_class < SI)
return;
 
-   if (rtex->resource.b.is_shared ||
-   rtex->surface.is_linear)
+   if (rtex->resource.b.is_shared)
return;
 
-   /* This fails with MSAA, depth, and compressed textures. */
-   if (r600_choose_tiling(rctx->screen, ) !=
-   RADEON_SURF_MODE_LINEAR_ALIGNED)
-   return;
+   if (new_bind_flag == PIPE_BIND_LINEAR) {
+   if (rtex->surface.is_linear)
+   return;
+
+   /* This fails with MSAA, depth, and compressed textures. */
+   if (r600_choose_tiling(rctx->screen, ) !=
+   RADEON_SURF_MODE_LINEAR_ALIGNED)
+   return;
+   }
 
new_tex = (struct r600_texture*)screen->resource_create(screen, );
if (!new_tex)
return;
 
/* Copy the pixels to the new texture. */
if (!invalidate_storage) {
for (i = 0; i <= templ.last_level; i++) {
struct pipe_box box;
 
u_box_3d(0, 0, 0,
 u_minify(templ.width0, i), 
u_minify(templ.height0, i),
 util_max_layer(, i) + 1, );
 
rctx->dma_copy(>b, _tex->resource.b.b, i, 0, 
0, 0,
   >resource.b.b, i, );
}
}
 
-   r600_texture_discard_cmask(rctx->screen, rtex);
-   r600_texture_discard_dcc(rctx->screen, rtex);
+   if (new_bind_flag == PIPE_BIND_LINEAR) {
+   r600_texture_discard_cmask(rctx->screen, rtex);
+   r600_texture_discard_dcc(rctx->screen, rtex);
+   }
 
/* Replace the structure fields of rtex. */
rtex->resource.b.b.bind = templ.bind;
pb_reference(>resource.buf, new_tex->resource.buf);
rtex->resource.gpu_address = new_tex->resource.gpu_address;
rtex->resource.vram_usage = new_tex->resource.vram_usage;
rtex->resource.gart_usage = new_tex->resource.gart_usage;
rtex->resource.bo_size = new_tex->resource.bo_size;
rtex->resource.bo_alignment = new_tex->resource.bo_alignment;
rtex->resource.domains = new_tex->resource.domains;
rtex->resource.flags = new_tex->resource.flags;
rtex->size = new_tex->size;
+   rtex->db_render_format = new_tex->db_render_format;
+   rtex->db_compatible = new_tex->db_compatible;
+   rtex->can_sample_z = new_tex->can_sample_z;
+   rtex->can_sample_s = new_tex->can_sample_s;
rtex->surface = new_tex->surface;
-   rtex->non_disp_tiling = new_tex->non_disp_tiling;
+   rtex->fmask = new_tex->fmask;
+   rtex->cmask = new_tex->cmask;
rtex->cb_color_info = new_tex->cb_color_info;
-   rtex->cmask = new_tex->cmask; /* needed even without CMASK */
+   rtex->last_msaa_resolve_target_micro_mode = 
new_tex->last_msaa_resolve_target_micro_mode;
+   rtex->htile_offset = new_tex->htile_offset;
+   rtex->tc_compatible_htile = new_tex->tc_compatible_htile;
+   rtex->depth_cleared = new_tex->depth_cleared;
+   rtex->stencil_cleared = new_tex->stencil_cleared;
+   rtex->non_disp_tiling = new_tex->non_disp_tiling;
+   rtex->dcc_gather_statistics = new_tex->dcc_gather_statistics;
+   rtex->framebuffers_bound = new_tex->framebuffers_bound;
 
-   

[Mesa-dev] [PATCH 06/14] gallium/radeon: disallow exports of sparse and suballocated BOs

[Marek Olšák]

From: Marek Olšák 

I think it's unsafe, because the slabs can reuse exported storage.
---
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 7 +++
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 7 +++
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index a86cc2c..5119d3f 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -1358,24 +1358,23 @@ error:
 
 static bool amdgpu_bo_get_handle(struct pb_buffer *buffer,
  unsigned stride, unsigned offset,
  unsigned slice_size,
  struct winsys_handle *whandle)
 {
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(buffer);
enum amdgpu_bo_handle_type type;
int r;
 
-   if (!bo->bo) {
-  offset += bo->va - bo->u.slab.real->va;
-  bo = bo->u.slab.real;
-   }
+   /* Don't allow exports of slab entries and sparse buffers. */
+   if (!bo->bo)
+  return false;
 
bo->u.real.use_reusable_pool = false;
 
switch (whandle->type) {
case DRM_API_HANDLE_TYPE_SHARED:
   type = amdgpu_bo_handle_type_gem_flink_name;
   break;
case DRM_API_HANDLE_TYPE_FD:
   type = amdgpu_bo_handle_type_dma_buf_fd;
   break;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 18d397d..274d576 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -1282,24 +1282,23 @@ fail:
 
 static bool radeon_winsys_bo_get_handle(struct pb_buffer *buffer,
 unsigned stride, unsigned offset,
 unsigned slice_size,
 struct winsys_handle *whandle)
 {
 struct drm_gem_flink flink;
 struct radeon_bo *bo = radeon_bo(buffer);
 struct radeon_drm_winsys *ws = bo->rws;
 
-if (!bo->handle) {
-offset += bo->va - bo->u.slab.real->va;
-bo = bo->u.slab.real;
-}
+/* Don't allow exports of slab entries. */
+if (!bo->handle)
+return false;
 
 memset(, 0, sizeof(flink));
 
 bo->u.real.use_reusable_pool = false;
 
 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 if (!bo->flink_name) {
 flink.handle = bo->handle;
 
 if (ioctl(ws->fd, DRM_IOCTL_GEM_FLINK, )) {
-- 
2.7.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 09/14] gallium/radeon: enable suballocations for VRAM with no CPU access

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/radeon_winsys.h| 15 ---
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c |  3 +++
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c |  3 +++
 3 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 95543bb..4ecd73f 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -652,70 +652,79 @@ static inline void radeon_emit(struct radeon_winsys_cs 
*cs, uint32_t value)
 }
 
 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 const uint32_t *values, unsigned count)
 {
 memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 cs->current.cdw += count;
 }
 
 enum radeon_heap {
+RADEON_HEAP_VRAM_NO_CPU_ACCESS,
 RADEON_HEAP_VRAM,
 RADEON_HEAP_VRAM_GTT, /* combined heaps */
 RADEON_HEAP_GTT_WC,
 RADEON_HEAP_GTT,
 RADEON_MAX_SLAB_HEAPS,
 };
 
 static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap 
heap)
 {
 switch (heap) {
+case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 case RADEON_HEAP_VRAM:
 return RADEON_DOMAIN_VRAM;
 case RADEON_HEAP_VRAM_GTT:
 return RADEON_DOMAIN_VRAM_GTT;
 case RADEON_HEAP_GTT_WC:
 case RADEON_HEAP_GTT:
 return RADEON_DOMAIN_GTT;
 default:
 assert(0);
 return 0;
 }
 }
 
 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
 {
 switch (heap) {
+case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
+return RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS;
 case RADEON_HEAP_VRAM:
 case RADEON_HEAP_VRAM_GTT:
 case RADEON_HEAP_GTT_WC:
 return RADEON_FLAG_GTT_WC;
 case RADEON_HEAP_GTT:
 default:
 return 0;
 }
 }
 
 /* Return the heap index for winsys allocators, or -1 on failure. */
 static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
 enum radeon_bo_flag flags)
 {
 /* VRAM implies WC (write combining) */
 assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
+/* NO_CPU_ACCESS implies VRAM only. */
+assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == 
RADEON_DOMAIN_VRAM);
 
-/* Unsupported flags: NO_CPU_ACCESS, NO_SUBALLOC, SPARSE. */
-if (flags & ~RADEON_FLAG_GTT_WC)
+/* Unsupported flags: NO_SUBALLOC, SPARSE. */
+if (flags & ~(RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS))
 return -1;
 
 switch (domain) {
 case RADEON_DOMAIN_VRAM:
-return RADEON_HEAP_VRAM;
+if (flags & RADEON_FLAG_NO_CPU_ACCESS)
+return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
+else
+return RADEON_HEAP_VRAM;
 case RADEON_DOMAIN_VRAM_GTT:
 return RADEON_HEAP_VRAM_GTT;
 case RADEON_DOMAIN_GTT:
 if (flags & RADEON_FLAG_GTT_WC)
 return RADEON_HEAP_GTT_WC;
 else
 return RADEON_HEAP_GTT;
 }
 return -1;
 }
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 5ebe59f..38aaa89 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -1131,20 +1131,23 @@ amdgpu_bo_create(struct radeon_winsys *rws,
  enum radeon_bo_domain domain,
  enum radeon_bo_flag flags)
 {
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys_bo *bo;
unsigned usage = 0, pb_cache_bucket;
 
/* VRAM implies WC. This is not optional. */
if (domain & RADEON_DOMAIN_VRAM)
   flags |= RADEON_FLAG_GTT_WC;
+   /* NO_CPU_ACCESS is valid with VRAM only. */
+   if (domain != RADEON_DOMAIN_VRAM)
+  flags &= ~RADEON_FLAG_NO_CPU_ACCESS;
 
/* Sub-allocate small buffers from slabs. */
if (!(flags & (RADEON_FLAG_NO_SUBALLOC | RADEON_FLAG_SPARSE)) &&
size <= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2) &&
alignment <= MAX2(1 << AMDGPU_SLAB_MIN_SIZE_LOG2, 
util_next_power_of_two(size))) {
   struct pb_slab_entry *entry;
   int heap = radeon_get_heap_index(domain, flags);
 
   if (heap < 0 || heap >= RADEON_MAX_SLAB_HEAPS)
  goto no_slab;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index a9421d6..cef88a6 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -918,20 +918,23 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
 
 assert(!(flags & RADEON_FLAG_SPARSE)); /* not supported */
 
 /* Only 32-bit sizes are supported. */
 if (size > UINT_MAX)
 return NULL;
 
 /* VRAM implies WC. This is not optional. */
 if (domain & RADEON_DOMAIN_VRAM)
 flags |= RADEON_FLAG_GTT_WC;
+/* NO_CPU_ACCESS is valid with VRAM only. */
+if (domain != 

[Mesa-dev] [PATCH 07/14] gallium/radeon: remove RADEON_FLAG_CPU_ACCESS

[Marek Olšák]

From: Marek Olšák 

https://lists.freedesktop.org/archives/amd-gfx/2017-June/010591.html
---
 src/gallium/drivers/radeon/r600_buffer_common.c | 4 
 src/gallium/drivers/radeon/radeon_winsys.h  | 7 +++
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c   | 9 +
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c   | 3 +--
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c   | 8 +---
 5 files changed, 6 insertions(+), 25 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c 
b/src/gallium/drivers/radeon/r600_buffer_common.c
index 342695c..262fe1d 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -125,21 +125,20 @@ void r600_init_resource_fields(struct r600_common_screen 
*rscreen,
case PIPE_USAGE_DYNAMIC:
/* Older kernels didn't always flush the HDP cache before
 * CS execution
 */
if (rscreen->info.drm_major == 2 &&
rscreen->info.drm_minor < 40) {
res->domains = RADEON_DOMAIN_GTT;
res->flags |= RADEON_FLAG_GTT_WC;
break;
}
-   res->flags |= RADEON_FLAG_CPU_ACCESS;
/* fall through */
case PIPE_USAGE_DEFAULT:
case PIPE_USAGE_IMMUTABLE:
default:
/* Not listing GTT here improves performance in some
 * apps. */
res->domains = RADEON_DOMAIN_VRAM;
res->flags |= RADEON_FLAG_GTT_WC;
break;
}
@@ -151,29 +150,26 @@ void r600_init_resource_fields(struct r600_common_screen 
*rscreen,
 * kernels, because they didn't always flush the HDP
 * cache before CS execution.
 *
 * Write-combined CPU mappings are fine, the kernel
 * ensures all CPU writes finish before the GPU
 * executes a command stream.
 */
if (rscreen->info.drm_major == 2 &&
rscreen->info.drm_minor < 40)
res->domains = RADEON_DOMAIN_GTT;
-   else if (res->domains & RADEON_DOMAIN_VRAM)
-   res->flags |= RADEON_FLAG_CPU_ACCESS;
}
 
/* Tiled textures are unmappable. Always put them in VRAM. */
if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
res->domains = RADEON_DOMAIN_VRAM;
-   res->flags &= ~RADEON_FLAG_CPU_ACCESS;
res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 RADEON_FLAG_GTT_WC;
}
 
/* If VRAM is just stolen system memory, allow both VRAM and
 * GTT, whichever has free space. If a buffer is evicted from
 * VRAM to GTT, it will stay there.
 *
 * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
 * placements even with a low amount of stolen VRAM.
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 706188f..1be94f7 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -44,24 +44,23 @@ enum radeon_bo_layout {
 };
 
 enum radeon_bo_domain { /* bitfield */
 RADEON_DOMAIN_GTT  = 2,
 RADEON_DOMAIN_VRAM = 4,
 RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
 };
 
 enum radeon_bo_flag { /* bitfield */
 RADEON_FLAG_GTT_WC =(1 << 0),
-RADEON_FLAG_CPU_ACCESS =(1 << 1),
-RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
-RADEON_FLAG_NO_SUBALLOC =   (1 << 3),
-RADEON_FLAG_SPARSE =(1 << 4),
+RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
+RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
+RADEON_FLAG_SPARSE =(1 << 3),
 };
 
 enum radeon_bo_usage { /* bitfield */
 RADEON_USAGE_READ = 2,
 RADEON_USAGE_WRITE = 4,
 RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
 
 /* The winsys ensures that the CS submission will be scheduled after
  * previously flushed CSs referencing this BO in a conflicting way.
  */
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 5119d3f..9736f44a 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -391,22 +391,20 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct 
amdgpu_winsys *ws,
pb_cache_init_entry(>bo_cache, >u.real.cache_entry, >base,
pb_cache_bucket);
request.alloc_size = size;
request.phys_alignment = alignment;
 
if (initial_domain & RADEON_DOMAIN_VRAM)
   request.preferred_heap |= AMDGPU_GEM_DOMAIN_VRAM;
if (initial_domain & RADEON_DOMAIN_GTT)
   request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;
 
-   if (flags 

[Mesa-dev] [PATCH 08/14] gallium/radeon: clean up (domain, flags) <-> (slab heap) translations

[Marek Olšák]

From: Marek Olšák 

This is cleaner, and we are down to 4 slabs.
---
 src/gallium/drivers/radeon/radeon_winsys.h| 62 +++
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 44 +++-
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |  2 +-
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 44 +++-
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |  2 +-
 5 files changed, 80 insertions(+), 74 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 1be94f7..95543bb 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -651,11 +651,73 @@ static inline void radeon_emit(struct radeon_winsys_cs 
*cs, uint32_t value)
 cs->current.buf[cs->current.cdw++] = value;
 }
 
 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 const uint32_t *values, unsigned count)
 {
 memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 cs->current.cdw += count;
 }
 
+enum radeon_heap {
+RADEON_HEAP_VRAM,
+RADEON_HEAP_VRAM_GTT, /* combined heaps */
+RADEON_HEAP_GTT_WC,
+RADEON_HEAP_GTT,
+RADEON_MAX_SLAB_HEAPS,
+};
+
+static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap 
heap)
+{
+switch (heap) {
+case RADEON_HEAP_VRAM:
+return RADEON_DOMAIN_VRAM;
+case RADEON_HEAP_VRAM_GTT:
+return RADEON_DOMAIN_VRAM_GTT;
+case RADEON_HEAP_GTT_WC:
+case RADEON_HEAP_GTT:
+return RADEON_DOMAIN_GTT;
+default:
+assert(0);
+return 0;
+}
+}
+
+static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
+{
+switch (heap) {
+case RADEON_HEAP_VRAM:
+case RADEON_HEAP_VRAM_GTT:
+case RADEON_HEAP_GTT_WC:
+return RADEON_FLAG_GTT_WC;
+case RADEON_HEAP_GTT:
+default:
+return 0;
+}
+}
+
+/* Return the heap index for winsys allocators, or -1 on failure. */
+static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
+enum radeon_bo_flag flags)
+{
+/* VRAM implies WC (write combining) */
+assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
+
+/* Unsupported flags: NO_CPU_ACCESS, NO_SUBALLOC, SPARSE. */
+if (flags & ~RADEON_FLAG_GTT_WC)
+return -1;
+
+switch (domain) {
+case RADEON_DOMAIN_VRAM:
+return RADEON_HEAP_VRAM;
+case RADEON_DOMAIN_VRAM_GTT:
+return RADEON_HEAP_VRAM_GTT;
+case RADEON_DOMAIN_GTT:
+if (flags & RADEON_FLAG_GTT_WC)
+return RADEON_HEAP_GTT_WC;
+else
+return RADEON_HEAP_GTT;
+}
+return -1;
+}
+
 #endif
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 9736f44a..5ebe59f 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -488,43 +488,27 @@ static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl = {
amdgpu_bo_slab_destroy
/* other functions are never called */
 };
 
 struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap,
  unsigned entry_size,
  unsigned group_index)
 {
struct amdgpu_winsys *ws = priv;
struct amdgpu_slab *slab = CALLOC_STRUCT(amdgpu_slab);
-   enum radeon_bo_domain domains;
-   enum radeon_bo_flag flags = 0;
+   enum radeon_bo_domain domains = radeon_domain_from_heap(heap);
+   enum radeon_bo_flag flags = radeon_flags_from_heap(heap);
uint32_t base_id;
 
if (!slab)
   return NULL;
 
-   if (heap & 1)
-  flags |= RADEON_FLAG_GTT_WC;
-
-   switch (heap >> 2) {
-   case 0:
-  domains = RADEON_DOMAIN_VRAM;
-  break;
-   default:
-   case 1:
-  domains = RADEON_DOMAIN_VRAM_GTT;
-  break;
-   case 2:
-  domains = RADEON_DOMAIN_GTT;
-  break;
-   }
-
slab->buffer = amdgpu_winsys_bo(amdgpu_bo_create(>base,
 64 * 1024, 64 * 1024,
 domains, flags));
if (!slab->buffer)
   goto fail;
 
assert(slab->buffer->bo);
 
slab->base.num_entries = slab->buffer->base.size / entry_size;
slab->base.num_free = slab->base.num_entries;
@@ -1144,45 +1128,33 @@ static struct pb_buffer *
 amdgpu_bo_create(struct radeon_winsys *rws,
  uint64_t size,
  unsigned alignment,
  enum radeon_bo_domain domain,
  enum radeon_bo_flag flags)
 {
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys_bo *bo;
unsigned usage = 0, pb_cache_bucket;
 
+   /* VRAM implies WC. This is not optional. */
+   if (domain & RADEON_DOMAIN_VRAM)
+  flags |= RADEON_FLAG_GTT_WC;
+
/* Sub-allocate small buffers from slabs. */
if (!(flags 

[Mesa-dev] [PATCH 05/14] gallium/radeon: clean up r600_texture_get_handle

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_texture.c | 47 +++
 1 file changed, 23 insertions(+), 24 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index c811d6a..e21dc37 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -530,28 +530,27 @@ static boolean r600_texture_get_handle(struct 
pipe_screen* screen,
struct r600_common_context *rctx;
struct r600_resource *res = (struct r600_resource*)resource;
struct r600_texture *rtex = (struct r600_texture*)resource;
struct radeon_bo_metadata metadata;
bool update_metadata = false;
unsigned stride, offset, slice_size;
 
ctx = threaded_context_unwrap_sync(ctx);
rctx = (struct r600_common_context*)(ctx ? ctx : rscreen->aux_context);
 
-   /* This is not supported now, but it might be required for OpenCL
-* interop in the future.
-*/
-   if (resource->target != PIPE_BUFFER &&
-   (resource->nr_samples > 1 || rtex->is_depth))
-   return false;
-
if (resource->target != PIPE_BUFFER) {
+   /* This is not supported now, but it might be required for 
OpenCL
+* interop in the future.
+*/
+   if (resource->nr_samples > 1 || rtex->is_depth)
+   return false;
+
/* Since shader image stores don't support DCC on VI,
 * disable it for external clients that want write
 * access.
 */
if (usage & PIPE_HANDLE_USAGE_WRITE && rtex->dcc_offset) {
if (r600_texture_disable_dcc(rctx, rtex))
update_metadata = true;
}
 
if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
@@ -568,51 +567,51 @@ static boolean r600_texture_get_handle(struct 
pipe_screen* screen,
 
/* Set metadata. */
if (!res->b.is_shared || update_metadata) {
r600_texture_init_metadata(rscreen, rtex, );
if (rscreen->query_opaque_metadata)
rscreen->query_opaque_metadata(rscreen, rtex,
   );
 
rscreen->ws->buffer_set_metadata(res->buf, );
}
+
+   if (rscreen->chip_class >= GFX9) {
+   offset = rtex->surface.u.gfx9.surf_offset;
+   stride = rtex->surface.u.gfx9.surf_pitch *
+rtex->surface.bpe;
+   slice_size = rtex->surface.u.gfx9.surf_slice_size;
+   } else {
+   offset = rtex->surface.u.legacy.level[0].offset;
+   stride = rtex->surface.u.legacy.level[0].nblk_x *
+rtex->surface.bpe;
+   slice_size = rtex->surface.u.legacy.level[0].slice_size;
+   }
+   } else {
+   /* Buffers */
+   offset = 0;
+   stride = 0;
+   slice_size = 0;
}
 
if (res->b.is_shared) {
/* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
 * doesn't set it.
 */
res->external_usage |= usage & 
~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
res->external_usage &= 
~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
} else {
res->b.is_shared = true;
res->external_usage = usage;
}
 
-   if (res->b.b.target == PIPE_BUFFER) {
-   offset = 0;
-   stride = 0;
-   slice_size = 0;
-   } else {
-   if (rscreen->chip_class >= GFX9) {
-   offset = rtex->surface.u.gfx9.surf_offset;
-   stride = rtex->surface.u.gfx9.surf_pitch *
-rtex->surface.bpe;
-   slice_size = rtex->surface.u.gfx9.surf_slice_size;
-   } else {
-   offset = rtex->surface.u.legacy.level[0].offset;
-   stride = rtex->surface.u.legacy.level[0].nblk_x *
-rtex->surface.bpe;
-   slice_size = rtex->surface.u.legacy.level[0].slice_size;
-   }
-   }
return rscreen->ws->buffer_get_handle(res->buf, stride, offset,
  slice_size, whandle);
 }
 
 static void r600_texture_destroy(struct pipe_screen *screen,
 struct pipe_resource *ptex)
 {
struct r600_texture *rtex = (struct r600_texture*)ptex;
struct r600_resource *resource = >resource;
 
-- 
2.7.4

[Mesa-dev] [PATCH 03/14] gallium/radeon: fix a possible crash for buffer exports

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_texture.c | 24 +++-
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index d68587b..139ab13 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -582,30 +582,36 @@ static boolean r600_texture_get_handle(struct 
pipe_screen* screen,
 * doesn't set it.
 */
res->external_usage |= usage & 
~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
res->external_usage &= 
~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
} else {
res->b.is_shared = true;
res->external_usage = usage;
}
 
-   if (rscreen->chip_class >= GFX9) {
-   offset = rtex->surface.u.gfx9.surf_offset;
-   stride = rtex->surface.u.gfx9.surf_pitch *
-rtex->surface.bpe;
-   slice_size = rtex->surface.u.gfx9.surf_slice_size;
+   if (res->b.b.target == PIPE_BUFFER) {
+   offset = 0;
+   stride = 0;
+   slice_size = 0;
} else {
-   offset = rtex->surface.u.legacy.level[0].offset;
-   stride = rtex->surface.u.legacy.level[0].nblk_x *
-rtex->surface.bpe;
-   slice_size = rtex->surface.u.legacy.level[0].slice_size;
+   if (rscreen->chip_class >= GFX9) {
+   offset = rtex->surface.u.gfx9.surf_offset;
+   stride = rtex->surface.u.gfx9.surf_pitch *
+rtex->surface.bpe;
+   slice_size = rtex->surface.u.gfx9.surf_slice_size;
+   } else {
+   offset = rtex->surface.u.legacy.level[0].offset;
+   stride = rtex->surface.u.legacy.level[0].nblk_x *
+rtex->surface.bpe;
+   slice_size = rtex->surface.u.legacy.level[0].slice_size;
+   }
}
return rscreen->ws->buffer_get_handle(res->buf, stride, offset,
  slice_size, whandle);
 }
 
 static void r600_texture_destroy(struct pipe_screen *screen,
 struct pipe_resource *ptex)
 {
struct r600_texture *rtex = (struct r600_texture*)ptex;
struct r600_resource *resource = >resource;
-- 
2.7.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 01/14] radeonsi: add a HUD query for getting an average GFX BO list size

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_query.c   | 18 ++
 src/gallium/drivers/radeon/r600_query.h   |  1 +
 src/gallium/drivers/radeon/radeon_winsys.h|  1 +
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c |  3 +++
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |  2 ++
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h |  1 +
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |  1 +
 7 files changed, 27 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_query.c 
b/src/gallium/drivers/radeon/r600_query.c
index 3308ad8..db70878 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -64,20 +64,21 @@ static enum radeon_value_id winsys_id_from_type(unsigned 
type)
 {
switch (type) {
case R600_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
case R600_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
case R600_QUERY_MAPPED_VRAM: return RADEON_MAPPED_VRAM;
case R600_QUERY_MAPPED_GTT: return RADEON_MAPPED_GTT;
case R600_QUERY_BUFFER_WAIT_TIME: return RADEON_BUFFER_WAIT_TIME_NS;
case R600_QUERY_NUM_MAPPED_BUFFERS: return RADEON_NUM_MAPPED_BUFFERS;
case R600_QUERY_NUM_GFX_IBS: return RADEON_NUM_GFX_IBS;
case R600_QUERY_NUM_SDMA_IBS: return RADEON_NUM_SDMA_IBS;
+   case R600_QUERY_GFX_BO_LIST_SIZE: return RADEON_GFX_BO_LIST_COUNTER;
case R600_QUERY_NUM_BYTES_MOVED: return RADEON_NUM_BYTES_MOVED;
case R600_QUERY_NUM_EVICTIONS: return RADEON_NUM_EVICTIONS;
case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: return 
RADEON_NUM_VRAM_CPU_PAGE_FAULTS;
case R600_QUERY_VRAM_USAGE: return RADEON_VRAM_USAGE;
case R600_QUERY_VRAM_VIS_USAGE: return RADEON_VRAM_VIS_USAGE;
case R600_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
case R600_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
case R600_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
case R600_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
case R600_QUERY_CS_THREAD_BUSY: return RADEON_CS_THREAD_TIME;
@@ -166,20 +167,26 @@ static bool r600_query_sw_begin(struct 
r600_common_context *rctx,
case R600_QUERY_BUFFER_WAIT_TIME:
case R600_QUERY_NUM_GFX_IBS:
case R600_QUERY_NUM_SDMA_IBS:
case R600_QUERY_NUM_BYTES_MOVED:
case R600_QUERY_NUM_EVICTIONS:
case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
break;
}
+   case R600_QUERY_GFX_BO_LIST_SIZE:
+   ws_id = winsys_id_from_type(query->b.type);
+   query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
+   query->begin_time = rctx->ws->query_value(rctx->ws,
+ RADEON_NUM_GFX_IBS);
+   break;
case R600_QUERY_CS_THREAD_BUSY:
ws_id = winsys_id_from_type(query->b.type);
query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
query->begin_time = os_time_get_nano();
break;
case R600_QUERY_GALLIUM_THREAD_BUSY:
query->begin_result =
rctx->tc ? 
util_queue_get_thread_time_nano(>tc->queue, 0) : 0;
query->begin_time = os_time_get_nano();
break;
@@ -311,20 +318,26 @@ static bool r600_query_sw_end(struct r600_common_context 
*rctx,
case R600_QUERY_NUM_MAPPED_BUFFERS:
case R600_QUERY_NUM_GFX_IBS:
case R600_QUERY_NUM_SDMA_IBS:
case R600_QUERY_NUM_BYTES_MOVED:
case R600_QUERY_NUM_EVICTIONS:
case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
break;
}
+   case R600_QUERY_GFX_BO_LIST_SIZE:
+   ws_id = winsys_id_from_type(query->b.type);
+   query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
+   query->end_time = rctx->ws->query_value(rctx->ws,
+   RADEON_NUM_GFX_IBS);
+   break;
case R600_QUERY_CS_THREAD_BUSY:
ws_id = winsys_id_from_type(query->b.type);
query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
query->end_time = os_time_get_nano();
break;
case R600_QUERY_GALLIUM_THREAD_BUSY:
query->end_result =
rctx->tc ? 
util_queue_get_thread_time_nano(>tc->queue, 0) : 0;
query->end_time = os_time_get_nano();
break;
@@ -397,20 +410,24 @@ static bool 

[Mesa-dev] [PATCH 02/14] gallium/radeon: ignore PIPE_BIND_SHARED for buffers

[Marek Olšák]

From: Marek Olšák 

BO exports can't be predicted this way.
---
 src/gallium/drivers/radeon/r600_buffer_common.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c 
b/src/gallium/drivers/radeon/r600_buffer_common.c
index 5336f55..342695c 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -603,22 +603,20 @@ r600_alloc_buffer_struct(struct pipe_screen *screen,
 
 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 const struct pipe_resource *templ,
 unsigned alignment)
 {
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 
r600_init_resource_fields(rscreen, rbuffer, templ->width0, alignment);
 
-   if (templ->bind & PIPE_BIND_SHARED)
-   rbuffer->flags |= RADEON_FLAG_HANDLE;
if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
rbuffer->flags |= RADEON_FLAG_SPARSE;
 
if (!r600_alloc_resource(rscreen, rbuffer)) {
FREE(rbuffer);
return NULL;
}
return >b.b;
 }
 
-- 
2.7.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 04/14] gallium/radeon: rename RADEON_FLAG_HANDLE -> RADEON_FLAG_NO_SUBALLOC

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/r300/r300_texture.c   | 2 +-
 src/gallium/drivers/radeon/r600_texture.c | 2 +-
 src/gallium/drivers/radeon/radeon_winsys.h| 2 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 6 +++---
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 4 ++--
 src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 2 +-
 6 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/r300/r300_texture.c 
b/src/gallium/drivers/r300/r300_texture.c
index c202fbe..cdf9ccb 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -1112,21 +1112,21 @@ r300_texture_create_object(struct r300_screen *rscreen,
 tex->domain &= ~RADEON_DOMAIN_GTT;
 }
 /* Just fail if the texture is too large. */
 if (!tex->domain) {
 goto fail;
 }
 
 /* Create the backing buffer if needed. */
 if (!tex->buf) {
 tex->buf = rws->buffer_create(rws, tex->tex.size_in_bytes, 2048,
-  tex->domain, RADEON_FLAG_HANDLE);
+  tex->domain, RADEON_FLAG_NO_SUBALLOC);
 
 if (!tex->buf) {
 goto fail;
 }
 }
 
 if (SCREEN_DBG_ON(rscreen, DBG_MSAA) && base->nr_samples > 1) {
 fprintf(stderr, "r300: %ix MSAA %s buffer created\n",
 base->nr_samples,
 util_format_is_depth_or_stencil(base->format) ? "depth" : 
"color");
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 139ab13..c811d6a 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1199,21 +1199,21 @@ r600_texture_create_object(struct pipe_screen *screen,
rtex->dcc_offset = align64(rtex->size, 
rtex->surface.dcc_alignment);
rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
}
}
 
/* Now create the backing buffer. */
if (!buf) {
r600_init_resource_fields(rscreen, resource, rtex->size,
  rtex->surface.surf_alignment);
 
-   resource->flags |= RADEON_FLAG_HANDLE;
+   resource->flags |= RADEON_FLAG_NO_SUBALLOC;
 
if (!r600_alloc_resource(rscreen, resource)) {
FREE(rtex);
return NULL;
}
} else {
resource->buf = buf;
resource->gpu_address = 
rscreen->ws->buffer_get_virtual_address(resource->buf);
resource->bo_size = buf->size;
resource->bo_alignment = buf->alignment;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 247fff0..706188f 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -46,21 +46,21 @@ enum radeon_bo_layout {
 enum radeon_bo_domain { /* bitfield */
 RADEON_DOMAIN_GTT  = 2,
 RADEON_DOMAIN_VRAM = 4,
 RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
 };
 
 enum radeon_bo_flag { /* bitfield */
 RADEON_FLAG_GTT_WC =(1 << 0),
 RADEON_FLAG_CPU_ACCESS =(1 << 1),
 RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
-RADEON_FLAG_HANDLE =(1 << 3), /* the buffer must not be 
suballocated */
+RADEON_FLAG_NO_SUBALLOC =   (1 << 3),
 RADEON_FLAG_SPARSE =(1 << 4),
 };
 
 enum radeon_bo_usage { /* bitfield */
 RADEON_USAGE_READ = 2,
 RADEON_USAGE_WRITE = 4,
 RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
 
 /* The winsys ensures that the CS submission will be scheduled after
  * previously flushed CSs referencing this BO in a conflicting way.
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 4017411..a86cc2c 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -683,21 +683,21 @@ sparse_backing_alloc(struct amdgpu_winsys_bo *bo, 
uint32_t *pstart_page, uint32_
 
   assert(bo->u.sparse.num_backing_pages < DIV_ROUND_UP(bo->base.size, 
RADEON_SPARSE_PAGE_SIZE));
 
   size = MIN3(bo->base.size / 16,
   8 * 1024 * 1024,
   bo->base.size - (uint64_t)bo->u.sparse.num_backing_pages * 
RADEON_SPARSE_PAGE_SIZE);
   size = MAX2(size, RADEON_SPARSE_PAGE_SIZE);
 
   buf = amdgpu_bo_create(>ws->base, size, RADEON_SPARSE_PAGE_SIZE,
  bo->initial_domain,
- bo->u.sparse.flags | RADEON_FLAG_HANDLE);
+ bo->u.sparse.flags | RADEON_FLAG_NO_SUBALLOC);
   if (!buf) {
  FREE(best_backing->chunks);
  FREE(best_backing);
  return NULL;
   }
 
   /* We might have gotten a bigger buffer than requested via caching. */
 

[Mesa-dev] [PATCH 00/14] AMD winsys cleanups, heaps, suballocation for textures

[Marek Olšák]

Hi,

This is mainly a cleanup series.

RADEON_FLAG_CPU_ACCESS(_REQUIRED) is no longer used. CPU access can
only be disallowed from now on, but it can't be enforced. See amd-gfx
for more discussion.

If we stay conservative, we only need 5 memory heaps, including the
VRAM_GTT heap, which isn't used with the current kernel driver.

The series defines 5 heaps and a bijective mapping between heaps and
(domain, flags) combinations. The list of heaps:
- VRAM_NO_CPU_ACCESS, VRAM, VRAM_GTT, GTT_WC, GTT

Those map nicely to pb_slab heaps, pb_cache usage flags, and pb_cache
buckets. No crazy playing with bits needed.

Finally, there are 3 changes to our suballocation code:
- suballocations are allowed for VRAM with no CPU access
- suballocations are allowed for textures
- the slab size increased to 128 KB with at most 64 KB suballocations;
  in the future, we might increase the slab size to 2 MB.

Here's a comparison of BO list sizes using a Borderlands 2 trace with
various suballocation changes. Note that the gameplay portion is the
hilly part on the far right!

https://people.freedesktop.org/~mareko/suballoc.svg

Please review.

Thanks,
Marek
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] swr: Minor cleanup of variable usage, no functional change.

[Bruce Cherniak]

In swr_update_derived, for consistency, index buffer validation should
be using the p_draw_info copy "info" rather than referencing
p_draw_info.

No functional change.
---
 src/gallium/drivers/swr/swr_state.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/swr/swr_state.cpp 
b/src/gallium/drivers/swr/swr_state.cpp
index 7a8786d96f..03dc324afe 100644
--- a/src/gallium/drivers/swr/swr_state.cpp
+++ b/src/gallium/drivers/swr/swr_state.cpp
@@ -1293,7 +1293,7 @@ swr_update_derived(struct pipe_context *pipe,
  const uint8_t *p_data;
  uint32_t size, pitch;
 
- pitch = p_draw_info->index_size ? p_draw_info->index_size : 
sizeof(uint32_t);
+ pitch = info.index_size ? info.index_size : sizeof(uint32_t);
  index_type = swr_convert_index_type(pitch);
 
  if (!info.has_user_indices) {
@@ -1319,7 +1319,7 @@ swr_update_derived(struct pipe_context *pipe,
  }
 
  SWR_INDEX_BUFFER_STATE swrIndexBuffer;
- swrIndexBuffer.format = 
swr_convert_index_type(p_draw_info->index_size);
+ swrIndexBuffer.format = swr_convert_index_type(info.index_size);
  swrIndexBuffer.pIndices = p_data;
  swrIndexBuffer.size = size;
 
-- 
2.11.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v3 5/5] android: build imx-drm winsys

[Emil Velikov]

On 29 June 2017 at 16:35, Robert Foss  wrote:
> On Thu, 2017-06-29 at 15:28 +0100, Emil Velikov wrote:
>> On 28 June 2017 at 22:52, Robert Foss 
>> wrote:
>> > From: Tomeu Vizoso 
>> >
>> > Add Android.mk for winsys/imx/drm.
>> >
>> > Signed-off-by: Tomeu Vizoso 
>> > Reviewed-by: Tapani Pälli 
>> > ---
>> > Changes since v2:
>> >   - Rebased on upstream/master
>> >   - Added commit message
>> >
>> > Changes since v1:
>> >   Emil Velikov 
>> >- Fix C_SOURCES include
>> >- Fix GALLIUM_LIBS assignment
>> >
>> >  Android.mk|  5 +++--
>> >  src/gallium/Android.mk|  1 +
>> >  src/gallium/winsys/imx/drm/Android.mk | 39
>> > +++
>> >  3 files changed, 43 insertions(+), 2 deletions(-)
>> >  create mode 100644 src/gallium/winsys/imx/drm/Android.mk
>> >
>> > diff --git a/Android.mk b/Android.mk
>> > index 2118405e1a..479a975999 100644
>> > --- a/Android.mk
>> > +++ b/Android.mk
>> > @@ -24,7 +24,7 @@
>> >  # BOARD_GPU_DRIVERS should be defined.  The valid values are
>> >  #
>> >  #   classic drivers: i915 i965
>> > -#   gallium drivers: swrast freedreno i915g nouveau pl111 r300g
>> > r600g radeonsi vc4 virgl vmwgfx etnaviv
>> > +#   gallium drivers: swrast freedreno i915g nouveau pl111 r300g
>> > r600g radeonsi vc4 virgl vmwgfx etnaviv imx
>> >  #
>> >  # The main target is libGLES_mesa.  For each classic driver
>> > enabled, a DRI
>> >  # module will also be built.  DRI modules will be loaded by
>> > libGLES_mesa.
>> > @@ -58,7 +58,8 @@ gallium_drivers := \
>> > vmwgfx.HAVE_GALLIUM_VMWGFX \
>> > vc4.HAVE_GALLIUM_VC4 \
>> > virgl.HAVE_GALLIUM_VIRGL \
>> > -   etnaviv.HAVE_GALLIUM_ETNAVIV
>> > +   etnaviv.HAVE_GALLIUM_ETNAVIV \
>> > +   imx.HAVE_GALLIUM_IMX
>> >
>> >  ifeq ($(BOARD_GPU_DRIVERS),all)
>> >  MESA_BUILD_CLASSIC := $(filter HAVE_%, $(subst ., ,
>> > $(classic_drivers)))
>> > diff --git a/src/gallium/Android.mk b/src/gallium/Android.mk
>> > index dc98fa00ed..8743dd6d26 100644
>> > --- a/src/gallium/Android.mk
>> > +++ b/src/gallium/Android.mk
>> > @@ -45,6 +45,7 @@ SUBDIRS += winsys/vc4/drm drivers/vc4
>> >  SUBDIRS += winsys/virgl/drm winsys/virgl/vtest drivers/virgl
>> >  SUBDIRS += winsys/svga/drm drivers/svga
>> >  SUBDIRS += winsys/etnaviv/drm drivers/etnaviv drivers/renderonly
>> > +SUBDIRS += winsys/imx/drm
>> >  SUBDIRS += state_trackers/dri
>> >
>> >  # sort to eliminate any duplicates
>> > diff --git a/src/gallium/winsys/imx/drm/Android.mk
>> > b/src/gallium/winsys/imx/drm/Android.mk
>> > new file mode 100644
>> > index 00..51649f8b87
>> > --- /dev/null
>> > +++ b/src/gallium/winsys/imx/drm/Android.mk
>> > @@ -0,0 +1,39 @@
>> > +# Copyright (C) 2016 Linaro, Ltd, Rob Herring 
>> > +#
>> > +# Permission is hereby granted, free of charge, to any person
>> > obtaining a
>> > +# copy of this software and associated documentation files (the
>> > "Software"),
>> > +# to deal in the Software without restriction, including without
>> > limitation
>> > +# the rights to use, copy, modify, merge, publish, distribute,
>> > sublicense,
>> > +# and/or sell copies of the Software, and to permit persons to
>> > whom the
>> > +# Software is furnished to do so, subject to the following
>> > conditions:
>> > +#
>> > +# The above copyright notice and this permission notice shall be
>> > included
>> > +# in all copies or substantial portions of the Software.
>> > +#
>> > +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> > EXPRESS OR
>> > +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> > MERCHANTABILITY,
>> > +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
>> > EVENT SHALL
>> > +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
>> > DAMAGES OR OTHER
>> > +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> > ARISING
>> > +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> > OTHER
>> > +# DEALINGS IN THE SOFTWARE.
>> > +
>> > +LOCAL_PATH := $(call my-dir)
>> > +
>> > +include $(LOCAL_PATH)/Makefile.sources
>> > +
>> > +include $(CLEAR_VARS)
>> > +
>> > +LOCAL_SRC_FILES := $(C_SOURCES)
>> > +
>> > +LOCAL_SHARED_LIBRARIES := libdrm_etnaviv
>> > +
>> > +LOCAL_MODULE := libmesa_winsys_imx
>> > +
>> > +include $(GALLIUM_COMMON_MK)
>> > +include $(BUILD_STATIC_LIBRARY)
>> > +
>> > +ifneq ($(HAVE_GALLIUM_FREEDRENO),)
>>
>> s/FREEDRENO/IMX/
>>
>> > +$(eval GALLIUM_LIBS += $(LOCAL_MODULE) libmesa_winsys_imx)
>>
>> I may have mislead you here - s/imx/etnaviv/
>>
>> Robert, seems like we've spent too long with this series and 4/5 +
>> 5/5
>> need a GALLIUM_TARGET_DRIVERS fix. See commit
>> a3d98ca62febdfbe035d655cb7c1f849bccfa105.
>>
>> Can you respin only those two - checking that things still work on
>> your end? I'll push the rest early 

Re: [Mesa-dev] [PATCH 2/5] vc4: Switch back to using a local copy of vc4_drm.h.

[Emil Velikov]

On 29 June 2017 at 16:38, Eric Anholt  wrote:
> Emil Velikov  writes:
>
>> Hi Eric,
>>
>> On 29 June 2017 at 02:15, Eric Anholt  wrote:
>>> Needing to get our uapi header from libdrm has only complicated things.
>>> Follow intel's lead and drop our requirement for it.
>>>
>> UAPI: I think I may have noticed some compat breakage here.
>>
>> The sizeof above struct will differ across 32/64bit builds and since
>> it's embedded below I doubt one can change it now.
>
> Why are you reviewing the existing UAPI in this patch?  It's UAPI.
Yes, UAPI cannot be broken/changed.

Guess I'm just naive enough, trying to help before corruption and/or
crashes occur.
If you've already sorted that - pardon for the noise. A simple - "It's
already addressed" would have been appreciated.

-Emil
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] vc4: Introduce XML-based packet header generation like Intel's.

[Eric Anholt]

Kenneth Graunke  writes:

> [ Unknown signature status ]
> On Wednesday, June 28, 2017 11:18:40 AM PDT Eric Anholt wrote:
>> I really liked this idea, as it should help with management of packet
>> parsing tools like the CL dump.  The python script is forked off of theirs
>> because our packets are byte-based instead of dwords, and the changes to
>> do so while avoiding performance regressions due to unaligned accesses
>> were quite invasive.
>> ---
>> 
>> I'm hoping for an ack from Jason or Kenneth on the genxml script fork
>> to the new location, and an Android test from Rob.  Full branch using
>> the XML stuff is at vc4-xml of my Mesa tree.
>> 
>>  Android.mk |   1 +
>>  configure.ac   |   1 +
>>  src/Makefile.am|   4 +
>>  src/broadcom/.gitignore|   1 +
>>  .../Android.genxml.mk} |  43 +-
>>  src/{intel => broadcom}/Android.mk |   5 -
>>  src/{amd => broadcom}/Makefile.am  |  22 +-
>>  .../Makefile.genxml.am}|  18 +-
>>  src/broadcom/Makefile.sources  |  12 +
>>  src/broadcom/cle/gen_pack_header.py| 547 
>> +
>>  src/broadcom/cle/v3d_packet_helpers.h  | 189 +++
>>  src/broadcom/cle/v3d_packet_v21.xml| 220 +
>>  src/gallium/drivers/vc4/Android.mk |   5 +-
>>  13 files changed, 1035 insertions(+), 33 deletions(-)
>>  create mode 100644 src/broadcom/.gitignore
>>  copy src/{mesa/Android.libmesa_git_sha1.mk => broadcom/Android.genxml.mk} 
>> (60%)
>>  copy src/{intel => broadcom}/Android.mk (86%)
>>  copy src/{amd => broadcom}/Makefile.am (75%)
>>  copy src/{intel/Makefile.common.am => broadcom/Makefile.genxml.am} (74%)
>>  create mode 100644 src/broadcom/Makefile.sources
>>  create mode 100644 src/broadcom/cle/gen_pack_header.py
>>  create mode 100644 src/broadcom/cle/v3d_packet_helpers.h
>>  create mode 100644 src/broadcom/cle/v3d_packet_v21.xml
>
> Neat!  I think it would be nice to standardize on a schema for the XML
> files, if only so things stay a bit more familiar across drivers.  It
> might allow us to share some tools too...but I'm not sure how realistic
> that is, either.  We can always do that later.
>
> You should rip off the INTEL_DEBUG=bat code as well. :)
>
> Acked-by: Kenneth Graunke 

I had just done basic code-generation that unpacks from the packed
field, and code-generation that printfs an unpacked struct.  With that,
I had to add just a bit of glue for switching over the set of packets
and recording addresses out of structs.

do_batch_dump() looks *so* much nicer, though.  Hmm.


signature.asc
Description: PGP signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2] intel: Move the DRM uapi headers to a non-Intel location.

[Rob Herring]

On Thu, Jun 29, 2017 at 10:42 AM, Eric Anholt  wrote:
> I want to remove vc4's dependency on headers from libdrm as well, but
> storing multiple copies of drm_fourcc.h in our tree would be silly.
>
> v2: Update Android.mk as well, move distcheck drm*.h references to
> top-level noinst_HEADERS.
>
> Reviewed-by: Lionel Landwerlin 
> Reviewed-by: Daniel Stone 
> ---
>  Makefile.am  |  4 
>  {src/intel/drm => include/drm-uapi}/README   |  0
>  {src/intel/drm => include/drm-uapi}/drm.h|  0
>  {src/intel/drm => include/drm-uapi}/drm_fourcc.h |  0
>  {src/intel/drm => include/drm-uapi}/drm_mode.h   |  0
>  {src/intel/drm => include/drm-uapi}/i915_drm.h   |  0
>  src/intel/Android.vulkan.mk  |  2 +-
>  src/intel/Makefile.am|  1 -
>  src/intel/Makefile.drm.am| 22 --
>  src/intel/Makefile.sources   |  6 --
>  src/intel/Makefile.vulkan.am |  2 +-
>  src/mesa/drivers/dri/i965/Android.mk |  4 ++--
>  src/mesa/drivers/dri/i965/Makefile.am|  2 +-
>  13 files changed, 9 insertions(+), 34 deletions(-)
>  rename {src/intel/drm => include/drm-uapi}/README (100%)
>  rename {src/intel/drm => include/drm-uapi}/drm.h (100%)
>  rename {src/intel/drm => include/drm-uapi}/drm_fourcc.h (100%)
>  rename {src/intel/drm => include/drm-uapi}/drm_mode.h (100%)
>  rename {src/intel/drm => include/drm-uapi}/i915_drm.h (100%)
>  delete mode 100644 src/intel/Makefile.drm.am

For Android:

Reviewed-by: Rob Herring 
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 101614] OSMesa 17.1.3 simd16intrin build FAIL on Win/MinGW - 'expected initializer before _simd16_setzero_ps ...'

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101614

--- Comment #8 from Trevor SANDY  ---
MSYS2 Setup Details - FYI

MSYS2 Install:
• Download and install msys2-x86_64-.exe (see instructions at
http://www.msys2.org/)
• Install to C:\msys64 (be sure to check 'Run MSYS2 now.' on the last install
dialogue)
• Update package database: pacman -Syu pacman
• Close MSYS2 terminal and launch again MSYS2 MSYS (Shell) from Start Menu
• Update core system packages: pacman -Suu
• Install packages:
  o pacman -S base-devel git wget p7zip
  o pacman -S perl ruby python2 python2-mako mingw-w64-x86_64-toolchain
   • toolchain package options:  ^4-6 (exclude 4 - 6)
  o pacman -S mingw-w64-x86_64-python2-mako
  o pacman -S mingw-w64-x86_64-cmake
  o pacman -S scons
• Update your .bash_profile (setup your PATH)
  o Open .bash profile in your editor (C:\mingw64\home\\.bash_profile

  # Set PATH so it includes MINGW_DIRS if they exists
  MINGW_PATHS=" \
   /mingw64/x86_64-w64-mingw32/bin \
   /mingw64/x86_64-w64-mingw32/include \
   /mingw64/x86_64-w64-mingw32/lib \
   /mingw64/bin \
   /mingw64/include \
   /mingw64/lib \
   "
  MINGW_DIRS=
  for dir in ${MINGW_PATHS}; do
   if [ -d "${dir}" ] ; then  
MINGW_DIRS="${dir}:${MINGW_DIRS}"
   fi
  done
  export PATH="${MINGW_DIRS}:${PATH}"

• Setup MSYS2 terminal shortcut
  o Navigate to C:\msys\usr\bin and right-click mintty.exe
  o From your context menu, select 'pin to start'
  o In start menu, find shortcut and select 'pin to taskbar'
• OSMesa install script:
  o mkdir -p ~/projects; cd ~/projects
  o git clone https://github.com/trevorsandy/osmesa-install.git
  o mkdir -p osmesa-install/build
• Install script setup
  o mkdir -p /opt/llvm
  o mkdir -p /opt/osmesa
• Execute install script 
  o Launch MSYS2 terminal
  o Select Mingw-w64 64 bit at selection dialogue
  o cd ~/projects/osmesa-install/build
  o ../osmesa-install.sh
• Notes: 
• python2-mako is installed in 2 places, MSYS2 base (/usr/bin) and mingw-w64
(/mingw64/bin)
• Review well the osmesa-insall.sh script to understand the options available
• At script launch, review well the env options output before accepting to
continue execution.
~~~fin~~~

-- 
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/8] swr/rast: Split backend.cpp to improve compile time

[Rowley, Timothy O]

> On Jun 28, 2017, at 3:56 AM, Emil Velikov  wrote:
> 
> On 26 June 2017 at 17:14, Rowley, Timothy O  
> wrote:
>> 
>> On Jun 26, 2017, at 7:57 AM, Emil Velikov  wrote:
> 
 +.INTERMEDIATE: backend.intermediate
 
>>> I have limited experience with .INTERMEDIATE and it didn't seem to
>>> bring single/incremental build times improvements.
>>> Have you seen any on your end? If not I'll just drop it.
>> 
>> 
>> I’m not really familiar with .INTERMEDIATE myself; found it when googling
>> around looking for a way to specify a code generator rule that produced
>> multiple files.  If there’s a better/cleaner way of doing this I’d like to
>> hear about it.
>> 
> AFAICT one can omit the line all together. I doubt it will hurt
> anything so don't bother removing it, just yet.
> 
>>> Hardcoding file names in generator scripts tends to be a bad idea. One
>>> example is the extra code needed to generate the cmake bits :-)
>>> One could prune that, but it's not a priority AFAICT.
>>> 
>>> 
>> I would like to be able to wildcard on the generated name, but it seems that
>> automake wants to have a static list of filenames at invocation.  Our cmake
>> approach internally generates a cmake fragment that is included by the
>> parent cmake, which is a little confusing but adds flexibility.
>> 
> Automake can use wildcards and template/suffix rules. Although we try
> to omit the former.
> 
> Can you share the flexibility points - I can only think of drawbacks.
> 
> I'm assuming your flow is as follows:
> A Ok, let's build the project
> B First go into go and execute a 'random file with magic arguments'
> C Now you can build via cmake
> 
> Doing any of the following and you're in a world of hurt:
> - Forget to do B - enjoy the strange error messages that you'll get ;-)
> - Do B, even when the file or any of it's dependencies have not changed.
> Your cmake files (and hence whole build) will be rebuild unnecessarily.
> 
> I think you/the team might have experienced some of those :-P
> Either way, I'll stop now since it's getting a tad much.

Ok, dug into the internal build system for this and the cmake solution isn’t as 
elegant as I thought.  We have a wrapper python script that runs cmake in the 
codegen directory to generate the cmake fragments and generated files based on 
the dependencies, then a normal cmake for the actual build that includes these 
fragments.  As long as people use that wrapper script everything builds without 
unnecessary work.

> -Emil
> P.S. Can we bribe you back to use plain text emails - I had to redo
> the email formatting :-\

This should be plain text.


___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2] intel: Move the DRM uapi headers to a non-Intel location.

[Alex Deucher]

On Thu, Jun 29, 2017 at 11:42 AM, Eric Anholt  wrote:
> I want to remove vc4's dependency on headers from libdrm as well, but
> storing multiple copies of drm_fourcc.h in our tree would be silly.
>
> v2: Update Android.mk as well, move distcheck drm*.h references to
> top-level noinst_HEADERS.
>
> Reviewed-by: Lionel Landwerlin 
> Reviewed-by: Daniel Stone 
> ---
>  Makefile.am  |  4 
>  {src/intel/drm => include/drm-uapi}/README   |  0
>  {src/intel/drm => include/drm-uapi}/drm.h|  0
>  {src/intel/drm => include/drm-uapi}/drm_fourcc.h |  0
>  {src/intel/drm => include/drm-uapi}/drm_mode.h   |  0
>  {src/intel/drm => include/drm-uapi}/i915_drm.h   |  0
>  src/intel/Android.vulkan.mk  |  2 +-
>  src/intel/Makefile.am|  1 -
>  src/intel/Makefile.drm.am| 22 --
>  src/intel/Makefile.sources   |  6 --
>  src/intel/Makefile.vulkan.am |  2 +-
>  src/mesa/drivers/dri/i965/Android.mk |  4 ++--
>  src/mesa/drivers/dri/i965/Makefile.am|  2 +-
>  13 files changed, 9 insertions(+), 34 deletions(-)
>  rename {src/intel/drm => include/drm-uapi}/README (100%)
>  rename {src/intel/drm => include/drm-uapi}/drm.h (100%)
>  rename {src/intel/drm => include/drm-uapi}/drm_fourcc.h (100%)
>  rename {src/intel/drm => include/drm-uapi}/drm_mode.h (100%)
>  rename {src/intel/drm => include/drm-uapi}/i915_drm.h (100%)
>  delete mode 100644 src/intel/Makefile.drm.am


I don't mean to pick on this patch specifically, but maybe it would
still make sense to depend on libdrm for the drm headers?  If not do
we want similar restrictions on updating these as we have for libdrm?

Alex
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [Intel-gfx] [PATCH libdrm 3/3] intel: PCI Ids for U SKU in CFL

[Rodrigo Vivi]

series merged to libdrm. thanks for patches and review.

On Wed, Jun 28, 2017 at 2:09 PM, Clint Taylor
 wrote:
>
>
> On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
>>
>> Add the PCI IDs for U SKU IN CFL by following the spec.
>>
>> v2: Update IDs
>>
>> Cc: Rodrigo Vivi 
>> Signed-off-by: Anusha Srivatsa 
>> ---
>>   intel/intel_chipset.h | 12 +++-
>>   1 file changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
>> index 4da145c..8a0d4ff 100644
>> --- a/intel/intel_chipset.h
>> +++ b/intel/intel_chipset.h
>> @@ -228,6 +228,10 @@
>>   #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
>>   #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
>>   #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
>> +#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
>> +#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
>> +#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
>> +#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
>
> Matches values in i915 driver.
> Reviewed-by: Clinton Taylor 
>
>> #define IS_MOBILE(devid)((devid) == PCI_CHIP_I855_GM || \
>>  (devid) == PCI_CHIP_I915_GM || \
>> @@ -469,8 +473,14 @@
>>   #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1
>> || \
>>(devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
>>   +#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1
>> || \
>> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2
>> || \
>> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3
>> || \
>> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4)
>> +
>>   #define IS_COFFEELAKE(devid)   (IS_CFL_S(devid) || \
>> -   IS_CFL_H(devid))
>> +   IS_CFL_H(devid) || \
>> +   IS_CFL_U(devid))
>> #define IS_GEN9(devid)  (IS_SKYLAKE(devid)  || \
>>  IS_BROXTON(devid)  || \
>
>
> ___
> Intel-gfx mailing list
> intel-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 12/18] nir/spirv: Compute offsets for UBOs and SSBOs up-front

[Jason Ekstrand]

Now that we have a pointer wrapper class, we can create offsets for UBOs
and SSBOs up-front instead of waiting until we have the full access
chain.  For push constants, we still use the old mechanism because it
provides us with some nice range information.
---
 src/compiler/spirv/vtn_private.h   |  13 +++-
 src/compiler/spirv/vtn_variables.c | 152 +++--
 2 files changed, 138 insertions(+), 27 deletions(-)

diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index 9542bec..5354ab9 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -284,14 +284,23 @@ struct vtn_pointer {
/** The dereferenced type of this pointer */
struct vtn_type *type;
 
-   /** The referenced variable */
+   /** The referenced variable, if known
+*
+* This field may be NULL if the pointer uses a (block_index, offset) pair
+* instead of an access chain.
+*/
struct vtn_variable *var;
 
/** An access chain describing how to get from var to the referenced data
 *
-* This field may be NULL if the pointer references the entire variable.
+* This field may be NULL if the pointer references the entire variable or
+* if a (block_index, offset) pair is used instead of an access chain.
 */
struct vtn_access_chain *chain;
+
+   /** A (block_index, offset) pair representing a UBO or SSBO position. */
+   struct nir_ssa_def *block_index;
+   struct nir_ssa_def *offset;
 };
 
 struct vtn_variable {
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 6ce225e..d26863b 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -59,9 +59,9 @@ vtn_access_chain_extend(struct vtn_builder *b, struct 
vtn_access_chain *old,
 
 /* Dereference the given base pointer by the access chain */
 static struct vtn_pointer *
-vtn_pointer_dereference(struct vtn_builder *b,
-struct vtn_pointer *base,
-struct vtn_access_chain *deref_chain)
+vtn_access_chain_pointer_dereference(struct vtn_builder *b,
+ struct vtn_pointer *base,
+ struct vtn_access_chain *deref_chain)
 {
struct vtn_access_chain *chain =
   vtn_access_chain_extend(b, base->chain, deref_chain->length);
@@ -103,6 +103,113 @@ vtn_access_link_as_ssa(struct vtn_builder *b, struct 
vtn_access_link link,
}
 }
 
+static nir_ssa_def *
+vtn_variable_resource_index(struct vtn_builder *b, struct vtn_variable *var,
+nir_ssa_def *desc_array_index)
+{
+   if (!desc_array_index) {
+  assert(glsl_type_is_struct(var->type->type));
+  desc_array_index = nir_imm_int(>nb, 0);
+   }
+
+   nir_intrinsic_instr *instr =
+  nir_intrinsic_instr_create(b->nb.shader,
+ nir_intrinsic_vulkan_resource_index);
+   instr->src[0] = nir_src_for_ssa(desc_array_index);
+   nir_intrinsic_set_desc_set(instr, var->descriptor_set);
+   nir_intrinsic_set_binding(instr, var->binding);
+
+   nir_ssa_dest_init(>instr, >dest, 1, 32, NULL);
+   nir_builder_instr_insert(>nb, >instr);
+
+   return >dest.ssa;
+}
+
+static struct vtn_pointer *
+vtn_ssa_offset_pointer_dereference(struct vtn_builder *b,
+   struct vtn_pointer *base,
+   struct vtn_access_chain *deref_chain)
+{
+   nir_ssa_def *block_index = base->block_index;
+   nir_ssa_def *offset = base->offset;
+   struct vtn_type *type = base->type;
+
+   unsigned idx = 0;
+   if (!block_index) {
+  assert(base->var);
+  if (glsl_type_is_array(type->type)) {
+ /* We need at least one element in the chain */
+ assert(deref_chain->length >= 1);
+
+ nir_ssa_def *desc_arr_idx =
+vtn_access_link_as_ssa(b, deref_chain->link[0], 1);
+ block_index = vtn_variable_resource_index(b, base->var, desc_arr_idx);
+ type = type->array_element;
+ idx++;
+  } else {
+ block_index = vtn_variable_resource_index(b, base->var, NULL);
+  }
+
+  /* This is the first access chain so we also need an offset */
+  assert(!offset);
+  offset = nir_imm_int(>nb, 0);
+   }
+   assert(offset);
+
+   for (; idx < deref_chain->length; idx++) {
+  switch (glsl_get_base_type(type->type)) {
+  case GLSL_TYPE_UINT:
+  case GLSL_TYPE_INT:
+  case GLSL_TYPE_UINT64:
+  case GLSL_TYPE_INT64:
+  case GLSL_TYPE_FLOAT:
+  case GLSL_TYPE_DOUBLE:
+  case GLSL_TYPE_BOOL:
+  case GLSL_TYPE_ARRAY: {
+ nir_ssa_def *elem_offset =
+vtn_access_link_as_ssa(b, deref_chain->link[idx], type->stride);
+ offset = nir_iadd(>nb, offset, elem_offset);
+ type = type->array_element;
+ break;
+  }
+
+  case GLSL_TYPE_STRUCT: {
+ assert(deref_chain->link[idx].mode == vtn_access_mode_literal);
+ 

[Mesa-dev] [PATCH 16/18] nir/spirv: Stop using glsl_type for function types

[Jason Ekstrand]

We're going to want the full vtn_type available to us anyway at which
point glsl_type isn't really buying us anything.
---
 src/compiler/spirv/spirv_to_nir.c | 23 +--
 src/compiler/spirv/vtn_cfg.c  | 30 +-
 src/compiler/spirv/vtn_private.h  |  9 +
 3 files changed, 31 insertions(+), 31 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 2d912e9..cc3ba0d 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -423,7 +423,6 @@ vtn_type_copy(struct vtn_builder *b, struct vtn_type *src)
case vtn_base_type_array:
case vtn_base_type_image:
case vtn_base_type_sampler:
-   case vtn_base_type_function:
   /* Nothing more to do */
   break;
 
@@ -436,6 +435,11 @@ vtn_type_copy(struct vtn_builder *b, struct vtn_type *src)
   memcpy(dest->offsets, src->offsets,
  src->length * sizeof(src->offsets[0]));
   break;
+
+   case vtn_base_type_function:
+  dest->params = ralloc_array(b, struct vtn_type *, src->length);
+  memcpy(dest->params, src->params, src->length * sizeof(src->params[0]));
+  break;
}
 
return dest;
@@ -840,18 +844,17 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
 
case SpvOpTypeFunction: {
   val->type->base_type = vtn_base_type_function;
+  val->type->type = NULL;
 
-  const struct glsl_type *return_type =
- vtn_value(b, w[2], vtn_value_type_type)->type->type;
-  NIR_VLA(struct glsl_function_param, params, count - 3);
-  for (unsigned i = 0; i < count - 3; i++) {
- params[i].type = vtn_value(b, w[i + 3], 
vtn_value_type_type)->type->type;
+  val->type->return_type = vtn_value(b, w[2], vtn_value_type_type)->type;
 
- /* FIXME: */
- params[i].in = true;
- params[i].out = true;
+  const unsigned num_params = count - 3;
+  val->type->length = num_params;
+  val->type->params = ralloc_array(b, struct vtn_type *, num_params);
+  for (unsigned i = 0; i < count - 3; i++) {
+ val->type->params[i] =
+vtn_value(b, w[i + 3], vtn_value_type_type)->type;
   }
-  val->type->type = glsl_function_type(return_type, params, count - 3);
   break;
}
 
diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
index 0bdc913..dc429e6 100644
--- a/src/compiler/spirv/vtn_cfg.c
+++ b/src/compiler/spirv/vtn_cfg.c
@@ -41,36 +41,24 @@ vtn_cfg_handle_prepass_instruction(struct vtn_builder *b, 
SpvOp opcode,
   struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_function);
   val->func = b->func;
 
-  const struct glsl_type *func_type =
- vtn_value(b, w[4], vtn_value_type_type)->type->type;
+  const struct vtn_type *func_type =
+ vtn_value(b, w[4], vtn_value_type_type)->type;
 
-  assert(glsl_get_function_return_type(func_type) == result_type);
+  assert(func_type->return_type->type == result_type);
 
   nir_function *func =
  nir_function_create(b->shader, ralloc_strdup(b->shader, val->name));
 
-  func->num_params = glsl_get_length(func_type);
+  func->num_params = func_type->length;
   func->params = ralloc_array(b->shader, nir_parameter, func->num_params);
   for (unsigned i = 0; i < func->num_params; i++) {
- const struct glsl_function_param *param =
-glsl_get_function_param(func_type, i);
- func->params[i].type = param->type;
- if (param->in) {
-if (param->out) {
-   func->params[i].param_type = nir_parameter_inout;
-} else {
-   func->params[i].param_type = nir_parameter_in;
-}
- } else {
-if (param->out) {
-   func->params[i].param_type = nir_parameter_out;
-} else {
-   assert(!"Parameter is neither in nor out");
-}
- }
+ func->params[i].type = func_type->params[i]->type;
+
+ /* TODO: We could do something smarter here. */
+ func->params[i].param_type = nir_parameter_inout;
   }
 
-  func->return_type = glsl_get_function_return_type(func_type);
+  func->return_type = func_type->return_type->type;
 
   b->func->impl = nir_function_impl_create(func);
 
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index e54ddf0..4972b55 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -271,6 +271,15 @@ struct vtn_type {
  /* Access qualifier for storage images */
  SpvAccessQualifier access_qualifier;
   };
+
+  /* Members for function types */
+  struct {
+ /* For functions, the vtn_type for each parameter */
+ struct vtn_type **params;
+
+ /* Return type for functions */
+ struct vtn_type *return_type;
+  };
};
 };
 
-- 
2.5.0.400.gff86faf

[Mesa-dev] [PATCH 15/18] nir/spirv: Beef up the type system a bit

[Jason Ekstrand]

This adds a vtn concept of base_type as well as a couple of other
fields.  This lets us be a tiny bit more efficient in some cases but,
more importantly, it will eventually let us express things the GLSL type
system can't.
---
 src/compiler/spirv/spirv_to_nir.c | 67 +++
 src/compiler/spirv/vtn_private.h  | 20 
 2 files changed, 59 insertions(+), 28 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 58e316d..2d912e9 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -415,32 +415,27 @@ vtn_type_copy(struct vtn_builder *b, struct vtn_type *src)
struct vtn_type *dest = ralloc(b, struct vtn_type);
*dest = *src;
 
-   if (!glsl_type_is_scalar(src->type)) {
-  switch (glsl_get_base_type(src->type)) {
-  case GLSL_TYPE_INT:
-  case GLSL_TYPE_UINT:
-  case GLSL_TYPE_INT64:
-  case GLSL_TYPE_UINT64:
-  case GLSL_TYPE_BOOL:
-  case GLSL_TYPE_FLOAT:
-  case GLSL_TYPE_DOUBLE:
-  case GLSL_TYPE_ARRAY:
- break;
-
-  case GLSL_TYPE_STRUCT: {
- unsigned elems = glsl_get_length(src->type);
+   switch (src->base_type) {
+   case vtn_base_type_void:
+   case vtn_base_type_scalar:
+   case vtn_base_type_vector:
+   case vtn_base_type_matrix:
+   case vtn_base_type_array:
+   case vtn_base_type_image:
+   case vtn_base_type_sampler:
+   case vtn_base_type_function:
+  /* Nothing more to do */
+  break;
 
- dest->members = ralloc_array(b, struct vtn_type *, elems);
- memcpy(dest->members, src->members, elems * sizeof(struct vtn_type 
*));
+   case vtn_base_type_struct:
+  dest->members = ralloc_array(b, struct vtn_type *, src->length);
+  memcpy(dest->members, src->members,
+ src->length * sizeof(src->members[0]));
 
- dest->offsets = ralloc_array(b, unsigned, elems);
- memcpy(dest->offsets, src->offsets, elems * sizeof(unsigned));
- break;
-  }
-
-  default:
- unreachable("unhandled type");
-  }
+  dest->offsets = ralloc_array(b, unsigned, src->length);
+  memcpy(dest->offsets, src->offsets,
+ src->length * sizeof(src->offsets[0]));
+  break;
}
 
return dest;
@@ -732,14 +727,17 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
 
switch (opcode) {
case SpvOpTypeVoid:
+  val->type->base_type = vtn_base_type_void;
   val->type->type = glsl_void_type();
   break;
case SpvOpTypeBool:
+  val->type->base_type = vtn_base_type_scalar;
   val->type->type = glsl_bool_type();
   break;
case SpvOpTypeInt: {
   int bit_size = w[2];
   const bool signedness = w[3];
+  val->type->base_type = vtn_base_type_scalar;
   if (bit_size == 64)
  val->type->type = (signedness ? glsl_int64_t_type() : 
glsl_uint64_t_type());
   else
@@ -748,6 +746,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
}
case SpvOpTypeFloat: {
   int bit_size = w[2];
+  val->type->base_type = vtn_base_type_scalar;
   val->type->type = bit_size == 64 ? glsl_double_type() : 
glsl_float_type();
   break;
}
@@ -757,6 +756,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
   unsigned elems = w[3];
 
   assert(glsl_type_is_scalar(base->type));
+  val->type->base_type = vtn_base_type_vector;
   val->type->type = glsl_vector_type(glsl_get_base_type(base->type), 
elems);
 
   /* Vectors implicitly have sizeof(base_type) stride.  For now, this
@@ -773,10 +773,12 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
   unsigned columns = w[3];
 
   assert(glsl_type_is_vector(base->type));
+  val->type->base_type = vtn_base_type_matrix;
   val->type->type = glsl_matrix_type(glsl_get_base_type(base->type),
  glsl_get_vector_elements(base->type),
  columns);
   assert(!glsl_type_is_error(val->type->type));
+  val->type->length = columns;
   val->type->array_element = base;
   val->type->row_major = false;
   val->type->stride = 0;
@@ -788,16 +790,16 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
   struct vtn_type *array_element =
  vtn_value(b, w[2], vtn_value_type_type)->type;
 
-  unsigned length;
   if (opcode == SpvOpTypeRuntimeArray) {
  /* A length of 0 is used to denote unsized arrays */
- length = 0;
+ val->type->length = 0;
   } else {
- length =
+ val->type->length =
 vtn_value(b, w[3], 
vtn_value_type_constant)->constant->values[0].u32[0];
   }
 
-  val->type->type = glsl_array_type(array_element->type, length);
+  val->type->base_type = vtn_base_type_array;
+  val->type->type = glsl_array_type(array_element->type, 
val->type->length);
   val->type->array_element = array_element;
   val->type->stride = 

[Mesa-dev] [PATCH 17/18] nir/spirv: Use real pointer types

[Jason Ekstrand]

---
 src/compiler/spirv/spirv_to_nir.c  | 23 +--
 src/compiler/spirv/vtn_cfg.c   | 12 ++--
 src/compiler/spirv/vtn_private.h   | 18 ++
 src/compiler/spirv/vtn_variables.c | 13 ++---
 4 files changed, 55 insertions(+), 11 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index cc3ba0d..462b049 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -421,6 +421,7 @@ vtn_type_copy(struct vtn_builder *b, struct vtn_type *src)
case vtn_base_type_vector:
case vtn_base_type_matrix:
case vtn_base_type_array:
+   case vtn_base_type_pointer:
case vtn_base_type_image:
case vtn_base_type_sampler:
   /* Nothing more to do */
@@ -858,13 +859,17 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
   break;
}
 
-   case SpvOpTypePointer:
-  /* FIXME:  For now, we'll just do the really lame thing and return
-   * the same type.  The validator should ensure that the proper number
-   * of dereferences happen
-   */
-  val->type = vtn_value(b, w[3], vtn_value_type_type)->type;
+   case SpvOpTypePointer: {
+  SpvStorageClass storage_class = w[2];
+  struct vtn_type *deref_type =
+ vtn_value(b, w[3], vtn_value_type_type)->type;
+
+  val->type->base_type = vtn_base_type_pointer;
+  val->type->type = NULL;
+  val->type->storage_class = storage_class;
+  val->type->deref = deref_type;
   break;
+   }
 
case SpvOpTypeImage: {
   val->type->base_type = vtn_base_type_image;
@@ -956,6 +961,12 @@ vtn_null_constant(struct vtn_builder *b, const struct 
glsl_type *type)
 {
nir_constant *c = rzalloc(b, nir_constant);
 
+   /* For pointers and other typeless things, we have to return something but
+* it doesn't matter what.
+*/
+   if (!type)
+  return c;
+
switch (glsl_get_base_type(type)) {
case GLSL_TYPE_INT:
case GLSL_TYPE_UINT:
diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
index dc429e6..83e77e2 100644
--- a/src/compiler/spirv/vtn_cfg.c
+++ b/src/compiler/spirv/vtn_cfg.c
@@ -52,7 +52,11 @@ vtn_cfg_handle_prepass_instruction(struct vtn_builder *b, 
SpvOp opcode,
   func->num_params = func_type->length;
   func->params = ralloc_array(b->shader, nir_parameter, func->num_params);
   for (unsigned i = 0; i < func->num_params; i++) {
- func->params[i].type = func_type->params[i]->type;
+ if (func_type->params[i]->base_type == vtn_base_type_pointer) {
+func->params[i].type = func_type->params[i]->deref->type;
+ } else {
+func->params[i].type = func_type->params[i]->type;
+ }
 
  /* TODO: We could do something smarter here. */
  func->params[i].param_type = nir_parameter_inout;
@@ -73,11 +77,15 @@ vtn_cfg_handle_prepass_instruction(struct vtn_builder *b, 
SpvOp opcode,
 
case SpvOpFunctionParameter: {
   struct vtn_type *type = vtn_value(b, w[1], vtn_value_type_type)->type;
+  if (type->base_type == vtn_base_type_pointer) {
+ type = type->deref;
+ assert(type->base_type != vtn_base_type_pointer);
+  }
 
   assert(b->func_param_idx < b->func->impl->num_params);
   nir_variable *param = b->func->impl->params[b->func_param_idx++];
 
-  assert(param->type == type->type);
+  assert(type->type == param->type);
 
   struct vtn_variable *vtn_var = rzalloc(b, struct vtn_variable);
   vtn_var->type = type;
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index 4972b55..446d9fa 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -203,6 +203,7 @@ enum vtn_base_type {
vtn_base_type_matrix,
vtn_base_type_array,
vtn_base_type_struct,
+   vtn_base_type_pointer,
vtn_base_type_image,
vtn_base_type_sampler,
vtn_base_type_function,
@@ -260,6 +261,15 @@ struct vtn_type {
  bool builtin_block:1;
   };
 
+  /* Members for pointer types */
+  struct {
+ /* For pointers, the vtn_type for dereferenced type */
+ struct vtn_type *deref;
+
+ /* Storage class for pointers */
+ SpvStorageClass storage_class;
+  };
+
   /* Members for image types */
   struct {
  /* For images, indicates whether it's sampled or storage */
@@ -327,6 +337,14 @@ struct vtn_pointer {
/** The dereferenced type of this pointer */
struct vtn_type *type;
 
+   /** The pointer type of this pointer
+*
+* This may be NULL for some temporary pointers constructed as part of a
+* large load, store, or copy.  It MUST be valid for all pointers which are
+* stored as SPIR-V SSA values.
+*/
+   struct vtn_type *ptr_type;
+
/** The referenced variable, if known
 *
 * This field may be NULL if the pointer uses a (block_index, offset) pair
diff --git 

[Mesa-dev] [PATCH 11/18] nir/spirv: Rework the way pointers get dereferenced

[Jason Ekstrand]

This has the advantage of moving all of the "extend an access chain"
code into one place.
---
 src/compiler/spirv/vtn_private.h   |   8 ++-
 src/compiler/spirv/vtn_variables.c | 144 +
 2 files changed, 88 insertions(+), 64 deletions(-)

diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index fb2d669..9542bec 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -255,8 +255,12 @@ struct vtn_access_link {
 struct vtn_access_chain {
uint32_t length;
 
-   /* Struct elements and array offsets */
-   struct vtn_access_link link[0];
+   /** Struct elements and array offsets.
+*
+* This is an array of 1 so that it can conveniently be created on the
+* stack but the real length is given by the length field.
+*/
+   struct vtn_access_link link[1];
 };
 
 enum vtn_variable_mode {
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 7890594..6ce225e 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -29,17 +29,27 @@
 #include "spirv_info.h"
 
 static struct vtn_access_chain *
+vtn_access_chain_create(struct vtn_builder *b, unsigned length)
+{
+   struct vtn_access_chain *chain;
+
+   /* Subtract 1 from the length since there's already one built in */
+   size_t size = sizeof(*chain) +
+ (MAX2(length, 1) - 1) * sizeof(chain->link[0]);
+   chain = rzalloc_size(b, size);
+   chain->length = length;
+
+   return chain;
+}
+
+static struct vtn_access_chain *
 vtn_access_chain_extend(struct vtn_builder *b, struct vtn_access_chain *old,
 unsigned new_ids)
 {
struct vtn_access_chain *chain;
 
unsigned old_len = old ? old->length : 0;
-   unsigned new_len = old_len + new_ids;
-   /* TODO: don't use rzalloc */
-   chain = rzalloc_size(b, sizeof(*chain) + new_len * sizeof(chain->link[0]));
-
-   chain->length = new_len;
+   chain = vtn_access_chain_create(b, old_len + new_ids);
 
for (unsigned i = 0; i < old_len; i++)
   chain->link[i] = old->link[i];
@@ -47,6 +57,37 @@ vtn_access_chain_extend(struct vtn_builder *b, struct 
vtn_access_chain *old,
return chain;
 }
 
+/* Dereference the given base pointer by the access chain */
+static struct vtn_pointer *
+vtn_pointer_dereference(struct vtn_builder *b,
+struct vtn_pointer *base,
+struct vtn_access_chain *deref_chain)
+{
+   struct vtn_access_chain *chain =
+  vtn_access_chain_extend(b, base->chain, deref_chain->length);
+   struct vtn_type *type = base->type;
+
+   unsigned start = base->chain ? base->chain->length : 0;
+   for (unsigned i = 0; i < deref_chain->length; i++) {
+  chain->link[start + i] = deref_chain->link[i];
+
+  if (glsl_type_is_struct(type->type)) {
+ assert(deref_chain->link[i].mode == vtn_access_mode_literal);
+ type = type->members[deref_chain->link[i].id];
+  } else {
+ type = type->array_element;
+  }
+   }
+
+   struct vtn_pointer *ptr = rzalloc(b, struct vtn_pointer);
+   ptr->mode = base->mode;
+   ptr->type = type;
+   ptr->var = base->var;
+   ptr->chain = chain;
+
+   return ptr;
+}
+
 static nir_ssa_def *
 vtn_access_link_as_ssa(struct vtn_builder *b, struct vtn_access_link link,
unsigned stride)
@@ -717,15 +758,16 @@ _vtn_variable_load_store(struct vtn_builder *b, bool load,
  (*inout)->elems = rzalloc_array(b, struct vtn_ssa_value *, elems);
   }
 
-  struct vtn_pointer elem = *ptr;
-  elem.chain = vtn_access_chain_extend(b, ptr->chain, 1);
-  unsigned link_idx = ptr->chain ? ptr->chain->length : 0;
-  elem.chain->link[link_idx].mode = vtn_access_mode_literal;
+  struct vtn_access_chain chain = {
+ .length = 1,
+ .link = {
+{ .mode = vtn_access_mode_literal, },
+ }
+  };
   for (unsigned i = 0; i < elems; i++) {
- elem.chain->link[link_idx].id = i;
- elem.type = (base_type == GLSL_TYPE_ARRAY) ? ptr->type->array_element 
:
-  ptr->type->members[i];
- _vtn_variable_load_store(b, load, , &(*inout)->elems[i]);
+ chain.link[0].id = i;
+ struct vtn_pointer *elem = vtn_pointer_dereference(b, ptr, );
+ _vtn_variable_load_store(b, load, elem, &(*inout)->elems[i]);
   }
   return;
}
@@ -784,24 +826,21 @@ _vtn_variable_copy(struct vtn_builder *b, struct 
vtn_pointer *dest,
 
case GLSL_TYPE_ARRAY:
case GLSL_TYPE_STRUCT: {
-  struct vtn_pointer src_elem = *src, dest_elem = *dest;
-  src_elem.chain = vtn_access_chain_extend(b, src->chain, 1);
-  dest_elem.chain = vtn_access_chain_extend(b, dest->chain, 1);
-  src_elem.chain->link[src_elem.chain->length - 1].mode = 
vtn_access_mode_literal;
-  dest_elem.chain->link[dest_elem.chain->length - 1].mode = 
vtn_access_mode_literal;
-

[Mesa-dev] [PATCH 14/18] nir/spirv: Compact vtn_type

[Jason Ekstrand]

Use an anonymous union of structs to help keep the structure small and
better organized.
---
 src/compiler/spirv/spirv_to_nir.c |  1 -
 src/compiler/spirv/vtn_private.h  | 64 ---
 2 files changed, 39 insertions(+), 26 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index c69cb8c..58e316d 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -728,7 +728,6 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
struct vtn_value *val = vtn_push_value(b, w[1], vtn_value_type_type);
 
val->type = rzalloc(b, struct vtn_type);
-   val->type->is_builtin = false;
val->type->val = val;
 
switch (opcode) {
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index 5354ab9..f7aa784 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -202,42 +202,56 @@ struct vtn_type {
/* The value that declares this type.  Used for finding decorations */
struct vtn_value *val;
 
-   /* for matrices, whether the matrix is stored row-major */
-   bool row_major;
+   union {
+  /* Members for scalar, vector, and array-like types */
+  struct {
+ /* for arrays, the vtn_type for the elements of the array */
+ struct vtn_type *array_element;
 
-   /* for structs, the offset of each member */
-   unsigned *offsets;
+ /* for arrays and matrices, the array stride */
+ unsigned stride;
 
-   /* for structs, whether it was decorated as a "non-SSBO-like" block */
-   bool block;
+ /* for matrices, whether the matrix is stored row-major */
+ bool row_major:1;
 
-   /* for structs, whether it was decorated as an "SSBO-like" block */
-   bool buffer_block;
+ /* Whether this type, or a parent type, has been decorated as a
+  * builtin
+  */
+ bool is_builtin:1;
 
-   /* for structs with block == true, whether this is a builtin block (i.e. a
-* block that contains only builtins).
-*/
-   bool builtin_block;
+ /* Which built-in to use */
+ SpvBuiltIn builtin;
+  };
 
-   /* Image format for image_load_store type images */
-   unsigned image_format;
+  /* Members for struct types */
+  struct {
+ /* for structures, the vtn_type for each member */
+ struct vtn_type **members;
 
-   /* Access qualifier for storage images */
-   SpvAccessQualifier access_qualifier;
+ /* for structs, the offset of each member */
+ unsigned *offsets;
 
-   /* for arrays and matrices, the array stride */
-   unsigned stride;
+ /* for structs, whether it was decorated as a "non-SSBO-like" block */
+ bool block:1;
 
-   /* for arrays, the vtn_type for the elements of the array */
-   struct vtn_type *array_element;
+ /* for structs, whether it was decorated as an "SSBO-like" block */
+ bool buffer_block:1;
 
-   /* for structures, the vtn_type for each member */
-   struct vtn_type **members;
+ /* for structs with block == true, whether this is a builtin block
+  * (i.e. a block that contains only builtins).
+  */
+ bool builtin_block:1;
+  };
 
-   /* Whether this type, or a parent type, has been decorated as a builtin */
-   bool is_builtin;
+  /* Members for image types */
+  struct {
+ /* Image format for image_load_store type images */
+ unsigned image_format;
 
-   SpvBuiltIn builtin;
+ /* Access qualifier for storage images */
+ SpvAccessQualifier access_qualifier;
+  };
+   };
 };
 
 struct vtn_variable;
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 13/18] nir/spirv: Simplify type copying

[Jason Ekstrand]

---
 src/compiler/spirv/spirv_to_nir.c | 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 3d9ef76..c69cb8c 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -413,10 +413,7 @@ static struct vtn_type *
 vtn_type_copy(struct vtn_builder *b, struct vtn_type *src)
 {
struct vtn_type *dest = ralloc(b, struct vtn_type);
-   dest->type = src->type;
-   dest->is_builtin = src->is_builtin;
-   if (src->is_builtin)
-  dest->builtin = src->builtin;
+   *dest = *src;
 
if (!glsl_type_is_scalar(src->type)) {
   switch (glsl_get_base_type(src->type)) {
@@ -428,9 +425,6 @@ vtn_type_copy(struct vtn_builder *b, struct vtn_type *src)
   case GLSL_TYPE_FLOAT:
   case GLSL_TYPE_DOUBLE:
   case GLSL_TYPE_ARRAY:
- dest->row_major = src->row_major;
- dest->stride = src->stride;
- dest->array_element = src->array_element;
  break;
 
   case GLSL_TYPE_STRUCT: {
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 18/18] nir/spirv: Rework function argument setup

[Jason Ekstrand]

Now that we have proper pointer types, we can be more sensible about the
way we set up function arguments and deal with the two cases of pointer
vs. SSA parameters distinctly.
---
 src/compiler/spirv/vtn_cfg.c | 62 +---
 1 file changed, 35 insertions(+), 27 deletions(-)

diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
index 83e77e2..f53572b 100644
--- a/src/compiler/spirv/vtn_cfg.c
+++ b/src/compiler/spirv/vtn_cfg.c
@@ -65,6 +65,7 @@ vtn_cfg_handle_prepass_instruction(struct vtn_builder *b, 
SpvOp opcode,
   func->return_type = func_type->return_type->type;
 
   b->func->impl = nir_function_impl_create(func);
+  b->nb.cursor = nir_before_cf_list(>func->impl->body);
 
   b->func_param_idx = 0;
   break;
@@ -77,43 +78,50 @@ vtn_cfg_handle_prepass_instruction(struct vtn_builder *b, 
SpvOp opcode,
 
case SpvOpFunctionParameter: {
   struct vtn_type *type = vtn_value(b, w[1], vtn_value_type_type)->type;
-  if (type->base_type == vtn_base_type_pointer) {
- type = type->deref;
- assert(type->base_type != vtn_base_type_pointer);
-  }
 
   assert(b->func_param_idx < b->func->impl->num_params);
   nir_variable *param = b->func->impl->params[b->func_param_idx++];
 
-  assert(type->type == param->type);
+  if (type->base_type == vtn_base_type_pointer) {
+ struct vtn_variable *vtn_var = rzalloc(b, struct vtn_variable);
+ vtn_var->type = type->deref;
+ vtn_var->var = param;
+
+ assert(vtn_var->type->type == param->type);
+
+ struct vtn_type *without_array = vtn_var->type;
+ while(glsl_type_is_array(without_array->type))
+without_array = without_array->array_element;
+
+ if (glsl_type_is_image(without_array->type)) {
+vtn_var->mode = vtn_variable_mode_image;
+param->interface_type = without_array->type;
+ } else if (glsl_type_is_sampler(without_array->type)) {
+vtn_var->mode = vtn_variable_mode_sampler;
+param->interface_type = without_array->type;
+ } else {
+vtn_var->mode = vtn_variable_mode_param;
+ }
 
-  struct vtn_variable *vtn_var = rzalloc(b, struct vtn_variable);
-  vtn_var->type = type;
-  vtn_var->var = param;
+ struct vtn_value *val =
+vtn_push_value(b, w[2], vtn_value_type_pointer);
 
-  struct vtn_type *without_array = type;
-  while(glsl_type_is_array(without_array->type))
- without_array = without_array->array_element;
+ /* Name the parameter so it shows up nicely in NIR */
+ param->name = ralloc_strdup(param, val->name);
 
-  if (glsl_type_is_image(without_array->type)) {
- vtn_var->mode = vtn_variable_mode_image;
- param->interface_type = without_array->type;
-  } else if (glsl_type_is_sampler(without_array->type)) {
- vtn_var->mode = vtn_variable_mode_sampler;
- param->interface_type = without_array->type;
+ val->pointer = rzalloc(b, struct vtn_pointer);
+ val->pointer->mode = vtn_var->mode;
+ val->pointer->type = type;
+ val->pointer->var = vtn_var;
   } else {
- vtn_var->mode = vtn_variable_mode_param;
-  }
+ /* We're a regular SSA value. */
+ struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_ssa);
 
-  struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_pointer);
+ /* Name the parameter so it shows up nicely in NIR */
+ param->name = ralloc_strdup(param, val->name);
 
-  /* Name the parameter so it shows up nicely in NIR */
-  param->name = ralloc_strdup(param, val->name);
-
-  val->pointer = rzalloc(b, struct vtn_pointer);
-  val->pointer->mode = vtn_var->mode;
-  val->pointer->type = type;
-  val->pointer->var = vtn_var;
+ val->ssa = vtn_local_load(b, nir_deref_var_create(b, param));
+  }
   break;
}
 
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 06/18] nir/spirv: Wrap access chains in a new vtn_pointer data structure

[Jason Ekstrand]

The vtn_pointer structure provides a bit better abstraction than passing
access chains around directly.  For one thing, if the pointer just
points to a variable, we don't need the access chain at all.  Also,
pointers know what their dereferenced type is so we can avoid passing
the type in a bunch of places.  Finally, pointers can, in theory, be
extended to the case where you don't actually know what variable is
being referenced.
---
 src/compiler/spirv/spirv_to_nir.c  |  17 +--
 src/compiler/spirv/vtn_cfg.c   |  17 +--
 src/compiler/spirv/vtn_private.h   |  40 --
 src/compiler/spirv/vtn_variables.c | 262 +++--
 4 files changed, 177 insertions(+), 159 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 02b42f2..18e3734 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -2069,7 +2069,7 @@ static void
 vtn_handle_ssbo_or_shared_atomic(struct vtn_builder *b, SpvOp opcode,
  const uint32_t *w, unsigned count)
 {
-   struct vtn_access_chain *ptr;
+   struct vtn_pointer *ptr;
nir_intrinsic_instr *atomic;
 
switch (opcode) {
@@ -2104,7 +2104,7 @@ vtn_handle_ssbo_or_shared_atomic(struct vtn_builder *b, 
SpvOp opcode,
SpvMemorySemanticsMask semantics = w[5];
*/
 
-   if (ptr->var->mode == vtn_variable_mode_workgroup) {
+   if (ptr->mode == vtn_variable_mode_workgroup) {
   nir_deref_var *deref = vtn_pointer_to_deref(b, ptr);
   const struct glsl_type *deref_type = nir_deref_tail(>deref)->type;
   nir_intrinsic_op op = get_shared_nir_atomic_op(opcode);
@@ -2144,9 +2144,9 @@ vtn_handle_ssbo_or_shared_atomic(struct vtn_builder *b, 
SpvOp opcode,
 
   }
} else {
-  assert(ptr->var->mode == vtn_variable_mode_ssbo);
-  struct vtn_type *type;
+  assert(ptr->mode == vtn_variable_mode_ssbo);
   nir_ssa_def *offset, *index;
+  struct vtn_type *type;
   offset = vtn_pointer_to_offset(b, ptr, , , NULL, false);
 
   nir_intrinsic_op op = get_ssbo_nir_atomic_op(opcode);
@@ -2155,13 +2155,13 @@ vtn_handle_ssbo_or_shared_atomic(struct vtn_builder *b, 
SpvOp opcode,
 
   switch (opcode) {
   case SpvOpAtomicLoad:
- atomic->num_components = glsl_get_vector_elements(type->type);
+ atomic->num_components = glsl_get_vector_elements(ptr->type->type);
  atomic->src[0] = nir_src_for_ssa(index);
  atomic->src[1] = nir_src_for_ssa(offset);
  break;
 
   case SpvOpAtomicStore:
- atomic->num_components = glsl_get_vector_elements(type->type);
+ atomic->num_components = glsl_get_vector_elements(ptr->type->type);
  nir_intrinsic_set_write_mask(atomic, (1 << atomic->num_components) - 
1);
  atomic->src[0] = nir_src_for_ssa(vtn_ssa_value(b, w[4])->def);
  atomic->src[1] = nir_src_for_ssa(index);
@@ -3063,11 +3063,12 @@ vtn_handle_body_instruction(struct vtn_builder *b, 
SpvOp opcode,
   break;
 
case SpvOpImageQuerySize: {
-  struct vtn_access_chain *image =
+  struct vtn_pointer *image =
  vtn_value(b, w[3], vtn_value_type_pointer)->pointer;
-  if (glsl_type_is_image(image->var->var->interface_type)) {
+  if (image->mode == vtn_variable_mode_image) {
  vtn_handle_image(b, opcode, w, count);
   } else {
+ assert(image->mode == vtn_variable_mode_sampler);
  vtn_handle_texture(b, opcode, w, count);
   }
   break;
diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
index 123a8c6..0bdc913 100644
--- a/src/compiler/spirv/vtn_cfg.c
+++ b/src/compiler/spirv/vtn_cfg.c
@@ -84,8 +84,6 @@ vtn_cfg_handle_prepass_instruction(struct vtn_builder *b, 
SpvOp opcode,
   break;
 
case SpvOpFunctionParameter: {
-  struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_pointer);
-
   struct vtn_type *type = vtn_value(b, w[1], vtn_value_type_type)->type;
 
   assert(b->func_param_idx < b->func->impl->num_params);
@@ -93,14 +91,9 @@ vtn_cfg_handle_prepass_instruction(struct vtn_builder *b, 
SpvOp opcode,
 
   assert(param->type == type->type);
 
-  /* Name the parameter so it shows up nicely in NIR */
-  param->name = ralloc_strdup(param, val->name);
-
   struct vtn_variable *vtn_var = rzalloc(b, struct vtn_variable);
   vtn_var->type = type;
   vtn_var->var = param;
-  vtn_var->ptr.var = vtn_var;
-  vtn_var->ptr.length = 0;
 
   struct vtn_type *without_array = type;
   while(glsl_type_is_array(without_array->type))
@@ -116,7 +109,15 @@ vtn_cfg_handle_prepass_instruction(struct vtn_builder *b, 
SpvOp opcode,
  vtn_var->mode = vtn_variable_mode_param;
   }
 
-  val->pointer = _var->ptr;
+  struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_pointer);
+
+  /* Name the parameter so it shows up nicely in NIR */
+  param->name = ralloc_strdup(param, val->name);
+
+ 

[Mesa-dev] [PATCH 10/18] nir/spirv: Break variable creation out into a helper

[Jason Ekstrand]

---
 src/compiler/spirv/vtn_variables.c | 362 +++--
 1 file changed, 187 insertions(+), 175 deletions(-)

diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 7821663..7890594 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1314,213 +1314,225 @@ is_per_vertex_inout(const struct vtn_variable *var, 
gl_shader_stage stage)
return false;
 }
 
-void
-vtn_handle_variables(struct vtn_builder *b, SpvOp opcode,
- const uint32_t *w, unsigned count)
+static void
+vtn_create_variable(struct vtn_builder *b, struct vtn_value *val,
+struct vtn_type *type, SpvStorageClass storage_class,
+nir_constant *initializer)
 {
-   switch (opcode) {
-   case SpvOpUndef: {
-  struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_undef);
-  val->type = vtn_value(b, w[1], vtn_value_type_type)->type;
-  break;
-   }
+   struct vtn_type *without_array = type;
+   while(glsl_type_is_array(without_array->type))
+  without_array = without_array->array_element;
 
-   case SpvOpVariable: {
-  struct vtn_type *type = vtn_value(b, w[1], vtn_value_type_type)->type;
+   enum vtn_variable_mode mode;
+   nir_variable_mode nir_mode;
+   mode = vtn_storage_class_to_mode(storage_class, without_array, _mode);
 
-  struct vtn_type *without_array = type;
-  while(glsl_type_is_array(without_array->type))
- without_array = without_array->array_element;
+   switch (mode) {
+   case vtn_variable_mode_ubo:
+  b->shader->info.num_ubos++;
+  break;
+   case vtn_variable_mode_ssbo:
+  b->shader->info.num_ssbos++;
+  break;
+   case vtn_variable_mode_image:
+  b->shader->info.num_images++;
+  break;
+   case vtn_variable_mode_sampler:
+  b->shader->info.num_textures++;
+  break;
+   case vtn_variable_mode_push_constant:
+  b->shader->num_uniforms = vtn_type_block_size(type);
+  break;
+   default:
+  /* No tallying is needed */
+  break;
+   }
 
-  enum vtn_variable_mode mode;
-  nir_variable_mode nir_mode;
-  mode = vtn_storage_class_to_mode(w[3], without_array, _mode);
+   assert(val->value_type == vtn_value_type_pointer);
+   val->pointer = rzalloc(b, struct vtn_pointer);
+   val->pointer->type = type;
+   val->pointer->mode = mode;
+
+   struct vtn_variable *var = rzalloc(b, struct vtn_variable);
+   var->type = type;
+   var->mode = mode;
+   val->pointer->var = var;
+
+   switch (var->mode) {
+   case vtn_variable_mode_local:
+   case vtn_variable_mode_global:
+   case vtn_variable_mode_image:
+   case vtn_variable_mode_sampler:
+   case vtn_variable_mode_workgroup:
+  /* For these, we create the variable normally */
+  var->var = rzalloc(b->shader, nir_variable);
+  var->var->name = ralloc_strdup(var->var, val->name);
+  var->var->type = var->type->type;
+  var->var->data.mode = nir_mode;
 
-  switch (mode) {
-  case vtn_variable_mode_ubo:
- b->shader->info.num_ubos++;
- break;
-  case vtn_variable_mode_ssbo:
- b->shader->info.num_ssbos++;
- break;
+  switch (var->mode) {
   case vtn_variable_mode_image:
- b->shader->info.num_images++;
- break;
   case vtn_variable_mode_sampler:
- b->shader->info.num_textures++;
- break;
-  case vtn_variable_mode_push_constant:
- b->shader->num_uniforms = vtn_type_block_size(type);
+ var->var->interface_type = without_array->type;
  break;
   default:
- /* No tallying is needed */
+ var->var->interface_type = NULL;
  break;
   }
+  break;
 
-  struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_pointer);
-  val->pointer = rzalloc(b, struct vtn_pointer);
-  val->pointer->type = type;
-  val->pointer->mode = mode;
+   case vtn_variable_mode_input:
+   case vtn_variable_mode_output: {
+  /* In order to know whether or not we're a per-vertex inout, we need
+   * the patch qualifier.  This means walking the variable decorations
+   * early before we actually create any variables.  Not a big deal.
+   *
+   * GLSLang really likes to place decorations in the most interior
+   * thing it possibly can.  In particular, if you have a struct, it
+   * will place the patch decorations on the struct members.  This
+   * should be handled by the variable splitting below just fine.
+   *
+   * If you have an array-of-struct, things get even more weird as it
+   * will place the patch decorations on the struct even though it's
+   * inside an array and some of the members being patch and others not
+   * makes no sense whatsoever.  Since the only sensible thing is for
+   * it to be all or nothing, we'll call it patch if any of the members
+   * are declared patch.
+   */
+  var->patch = false;
+