Re: [Mesa-dev] [PATCH v2 1/3] glsl: add glsl_external_mode() helper

[Timothy Arceri]

On 17/05/18 15:23, Timothy Arceri wrote:

On 17/05/18 14:59, Marek Olšák wrote:
On Thu, May 17, 2018 at 12:50 AM, Timothy Arceri 
> wrote:




    On 17/05/18 14:36, Marek Olšák wrote:

    On Wed, May 16, 2018 at 11:01 PM, Timothy Arceri
    
    >>
    wrote:



     On 17/05/18 10:59, Marek Olšák wrote:

         On Sat, May 12, 2018 at 12:49 AM, Timothy Arceri
         
    >
          

[Mesa-dev] [PATCH v2] android: enable VK_ANDROID_native_buffer

[Tapani Pälli]

Patch changes entrypoints generator to not skip this extension even
though it is set as disabled in the xml. We also need compilation
flag VK_USE_PLATFORM_ANDROID_KHR to be enabled.

It looks like this extension got disabled in commit 69f447553c.

v2: just remove the whole 'supported' attrib check + remove
vk_icd.h compilation fix (fix in VulkanHeaders instead)

Signed-off-by: Tapani Pälli 
---
 Android.common.mk   | 1 +
 src/intel/vulkan/anv_entrypoints_gen.py | 3 ---
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/Android.common.mk b/Android.common.mk
index e8aed48c31..999e17789b 100644
--- a/Android.common.mk
+++ b/Android.common.mk
@@ -73,6 +73,7 @@ LOCAL_CFLAGS += \
-DHAVE_ENDIAN_H \
-DHAVE_ZLIB \
-DMAJOR_IN_SYSMACROS \
+   -DVK_USE_PLATFORM_ANDROID_KHR \
-fvisibility=hidden \
-Wno-sign-compare
 
diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index d603ac1b20..230671d36a 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -495,9 +495,6 @@ def get_entrypoints(doc, entrypoints_to_defines, 
start_index):
 if ext_name not in supported_exts:
 continue
 
-if extension.attrib['supported'] != 'vulkan':
-continue
-
 ext = supported_exts[ext_name]
 ext.type = extension.attrib['type']
 
-- 
2.14.3

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Re: [Mesa-dev] [PATCH v2 1/3] glsl: add glsl_external_mode() helper

[Timothy Arceri]

On 17/05/18 14:59, Marek Olšák wrote:
On Thu, May 17, 2018 at 12:50 AM, Timothy Arceri > wrote:




On 17/05/18 14:36, Marek Olšák wrote:

On Wed, May 16, 2018 at 11:01 PM, Timothy Arceri

>>
wrote:



     On 17/05/18 10:59, Marek Olšák wrote:

         On Sat, May 12, 2018 at 12:49 AM, Timothy Arceri
         
>
          

Re: [Mesa-dev] [PATCH v2 1/3] glsl: add glsl_external_mode() helper

[Marek Olšák]

On Thu, May 17, 2018 at 12:50 AM, Timothy Arceri 
wrote:

>
>
> On 17/05/18 14:36, Marek Olšák wrote:
>
>> On Wed, May 16, 2018 at 11:01 PM, Timothy Arceri > > wrote:
>>
>>
>>
>> On 17/05/18 10:59, Marek Olšák wrote:
>>
>> On Sat, May 12, 2018 at 12:49 AM, Timothy Arceri
>> 
>> >>
>>
>> wrote:
>>
>>  This allows us to get the variable mode as specified by the
>> GLSL
>>  spec. We will use this in the following patch.
>>  ---
>>src/compiler/glsl/ast_to_hir.cpp | 73
>> 
>>1 file changed, 73 insertions(+)
>>
>>  diff --git a/src/compiler/glsl/ast_to_hir.cpp
>>  b/src/compiler/glsl/ast_to_hir.cpp
>>  index 3bf581571e2..a7a9ac80769 100644
>>  --- a/src/compiler/glsl/ast_to_hir.cpp
>>  +++ b/src/compiler/glsl/ast_to_hir.cpp
>>  @@ -4175,6 +4175,79 @@
>> apply_type_qualifier_to_variable(const struct
>>  ast_type_qualifier *qual,
>>   apply_image_qualifier_to_variable(qual, var, state,
>> loc);
>>}
>>
>>  +/**
>>  + * Get the GLSL mode specified in for system values (if
>> any).
>>  + */
>>  +static enum ir_variable_mode
>>  +glsl_external_mode(enum ir_variable_mode internal_mode,
>>  gl_shader_stage stage,
>>  +   unsigned slot) {
>>  +   if (internal_mode == ir_var_system_value) {
>>  +  switch (slot) {
>>  +  case SYSTEM_VALUE_SUBGROUP_SIZE:
>>  + return ir_var_uniform;
>>  +  case SYSTEM_VALUE_PRIMITIVE_ID:
>>  + if (stage == MESA_SHADER_GEOMETRY) {
>>  +return ir_var_shader_out;
>>
>>
>> System values are always inputs. This one is gl_PrimitiveIDIn.
>>
>>  + } else {
>>  +return ir_var_shader_in;
>>  + }
>>  +  case SYSTEM_VALUE_TESS_LEVEL_OUTER:
>>  +  case SYSTEM_VALUE_TESS_LEVEL_INNER:
>>  + if (stage == MESA_SHADER_TESS_CTRL) {
>>  +return ir_var_shader_out;
>>
>>
>> System values are always inputs, i.e. TESS_CTRL isn't allowed
>> here.
>>
>>
>> Hmm yeah your right I seem to have confused myself here a bit.
>> However SYSTEM_VALUE_SUBGROUP_SIZE seems to be the odd one out in
>> that its a uniform.
>>
>>
>> Why is it uniform?
>>
>
> From ARB_shader_ballot:
>
>
> (Add to the list of built-in uniform variable declaration)
>
> uniform uint  gl_SubGroupSizeARB;
>

I think it means that gl_SubGroupSizeARB is a compile-time constant. It
probably shouldn't be a system value.

Marek
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Re: [Mesa-dev] [PATCH v2 1/3] glsl: add glsl_external_mode() helper

[Timothy Arceri]

On 17/05/18 14:36, Marek Olšák wrote:
On Wed, May 16, 2018 at 11:01 PM, Timothy Arceri > wrote:




On 17/05/18 10:59, Marek Olšák wrote:

On Sat, May 12, 2018 at 12:49 AM, Timothy Arceri

>>
wrote:

     This allows us to get the variable mode as specified by the
GLSL
     spec. We will use this in the following patch.
     ---
       src/compiler/glsl/ast_to_hir.cpp | 73

       1 file changed, 73 insertions(+)

     diff --git a/src/compiler/glsl/ast_to_hir.cpp
     b/src/compiler/glsl/ast_to_hir.cpp
     index 3bf581571e2..a7a9ac80769 100644
     --- a/src/compiler/glsl/ast_to_hir.cpp
     +++ b/src/compiler/glsl/ast_to_hir.cpp
     @@ -4175,6 +4175,79 @@
apply_type_qualifier_to_variable(const struct
     ast_type_qualifier *qual,
          apply_image_qualifier_to_variable(qual, var, state, loc);
       }

     +/**
     + * Get the GLSL mode specified in for system values (if any).
     + */
     +static enum ir_variable_mode
     +glsl_external_mode(enum ir_variable_mode internal_mode,
     gl_shader_stage stage,
     +                   unsigned slot) {
     +   if (internal_mode == ir_var_system_value) {
     +      switch (slot) {
     +      case SYSTEM_VALUE_SUBGROUP_SIZE:
     +         return ir_var_uniform;
     +      case SYSTEM_VALUE_PRIMITIVE_ID:
     +         if (stage == MESA_SHADER_GEOMETRY) {
     +            return ir_var_shader_out;


System values are always inputs. This one is gl_PrimitiveIDIn.

     +         } else {
     +            return ir_var_shader_in;
     +         }
     +      case SYSTEM_VALUE_TESS_LEVEL_OUTER:
     +      case SYSTEM_VALUE_TESS_LEVEL_INNER:
     +         if (stage == MESA_SHADER_TESS_CTRL) {
     +            return ir_var_shader_out;


System values are always inputs, i.e. TESS_CTRL isn't allowed here.


Hmm yeah your right I seem to have confused myself here a bit.
However SYSTEM_VALUE_SUBGROUP_SIZE seems to be the odd one out in
that its a uniform.


Why is it uniform?


From ARB_shader_ballot:


(Add to the list of built-in uniform variable declaration)

uniform uint  gl_SubGroupSizeARB;



Marek

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Re: [Mesa-dev] [PATCH 2/2] glsl: allow linking ES shaders with desktop shaders in desktop GL

[Timothy Arceri]

On 17/05/18 14:23, Ilia Mirkin wrote:

Was this trace taken with mesa? Looks like the app was subjected to
adverse conditions...


Here is a better trace using mesa master:

https://drive.google.com/open?id=1pws2OfCMHBL8QkOZKoVp1NbtgD9zPHh6



60876 glCreateShader(type = GL_VERTEX_SHADER) = 5
60877 glShaderSource(shader = 5, count = 1, string = &"#version 100

uniform mat4 uClipFromEyeMatrix;
uniform mat4 uStartFromModelMatrix;
uniform mat4 uEyeFromStartMatrix;
uniform mat4 uHeadFromStartMatrix;
attribute vec3 aVertex;
attribute vec2 aTexCoords;
varying vec2 vTexCoords;

void main(void) {
   vTexCoords = aTexCoords;
   gl_Position = uClipFromEyeMatrix * uEyeFromStartMatrix *
   uStartFromModelMatrix * vec4(aVertex, 1.);
}
", length = NULL)
60878 glCompileShader(shader = 5)
60879 glGetShaderiv(shader = 5, pname = GL_COMPILE_STATUS, params = &0)
60880 glGetShaderInfoLog(shader = 5, bufSize = 2047, length = NULL,
infoLog = "0:1(10): error: GLSL ES 1.10 is not supported. Supported
versions are: 1.10, 1.20, 1.30, 1.40, 1.50, 3.30, 1.00 ES, and 3.00 ES
")
60881 glDeleteShader(shader = 5)

Dunno where GLSL ES 1.10 came from, but that's not even a thing. Nor
is it requested... perhaps some kind of override going wrong?

Anyways, it does seem to try to link version 100 + version 110
together later on. But perhaps that only ends up happening because
compiling the ES shader fails (from the application's standpoint).

   -ilia

On Thu, May 17, 2018 at 12:12 AM, Timothy Arceri  wrote:



On 17/05/18 10:55, Ilia Mirkin wrote:


ES has all kinds of additional linking rules. I suspect they'll break
down if some of the shaders are ES and some are not-ES.

This all does sound very odd -- what did you see in practice?



Here is a trace is you want to have a look at the various isses for
yourself:

https://drive.google.com/open?id=16z5udwUFUmCbg9kEyO741ydXzgRLB7kK




On Wed, May 16, 2018 at 3:04 AM, Timothy Arceri 
wrote:


In GLES shader versions must match but there is nothing
in the ARB_ES*_compatibility specs that say they must match.

This fixes some compilation errors in Google Earth VR.
---
   src/compiler/glsl/linker.cpp | 6 --
   1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index f060c5316fa..2b7ee0ad5a6 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -83,6 +83,7 @@
   #include "builtin_functions.h"
   #include "shader_cache.h"

+#include "main/context.h"
   #include "main/imports.h"
   #include "main/shaderobj.h"
   #include "main/enums.h"
@@ -4799,7 +4800,8 @@ link_shaders(struct gl_context *ctx, struct
gl_shader_program *prog)
 min_version = MIN2(min_version, prog->Shaders[i]->Version);
 max_version = MAX2(max_version, prog->Shaders[i]->Version);

-  if (prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
+  if (!_mesa_is_desktop_gl(ctx) &&
+  prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
linker_error(prog, "all shaders must use same shading "
 "language version\n");
goto done;
@@ -4817,7 +4819,7 @@ link_shaders(struct gl_context *ctx, struct
gl_shader_program *prog)
  /* In desktop GLSL, different shader versions may be linked
together.  In
   * GLSL ES, all shader versions must be the same.
   */
-   if (prog->Shaders[0]->IsES && min_version != max_version) {
+   if (!_mesa_is_desktop_gl(ctx) && min_version != max_version) {
 linker_error(prog, "all shaders must use same shading "
  "language version\n");
 goto done;
--
2.17.0

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Re: [Mesa-dev] [PATCH 9.5/17] squash! i965/miptree: Unify aux buffer allocation

[Pohjolainen, Topi]

On Wed, May 16, 2018 at 09:33:34AM -0700, Nanley Chery wrote:
> On Wed, May 16, 2018 at 09:11:38AM +0300, Pohjolainen, Topi wrote:
> > On Wed, May 09, 2018 at 10:47:24AM -0700, Nanley Chery wrote:
> > > v2: Inline the switch statement (Jason)
> > > 
> > > Reviewed-by: Jason Ekstrand 
> > > ---
> > >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 90 ---
> > >  1 file changed, 38 insertions(+), 52 deletions(-)
> > > 
> > > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> > > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > index f78b862a702..b5d7d691ecc 100644
> > > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > @@ -1777,30 +1777,37 @@ intel_miptree_level_enable_hiz(struct brw_context 
> > > *brw,
> > >  }
> > >  
> > >  
> > > -/* Returns true iff all params are successfully filled. */
> > > -static bool
> > > -get_aux_buf_params(const struct brw_context *brw,
> > > -   const struct intel_mipmap_tree *mt,
> > > -   enum isl_aux_state *initial_state,
> > > -   uint8_t *memset_value,
> > > -   struct isl_surf *aux_surf)
> > > +/**
> > > + * Allocate the initial aux surface for a miptree based on mt->aux_usage
> > > + *
> > > + * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
> > > + * create the auxiliary surfaces up-front.  CCS_D, on the other hand, 
> > > can only
> > > + * compress clear color so we wait until an actual fast-clear to 
> > > allocate it.
> > > + */
> > > +bool
> > > +intel_miptree_alloc_aux(struct brw_context *brw,
> > > +struct intel_mipmap_tree *mt)
> > >  {
> > > -   assert(initial_state && memset_value && aux_surf);
> > > +   assert(mt->aux_buf == NULL);
> > > +
> > > +   /* Get the aux buf allocation parameters for this miptree. */
> > > +   enum isl_aux_state initial_state;
> > > +   uint8_t memset_value;
> > > +   struct isl_surf aux_surf;
> > > +   bool aux_surf_ok;
> > >  
> > > switch (mt->aux_usage) {
> > > case ISL_AUX_USAGE_NONE:
> > > -  aux_surf->size = 0;
> > > -  return true;
> > > +  aux_surf.size = 0;
> > > +  aux_surf_ok = true;
> > > +  break;
> > > case ISL_AUX_USAGE_HIZ:
> > >assert(!_mesa_is_format_color_format(mt->format));
> > >  
> > > -  *initial_state = ISL_AUX_STATE_AUX_INVALID;
> > > -  {
> > > - MAYBE_UNUSED bool ok =
> > > -isl_surf_get_hiz_surf(>isl_dev, >surf, aux_surf);
> > > - assert(ok);
> > > -  }
> > > -  return true;
> > > +  initial_state = ISL_AUX_STATE_AUX_INVALID;
> > > +  aux_surf_ok = isl_surf_get_hiz_surf(>isl_dev, >surf, 
> > > _surf);
> > > +  assert(aux_surf_ok);
> > > +  break;
> > > case ISL_AUX_USAGE_MCS:
> > >assert(_mesa_is_format_color_format(mt->format));
> > >assert(brw->screen->devinfo.gen >= 7); /* MCS only used on Gen7+ */
> > > @@ -1817,14 +1824,11 @@ get_aux_buf_params(const struct brw_context *brw,
> > > * Note: the clear value for MCS buffers is all 1's, so we memset 
> > > to
> > > * 0xff.
> > > */
> > > -  *initial_state = ISL_AUX_STATE_CLEAR;
> > > -  *memset_value = 0xFF;
> > > -  {
> > > - MAYBE_UNUSED bool ok =
> > > -isl_surf_get_mcs_surf(>isl_dev, >surf, aux_surf);
> > > - assert(ok);
> > > -  }
> > > -  return true;
> > > +  initial_state = ISL_AUX_STATE_CLEAR;
> > > +  memset_value = 0xFF;
> > > +  aux_surf_ok = isl_surf_get_mcs_surf(>isl_dev, >surf, 
> > > _surf);
> > > +  assert(aux_surf_ok);
> > > +  break;
> > > case ISL_AUX_USAGE_CCS_D:
> > > case ISL_AUX_USAGE_CCS_E:
> > >assert(_mesa_is_format_color_format(mt->format));
> > > @@ -1839,36 +1843,18 @@ get_aux_buf_params(const struct brw_context *brw,
> > > * A CCS value of 0 indicates that the corresponding block is in 
> > > the
> > > * pass-through state which is what we want.
> > > *
> > > -   * For CCS_D, do the same thing. On gen9+, this avoids having any 
> > > undefined
> > > -   * bits in the aux buffer.
> > > +   * For CCS_D, do the same thing. On gen9+, this avoids having any
> > > +   * undefined bits in the aux buffer.
> > > */
> > > -  *initial_state = ISL_AUX_STATE_PASS_THROUGH;
> > > -  *memset_value = 0;
> > > -  return isl_surf_get_ccs_surf(>isl_dev, >surf, aux_surf, 
> > > 0);
> > > +  initial_state = ISL_AUX_STATE_PASS_THROUGH;
> > > +  memset_value = 0;
> > > +  aux_surf_ok =
> > > + isl_surf_get_ccs_surf(>isl_dev, >surf, _surf, 0);
> > 
> > Should we assert here also?
> > 
> >  assert(aux_surf_ok);
> > 
> 
> We can't at the moment. One example that would cause
> isl_surf_get_ccs_surf() to return false is where we're on gen8 and we
> attempt to fast-clear level 0 of a 3D texture.
> 
> > > +  

Re: [Mesa-dev] [PATCH v2 1/3] glsl: add glsl_external_mode() helper

[Marek Olšák]

On Wed, May 16, 2018 at 11:01 PM, Timothy Arceri 
wrote:

>
>
> On 17/05/18 10:59, Marek Olšák wrote:
>
> On Sat, May 12, 2018 at 12:49 AM, Timothy Arceri > > wrote:
>>
>> This allows us to get the variable mode as specified by the GLSL
>> spec. We will use this in the following patch.
>> ---
>>   src/compiler/glsl/ast_to_hir.cpp | 73
>> 
>>   1 file changed, 73 insertions(+)
>>
>> diff --git a/src/compiler/glsl/ast_to_hir.cpp
>> b/src/compiler/glsl/ast_to_hir.cpp
>> index 3bf581571e2..a7a9ac80769 100644
>> --- a/src/compiler/glsl/ast_to_hir.cpp
>> +++ b/src/compiler/glsl/ast_to_hir.cpp
>> @@ -4175,6 +4175,79 @@ apply_type_qualifier_to_variable(const struct
>> ast_type_qualifier *qual,
>>  apply_image_qualifier_to_variable(qual, var, state, loc);
>>   }
>>
>> +/**
>> + * Get the GLSL mode specified in for system values (if any).
>> + */
>> +static enum ir_variable_mode
>> +glsl_external_mode(enum ir_variable_mode internal_mode,
>> gl_shader_stage stage,
>> +   unsigned slot) {
>> +   if (internal_mode == ir_var_system_value) {
>> +  switch (slot) {
>> +  case SYSTEM_VALUE_SUBGROUP_SIZE:
>> + return ir_var_uniform;
>> +  case SYSTEM_VALUE_PRIMITIVE_ID:
>> + if (stage == MESA_SHADER_GEOMETRY) {
>> +return ir_var_shader_out;
>>
>>
>> System values are always inputs. This one is gl_PrimitiveIDIn.
>>
>> + } else {
>> +return ir_var_shader_in;
>> + }
>> +  case SYSTEM_VALUE_TESS_LEVEL_OUTER:
>> +  case SYSTEM_VALUE_TESS_LEVEL_INNER:
>> + if (stage == MESA_SHADER_TESS_CTRL) {
>> +return ir_var_shader_out;
>>
>>
>> System values are always inputs, i.e. TESS_CTRL isn't allowed here.
>>
>
> Hmm yeah your right I seem to have confused myself here a bit. However
> SYSTEM_VALUE_SUBGROUP_SIZE seems to be the odd one out in that its a
> uniform.
>

Why is it uniform?

Marek
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Re: [Mesa-dev] [PATCH v2 3/5] st/mesa: add support for ARB_sample_locations

[Marek Olšák]

For the first 3 patches:

Reviewed-by: Marek Olšák 

You can also update relnotes in patch 5.

Marek

On Thu, May 10, 2018 at 12:28 PM, Rhys Perry 
wrote:

> Signed-off-by: Rhys Perry 
> ---
>  src/mesa/state_tracker/st_atom.h   |  2 +-
>  src/mesa/state_tracker/st_atom_list.h  |  2 +-
>  src/mesa/state_tracker/st_atom_msaa.c  | 77
> +-
>  src/mesa/state_tracker/st_cb_msaa.c| 27 
>  src/mesa/state_tracker/st_context.c|  7 ++--
>  src/mesa/state_tracker/st_context.h|  6 +++
>  src/mesa/state_tracker/st_extensions.c |  1 +
>  7 files changed, 115 insertions(+), 7 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_atom.h b/src/mesa/state_tracker/st_
> atom.h
> index 2567ad30df..96e128d38c 100644
> --- a/src/mesa/state_tracker/st_atom.h
> +++ b/src/mesa/state_tracker/st_atom.h
> @@ -86,7 +86,7 @@ enum {
>   ST_NEW_CS_SAMPLERS)
>
>  #define ST_NEW_FRAMEBUFFER  (ST_NEW_FB_STATE | \
> - ST_NEW_SAMPLE_MASK | \
> + ST_NEW_SAMPLE_STATE | \
>   ST_NEW_SAMPLE_SHADING)
>
>  #define ST_NEW_VERTEX_PROGRAM(st, p) (p->affected_states | \
> diff --git a/src/mesa/state_tracker/st_atom_list.h
> b/src/mesa/state_tracker/st_atom_list.h
> index 5391d4710c..e1aebc91e7 100644
> --- a/src/mesa/state_tracker/st_atom_list.h
> +++ b/src/mesa/state_tracker/st_atom_list.h
> @@ -34,7 +34,7 @@ ST_STATE(ST_NEW_FS_IMAGES, st_bind_fs_images)
>  ST_STATE(ST_NEW_FB_STATE, st_update_framebuffer_state) /* depends on
> update_*_texture and bind_*_images */
>  ST_STATE(ST_NEW_BLEND, st_update_blend) /* depends on
> update_framebuffer_state */
>  ST_STATE(ST_NEW_RASTERIZER, st_update_rasterizer) /* depends on
> update_framebuffer_state */
> -ST_STATE(ST_NEW_SAMPLE_MASK, st_update_sample_mask) /* depends on
> update_framebuffer_state */
> +ST_STATE(ST_NEW_SAMPLE_STATE, st_update_sample_state) /* depends on
> update_framebuffer_state */
>  ST_STATE(ST_NEW_SAMPLE_SHADING, st_update_sample_shading)
>  ST_STATE(ST_NEW_SCISSOR, st_update_scissor) /* depends on
> update_framebuffer_state */
>  ST_STATE(ST_NEW_VIEWPORT, st_update_viewport) /* depends on
> update_framebuffer_state */
> diff --git a/src/mesa/state_tracker/st_atom_msaa.c
> b/src/mesa/state_tracker/st_atom_msaa.c
> index 556c7c5889..c6affec552 100644
> --- a/src/mesa/state_tracker/st_atom_msaa.c
> +++ b/src/mesa/state_tracker/st_atom_msaa.c
> @@ -33,13 +33,84 @@
>  #include "st_program.h"
>
>  #include "cso_cache/cso_context.h"
> +#include "util/u_framebuffer.h"
>  #include "main/framebuffer.h"
>
>
> -/* Update the sample mask for MSAA.
> +/**
> + * Update the sample locations
> + */
> +static void
> +update_sample_locations(struct st_context *st)
> +{
> +   struct gl_framebuffer *fb = st->ctx->DrawBuffer;
> +
> +   if (!st->ctx->Extensions.ARB_sample_locations)
> +  return;
> +
> +   if (fb->ProgrammableSampleLocations) {
> +  unsigned grid_width, grid_height, size, pixel, sample_index;
> +  unsigned samples = st->state.fb_num_samples;
> +  bool sample_location_pixel_grid = fb->SampleLocationPixelGrid;
> +  uint8_t locations[
> + PIPE_MAX_SAMPLE_LOCATION_GRID_SIZE *
> + PIPE_MAX_SAMPLE_LOCATION_GRID_SIZE * 32];
> +
> +  st->pipe->screen->get_sample_pixel_grid(
> + st->pipe->screen, samples, _width, _height);
> +  size = grid_width * grid_height * samples;
> +
> +  /**
> +   * when a dimension is greater than MAX_SAMPLE_LOCATION_GRID_SIZE,
> +   * st->ctx->Driver.GetSamplePixelGrid() returns 1 for both
> dimensions.
> +   */
> +  if (grid_width > MAX_SAMPLE_LOCATION_GRID_SIZE ||
> +  grid_height > MAX_SAMPLE_LOCATION_GRID_SIZE)
> + sample_location_pixel_grid = false;
> +
> +  for (pixel = 0; pixel < grid_width * grid_height; pixel++) {
> + for (sample_index = 0; sample_index < samples; sample_index++) {
> +int table_index = sample_index;
> +float x = 0.5f, y = 0.5f;
> +uint8_t loc;
> +if (sample_location_pixel_grid)
> +   table_index = pixel * samples + sample_index;
> +if (fb->SampleLocationTable) {
> +   x = fb->SampleLocationTable[table_index*2];
> +   y = fb->SampleLocationTable[table_index*2+1];
> +}
> +if (st->state.fb_orientation == Y_0_BOTTOM)
> +   y = 1.0 - y;
> +
> +loc = roundf(CLAMP(x * 16.0f, 0.0f, 15.0f));
> +loc |= (int)roundf(CLAMP(y * 16.0f, 0.0f, 15.0f)) << 4;
> +locations[pixel * samples + sample_index] = loc;
> + }
> +  }
> +
> +  util_sample_locations_flip_y(
> + st->pipe->screen, st->state.fb_height, samples, locations);
> +
> +  if (!st->state.enable_sample_locations ||
> +  

Re: [Mesa-dev] [PATCH 2/2] glsl: allow linking ES shaders with desktop shaders in desktop GL

[Timothy Arceri]

On 17/05/18 14:23, Ilia Mirkin wrote:

Was this trace taken with mesa? Looks like the app was subjected to
adverse conditions...


Oh right I need a fresh trace the GLSL ES 1.10 is not supported issue 
was cause by a dodgy change I made.




60876 glCreateShader(type = GL_VERTEX_SHADER) = 5
60877 glShaderSource(shader = 5, count = 1, string = &"#version 100

uniform mat4 uClipFromEyeMatrix;
uniform mat4 uStartFromModelMatrix;
uniform mat4 uEyeFromStartMatrix;
uniform mat4 uHeadFromStartMatrix;
attribute vec3 aVertex;
attribute vec2 aTexCoords;
varying vec2 vTexCoords;

void main(void) {
   vTexCoords = aTexCoords;
   gl_Position = uClipFromEyeMatrix * uEyeFromStartMatrix *
   uStartFromModelMatrix * vec4(aVertex, 1.);
}
", length = NULL)
60878 glCompileShader(shader = 5)
60879 glGetShaderiv(shader = 5, pname = GL_COMPILE_STATUS, params = &0)
60880 glGetShaderInfoLog(shader = 5, bufSize = 2047, length = NULL,
infoLog = "0:1(10): error: GLSL ES 1.10 is not supported. Supported
versions are: 1.10, 1.20, 1.30, 1.40, 1.50, 3.30, 1.00 ES, and 3.00 ES
")
60881 glDeleteShader(shader = 5)

Dunno where GLSL ES 1.10 came from, but that's not even a thing. Nor
is it requested... perhaps some kind of override going wrong?

Anyways, it does seem to try to link version 100 + version 110
together later on. But perhaps that only ends up happening because
compiling the ES shader fails (from the application's standpoint)

   -ilia

On Thu, May 17, 2018 at 12:12 AM, Timothy Arceri  wrote:



On 17/05/18 10:55, Ilia Mirkin wrote:


ES has all kinds of additional linking rules. I suspect they'll break
down if some of the shaders are ES and some are not-ES.

This all does sound very odd -- what did you see in practice?



Here is a trace is you want to have a look at the various isses for
yourself:

https://drive.google.com/open?id=16z5udwUFUmCbg9kEyO741ydXzgRLB7kK




On Wed, May 16, 2018 at 3:04 AM, Timothy Arceri 
wrote:


In GLES shader versions must match but there is nothing
in the ARB_ES*_compatibility specs that say they must match.

This fixes some compilation errors in Google Earth VR.
---
   src/compiler/glsl/linker.cpp | 6 --
   1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index f060c5316fa..2b7ee0ad5a6 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -83,6 +83,7 @@
   #include "builtin_functions.h"
   #include "shader_cache.h"

+#include "main/context.h"
   #include "main/imports.h"
   #include "main/shaderobj.h"
   #include "main/enums.h"
@@ -4799,7 +4800,8 @@ link_shaders(struct gl_context *ctx, struct
gl_shader_program *prog)
 min_version = MIN2(min_version, prog->Shaders[i]->Version);
 max_version = MAX2(max_version, prog->Shaders[i]->Version);

-  if (prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
+  if (!_mesa_is_desktop_gl(ctx) &&
+  prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
linker_error(prog, "all shaders must use same shading "
 "language version\n");
goto done;
@@ -4817,7 +4819,7 @@ link_shaders(struct gl_context *ctx, struct
gl_shader_program *prog)
  /* In desktop GLSL, different shader versions may be linked
together.  In
   * GLSL ES, all shader versions must be the same.
   */
-   if (prog->Shaders[0]->IsES && min_version != max_version) {
+   if (!_mesa_is_desktop_gl(ctx) && min_version != max_version) {
 linker_error(prog, "all shaders must use same shading "
  "language version\n");
 goto done;
--
2.17.0

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Re: [Mesa-dev] [PATCH 2/2] glsl: allow linking ES shaders with desktop shaders in desktop GL

[Ilia Mirkin]

Was this trace taken with mesa? Looks like the app was subjected to
adverse conditions...

60876 glCreateShader(type = GL_VERTEX_SHADER) = 5
60877 glShaderSource(shader = 5, count = 1, string = &"#version 100

uniform mat4 uClipFromEyeMatrix;
uniform mat4 uStartFromModelMatrix;
uniform mat4 uEyeFromStartMatrix;
uniform mat4 uHeadFromStartMatrix;
attribute vec3 aVertex;
attribute vec2 aTexCoords;
varying vec2 vTexCoords;

void main(void) {
  vTexCoords = aTexCoords;
  gl_Position = uClipFromEyeMatrix * uEyeFromStartMatrix *
  uStartFromModelMatrix * vec4(aVertex, 1.);
}
", length = NULL)
60878 glCompileShader(shader = 5)
60879 glGetShaderiv(shader = 5, pname = GL_COMPILE_STATUS, params = &0)
60880 glGetShaderInfoLog(shader = 5, bufSize = 2047, length = NULL,
infoLog = "0:1(10): error: GLSL ES 1.10 is not supported. Supported
versions are: 1.10, 1.20, 1.30, 1.40, 1.50, 3.30, 1.00 ES, and 3.00 ES
")
60881 glDeleteShader(shader = 5)

Dunno where GLSL ES 1.10 came from, but that's not even a thing. Nor
is it requested... perhaps some kind of override going wrong?

Anyways, it does seem to try to link version 100 + version 110
together later on. But perhaps that only ends up happening because
compiling the ES shader fails (from the application's standpoint).

  -ilia

On Thu, May 17, 2018 at 12:12 AM, Timothy Arceri  wrote:
>
>
> On 17/05/18 10:55, Ilia Mirkin wrote:
>>
>> ES has all kinds of additional linking rules. I suspect they'll break
>> down if some of the shaders are ES and some are not-ES.
>>
>> This all does sound very odd -- what did you see in practice?
>
>
> Here is a trace is you want to have a look at the various isses for
> yourself:
>
> https://drive.google.com/open?id=16z5udwUFUmCbg9kEyO741ydXzgRLB7kK
>
>
>>
>> On Wed, May 16, 2018 at 3:04 AM, Timothy Arceri 
>> wrote:
>>>
>>> In GLES shader versions must match but there is nothing
>>> in the ARB_ES*_compatibility specs that say they must match.
>>>
>>> This fixes some compilation errors in Google Earth VR.
>>> ---
>>>   src/compiler/glsl/linker.cpp | 6 --
>>>   1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
>>> index f060c5316fa..2b7ee0ad5a6 100644
>>> --- a/src/compiler/glsl/linker.cpp
>>> +++ b/src/compiler/glsl/linker.cpp
>>> @@ -83,6 +83,7 @@
>>>   #include "builtin_functions.h"
>>>   #include "shader_cache.h"
>>>
>>> +#include "main/context.h"
>>>   #include "main/imports.h"
>>>   #include "main/shaderobj.h"
>>>   #include "main/enums.h"
>>> @@ -4799,7 +4800,8 @@ link_shaders(struct gl_context *ctx, struct
>>> gl_shader_program *prog)
>>> min_version = MIN2(min_version, prog->Shaders[i]->Version);
>>> max_version = MAX2(max_version, prog->Shaders[i]->Version);
>>>
>>> -  if (prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
>>> +  if (!_mesa_is_desktop_gl(ctx) &&
>>> +  prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
>>>linker_error(prog, "all shaders must use same shading "
>>> "language version\n");
>>>goto done;
>>> @@ -4817,7 +4819,7 @@ link_shaders(struct gl_context *ctx, struct
>>> gl_shader_program *prog)
>>>  /* In desktop GLSL, different shader versions may be linked
>>> together.  In
>>>   * GLSL ES, all shader versions must be the same.
>>>   */
>>> -   if (prog->Shaders[0]->IsES && min_version != max_version) {
>>> +   if (!_mesa_is_desktop_gl(ctx) && min_version != max_version) {
>>> linker_error(prog, "all shaders must use same shading "
>>>  "language version\n");
>>> goto done;
>>> --
>>> 2.17.0
>>>
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Re: [Mesa-dev] [PATCH 2/2] glsl: allow linking ES shaders with desktop shaders in desktop GL

[Timothy Arceri]

On 17/05/18 10:55, Ilia Mirkin wrote:

ES has all kinds of additional linking rules. I suspect they'll break
down if some of the shaders are ES and some are not-ES.

This all does sound very odd -- what did you see in practice?


Here is a trace is you want to have a look at the various isses for 
yourself:


https://drive.google.com/open?id=16z5udwUFUmCbg9kEyO741ydXzgRLB7kK



On Wed, May 16, 2018 at 3:04 AM, Timothy Arceri  wrote:

In GLES shader versions must match but there is nothing
in the ARB_ES*_compatibility specs that say they must match.

This fixes some compilation errors in Google Earth VR.
---
  src/compiler/glsl/linker.cpp | 6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index f060c5316fa..2b7ee0ad5a6 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -83,6 +83,7 @@
  #include "builtin_functions.h"
  #include "shader_cache.h"

+#include "main/context.h"
  #include "main/imports.h"
  #include "main/shaderobj.h"
  #include "main/enums.h"
@@ -4799,7 +4800,8 @@ link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
min_version = MIN2(min_version, prog->Shaders[i]->Version);
max_version = MAX2(max_version, prog->Shaders[i]->Version);

-  if (prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
+  if (!_mesa_is_desktop_gl(ctx) &&
+  prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
   linker_error(prog, "all shaders must use same shading "
"language version\n");
   goto done;
@@ -4817,7 +4819,7 @@ link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
 /* In desktop GLSL, different shader versions may be linked together.  In
  * GLSL ES, all shader versions must be the same.
  */
-   if (prog->Shaders[0]->IsES && min_version != max_version) {
+   if (!_mesa_is_desktop_gl(ctx) && min_version != max_version) {
linker_error(prog, "all shaders must use same shading "
 "language version\n");
goto done;
--
2.17.0

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[Mesa-dev] [Bug 78097] glUniform1ui and friends not supported by display lists

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=78097

Timothy Arceri  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #1 from Timothy Arceri  ---
Fixed by:

commit f71714022b2cd26bb1892e6a7f3d7308515f210e
Author: Timothy Arceri 
Date:   Thu May 10 13:42:16 2018 +1000

mesa: add glUniform*ui{v} support to display lists

Fixes: a017c7ecb7ae "mesa: display list support for uint uniforms"

Reviewed-by: Marek Olšák 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78097

Piglit test:

commit 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d
Author: Timothy Arceri 
Date:   Thu May 10 13:51:44 2018 +1000

gl-3.0: test glUniform*ui{v} functions are compiled into display lists

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78097

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Re: [Mesa-dev] [PATCH 2/2] glsl: allow linking ES shaders with desktop shaders in desktop GL

[Timothy Arceri]

On 17/05/18 10:55, Ilia Mirkin wrote:

ES has all kinds of additional linking rules. I suspect they'll break
down if some of the shaders are ES and some are not-ES.


Hmm looking closer there are indeed assumptions in the linker that all 
shaders are either ES or desktop. But I'm not sure that this change is 
an less valid. The shaders do seem to link successfully in the case I'm 
seeing at least.




This all does sound very odd -- what did you see in practice?


In practice I see the app request an OpenGL 3.2 compat profile then at 
least once link a GLSL ES 1.00 shader with a GLSL 1.10 shader.


Besides this issue and the issue in patch 1. There is also GLSL 1.10 
shaders that do the following:


const float t1 = 0.001;
const float y1 = 0.4;
const float t2 = 0.25;
const float y2 = 0.01;
const float b = log(y1 / y2) / (t2 - t1);
const float a = y2 / exp(-b * t2);

But using builtins when initialising constants werent allowed by the 
spec until 1.20. There seems to be other non shader issues with the app 
too so I'm loosing confidence in this app fast :(





On Wed, May 16, 2018 at 3:04 AM, Timothy Arceri  wrote:

In GLES shader versions must match but there is nothing
in the ARB_ES*_compatibility specs that say they must match.

This fixes some compilation errors in Google Earth VR.
---
  src/compiler/glsl/linker.cpp | 6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index f060c5316fa..2b7ee0ad5a6 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -83,6 +83,7 @@
  #include "builtin_functions.h"
  #include "shader_cache.h"

+#include "main/context.h"
  #include "main/imports.h"
  #include "main/shaderobj.h"
  #include "main/enums.h"
@@ -4799,7 +4800,8 @@ link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
min_version = MIN2(min_version, prog->Shaders[i]->Version);
max_version = MAX2(max_version, prog->Shaders[i]->Version);

-  if (prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
+  if (!_mesa_is_desktop_gl(ctx) &&
+  prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
   linker_error(prog, "all shaders must use same shading "
"language version\n");
   goto done;
@@ -4817,7 +4819,7 @@ link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
 /* In desktop GLSL, different shader versions may be linked together.  In
  * GLSL ES, all shader versions must be the same.
  */
-   if (prog->Shaders[0]->IsES && min_version != max_version) {
+   if (!_mesa_is_desktop_gl(ctx) && min_version != max_version) {
linker_error(prog, "all shaders must use same shading "
 "language version\n");
goto done;
--
2.17.0

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Re: [Mesa-dev] [PATCH v2 1/3] glsl: add glsl_external_mode() helper

[Timothy Arceri]

On 17/05/18 10:59, Marek Olšák wrote:
On Sat, May 12, 2018 at 12:49 AM, Timothy Arceri > wrote:


This allows us to get the variable mode as specified by the GLSL
spec. We will use this in the following patch.
---
  src/compiler/glsl/ast_to_hir.cpp | 73 
  1 file changed, 73 insertions(+)

diff --git a/src/compiler/glsl/ast_to_hir.cpp
b/src/compiler/glsl/ast_to_hir.cpp
index 3bf581571e2..a7a9ac80769 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -4175,6 +4175,79 @@ apply_type_qualifier_to_variable(const struct
ast_type_qualifier *qual,
     apply_image_qualifier_to_variable(qual, var, state, loc);
  }

+/**
+ * Get the GLSL mode specified in for system values (if any).
+ */
+static enum ir_variable_mode
+glsl_external_mode(enum ir_variable_mode internal_mode,
gl_shader_stage stage,
+                   unsigned slot) {
+   if (internal_mode == ir_var_system_value) {
+      switch (slot) {
+      case SYSTEM_VALUE_SUBGROUP_SIZE:
+         return ir_var_uniform;
+      case SYSTEM_VALUE_PRIMITIVE_ID:
+         if (stage == MESA_SHADER_GEOMETRY) {
+            return ir_var_shader_out;


System values are always inputs. This one is gl_PrimitiveIDIn.

+         } else {
+            return ir_var_shader_in;
+         }
+      case SYSTEM_VALUE_TESS_LEVEL_OUTER:
+      case SYSTEM_VALUE_TESS_LEVEL_INNER:
+         if (stage == MESA_SHADER_TESS_CTRL) {
+            return ir_var_shader_out;


System values are always inputs, i.e. TESS_CTRL isn't allowed here.


Hmm yeah your right I seem to have confused myself here a bit. However 
SYSTEM_VALUE_SUBGROUP_SIZE seems to be the odd one out in that its a 
uniform.




Marek


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Re: [Mesa-dev] [PATCH] amd: remove support for LLVM 4.0

[Dave Airlie]

On 17 May 2018 at 12:25, Marek Olšák  wrote:
> From: Marek Olšák 

LGTM,

Acked-by: Dave Airlie 
>
> It doesn't support GFX9.
> ---
>  .travis.yml   |   6 +-
>  configure.ac  |   4 +-
>  meson.build   |   4 +-
>  src/amd/common/ac_llvm_build.c| 282 +++---
>  src/amd/common/ac_llvm_helper.cpp |  12 -
>  src/amd/vulkan/radv_debug.c   |   8 +-
>  src/amd/vulkan/radv_device.c  |   9 +-
>  src/amd/vulkan/radv_nir_to_llvm.c |   2 +-
>  .../vulkan/winsys/amdgpu/radv_amdgpu_winsys.c |   7 -
>  src/gallium/drivers/radeonsi/si_get.c |   4 +-
>  src/gallium/drivers/radeonsi/si_pipe.c|   2 +-
>  .../drivers/radeonsi/si_shader_tgsi_setup.c   |   3 +-
>  src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |   7 -
>  13 files changed, 121 insertions(+), 229 deletions(-)
>
> diff --git a/.travis.yml b/.travis.yml
> index e0d6a827a6d..c8b68a66967 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -116,37 +116,37 @@ matrix:
>  - x11proto-xf86vidmode-dev
>  - libexpat1-dev
>  - libx11-xcb-dev
>  - libelf-dev
>  - libunwind8-dev
>  - env:
>  - LABEL="make Gallium Drivers RadeonSI"
>  - BUILD=make
>  - MAKEFLAGS="-j4"
>  - MAKE_CHECK_COMMAND="true"
> -- LLVM_VERSION=4.0
> +- LLVM_VERSION=5.0
>  - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
>  - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
>  - DRI_DRIVERS=""
>  - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
> --disable-nine --disable-xvmc --disable-vdpau --disable-va 
> --disable-omx-bellagio --disable-gallium-osmesa"
>  - GALLIUM_DRIVERS="radeonsi"
>  - VULKAN_DRIVERS=""
>  - LIBUNWIND_FLAGS="--enable-libunwind"
>addons:
>  apt:
>sources:
> -- llvm-toolchain-trusty-4.0
> +- llvm-toolchain-trusty-5.0
>packages:
>  # LLVM packaging is broken and misses these dependencies
>  - libedit-dev
>  # From sources above
> -- llvm-4.0-dev
> +- llvm-5.0-dev
>  # Common
>  - xz-utils
>  - x11proto-xf86vidmode-dev
>  - libexpat1-dev
>  - libx11-xcb-dev
>  - libelf-dev
>  - libunwind8-dev
>  - env:
>  - LABEL="make Gallium Drivers Other"
>  - BUILD=make
> diff --git a/configure.ac b/configure.ac
> index 30980151ee1..6b145f1cdb2 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -99,22 +99,22 @@ XDAMAGE_REQUIRED=1.1
>  XSHMFENCE_REQUIRED=1.1
>  XVMC_REQUIRED=1.0.6
>  PYTHON_MAKO_REQUIRED=0.8.0
>  LIBSENSORS_REQUIRED=4.0.0
>  ZLIB_REQUIRED=1.2.3
>
>  dnl LLVM versions
>  LLVM_REQUIRED_GALLIUM=3.3.0
>  LLVM_REQUIRED_OPENCL=3.9.0
>  LLVM_REQUIRED_R600=3.9.0
> -LLVM_REQUIRED_RADEONSI=4.0.0
> -LLVM_REQUIRED_RADV=4.0.0
> +LLVM_REQUIRED_RADEONSI=5.0.0
> +LLVM_REQUIRED_RADV=5.0.0
>  LLVM_REQUIRED_SWR=4.0.0
>
>  dnl Check for progs
>  AC_PROG_CPP
>  AC_PROG_CC
>  AC_PROG_CXX
>  dnl add this here, so the help for this environmnet variable is close to
>  dnl other CC/CXX flags related help
>  AC_ARG_VAR([CXX11_CXXFLAGS], [Compiler flag to enable C++11 support (only 
> needed if not
>enabled by default and different  from 
> -std=c++11)])
> diff --git a/meson.build b/meson.build
> index b8ebda9cdc7..2d0f78fcdce 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -1094,21 +1094,23 @@ if with_amd_vk or with_gallium_radeonsi or 
> with_gallium_r600
>endif
>  endif
>  if with_gallium_opencl
>llvm_modules += [
>  'all-targets', 'linker', 'coverage', 'instrumentation', 'ipo', 
> 'irreader',
>  'lto', 'option', 'objcarcopts', 'profiledata',
>]
># TODO: optional modules
>  endif
>
> -if with_amd_vk or with_gallium_radeonsi or with_gallium_swr
> +if with_amd_vk or with_gallium_radeonsi
> +  _llvm_version = '>= 5.0.0'
> +elif with_gallium_swr
>_llvm_version = '>= 4.0.0'
>  elif with_gallium_opencl or with_gallium_r600
>_llvm_version = '>= 3.9.0'
>  else
>_llvm_version = '>= 3.3.0'
>  endif
>
>  _llvm = get_option('llvm')
>  if _llvm == 'auto'
>dep_llvm = dependency(
> diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
> index 6f5f04496ee..36c1d62637b 100644
> --- a/src/amd/common/ac_llvm_build.c
> +++ b/src/amd/common/ac_llvm_build.c
> @@ -881,141 +881,105 @@ ac_build_buffer_store_dword(struct ac_llvm_context 
> *ctx,
> LLVMValueRef vdata,
> unsigned num_channels,
> LLVMValueRef voffset,
> LLVMValueRef soffset,
> unsigned 

[Mesa-dev] [PATCH] amd: remove support for LLVM 4.0

[Marek Olšák]

From: Marek Olšák 

It doesn't support GFX9.
---
 .travis.yml   |   6 +-
 configure.ac  |   4 +-
 meson.build   |   4 +-
 src/amd/common/ac_llvm_build.c| 282 +++---
 src/amd/common/ac_llvm_helper.cpp |  12 -
 src/amd/vulkan/radv_debug.c   |   8 +-
 src/amd/vulkan/radv_device.c  |   9 +-
 src/amd/vulkan/radv_nir_to_llvm.c |   2 +-
 .../vulkan/winsys/amdgpu/radv_amdgpu_winsys.c |   7 -
 src/gallium/drivers/radeonsi/si_get.c |   4 +-
 src/gallium/drivers/radeonsi/si_pipe.c|   2 +-
 .../drivers/radeonsi/si_shader_tgsi_setup.c   |   3 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |   7 -
 13 files changed, 121 insertions(+), 229 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index e0d6a827a6d..c8b68a66967 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -116,37 +116,37 @@ matrix:
 - x11proto-xf86vidmode-dev
 - libexpat1-dev
 - libx11-xcb-dev
 - libelf-dev
 - libunwind8-dev
 - env:
 - LABEL="make Gallium Drivers RadeonSI"
 - BUILD=make
 - MAKEFLAGS="-j4"
 - MAKE_CHECK_COMMAND="true"
-- LLVM_VERSION=4.0
+- LLVM_VERSION=5.0
 - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
 - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
 - DRI_DRIVERS=""
 - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
--disable-nine --disable-xvmc --disable-vdpau --disable-va 
--disable-omx-bellagio --disable-gallium-osmesa"
 - GALLIUM_DRIVERS="radeonsi"
 - VULKAN_DRIVERS=""
 - LIBUNWIND_FLAGS="--enable-libunwind"
   addons:
 apt:
   sources:
-- llvm-toolchain-trusty-4.0
+- llvm-toolchain-trusty-5.0
   packages:
 # LLVM packaging is broken and misses these dependencies
 - libedit-dev
 # From sources above
-- llvm-4.0-dev
+- llvm-5.0-dev
 # Common
 - xz-utils
 - x11proto-xf86vidmode-dev
 - libexpat1-dev
 - libx11-xcb-dev
 - libelf-dev
 - libunwind8-dev
 - env:
 - LABEL="make Gallium Drivers Other"
 - BUILD=make
diff --git a/configure.ac b/configure.ac
index 30980151ee1..6b145f1cdb2 100644
--- a/configure.ac
+++ b/configure.ac
@@ -99,22 +99,22 @@ XDAMAGE_REQUIRED=1.1
 XSHMFENCE_REQUIRED=1.1
 XVMC_REQUIRED=1.0.6
 PYTHON_MAKO_REQUIRED=0.8.0
 LIBSENSORS_REQUIRED=4.0.0
 ZLIB_REQUIRED=1.2.3
 
 dnl LLVM versions
 LLVM_REQUIRED_GALLIUM=3.3.0
 LLVM_REQUIRED_OPENCL=3.9.0
 LLVM_REQUIRED_R600=3.9.0
-LLVM_REQUIRED_RADEONSI=4.0.0
-LLVM_REQUIRED_RADV=4.0.0
+LLVM_REQUIRED_RADEONSI=5.0.0
+LLVM_REQUIRED_RADV=5.0.0
 LLVM_REQUIRED_SWR=4.0.0
 
 dnl Check for progs
 AC_PROG_CPP
 AC_PROG_CC
 AC_PROG_CXX
 dnl add this here, so the help for this environmnet variable is close to
 dnl other CC/CXX flags related help
 AC_ARG_VAR([CXX11_CXXFLAGS], [Compiler flag to enable C++11 support (only 
needed if not
   enabled by default and different  from 
-std=c++11)])
diff --git a/meson.build b/meson.build
index b8ebda9cdc7..2d0f78fcdce 100644
--- a/meson.build
+++ b/meson.build
@@ -1094,21 +1094,23 @@ if with_amd_vk or with_gallium_radeonsi or 
with_gallium_r600
   endif
 endif
 if with_gallium_opencl
   llvm_modules += [
 'all-targets', 'linker', 'coverage', 'instrumentation', 'ipo', 'irreader',
 'lto', 'option', 'objcarcopts', 'profiledata',
   ]
   # TODO: optional modules
 endif
 
-if with_amd_vk or with_gallium_radeonsi or with_gallium_swr
+if with_amd_vk or with_gallium_radeonsi
+  _llvm_version = '>= 5.0.0'
+elif with_gallium_swr
   _llvm_version = '>= 4.0.0'
 elif with_gallium_opencl or with_gallium_r600
   _llvm_version = '>= 3.9.0'
 else
   _llvm_version = '>= 3.3.0'
 endif
 
 _llvm = get_option('llvm')
 if _llvm == 'auto'
   dep_llvm = dependency(
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 6f5f04496ee..36c1d62637b 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -881,141 +881,105 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
LLVMValueRef vdata,
unsigned num_channels,
LLVMValueRef voffset,
LLVMValueRef soffset,
unsigned inst_offset,
bool glc,
bool slc,
bool writeonly_memory,
bool swizzle_enable_hint)
 {
-   static unsigned dfmt[] = {
-   V_008F0C_BUF_DATA_FORMAT_32,
-   V_008F0C_BUF_DATA_FORMAT_32_32,
-   V_008F0C_BUF_DATA_FORMAT_32_32_32,
- 

Re: [Mesa-dev] [PATCH] radeonsi: create .gitignore

[Marek Olšák]

Sure. Done.

Marek

On Wed, May 16, 2018 at 7:54 AM, Dieter Nützel  wrote:

> Thank you Marek,
>
> can someone (you) commit for me, then? ;-)
>
> Dieter
>
>
> Am 15.05.2018 18:35, schrieb Marek Olšák:
>
>> Reviewed-by: Marek Olšák 
>>
>> Marek
>>
>> On Tue, May 15, 2018 at 9:55 AM, Dieter Nützel 
>> wrote:
>>
>> Hello Marek,
>>>
>>> sorry I have some trouble with 'git send-email' (configuration)
>>>
>>> Command unknown: 'AUTH' at /usr/lib/git/git-send-email line 1455
>>>
>>> currently, so I send it this way.
>>>
>>> Dieter
>>>
>>
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[Mesa-dev] [PATCH 3/6] radeonsi: remove some old gfx 9.x registers

[Marek Olšák]

From: Marek Olšák 

Leftover from bring up.
---
 src/amd/common/gfx9d.h | 48 --
 1 file changed, 48 deletions(-)

diff --git a/src/amd/common/gfx9d.h b/src/amd/common/gfx9d.h
index 8c616451849..485fd7d0fed 100644
--- a/src/amd/common/gfx9d.h
+++ b/src/amd/common/gfx9d.h
@@ -1116,21 +1116,20 @@
 #define   C_030960_WD_SWITCH_ON_EOP   
0xFFEF
 #define   S_030960_EN_INST_OPT_BASIC(x)   
(((unsigned)(x) & 0x1) << 21)
 #define   G_030960_EN_INST_OPT_BASIC(x)   (((x) >> 
21) & 0x1)
 #define   C_030960_EN_INST_OPT_BASIC  
0xFFDF
 #define   S_030960_EN_INST_OPT_ADV(x) 
(((unsigned)(x) & 0x1) << 22)
 #define   G_030960_EN_INST_OPT_ADV(x) (((x) >> 
22) & 0x1)
 #define   C_030960_EN_INST_OPT_ADV
0xFFBF
 #define   S_030960_HW_USE_ONLY(x) 
(((unsigned)(x) & 0x1) << 23)
 #define   G_030960_HW_USE_ONLY(x) (((x) >> 
23) & 0x1)
 #define   C_030960_HW_USE_ONLY
0xFF7F
-#define R_030964_VGT_OBJECT_ID  
0x030964
 #define R_030968_VGT_INSTANCE_BASE_ID   
0x030968
 #define R_030A00_PA_SU_LINE_STIPPLE_VALUE   
0x030A00
 #define   S_030A00_LINE_STIPPLE_VALUE(x)  
(((unsigned)(x) & 0xFF) << 0)
 #define   G_030A00_LINE_STIPPLE_VALUE(x)  (((x) >> 
0) & 0xFF)
 #define   C_030A00_LINE_STIPPLE_VALUE 
0xFF00
 #define R_030A04_PA_SC_LINE_STIPPLE_STATE   
0x030A04
 #define   S_030A04_CURRENT_PTR(x) 
(((unsigned)(x) & 0x0F) << 0)
 #define   G_030A04_CURRENT_PTR(x) (((x) >> 
0) & 0x0F)
 #define   C_030A04_CURRENT_PTR
0xFFF0
 #define   S_030A04_CURRENT_COUNT(x)   
(((unsigned)(x) & 0xFF) << 8)
@@ -1188,33 +1187,20 @@
 #define   G_030D24_DWB(x) (((x) >> 
0) & 0x1)
 #define   C_030D24_DWB
0xFFFE
 #define   S_030D24_DIRTY(x)   
(((unsigned)(x) & 0x1) << 1)
 #define   G_030D24_DIRTY(x)   (((x) >> 
1) & 0x1)
 #define   C_030D24_DIRTY  
0xFFFD
 #define R_030E00_TA_CS_BC_BASE_ADDR 
0x030E00
 #define R_030E04_TA_CS_BC_BASE_ADDR_HI  
0x030E04
 #define   S_030E04_ADDRESS(x) 
(((unsigned)(x) & 0xFF) << 0)
 #define   G_030E04_ADDRESS(x) (((x) >> 
0) & 0xFF)
 #define   C_030E04_ADDRESS
0xFF00
-#define R_030E08_TA_GRAD_ADJ_UCONFIG
0x030E08
-#define   S_030E08_GRAD_ADJ_0(x)  
(((unsigned)(x) & 0xFF) << 0)
-#define   G_030E08_GRAD_ADJ_0(x)  (((x) >> 
0) & 0xFF)
-#define   C_030E08_GRAD_ADJ_0 
0xFF00
-#define   S_030E08_GRAD_ADJ_1(x)  
(((unsigned)(x) & 0xFF) << 8)
-#define   G_030E08_GRAD_ADJ_1(x)  (((x) >> 
8) & 0xFF)
-#define   C_030E08_GRAD_ADJ_1 
0x00FF
-#define   S_030E08_GRAD_ADJ_2(x)  
(((unsigned)(x) & 0xFF) << 16)
-#define   G_030E08_GRAD_ADJ_2(x)  (((x) >> 
16) & 0xFF)
-#define   C_030E08_GRAD_ADJ_2 
0xFF00
-#define   S_030E08_GRAD_ADJ_3(x)  
(((unsigned)(x) & 0xFF) << 24)
-#define   G_030E08_GRAD_ADJ_3(x)  (((x) >> 
24) & 0xFF)
-#define   C_030E08_GRAD_ADJ_3 
0x00FF
 #define R_030F00_DB_OCCLUSION_COUNT0_LOW
0x030F00
 #define R_008F00_SQ_BUF_RSRC_WORD0  
0x008F00
 #define R_030F04_DB_OCCLUSION_COUNT0_HI 
0x030F04
 #define   S_030F04_COUNT_HI(x)
(((unsigned)(x) & 0x7FFF) << 0)
 #define   G_030F04_COUNT_HI(x)(((x) >> 
0) & 0x7FFF)
 #define   C_030F04_COUNT_HI   
0x8000
 #define R_008F04_SQ_BUF_RSRC_WORD1  
0x008F04
 

[Mesa-dev] [PATCH 6/6] radeonsi: set DB_EQAA.MAX_ANCHOR_SAMPLES correctly

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_state.c | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index f4e29f68b29..3a7e928df53 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -,21 +,21 @@ static void si_emit_msaa_config(struct si_context *sctx)
S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
S_028A4C_FORCE_EOV_REZ_ENABLE(1);
unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
   S_028804_INCOHERENT_EQAA_READS(1) |
   S_028804_INTERPOLATE_COMP_Z(1) |
   S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
-   unsigned coverage_samples, color_samples;
+   unsigned coverage_samples, color_samples, z_samples;
 
/* S: Coverage samples (up to 16x):
 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
 *
 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color 
samples):
 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
 * - Value seen by CB, must be correct even if Z/S is unbound 
(DB_EQAA.MAX_ANCHOR_SAMPLES)
 * # Missing samples are derived from Z planes if Z is compressed (up 
to 16x quality), or
 * # from the closest defined sample if Z is uncompressed (same quality 
as the number of
@@ -3379,24 +3379,31 @@ static void si_emit_msaa_config(struct si_context *sctx)
 *   EQAA  8s 8z 2f - might look the same as 8x MSAA with low-density 
geometry
 *   EQAA  8s 4z 4f - might look the same as 8x MSAA if Z is compressed
 *   EQAA  8s 4z 2f - might look the same as 8x MSAA with low-density 
geometry if Z is compressed
 *   EQAA  4s 4z 4f = 4x MSAA
 *   EQAA  4s 4z 2f - might look the same as 4x MSAA with low-density 
geometry
 *   EQAA  2s 2z 2f = 2x MSAA
 */
if (sctx->framebuffer.nr_samples > 1) {
coverage_samples = sctx->framebuffer.nr_samples;
color_samples = sctx->framebuffer.nr_color_samples;
+
+   if (sctx->framebuffer.state.zsbuf) {
+   z_samples = 
sctx->framebuffer.state.zsbuf->texture->nr_samples;
+   z_samples = MAX2(1, z_samples);
+   } else {
+   z_samples = coverage_samples;
+   }
} else if (sctx->smoothing_enabled) {
-   coverage_samples = color_samples = SI_NUM_SMOOTH_AA_SAMPLES;
+   coverage_samples = color_samples = z_samples = 
SI_NUM_SMOOTH_AA_SAMPLES;
} else {
-   coverage_samples = color_samples = 1;
+   coverage_samples = color_samples = z_samples = 1;
}
 
/* Required by OpenGL line rasterization.
 *
 * TODO: We should also enable perpendicular endcaps for AA lines,
 *   but that requires implementing line stippling in the pixel
 *   shader. SC can only do line stippling with axis-aligned
 *   endcaps.
 */
unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
@@ -3404,34 +3411,35 @@ static void si_emit_msaa_config(struct si_context *sctx)
if (coverage_samples > 1) {
/* distance from the pixel center, indexed by log2(nr_samples) 
*/
static unsigned max_dist[] = {
0, /* unused */
4, /* 2x MSAA */
6, /* 4x MSAA */
7, /* 8x MSAA */
8, /* 16x MSAA */
};
unsigned log_samples = util_logbase2(coverage_samples);
+   unsigned log_z_samples = util_logbase2(z_samples);
unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
 
radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, sc_line_cntl |
S_028BDC_EXPAND_LINE_WIDTH(1)); /* 
R_028BDC_PA_SC_LINE_CNTL */
radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* 
R_028BE0_PA_SC_AA_CONFIG */
 
if (sctx->framebuffer.nr_samples > 1) {
radeon_set_context_reg(cs, R_028804_DB_EQAA,
   db_eqaa |
-   

[Mesa-dev] [PATCH 4/6] radeonsi: remove redundant ps_iter_samples clamp

[Marek Olšák]

From: Marek Olšák 

si_get_ps_iter_samples already does this.
---
 src/gallium/drivers/radeonsi/si_state.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 675b1adbe65..5bbf134b706 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3405,21 +3405,20 @@ static void si_emit_msaa_config(struct si_context *sctx)
/* distance from the pixel center, indexed by log2(nr_samples) 
*/
static unsigned max_dist[] = {
0, /* unused */
4, /* 2x MSAA */
6, /* 4x MSAA */
7, /* 8x MSAA */
8, /* 16x MSAA */
};
unsigned log_samples = util_logbase2(coverage_samples);
unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
-   ps_iter_samples = MIN2(ps_iter_samples, color_samples);
unsigned log_ps_iter_samples =
util_logbase2(util_next_power_of_two(ps_iter_samples));
 
radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, sc_line_cntl |
S_028BDC_EXPAND_LINE_WIDTH(1)); /* 
R_028BDC_PA_SC_LINE_CNTL */
radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* 
R_028BE0_PA_SC_AA_CONFIG */
 
-- 
2.17.0

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[Mesa-dev] [PATCH 2/6] radeonsi: disable primitive binning for all blitter ops

[Marek Olšák]

From: Marek Olšák 

same as Vulkan.
---
 src/gallium/drivers/radeonsi/si_blit.c  | 10 ++
 src/gallium/drivers/radeonsi/si_pipe.h  |  2 +-
 src/gallium/drivers/radeonsi/si_state_binning.c |  2 +-
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 6f4cd1f9044..fe059b36577 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -68,24 +68,34 @@ void si_blitter_begin(struct si_context *sctx, enum 
si_blitter_op op)
util_blitter_save_fragment_sampler_states(
sctx->blitter, 2,

(void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
 
util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
sctx->samplers[PIPE_SHADER_FRAGMENT].views);
}
 
if (op & SI_DISABLE_RENDER_COND)
sctx->render_cond_force_off = true;
+
+   if (sctx->screen->dpbb_allowed) {
+   sctx->dpbb_force_off = true;
+   si_mark_atom_dirty(sctx, >atoms.s.dpbb_state);
+   }
 }
 
 void si_blitter_end(struct si_context *sctx)
 {
+   if (sctx->screen->dpbb_allowed) {
+   sctx->dpbb_force_off = false;
+   si_mark_atom_dirty(sctx, >atoms.s.dpbb_state);
+   }
+
sctx->render_cond_force_off = false;
 
/* Restore shader pointers because the VS blit shader changed all
 * non-global VS user SGPRs. */
sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX);
sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
si_mark_atom_dirty(sctx, >atoms.s.shader_pointers);
 }
 
 static unsigned u_max_sample(struct pipe_resource *r)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index 6917d5e6068..5d1671fb87f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -920,21 +920,21 @@ struct si_context {
 
/* Debug state. */
boolis_debug;
struct si_saved_cs  *current_saved_cs;
uint64_tdmesg_timestamp;
unsignedapitrace_call_number;
 
/* Other state */
bool need_check_render_feedback;
booldecompression_enabled;
-
+   booldpbb_force_off;
boolvs_writes_viewport_index;
boolvs_disables_clipping_viewport;
 
/* Precomputed IA_MULTI_VGT_PARAM */
union si_vgt_param_key  ia_multi_vgt_param_key;
unsignedia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 
/* Bindless descriptors. */
struct si_descriptors   bindless_descriptors;
struct util_idalloc bindless_used_slots;
diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c 
b/src/gallium/drivers/radeonsi/si_state_binning.c
index 80b1137fd0c..2605b59bbef 100644
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -336,21 +336,21 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
 
 void si_emit_dpbb_state(struct si_context *sctx)
 {
struct si_screen *sscreen = sctx->screen;
struct si_state_blend *blend = sctx->queued.named.blend;
struct si_state_dsa *dsa = sctx->queued.named.dsa;
unsigned db_shader_control = sctx->ps_db_shader_control;
 
assert(sctx->chip_class >= GFX9);
 
-   if (!sscreen->dpbb_allowed || !blend || !dsa) {
+   if (!sscreen->dpbb_allowed || !blend || !dsa || sctx->dpbb_force_off) {
si_emit_dpbb_disable(sctx);
return;
}
 
bool ps_can_kill = G_02880C_KILL_ENABLE(db_shader_control) ||
   G_02880C_MASK_EXPORT_ENABLE(db_shader_control) ||
   G_02880C_COVERAGE_TO_MASK_ENABLE(db_shader_control) 
||
   blend->alpha_to_coverage;
 
/* This is ported from Vulkan, but it doesn't make much sense to me.
-- 
2.17.0

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[Mesa-dev] [PATCH 5/6] radeonsi: round ps_iter_samples in set_min_samples

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_state.c | 6 --
 src/gallium/drivers/radeonsi/si_state_shaders.c | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 5bbf134b706..f4e29f68b29 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3405,22 +3405,21 @@ static void si_emit_msaa_config(struct si_context *sctx)
/* distance from the pixel center, indexed by log2(nr_samples) 
*/
static unsigned max_dist[] = {
0, /* unused */
4, /* 2x MSAA */
6, /* 4x MSAA */
7, /* 8x MSAA */
8, /* 16x MSAA */
};
unsigned log_samples = util_logbase2(coverage_samples);
unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
-   unsigned log_ps_iter_samples =
-   util_logbase2(util_next_power_of_two(ps_iter_samples));
+   unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
 
radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, sc_line_cntl |
S_028BDC_EXPAND_LINE_WIDTH(1)); /* 
R_028BDC_PA_SC_LINE_CNTL */
radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* 
R_028BE0_PA_SC_AA_CONFIG */
 
if (sctx->framebuffer.nr_samples > 1) {
radeon_set_context_reg(cs, R_028804_DB_EQAA,
@@ -3461,20 +3460,23 @@ void si_update_ps_iter_samples(struct si_context *sctx)
if (sctx->framebuffer.nr_samples > 1)
si_mark_atom_dirty(sctx, >atoms.s.msaa_config);
if (sctx->screen->dpbb_allowed)
si_mark_atom_dirty(sctx, >atoms.s.dpbb_state);
 }
 
 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
 {
struct si_context *sctx = (struct si_context *)ctx;
 
+   /* The hardware can only do sample shading with 2^n samples. */
+   min_samples = util_next_power_of_two(min_samples);
+
if (sctx->ps_iter_samples == min_samples)
return;
 
sctx->ps_iter_samples = min_samples;
sctx->do_update_shaders = true;
 
si_update_ps_iter_samples(sctx);
 }
 
 /*
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 2e215b91ce8..1b618502e85 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1407,21 +1407,21 @@ static inline void si_shader_selector_key(struct 
pipe_context *ctx,
 
key->part.ps.prolog.poly_stipple = 
rs->poly_stipple_enable && is_poly;
key->part.ps.epilog.poly_line_smoothing = ((is_poly && 
rs->poly_smooth) ||
  (is_line && 
rs->line_smooth)) &&
 
sctx->framebuffer.nr_samples <= 1;
key->part.ps.epilog.clamp_color = 
rs->clamp_fragment_color;
 
if (sctx->ps_iter_samples > 1 &&
sel->info.reads_samplemask) {
key->part.ps.prolog.samplemask_log_ps_iter =
-   
util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
+   util_logbase2(sctx->ps_iter_samples);
}
 
if (rs->force_persample_interp &&
rs->multisample_enable &&
sctx->framebuffer.nr_samples > 1 &&
sctx->ps_iter_samples > 1) {
key->part.ps.prolog.force_persp_sample_interp =
sel->info.uses_persp_center ||
sel->info.uses_persp_centroid;
 
-- 
2.17.0

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[Mesa-dev] [PATCH 1/6] ac/surface/gfx6: don't overallocate mipmapped HTILE

[Marek Olšák]

From: Marek Olšák 

---
 src/amd/common/ac_surface.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 9e742dc8a45..47de522d15d 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -927,22 +927,31 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 *
 * "dcc_alignment * 4" was determined by trial and error.
 */
surf->dcc_size = align64(surf->surf_size >> 8,
 surf->dcc_alignment * 4);
}
 
/* Make sure HTILE covers the whole miptree, because the shader reads
 * TC-compatible HTILE even for levels where it's disabled by DB.
 */
-   if (surf->htile_size && config->info.levels > 1)
-   surf->htile_size *= 2;
+   if (surf->htile_size && config->info.levels > 1 &&
+   surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
+   /* MSAA can't occur with levels > 1, so ignore the sample 
count. */
+   const unsigned total_pixels = surf->surf_size / surf->bpe;
+   const unsigned htile_block_size = 8 * 8;
+   const unsigned htile_element_size = 4;
+
+   surf->htile_size = (total_pixels / htile_block_size) *
+  htile_element_size;
+   surf->htile_size = align(surf->htile_size, 
surf->htile_alignment);
+   }
 
surf->is_linear = surf->u.legacy.level[0].mode == 
RADEON_SURF_MODE_LINEAR_ALIGNED;
surf->is_displayable = surf->is_linear ||
   surf->micro_tile_mode == 
RADEON_MICRO_MODE_DISPLAY ||
   surf->micro_tile_mode == 
RADEON_MICRO_MODE_ROTATED;
return 0;
 }
 
 /* This is only called when expecting a tiled layout. */
 static int
-- 
2.17.0

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Re: [Mesa-dev] [PATCH] r600: fix constant buffer bounds.

[Marek Olšák]

On Thu, May 10, 2018 at 10:58 AM, Roland Scheidegger 
wrote:

> Am 10.05.2018 um 16:47 schrieb Ivan Kalvachev:
> > On 5/10/18, Roland Scheidegger  wrote:
> >> Quite a sneaky little bug, can't hurt to make undefined behavior a bit
> >> more defined :-).
> >
> > Actually, this behavior is completely defined in Direct3D,
> > where out-of-bound access is expected to
> > always return 0.0 .
> > This is why Witcher1 has the issue in both Gallium Nine and WineD3D
> OpenGL.
> > (Curiously, only the Linux native OpenGL version of Trine1 EE has that
> issue.)
> >
> > In OpenGL there is "ARB_robust_buffer_access_behavior"
> > that Mesa3D claims to support.
> > https://urldefense.proofpoint.com/v2/url?u=https-3A__www.
> khronos.org_registry_OpenGL_extensions_ARB_ARB-5Frobust-
> 5Fbuffer-5Faccess-5Fbehavior.txt=DwIBaQ=uilaK90D4TOVoH58JNXRgQ=_
> QIjpv-UJ77xEQY8fIYoQtr5qv8wKrPJc7v7_-CYAb0=
> HABSbOZm1CI6dmKtNDRaqMEehdOkLSLHDcqhAPZECQo=IUJuFond_Xq02RLZJgY8K1CFlBF_
> pojvx3uMNzW113Q=
> >
> > Here is a quote that might be relevant to these cases:
> > ---
> > Add to Section 2.8 "Vertex Arrays" before 2.8.1 (Packed Vertex Data
> > Formats):
> >
> > "Robust buffer access can be enabled by creating a context with
> robust
> > access enabled through the window system binding APIs. When enabled,
> > indices within the elements array that reference vertex data that
> > lies outside the enabled attributes vertex buffer objects, result in
> > reading zero.[...]
> > ---
>
> Vertex arrays.
> Buffer objects in general (such as for uniform buffers) can still return
> just about anything (albeit not allowed to be data from outside the
> buffer, either 0 or any value from inside the buffer). (And for
> out-of-bounds it even considers the full buffer, not the bound buffer
> range). So a test checking for conformance there wouldn't help.
>

The Witcher1 issue isn't even about buffers. It uses out-of-bounds indexing
on uniform arrays. So ARB_robust_buffer_access_behavior doesn't apply.

Marek
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Re: [Mesa-dev] [PATCH] mesa: add glUniform*ui{v} support to display lists

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Wed, May 9, 2018 at 11:53 PM, Timothy Arceri 
wrote:

> Fixes: a017c7ecb7ae "mesa: display list support for uint uniforms"
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78097
> ---
>
>  Piglit test: https://patchwork.freedesktop.org/patch/221794/
>
>  src/mesa/main/dlist.c | 50 +++
>  1 file changed, 17 insertions(+), 33 deletions(-)
>
> diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
> index 01df4693f98..9e6cb725f54 100644
> --- a/src/mesa/main/dlist.c
> +++ b/src/mesa/main/dlist.c
> @@ -6596,7 +6596,7 @@ save_Uniform1ui(GLint location, GLuint x)
>n[2].i = x;
> }
> if (ctx->ExecuteFlag) {
> -  /*CALL_Uniform1ui(ctx->Exec, (location, x));*/
> +  CALL_Uniform1ui(ctx->Exec, (location, x));
> }
>  }
>
> @@ -6613,7 +6613,7 @@ save_Uniform2ui(GLint location, GLuint x, GLuint y)
>n[3].i = y;
> }
> if (ctx->ExecuteFlag) {
> -  /*CALL_Uniform2ui(ctx->Exec, (location, x, y));*/
> +  CALL_Uniform2ui(ctx->Exec, (location, x, y));
> }
>  }
>
> @@ -6631,7 +6631,7 @@ save_Uniform3ui(GLint location, GLuint x, GLuint y,
> GLuint z)
>n[4].i = z;
> }
> if (ctx->ExecuteFlag) {
> -  /*CALL_Uniform3ui(ctx->Exec, (location, x, y, z));*/
> +  CALL_Uniform3ui(ctx->Exec, (location, x, y, z));
> }
>  }
>
> @@ -6650,7 +6650,7 @@ save_Uniform4ui(GLint location, GLuint x, GLuint y,
> GLuint z, GLuint w)
>n[5].i = w;
> }
> if (ctx->ExecuteFlag) {
> -  /*CALL_Uniform4ui(ctx->Exec, (location, x, y, z, w));*/
> +  CALL_Uniform4ui(ctx->Exec, (location, x, y, z, w));
> }
>  }
>
> @@ -6669,7 +6669,7 @@ save_Uniform1uiv(GLint location, GLsizei count,
> const GLuint *v)
>save_pointer([3], memdup(v, count * 1 * sizeof(*v)));
> }
> if (ctx->ExecuteFlag) {
> -  /*CALL_Uniform1uiv(ctx->Exec, (location, count, v));*/
> +  CALL_Uniform1uiv(ctx->Exec, (location, count, v));
> }
>  }
>
> @@ -6686,7 +6686,7 @@ save_Uniform2uiv(GLint location, GLsizei count,
> const GLuint *v)
>save_pointer([3], memdup(v, count * 2 * sizeof(*v)));
> }
> if (ctx->ExecuteFlag) {
> -  /*CALL_Uniform2uiv(ctx->Exec, (location, count, v));*/
> +  CALL_Uniform2uiv(ctx->Exec, (location, count, v));
> }
>  }
>
> @@ -6703,7 +6703,7 @@ save_Uniform3uiv(GLint location, GLsizei count,
> const GLuint *v)
>save_pointer([3], memdup(v, count * 3 * sizeof(*v)));
> }
> if (ctx->ExecuteFlag) {
> -  /*CALL_Uniform3uiv(ctx->Exec, (location, count, v));*/
> +  CALL_Uniform3uiv(ctx->Exec, (location, count, v));
> }
>  }
>
> @@ -6720,7 +6720,7 @@ save_Uniform4uiv(GLint location, GLsizei count,
> const GLuint *v)
>save_pointer([3], memdup(v, count * 4 * sizeof(*v)));
> }
> if (ctx->ExecuteFlag) {
> -  /*CALL_Uniform4uiv(ctx->Exec, (location, count, v));*/
> +  CALL_Uniform4uiv(ctx->Exec, (location, count, v));
> }
>  }
>
> @@ -8785,34 +8785,29 @@ execute_list(struct gl_context *ctx, GLuint list)
>  CALL_Uniform4iv(ctx->Exec, (n[1].i, n[2].i,
> get_pointer([3])));
>  break;
>   case OPCODE_UNIFORM_1UI:
> -/*CALL_Uniform1uiARB(ctx->Exec, (n[1].i, n[2].i));*/
> +CALL_Uniform1ui(ctx->Exec, (n[1].i, n[2].i));
>  break;
>   case OPCODE_UNIFORM_2UI:
> -/*CALL_Uniform2uiARB(ctx->Exec, (n[1].i, n[2].i, n[3].i));*/
> +CALL_Uniform2ui(ctx->Exec, (n[1].i, n[2].i, n[3].i));
>  break;
>   case OPCODE_UNIFORM_3UI:
> -/*CALL_Uniform3uiARB(ctx->Exec, (n[1].i, n[2].i, n[3].i,
> n[4].i));*/
> +CALL_Uniform3ui(ctx->Exec, (n[1].i, n[2].i, n[3].i, n[4].i));
>  break;
>   case OPCODE_UNIFORM_4UI:
> -/*CALL_Uniform4uiARB(ctx->Exec,
> -  (n[1].i, n[2].i, n[3].i, n[4].i, n[5].i));
> -*/
> +CALL_Uniform4ui(ctx->Exec,
> +(n[1].i, n[2].i, n[3].i, n[4].i, n[5].i));
>  break;
>   case OPCODE_UNIFORM_1UIV:
> -/*CALL_Uniform1uivARB(ctx->Exec, (n[1].i, n[2].i,
> -  get_pointer([3])));*/
> +CALL_Uniform1uiv(ctx->Exec, (n[1].i, n[2].i,
> get_pointer([3])));
>  break;
>   case OPCODE_UNIFORM_2UIV:
> -/*CALL_Uniform2uivARB(ctx->Exec, (n[1].i, n[2].i,
> -  get_pointer([3])));*/
> +CALL_Uniform2uiv(ctx->Exec, (n[1].i, n[2].i,
> get_pointer([3])));
>  break;
>   case OPCODE_UNIFORM_3UIV:
> -/*CALL_Uniform3uivARB(ctx->Exec, (n[1].i, n[2].i,
> -  get_pointer([3])));*/
> +CALL_Uniform3uiv(ctx->Exec, (n[1].i, n[2].i,
> get_pointer([3])));
>  break;
>  

Re: [Mesa-dev] [PATCH v2 1/3] glsl: add glsl_external_mode() helper

[Marek Olšák]

On Sat, May 12, 2018 at 12:49 AM, Timothy Arceri 
wrote:

> This allows us to get the variable mode as specified by the GLSL
> spec. We will use this in the following patch.
> ---
>  src/compiler/glsl/ast_to_hir.cpp | 73 
>  1 file changed, 73 insertions(+)
>
> diff --git a/src/compiler/glsl/ast_to_hir.cpp
> b/src/compiler/glsl/ast_to_hir.cpp
> index 3bf581571e2..a7a9ac80769 100644
> --- a/src/compiler/glsl/ast_to_hir.cpp
> +++ b/src/compiler/glsl/ast_to_hir.cpp
> @@ -4175,6 +4175,79 @@ apply_type_qualifier_to_variable(const struct
> ast_type_qualifier *qual,
> apply_image_qualifier_to_variable(qual, var, state, loc);
>  }
>
> +/**
> + * Get the GLSL mode specified in for system values (if any).
> + */
> +static enum ir_variable_mode
> +glsl_external_mode(enum ir_variable_mode internal_mode, gl_shader_stage
> stage,
> +   unsigned slot) {
> +   if (internal_mode == ir_var_system_value) {
> +  switch (slot) {
> +  case SYSTEM_VALUE_SUBGROUP_SIZE:
> + return ir_var_uniform;
> +  case SYSTEM_VALUE_PRIMITIVE_ID:
> + if (stage == MESA_SHADER_GEOMETRY) {
> +return ir_var_shader_out;
>

System values are always inputs. This one is gl_PrimitiveIDIn.


> + } else {
> +return ir_var_shader_in;
> + }
> +  case SYSTEM_VALUE_TESS_LEVEL_OUTER:
> +  case SYSTEM_VALUE_TESS_LEVEL_INNER:
> + if (stage == MESA_SHADER_TESS_CTRL) {
> +return ir_var_shader_out;
>

System values are always inputs, i.e. TESS_CTRL isn't allowed here.

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Re: [Mesa-dev] [PATCH 2/2] glsl: allow linking ES shaders with desktop shaders in desktop GL

[Ilia Mirkin]

ES has all kinds of additional linking rules. I suspect they'll break
down if some of the shaders are ES and some are not-ES.

This all does sound very odd -- what did you see in practice?

On Wed, May 16, 2018 at 3:04 AM, Timothy Arceri  wrote:
> In GLES shader versions must match but there is nothing
> in the ARB_ES*_compatibility specs that say they must match.
>
> This fixes some compilation errors in Google Earth VR.
> ---
>  src/compiler/glsl/linker.cpp | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
> index f060c5316fa..2b7ee0ad5a6 100644
> --- a/src/compiler/glsl/linker.cpp
> +++ b/src/compiler/glsl/linker.cpp
> @@ -83,6 +83,7 @@
>  #include "builtin_functions.h"
>  #include "shader_cache.h"
>
> +#include "main/context.h"
>  #include "main/imports.h"
>  #include "main/shaderobj.h"
>  #include "main/enums.h"
> @@ -4799,7 +4800,8 @@ link_shaders(struct gl_context *ctx, struct 
> gl_shader_program *prog)
>min_version = MIN2(min_version, prog->Shaders[i]->Version);
>max_version = MAX2(max_version, prog->Shaders[i]->Version);
>
> -  if (prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
> +  if (!_mesa_is_desktop_gl(ctx) &&
> +  prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
>   linker_error(prog, "all shaders must use same shading "
>"language version\n");
>   goto done;
> @@ -4817,7 +4819,7 @@ link_shaders(struct gl_context *ctx, struct 
> gl_shader_program *prog)
> /* In desktop GLSL, different shader versions may be linked together.  In
>  * GLSL ES, all shader versions must be the same.
>  */
> -   if (prog->Shaders[0]->IsES && min_version != max_version) {
> +   if (!_mesa_is_desktop_gl(ctx) && min_version != max_version) {
>linker_error(prog, "all shaders must use same shading "
> "language version\n");
>goto done;
> --
> 2.17.0
>
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Re: [Mesa-dev] [PATCH] ac/llvm: use amdgcn.tbuffer.store instead of SI.tbuffer.store intrinsic

[Marek Olšák]

The new intrinsic is supported since LLVM 5.0. With that fixed:

Reviewed-by: Marek Olšák 

Marek

On Tue, May 15, 2018 at 8:24 PM, Dave Airlie  wrote:

> From: Dave Airlie 
>
> Drop the use of the old intrinsic.
> ---
>  src/amd/common/ac_llvm_build.c | 92 +++---
> 
>  1 file changed, 60 insertions(+), 32 deletions(-)
>
> diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_
> build.c
> index c9b2e36b632..18a624a0dae 100644
> --- a/src/amd/common/ac_llvm_build.c
> +++ b/src/amd/common/ac_llvm_build.c
> @@ -888,11 +888,18 @@ ac_build_buffer_store_dword(struct ac_llvm_context
> *ctx,
> bool writeonly_memory,
> bool swizzle_enable_hint)
>  {
> +   static unsigned dfmt[] = {
> +   V_008F0C_BUF_DATA_FORMAT_32,
> +   V_008F0C_BUF_DATA_FORMAT_32_32,
> +   V_008F0C_BUF_DATA_FORMAT_32_32_32,
> +   V_008F0C_BUF_DATA_FORMAT_32_32_32_32
> +   };
> +
> /* SWIZZLE_ENABLE requires that soffset isn't folded into voffset
>  * (voffset is swizzled, but soffset isn't swizzled).
>  * llvm.amdgcn.buffer.store doesn't have a separate soffset
> parameter.
>  */
> -   if (!swizzle_enable_hint) {
> +   if (!swizzle_enable_hint || HAVE_LLVM >= 0x0700) {
> /* Split 3 channel stores, becase LLVM doesn't support
> 3-channel
>  * intrinsics. */
> if (num_channels == 3) {
> @@ -915,42 +922,63 @@ ac_build_buffer_store_dword(struct ac_llvm_context
> *ctx,
> }
>
> unsigned func = CLAMP(num_channels, 1, 3) - 1;
> -   static const char *types[] = {"f32", "v2f32", "v4f32"};
> char name[256];
> -   LLVMValueRef offset = soffset;
> -
> -   if (inst_offset)
> -   offset = LLVMBuildAdd(ctx->builder, offset,
> - LLVMConstInt(ctx->i32,
> inst_offset, 0), "");
> -   if (voffset)
> -   offset = LLVMBuildAdd(ctx->builder, offset,
> voffset, "");
> -
> -   LLVMValueRef args[] = {
> -   ac_to_float(ctx, vdata),
> -   LLVMBuildBitCast(ctx->builder, rsrc, ctx->v4i32,
> ""),
> -   LLVMConstInt(ctx->i32, 0, 0),
> -   offset,
> -   LLVMConstInt(ctx->i1, glc, 0),
> -   LLVMConstInt(ctx->i1, slc, 0),
> -   };
> -
> -   snprintf(name, sizeof(name), "llvm.amdgcn.buffer.store.%s",
> -types[func]);
> -
> -   ac_build_intrinsic(ctx, name, ctx->voidt,
> -  args, ARRAY_SIZE(args),
> -  writeonly_memory ?
> +
> +   if (!swizzle_enable_hint) {
> +   LLVMValueRef offset = soffset;
> +
> +   static const char *types[] = {"f32", "v2f32",
> "v4f32"};
> +
> +   if (inst_offset)
> +   offset = LLVMBuildAdd(ctx->builder, offset,
> +
>  LLVMConstInt(ctx->i32, inst_offset, 0), "");
> +   if (voffset)
> +   offset = LLVMBuildAdd(ctx->builder,
> offset, voffset, "");
> +
> +   LLVMValueRef args[] = {
> +   ac_to_float(ctx, vdata),
> +   LLVMBuildBitCast(ctx->builder, rsrc,
> ctx->v4i32, ""),
> +   LLVMConstInt(ctx->i32, 0, 0),
> +   offset,
> +   LLVMConstInt(ctx->i1, glc, 0),
> +   LLVMConstInt(ctx->i1, slc, 0),
> +   };
> +
> +   snprintf(name, sizeof(name),
> "llvm.amdgcn.buffer.store.%s",
> +types[func]);
> +
> +   ac_build_intrinsic(ctx, name, ctx->voidt,
> +  args, ARRAY_SIZE(args),
> +  writeonly_memory ?
>AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY
> :
>AC_FUNC_ATTR_WRITEONLY);
> -   return;
> +   return;
> +   } else {
> +   static const char *types[] = {"i32", "v2i32",
> "v4i32"};
> +   LLVMValueRef args[] = {
> +   vdata,
> +   LLVMBuildBitCast(ctx->builder, rsrc,
> ctx->v4i32, ""),
> +   LLVMConstInt(ctx->i32, 0, 0),
> +   voffset ? voffset : LLVMConstInt(ctx->i32,
> 0, 0),
> +   soffset,
> +   

Re: [Mesa-dev] [PATCH 2/2] glsl: allow linking ES shaders with desktop shaders in desktop GL

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Wed, May 16, 2018 at 3:04 AM, Timothy Arceri 
wrote:

> In GLES shader versions must match but there is nothing
> in the ARB_ES*_compatibility specs that say they must match.
>
> This fixes some compilation errors in Google Earth VR.
> ---
>  src/compiler/glsl/linker.cpp | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
> index f060c5316fa..2b7ee0ad5a6 100644
> --- a/src/compiler/glsl/linker.cpp
> +++ b/src/compiler/glsl/linker.cpp
> @@ -83,6 +83,7 @@
>  #include "builtin_functions.h"
>  #include "shader_cache.h"
>
> +#include "main/context.h"
>  #include "main/imports.h"
>  #include "main/shaderobj.h"
>  #include "main/enums.h"
> @@ -4799,7 +4800,8 @@ link_shaders(struct gl_context *ctx, struct
> gl_shader_program *prog)
>min_version = MIN2(min_version, prog->Shaders[i]->Version);
>max_version = MAX2(max_version, prog->Shaders[i]->Version);
>
> -  if (prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
> +  if (!_mesa_is_desktop_gl(ctx) &&
> +  prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
>   linker_error(prog, "all shaders must use same shading "
>"language version\n");
>   goto done;
> @@ -4817,7 +4819,7 @@ link_shaders(struct gl_context *ctx, struct
> gl_shader_program *prog)
> /* In desktop GLSL, different shader versions may be linked together.
> In
>  * GLSL ES, all shader versions must be the same.
>  */
> -   if (prog->Shaders[0]->IsES && min_version != max_version) {
> +   if (!_mesa_is_desktop_gl(ctx) && min_version != max_version) {
>linker_error(prog, "all shaders must use same shading "
> "language version\n");
>goto done;
> --
> 2.17.0
>
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Re: [Mesa-dev] docs: Intel Mesa Drivers infographic

[Rob Clark]

feel free to disregard, considering the target audience, but
s/Designed for Intel GPUs/Designed for GPUs/ ?

(I mean compared to, say, LLVM, NIR has more passes that are in
general useful to GPUs and much of what it misses compared to LLVM
seems less useful for GPUs or SIMT processors.. I think for other
drivers that do nir->backend (which is not LLVM) we could still get
some benefit of adding some non-intel-specific opcodes to NIR, but
that is more a matter of other drivers not having typed up the patches
than some NIR limitation)

BR,
-R

On Wed, May 16, 2018 at 6:14 PM, Laura Ekstrand  wrote:
> https://drive.google.com/file/d/1D0k3-p88xEame5gepJQfIcCyZhG4CAsW/view?usp=sharing
>
> On Mon, May 14, 2018 at 5:44 PM, Jason Ekstrand 
> wrote:
>>
>> One more comment: NIR is *not* a stable API.
>>
>> On Mon, May 14, 2018 at 2:10 PM, Laura Ekstrand 
>> wrote:
>>>
>>> I've made the edits.
>>> https://drive.google.com/file/d/1D0k3-p88xEame5gepJQfIcCyZhG4CAsW/view?usp=sharing
>>>
>>> Thanks.
>>>
>>> Laura
>>>
>>> On Fri, May 11, 2018 at 5:07 PM, Jason Ekstrand 
>>> wrote:

 Couple of edits:

 i915:  I'd leave the bit about "embedded" out.  I don't think it's used
 for any new deployments at this point.

 1965: How about "Implements intel-specific parts of OpenGL entrypoints"

 ISL isn't really for converting between surface formats.  A better
 one-sentence description would be "A library for computing image sizes and
 memory layouts"

 BLORP: How about "blit, clear, and resolve functionality" rather than
 "driver functionality"

 NIR: Not really a "front-end" more of an "optimizing middle compiler"

 Looks snazzy though. :-)

 On Thu, May 10, 2018 at 6:19 PM, Laura Ekstrand 
 wrote:
>
> Hi All,
>
> I developed the following infographic to inform readers about the
> various parts that make up the Intel Mesa drivers.  It is intended to help
> groups inside Intel better understand the open source community, and at 
> the
> same time, it helps train newcomers to Mesa in driver architecture.
>
> I haven't put this in a tree yet since it is a combination of a
> LibreOffice Draw document and a binary image file.
>
> Thanks.
>
> Laura
>
>
> https://drive.google.com/file/d/1D0k3-p88xEame5gepJQfIcCyZhG4CAsW/view?usp=sharing
>
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>>>
>>
>
>
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Re: [Mesa-dev] [PATCH v2] st/mesa: only define GLSL 1.4 for compat if driver supports it

[Timothy Arceri]

On 17/05/18 00:17, Grazvydas Ignotas wrote:

On Wed, May 16, 2018 at 5:02 PM, Christian Gmeiner
 wrote:

Currently GLSL 1.4 is defined for all gallium drivers even only
GLSL 1.2 is supported as seen on etnaviv.

v1 -> v2:
  - use _min(..) as suggested by Lucas Stach and Michel Dänzer

Fixes 4560aad780b ("mesa: add GLSLVersionCompat constant")


Should be "Fixes: ...".
See git log for examples.


With this:

Reviewed-by: Timothy Arceri 



Gražvydas


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Re: [Mesa-dev] docs: Intel Mesa Drivers infographic

[Laura Ekstrand]

https://drive.google.com/file/d/1D0k3-p88xEame5gepJQfIcCyZhG4CAsW/view?usp=sharing

On Mon, May 14, 2018 at 5:44 PM, Jason Ekstrand 
wrote:

> One more comment: NIR is *not* a stable API.
>
> On Mon, May 14, 2018 at 2:10 PM, Laura Ekstrand 
> wrote:
>
>> I've made the edits.  https://drive.google.com/file/
>> d/1D0k3-p88xEame5gepJQfIcCyZhG4CAsW/view?usp=sharing
>>
>> Thanks.
>>
>> Laura
>>
>> On Fri, May 11, 2018 at 5:07 PM, Jason Ekstrand 
>> wrote:
>>
>>> Couple of edits:
>>>
>>> i915:  I'd leave the bit about "embedded" out.  I don't think it's used
>>> for any new deployments at this point.
>>>
>>> 1965: How about "Implements intel-specific parts of OpenGL entrypoints"
>>>
>>> ISL isn't really for converting between surface formats.  A better
>>> one-sentence description would be "A library for computing image sizes and
>>> memory layouts"
>>>
>>> BLORP: How about "blit, clear, and resolve functionality" rather than
>>> "driver functionality"
>>>
>>> NIR: Not really a "front-end" more of an "optimizing middle compiler"
>>>
>>> Looks snazzy though. :-)
>>>
>>> On Thu, May 10, 2018 at 6:19 PM, Laura Ekstrand 
>>> wrote:
>>>
 Hi All,

 I developed the following infographic to inform readers about the
 various parts that make up the Intel Mesa drivers.  It is intended to help
 groups inside Intel better understand the open source community, and at the
 same time, it helps train newcomers to Mesa in driver architecture.

 I haven't put this in a tree yet since it is a combination of a
 LibreOffice Draw document and a binary image file.

 Thanks.

 Laura

 https://drive.google.com/file/d/1D0k3-p88xEame5gepJQfIcCyZhG
 4CAsW/view?usp=sharing

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>>>
>>
>
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[Mesa-dev] [PATCH 1/4] i965: Make get_ccs_surf succeed in alloc_aux

[Nanley Chery]

Synchronize the requirements listed in isl_surf_get_ccs_surf with
intel_miptree_supports_ccs by importing a restriction from ISL. Some
implications:
* We successfully create every aux_surf in alloc_aux
* We only return false from alloc_aux if we run out of memory
---
 src/mesa/drivers/dri/i965/brw_blorp.c |  5 +
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16 ++--
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 636591c0b79..70c8e0d5816 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1209,10 +1209,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
if (can_fast_clear && !irb->mt->aux_buf) {
   assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
   if (!intel_miptree_alloc_aux(brw, irb->mt)) {
- /* There are a few reasons in addition to out-of-memory, that can
-  * cause intel_miptree_alloc_non_msrt_mcs to fail.  Try to recover by
-  * falling back to non-fast clear.
-  */
+ /* We're out of memory. Fall back to a non-fast clear. */
  can_fast_clear = false;
   }
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0c7c89a9ac4..0289f4f7e4c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -204,6 +204,13 @@ intel_miptree_supports_ccs(struct brw_context *brw,
if (devinfo->gen < 8 && (mip_mapped || arrayed))
   return false;
 
+   /* The PRM doesn't say this explicitly, but fast-clears don't appear to
+* work for 3D textures until gen9 where the layout of 3D textures changes
+* to match 2D array textures.
+*/
+   if (devinfo->gen <= 8 && mt->surf.dim != ISL_SURF_DIM_2D)
+  return false;
+
/* There's no point in using an MCS buffer if the surface isn't in a
 * renderable format.
 */
@@ -1793,7 +1800,7 @@ intel_miptree_alloc_aux(struct brw_context *brw,
enum isl_aux_state initial_state;
uint8_t memset_value;
struct isl_surf aux_surf;
-   bool aux_surf_ok;
+   MAYBE_UNUSED bool aux_surf_ok;
 
switch (mt->aux_usage) {
case ISL_AUX_USAGE_NONE:
@@ -1805,7 +1812,6 @@ intel_miptree_alloc_aux(struct brw_context *brw,
 
   initial_state = ISL_AUX_STATE_AUX_INVALID;
   aux_surf_ok = isl_surf_get_hiz_surf(>isl_dev, >surf, _surf);
-  assert(aux_surf_ok);
   break;
case ISL_AUX_USAGE_MCS:
   assert(_mesa_is_format_color_format(mt->format));
@@ -1826,7 +1832,6 @@ intel_miptree_alloc_aux(struct brw_context *brw,
   initial_state = ISL_AUX_STATE_CLEAR;
   memset_value = 0xFF;
   aux_surf_ok = isl_surf_get_mcs_surf(>isl_dev, >surf, _surf);
-  assert(aux_surf_ok);
   break;
case ISL_AUX_USAGE_CCS_D:
case ISL_AUX_USAGE_CCS_E:
@@ -1852,9 +1857,8 @@ intel_miptree_alloc_aux(struct brw_context *brw,
   break;
}
 
-   /* Ensure we have a valid aux_surf. */
-   if (aux_surf_ok == false)
-  return false;
+   /* We should have a valid aux_surf. */
+   assert(aux_surf_ok);
 
/* No work is needed for a zero-sized auxiliary buffer. */
if (aux_surf.size == 0)
-- 
2.17.0

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[Mesa-dev] [PATCH 4/4] i965: isl: Move the MCS gen7+ assertion into ISL

[Nanley Chery]

This is useful for every user of ISL. Drop the comment along the way to
match similar functions in ISL.
---
 src/intel/isl/isl.c   | 2 ++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 --
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 7dfead00dc6..f39d8a79995 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1642,6 +1642,8 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
   const struct isl_surf *surf,
   struct isl_surf *mcs_surf)
 {
+   assert(ISL_DEV_GEN(dev) >= 7);
+
/* It must be multisampled with an array layout */
assert(surf->samples > 1 && surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index b783cf3abf1..5f19e23b018 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1808,8 +1808,6 @@ intel_miptree_alloc_aux(struct brw_context *brw,
   aux_surf_ok = isl_surf_get_hiz_surf(>isl_dev, >surf, _surf);
   break;
case ISL_AUX_USAGE_MCS:
-  assert(brw->screen->devinfo.gen >= 7); /* MCS only used on Gen7+ */
-
   /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
*
* When MCS buffer is enabled and bound to MSRT, it is required that
-- 
2.17.0

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[Mesa-dev] [PATCH 3/4] i965/miptree: Remove format assertion in alloc_aux

[Nanley Chery]

intel_miptree_supports_{ccs,mcs,hiz} ensures the format is valid for the
color or depth miptree before the miptree is assigned an aux_usage.
alloc_aux switches on the aux_usage so don't assert that the format is
valid.
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 1a797326a82..b783cf3abf1 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1804,13 +1804,10 @@ intel_miptree_alloc_aux(struct brw_context *brw,
   aux_surf_ok = true;
   break;
case ISL_AUX_USAGE_HIZ:
-  assert(!_mesa_is_format_color_format(mt->format));
-
   initial_state = ISL_AUX_STATE_AUX_INVALID;
   aux_surf_ok = isl_surf_get_hiz_surf(>isl_dev, >surf, _surf);
   break;
case ISL_AUX_USAGE_MCS:
-  assert(_mesa_is_format_color_format(mt->format));
   assert(brw->screen->devinfo.gen >= 7); /* MCS only used on Gen7+ */
 
   /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
@@ -1831,8 +1828,6 @@ intel_miptree_alloc_aux(struct brw_context *brw,
   break;
case ISL_AUX_USAGE_CCS_D:
case ISL_AUX_USAGE_CCS_E:
-  assert(_mesa_is_format_color_format(mt->format));
-
   /* When CCS_E is used, we need to ensure that the CCS starts off in a
* valid state.  From the Sky Lake PRM, "MCS Buffer for Render
* Target(s)":
-- 
2.17.0

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[Mesa-dev] [PATCH 2/4] i965/miptree: Simplify the switch in supports_ccs

[Nanley Chery]

---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0289f4f7e4c..1a797326a82 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -159,12 +159,8 @@ intel_miptree_supports_ccs(struct brw_context *brw,
   return false;
 
/* MCS is only supported for color buffers */
-   switch (_mesa_get_format_base_format(mt->format)) {
-   case GL_DEPTH_COMPONENT:
-   case GL_DEPTH_STENCIL:
-   case GL_STENCIL_INDEX:
+   if (!_mesa_is_format_color_format(mt->format))
   return false;
-   }
 
if (mt->cpp != 4 && mt->cpp != 8 && mt->cpp != 16)
   return false;
-- 
2.17.0

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[Mesa-dev] [PATCH 0/4] intel: Make get_ccs_surf succeed in alloc_aux

[Nanley Chery]

Topi noticed that in intel_miptree_alloc_aux, we allowed CCS surface
retrieval to fail, but asserted that HiZ and MCS surface retrieval would
succeed. This series gets rid of that inconsistency and modifies some
related assertions.

This series is on top of 
"i965: Avoid a redundant color buffer fast-clear"
which will be pushed soon.

Nanley Chery (4):
  i965: Make get_ccs_surf succeed in alloc_aux
  i965/miptree: Simplify the switch in supports_ccs
  i965/miptree: Remove format assertion in alloc_aux
  i965: isl: Move the MCS gen7+ assertion into ISL

 src/intel/isl/isl.c   |  2 ++
 src/mesa/drivers/dri/i965/brw_blorp.c |  5 +---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 +++
 3 files changed, 14 insertions(+), 22 deletions(-)

-- 
2.17.0

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Re: [Mesa-dev] [PATCH v2] docs: add 18.0.5 in the release calendar

[Andres Gomez]

On Mon, 2018-05-14 at 16:18 +0200, Juan A. Suarez Romero wrote:
> Mesa 18.1 series has not been released yet, so let's extend 18.0 lifetime.

I suppose this also means that the part of the table regarding the 18.1
release should also be updated.

In any case, this is:

Reviewed-by: Andres Gomez 

-- 
Br,

Andres
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Re: [Mesa-dev] [PATCH] etnaviv: Fix missing rnndb file in tarballs

[Christian Gmeiner]

Am Mi., 16. Mai 2018 um 19:17 Uhr schrieb Christian Gmeiner <
christian.gmei...@gmail.com>:


> Am Mi., 16. Mai 2018 um 19:04 Uhr schrieb Stuart Young :

> > Seems that when the rnndb files for etniviv were updated/included back
> > in Nov 2017, hw/texdesc_3d.xml.h was missed from Makefile.sources and
> > meson.build. This was all during the conversion to meson, so it apears
> > to have slipped through the cracks. As such, this file has been missing
> > from the official tarballs since inclusion in Mesa, so the git trees
> > and tarballs differ.

> > Found due to lintian errors in the Debian packages.

> > Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb")


> Reviewed-by: Christian Gmeiner 

I think this should also land in stable...

Cc: mesa-sta...@lists.freedesktop.org


> > ---
> >   src/gallium/drivers/etnaviv/Makefile.sources | 1 +
> >   src/gallium/drivers/etnaviv/meson.build  | 1 +
> >   2 files changed, 2 insertions(+)

> > diff --git a/src/gallium/drivers/etnaviv/Makefile.sources
> b/src/gallium/drivers/etnaviv/Makefile.sources
> > index 05df2d9c5f..0b20812299 100644
> > --- a/src/gallium/drivers/etnaviv/Makefile.sources
> > +++ b/src/gallium/drivers/etnaviv/Makefile.sources
> > @@ -6,6 +6,7 @@ C_SOURCES :=  \
> >  hw/state_3d.xml.h \
> >  hw/state_blt.xml.h \
> >  hw/state.xml.h \
> > +   hw/texdesc_3d.xml.h \
> >  \
> >  etnaviv_asm.c \
> >  etnaviv_asm.h \
> > diff --git a/src/gallium/drivers/etnaviv/meson.build
> b/src/gallium/drivers/etnaviv/meson.build
> > index 48e99d28c8..1733024ac9 100644
> > --- a/src/gallium/drivers/etnaviv/meson.build
> > +++ b/src/gallium/drivers/etnaviv/meson.build
> > @@ -26,6 +26,7 @@ files_etnaviv = files(
> > 'hw/state_3d.xml.h',
> > 'hw/state_blt.xml.h',
> > 'hw/state.xml.h',
> > +  'hw/texdesc_3d.xml.h',
> > 'etnaviv_asm.c',
> > 'etnaviv_asm.h',
> > 'etnaviv_blend.c',
> > --
> > 2.11.0

> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev



> --
> greets
> --
> Christian Gmeiner, MSc

> https://christian-gmeiner.info



-- 
greets
--
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https://christian-gmeiner.info
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Re: [Mesa-dev] [PATCH] etnaviv: Fix missing rnndb file in tarballs

[Christian Gmeiner]

Am Mi., 16. Mai 2018 um 19:04 Uhr schrieb Stuart Young :

> Seems that when the rnndb files for etniviv were updated/included back
> in Nov 2017, hw/texdesc_3d.xml.h was missed from Makefile.sources and
> meson.build. This was all during the conversion to meson, so it apears
> to have slipped through the cracks. As such, this file has been missing
> from the official tarballs since inclusion in Mesa, so the git trees
> and tarballs differ.

> Found due to lintian errors in the Debian packages.

> Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb")


Reviewed-by: Christian Gmeiner 

> ---
>   src/gallium/drivers/etnaviv/Makefile.sources | 1 +
>   src/gallium/drivers/etnaviv/meson.build  | 1 +
>   2 files changed, 2 insertions(+)

> diff --git a/src/gallium/drivers/etnaviv/Makefile.sources
b/src/gallium/drivers/etnaviv/Makefile.sources
> index 05df2d9c5f..0b20812299 100644
> --- a/src/gallium/drivers/etnaviv/Makefile.sources
> +++ b/src/gallium/drivers/etnaviv/Makefile.sources
> @@ -6,6 +6,7 @@ C_SOURCES :=  \
>  hw/state_3d.xml.h \
>  hw/state_blt.xml.h \
>  hw/state.xml.h \
> +   hw/texdesc_3d.xml.h \
>  \
>  etnaviv_asm.c \
>  etnaviv_asm.h \
> diff --git a/src/gallium/drivers/etnaviv/meson.build
b/src/gallium/drivers/etnaviv/meson.build
> index 48e99d28c8..1733024ac9 100644
> --- a/src/gallium/drivers/etnaviv/meson.build
> +++ b/src/gallium/drivers/etnaviv/meson.build
> @@ -26,6 +26,7 @@ files_etnaviv = files(
> 'hw/state_3d.xml.h',
> 'hw/state_blt.xml.h',
> 'hw/state.xml.h',
> +  'hw/texdesc_3d.xml.h',
> 'etnaviv_asm.c',
> 'etnaviv_asm.h',
> 'etnaviv_blend.c',
> --
> 2.11.0

> ___
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-- 
greets
--
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https://christian-gmeiner.info
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[Mesa-dev] [PATCH] etnaviv: Fix missing rnndb file in tarballs

[Stuart Young]

Seems that when the rnndb files for etniviv were updated/included back
in Nov 2017, hw/texdesc_3d.xml.h was missed from Makefile.sources and
meson.build. This was all during the conversion to meson, so it apears
to have slipped through the cracks. As such, this file has been missing
from the official tarballs since inclusion in Mesa, so the git trees
and tarballs differ.

Found due to lintian errors in the Debian packages.

Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb")

---
 src/gallium/drivers/etnaviv/Makefile.sources | 1 +
 src/gallium/drivers/etnaviv/meson.build  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/gallium/drivers/etnaviv/Makefile.sources 
b/src/gallium/drivers/etnaviv/Makefile.sources
index 05df2d9c5f..0b20812299 100644
--- a/src/gallium/drivers/etnaviv/Makefile.sources
+++ b/src/gallium/drivers/etnaviv/Makefile.sources
@@ -6,6 +6,7 @@ C_SOURCES :=  \
hw/state_3d.xml.h \
hw/state_blt.xml.h \
hw/state.xml.h \
+   hw/texdesc_3d.xml.h \
\
etnaviv_asm.c \
etnaviv_asm.h \
diff --git a/src/gallium/drivers/etnaviv/meson.build 
b/src/gallium/drivers/etnaviv/meson.build
index 48e99d28c8..1733024ac9 100644
--- a/src/gallium/drivers/etnaviv/meson.build
+++ b/src/gallium/drivers/etnaviv/meson.build
@@ -26,6 +26,7 @@ files_etnaviv = files(
   'hw/state_3d.xml.h',
   'hw/state_blt.xml.h',
   'hw/state.xml.h',
+  'hw/texdesc_3d.xml.h',
   'etnaviv_asm.c',
   'etnaviv_asm.h',
   'etnaviv_blend.c',
-- 
2.11.0

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Re: [Mesa-dev] [PATCH] virgl: Update virgl_hw.h

[Gurchetan Singh]

Yes, it seems needed for the GLES on GLES work.  Still needs to land:

Reviewed-by: Gurchetan Singh 
On Wed, May 9, 2018 at 7:15 PM Dave Airlie  wrote:

> On 4 April 2018 at 02:06, Jakob Bornecrantz  wrote:
> > Signed-off-by: Jakob Bornecrantz 

> not sure if still needed or not, but

> Reviewed-by: Dave Airlie 
> > ---
> >  src/gallium/drivers/virgl/virgl_hw.h | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/src/gallium/drivers/virgl/virgl_hw.h
b/src/gallium/drivers/virgl/virgl_hw.h
> > index 93849c03dd..180dead80a 100644
> > --- a/src/gallium/drivers/virgl/virgl_hw.h
> > +++ b/src/gallium/drivers/virgl/virgl_hw.h
> > @@ -83,6 +83,7 @@ enum virgl_formats {
> > VIRGL_FORMAT_L8A8_SRGB   = 96,
> > VIRGL_FORMAT_B8G8R8A8_SRGB   = 100,
> > VIRGL_FORMAT_B8G8R8X8_SRGB   = 101,
> > +   VIRGL_FORMAT_R8G8B8A8_SRGB   = 104,
> >
> > /* compressed formats */
> > VIRGL_FORMAT_DXT1_RGB= 105,
> > --
> > 2.14.1
> >
> > ___
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> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> ___
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Re: [Mesa-dev] [PATCH 9.5/17] squash! i965/miptree: Unify aux buffer allocation

[Nanley Chery]

On Wed, May 16, 2018 at 09:11:38AM +0300, Pohjolainen, Topi wrote:
> On Wed, May 09, 2018 at 10:47:24AM -0700, Nanley Chery wrote:
> > v2: Inline the switch statement (Jason)
> > 
> > Reviewed-by: Jason Ekstrand 
> > ---
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 90 ---
> >  1 file changed, 38 insertions(+), 52 deletions(-)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > index f78b862a702..b5d7d691ecc 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -1777,30 +1777,37 @@ intel_miptree_level_enable_hiz(struct brw_context 
> > *brw,
> >  }
> >  
> >  
> > -/* Returns true iff all params are successfully filled. */
> > -static bool
> > -get_aux_buf_params(const struct brw_context *brw,
> > -   const struct intel_mipmap_tree *mt,
> > -   enum isl_aux_state *initial_state,
> > -   uint8_t *memset_value,
> > -   struct isl_surf *aux_surf)
> > +/**
> > + * Allocate the initial aux surface for a miptree based on mt->aux_usage
> > + *
> > + * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
> > + * create the auxiliary surfaces up-front.  CCS_D, on the other hand, can 
> > only
> > + * compress clear color so we wait until an actual fast-clear to allocate 
> > it.
> > + */
> > +bool
> > +intel_miptree_alloc_aux(struct brw_context *brw,
> > +struct intel_mipmap_tree *mt)
> >  {
> > -   assert(initial_state && memset_value && aux_surf);
> > +   assert(mt->aux_buf == NULL);
> > +
> > +   /* Get the aux buf allocation parameters for this miptree. */
> > +   enum isl_aux_state initial_state;
> > +   uint8_t memset_value;
> > +   struct isl_surf aux_surf;
> > +   bool aux_surf_ok;
> >  
> > switch (mt->aux_usage) {
> > case ISL_AUX_USAGE_NONE:
> > -  aux_surf->size = 0;
> > -  return true;
> > +  aux_surf.size = 0;
> > +  aux_surf_ok = true;
> > +  break;
> > case ISL_AUX_USAGE_HIZ:
> >assert(!_mesa_is_format_color_format(mt->format));
> >  
> > -  *initial_state = ISL_AUX_STATE_AUX_INVALID;
> > -  {
> > - MAYBE_UNUSED bool ok =
> > -isl_surf_get_hiz_surf(>isl_dev, >surf, aux_surf);
> > - assert(ok);
> > -  }
> > -  return true;
> > +  initial_state = ISL_AUX_STATE_AUX_INVALID;
> > +  aux_surf_ok = isl_surf_get_hiz_surf(>isl_dev, >surf, 
> > _surf);
> > +  assert(aux_surf_ok);
> > +  break;
> > case ISL_AUX_USAGE_MCS:
> >assert(_mesa_is_format_color_format(mt->format));
> >assert(brw->screen->devinfo.gen >= 7); /* MCS only used on Gen7+ */
> > @@ -1817,14 +1824,11 @@ get_aux_buf_params(const struct brw_context *brw,
> > * Note: the clear value for MCS buffers is all 1's, so we memset to
> > * 0xff.
> > */
> > -  *initial_state = ISL_AUX_STATE_CLEAR;
> > -  *memset_value = 0xFF;
> > -  {
> > - MAYBE_UNUSED bool ok =
> > -isl_surf_get_mcs_surf(>isl_dev, >surf, aux_surf);
> > - assert(ok);
> > -  }
> > -  return true;
> > +  initial_state = ISL_AUX_STATE_CLEAR;
> > +  memset_value = 0xFF;
> > +  aux_surf_ok = isl_surf_get_mcs_surf(>isl_dev, >surf, 
> > _surf);
> > +  assert(aux_surf_ok);
> > +  break;
> > case ISL_AUX_USAGE_CCS_D:
> > case ISL_AUX_USAGE_CCS_E:
> >assert(_mesa_is_format_color_format(mt->format));
> > @@ -1839,36 +1843,18 @@ get_aux_buf_params(const struct brw_context *brw,
> > * A CCS value of 0 indicates that the corresponding block is in the
> > * pass-through state which is what we want.
> > *
> > -   * For CCS_D, do the same thing. On gen9+, this avoids having any 
> > undefined
> > -   * bits in the aux buffer.
> > +   * For CCS_D, do the same thing. On gen9+, this avoids having any
> > +   * undefined bits in the aux buffer.
> > */
> > -  *initial_state = ISL_AUX_STATE_PASS_THROUGH;
> > -  *memset_value = 0;
> > -  return isl_surf_get_ccs_surf(>isl_dev, >surf, aux_surf, 0);
> > +  initial_state = ISL_AUX_STATE_PASS_THROUGH;
> > +  memset_value = 0;
> > +  aux_surf_ok =
> > + isl_surf_get_ccs_surf(>isl_dev, >surf, _surf, 0);
> 
> Should we assert here also?
> 
>assert(aux_surf_ok);
> 

We can't at the moment. One example that would cause
isl_surf_get_ccs_surf() to return false is where we're on gen8 and we
attempt to fast-clear level 0 of a 3D texture.

> > +  break;
> > }
> >  
> > -   unreachable("Invalid aux usage");
> > -}
> > -
> > -
> > -/**
> > - * Allocate the initial aux surface for a miptree based on mt->aux_usage
> > - *
> > - * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
> > - * create the auxiliary surfaces up-front.  CCS_D, on the other 

[Mesa-dev] [PATCH 3/5] swr/rast: fix VCVTPD2PS generation for AVX512

[Alok Hota]

---
 .../swr/rasterizer/jitter/functionpasses/lower_x86.cpp   | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git 
a/src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp 
b/src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp
index 3caea67..e0296f6 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp
@@ -265,8 +265,16 @@ namespace SwrJit
 // Assuming the intrinsics are consistent and place the src 
operand and mask last in the argument list.
 if (mTarget == AVX512)
 {
-args.push_back(GetZeroVec(vecWidth, pElemTy));
-args.push_back(GetMask(vecWidth));
+if (pFunc->getName().equals("meta.intrinsic.VCVTPD2PS")) {
+args.push_back(GetZeroVec(W256, 
pCallInst->getType()->getScalarType()));
+args.push_back(GetMask(W256));
+// for AVX512 VCVTPD2PS, we also have to add rounding 
mode
+args.push_back(B->C(_MM_FROUND_TO_NEAREST_INT |
+_MM_FROUND_NO_EXC));
+} else {
+args.push_back(GetZeroVec(vecWidth, pElemTy));
+args.push_back(GetMask(vecWidth));
+}
 }
 
 return B->CALLA(pIntrin, args);
-- 
2.7.4

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[Mesa-dev] [PATCH 4/5] swr/rast: Whitespace and tab-to-spaces changes

[Alok Hota]

---
 .../drivers/swr/rasterizer/jitter/JitManager.cpp   |  1 -
 .../swr/rasterizer/jitter/builder_gfx_mem.cpp  | 27 --
 .../swr/rasterizer/jitter/builder_gfx_mem.h|  2 +-
 .../drivers/swr/rasterizer/jitter/builder_mem.cpp  |  1 -
 .../rasterizer/jitter/functionpasses/lower_x86.cpp |  4 ++--
 5 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp 
b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
index efb747a..e9412b1 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
@@ -580,7 +580,6 @@ int ExecUnhookedProcess(const std::string& CmdLine, 
std::string* pStdOut, std::s
 return ExecCmd(CmdLine, "", pStdOut, pStdErr);
 }
 
-
 /// notifyObjectCompiled - Provides a pointer to compiled code for Module M.
 void JitCache::notifyObjectCompiled(const llvm::Module *M, 
llvm::MemoryBufferRef Obj)
 {
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_gfx_mem.cpp 
b/src/gallium/drivers/swr/rasterizer/jitter/builder_gfx_mem.cpp
index c6d0619..3013bc5 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/builder_gfx_mem.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/builder_gfx_mem.cpp
@@ -57,14 +57,15 @@ namespace SwrJit
 
 
 //
-/// @brief Generate a masked gather operation in LLVM IR.  If not  
+/// @brief Generate a masked gather operation in LLVM IR.  If not
 /// supported on the underlying platform, emulate it with loads
 /// @param vSrc - SIMD wide value that will be loaded if mask is invalid
 /// @param pBase - Int8* base VB address pointer value
 /// @param vIndices - SIMD wide value of VB byte offsets
 /// @param vMask - SIMD wide mask that controls whether to access memory 
or the src values
 /// @param scale - value to scale indices by
-Value* BuilderGfxMem::GATHERPS(Value* vSrc, Value* pBase, Value* vIndices, 
Value* vMask, uint8_t scale, JIT_MEM_CLIENT usage)
+Value* BuilderGfxMem::GATHERPS(Value* vSrc, Value* pBase, Value* vIndices, 
Value* vMask,
+   uint8_t scale, JIT_MEM_CLIENT usage)
 {
 // address may be coming in as 64bit int now so get the pointer
 if (pBase->getType() == mInt64Ty)
@@ -77,14 +78,15 @@ namespace SwrJit
 }
 
 //
-/// @brief Generate a masked gather operation in LLVM IR.  If not  
+/// @brief Generate a masked gather operation in LLVM IR.  If not
 /// supported on the underlying platform, emulate it with loads
 /// @param vSrc - SIMD wide value that will be loaded if mask is invalid
 /// @param pBase - Int8* base VB address pointer value
 /// @param vIndices - SIMD wide value of VB byte offsets
 /// @param vMask - SIMD wide mask that controls whether to access memory 
or the src values
 /// @param scale - value to scale indices by
-Value* BuilderGfxMem::GATHERDD(Value* vSrc, Value* pBase, Value* vIndices, 
Value* vMask, uint8_t scale, JIT_MEM_CLIENT usage)
+Value* BuilderGfxMem::GATHERDD(Value* vSrc, Value* pBase, Value* vIndices, 
Value* vMask,
+   uint8_t scale, JIT_MEM_CLIENT usage)
 {
 
 // address may be coming in as 64bit int now so get the pointer
@@ -98,38 +100,39 @@ namespace SwrJit
 }
 
 
-Value* BuilderGfxMem::OFFSET_TO_NEXT_COMPONENT(Value* base, Constant 
*offset)
+Value* BuilderGfxMem::OFFSET_TO_NEXT_COMPONENT(Value* base, Constant* 
offset)
 {
 return ADD(base, offset);
 }
-
-Value* BuilderGfxMem::GEP(Value* Ptr, Value* Idx, Type *Ty, const Twine 
)
+
+Value* BuilderGfxMem::GEP(Value* Ptr, Value* Idx, Type* Ty, const Twine& 
Name)
 {
 Ptr = TranslationHelper(Ptr, Ty);
 return Builder::GEP(Ptr, Idx, nullptr, Name);
 }
 
-Value* BuilderGfxMem::GEP(Type *Ty, Value* Ptr, Value* Idx, const Twine 
)
+Value* BuilderGfxMem::GEP(Type* Ty, Value* Ptr, Value* Idx, const Twine& 
Name)
 {
 Ptr = TranslationHelper(Ptr, Ty);
 return Builder::GEP(Ty, Ptr, Idx, Name);
 }
 
-Value* BuilderGfxMem::GEP(Value* Ptr, const std::initializer_list 
, Type *Ty)
+Value* BuilderGfxMem::GEP(Value* Ptr, const std::initializer_list& 
indexList, Type* Ty)
 {
 Ptr = TranslationHelper(Ptr, Ty);
 return Builder::GEP(Ptr, indexList);
 }
 
-Value* BuilderGfxMem::GEP(Value* Ptr, const 
std::initializer_list , Type *Ty)
+Value* BuilderGfxMem::GEP(Value* Ptr, const 
std::initializer_list& indexList, Type* Ty)
 {
 Ptr = TranslationHelper(Ptr, Ty);
 return Builder::GEP(Ptr, indexList);
 }
 
-Value* BuilderGfxMem::TranslationHelper(Value* Ptr, Type *Ty)
+Value* BuilderGfxMem::TranslationHelper(Value* 

[Mesa-dev] [PATCH 5/5] swr/rast: Added FEClipRectangles event

[Alok Hota]

and also added some comments
---
 src/gallium/drivers/swr/rasterizer/core/rdtsc_core.cpp | 1 +
 src/gallium/drivers/swr/rasterizer/core/rdtsc_core.h   | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.cpp 
b/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.cpp
index f1355dd..f289a31 100644
--- a/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.cpp
@@ -54,6 +54,7 @@ BUCKET_DESC gCoreBuckets[] = {
 { "FEClipPoints", "", false, 0x },
 { "FEClipLines", "", false, 0x },
 { "FEClipTriangles", "", false, 0x },
+{ "FEClipRectangles", "", false, 0x },
 { "FECullZeroAreaAndBackface", "", false, 0x },
 { "FECullBetweenCenters", "", false, 0x },
 { "FEEarlyRastEnter", "", false, 0x },
diff --git a/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.h 
b/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.h
index 3a7ee4c..704da65 100644
--- a/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.h
+++ b/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.h
@@ -29,6 +29,9 @@
 
 #include 
 
+///
+// NOTE:  This enum MUST be kept in sync with gCoreBuckets in rdtsc_core.cpp
+///
 enum CORE_BUCKETS
 {
 APIClearRenderTarget,
-- 
2.7.4

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[Mesa-dev] [PATCH 2/5] swr/rast: Rectlist support for GS

[Alok Hota]

Add rectlist as an option for GS.  Needed to support some driver
optimizations.
---
 src/gallium/drivers/swr/rasterizer/core/clip.cpp   | 24 
 src/gallium/drivers/swr/rasterizer/core/clip.h |  6 ++
 .../drivers/swr/rasterizer/core/frontend.cpp   |  2 +
 src/gallium/drivers/swr/rasterizer/core/pa.h   | 68 ++
 .../drivers/swr/rasterizer/core/rdtsc_core.h   |  1 +
 src/gallium/drivers/swr/rasterizer/core/state.h|  2 +-
 6 files changed, 102 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/clip.cpp 
b/src/gallium/drivers/swr/rasterizer/core/clip.cpp
index 780ca15..e6c2218 100644
--- a/src/gallium/drivers/swr/rasterizer/core/clip.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/clip.cpp
@@ -160,6 +160,15 @@ int ClipTriToPlane( const float *pInPts, int numInPts,
 return i;
 }
 
+void ClipRectangles(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t workerId, 
simdvector prims[], uint32_t primMask,
+simdscalari const , simdscalari const , simdscalari 
const )
+{
+RDTSC_BEGIN(FEClipRectangles, pDC->drawId);
+Clipper clipper(workerId, pDC);
+clipper.ExecuteStage(pa, prims, primMask, primId, viewportIdx, rtIdx);
+RDTSC_END(FEClipRectangles, 1);
+}
+
 void ClipTriangles(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t workerId, 
simdvector prims[], uint32_t primMask,
simdscalari const , simdscalari const , 
simdscalari const )
 {
@@ -188,6 +197,21 @@ void ClipPoints(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simdvector p
 }
 
 #if USE_SIMD16_FRONTEND
+void SIMDCALL ClipRectangles_simd16(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simd16vector prims[], uint32_t primMask,
+simd16scalari const , simd16scalari const , 
simd16scalari const )
+{
+RDTSC_BEGIN(FEClipRectangles, pDC->drawId);
+
+enum { VERTS_PER_PRIM = 3 };
+
+Clipper clipper(workerId, pDC);
+
+pa.useAlternateOffset = false;
+clipper.ExecuteStage(pa, prims, primMask, primId, viewportIdx, rtIdx);
+
+RDTSC_END(FEClipRectangles, 1);
+}
+
 void SIMDCALL ClipTriangles_simd16(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simd16vector prims[], uint32_t primMask,
simd16scalari const , simd16scalari 
const , simd16scalari const )
 {
diff --git a/src/gallium/drivers/swr/rasterizer/core/clip.h 
b/src/gallium/drivers/swr/rasterizer/core/clip.h
index 0f8399c..90ae426 100644
--- a/src/gallium/drivers/swr/rasterizer/core/clip.h
+++ b/src/gallium/drivers/swr/rasterizer/core/clip.h
@@ -531,6 +531,10 @@ public:
 {
 clipTopology = TOP_POINT_LIST;
 }
+else if (pa.binTopology == TOP_RECT_LIST)
+{
+clipTopology = TOP_RECT_LIST;
+}
 }
 else if (NumVertsPerPrim == 2)
 {
@@ -1149,10 +1153,12 @@ private:
 
 
 // pipeline stage functions
+void ClipRectangles(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t workerId, 
simdvector prims[], uint32_t primMask, simdscalari const , simdscalari 
const , simdscalari const );
 void ClipTriangles(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t workerId, 
simdvector prims[], uint32_t primMask, simdscalari const , simdscalari 
const , simdscalari const );
 void ClipLines(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t workerId, simdvector 
prims[], uint32_t primMask, simdscalari const , simdscalari const 
, simdscalari const );
 void ClipPoints(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t workerId, simdvector 
prims[], uint32_t primMask, simdscalari const , simdscalari const 
, simdscalari const );
 #if USE_SIMD16_FRONTEND
+void SIMDCALL ClipRectangles_simd16(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simd16vector prims[], uint32_t primMask, simd16scalari const , 
simd16scalari const , simd16scalari const );
 void SIMDCALL ClipTriangles_simd16(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simd16vector prims[], uint32_t primMask, simd16scalari const , 
simd16scalari const , simd16scalari const );
 void SIMDCALL ClipLines_simd16(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simd16vector prims[], uint32_t primMask, simd16scalari const , 
simd16scalari const , simd16scalari const );
 void SIMDCALL ClipPoints_simd16(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simd16vector prims[], uint32_t primMask, simd16scalari const , 
simd16scalari const , simd16scalari const );
diff --git a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp 
b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
index 1847c3e..47c0662 100644
--- a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
@@ -868,6 +868,7 @@ static void GeometryShaderStage(
 {
 switch (pState->outputTopology)
 {
+case TOP_RECT_LIST: pfnClipFunc = ClipRectangles_simd16; break;
 case TOP_TRIANGLE_STRIP:pfnClipFunc = ClipTriangles_simd16; 

[Mesa-dev] [PATCH 1/5] swr/rast: Remove unneeded virtual from methods

[Alok Hota]

---
 src/gallium/drivers/swr/rasterizer/jitter/JitManager.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h 
b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
index 54a25d8..152776a 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
+++ b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
@@ -108,12 +108,12 @@ public:
 }
 
 /// notifyObjectCompiled - Provides a pointer to compiled code for Module 
M.
-virtual void notifyObjectCompiled(const llvm::Module *M, 
llvm::MemoryBufferRef Obj);
+void notifyObjectCompiled(const llvm::Module *M, llvm::MemoryBufferRef 
Obj) override;
 
 /// Returns a pointer to a newly allocated MemoryBuffer that contains the
 /// object which corresponds with Module M, or 0 if an object is not
 /// available.
-virtual std::unique_ptr getObject(const llvm::Module* 
M);
+std::unique_ptr getObject(const llvm::Module* M) 
override;
 
 private:
 std::string mCpu;
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 04/17] i965/miptree: Initialize the indirect clear color to zero

[Nanley Chery]

On Wed, May 16, 2018 at 09:02:51AM +0300, Pohjolainen, Topi wrote:
> On Tue, May 08, 2018 at 02:05:37PM -0700, Nanley Chery wrote:
> > On Tue, May 08, 2018 at 08:31:39AM +0300, Pohjolainen, Topi wrote:
> > > On Mon, May 07, 2018 at 10:11:39AM -0700, Nanley Chery wrote:
> > > > On Mon, May 07, 2018 at 11:30:15AM +0300, Pohjolainen, Topi wrote:
> > > > > On Thu, May 03, 2018 at 12:03:51PM -0700, Nanley Chery wrote:
> > > > > > The indirect clear color isn't correctly tracked in
> > > > > > intel_miptree::fast_clear_color. The initial value of 
> > > > > > ::fast_clear_color
> > > > > > is zero, while that of the indirect clear color is undefined or
> > > > > > non-zero.
> > > > > > 
> > > > > > Topi Pohjolainen discovered this issue with MCS buffers. This issue 
> > > > > > is
> > > > > > apparent when fast-clearing an MCS buffer for the first time with
> > > > > > glClearColor = {0.0,}. Although the indirect clear color is 
> > > > > > non-zero,
> > > > > > the initial aux state of the MCS is CLEAR and the tracked clear 
> > > > > > color is
> > > > > > zero, so we avoid updating the indirect clear color with {0.0,}.
> > > > > > 
> > > > > > Make the indirect clear color match the initial value of
> > > > > > ::fast_clear_color.
> > > > > > 
> > > > > > ---
> > > > > > 
> > > > > > Hey Topi,
> > > > > > 
> > > > > > Just FYI, this patch should fix the MCS bug you reported earlier.
> > > > > > 
> > > > > >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 33 
> > > > > > ++-
> > > > > >  1 file changed, 22 insertions(+), 11 deletions(-)
> > > > > > 
> > > > > > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> > > > > > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > > > > index 5d3ee569bd8..e70c9ff1ef4 100644
> > > > > > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > > > > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > > > > @@ -978,11 +978,11 @@ create_ccs_buf_for_image(struct brw_context 
> > > > > > *brw,
> > > > > >  * system with CCS, we don't have the extra space at the end of 
> > > > > > the aux
> > > > > >  * buffer. So create a new bo here that will store that clear 
> > > > > > color.
> > > > > >  */
> > > > > > -   const struct gen_device_info *devinfo = >screen->devinfo;
> > > > > > -   if (devinfo->gen >= 10) {
> > > > > > +   if (brw->isl_dev.ss.clear_color_state_size > 0) {
> > > > > >mt->aux_buf->clear_color_bo =
> > > > > > - brw_bo_alloc(brw->bufmgr, "clear_color_bo",
> > > > > > -  brw->isl_dev.ss.clear_color_state_size);
> > > > > > + brw_bo_alloc_tiled(brw->bufmgr, "clear_color_bo",
> > > > > > +brw->isl_dev.ss.clear_color_state_size,
> > > > > > +I915_TILING_NONE, 0, BO_ALLOC_ZEROED);
> > > > > >if (!mt->aux_buf->clear_color_bo) {
> > > > > >   free(mt->aux_buf);
> > > > > >   mt->aux_buf = NULL;
> > > > > > @@ -1673,9 +1673,9 @@ intel_alloc_aux_buffer(struct brw_context 
> > > > > > *brw,
> > > > > >  
> > > > > > buf->size = aux_surf->size;
> > > > > >  
> > > > > > -   const struct gen_device_info *devinfo = >screen->devinfo;
> > > > > > -   if (devinfo->gen >= 10) {
> > > > > > -  /* On CNL, instead of setting the clear color in the 
> > > > > > SURFACE_STATE, we
> > > > > > +   const bool has_indirect_clear = 
> > > > > > brw->isl_dev.ss.clear_color_state_size > 0;
> > > > > > +   if (has_indirect_clear) {
> > > > > > +  /* On CNL+, instead of setting the clear color in the 
> > > > > > SURFACE_STATE, we
> > > > > > * will set a pointer to a dword somewhere that contains the 
> > > > > > color. So,
> > > > > > * allocate the space for the clear color value here on the 
> > > > > > aux buffer.
> > > > > > */
> > > > > > @@ -1698,7 +1698,8 @@ intel_alloc_aux_buffer(struct brw_context 
> > > > > > *brw,
> > > > > > }
> > > > > >  
> > > > > > /* Initialize the bo to the desired value */
> > > > > > -   if (wants_memset) {
> > > > > > +   const bool needs_memset = wants_memset || has_indirect_clear;
> > > > > > +   if (needs_memset) {
> > > > > >assert(!(alloc_flags & BO_ALLOC_BUSY));
> > > > > >  
> > > > > >void *map = brw_bo_map(brw, buf->bo, MAP_WRITE | MAP_RAW);
> > > > > > @@ -1706,11 +1707,21 @@ intel_alloc_aux_buffer(struct brw_context 
> > > > > > *brw,
> > > > > >   intel_miptree_aux_buffer_free(buf);
> > > > > >   return NULL;
> > > > > >}
> > > > > > -  memset(map, memset_value, mt->aux_buf->size);
> > > > > > +
> > > > > > +  /* Memset the aux_surf portion of the BO. */
> > > > > > +  if (wants_memset)
> > > > > > + memset(map, memset_value, aux_surf->size);
> > > > > > +
> > > > > > +  /* Zero the indirect clear color to match 
> > > > > > ::fast_clear_color. */
> > > > > > +  if (has_indirect_clear) {
> > > > > > + memset((char *)map + 

Re: [Mesa-dev] [PATCH 2/2] radv: do not emit unnecessary ES output stores

[Bas Nieuwenhuizen]

Thanks!

Reviewed-by: Bas Nieuwenhuizen 

for the series.

On Wed, May 16, 2018 at 5:43 PM, Samuel Pitoiset
 wrote:
> GFX9:
> Totals from affected shaders:
> SGPRS: 472 -> 464 (-1.69 %)
> VGPRS: 576 -> 584 (1.39 %)
> Code Size: 45432 -> 44324 (-2.44 %) bytes
> Max Waves: 40 -> 40 (0.00 %)
>
> VI:
> SGPRS: 720 -> 720 (0.00 %)
> VGPRS: 728 -> 728 (0.00 %)
> Code Size: 45348 -> 43992 (-2.99 %) bytes
> Max Waves: 120 -> 120 (0.00 %)
>
> This affects Rise of Tomb Raider and the three Vulkan demos
> that use a geometry shader (geometryshader, deferredshadows
> and viewportarray).
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_nir_to_llvm.c | 18 +++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
> b/src/amd/vulkan/radv_nir_to_llvm.c
> index bfae2a489e..2c3abc2109 100644
> --- a/src/amd/vulkan/radv_nir_to_llvm.c
> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> @@ -2580,6 +2580,8 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
> }
>
> for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
> +   unsigned output_usage_mask =
> +   ctx->shader_info->info.vs.output_usage_mask[i];
> LLVMValueRef dw_addr = NULL;
> LLVMValueRef *out_ptr = >abi.outputs[i * 4];
> int param_index;
> @@ -2588,8 +2590,10 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
> if (!(ctx->output_mask & (1ull << i)))
> continue;
>
> -   if (i == VARYING_SLOT_CLIP_DIST0)
> +   if (i == VARYING_SLOT_CLIP_DIST0) {
> length = ctx->num_output_clips + 
> ctx->num_output_culls;
> +   output_usage_mask = (1 << length) - 1;
> +   }
>
> param_index = shader_io_get_unique_index(i);
>
> @@ -2598,14 +2602,22 @@ handle_es_outputs_post(struct radv_shader_context 
> *ctx,
>LLVMConstInt(ctx->ac.i32, 
> param_index * 4, false),
>"");
> }
> +
> for (j = 0; j < length; j++) {
> +   if (!(output_usage_mask & (1 << j)))
> +   continue;
> +
> LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, 
> out_ptr[j], "");
> out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, 
> ctx->ac.i32, "");
>
> if (ctx->ac.chip_class  >= GFX9) {
> -   ac_lds_store(>ac, dw_addr,
> +   LLVMValueRef dw_addr_offset =
> +   LLVMBuildAdd(ctx->ac.builder, dw_addr,
> +LLVMConstInt(ctx->ac.i32,
> + j, false), 
> "");
> +
> +   ac_lds_store(>ac, dw_addr_offset,
>  LLVMBuildLoad(ctx->ac.builder, 
> out_ptr[j], ""));
> -   dw_addr = LLVMBuildAdd(ctx->ac.builder, 
> dw_addr, ctx->ac.i32_1, "");
> } else {
> ac_build_buffer_store_dword(>ac,
> ctx->esgs_ring,
> --
> 2.17.0
>
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Re: [Mesa-dev] [PATCH 6/9] intel/blorp: Make blorp_ccs_ambiguate just an internal helper

[Jason Ekstrand]

On Wed, May 16, 2018 at 4:00 AM, Iago Toral  wrote:

> On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote:
> > Now that anv uses blorp_ccs_op for everything, we no longer need to
> > expose the ccs_ambiguate function directly.  It's much better tucked
> > away as an implementation detail.
> > ---
> >  src/intel/blorp/blorp.h   |  5 -
> >  src/intel/blorp/blorp_clear.c | 21 ++---
> >  2 files changed, 10 insertions(+), 16 deletions(-)
> >
> > diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
> > index 8c775bf..e27ea7e 100644
> > --- a/src/intel/blorp/blorp.h
> > +++ b/src/intel/blorp/blorp.h
> > @@ -208,11 +208,6 @@ blorp_ccs_op(struct blorp_batch *batch,
> >   enum isl_aux_op ccs_op);
> >
> >  void
> > -blorp_ccs_ambiguate(struct blorp_batch *batch,
> > -struct blorp_surf *surf,
> > -uint32_t level, uint32_t layer);
> > -
> > -void
> >  blorp_mcs_partial_resolve(struct blorp_batch *batch,
> >struct blorp_surf *surf,
> >enum isl_format format,
> > diff --git a/src/intel/blorp/blorp_clear.c
> > b/src/intel/blorp/blorp_clear.c
> > index 6f5549f..39bc0c6 100644
> > --- a/src/intel/blorp/blorp_clear.c
> > +++ b/src/intel/blorp/blorp_clear.c
> > @@ -814,6 +814,11 @@ blorp_clear_attachments(struct blorp_batch
> > *batch,
> > batch->blorp->exec(batch, );
> >  }
> >
> > +static void
> > +blorp_legacy_ccs_ambiguate(struct blorp_batch *batch,
> > +   struct blorp_surf *surf,
> > +   uint32_t level, uint32_t layer);
> > +
> >  void
> >  blorp_ccs_op(struct blorp_batch *batch,
> >   struct blorp_surf *surf, uint32_t level,
> > @@ -835,7 +840,7 @@ blorp_ccs_op(struct blorp_batch *batch,
> > * mess to another function.
> > */
> >for (uint32_t a = 0; a < num_layers; a++)
> > - blorp_ccs_ambiguate(batch, surf, level, start_layer + a);
> > + blorp_legacy_ccs_ambiguate(batch, surf, level, start_layer
> > + a);
> >return;
> > }
> >
> > @@ -1022,17 +1027,11 @@ blorp_mcs_partial_resolve(struct blorp_batch
> > *batch,
> >   * for a given layer/level of a surface to 0x0 which is the
> > "uncompressed"
> >   * state which tells the sampler to go look at the main surface.
> >   */
> > -void
> > -blorp_ccs_ambiguate(struct blorp_batch *batch,
> > -struct blorp_surf *surf,
> > -uint32_t level, uint32_t layer)
> > +static void
> > +blorp_legacy_ccs_ambiguate(struct blorp_batch *batch,
> > +   struct blorp_surf *surf,
> > +   uint32_t level, uint32_t layer)
> >  {
> > -   if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 10) {
> > -  /* On gen10 and above, we have a hardware resolve op for this
> > */
> > -  return blorp_ccs_op(batch, surf, level, layer, 1,
> > -  surf->surf->format, ISL_AUX_OP_AMBIGUATE);
> > -   }
> > -
>
> Since we don't want to call this in gen10+, would it make sense to an
> assert for gen < 10?
>

It does work on gen10 and 11 (and we used it on gen 10 for a while).  I'll
make it gen < 12.
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[Mesa-dev] [PATCH 2/2] radv: do not emit unnecessary ES output stores

[Samuel Pitoiset]

GFX9:
Totals from affected shaders:
SGPRS: 472 -> 464 (-1.69 %)
VGPRS: 576 -> 584 (1.39 %)
Code Size: 45432 -> 44324 (-2.44 %) bytes
Max Waves: 40 -> 40 (0.00 %)

VI:
SGPRS: 720 -> 720 (0.00 %)
VGPRS: 728 -> 728 (0.00 %)
Code Size: 45348 -> 43992 (-2.99 %) bytes
Max Waves: 120 -> 120 (0.00 %)

This affects Rise of Tomb Raider and the three Vulkan demos
that use a geometry shader (geometryshader, deferredshadows
and viewportarray).

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_nir_to_llvm.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index bfae2a489e..2c3abc2109 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2580,6 +2580,8 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
}
 
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
+   unsigned output_usage_mask =
+   ctx->shader_info->info.vs.output_usage_mask[i];
LLVMValueRef dw_addr = NULL;
LLVMValueRef *out_ptr = >abi.outputs[i * 4];
int param_index;
@@ -2588,8 +2590,10 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
if (!(ctx->output_mask & (1ull << i)))
continue;
 
-   if (i == VARYING_SLOT_CLIP_DIST0)
+   if (i == VARYING_SLOT_CLIP_DIST0) {
length = ctx->num_output_clips + ctx->num_output_culls;
+   output_usage_mask = (1 << length) - 1;
+   }
 
param_index = shader_io_get_unique_index(i);
 
@@ -2598,14 +2602,22 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
   LLVMConstInt(ctx->ac.i32, 
param_index * 4, false),
   "");
}
+
for (j = 0; j < length; j++) {
+   if (!(output_usage_mask & (1 << j)))
+   continue;
+
LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, 
out_ptr[j], "");
out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, 
ctx->ac.i32, "");
 
if (ctx->ac.chip_class  >= GFX9) {
-   ac_lds_store(>ac, dw_addr,
+   LLVMValueRef dw_addr_offset =
+   LLVMBuildAdd(ctx->ac.builder, dw_addr,
+LLVMConstInt(ctx->ac.i32,
+ j, false), 
"");
+
+   ac_lds_store(>ac, dw_addr_offset,
 LLVMBuildLoad(ctx->ac.builder, 
out_ptr[j], ""));
-   dw_addr = LLVMBuildAdd(ctx->ac.builder, 
dw_addr, ctx->ac.i32_1, "");
} else {
ac_build_buffer_store_dword(>ac,
ctx->esgs_ring,
-- 
2.17.0

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[Mesa-dev] [PATCH 1/2] radv: do not emit unnecessary GS output stores

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_nir_to_llvm.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 95bc860e66..bfae2a489e 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1684,6 +1684,8 @@ visit_emit_vertex(struct ac_shader_abi *abi, unsigned 
stream, LLVMValueRef *addr
/* loop num outputs */
idx = 0;
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
+   unsigned output_usage_mask =
+   ctx->shader_info->info.gs.output_usage_mask[i];
LLVMValueRef *out_ptr = [i * 4];
int length = 4;
int slot = idx;
@@ -1697,8 +1699,13 @@ visit_emit_vertex(struct ac_shader_abi *abi, unsigned 
stream, LLVMValueRef *addr
length = ctx->num_output_clips + ctx->num_output_culls;
if (length > 4)
slot_inc = 2;
+   output_usage_mask = (1 << length) - 1;
}
+
for (unsigned j = 0; j < length; j++) {
+   if (!(output_usage_mask & (1 << j)))
+   continue;
+
LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
 out_ptr[j], "");
LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot 
* 4 + j) * ctx->gs_max_out_vertices, false);
-- 
2.17.0

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Re: [Mesa-dev] [PATCH v2 1/2] cast the "GLenum16" to "GLint" to avoid compile warning on android

[Brian Paul]

On 05/16/2018 01:02 AM, jenny.q.cao wrote:

force cast the I to GLint to avoid the compile warning when type is GLenum16, in
vendor/intel/external/mesa3d-intel/src/mesa/main/get.c:3005:19: warning: 
comparison of constant -32768 with
expression of type 'GLenum16' (aka 'unsigned short') is always false 
-Wtautologicalia-constant-out-of-range-compare

Tests: compilation without this warning
Signed-off-by: jenny.q.cao 
---
  src/mesa/main/get.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 90ab7ca60f8b..5f9a60b0801c 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -3002,7 +3002,7 @@ _mesa_GetFixedv(GLenum pname, GLfixed *params)
break;
  
 case TYPE_ENUM16:

-  params[0] = INT_TO_FIXED(((GLenum16 *) p)[0]);
+  params[0] = INT_TO_FIXED((GLint)(((GLenum16 *) p)[0]));
break;
  
 case TYPE_INT_N:




Reviewed-by: Brian Paul 

I'll clean up the commit message a bit and commit this soon.  Thanks.
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Re: [Mesa-dev] [PATCH] android: enable VK_ANDROID_native_buffer

[Jason Ekstrand]

On May 15, 2018 22:59:20 Tapani Pälli  wrote:


On 05/16/2018 08:46 AM, Jason Ekstrand wrote:

On Tue, May 15, 2018 at 10:42 PM, Tapani Pälli > wrote:

Patch changes entrypoints generator to not skip this extension even
though it is set as disabled in the xml. We also need compilation
flag VK_USE_PLATFORM_ANDROID_KHR to be enabled and a small fix to
vk_icd.h because of following compilation error:

vk_icd.h:116:5: error: must use 'struct' tag to refer to type
'ANativeWindow'

It looks like this extension got disabled in commit 69f447553c.

Signed-off-by: Tapani Pälli >
---
Android.common.mk    | 1 +
include/vulkan/vk_icd.h | 2 +-
src/intel/vulkan/anv_entrypoints_gen.py | 5 -
3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/Android.common.mk 
b/Android.common.mk 
index e8aed48c31..999e17789b 100644
--- a/Android.common.mk 
+++ b/Android.common.mk 
@@ -73,6 +73,7 @@ LOCAL_CFLAGS += \
   -DHAVE_ENDIAN_H \
   -DHAVE_ZLIB \
   -DMAJOR_IN_SYSMACROS \
+   -DVK_USE_PLATFORM_ANDROID_KHR \
   -fvisibility=hidden \
   -Wno-sign-compare

diff --git a/include/vulkan/vk_icd.h b/include/vulkan/vk_icd.h
index 7b54fb5774..77709c9f8d 100644
--- a/include/vulkan/vk_icd.h
+++ b/include/vulkan/vk_icd.h
@@ -113,7 +113,7 @@ typedef struct {

#ifdef VK_USE_PLATFORM_ANDROID_KHR
typedef struct {
-ANativeWindow* window;
+struct ANativeWindow* window;


Please submit a PR against the Vulkan-LoaderAndValidationLayers for
this.  I belive the core issue is that we're including it from C whereas
most people are using C++.


Yeah, that is the case. Will submit PR.


} VkIcdSurfaceAndroid;
#endif //VK_USE_PLATFORM_ANDROID_KHR

diff --git a/src/intel/vulkan/anv_entrypoints_gen.py
b/src/intel/vulkan/anv_entrypoints_gen.py
index d603ac1b20..53ffbe30b9 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -495,7 +495,10 @@ def get_entrypoints(doc,
entrypoints_to_defines, start_index):
if ext_name not in supported_exts:
continue

-if extension.attrib['supported'] != 'vulkan':
+# VK_ANDROID_native_buffer is set as 'disabled' but Mesa
+# supports it.
+if (extension.attrib['supported'] != 'vulkan' and
+ext_name != 'VK_ANDROID_native_buffer'):


Is this continue even needed anymore?  I honestly don't remember what
it's here for.


It is currently skipping only VK_ANDROID_native_buffer, I was not sure
if we want to get rid of it. Maybe it could only print warning in case
something is not enabled?


I think it's left over from when we had two XML files and wanted to skip 
the disabled version.  Now that we don't, we should be able to drop it 
entirely.





continue

ext = supported_exts[ext_name]
--
2.14.3

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// Tapani




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Re: [Mesa-dev] [PATCH v2] st/mesa: only define GLSL 1.4 for compat if driver supports it

[Grazvydas Ignotas]

On Wed, May 16, 2018 at 5:02 PM, Christian Gmeiner
 wrote:
> Currently GLSL 1.4 is defined for all gallium drivers even only
> GLSL 1.2 is supported as seen on etnaviv.
>
> v1 -> v2:
>  - use _min(..) as suggested by Lucas Stach and Michel Dänzer
>
> Fixes 4560aad780b ("mesa: add GLSLVersionCompat constant")

Should be "Fixes: ...".
See git log for examples.

Gražvydas
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Re: [Mesa-dev] [PATCH v2] st/mesa: only define GLSL 1.4 for compat if driver supports it

[Lucas Stach]

Am Mittwoch, den 16.05.2018, 16:02 +0200 schrieb Christian Gmeiner:
> Currently GLSL 1.4 is defined for all gallium drivers even only
> GLSL 1.2 is supported as seen on etnaviv.
> 
> v1 -> v2:
>  - use _min(..) as suggested by Lucas Stach and Michel Dänzer
> 
> Fixes 4560aad780b ("mesa: add GLSLVersionCompat constant")
> Signed-off-by: Christian Gmeiner 

Reviewed-by: Lucas Stach 

> ---
>  src/mesa/state_tracker/st_extensions.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/state_tracker/st_extensions.c 
> b/src/mesa/state_tracker/st_extensions.c
> index 19ef736e5b..2d56a88027 100644
> --- a/src/mesa/state_tracker/st_extensions.c
> +++ b/src/mesa/state_tracker/st_extensions.c
> @@ -936,7 +936,7 @@ void st_init_extensions(struct pipe_screen *screen,
>  
> /* Figure out GLSL support and set GLSLVersion to it. */
> consts->GLSLVersion = screen->get_param(screen, 
> PIPE_CAP_GLSL_FEATURE_LEVEL);
> -   consts->GLSLVersionCompat = 140;
> +   consts->GLSLVersionCompat = _min(consts->GLSLVersion, 140);
>  
> _mesa_override_glsl_version(consts);
>  
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[Mesa-dev] [PATCH] mesa: pipe attachment incomplete debug message to debug output

[Timothy Arceri]

---
 src/mesa/main/fbobject.c | 44 
 1 file changed, 26 insertions(+), 18 deletions(-)

diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index a63e8b8de52..82f7d522af9 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -656,8 +656,16 @@ _mesa_has_depthstencil_combined(const struct 
gl_framebuffer *fb)
  * For debug only.
  */
 static void
-att_incomplete(const char *msg)
+att_incomplete(struct gl_context *ctx, const char *msg)
 {
+   static GLuint msg_id;
+
+   _mesa_gl_debug(ctx, _id,
+  MESA_DEBUG_SOURCE_API,
+  MESA_DEBUG_TYPE_OTHER,
+  MESA_DEBUG_SEVERITY_MEDIUM,
+  "Attachment incomplete: %s\n", msg);
+
if (MESA_DEBUG_FLAGS & DEBUG_INCOMPLETE_FBO) {
   _mesa_debug(NULL, "attachment incomplete: %s\n", msg);
}
@@ -782,7 +790,7 @@ is_legal_depth_format(const struct gl_context *ctx, GLenum 
baseFormat)
  *   if GL_STENCIL, this is a stencil component attachment point.
  */
 static void
-test_attachment_completeness(const struct gl_context *ctx, GLenum format,
+test_attachment_completeness(struct gl_context *ctx, GLenum format,
  struct gl_renderbuffer_attachment *att)
 {
assert(format == GL_COLOR || format == GL_DEPTH || format == GL_STENCIL);
@@ -797,19 +805,19 @@ test_attachment_completeness(const struct gl_context 
*ctx, GLenum format,
   GLenum baseFormat;
 
   if (!texObj) {
- att_incomplete("no texobj");
+ att_incomplete(ctx, "no texobj");
  att->Complete = GL_FALSE;
  return;
   }
 
   texImage = texObj->Image[att->CubeMapFace][att->TextureLevel];
   if (!texImage) {
- att_incomplete("no teximage");
+ att_incomplete(ctx, "no teximage");
  att->Complete = GL_FALSE;
  return;
   }
   if (texImage->Width < 1 || texImage->Height < 1) {
- att_incomplete("teximage width/height=0");
+ att_incomplete(ctx, "teximage width/height=0");
  att->Complete = GL_FALSE;
  return;
   }
@@ -817,28 +825,28 @@ test_attachment_completeness(const struct gl_context 
*ctx, GLenum format,
   switch (texObj->Target) {
   case GL_TEXTURE_3D:
  if (att->Zoffset >= texImage->Depth) {
-att_incomplete("bad z offset");
+att_incomplete(ctx, "bad z offset");
 att->Complete = GL_FALSE;
 return;
  }
  break;
   case GL_TEXTURE_1D_ARRAY:
  if (att->Zoffset >= texImage->Height) {
-att_incomplete("bad 1D-array layer");
+att_incomplete(ctx, "bad 1D-array layer");
 att->Complete = GL_FALSE;
 return;
  }
  break;
   case GL_TEXTURE_2D_ARRAY:
  if (att->Zoffset >= texImage->Depth) {
-att_incomplete("bad 2D-array layer");
+att_incomplete(ctx, "bad 2D-array layer");
 att->Complete = GL_FALSE;
 return;
  }
  break;
   case GL_TEXTURE_CUBE_MAP_ARRAY:
  if (att->Zoffset >= texImage->Depth) {
-att_incomplete("bad cube-array layer");
+att_incomplete(ctx, "bad cube-array layer");
 att->Complete = GL_FALSE;
 return;
  }
@@ -849,12 +857,12 @@ test_attachment_completeness(const struct gl_context 
*ctx, GLenum format,
 
   if (format == GL_COLOR) {
  if (!_mesa_is_legal_color_format(ctx, baseFormat)) {
-att_incomplete("bad format");
+att_incomplete(ctx, "bad format");
 att->Complete = GL_FALSE;
 return;
  }
  if (_mesa_is_format_compressed(texImage->TexFormat)) {
-att_incomplete("compressed internalformat");
+att_incomplete(ctx, "compressed internalformat");
 att->Complete = GL_FALSE;
 return;
  }
@@ -865,7 +873,7 @@ test_attachment_completeness(const struct gl_context *ctx, 
GLenum format,
   * GL_EXT_color_buffer(_half)_float with set of new sized types.
   */
  if (_mesa_is_gles(ctx) && (texObj->_IsFloat || texObj->_IsHalfFloat)) 
{
-att_incomplete("bad internal format");
+att_incomplete(ctx, "bad internal format");
 att->Complete = GL_FALSE;
 return;
  }
@@ -880,7 +888,7 @@ test_attachment_completeness(const struct gl_context *ctx, 
GLenum format,
  }
  else {
 att->Complete = GL_FALSE;
-att_incomplete("bad depth format");
+att_incomplete(ctx, "bad depth format");
 return;
  }
   }
@@ -894,7 +902,7 @@ test_attachment_completeness(const struct gl_context *ctx, 
GLenum format,
 /* OK */
  } else {
 /* no such thing as stencil-only textures */
-att_incomplete("illegal stencil texture");
+

[Mesa-dev] [PATCH v2] st/mesa: only define GLSL 1.4 for compat if driver supports it

[Christian Gmeiner]

Currently GLSL 1.4 is defined for all gallium drivers even only
GLSL 1.2 is supported as seen on etnaviv.

v1 -> v2:
 - use _min(..) as suggested by Lucas Stach and Michel Dänzer

Fixes 4560aad780b ("mesa: add GLSLVersionCompat constant")
Signed-off-by: Christian Gmeiner 
---
 src/mesa/state_tracker/st_extensions.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index 19ef736e5b..2d56a88027 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -936,7 +936,7 @@ void st_init_extensions(struct pipe_screen *screen,
 
/* Figure out GLSL support and set GLSLVersion to it. */
consts->GLSLVersion = screen->get_param(screen, 
PIPE_CAP_GLSL_FEATURE_LEVEL);
-   consts->GLSLVersionCompat = 140;
+   consts->GLSLVersionCompat = _min(consts->GLSLVersion, 140);
 
_mesa_override_glsl_version(consts);
 
-- 
2.17.0

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[Mesa-dev] [PATCH] radv: allow to print GPU info with RADV_DEBUG=info

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_debug.h  | 1 +
 src/amd/vulkan/radv_device.c | 4 
 2 files changed, 5 insertions(+)

diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index 9dda9b6b0c2..b6993cee1c8 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -45,6 +45,7 @@ enum {
RADV_DEBUG_PREOPTIR  = 0x8000,
RADV_DEBUG_NO_DYNAMIC_BOUNDS = 0x1,
RADV_DEBUG_NO_OUT_OF_ORDER   = 0x2,
+   RADV_DEBUG_INFO  = 0x4,
 };
 
 enum {
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a7f4a5ab7b8..115f33ea4b3 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -329,6 +329,9 @@ radv_physical_device_init(struct radv_physical_device 
*device,
goto fail;
}
 
+   if ((device->instance->debug_flags & RADV_DEBUG_INFO))
+   ac_print_gpu_info(>rad_info);
+
return VK_SUCCESS;
 
 fail:
@@ -391,6 +394,7 @@ static const struct debug_control radv_debug_options[] = {
{"preoptir", RADV_DEBUG_PREOPTIR},
{"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
{"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
+   {"info", RADV_DEBUG_INFO},
{NULL, 0}
 };
 
-- 
2.17.0

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Re: [Mesa-dev] [PATCH] dri3: Stricter SBC wraparound handling

[Michel Dänzer]

On 2018-05-16 01:39 PM, Mike Lothian wrote:
> Can this be added to stable too?

Right, I meant add that but forgot, thanks for the reminder. Consider it
done.


-- 
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Re: [Mesa-dev] [PATCH] st/mesa: only define GLSL 1.4 for compat if driver supports it

[Michel Dänzer]

On 2018-05-16 03:31 PM, Christian Gmeiner wrote:
> Currently GLSL 1.4 is defined for all gallium drivers even only
> GLSL 1.2 is supported as seen on etnaviv.
> 
> Fixes 4560aad780b ("mesa: add GLSLVersionCompat constant")
> 
> Signed-off-by: Christian Gmeiner 
> ---
>  src/mesa/state_tracker/st_extensions.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/state_tracker/st_extensions.c 
> b/src/mesa/state_tracker/st_extensions.c
> index 19ef736e5b..945ca3a16c 100644
> --- a/src/mesa/state_tracker/st_extensions.c
> +++ b/src/mesa/state_tracker/st_extensions.c
> @@ -936,7 +936,11 @@ void st_init_extensions(struct pipe_screen *screen,
>  
> /* Figure out GLSL support and set GLSLVersion to it. */
> consts->GLSLVersion = screen->get_param(screen, 
> PIPE_CAP_GLSL_FEATURE_LEVEL);
> -   consts->GLSLVersionCompat = 140;
> +
> +   if (consts->GLSLVersion >= 140)
> +  consts->GLSLVersionCompat = 140;
> +   else
> +  consts->GLSLVersionCompat = 120;

   consts->GLSLVersionCompat = min(consts->GLSLVersion, 140);

?


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Re: [Mesa-dev] [PATCH] st/mesa: only define GLSL 1.4 for compat if driver supports it

[Lucas Stach]

Am Mittwoch, den 16.05.2018, 15:31 +0200 schrieb Christian Gmeiner:
> Currently GLSL 1.4 is defined for all gallium drivers even only
> GLSL 1.2 is supported as seen on etnaviv.
> 
> Fixes 4560aad780b ("mesa: add GLSLVersionCompat constant")
> 
> > Signed-off-by: Christian Gmeiner 
> ---
>  src/mesa/state_tracker/st_extensions.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/state_tracker/st_extensions.c 
> b/src/mesa/state_tracker/st_extensions.c
> index 19ef736e5b..945ca3a16c 100644
> --- a/src/mesa/state_tracker/st_extensions.c
> +++ b/src/mesa/state_tracker/st_extensions.c
> @@ -936,7 +936,11 @@ void st_init_extensions(struct pipe_screen *screen,
>  
> /* Figure out GLSL support and set GLSLVersion to it. */
> consts->GLSLVersion = screen->get_param(screen, 
> PIPE_CAP_GLSL_FEATURE_LEVEL);
> -   consts->GLSLVersionCompat = 140;
> +
> +   if (consts->GLSLVersion >= 140)
> +  consts->GLSLVersionCompat = 140;
> +   else
> +  consts->GLSLVersionCompat = 120;

A driver might want to expose the intermediate version 130 at some
point. So the compat version should really be min(GLSLVersion, 140) to
cover this, right?

Regards,
Lucas
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[Mesa-dev] [PATCH] st/mesa: only define GLSL 1.4 for compat if driver supports it

[Christian Gmeiner]

Currently GLSL 1.4 is defined for all gallium drivers even only
GLSL 1.2 is supported as seen on etnaviv.

Fixes 4560aad780b ("mesa: add GLSLVersionCompat constant")

Signed-off-by: Christian Gmeiner 
---
 src/mesa/state_tracker/st_extensions.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index 19ef736e5b..945ca3a16c 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -936,7 +936,11 @@ void st_init_extensions(struct pipe_screen *screen,
 
/* Figure out GLSL support and set GLSLVersion to it. */
consts->GLSLVersion = screen->get_param(screen, 
PIPE_CAP_GLSL_FEATURE_LEVEL);
-   consts->GLSLVersionCompat = 140;
+
+   if (consts->GLSLVersion >= 140)
+  consts->GLSLVersionCompat = 140;
+   else
+  consts->GLSLVersionCompat = 120;
 
_mesa_override_glsl_version(consts);
 
-- 
2.17.0

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Re: [Mesa-dev] threading in OSMesa and gallium swr driver

[Cherniak, Bruce]

On May 14, 2018, at 8:59 AM, Alexandre 
>
 wrote:

Hello,

Sorry for the inconvenience if this message is not appropriate for this mailing 
list.

The following is a question for developers of the swr driver of gallium.

I am the main developer of a motion graphics application.
Our application internally has a dependency graph where each node may run 
concurrently.
We use OpenGL extensively in the implementation of the nodes (for example with 
Shadertoy).

Our application has 2 main requirements:
- A GPU backend, mainly for user interaction and fast results
- A CPU backend for batch rendering

Internally we use OSMesa for CPU backend so that our code is mostly identical 
for both GPU and CPU paths.
However when it comes to CPU, our application is heavily multi-threaded: each 
processing node can potentially run in parallel of others as a dependency graph.
We use Intel TBB to schedule the CPU threads.

For each actual hardware thread (not task) we allocate a new OSMesa context so 
that we can freely multi-thread operators rendering. It works fine with 
llvmpipe and also SWR so far (with a  patch to fix some static variables inside 
state_trackers/osmesa.c).

However with SWR using its own thread pool, I’m afraid of over-threading, 
introducing a bottleneck in threads scheduling
e.g: on a 32 cores processor, we already have lets say 24 threads busy on a TBB 
task on each core with 1 OSMesa context.
I looked at the code and all those concurrent OSMesa contexts will create a SWR 
context and each will try to initialise its own thread pool in CreateThreadPool 
in swr/rasterizer/core/api.cpp

Is there a way to have a single “static” thread-pool shared across all contexts 
?

There is not currently a way to create a single thread-pool shared across all 
contexts.  Each context creates unique worker threads.

However, OpenSWR provides an environment variable, KNOB_MAX_WORKER_THREADS, 
that overrides the default thread allocation.
Setting this will limit the number of threads created by an OpenSWR context 
*and* prevent the threads from being bound to physical cores.

Please, give this a try.  By adjusting the value, you may find the optimal 
value for your situation.

Cheers,
Bruce

Thank you

Alexandre










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Re: [Mesa-dev] [PATCH 1/2] glsl: always enable OES_standard_derivatives features if supported

[Timothy Arceri]

On 16/05/18 22:29, Ilia Mirkin wrote:

On Wed, May 16, 2018 at 8:26 AM, Timothy Arceri  wrote:



On 16/05/18 22:09, Ilia Mirkin wrote:


On Wed, May 16, 2018 at 8:04 AM, Timothy Arceri 
wrote:




On 16/05/18 21:12, Ilia Mirkin wrote:



   From the spec,

"""
   The built-in derivative functions dFdx, dFdy, and fwidth are
optional, and
   must be enabled by

   #extension GL_OES_standard_derivatives : enable

   before being used.
"""

Sounds like you need an application override?




The ES spec has no such wording is simply states:

"dFdx(), dFdy(), and fwidth() are made optional."



That is under the heading of "Changes from Revision 59 of the OpenGL
Shading Language specification:", i.e. desktop GLSL.

There isn't a single other reference to those functions anywhere else
in https://www.khronos.org/files/opengles_shading_language.pdf . The
"optional" is in reference to it being moved out to an extension
rather than being part of the core language.



It also says noise is optional but there is no spec for it that I can see.


Yeah, the function just doesn't exist in ES. Those comments sections
at the top of "how does this differ from X" aren't normative. Look at
the list of functions -- is it in there? If not, it doesn't exist.


Ok, well I guess I'll submit a CTS test since I don't think we can do 
application overrides with wine apps.

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Re: [Mesa-dev] [PATCH 1/2] glsl: always enable OES_standard_derivatives features if supported

[Ilia Mirkin]

On Wed, May 16, 2018 at 8:26 AM, Timothy Arceri  wrote:
>
>
> On 16/05/18 22:09, Ilia Mirkin wrote:
>>
>> On Wed, May 16, 2018 at 8:04 AM, Timothy Arceri 
>> wrote:
>>>
>>>
>>>
>>> On 16/05/18 21:12, Ilia Mirkin wrote:


   From the spec,

 """
   The built-in derivative functions dFdx, dFdy, and fwidth are
 optional, and
   must be enabled by

   #extension GL_OES_standard_derivatives : enable

   before being used.
 """

 Sounds like you need an application override?
>>>
>>>
>>>
>>> The ES spec has no such wording is simply states:
>>>
>>> "dFdx(), dFdy(), and fwidth() are made optional."
>>
>>
>> That is under the heading of "Changes from Revision 59 of the OpenGL
>> Shading Language specification:", i.e. desktop GLSL.
>>
>> There isn't a single other reference to those functions anywhere else
>> in https://www.khronos.org/files/opengles_shading_language.pdf . The
>> "optional" is in reference to it being moved out to an extension
>> rather than being part of the core language.
>
>
> It also says noise is optional but there is no spec for it that I can see.

Yeah, the function just doesn't exist in ES. Those comments sections
at the top of "how does this differ from X" aren't normative. Look at
the list of functions -- is it in there? If not, it doesn't exist.

  -ilia
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Re: [Mesa-dev] [PATCH 1/2] glsl: always enable OES_standard_derivatives features if supported

[Timothy Arceri]

On 16/05/18 22:09, Ilia Mirkin wrote:

On Wed, May 16, 2018 at 8:04 AM, Timothy Arceri  wrote:



On 16/05/18 21:12, Ilia Mirkin wrote:


  From the spec,

"""
  The built-in derivative functions dFdx, dFdy, and fwidth are
optional, and
  must be enabled by

  #extension GL_OES_standard_derivatives : enable

  before being used.
"""

Sounds like you need an application override?



The ES spec has no such wording is simply states:

"dFdx(), dFdy(), and fwidth() are made optional."


That is under the heading of "Changes from Revision 59 of the OpenGL
Shading Language specification:", i.e. desktop GLSL.

There isn't a single other reference to those functions anywhere else
in https://www.khronos.org/files/opengles_shading_language.pdf . The
"optional" is in reference to it being moved out to an extension
rather than being part of the core language.


It also says noise is optional but there is no spec for it that I can see.



   -ilia


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Re: [Mesa-dev] [PATCH 1/2] glsl: always enable OES_standard_derivatives features if supported

[Timothy Arceri]

On 16/05/18 22:09, Ilia Mirkin wrote:

On Wed, May 16, 2018 at 8:04 AM, Timothy Arceri  wrote:



On 16/05/18 21:12, Ilia Mirkin wrote:


  From the spec,

"""
  The built-in derivative functions dFdx, dFdy, and fwidth are
optional, and
  must be enabled by

  #extension GL_OES_standard_derivatives : enable

  before being used.
"""

Sounds like you need an application override?



The ES spec has no such wording is simply states:

"dFdx(), dFdy(), and fwidth() are made optional."


That is under the heading of "Changes from Revision 59 of the OpenGL
Shading Language specification:", i.e. desktop GLSL.

There isn't a single other reference to those functions anywhere else
in https://www.khronos.org/files/opengles_shading_language.pdf . The
"optional" is in reference to it being moved out to an extension
rather than being part of the core language.


Well it's not very clear either way. If it is as you suspect it seems 
odd that none of the conformance suites test for it. They are normally 
pretty good at this type of testing.




   -ilia


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Re: [Mesa-dev] [PATCH 1/2] glsl: always enable OES_standard_derivatives features if supported

[Ilia Mirkin]

On Wed, May 16, 2018 at 8:04 AM, Timothy Arceri  wrote:
>
>
> On 16/05/18 21:12, Ilia Mirkin wrote:
>>
>>  From the spec,
>>
>> """
>>  The built-in derivative functions dFdx, dFdy, and fwidth are
>> optional, and
>>  must be enabled by
>>
>>  #extension GL_OES_standard_derivatives : enable
>>
>>  before being used.
>> """
>>
>> Sounds like you need an application override?
>
>
> The ES spec has no such wording is simply states:
>
> "dFdx(), dFdy(), and fwidth() are made optional."

That is under the heading of "Changes from Revision 59 of the OpenGL
Shading Language specification:", i.e. desktop GLSL.

There isn't a single other reference to those functions anywhere else
in https://www.khronos.org/files/opengles_shading_language.pdf . The
"optional" is in reference to it being moved out to an extension
rather than being part of the core language.

  -ilia
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Re: [Mesa-dev] [PATCH 1/2] glsl: always enable OES_standard_derivatives features if supported

[Timothy Arceri]

On 16/05/18 21:12, Ilia Mirkin wrote:

 From the spec,

"""
 The built-in derivative functions dFdx, dFdy, and fwidth are optional, and
 must be enabled by

 #extension GL_OES_standard_derivatives : enable

 before being used.
"""

Sounds like you need an application override?


The ES spec has no such wording is simply states:

"dFdx(), dFdy(), and fwidth() are made optional."

As sloppy as it is for the spec to do this it seem perfectly legal to 
expose them if we choose to do so. The wording in the 
OES_standard_derivatives spec makes sense if you don't expose them 
normally but it you choose to do so its redundant.




On Wed, May 16, 2018 at 3:04 AM, Timothy Arceri  wrote:

The GLSL ES 1.0 spec made these features optional. With
OES_standard_derivatives they are guaranteed to be available
but currently the extension must be enabled to use them.

Instead this changes the code to check if the driver supports
the extension and if so always enables them.

This fixes compiler errors in Google Earth VR.
---
  src/compiler/glsl/builtin_functions.cpp | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/glsl/builtin_functions.cpp 
b/src/compiler/glsl/builtin_functions.cpp
index e1ee9943172..1ecbdc98404 100644
--- a/src/compiler/glsl/builtin_functions.cpp
+++ b/src/compiler/glsl/builtin_functions.cpp
@@ -446,7 +446,7 @@ fs_oes_derivatives(const _mesa_glsl_parse_state *state)
  {
 return state->stage == MESA_SHADER_FRAGMENT &&
(state->is_version(110, 300) ||
-   state->OES_standard_derivatives_enable);
+   state->extensions->OES_standard_derivatives);
  }

  static bool
--
2.17.0

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Re: [Mesa-dev] [PATCH] radeonsi: create .gitignore

[Dieter Nützel]

Thank you Marek,

can someone (you) commit for me, then? ;-)

Dieter

Am 15.05.2018 18:35, schrieb Marek Olšák:

Reviewed-by: Marek Olšák 

Marek

On Tue, May 15, 2018 at 9:55 AM, Dieter Nützel 
wrote:


Hello Marek,

sorry I have some trouble with 'git send-email' (configuration)

Command unknown: 'AUTH' at /usr/lib/git/git-send-email line 1455

currently, so I send it this way.

Dieter

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Re: [Mesa-dev] [PATCH 0/9] intel/blorp: Refactors, cleanups, and fixes

[Iago Toral]

I skipped the first two patches in the series. I believe that there is
probably someone else more suitable than me to review or verify patch 1
and I don't think we have public gen10 PRMs available yet for patch 2.

I dropped a minor comment on patch 6 which you can take or leave. In
any case, patches 3-9 are:

Reviewed-by: Iago Toral Quiroga 

Iago

On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote:
> This little series makes a bunch of mostly small changes to
> blorp.  The end
> objective is to get to the point where you just call blorp_ccs_op and
> hand
> it an isl_aux_op instead of having different entrypoints for
> everything.
> This is similar to what we do for HiZ.  For MCS, we still have two
> functions: blorp_mcs_clear and blorp_mcs_partial_resolve.  Since
> those are
> the only two MCS operations you can do (and partial resolve isn't an
> actual
> hardware op), that seemed ok.
> 
> The difficult patch in here is the first one.  I fairly firmly
> believe it
> to be correct but it's a deviation of the docs so it's a bit hard to
> say.
> Unfortunately, it's one of the worst bits of documentation we have
> for our
> GPUs and, as the giant comment explains, it's actually self-
> contradictory
> once you start doing the math.
> 
> Jason Ekstrand (9):
>   intel/blorp: Only double the fast-clear rect alignment on HSW
>   intel/blorp: Use the hardware op for CCS ambiguate on gen10+
>   intel/blorp: Rename blorp_ccs_resolve to blorp_ccs_op
>   intel/blorp: Simplify asserts in blorp_ccs_op
>   anv/blorp: Use blorp_ccs_op for everything
>   intel/blorp: Make blorp_ccs_ambiguate just an internal helper
>   i965: Use blorp_ccs_op for CCS fast-clears
>   intel/blorp: Handle fast-clear directly in blorp_ccs_op
>   intel/blorp: Refactor MCS clears
> 
>  src/intel/blorp/blorp.h   |  24 ++-
>  src/intel/blorp/blorp_clear.c | 327 ++
> 
>  src/intel/blorp/blorp_genX_exec.h |   6 +
>  src/intel/vulkan/anv_blorp.c  |  34 +---
>  src/mesa/drivers/dri/i965/brw_blorp.c |  18 +-
>  5 files changed, 203 insertions(+), 206 deletions(-)
> 
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Re: [Mesa-dev] [PATCH 8/9] intel/blorp: Handle fast-clear directly in blorp_ccs_op

[Iago Toral]

On Wed, 2018-05-16 at 13:34 +0200, Iago Toral wrote:
> On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote:
> > ---
> >  src/intel/blorp/blorp_clear.c | 199 +++---
> > --
> > --
> >  1 file changed, 88 insertions(+), 111 deletions(-)
> > 
> > diff --git a/src/intel/blorp/blorp_clear.c
> > b/src/intel/blorp/blorp_clear.c
> > index 39bc0c6..5625221 100644
> > --- a/src/intel/blorp/blorp_clear.c
> > +++ b/src/intel/blorp/blorp_clear.c
> > @@ -193,104 +193,7 @@ get_fast_clear_rect(const struct isl_device
> > *dev,
> >  
> > /* Only single sampled surfaces need to (and actually can) be
> > resolved. */
> > if (aux_surf->usage == ISL_SURF_USAGE_CCS_BIT) {
> > -  /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for
> > Render
> > -   * Target(s)", beneath the "Fast Color Clear" bullet (p327):
> > -   *
> > -   * Clear pass must have a clear rectangle that must
> > follow
> > -   * alignment rules in terms of pixels and lines as shown
> > in the
> > -   * table below. Further, the clear-rectangle height and
> > width
> > -   * must be multiple of the following dimensions. If the
> > height
> > -   * and width of the render target being cleared do not
> > meet these
> > -   * requirements, an MCS buffer can be created such that
> > it
> > -   * follows the requirement and covers the RT.
> > -   *
> > -   * The alignment size in the table that follows is related
> > to
> > the
> > -   * alignment size that is baked into the CCS surface format
> > but with X
> > -   * alignment multiplied by 16 and Y alignment multiplied by
> > 32.
> > -   */
> > -  x_align = isl_format_get_layout(aux_surf->format)->bw;
> > -  y_align = isl_format_get_layout(aux_surf->format)->bh;
> > -
> > -  x_align *= 16;
> > -
> > -  /* SKL+ line alignment requirement for Y-tiled are half
> > those
> > of the prior
> > -   * generations.
> > -   */
> > -  if (dev->info->gen >= 9)
> > - y_align *= 16;
> > -  else
> > - y_align *= 32;
> > -
> > -  /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for
> > Render
> > -   * Target(s)", beneath the "Fast Color Clear" bullet (p327):
> > -   *
> > -   * In order to optimize the performance MCS buffer (when
> > bound to
> > -   * 1X RT) clear similarly to MCS buffer clear for MSRT
> > case,
> > -   * clear rect is required to be scaled by the following
> > factors
> > -   * in the horizontal and vertical directions:
> > -   *
> > -   * The X and Y scale down factors in the table that follows
> > are each
> > -   * equal to half the alignment value computed above.
> > -   */
> > -  x_scaledown = x_align / 2;
> > -  y_scaledown = y_align / 2;
> > -
> > -  if (ISL_DEV_IS_HASWELL(dev)) {
> > - /* The following text was added in the Haswell PRM, "3D
> > Media GPGPU
> > -  * Engine" >> "MCS Buffer for Render Target(s)" >> Table
> > "Color Clear
> > -  * of Non-MultiSampler Render Target Restrictions":
> > -  *
> > -  *"Clear rectangle must be aligned to two times the
> > number of
> > -  *pixels in the table shown below due to 16X16
> > hashing
> > across the
> > -  *slice."
> > -  *
> > -  * It has persisted in the documentation for all
> > platforms
> > up until
> > -  * Cannonlake and possibly even beyond.  However, we
> > believe that it
> > -  * is only needed on Haswell.
> > -  *
> > -  * There are a couple possible explanations for this
> > restriction:
> > -  *
> > -  * 1) If you assume that the hardware is writing to the
> > CCS
> > as
> > -  *bytes, then the x/y_align computed above gives you
> > an
> > alignment
> > -  *in the CCS of 8x8 bytes and, if 16x16 is needed for
> > hashing, we
> > -  *need to multiply by 2.
> > -  *
> > -  * 2) Haswell is a bit unique in that it's CCS tiling
> > does
> > not line
> > -  *up with Y-tiling on a cache-line
> > granularity.  Instead, it has
> > -  *an extra bit of swizzling in bit 9.  Also, bit 6
> > swizzling
> > -  *applies to the CCS on Haswell.  This means that
> > Haswell CTS
> > -  *does not match on a cache-line granularity but it
> > does match on
> > -  *a 2x2 cache line granularity.
> > -  *
> > -  * Clearly, the first explanation seems to follow
> > documentation the
> > -  * best but they may be related.  In any case, empirical
> > evidence
> > -  * seems to confirm that it is, indeed required on
> > Haswell.
> > -  *
> > -  * On Broadwell things get a bit stickier.  Broadwell
> > adds
> > support
> > -  * for mip-mapped CCS with an alignment in the CCS of
> > 256x128.  For a
> > -  * 

Re: [Mesa-dev] [PATCH] dri3: Stricter SBC wraparound handling

[Mike Lothian]

Can this be added to stable too?

On Wed, 16 May 2018 at 10:33 Michel Dänzer  wrote:

> On 2018-05-16 11:14 AM, Axel Davy wrote:
> > Hi,
> >
> > Shouldn't this be fixed on the xserver or the ddx side, rather than in
> > Mesa ?
> No, it's a Mesa bug, the X server is doing what it's asked. (This wasn't
> noticed earlier because Xorg drivers using the old DRM_IOCTL_WAIT_VBLANK
> ioctl effectively ignore the upper 32 bits of the target MSC value).
>
>
> --
> Earthling Michel Dänzer   |   http://www.amd.com
> Libre software enthusiast | Mesa and X developer
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Re: [Mesa-dev] [PATCH] mesa: handle a bunch of formats in IMPLEMENTATION_COLOR_READ_*

[Gert Wollny]

Tested-By: Gert Wollny 

Am Montag, den 14.05.2018, 15:14 +0200 schrieb Tomeu Vizoso:
> Virgl could save a lot of work converting buffers in the host side
> between formats if Mesa supported a bunch of other formats when
> reading
> pixels.
> 
> This commit adds cases to handle specific formats so that the values
> reported by the two calls match more closely the underlying native
> formats.
> 
> In GLES is important that IMPLEMENTATION_COLOR_READ_* return the
> native
> format and data type because the spec only allows reading with those,
> besides GL_RGBA or GL_RGBA_INTEGER.
> 
> Additionally, because virgl currently doesn't implement such
> conversions,
> this commit fixes several tests in
> dEQP-GLES3.functional.fbo.color.clear.*, when using virgl in the
> guest
> side.
> 
> Signed-off-by: Tomeu Vizoso 
> ---
>  src/mesa/main/framebuffer.c | 73 ---
> --
>  1 file changed, 64 insertions(+), 9 deletions(-)
> 
> diff --git a/src/mesa/main/framebuffer.c
> b/src/mesa/main/framebuffer.c
> index 8e751b453b75..a22c66b349f2 100644
> --- a/src/mesa/main/framebuffer.c
> +++ b/src/mesa/main/framebuffer.c
> @@ -836,15 +836,43 @@ _mesa_get_color_read_format(struct gl_context
> *ctx,
>const mesa_format format = fb->_ColorReadBuffer->Format;
>const GLenum data_type = _mesa_get_format_datatype(format);
>  
> -  if (format == MESA_FORMAT_B8G8R8A8_UNORM)
> +  switch(format) {
> +  case MESA_FORMAT_B8G8R8A8_UNORM:
>   return GL_BGRA;
> -  else if (format == MESA_FORMAT_B5G6R5_UNORM)
> +  case MESA_FORMAT_R10G10B10A2_UINT:
> + return GL_BGRA_INTEGER;
> +  case MESA_FORMAT_B5G6R5_UNORM:
> +  case MESA_FORMAT_R11G11B10_FLOAT:
>   return GL_RGB;
> -  else if (format == MESA_FORMAT_R_UNORM8)
> +  case MESA_FORMAT_RG_FLOAT32:
> +  case MESA_FORMAT_RG_FLOAT16:
> +  case MESA_FORMAT_R8G8_UNORM:
> + return GL_RG;
> +  case MESA_FORMAT_RG_SINT32:
> +  case MESA_FORMAT_RG_UINT32:
> +  case MESA_FORMAT_RG_SINT16:
> +  case MESA_FORMAT_RG_UINT16:
> +  case MESA_FORMAT_RG_SINT8:
> +  case MESA_FORMAT_RG_UINT8:
> + return GL_RG_INTEGER;
> +  case MESA_FORMAT_R_FLOAT32:
> +  case MESA_FORMAT_R_FLOAT16:
> +  case MESA_FORMAT_R_UNORM8:
>   return GL_RED;
> +  case MESA_FORMAT_R_SINT32:
> +  case MESA_FORMAT_R_UINT32:
> +  case MESA_FORMAT_R_SINT16:
> +  case MESA_FORMAT_R_UINT16:
> +  case MESA_FORMAT_R_SINT8:
> +  case MESA_FORMAT_R_UINT8:
> + return GL_RED_INTEGER;
> +  default:
> + break;
> +  }
>  
>switch (data_type) {
>case GL_UNSIGNED_INT:
> +  case GL_UNSIGNED_BYTE:
>case GL_INT:
>   return GL_RGBA_INTEGER;
>default:
> @@ -885,14 +913,41 @@ _mesa_get_color_read_type(struct gl_context
> *ctx,
>const GLenum format = fb->_ColorReadBuffer->Format;
>const GLenum data_type = _mesa_get_format_datatype(format);
>  
> -  if (format == MESA_FORMAT_B5G6R5_UNORM)
> +  switch(format) {
> +  case MESA_FORMAT_B5G6R5_UNORM:
>   return GL_UNSIGNED_SHORT_5_6_5;
> -
> -  if (format == MESA_FORMAT_B10G10R10A2_UNORM ||
> -  format == MESA_FORMAT_B10G10R10X2_UNORM ||
> -  format == MESA_FORMAT_R10G10B10A2_UNORM ||
> -  format == MESA_FORMAT_R10G10B10X2_UNORM)
> +  case MESA_FORMAT_B10G10R10A2_UNORM:
> +  case MESA_FORMAT_B10G10R10X2_UNORM:
> +  case MESA_FORMAT_R10G10B10A2_UNORM:
> +  case MESA_FORMAT_R10G10B10X2_UNORM:
> +  case MESA_FORMAT_B10G10R10A2_UINT:
> +  case MESA_FORMAT_R10G10B10A2_UINT:
>   return GL_UNSIGNED_INT_2_10_10_10_REV;
> +  case MESA_FORMAT_R11G11B10_FLOAT:
> + return GL_UNSIGNED_INT_10F_11F_11F_REV;
> +  case MESA_FORMAT_RGBA_FLOAT16:
> +  case MESA_FORMAT_RG_FLOAT16:
> +  case MESA_FORMAT_R_FLOAT16:
> + return GL_HALF_FLOAT;
> +  case MESA_FORMAT_RGBA_SINT16:
> +  case MESA_FORMAT_RG_SINT16:
> +  case MESA_FORMAT_R_SINT16:
> + return GL_SHORT;
> +  case MESA_FORMAT_RGBA_UINT16:
> +  case MESA_FORMAT_RG_UINT16:
> +  case MESA_FORMAT_R_UINT16:
> + return GL_UNSIGNED_SHORT;
> +  case MESA_FORMAT_RGBA_SINT8:
> +  case MESA_FORMAT_RG_SINT8:
> +  case MESA_FORMAT_R_SINT8:
> + return GL_BYTE;
> +  case MESA_FORMAT_RG_UINT8:
> +  case MESA_FORMAT_RGBA_UINT8:
> +  case MESA_FORMAT_R_UINT8:
> + return GL_UNSIGNED_BYTE;
> +  default:
> + break;
> +  }
>  
>switch (data_type) {
>case GL_SIGNED_NORMALIZED:
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Re: [Mesa-dev] [PATCH 8/9] intel/blorp: Handle fast-clear directly in blorp_ccs_op

[Iago Toral]

On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote:
> ---
>  src/intel/blorp/blorp_clear.c | 199 +++-
> --
>  1 file changed, 88 insertions(+), 111 deletions(-)
> 
> diff --git a/src/intel/blorp/blorp_clear.c
> b/src/intel/blorp/blorp_clear.c
> index 39bc0c6..5625221 100644
> --- a/src/intel/blorp/blorp_clear.c
> +++ b/src/intel/blorp/blorp_clear.c
> @@ -193,104 +193,7 @@ get_fast_clear_rect(const struct isl_device
> *dev,
>  
> /* Only single sampled surfaces need to (and actually can) be
> resolved. */
> if (aux_surf->usage == ISL_SURF_USAGE_CCS_BIT) {
> -  /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for
> Render
> -   * Target(s)", beneath the "Fast Color Clear" bullet (p327):
> -   *
> -   * Clear pass must have a clear rectangle that must follow
> -   * alignment rules in terms of pixels and lines as shown
> in the
> -   * table below. Further, the clear-rectangle height and
> width
> -   * must be multiple of the following dimensions. If the
> height
> -   * and width of the render target being cleared do not
> meet these
> -   * requirements, an MCS buffer can be created such that it
> -   * follows the requirement and covers the RT.
> -   *
> -   * The alignment size in the table that follows is related to
> the
> -   * alignment size that is baked into the CCS surface format
> but with X
> -   * alignment multiplied by 16 and Y alignment multiplied by
> 32.
> -   */
> -  x_align = isl_format_get_layout(aux_surf->format)->bw;
> -  y_align = isl_format_get_layout(aux_surf->format)->bh;
> -
> -  x_align *= 16;
> -
> -  /* SKL+ line alignment requirement for Y-tiled are half those
> of the prior
> -   * generations.
> -   */
> -  if (dev->info->gen >= 9)
> - y_align *= 16;
> -  else
> - y_align *= 32;
> -
> -  /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for
> Render
> -   * Target(s)", beneath the "Fast Color Clear" bullet (p327):
> -   *
> -   * In order to optimize the performance MCS buffer (when
> bound to
> -   * 1X RT) clear similarly to MCS buffer clear for MSRT
> case,
> -   * clear rect is required to be scaled by the following
> factors
> -   * in the horizontal and vertical directions:
> -   *
> -   * The X and Y scale down factors in the table that follows
> are each
> -   * equal to half the alignment value computed above.
> -   */
> -  x_scaledown = x_align / 2;
> -  y_scaledown = y_align / 2;
> -
> -  if (ISL_DEV_IS_HASWELL(dev)) {
> - /* The following text was added in the Haswell PRM, "3D
> Media GPGPU
> -  * Engine" >> "MCS Buffer for Render Target(s)" >> Table
> "Color Clear
> -  * of Non-MultiSampler Render Target Restrictions":
> -  *
> -  *"Clear rectangle must be aligned to two times the
> number of
> -  *pixels in the table shown below due to 16X16 hashing
> across the
> -  *slice."
> -  *
> -  * It has persisted in the documentation for all platforms
> up until
> -  * Cannonlake and possibly even beyond.  However, we
> believe that it
> -  * is only needed on Haswell.
> -  *
> -  * There are a couple possible explanations for this
> restriction:
> -  *
> -  * 1) If you assume that the hardware is writing to the CCS
> as
> -  *bytes, then the x/y_align computed above gives you an
> alignment
> -  *in the CCS of 8x8 bytes and, if 16x16 is needed for
> hashing, we
> -  *need to multiply by 2.
> -  *
> -  * 2) Haswell is a bit unique in that it's CCS tiling does
> not line
> -  *up with Y-tiling on a cache-line
> granularity.  Instead, it has
> -  *an extra bit of swizzling in bit 9.  Also, bit 6
> swizzling
> -  *applies to the CCS on Haswell.  This means that
> Haswell CTS
> -  *does not match on a cache-line granularity but it
> does match on
> -  *a 2x2 cache line granularity.
> -  *
> -  * Clearly, the first explanation seems to follow
> documentation the
> -  * best but they may be related.  In any case, empirical
> evidence
> -  * seems to confirm that it is, indeed required on Haswell.
> -  *
> -  * On Broadwell things get a bit stickier.  Broadwell adds
> support
> -  * for mip-mapped CCS with an alignment in the CCS of
> 256x128.  For a
> -  * 32bpb main surface, the above computation will yield a
> x/y_align
> -  * of 128x128 for a Y-tiled main surface and 256x64 for X-
> tiled.  In
> -  * either case, if we double the alignment, we will get an
> alignment
> -  * bigger than horizontal and vertical alignment of the CCS
> and fast
> -  * clears of one LOD may 

Re: [Mesa-dev] [PATCH] mesa: handle a bunch of formats in IMPLEMENTATION_COLOR_READ_*

[Jakob Bornecrantz]

Tested-by: Jakob Bornecrantz 

On Mon, May 14, 2018 at 3:14 PM, Tomeu Vizoso
 wrote:
> Virgl could save a lot of work converting buffers in the host side
> between formats if Mesa supported a bunch of other formats when reading
> pixels.
>
> This commit adds cases to handle specific formats so that the values
> reported by the two calls match more closely the underlying native
> formats.
>
> In GLES is important that IMPLEMENTATION_COLOR_READ_* return the native
> format and data type because the spec only allows reading with those,
> besides GL_RGBA or GL_RGBA_INTEGER.
>
> Additionally, because virgl currently doesn't implement such conversions,
> this commit fixes several tests in
> dEQP-GLES3.functional.fbo.color.clear.*, when using virgl in the guest
> side.
>
> Signed-off-by: Tomeu Vizoso 
> ---
>  src/mesa/main/framebuffer.c | 73 -
>  1 file changed, 64 insertions(+), 9 deletions(-)
>
> diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
> index 8e751b453b75..a22c66b349f2 100644
> --- a/src/mesa/main/framebuffer.c
> +++ b/src/mesa/main/framebuffer.c
> @@ -836,15 +836,43 @@ _mesa_get_color_read_format(struct gl_context *ctx,
>const mesa_format format = fb->_ColorReadBuffer->Format;
>const GLenum data_type = _mesa_get_format_datatype(format);
>
> -  if (format == MESA_FORMAT_B8G8R8A8_UNORM)
> +  switch(format) {
> +  case MESA_FORMAT_B8G8R8A8_UNORM:
>   return GL_BGRA;
> -  else if (format == MESA_FORMAT_B5G6R5_UNORM)
> +  case MESA_FORMAT_R10G10B10A2_UINT:
> + return GL_BGRA_INTEGER;
> +  case MESA_FORMAT_B5G6R5_UNORM:
> +  case MESA_FORMAT_R11G11B10_FLOAT:
>   return GL_RGB;
> -  else if (format == MESA_FORMAT_R_UNORM8)
> +  case MESA_FORMAT_RG_FLOAT32:
> +  case MESA_FORMAT_RG_FLOAT16:
> +  case MESA_FORMAT_R8G8_UNORM:
> + return GL_RG;
> +  case MESA_FORMAT_RG_SINT32:
> +  case MESA_FORMAT_RG_UINT32:
> +  case MESA_FORMAT_RG_SINT16:
> +  case MESA_FORMAT_RG_UINT16:
> +  case MESA_FORMAT_RG_SINT8:
> +  case MESA_FORMAT_RG_UINT8:
> + return GL_RG_INTEGER;
> +  case MESA_FORMAT_R_FLOAT32:
> +  case MESA_FORMAT_R_FLOAT16:
> +  case MESA_FORMAT_R_UNORM8:
>   return GL_RED;
> +  case MESA_FORMAT_R_SINT32:
> +  case MESA_FORMAT_R_UINT32:
> +  case MESA_FORMAT_R_SINT16:
> +  case MESA_FORMAT_R_UINT16:
> +  case MESA_FORMAT_R_SINT8:
> +  case MESA_FORMAT_R_UINT8:
> + return GL_RED_INTEGER;
> +  default:
> + break;
> +  }
>
>switch (data_type) {
>case GL_UNSIGNED_INT:
> +  case GL_UNSIGNED_BYTE:
>case GL_INT:
>   return GL_RGBA_INTEGER;
>default:
> @@ -885,14 +913,41 @@ _mesa_get_color_read_type(struct gl_context *ctx,
>const GLenum format = fb->_ColorReadBuffer->Format;
>const GLenum data_type = _mesa_get_format_datatype(format);
>
> -  if (format == MESA_FORMAT_B5G6R5_UNORM)
> +  switch(format) {
> +  case MESA_FORMAT_B5G6R5_UNORM:
>   return GL_UNSIGNED_SHORT_5_6_5;
> -
> -  if (format == MESA_FORMAT_B10G10R10A2_UNORM ||
> -  format == MESA_FORMAT_B10G10R10X2_UNORM ||
> -  format == MESA_FORMAT_R10G10B10A2_UNORM ||
> -  format == MESA_FORMAT_R10G10B10X2_UNORM)
> +  case MESA_FORMAT_B10G10R10A2_UNORM:
> +  case MESA_FORMAT_B10G10R10X2_UNORM:
> +  case MESA_FORMAT_R10G10B10A2_UNORM:
> +  case MESA_FORMAT_R10G10B10X2_UNORM:
> +  case MESA_FORMAT_B10G10R10A2_UINT:
> +  case MESA_FORMAT_R10G10B10A2_UINT:
>   return GL_UNSIGNED_INT_2_10_10_10_REV;
> +  case MESA_FORMAT_R11G11B10_FLOAT:
> + return GL_UNSIGNED_INT_10F_11F_11F_REV;
> +  case MESA_FORMAT_RGBA_FLOAT16:
> +  case MESA_FORMAT_RG_FLOAT16:
> +  case MESA_FORMAT_R_FLOAT16:
> + return GL_HALF_FLOAT;
> +  case MESA_FORMAT_RGBA_SINT16:
> +  case MESA_FORMAT_RG_SINT16:
> +  case MESA_FORMAT_R_SINT16:
> + return GL_SHORT;
> +  case MESA_FORMAT_RGBA_UINT16:
> +  case MESA_FORMAT_RG_UINT16:
> +  case MESA_FORMAT_R_UINT16:
> + return GL_UNSIGNED_SHORT;
> +  case MESA_FORMAT_RGBA_SINT8:
> +  case MESA_FORMAT_RG_SINT8:
> +  case MESA_FORMAT_R_SINT8:
> + return GL_BYTE;
> +  case MESA_FORMAT_RG_UINT8:
> +  case MESA_FORMAT_RGBA_UINT8:
> +  case MESA_FORMAT_R_UINT8:
> + return GL_UNSIGNED_BYTE;
> +  default:
> + break;
> +  }
>
>switch (data_type) {
>case GL_SIGNED_NORMALIZED:
> --
> 2.17.0
>
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Re: [Mesa-dev] [PATCH 7/9] i965: Use blorp_ccs_op for CCS fast-clears

[Iago Toral]

On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c | 12 +---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index dab04f2..b6097f5 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -1260,9 +1260,15 @@ do_single_blorp_clear(struct brw_context *brw,
> struct gl_framebuffer *fb,
>  
>struct blorp_batch batch;
>blorp_batch_init(>blorp, , brw, 0);
> -  blorp_fast_clear(, , isl_format,
> -   level, irb->mt_layer, num_layers,
> -   x0, y0, x1, y1);
> +  if (surf.aux_usage == ISL_AUX_USAGE_CCS_E ||
> +  surf.aux_usage == ISL_AUX_USAGE_CCS_D) {
> + blorp_ccs_op(, , level, irb->mt_layer,
> num_layers,
> +  isl_format, ISL_AUX_OP_FAST_CLEAR);
> +  } else {
> + blorp_fast_clear(, , isl_format,
> +  level, irb->mt_layer, num_layers,
> +  x0, y0, x1, y1);
> +  }

On its own, this looks a bit weird, but reading further into the series
this seems to be preparation for the last patch in the series.

>blorp_batch_finish();
>  
>brw_emit_end_of_pipe_sync(brw,
> PIPE_CONTROL_RENDER_TARGET_FLUSH);
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Re: [Mesa-dev] [PATCH 1/2] glsl: always enable OES_standard_derivatives features if supported

[Ilia Mirkin]

From the spec,

"""
The built-in derivative functions dFdx, dFdy, and fwidth are optional, and
must be enabled by

#extension GL_OES_standard_derivatives : enable

before being used.
"""

Sounds like you need an application override?

On Wed, May 16, 2018 at 3:04 AM, Timothy Arceri  wrote:
> The GLSL ES 1.0 spec made these features optional. With
> OES_standard_derivatives they are guaranteed to be available
> but currently the extension must be enabled to use them.
>
> Instead this changes the code to check if the driver supports
> the extension and if so always enables them.
>
> This fixes compiler errors in Google Earth VR.
> ---
>  src/compiler/glsl/builtin_functions.cpp | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/compiler/glsl/builtin_functions.cpp 
> b/src/compiler/glsl/builtin_functions.cpp
> index e1ee9943172..1ecbdc98404 100644
> --- a/src/compiler/glsl/builtin_functions.cpp
> +++ b/src/compiler/glsl/builtin_functions.cpp
> @@ -446,7 +446,7 @@ fs_oes_derivatives(const _mesa_glsl_parse_state *state)
>  {
> return state->stage == MESA_SHADER_FRAGMENT &&
>(state->is_version(110, 300) ||
> -   state->OES_standard_derivatives_enable);
> +   state->extensions->OES_standard_derivatives);
>  }
>
>  static bool
> --
> 2.17.0
>
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Re: [Mesa-dev] [PATCH 6/9] intel/blorp: Make blorp_ccs_ambiguate just an internal helper

[Iago Toral]

On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote:
> Now that anv uses blorp_ccs_op for everything, we no longer need to
> expose the ccs_ambiguate function directly.  It's much better tucked
> away as an implementation detail.
> ---
>  src/intel/blorp/blorp.h   |  5 -
>  src/intel/blorp/blorp_clear.c | 21 ++---
>  2 files changed, 10 insertions(+), 16 deletions(-)
> 
> diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
> index 8c775bf..e27ea7e 100644
> --- a/src/intel/blorp/blorp.h
> +++ b/src/intel/blorp/blorp.h
> @@ -208,11 +208,6 @@ blorp_ccs_op(struct blorp_batch *batch,
>   enum isl_aux_op ccs_op);
>  
>  void
> -blorp_ccs_ambiguate(struct blorp_batch *batch,
> -struct blorp_surf *surf,
> -uint32_t level, uint32_t layer);
> -
> -void
>  blorp_mcs_partial_resolve(struct blorp_batch *batch,
>struct blorp_surf *surf,
>enum isl_format format,
> diff --git a/src/intel/blorp/blorp_clear.c
> b/src/intel/blorp/blorp_clear.c
> index 6f5549f..39bc0c6 100644
> --- a/src/intel/blorp/blorp_clear.c
> +++ b/src/intel/blorp/blorp_clear.c
> @@ -814,6 +814,11 @@ blorp_clear_attachments(struct blorp_batch
> *batch,
> batch->blorp->exec(batch, );
>  }
>  
> +static void
> +blorp_legacy_ccs_ambiguate(struct blorp_batch *batch,
> +   struct blorp_surf *surf,
> +   uint32_t level, uint32_t layer);
> +
>  void
>  blorp_ccs_op(struct blorp_batch *batch,
>   struct blorp_surf *surf, uint32_t level,
> @@ -835,7 +840,7 @@ blorp_ccs_op(struct blorp_batch *batch,
> * mess to another function.
> */
>for (uint32_t a = 0; a < num_layers; a++)
> - blorp_ccs_ambiguate(batch, surf, level, start_layer + a);
> + blorp_legacy_ccs_ambiguate(batch, surf, level, start_layer
> + a);
>return;
> }
>  
> @@ -1022,17 +1027,11 @@ blorp_mcs_partial_resolve(struct blorp_batch
> *batch,
>   * for a given layer/level of a surface to 0x0 which is the
> "uncompressed"
>   * state which tells the sampler to go look at the main surface.
>   */
> -void
> -blorp_ccs_ambiguate(struct blorp_batch *batch,
> -struct blorp_surf *surf,
> -uint32_t level, uint32_t layer)
> +static void
> +blorp_legacy_ccs_ambiguate(struct blorp_batch *batch,
> +   struct blorp_surf *surf,
> +   uint32_t level, uint32_t layer)
>  {
> -   if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 10) {
> -  /* On gen10 and above, we have a hardware resolve op for this
> */
> -  return blorp_ccs_op(batch, surf, level, layer, 1,
> -  surf->surf->format, ISL_AUX_OP_AMBIGUATE);
> -   }
> -

Since we don't want to call this in gen10+, would it make sense to an
assert for gen < 10?

Iago

> struct blorp_params params;
> blorp_params_init();
>  
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[Mesa-dev] [Bug 106542] osmesa gallium state tracker: Leak of screens and buffers on exit/shared library unload

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106542

Ricardo Barreira  changed:

   What|Removed |Added

 Status|NEW |ASSIGNED

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[Mesa-dev] [Bug 106542] osmesa gallium state tracker: Leak of screens and buffers on exit/shared library unload

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106542

--- Comment #1 from Ricardo Barreira  ---
Patch has been sent here:

https://lists.freedesktop.org/archives/mesa-dev/2017-December/180118.html

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[Mesa-dev] [Bug 106542] osmesa gallium state tracker: Leak of screens and buffers on exit/shared library unload

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106542

Ricardo Barreira  changed:

   What|Removed |Added

   Assignee|mesa-dev@lists.freedesktop. |r...@google.com
   |org |

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[Mesa-dev] [Bug 106542] osmesa gallium state tracker: Leak of screens and buffers on exit/shared library unload

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106542

Bug ID: 106542
   Summary: osmesa gallium state tracker: Leak of screens and
buffers on exit/shared library unload
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/OSMesa
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: r...@google.com
QA Contact: mesa-dev@lists.freedesktop.org

state_trackers/osmesa/osmesa.c does not destroy screens and buffers on exit.
This is a problem when using mesa in dynamically-loaded libraries.

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Re: [Mesa-dev] [PATCH] dri3: Stricter SBC wraparound handling

[Michel Dänzer]

On 2018-05-16 11:14 AM, Axel Davy wrote:
> Hi,
> 
> Shouldn't this be fixed on the xserver or the ddx side, rather than in
> Mesa ?
No, it's a Mesa bug, the X server is doing what it's asked. (This wasn't
noticed earlier because Xorg drivers using the old DRM_IOCTL_WAIT_VBLANK
ioctl effectively ignore the upper 32 bits of the target MSC value).


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Re: [Mesa-dev] [PATCH] mesa: handle a bunch of formats in IMPLEMENTATION_COLOR_READ_*

[Eric Anholt]

Tomeu Vizoso  writes:

> Virgl could save a lot of work converting buffers in the host side
> between formats if Mesa supported a bunch of other formats when reading
> pixels.
>
> This commit adds cases to handle specific formats so that the values
> reported by the two calls match more closely the underlying native
> formats.
>
> In GLES is important that IMPLEMENTATION_COLOR_READ_* return the native
> format and data type because the spec only allows reading with those,
> besides GL_RGBA or GL_RGBA_INTEGER.
>
> Additionally, because virgl currently doesn't implement such conversions,
> this commit fixes several tests in
> dEQP-GLES3.functional.fbo.color.clear.*, when using virgl in the guest
> side.
>
> Signed-off-by: Tomeu Vizoso 
> ---
>  src/mesa/main/framebuffer.c | 73 -
>  1 file changed, 64 insertions(+), 9 deletions(-)
>
> diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
> index 8e751b453b75..a22c66b349f2 100644
> --- a/src/mesa/main/framebuffer.c
> +++ b/src/mesa/main/framebuffer.c
> @@ -836,15 +836,43 @@ _mesa_get_color_read_format(struct gl_context *ctx,
>const mesa_format format = fb->_ColorReadBuffer->Format;
>const GLenum data_type = _mesa_get_format_datatype(format);
>  
> -  if (format == MESA_FORMAT_B8G8R8A8_UNORM)
> +  switch(format) {
> +  case MESA_FORMAT_B8G8R8A8_UNORM:
>   return GL_BGRA;
> -  else if (format == MESA_FORMAT_B5G6R5_UNORM)
> +  case MESA_FORMAT_R10G10B10A2_UINT:
> + return GL_BGRA_INTEGER;

Surely this should be GL_RGBA_INTEGER?  (maybe just fall back to the
GL_UNSIGNED_INT case below)

Other than that, this patch looks correct and would be an improvement.
However, I'm wondering if we could avoid having so much code by doing
something with _mesa_uncompressed_format_to_type_and_comps() and a bit
of logic on the swizzle of the format to choose between RGB and BGR for
3/4 comps.

Also, could we assert something about
_mesa_format_matches_format_and_type() using the result of this
function, for sanity checking?


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Re: [Mesa-dev] [PATCH] dri3: Stricter SBC wraparound handling

[Axel Davy]

Hi,

Shouldn't this be fixed on the xserver or the ddx side, rather than in 
Mesa ?


Yours,

Axel Davy

On 16/05/2018 11:10, Michel Dänzer wrote:

From: Michel Dänzer 

Prevents spuriously bumping the upper 32 bits of the SBC, which results
in hangs with the modesetting driver from xserver 1.20.

Bugzilla: https://bugs.freedesktop.org/106351
Tested-by: Mike Lothian 
Signed-off-by: Michel Dänzer 
---
  src/loader/loader_dri3_helper.c | 14 +++---
  1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index 6db8303d26d..f0ff2f07bde 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -370,9 +370,17 @@ dri3_handle_present_event(struct loader_dri3_drawable 
*draw,
 * checking for wrap.
 */
if (ce->kind == XCB_PRESENT_COMPLETE_KIND_PIXMAP) {
- draw->recv_sbc = (draw->send_sbc & 0xLL) | ce->serial;
- if (draw->recv_sbc > draw->send_sbc)
-draw->recv_sbc -= 0x1;
+ uint64_t recv_sbc = (draw->send_sbc & 0xLL) | 
ce->serial;
+
+ /* Only assume wraparound if that results in exactly the previous
+  * SBC + 1, otherwise ignore received SBC > sent SBC (those are
+  * probably from a previous loader_dri3_drawable instance) to avoid
+  * calculating bogus target MSC values in loader_dri3_swap_buffers_msc
+  */
+ if (recv_sbc <= draw->send_sbc)
+draw->recv_sbc = recv_sbc;
+ else if (recv_sbc == (draw->recv_sbc + 0x10001ULL))
+draw->recv_sbc = recv_sbc - 0x1ULL;
  
   /* When moving from flip to copy, we assume that we can allocate in

* a more optimal way if we don't need to cater for the display



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[Mesa-dev] [Bug 106404] Hang in draw function caused by interaction of glutInitWindowPosition, glutFullScreen , glDrawBuffer(GL_FRONT)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106404

Michel Dänzer  changed:

   What|Removed |Added

 QA Contact|dri-devel@lists.freedesktop |mesa-dev@lists.freedesktop.
   |.org|org
  Component|Drivers/Gallium/radeonsi|Mesa core
   Assignee|dri-devel@lists.freedesktop |mesa-dev@lists.freedesktop.
   |.org|org

--- Comment #4 from Michel Dänzer  ---
Doesn't look driver specific, reassigning to Mesa core.

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[Mesa-dev] [PATCH] dri3: Stricter SBC wraparound handling

[Michel Dänzer]

From: Michel Dänzer 

Prevents spuriously bumping the upper 32 bits of the SBC, which results
in hangs with the modesetting driver from xserver 1.20.

Bugzilla: https://bugs.freedesktop.org/106351
Tested-by: Mike Lothian 
Signed-off-by: Michel Dänzer 
---
 src/loader/loader_dri3_helper.c | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index 6db8303d26d..f0ff2f07bde 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -370,9 +370,17 @@ dri3_handle_present_event(struct loader_dri3_drawable 
*draw,
* checking for wrap.
*/
   if (ce->kind == XCB_PRESENT_COMPLETE_KIND_PIXMAP) {
- draw->recv_sbc = (draw->send_sbc & 0xLL) | ce->serial;
- if (draw->recv_sbc > draw->send_sbc)
-draw->recv_sbc -= 0x1;
+ uint64_t recv_sbc = (draw->send_sbc & 0xLL) | 
ce->serial;
+
+ /* Only assume wraparound if that results in exactly the previous
+  * SBC + 1, otherwise ignore received SBC > sent SBC (those are
+  * probably from a previous loader_dri3_drawable instance) to avoid
+  * calculating bogus target MSC values in loader_dri3_swap_buffers_msc
+  */
+ if (recv_sbc <= draw->send_sbc)
+draw->recv_sbc = recv_sbc;
+ else if (recv_sbc == (draw->recv_sbc + 0x10001ULL))
+draw->recv_sbc = recv_sbc - 0x1ULL;
 
  /* When moving from flip to copy, we assume that we can allocate in
   * a more optimal way if we don't need to cater for the display
-- 
2.17.0

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Re: [Mesa-dev] [PATCH 1/3] intel/compiler: make brw_reg_type_from_bit_size usable from other places

[Chema Casanova]

El 15/05/18 a las 13:05, Iago Toral Quiroga escribió:
> This was private to brw_fs_nir.cpp but we are going to need it soon in
> brw_fs.cpp, so move it there and make it available to other files as we
> do for other utility functions.
> ---
>  src/intel/compiler/brw_fs.cpp | 59 
> +++
>  src/intel/compiler/brw_fs.h   |  4 +++
>  src/intel/compiler/brw_fs_nir.cpp | 59 
> ---
>  3 files changed, 63 insertions(+), 59 deletions(-)
> 
> diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
> index dcba4ee8068..458c534c9c7 100644
> --- a/src/intel/compiler/brw_fs.cpp
> +++ b/src/intel/compiler/brw_fs.cpp
> @@ -900,6 +900,65 @@ fs_inst::size_read(int arg) const
> return 0;
>  }
>  
> +/*
> + * Returns a type based on a reference_type (word, float, half-float) and a
> + * given bit_size.
> + *
> + * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
> + *
> + * @FIXME: 64-bit return types are always DF on integer types to maintain
> + * compability with uses of DF previously to the introduction of int64
> + * support.
> + */

This FIXME comment doesn't apply to current code so it can be removed.

With that:

Reviewed-by: Jose Maria Casanova Crespo 


> +brw_reg_type
> +brw_reg_type_from_bit_size(const unsigned bit_size,
> +   const brw_reg_type reference_type)
> +{
> +   switch(reference_type) {
> +   case BRW_REGISTER_TYPE_HF:
> +   case BRW_REGISTER_TYPE_F:
> +   case BRW_REGISTER_TYPE_DF:
> +  switch(bit_size) {
> +  case 16:
> + return BRW_REGISTER_TYPE_HF;
> +  case 32:
> + return BRW_REGISTER_TYPE_F;
> +  case 64:
> + return BRW_REGISTER_TYPE_DF;
> +  default:
> + unreachable("Invalid bit size");
> +  }
> +   case BRW_REGISTER_TYPE_W:
> +   case BRW_REGISTER_TYPE_D:
> +   case BRW_REGISTER_TYPE_Q:
> +  switch(bit_size) {
> +  case 16:
> + return BRW_REGISTER_TYPE_W;
> +  case 32:
> + return BRW_REGISTER_TYPE_D;
> +  case 64:
> + return BRW_REGISTER_TYPE_Q;
> +  default:
> + unreachable("Invalid bit size");
> +  }
> +   case BRW_REGISTER_TYPE_UW:
> +   case BRW_REGISTER_TYPE_UD:
> +   case BRW_REGISTER_TYPE_UQ:
> +  switch(bit_size) {
> +  case 16:
> + return BRW_REGISTER_TYPE_UW;
> +  case 32:
> + return BRW_REGISTER_TYPE_UD;
> +  case 64:
> + return BRW_REGISTER_TYPE_UQ;
> +  default:
> + unreachable("Invalid bit size");
> +  }
> +   default:
> +  unreachable("Unknown type");
> +   }
> +}
> +
>  namespace {
> /* Return the subset of flag registers that an instruction could
>  * potentially read or write based on the execution controls and flag
> diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
> index e384db809dc..c4d5ebee239 100644
> --- a/src/intel/compiler/brw_fs.h
> +++ b/src/intel/compiler/brw_fs.h
> @@ -525,4 +525,8 @@ fs_reg setup_imm_df(const brw::fs_builder ,
>  enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode,
> nir_intrinsic_op op);
>  
> +brw_reg_type
> +brw_reg_type_from_bit_size(const unsigned bit_size,
> +   const brw_reg_type reference_type);
> +
>  #endif /* BRW_FS_H */
> diff --git a/src/intel/compiler/brw_fs_nir.cpp 
> b/src/intel/compiler/brw_fs_nir.cpp
> index 58ddc456bae..490fd4a0461 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -260,65 +260,6 @@ fs_visitor::nir_emit_system_values()
> }
>  }
>  
> -/*
> - * Returns a type based on a reference_type (word, float, half-float) and a
> - * given bit_size.
> - *
> - * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
> - *
> - * @FIXME: 64-bit return types are always DF on integer types to maintain
> - * compability with uses of DF previously to the introduction of int64
> - * support.
> - */
> -static brw_reg_type
> -brw_reg_type_from_bit_size(const unsigned bit_size,
> -   const brw_reg_type reference_type)
> -{
> -   switch(reference_type) {
> -   case BRW_REGISTER_TYPE_HF:
> -   case BRW_REGISTER_TYPE_F:
> -   case BRW_REGISTER_TYPE_DF:
> -  switch(bit_size) {
> -  case 16:
> - return BRW_REGISTER_TYPE_HF;
> -  case 32:
> - return BRW_REGISTER_TYPE_F;
> -  case 64:
> - return BRW_REGISTER_TYPE_DF;
> -  default:
> - unreachable("Invalid bit size");
> -  }
> -   case BRW_REGISTER_TYPE_W:
> -   case BRW_REGISTER_TYPE_D:
> -   case BRW_REGISTER_TYPE_Q:
> -  switch(bit_size) {
> -  case 16:
> - return BRW_REGISTER_TYPE_W;
> -  case 32:
> - return BRW_REGISTER_TYPE_D;
> -  case 64:
> - return BRW_REGISTER_TYPE_Q;
> -  default:
> - unreachable("Invalid bit size");
> -  }
> -   case BRW_REGISTER_TYPE_UW:
> -   

[Mesa-dev] [PATCH v2 1/2] cast the "GLenum16" to "GLint" to avoid compile warning on android

[jenny.q.cao]

force cast the I to GLint to avoid the compile warning when type is GLenum16, in
vendor/intel/external/mesa3d-intel/src/mesa/main/get.c:3005:19: warning: 
comparison of constant -32768 with
expression of type 'GLenum16' (aka 'unsigned short') is always false 
-Wtautologicalia-constant-out-of-range-compare

Tests: compilation without this warning
Signed-off-by: jenny.q.cao 
---
 src/mesa/main/get.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 90ab7ca60f8b..5f9a60b0801c 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -3002,7 +3002,7 @@ _mesa_GetFixedv(GLenum pname, GLfixed *params)
   break;
 
case TYPE_ENUM16:
-  params[0] = INT_TO_FIXED(((GLenum16 *) p)[0]);
+  params[0] = INT_TO_FIXED((GLint)(((GLenum16 *) p)[0]));
   break;
 
case TYPE_INT_N:
-- 
1.9.1

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[Mesa-dev] [PATCH 1/2] glsl: always enable OES_standard_derivatives features if supported

[Timothy Arceri]

The GLSL ES 1.0 spec made these features optional. With
OES_standard_derivatives they are guaranteed to be available
but currently the extension must be enabled to use them.

Instead this changes the code to check if the driver supports
the extension and if so always enables them.

This fixes compiler errors in Google Earth VR.
---
 src/compiler/glsl/builtin_functions.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/glsl/builtin_functions.cpp 
b/src/compiler/glsl/builtin_functions.cpp
index e1ee9943172..1ecbdc98404 100644
--- a/src/compiler/glsl/builtin_functions.cpp
+++ b/src/compiler/glsl/builtin_functions.cpp
@@ -446,7 +446,7 @@ fs_oes_derivatives(const _mesa_glsl_parse_state *state)
 {
return state->stage == MESA_SHADER_FRAGMENT &&
   (state->is_version(110, 300) ||
-   state->OES_standard_derivatives_enable);
+   state->extensions->OES_standard_derivatives);
 }
 
 static bool
-- 
2.17.0

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[Mesa-dev] [PATCH 2/2] glsl: allow linking ES shaders with desktop shaders in desktop GL

[Timothy Arceri]

In GLES shader versions must match but there is nothing
in the ARB_ES*_compatibility specs that say they must match.

This fixes some compilation errors in Google Earth VR.
---
 src/compiler/glsl/linker.cpp | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index f060c5316fa..2b7ee0ad5a6 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -83,6 +83,7 @@
 #include "builtin_functions.h"
 #include "shader_cache.h"
 
+#include "main/context.h"
 #include "main/imports.h"
 #include "main/shaderobj.h"
 #include "main/enums.h"
@@ -4799,7 +4800,8 @@ link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
   min_version = MIN2(min_version, prog->Shaders[i]->Version);
   max_version = MAX2(max_version, prog->Shaders[i]->Version);
 
-  if (prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
+  if (!_mesa_is_desktop_gl(ctx) &&
+  prog->Shaders[i]->IsES != prog->Shaders[0]->IsES) {
  linker_error(prog, "all shaders must use same shading "
   "language version\n");
  goto done;
@@ -4817,7 +4819,7 @@ link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
/* In desktop GLSL, different shader versions may be linked together.  In
 * GLSL ES, all shader versions must be the same.
 */
-   if (prog->Shaders[0]->IsES && min_version != max_version) {
+   if (!_mesa_is_desktop_gl(ctx) && min_version != max_version) {
   linker_error(prog, "all shaders must use same shading "
"language version\n");
   goto done;
-- 
2.17.0

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[Mesa-dev] [Bug 106536] glXWaitVideoSyncSGI blocks forever

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106536

--- Comment #1 from Michel Dänzer  ---
Please attach a backtrace of the app when it hangs, and the corresponding Xorg
log file.

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[Mesa-dev] [Bug 106351] Freezes with plasmashell and steam client

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106351

Michel Dänzer  changed:

   What|Removed |Added

 CC||tobias.johannes.klausmann@m
   ||ni.thm.de

--- Comment #16 from Michel Dänzer  ---
*** Bug 106372 has been marked as a duplicate of this bug. ***

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[Mesa-dev] [Bug 106351] Freezes with plasmashell and steam client

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106351

Markus Rathgeb  changed:

   What|Removed |Added

 CC||maggu2...@gmail.com

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[Mesa-dev] [Bug 106536] glXWaitVideoSyncSGI blocks forever

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106536

Bug ID: 106536
   Summary: glXWaitVideoSyncSGI blocks forever
   Product: Mesa
   Version: 18.0
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: GLX
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: ge...@hostfission.com
QA Contact: mesa-dev@lists.freedesktop.org

Before mesa 18.0 glXWaitVideoSyncSGI worked perfectly, but after updating to
mesa 18 it blocks forever, see the following for the code exhibiting this
behavior.

https://github.com/gnif/LookingGlass/blob/da2bcfdf9a3d559928a450cfc4642e8635c8f71f/client/renderers/opengl.c#L433

We have seen this occur on AMD hardware, I personally can reproduce it on a
Vega 56. It may affect other platforms but I can not confirm.

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Re: [Mesa-dev] [PATCH 9.5/17] squash! i965/miptree: Unify aux buffer allocation

[Pohjolainen, Topi]

On Wed, May 09, 2018 at 10:47:24AM -0700, Nanley Chery wrote:
> v2: Inline the switch statement (Jason)
> 
> Reviewed-by: Jason Ekstrand 
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 90 ---
>  1 file changed, 38 insertions(+), 52 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index f78b862a702..b5d7d691ecc 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -1777,30 +1777,37 @@ intel_miptree_level_enable_hiz(struct brw_context 
> *brw,
>  }
>  
>  
> -/* Returns true iff all params are successfully filled. */
> -static bool
> -get_aux_buf_params(const struct brw_context *brw,
> -   const struct intel_mipmap_tree *mt,
> -   enum isl_aux_state *initial_state,
> -   uint8_t *memset_value,
> -   struct isl_surf *aux_surf)
> +/**
> + * Allocate the initial aux surface for a miptree based on mt->aux_usage
> + *
> + * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
> + * create the auxiliary surfaces up-front.  CCS_D, on the other hand, can 
> only
> + * compress clear color so we wait until an actual fast-clear to allocate it.
> + */
> +bool
> +intel_miptree_alloc_aux(struct brw_context *brw,
> +struct intel_mipmap_tree *mt)
>  {
> -   assert(initial_state && memset_value && aux_surf);
> +   assert(mt->aux_buf == NULL);
> +
> +   /* Get the aux buf allocation parameters for this miptree. */
> +   enum isl_aux_state initial_state;
> +   uint8_t memset_value;
> +   struct isl_surf aux_surf;
> +   bool aux_surf_ok;
>  
> switch (mt->aux_usage) {
> case ISL_AUX_USAGE_NONE:
> -  aux_surf->size = 0;
> -  return true;
> +  aux_surf.size = 0;
> +  aux_surf_ok = true;
> +  break;
> case ISL_AUX_USAGE_HIZ:
>assert(!_mesa_is_format_color_format(mt->format));
>  
> -  *initial_state = ISL_AUX_STATE_AUX_INVALID;
> -  {
> - MAYBE_UNUSED bool ok =
> -isl_surf_get_hiz_surf(>isl_dev, >surf, aux_surf);
> - assert(ok);
> -  }
> -  return true;
> +  initial_state = ISL_AUX_STATE_AUX_INVALID;
> +  aux_surf_ok = isl_surf_get_hiz_surf(>isl_dev, >surf, 
> _surf);
> +  assert(aux_surf_ok);
> +  break;
> case ISL_AUX_USAGE_MCS:
>assert(_mesa_is_format_color_format(mt->format));
>assert(brw->screen->devinfo.gen >= 7); /* MCS only used on Gen7+ */
> @@ -1817,14 +1824,11 @@ get_aux_buf_params(const struct brw_context *brw,
> * Note: the clear value for MCS buffers is all 1's, so we memset to
> * 0xff.
> */
> -  *initial_state = ISL_AUX_STATE_CLEAR;
> -  *memset_value = 0xFF;
> -  {
> - MAYBE_UNUSED bool ok =
> -isl_surf_get_mcs_surf(>isl_dev, >surf, aux_surf);
> - assert(ok);
> -  }
> -  return true;
> +  initial_state = ISL_AUX_STATE_CLEAR;
> +  memset_value = 0xFF;
> +  aux_surf_ok = isl_surf_get_mcs_surf(>isl_dev, >surf, 
> _surf);
> +  assert(aux_surf_ok);
> +  break;
> case ISL_AUX_USAGE_CCS_D:
> case ISL_AUX_USAGE_CCS_E:
>assert(_mesa_is_format_color_format(mt->format));
> @@ -1839,36 +1843,18 @@ get_aux_buf_params(const struct brw_context *brw,
> * A CCS value of 0 indicates that the corresponding block is in the
> * pass-through state which is what we want.
> *
> -   * For CCS_D, do the same thing. On gen9+, this avoids having any 
> undefined
> -   * bits in the aux buffer.
> +   * For CCS_D, do the same thing. On gen9+, this avoids having any
> +   * undefined bits in the aux buffer.
> */
> -  *initial_state = ISL_AUX_STATE_PASS_THROUGH;
> -  *memset_value = 0;
> -  return isl_surf_get_ccs_surf(>isl_dev, >surf, aux_surf, 0);
> +  initial_state = ISL_AUX_STATE_PASS_THROUGH;
> +  memset_value = 0;
> +  aux_surf_ok =
> + isl_surf_get_ccs_surf(>isl_dev, >surf, _surf, 0);

Should we assert here also?

 assert(aux_surf_ok);

> +  break;
> }
>  
> -   unreachable("Invalid aux usage");
> -}
> -
> -
> -/**
> - * Allocate the initial aux surface for a miptree based on mt->aux_usage
> - *
> - * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
> - * create the auxiliary surfaces up-front.  CCS_D, on the other hand, can 
> only
> - * compress clear color so we wait until an actual fast-clear to allocate it.
> - */
> -bool
> -intel_miptree_alloc_aux(struct brw_context *brw,
> -struct intel_mipmap_tree *mt)
> -{
> -   assert(mt->aux_buf == NULL);
> -
> -   /* Get the aux buf allocation parameters for this miptree. */
> -   enum isl_aux_state initial_state;
> -   uint8_t memset_value;
> -   struct isl_surf aux_surf;
> -   if (!get_aux_buf_params(brw, mt, _state, _value, 
>