Re: [Mesa-dev] INTEL_map_texture on i915/i965

[Tapani Pälli]

On 08/17/2018 07:37 AM, Jason Ekstrand wrote:
On Thu, Aug 16, 2018 at 10:39 PM Matt Turner > wrote:


On Thu, Aug 16, 2018 at 5:50 PM Jason Ekstrand mailto:ja...@jlekstrand.net>> wrote:
 > If that's true then the extension makes no sense other than maybe
"we're a
 > UMA, we can make things cheap." I think it's more likely that the
intention
 > is to use a fenced map through the GTT to do the detiling. That
said, given
 > how sketchy GTT maps are, it's still a pretty questionable
extension at
 > best and something we don't want to commit to going forward.

Why are you speculating about it instead of just reading the extension?


Replying to e-mails from my phone?  I know, not a good excuse.


https://www.khronos.org/registry/OpenGL/extensions/INTEL/INTEL_map_texture.txt

     This extension allows to create textures with 'linear' layout
which allows
     for simplified access on user side (potentially sacrificing some
     performance during texture sampling).


Yeah, that's pretty bad.  I mean, there probably are uses such as if 
you're doing piles of CPU-side rendering.  If someone really badly wants 
that trade-off, maybe it's worth implementing but I'm still a skeptic.




One use-case (at least on GLES side with EGL_KHR_lock_surface*) is to 
stream video data to a texture without having to do copy. Maybe using 
texture buffer objects gives this same/similar benefit (?)


// Tapani
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[Mesa-dev] [Bug 107601] Rise of the Tomb Raider Segmentation Fault when the game starts

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107601

Bug ID: 107601
   Summary: Rise of the Tomb Raider Segmentation Fault when the
game starts
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Vulkan/radeon
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: fin4...@hotmail.com
QA Contact: mesa-dev@lists.freedesktop.org

The game crashes when starting the benchmark or continue the game from the main
menu. A dialog pops up with a Segmentation Fault (signal 11) message and a
crash dump is created. Using latest Oibaf ppa Mesa git. The game did work four
days ago but not after Mesa update.

This Vulkan demo works fine:
http://nonfatmatt.blogspot.com/2018/07/new-demo-for-testing-unreal-engine-4-in.html

My System:
  Host: ryzenpc Kernel: 4.18.0-rc1+ x86_64 bits: 64 Desktop: Xfce 4.12.4 
  Distro: Debian GNU/Linux buster/sid 
Machine:
  Type: Desktop Mobo: ASUSTeK model: PRIME B350M-K v: Rev X.0x 
  serial:  UEFI: American Megatrends v: 4011 date: 04/19/2018 
CPU:
  6-Core: AMD Ryzen 5 1600 type: MT MCP speed: 2727 MHz 
Graphics:
  Card-1: AMD Baffin [Polaris11] driver: amdgpu v: kernel 
  Display: x11 server: X.Org 1.20.0 driver: amdgpu,ati 
  unloaded: fbdev,modesetting,vesa resolution: 1920x1080~60Hz 
  OpenGL: renderer: Radeon RX 560 Series (POLARIS11 DRM 3.27.0 4.18.0-rc1+ 
  LLVM 6.0.1) 
  v: 4.5 Mesa 18.3.0-devel

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Re: [Mesa-dev] [PATCH 5/5] anv/pipeline: Lower pipeline layouts etc. after linking

[Jason Ekstrand]

On Thu, Aug 16, 2018 at 10:11 PM Timothy Arceri 
wrote:

> Nice numbers :)
>
> I'm not sure I 100% follow the why for patch 1 but the logic seems
> correct for the way you want to change
>

I just sort-of found that one along the way.  It'd be good if Lionel took a
real quick look at it.


> t, and all other patches look
> good to me so series:
>
> Reviewed-by: Timothy Arceri 
>

Thanks!


> On 08/08/18 18:12, Jason Ekstrand wrote:
> > This allows us to use the link-optimized shader for determining binding
> > table layouts and, more importantly, URB layouts.  For apps running on
> > DXVK, this is extremely important as DXVK likes to declare max-size
> > inputs and outputs and this lets is massively shrink our URB space
> > requirements.
> >
> > VkPipeline-db results (Batman pipelines only) on KBL:
> >
> >  total instructions in shared programs: 820403 -> 790008 (-3.70%)
> >  instructions in affected programs: 273759 -> 243364 (-11.10%)
> >  helped: 622
> >  HURT: 42
> >
> >  total spills in shared programs: 8449 -> 5212 (-38.31%)
> >  spills in affected programs: 3427 -> 190 (-94.46%)
> >  helped: 607
> >  HURT: 2
> >
> >  total fills in shared programs: 11638 -> 6067 (-47.87%)
> >  fills in affected programs: 5879 -> 308 (-94.76%)
> >  helped: 606
> >  HURT: 3
> >
> > Looking at shaders by hand, it makes the URB between TCS and TES go from
> > containing 32 per-vertex varyings per tessellation shader pair to a more
> > reasonable 8-12.  For a 3-vertex patch, that's at least half the URB
> > space no matter how big the patch section is.
> > ---
> >   src/intel/vulkan/anv_pipeline.c | 58 -
> >   1 file changed, 28 insertions(+), 30 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_pipeline.c
> b/src/intel/vulkan/anv_pipeline.c
> > index d4d31a43213..7708486c442 100644
> > --- a/src/intel/vulkan/anv_pipeline.c
> > +++ b/src/intel/vulkan/anv_pipeline.c
> > @@ -472,24 +472,17 @@ anv_pipeline_hash_compute(struct anv_pipeline
> *pipeline,
> >  _mesa_sha1_final(, sha1_out);
> >   }
> >
> > -static nir_shader *
> > -anv_pipeline_compile(struct anv_pipeline *pipeline,
> > - void *mem_ctx,
> > - struct anv_pipeline_layout *layout,
> > - struct anv_pipeline_stage *stage,
> > - struct brw_stage_prog_data *prog_data,
> > - struct anv_pipeline_bind_map *map)
> > +static void
> > +anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
> > +   void *mem_ctx,
> > +   struct anv_pipeline_stage *stage,
> > +   struct anv_pipeline_layout *layout)
> >   {
> >  const struct brw_compiler *compiler =
> > pipeline->device->instance->physicalDevice.compiler;
> >
> > -   nir_shader *nir = anv_shader_compile_to_nir(pipeline, mem_ctx,
> > -   stage->module,
> > -   stage->entrypoint,
> > -   stage->stage,
> > -   stage->spec_info);
> > -   if (nir == NULL)
> > -  return NULL;
> > +   struct brw_stage_prog_data *prog_data = >prog_data.base;
> > +   nir_shader *nir = stage->nir;
> >
> >  NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
> >
> > @@ -531,15 +524,17 @@ anv_pipeline_compile(struct anv_pipeline *pipeline,
> > pipeline->needs_data_cache = true;
> >
> >  /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
> > -   if (layout)
> > -  anv_nir_apply_pipeline_layout(pipeline, layout, nir, prog_data,
> map);
> > +   if (layout) {
> > +  anv_nir_apply_pipeline_layout(pipeline, layout, nir, prog_data,
> > +>bind_map);
> > +   }
> >
> >  if (nir->info.stage != MESA_SHADER_COMPUTE)
> > brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
> prog_data->ubo_ranges);
> >
> >  assert(nir->num_uniforms == prog_data->nr_params * 4);
> >
> > -   return nir;
> > +   stage->nir = nir;
> >   }
> >
> >   static void
> > @@ -807,16 +802,12 @@ anv_pipeline_link_fs(const struct brw_compiler
> *compiler,
> >  stage->key.wm.color_outputs_valid = (1 << num_rts) - 1;
> >
> >  assert(num_rts <= max_rt);
> > -   assert(stage->bind_map.surface_count + num_rts <= 256);
> > -   memmove(stage->bind_map.surface_to_descriptor + num_rts,
> > -   stage->bind_map.surface_to_descriptor,
> > -   stage->bind_map.surface_count *
> > -   sizeof(*stage->bind_map.surface_to_descriptor));
> > +   assert(stage->bind_map.surface_count == 0);
> >  typed_memcpy(stage->bind_map.surface_to_descriptor,
> >   rt_bindings, num_rts);
> >  stage->bind_map.surface_count += num_rts;
> >
> > -   anv_fill_binding_table(>prog_data.wm.base, num_rts);
> > +   anv_fill_binding_table(>prog_data.wm.base, 0);
> >   }

Re: [Mesa-dev] INTEL_map_texture on i915/i965

[Jason Ekstrand]

On Thu, Aug 16, 2018 at 10:39 PM Matt Turner  wrote:

> On Thu, Aug 16, 2018 at 5:50 PM Jason Ekstrand 
> wrote:
> > If that's true then the extension makes no sense other than maybe "we're
> a
> > UMA, we can make things cheap." I think it's more likely that the
> intention
> > is to use a fenced map through the GTT to do the detiling. That said,
> given
> > how sketchy GTT maps are, it's still a pretty questionable extension at
> > best and something we don't want to commit to going forward.
>
> Why are you speculating about it instead of just reading the extension?
>

Replying to e-mails from my phone?  I know, not a good excuse.


>
> https://www.khronos.org/registry/OpenGL/extensions/INTEL/INTEL_map_texture.txt
>
> This extension allows to create textures with 'linear' layout which
> allows
> for simplified access on user side (potentially sacrificing some
> performance during texture sampling).
>

Yeah, that's pretty bad.  I mean, there probably are uses such as if you're
doing piles of CPU-side rendering.  If someone really badly wants that
trade-off, maybe it's worth implementing but I'm still a skeptic.

--Jason
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Re: [Mesa-dev] INTEL_map_texture on i915/i965

[Matt Turner]

On Thu, Aug 16, 2018 at 5:50 PM Jason Ekstrand  wrote:
> If that's true then the extension makes no sense other than maybe "we're a
> UMA, we can make things cheap." I think it's more likely that the intention
> is to use a fenced map through the GTT to do the detiling. That said, given
> how sketchy GTT maps are, it's still a pretty questionable extension at
> best and something we don't want to commit to going forward.

Why are you speculating about it instead of just reading the extension?

https://www.khronos.org/registry/OpenGL/extensions/INTEL/INTEL_map_texture.txt

This extension allows to create textures with 'linear' layout which allows
for simplified access on user side (potentially sacrificing some
performance during texture sampling).
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Re: [Mesa-dev] [PATCH 5/5] anv/pipeline: Lower pipeline layouts etc. after linking

[Timothy Arceri]

Nice numbers :)

I'm not sure I 100% follow the why for patch 1 but the logic seems 
correct for the way you want to change it, and all other patches look 
good to me so series:


Reviewed-by: Timothy Arceri 

On 08/08/18 18:12, Jason Ekstrand wrote:

This allows us to use the link-optimized shader for determining binding
table layouts and, more importantly, URB layouts.  For apps running on
DXVK, this is extremely important as DXVK likes to declare max-size
inputs and outputs and this lets is massively shrink our URB space
requirements.

VkPipeline-db results (Batman pipelines only) on KBL:

 total instructions in shared programs: 820403 -> 790008 (-3.70%)
 instructions in affected programs: 273759 -> 243364 (-11.10%)
 helped: 622
 HURT: 42

 total spills in shared programs: 8449 -> 5212 (-38.31%)
 spills in affected programs: 3427 -> 190 (-94.46%)
 helped: 607
 HURT: 2

 total fills in shared programs: 11638 -> 6067 (-47.87%)
 fills in affected programs: 5879 -> 308 (-94.76%)
 helped: 606
 HURT: 3

Looking at shaders by hand, it makes the URB between TCS and TES go from
containing 32 per-vertex varyings per tessellation shader pair to a more
reasonable 8-12.  For a 3-vertex patch, that's at least half the URB
space no matter how big the patch section is.
---
  src/intel/vulkan/anv_pipeline.c | 58 -
  1 file changed, 28 insertions(+), 30 deletions(-)

diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index d4d31a43213..7708486c442 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -472,24 +472,17 @@ anv_pipeline_hash_compute(struct anv_pipeline *pipeline,
 _mesa_sha1_final(, sha1_out);
  }
  
-static nir_shader *

-anv_pipeline_compile(struct anv_pipeline *pipeline,
- void *mem_ctx,
- struct anv_pipeline_layout *layout,
- struct anv_pipeline_stage *stage,
- struct brw_stage_prog_data *prog_data,
- struct anv_pipeline_bind_map *map)
+static void
+anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
+   void *mem_ctx,
+   struct anv_pipeline_stage *stage,
+   struct anv_pipeline_layout *layout)
  {
 const struct brw_compiler *compiler =
pipeline->device->instance->physicalDevice.compiler;
  
-   nir_shader *nir = anv_shader_compile_to_nir(pipeline, mem_ctx,

-   stage->module,
-   stage->entrypoint,
-   stage->stage,
-   stage->spec_info);
-   if (nir == NULL)
-  return NULL;
+   struct brw_stage_prog_data *prog_data = >prog_data.base;
+   nir_shader *nir = stage->nir;
  
 NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
  
@@ -531,15 +524,17 @@ anv_pipeline_compile(struct anv_pipeline *pipeline,

pipeline->needs_data_cache = true;
  
 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */

-   if (layout)
-  anv_nir_apply_pipeline_layout(pipeline, layout, nir, prog_data, map);
+   if (layout) {
+  anv_nir_apply_pipeline_layout(pipeline, layout, nir, prog_data,
+>bind_map);
+   }
  
 if (nir->info.stage != MESA_SHADER_COMPUTE)

brw_nir_analyze_ubo_ranges(compiler, nir, NULL, prog_data->ubo_ranges);
  
 assert(nir->num_uniforms == prog_data->nr_params * 4);
  
-   return nir;

+   stage->nir = nir;
  }
  
  static void

@@ -807,16 +802,12 @@ anv_pipeline_link_fs(const struct brw_compiler *compiler,
 stage->key.wm.color_outputs_valid = (1 << num_rts) - 1;
  
 assert(num_rts <= max_rt);

-   assert(stage->bind_map.surface_count + num_rts <= 256);
-   memmove(stage->bind_map.surface_to_descriptor + num_rts,
-   stage->bind_map.surface_to_descriptor,
-   stage->bind_map.surface_count *
-   sizeof(*stage->bind_map.surface_to_descriptor));
+   assert(stage->bind_map.surface_count == 0);
 typed_memcpy(stage->bind_map.surface_to_descriptor,
  rt_bindings, num_rts);
 stage->bind_map.surface_count += num_rts;
  
-   anv_fill_binding_table(>prog_data.wm.base, num_rts);

+   anv_fill_binding_table(>prog_data.wm.base, 0);
  }
  
  static const unsigned *

@@ -976,10 +967,11 @@ anv_pipeline_compile_graphics(struct anv_pipeline 
*pipeline,
   .sampler_to_descriptor = stages[s].sampler_to_descriptor
};
  
-  stages[s].nir = anv_pipeline_compile(pipeline, pipeline_ctx, layout,

-   [s],
-   [s].prog_data.base,
-   [s].bind_map);
+  stages[s].nir = anv_shader_compile_to_nir(pipeline, pipeline_ctx,
+  

[Mesa-dev] [Bug 106590] Wrong line numbers expanded while compiling shaders

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106590

--- Comment #4 from Zhaowei Yuan  ---
A new patch to fix this issue:
https://patchwork.freedesktop.org/patch/245027/

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[Mesa-dev] [PATCH] glcpp: Expand macro before expanding __LINE__ in its replacement

[Zhaowei Yuan]

From: zhaowei yuan 

If a macro which contains __LINE__ in its replacement, we should expand the
macro itself firstly and then expanding __LINE__, otherwise __LINE__ will
be expanded as an wrong line number.

This patch fixes following CTS test case:
dEQP-GLES2.functional.shaders.preprocessor.predefined_macros.line_2_vertex
dEQP-GLES2.functional.shaders.preprocessor.predefined_macros.line_2_fragment
dEQP-GLES3.functional.shaders.preprocessor.predefined_macros.line_2_vertex
dEQP-GLES3.functional.shaders.preprocessor.predefined_macros.line_2_fragment

Signed-off-by: zhaowei yuan 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106590

Signed-off-by: zhaowei yuan 
---
 src/compiler/glsl/glcpp/glcpp-lex.l   |  1 +
 src/compiler/glsl/glcpp/glcpp-parse.y | 55 ++-
 src/compiler/glsl/glcpp/glcpp.h   |  4 ++-
 src/compiler/glsl/glcpp/pp.c  |  3 +-
 4 files changed, 54 insertions(+), 9 deletions(-)

diff --git a/src/compiler/glsl/glcpp/glcpp-lex.l 
b/src/compiler/glsl/glcpp/glcpp-lex.l
index 9cfcc12..86b82c2 100644
--- a/src/compiler/glsl/glcpp/glcpp-lex.l
+++ b/src/compiler/glsl/glcpp/glcpp-lex.l
@@ -50,6 +50,7 @@ void glcpp_set_column (int  column_no , yyscan_t yyscanner);
yylloc->first_line = yylloc->last_line = yylineno;  \
yycolumn += yyleng; \
yylloc->last_column = yycolumn + 1; \
+   yylloc->position = (yytext - 
YY_CURRENT_BUFFER_LVALUE->yy_ch_buf); \
parser->has_new_line_number = 0;\
parser->has_new_source_number = 0;  \
} while(0);
diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y 
b/src/compiler/glsl/glcpp/glcpp-parse.y
index 4be5cfa..27a1873 100644
--- a/src/compiler/glsl/glcpp/glcpp-parse.y
+++ b/src/compiler/glsl/glcpp/glcpp-parse.y
@@ -1016,7 +1016,7 @@ _token_list_append_list(token_list_t *list, token_list_t 
*tail)
 }
 
 static token_list_t *
-_token_list_copy(glcpp_parser_t *parser, token_list_t *other)
+_token_list_copy(glcpp_parser_t *parser, token_list_t *other, token_node_t 
*macro_node)
 {
token_list_t *copy;
token_node_t *node;
@@ -1028,6 +1028,12 @@ _token_list_copy(glcpp_parser_t *parser, token_list_t 
*other)
for (node = other->head; node; node = node->next) {
   token_t *new_token = linear_alloc_child(parser->linalloc, 
sizeof(token_t));
   *new_token = *node->token;
+
+  if (macro_node) {
+ new_token->location.first_line = 
macro_node->token->location.first_line;
+ new_token->location.last_line = macro_node->token->location.last_line;
+  }
+
   _token_list_append (parser, copy, new_token);
}
 
@@ -1344,7 +1350,7 @@ add_builtin_define(glcpp_parser_t *parser, const char 
*name, int value)
 
 glcpp_parser_t *
 glcpp_parser_create(const struct gl_extensions *extension_list,
-glcpp_extension_iterator extensions, void *state, gl_api 
api)
+glcpp_extension_iterator extensions, void *state, gl_api 
api, const char *input)
 {
glcpp_parser_t *parser;
 
@@ -1372,6 +1378,11 @@ glcpp_parser_create(const struct gl_extensions 
*extension_list,
parser->lex_from_list = NULL;
parser->lex_from_node = NULL;
 
+   parser->input = _mesa_string_buffer_create(parser, strlen(input) + 1);
+   strcpy(parser->input->buf, input);
+   parser->input->buf[strlen(input)] = '\0';
+   parser->input->length = strlen(input);
+
parser->output = _mesa_string_buffer_create(parser,
INITIAL_PP_OUTPUT_BUF_SIZE);
parser->info_log = _mesa_string_buffer_create(parser,
@@ -1436,7 +1447,7 @@ typedef enum function_status
 static function_status_t
 _arguments_parse(glcpp_parser_t *parser,
  argument_list_t *arguments, token_node_t *node,
- token_node_t **last)
+ token_node_t **last, int *end_position)
 {
token_list_t *argument;
int paren_count;
@@ -1460,8 +1471,10 @@ _arguments_parse(glcpp_parser_t *parser,
  paren_count++;
   } else if (node->token->type == ')') {
  paren_count--;
- if (paren_count == 0)
+ if (paren_count == 0) {
+*end_position = node->token->location.position;
 break;
+ }
   }
 
   if (node->token->type == ',' && paren_count == 1) {
@@ -1697,6 +1710,28 @@ _glcpp_parser_apply_pastes(glcpp_parser_t *parser, 
token_list_t *list)
list->non_space_tail = list->tail;
 }
 
+static int
+_glcpp_parser_get_line(glcpp_parser_t *parser, int offset)
+{
+   int line = 1;
+   int i;
+
+   for (i = 0; parser->input->buf[i] && i <= offset; i++) {
+  if (parser->input->buf[i] == '\n' || parser->input->buf[i] == '\r')
+ line++;
+   }
+
+   return line;
+}
+
+static void
+_glcpp_sync_location(glcpp_parser_t *parser, token_t *token, token_t 
*macro_token)
+{
+   token->location.source 

Re: [Mesa-dev] [PATCH 03/13] docs: Initial version of INTEL_shader_atomic_float_minmax spec

[Caio Marcelo de Oliveira Filho]

Hello,

> +(add a new row after the exiting "atomicMax" table row, p. 179)
> +
> +float atomicMax(inout float mem, float data)
> +
> +Computes a new value by taking the maximum of the value of data and
> + the contents of mem.  If one of these is an IEEE signaling NaN (i.e.,

The two lines above have different indentations, maybe the
"Computes..." line should be starting with a TAB.


> +Interactions with OpenGL 4.6 and ARB_gl_spirv
> +
> +If OpenGL 4.6 or ARB_gl_spirv is supported, then
> +SPV_INTEL_shader_atomic_float_minmax must also be supported.

Couldn't find the SPIR-V extension, but I guess is work in
progress.  Is there a Vulkan extension too?


> +* atomicMin and atomicMax implement the IEEE specification with respect 
> to
> +  NaN.  IEEE considers two different kinds of NaN: signaling NaN and 
> quiet
> +  NaN.  A quiet NaN has the most significant bit of the mantissa set, and
> +  a signaling NaN does not.  This concept does not exist in SPIR-V,
> +  Vulkan, or OpenGL.  Let qNaN denote a quiet NaN and sNaN denote a
> +  signaling NaN.  atomicMin and atomicMax specifically implement
> +
> +  - fmin(qNaN, x) = fmin(x, qNaN) = fmax(qNaN, x) = fmax(x, qNaN) = x
> +  - fmin(sNaN, x) = fmin(x, sNaN) = fmax(sNaN, x) = fmax(x, sNaN) = sNaN
> +  - fmin(sNaN, qNaN) = fmin(qNaN, sNaN) = fmax(sNaN, qNaN) =
> +fmax(qNaN, sNaN) = sNaN

For the two items above, is it implicit that the result will be
quietized?  This matters when using such result with other operation
with a real value, e.g. is "fmin(fmin(x, sNaN), y)" equals to "y" or
to "sNaN"?

The PRM for Skylake says

"Max(x, sNaN) = Max(sNaN, x) = qNaN (quietized value corresponding
to the input sNaN) and signal the Invalid Operation exception."


Thanks,
Caio
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Re: [Mesa-dev] INTEL_map_texture on i915/i965

[Jason Ekstrand]

If that's true then the extension makes no sense other than maybe "we're a 
UMA, we can make things cheap." I think it's more likely that the intention 
is to use a fenced map through the GTT to do the detiling. That said, given 
how sketchy GTT maps are, it's still a pretty questionable extension at 
best and something we don't want to commit to going forward.


--Jason


On August 16, 2018 13:02:50 Ian Romanick  wrote:


My recollection is that we never implemented this because it required
linear textures instead of tiled textures.  In every speed test we did,
the read performance of tiled textures was so much better than the read
performance of linear textures that it seemed unlikely to be a benefit.
Instead, we chose to spend time making our regular texture upload paths
more performant.

On 08/16/2018 06:23 AM, Phi Nguyen wrote:

Hi,

I hope to use the zero-memory copy on the Iris Pro 6200 (Broadwell/Skylake).

The extension
 
says

only OpenGL 3.0 is required yet it does not show up on Ubuntu 18.04.  I
saw a post from 2016
 
mentioning

this feature, but that didn't get any replies.

Does an implementation of this even exist?  How would I go about getting it?

Thank you,
Phi


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[Mesa-dev] [Bug 107457] [Tracker] Mesa 18.2 release tracker

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107457
Bug 107457 depends on bug 107510, which changed state.

Bug 107510 Summary: [GEN8+] up to 10% perf drop on several 3D benchmarks
https://bugs.freedesktop.org/show_bug.cgi?id=107510

   What|Removed |Added

 Status|ASSIGNED|RESOLVED
 Resolution|--- |FIXED

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Re: [Mesa-dev] [PATCH 1/2] compiler/glsl/tests: Make tests python3 safe

[Mathieu Bridon]

On Thu, 2018-08-16 at 14:21 -0700, Dylan Baker wrote:
> ---
> 
> I didn't see any patches from anyone else, so I wrote some real
> quick. Please
> point to them if other patches already exist.

I was about to send mine, but you were faster. >_<

They ar every similar though, except that you missed glcpp_test.py,
which requires a few more changes. (I have them ready, and can send
them separately)

> diff --git a/src/compiler/glsl/tests/optimization_test.py
> b/src/compiler/glsl/tests/optimization_test.py
> index 577d2dfc20f..f40d0cee6bd 100755
> --- a/src/compiler/glsl/tests/optimization_test.py
> +++ b/src/compiler/glsl/tests/optimization_test.py
> @@ -1,4 +1,4 @@
> -#!/usr/bin/env python2
> +#!/usr/bin/env python
>  # encoding=utf-8
>  # Copyright © 2018 Intel Corporation
>  
> @@ -71,7 +71,9 @@ def main():
>  stdout=subprocess.PIPE,
>  stderr=subprocess.PIPE,
>  stdin=subprocess.PIPE)
> -out, err = proc.communicate(source)
> +out, err = proc.communicate(source.encode())
> +out = out.decode()
> +err = err.decode()

I usually find it too unpredictable to use the default encoding, and
prefer always specifying 'utf-8'. (even on Python 3, you can't be sure
that will always be the default)

> diff --git a/src/compiler/glsl/tests/sexps.py
> b/src/compiler/glsl/tests/sexps.py
> index a714af8d236..b69d3a5e5d7 100644
> --- a/src/compiler/glsl/tests/sexps.py
> +++ b/src/compiler/glsl/tests/sexps.py
> @@ -28,6 +28,11 @@
>  # as ['constant', 'float', ['1.00']].
>  
>  import re
> +import sys
> +if sys.version_info >= (3, 0, 0):
> +STRINGS = str
> +else:
> +STRINGS = (str, unicode)
>  
>  def check_sexp(sexp):
>  """Verify that the argument is a proper sexp.
> @@ -39,7 +44,7 @@ def check_sexp(sexp):
>  if isinstance(sexp, list):
>  for s in sexp:
>  check_sexp(s)
> -elif not isinstance(sexp, basestring):
> +elif not isinstance(sexp, STRINGS):
>  raise Exception('Not a sexp: {0!r}'.format(sexp))
>  
>  def parse_sexp(sexp):
> @@ -70,7 +75,7 @@ def sexp_to_string(sexp):
>  """Convert a sexp, represented as nested lists containing
> strings,
>  into a single string of the form parseable by mesa.
>  """
> -if isinstance(sexp, basestring):
> +if isinstance(sexp, STRINGS):
>  return sexp

Someone on this list ( :P ) once told me to avoid mising bytes and
strings.

In this case, I believe the patch would be better as follows:

-if isinstance(sexp, basestring):
+if isinstance(sexp, bytes):
+return sexp.decode('utf-8')
+if isinstance(sexp, string_type):
 return sexp

And then the previous hunks can be:

+if sys.version_info < (3, 0):
+string_type = unicode
+else:
+string_type = str
…
-elif not isinstance(sexp, basestring):
+elif not isinstance(sexp, (string_type, bytes)):


-- 
Mathieu

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[Mesa-dev] [Bug 83785] Shader branches excluded by uniform values are not optimized out

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=83785

--- Comment #5 from Roland Scheidegger  ---
Well it was already classified as an enhancement, so technically it's still
open (I actually wrote some code to fix this but it's not fully fleshed out and
never finished it).

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[Mesa-dev] [Bug 107594] [PATCH] fix crosscompilling with meson

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107594

Dylan Baker  changed:

   What|Removed |Added

 CC||baker.dyla...@gmail.com
   Assignee|mesa-dev@lists.freedesktop. |baker.dyla...@gmail.com
   |org |

--- Comment #1 from Dylan Baker  ---
In the future please send patches to the list to review, we don't do review in
bugzilla (https://www.mesa3d.org/submittingpatches.html).

I don't think this patch is correct, however. The only time that one should be
building that binary is in an [x86, x86_64] -> [x86, x86_64] case, and it needs
to be built for the host architecture (in meson speak, the host is the platform
running the code).

What his your build machine architecture and host machine architecture? I think
there might be a bug from non-x86 to x86*, now that I look at this code closer.

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Re: [Mesa-dev] [PATCH 09/21] mesa: remove legacy TCL dri config options

[Roland Scheidegger]

Am 15.08.2018 um 20:47 schrieb Ian Romanick:
> On 08/15/2018 04:09 AM, Timothy Arceri wrote:
>> On 15/08/18 20:26, Michel Dänzer wrote:
>>> On 2018-08-15 12:13 PM, Timothy Arceri wrote:
 Use enviroment var overrides in legacy drivers instead.
>>>
>>> This could break existing user configurations using the driconf tcl_mode
>>> option.
>>>
>>> Apart from this, I like the idea of this series.
>>
>> I assumed this was a debug like option. If you think I should keep the
>> dri config entry I can move it to the driver.
> 
> I have some vague recollection that at least at one time there were
> applications that didn't work with HW TNL on at least R100 cards... or
> maybe they just had rubbish performance.  The memories are pretty fuzzy.
>  Moving it to the driver and deleting the duplicate envvar seems like
> the safest option.
> 

I suspect there might be issues with z-fighting if the app renders
something which causes tcl fallbacks and something which doesn't. Albeit
I don't think the state changes causing fallbacks or not would be
covered under the GL invariance guarantee, apps wouldn't care about such
details. So just forcing it off always would prevent this. Can't
remember neither though if it was an actual problem with some apps.

Roland
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[Mesa-dev] [PATCH 1/2] compiler/glsl/tests: Make tests python3 safe

[Dylan Baker]

---

I didn't see any patches from anyone else, so I wrote some real quick. Please
point to them if other patches already exist.

 src/compiler/glsl/tests/lower_jump_cases.py  | 2 +-
 src/compiler/glsl/tests/optimization_test.py | 6 --
 src/compiler/glsl/tests/sexps.py | 9 +++--
 3 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/src/compiler/glsl/tests/lower_jump_cases.py 
b/src/compiler/glsl/tests/lower_jump_cases.py
index b50ab734798..1977f3a9b4f 100644
--- a/src/compiler/glsl/tests/lower_jump_cases.py
+++ b/src/compiler/glsl/tests/lower_jump_cases.py
@@ -54,7 +54,7 @@ def make_test_case(f_name, ret_type, body):
 else:
 make_declarations(s, already_declared)
 make_declarations(body)
-return declarations.values() + \
+return list(declarations.values()) + \
 [['function', f_name, ['signature', ret_type, ['parameters'], body]]]
 
 
diff --git a/src/compiler/glsl/tests/optimization_test.py 
b/src/compiler/glsl/tests/optimization_test.py
index 577d2dfc20f..f40d0cee6bd 100755
--- a/src/compiler/glsl/tests/optimization_test.py
+++ b/src/compiler/glsl/tests/optimization_test.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python2
+#!/usr/bin/env python
 # encoding=utf-8
 # Copyright © 2018 Intel Corporation
 
@@ -71,7 +71,9 @@ def main():
 stdout=subprocess.PIPE,
 stderr=subprocess.PIPE,
 stdin=subprocess.PIPE)
-out, err = proc.communicate(source)
+out, err = proc.communicate(source.encode())
+out = out.decode()
+err = err.decode()
 if err:
 print('FAIL')
 print('Unexpected output on stderr: {}'.format(err),
diff --git a/src/compiler/glsl/tests/sexps.py b/src/compiler/glsl/tests/sexps.py
index a714af8d236..b69d3a5e5d7 100644
--- a/src/compiler/glsl/tests/sexps.py
+++ b/src/compiler/glsl/tests/sexps.py
@@ -28,6 +28,11 @@
 # as ['constant', 'float', ['1.00']].
 
 import re
+import sys
+if sys.version_info >= (3, 0, 0):
+STRINGS = str
+else:
+STRINGS = (str, unicode)
 
 def check_sexp(sexp):
 """Verify that the argument is a proper sexp.
@@ -39,7 +44,7 @@ def check_sexp(sexp):
 if isinstance(sexp, list):
 for s in sexp:
 check_sexp(s)
-elif not isinstance(sexp, basestring):
+elif not isinstance(sexp, STRINGS):
 raise Exception('Not a sexp: {0!r}'.format(sexp))
 
 def parse_sexp(sexp):
@@ -70,7 +75,7 @@ def sexp_to_string(sexp):
 """Convert a sexp, represented as nested lists containing strings,
 into a single string of the form parseable by mesa.
 """
-if isinstance(sexp, basestring):
+if isinstance(sexp, STRINGS):
 return sexp
 assert isinstance(sexp, list)
 result = ''
-- 
2.18.0

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[Mesa-dev] [PATCH 2/2] meson: Use python3 to run glsl tests

[Dylan Baker]

---
 src/compiler/glsl/tests/meson.build | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/compiler/glsl/tests/meson.build 
b/src/compiler/glsl/tests/meson.build
index fc7b863a278..2a41e30a28d 100644
--- a/src/compiler/glsl/tests/meson.build
+++ b/src/compiler/glsl/tests/meson.build
@@ -84,8 +84,10 @@ test(
 )
 
 test(
-  'glsl compiler warnings', find_program('warnings_test.py'),
+  'glsl compiler warnings',
+  prog_python,
   args : [
+join_paths(meson.current_source_dir(), 'warnings_test.py'),
 '--glsl-compiler', glsl_compiler,
 '--test-directory', join_paths(
   meson.source_root(), 'src', 'compiler', 'glsl', 'tests', 'warnings'
@@ -94,6 +96,9 @@ test(
 )
 test(
   'glsl optimization',
-  find_program('optimization_test.py'),
-  args : ['--test-runner', glsl_test],
+  prog_python,
+  args : [
+join_paths(meson.current_source_dir(), 'optimization_test.py'),
+'--test-runner', glsl_test
+  ],
 )
-- 
2.18.0

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Re: [Mesa-dev] [PATCH 12/13] winsys/amdgpu: add vcn jpeg cs support

[Boyuan Zhang]

On 2018-08-16 01:41 PM, Leo Liu wrote:



On 08/16/2018 12:06 PM, boyuan.zh...@amd.com wrote:

From: Boyuan Zhang 

Add vcn jpeg cs support, align cs by no-op.

Signed-off-by: Boyuan Zhang 
---
  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 12 
  1 file changed, 12 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

index a3feeb9..5092f49 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -840,6 +840,10 @@ static bool amdgpu_init_cs_context(struct 
amdgpu_cs_context *cs,

    cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_ENC;
    break;
  +   case RING_VCN_JPEG:
+  cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_JPEG;
+  break;
+
 default:
 case RING_GFX:
    cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_GFX;
@@ -1545,6 +1549,14 @@ static int amdgpu_cs_flush(struct 
radeon_winsys_cs *rcs,

    while (rcs->current.cdw & 15)
   radeon_emit(rcs, 0x8000); /* type2 nop packet */
    break;
+   case RING_VCN_JPEG:
+  if (rcs->current.cdw % 2)
+ assert(0);
+  while (rcs->current.cdw & 15) {
+ radeon_emit(rcs, 0x6000); /* nop packet */
+ radeon_emit(rcs, 0x);
+  }
+  break;
 case RING_VCN_DEC:
    while (rcs->current.cdw & 15)
   radeon_emit(rcs, 0x81ff); /* nop packet */

The patch is:
Reviewed-by: Leo Liu 

BTW, if you got chance, please fix the NOP for VCN DEC here in the 
same way. i.e 0x81ff and 0.


Regards,
Leo



Sure, I will prepare a separate patch for that.

Regards,
Boyuan









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[Mesa-dev] [PATCH 2/4] i965: Allow creation of brw_bo from system memory (userptr)

[Chris Wilson]

Since v3.16 (though universal access was only enabled by default in v4.6),
the kernel has offered the ability to wrap any system memory (i.e. RAM
and not I/O mapped memory) into an object that can be used by the GPU. The
caveat is that this object is marked as cache coherent (so that the client
can continue accessing the memory blissfully ignorant of the
synchronisation required with the GPU) and on !llc platforms this means
that the object is snooped. Snooping imposes a large performance penalty
and is only advised to be used for one-off transfers. However, it provides
another useful tool in the driver toolbox.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.c   | 70 +++-
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |  8 +++
 src/mesa/drivers/dri/i965/intel_screen.c | 20 +++
 src/mesa/drivers/dri/i965/intel_screen.h |  1 +
 4 files changed, 98 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index f1675b191c1..ea7886d6df5 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -723,6 +723,74 @@ brw_bo_alloc_tiled_2d(struct brw_bufmgr *bufmgr, const 
char *name,
 flags, tiling, stride);
 }
 
+/*
+ * Wrap the chunk of client memory given by ptr+size inside a GPU
+ * buffer, and make it cache coherent (though on non-LLC architectures
+ * this requires snooping on explicit cache flushes). This allows the
+ * caller to write into the memory chunk and for those writes to be
+ * visible on the GPU (exactly as if they create the buffer and then
+ * persistently mapped it to obtain the pointer).
+ */
+struct brw_bo *
+brw_bo_alloc_userptr(struct brw_bufmgr *bufmgr,
+ const char *name, void *ptr, uint64_t size)
+{
+   struct brw_bo *bo = calloc(1, sizeof(*bo));
+   if (!bo)
+  return NULL;
+
+   bo->bufmgr = bufmgr;
+   bo->name = name;
+   p_atomic_set(>refcount, 1);
+
+   bo->size = size;
+   bo->map_cpu = ptr;
+   bo->userptr = true;
+   bo->reusable = false;
+   bo->cache_coherent = true;
+   bo->idle = true;
+   bo->kflags = bufmgr->initial_kflags;
+
+   bo->tiling_mode = I915_TILING_NONE;
+   bo->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
+   bo->stride = 0;
+
+   struct drm_i915_gem_userptr arg = {
+  .user_ptr = (uintptr_t)ptr,
+  .user_size = size,
+  .flags = 0,
+   };
+   if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_USERPTR, )) {
+  free(bo);
+  return NULL;
+   }
+
+   bo->gem_handle = arg.handle;
+
+   /* Check the buffer for validity before we try and use it in a batch */
+   struct drm_i915_gem_set_domain sd = {
+  .handle = bo->gem_handle,
+  .read_domains = I915_GEM_DOMAIN_CPU,
+   };
+   if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, ))
+  goto err_free;
+
+   if (brw_using_softpin(bufmgr)) {
+  bo->gtt_offset = vma_alloc(bufmgr, BRW_MEMZONE_OTHER, size, 1);
+  if (bo->gtt_offset == 0ull)
+ goto err_free;
+   }
+
+   VG_DEFINED(ptr, size); /* Presume we write to it using the GPU */
+   return bo;
+
+err_free:
+   mtx_lock(>lock);
+   bo_free(bo);
+   mtx_unlock(>lock);
+   return NULL;
+}
+
 /**
  * Returns a brw_bo wrapping the given buffer object handle.
  *
@@ -813,7 +881,7 @@ bo_free(struct brw_bo *bo)
 {
struct brw_bufmgr *bufmgr = bo->bufmgr;
 
-   if (bo->map_cpu) {
+   if (bo->map_cpu && !bo->userptr) {
   VG_NOACCESS(bo->map_cpu, bo->size);
   drm_munmap(bo->map_cpu, bo->size);
}
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 32fc7a553c9..ba9cf67b2ec 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -193,6 +193,11 @@ struct brw_bo {
 * Boolean of whether this buffer is cache coherent
 */
bool cache_coherent;
+
+   /**
+* Boolean of whether this buffer is a userptr
+*/
+   bool userptr:1;
 };
 
 #define BO_ALLOC_BUSY   (1<<0)
@@ -227,6 +232,9 @@ struct brw_bo *brw_bo_alloc_tiled(struct brw_bufmgr *bufmgr,
   uint32_t pitch,
   unsigned flags);
 
+struct brw_bo *brw_bo_alloc_userptr(struct brw_bufmgr *bufmgr,
+const char *name, void *ptr, uint64_t 
size);
+
 /**
  * Allocate a tiled buffer object.
  *
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index f1c195c5d14..1ba2f021fcd 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1889,6 +1889,22 @@ intel_detect_swizzling(struct intel_screen *screen)
return swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
 }
 
+static bool
+intel_detect_userptr(struct intel_screen *screen)
+{
+   struct drm_i915_gem_userptr arg = {
+  .user_ptr = -4096ULL,
+  .user_size = 8192, /* invalid 64b wrap around */
+   };
+
+   if (screen->devinfo.has_snoop_bug)
+  return false;
+
+  

[Mesa-dev] [PATCH 1/4] intel: Mark i965g/i965gm as having buggy snoop access

[Chris Wilson]

Recent kernels do exclude snoop access for i965g/i965gm as it does not
work as advertised. However to avoid depending on a recent kernel for
old hardware, mark the presence of the bug in gen_device_info.

See kernel commit df0700e53047662c167836bd6fdeea55d5d8dcfa
Author: Chris Wilson 
Date:   Wed Sep 6 20:24:24 2017 +0100

drm/i915: Disable snooping (userptr, set-cache-level) on gen4
---
 src/intel/dev/gen_device_info.c | 1 +
 src/intel/dev/gen_device_info.h | 8 
 2 files changed, 9 insertions(+)

diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index b0ae4d18034..d0449a49389 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -93,6 +93,7 @@ gen_get_pci_device_id_override(void)
 
 static const struct gen_device_info gen_device_info_i965 = {
.gen = 4,
+   .has_snoop_bug = true,
.has_negative_rhw_bug = true,
.num_slices = 1,
.num_subslices = { 1, },
diff --git a/src/intel/dev/gen_device_info.h b/src/intel/dev/gen_device_info.h
index 291a3cce8f8..80da9f713fa 100644
--- a/src/intel/dev/gen_device_info.h
+++ b/src/intel/dev/gen_device_info.h
@@ -80,6 +80,14 @@ struct gen_device_info
 */
bool has_negative_rhw_bug;
 
+   /**
+* Some specific Intel chipset do not invalidate the CPU cache from the
+* GPU for a snooped address, leading to stale data being read by the CPU
+* and incorrect results. Enabling this flag will prevent the driver from
+* using snooped access, e.g. userptr.
+*/
+   bool has_snoop_bug;
+
/**
 * Some versions of Gen hardware don't do centroid interpolation correctly
 * on unlit pixels, causing incorrect values for derivatives near triangle
-- 
2.18.0

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[Mesa-dev] [PATCH 3/4] i965: Expose AMD_pinned_memory

[Chris Wilson]

All GEN GPU can bind to any piece of memory (thanks UMA), and so through
a special ioctl we can map a chunk of page-aligned client memory into
the GPU address space. However, not all GEN are equal. Some have
cache-coherency between the CPU and the GPU, whilst the others are
incoherent and rely on snooping on explicit flushes to push/pull dirty
data. Whereas we can use client buffers as a general replacement for kernel
allocated buffers with LLC (cache coherency), using snooped buffers
behaves differently and so must be used with care.

AMD_pinned_memory supposes that the client memory buffer is suitable
for any general usage (e.g. vertex data, texture data) and so only on
LLC can we offer that extension.
---
 .../drivers/dri/i965/intel_buffer_objects.c   | 68 +--
 .../drivers/dri/i965/intel_buffer_objects.h   |  6 ++
 src/mesa/drivers/dri/i965/intel_extensions.c  | 11 +++
 3 files changed, 65 insertions(+), 20 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c 
b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index 452e6d33c07..4b34b55793b 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -72,6 +72,23 @@ mark_buffer_invalid(struct intel_buffer_object *intel_obj)
intel_obj->valid_data_end = 0;
 }
 
+/** Allocates a new brw_bo to store the data for the buffer object. */
+static void
+mark_new_state(struct brw_context *brw,
+   struct intel_buffer_object *intel_obj)
+{
+   /* the buffer might be bound as a uniform buffer, need to update it
+*/
+   if (intel_obj->Base.UsageHistory & USAGE_UNIFORM_BUFFER)
+  brw->ctx.NewDriverState |= BRW_NEW_UNIFORM_BUFFER;
+   if (intel_obj->Base.UsageHistory & USAGE_SHADER_STORAGE_BUFFER)
+  brw->ctx.NewDriverState |= BRW_NEW_UNIFORM_BUFFER;
+   if (intel_obj->Base.UsageHistory & USAGE_TEXTURE_BUFFER)
+  brw->ctx.NewDriverState |= BRW_NEW_TEXTURE_BUFFER;
+   if (intel_obj->Base.UsageHistory & USAGE_ATOMIC_COUNTER_BUFFER)
+  brw->ctx.NewDriverState |= BRW_NEW_UNIFORM_BUFFER;
+}
+
 /** Allocates a new brw_bo to store the data for the buffer object. */
 static void
 alloc_buffer_object(struct brw_context *brw,
@@ -96,20 +113,28 @@ alloc_buffer_object(struct brw_context *brw,
*/
   size += 64 * 32; /* max read length of 64 256-bit units */
}
+
+   assert(!intel_obj->pinned);
intel_obj->buffer =
   brw_bo_alloc(brw->bufmgr, "bufferobj", size, BRW_MEMZONE_OTHER);
 
-   /* the buffer might be bound as a uniform buffer, need to update it
-*/
-   if (intel_obj->Base.UsageHistory & USAGE_UNIFORM_BUFFER)
-  brw->ctx.NewDriverState |= BRW_NEW_UNIFORM_BUFFER;
-   if (intel_obj->Base.UsageHistory & USAGE_SHADER_STORAGE_BUFFER)
-  brw->ctx.NewDriverState |= BRW_NEW_UNIFORM_BUFFER;
-   if (intel_obj->Base.UsageHistory & USAGE_TEXTURE_BUFFER)
-  brw->ctx.NewDriverState |= BRW_NEW_TEXTURE_BUFFER;
-   if (intel_obj->Base.UsageHistory & USAGE_ATOMIC_COUNTER_BUFFER)
-  brw->ctx.NewDriverState |= BRW_NEW_UNIFORM_BUFFER;
+   mark_new_state(brw, intel_obj);
+   mark_buffer_inactive(intel_obj);
+   mark_buffer_invalid(intel_obj);
+}
+
+static void
+alloc_userptr_object(struct brw_context *brw,
+ struct intel_buffer_object *intel_obj,
+ GLsizeiptrARB size,
+ const GLvoid *data)
+{
+   intel_obj->buffer =
+  brw_bo_alloc_userptr(brw->bufmgr, "bufferobj(userptr)",
+   (void *)data, size);
+   intel_obj->pinned = true;
 
+   mark_new_state(brw, intel_obj);
mark_buffer_inactive(intel_obj);
mark_buffer_invalid(intel_obj);
 }
@@ -119,6 +144,7 @@ release_buffer(struct intel_buffer_object *intel_obj)
 {
brw_bo_unreference(intel_obj->buffer);
intel_obj->buffer = NULL;
+   intel_obj->pinned = false;
 }
 
 /**
@@ -192,10 +218,6 @@ brw_buffer_data(struct gl_context *ctx,
struct brw_context *brw = brw_context(ctx);
struct intel_buffer_object *intel_obj = intel_buffer_object(obj);
 
-   /* Part of the ABI, but this function doesn't use it.
-*/
-   (void) target;
-
intel_obj->Base.Size = size;
intel_obj->Base.Usage = usage;
intel_obj->Base.StorageFlags = storageFlags;
@@ -207,12 +229,16 @@ brw_buffer_data(struct gl_context *ctx,
   release_buffer(intel_obj);
 
if (size != 0) {
-  alloc_buffer_object(brw, intel_obj);
+  if (target != GL_EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD)
+ alloc_buffer_object(brw, intel_obj);
+  else
+ alloc_userptr_object(brw, intel_obj, size, data);
   if (!intel_obj->buffer)
  return false;
 
   if (data != NULL) {
- brw_bo_subdata(intel_obj->buffer, 0, size, data);
+ if (target != GL_EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD)
+brw_bo_subdata(intel_obj->buffer, 0, size, data);
  mark_buffer_valid_data(intel_obj, 0, size);
   }
}
@@ -275,9 +301,10 @@ brw_buffer_subdata(struct gl_context *ctx,
 

[Mesa-dev] [PATCH 4/4] docs/relnotes: Add AMD_pinned_memory for i965

[Chris Wilson]

Technically only for Sandybridge and later core designs, but finally we
can claim support for allowing clients to create glBufferObjects from
their own memory.
---
 docs/relnotes/18.3.0.html | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
index ac2cc1e893b..4ab9fb44736 100644
--- a/docs/relnotes/18.3.0.html
+++ b/docs/relnotes/18.3.0.html
@@ -53,6 +53,7 @@ Note: some of the new features are only available with 
certain drivers.
 
 GL_AMD_framebuffer_multisample_advanced on radeonsi.
 GL_EXT_window_rectangles on radeonsi.
+GL_AMD_pinned_memory on i965
 
 
 Bug fixes
-- 
2.18.0

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Re: [Mesa-dev] [PATCH 07/13] st/va: get mjpeg slice header

[Boyuan Zhang]

On 2018-08-16 01:26 PM, Leo Liu wrote:



On 08/16/2018 12:06 PM, boyuan.zh...@amd.com wrote:

From: Boyuan Zhang 

Move the previous get_mjpeg_slice_header function from radeon/vcn to 
st/va.


Signed-off-by: Boyuan Zhang 
---
  src/gallium/state_trackers/va/picture.c   |   3 +
  src/gallium/state_trackers/va/picture_mjpeg.c | 132 
++

  src/gallium/state_trackers/va/va_private.h    |   3 +
  3 files changed, 138 insertions(+)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c

index f2e9ba8..d326ed4 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -293,6 +293,9 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)

    sizes[num_buffers++] = context->mpeg4.start_code_size;
    break;
 case PIPE_VIDEO_FORMAT_JPEG:
+  vlVaGetJpegSliceHeader(context);
+  buffers[num_buffers] = (void *)context->mjpeg.slice_header;
+  sizes[num_buffers++] = context->mjpeg.slice_header_size;
    break;
 default:
    break;
diff --git a/src/gallium/state_trackers/va/picture_mjpeg.c 
b/src/gallium/state_trackers/va/picture_mjpeg.c

index 396b743..f1292ea 100644
--- a/src/gallium/state_trackers/va/picture_mjpeg.c
+++ b/src/gallium/state_trackers/va/picture_mjpeg.c
@@ -114,3 +114,135 @@ void 
vlVaHandleSliceParameterBufferMJPEG(vlVaContext *context, vlVaBuffer 
*buf)
 context->desc.mjpeg.slice_parameter.restart_interval = 
mjpeg->restart_interval;

 context->desc.mjpeg.slice_parameter.num_mcus = mjpeg->num_mcus;
  }
+
+void vlVaGetJpegSliceHeader(vlVaContext *context)
+{
+   int size = 0, saved_size, len_pos, i;
+   uint16_t *bs;
+   uint8_t *p = context->mjpeg.slice_header;
+
+   /* SOI */
+   p[size++] = 0xff;
+   p[size++] = 0xd8;
+
+   /* DQT */
+   p[size++] = 0xff;
+   p[size++] = 0xdb;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 4; ++i) {
+  if 
(context->desc.mjpeg.quantization_table.load_quantiser_table[i] == 0)

+ continue;
+
+  p[size++] = i;
+  memcpy((p + size), 
>desc.mjpeg.quantization_table.quantiser_table[i], 64);

+  size += 64;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - 4);
+
+   saved_size = size;
+
+   /* DHT */
+   p[size++] = 0xff;
+   p[size++] = 0xc4;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 2; ++i) {
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x00 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_dc_codes, 16);

+  size += 16;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].dc_values, 12);

+  size += 12;
+   }
+
+   for (i = 0; i < 2; ++i) {
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x10 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_ac_codes, 16);

+  size += 16;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].ac_values, 162);

+  size += 162;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - saved_size - 2);
+
+   saved_size = size;
+
+   /* DRI */
+   if (context->desc.mjpeg.slice_parameter.restart_interval) {
+  p[size++] = 0xff;
+  p[size++] = 0xdd;
+  p[size++] = 0x00;
+  p[size++] = 0x04;
+  bs = (uint16_t*)[size++];
+  *bs = 
util_bswap16(context->desc.mjpeg.slice_parameter.restart_interval);

+  saved_size = ++size;
+   }
+
+   /* SOF */
+   p[size++] = 0xff;
+   p[size++] = 0xc0;
+
+   len_pos = size++;
+   size++;
+
+   p[size++] = 0x08;
+
+   bs = (uint16_t*)[size++];
+   *bs = 
util_bswap16(context->desc.mjpeg.picture_parameter.picture_height);

+   size++;
+
+   bs = (uint16_t*)[size++];
+   *bs = 
util_bswap16(context->desc.mjpeg.picture_parameter.picture_width);

+   size++;
+
+   p[size++] = context->desc.mjpeg.picture_parameter.num_components;
+
+   for (i = 0; i < 
context->desc.mjpeg.picture_parameter.num_components; ++i) {
+  p[size++] = 
context->desc.mjpeg.picture_parameter.components[i].component_id;
+  p[size++] = 
context->desc.mjpeg.picture_parameter.components[i].h_sampling_factor 
<< 4 |

+ context->desc.mjpeg.picture_parameter.components[i].v_sampling_factor;
+  p[size++] = 
context->desc.mjpeg.picture_parameter.components[i].quantiser_table_selector;

+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - saved_size - 2);
+
+   saved_size = size;
+
+   /* SOS */
+   p[size++] = 0xff;
+   p[size++] = 0xda;
+
+   len_pos = size++;
+   size++;
+
+   p[size++] = context->desc.mjpeg.slice_parameter.num_components;
+
+   for (i = 0; i < 
context->desc.mjpeg.slice_parameter.num_components; ++i) {
+  p[size++] = 
context->desc.mjpeg.slice_parameter.components[i].component_selector;
+  p[size++] = 
context->desc.mjpeg.slice_parameter.components[i].dc_table_selector 
<< 4 |

+ 

Re: [Mesa-dev] [PATCH 06/13] radeon/vcn: add jpeg decode implementation

[Boyuan Zhang]

On 2018-08-16 01:19 PM, Leo Liu wrote:



On 08/16/2018 12:06 PM, boyuan.zh...@amd.com wrote:

From: Boyuan Zhang 

Add a new file to handle VCN Jpeg decode specific functions. Use Jpeg
specific cmd sending function in end_frame call.

Signed-off-by: Boyuan Zhang 
---
  src/gallium/drivers/radeon/Makefile.sources  |  1 +
  src/gallium/drivers/radeon/meson.build   |  1 +
  src/gallium/drivers/radeon/radeon_vcn_dec.c  | 32 ++--
  src/gallium/drivers/radeon/radeon_vcn_dec.h  |  4 +
  src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c | 99 


  5 files changed, 130 insertions(+), 7 deletions(-)
  create mode 100644 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources

index f8ee860..e3ee82c 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -10,6 +10,7 @@ C_SOURCES := \
  r600_texture.c \
  radeon_uvd.c \
  radeon_uvd.h \
+    radeon_vcn_dec_jpeg.c \
  radeon_vcn_dec.c \
  radeon_vcn_dec.h \
  radeon_vcn_enc_1_2.c \
diff --git a/src/gallium/drivers/radeon/meson.build 
b/src/gallium/drivers/radeon/meson.build

index 582a5ff..c984a75 100644
--- a/src/gallium/drivers/radeon/meson.build
+++ b/src/gallium/drivers/radeon/meson.build
@@ -33,6 +33,7 @@ files_libradeon = files(
    'radeon_vcn_enc_1_2.c',
    'radeon_vcn_enc.c',
    'radeon_vcn_enc.h',
+  'radeon_vcn_dec_jpeg.c',
    'radeon_vcn_dec.c',
    'radeon_vcn_dec.h',
    'radeon_uvd_enc_1_1.c',
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c

index 30a8952..861a40e 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -991,6 +991,10 @@ static unsigned calc_dpb_size(struct 
radeon_decoder *dec)

  dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
  break;
  +    case PIPE_VIDEO_FORMAT_JPEG:
+    dpb_size = 0;
+    break;
+
  default:
  // something is missing here
  assert(0);
@@ -1078,6 +1082,7 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,

    const unsigned *sizes)
  {
  struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
+    enum pipe_video_format format = 
u_reduce_video_profile(picture->profile);

  unsigned i;
    assert(decoder);
@@ -1089,6 +1094,9 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,

  struct rvid_buffer *buf = >bs_buffers[dec->cur_buffer];
  unsigned new_size = dec->bs_size + sizes[i];
  +    if (format == PIPE_VIDEO_FORMAT_JPEG)
+    new_size += 2; /* save for EOI */
+
  if (new_size > buf->res->buf->size) {
  dec->ws->buffer_unmap(buf->res->buf);
  if (!si_vid_resize_buffer(dec->screen, dec->cs, buf, 
new_size)) {
@@ -1108,6 +1116,13 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,

  dec->bs_size += sizes[i];
  dec->bs_ptr += sizes[i];
  }
+
+    if (format == PIPE_VIDEO_FORMAT_JPEG) {
+    ((uint8_t *)dec->bs_ptr)[0] = 0xff;    /* EOI */
+    ((uint8_t *)dec->bs_ptr)[1] = 0xd9;
+    dec->bs_size += 2;
+    dec->bs_ptr += 2;
+    }

Can this also be moved to ST?

With handleVASliceDataBufferType() after

buffers[num_buffers] = buf->data;
sizes[num_buffers] = buf->size;
++num_buffers;

by increasing the buffers size to 3.


Regards,
Leo


Agree! This part should be moved to ST as well.

Please see the new patches #6 #7 #8 with this changes.

Regards,
Boyuan






  }
    /**
@@ -1270,14 +1285,14 @@ struct pipe_video_codec 
*radeon_create_decoder(struct pipe_context *context,

  }
    dpb_size = calc_dpb_size(dec);
-
-    if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {

-    RVID_ERR("Can't allocated dpb.\n");
-    goto error;
+    if (dpb_size) {
+    if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {

+    RVID_ERR("Can't allocated dpb.\n");
+    goto error;
+    }
+    si_vid_clear_buffer(context, >dpb);
  }
  -    si_vid_clear_buffer(context, >dpb);
-
  if (dec->stream_type == RDECODE_CODEC_H264_PERF) {
  unsigned ctx_size = calc_ctx_size_h264_perf(dec);
  if (!si_vid_create_buffer(dec->screen, >ctx, ctx_size, 
PIPE_USAGE_DEFAULT)) {
@@ -1304,7 +1319,10 @@ struct pipe_video_codec 
*radeon_create_decoder(struct pipe_context *context,

    next_buffer(dec);
  -    dec->send_cmd = send_cmd_dec;
+    if (stream_type == RDECODE_CODEC_JPEG)
+    dec->send_cmd = send_cmd_jpeg;
+    else
+    dec->send_cmd = send_cmd_dec;
    return >base;
  diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h

index 05e4847..782eb65 100644
--- 

[Mesa-dev] [PATCH 06/13] radeon/vcn: add jpeg decode implementation

[boyuan.zhang]

From: Boyuan Zhang 

Add a new file to handle VCN Jpeg decode specific functions. Use Jpeg
specific cmd sending function in end_frame call.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/Makefile.sources  |  1 +
 src/gallium/drivers/radeon/meson.build   |  1 +
 src/gallium/drivers/radeon/radeon_vcn_dec.c  | 21 +++--
 src/gallium/drivers/radeon/radeon_vcn_dec.h  |  4 +
 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c | 99 
 5 files changed, 119 insertions(+), 7 deletions(-)
 create mode 100644 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index f8ee860..e3ee82c 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -10,6 +10,7 @@ C_SOURCES := \
r600_texture.c \
radeon_uvd.c \
radeon_uvd.h \
+   radeon_vcn_dec_jpeg.c \
radeon_vcn_dec.c \
radeon_vcn_dec.h \
radeon_vcn_enc_1_2.c \
diff --git a/src/gallium/drivers/radeon/meson.build 
b/src/gallium/drivers/radeon/meson.build
index 582a5ff..c984a75 100644
--- a/src/gallium/drivers/radeon/meson.build
+++ b/src/gallium/drivers/radeon/meson.build
@@ -33,6 +33,7 @@ files_libradeon = files(
   'radeon_vcn_enc_1_2.c',
   'radeon_vcn_enc.c',
   'radeon_vcn_enc.h',
+  'radeon_vcn_dec_jpeg.c',
   'radeon_vcn_dec.c',
   'radeon_vcn_dec.h',
   'radeon_uvd_enc_1_1.c',
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 30a8952..264abea 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -991,6 +991,10 @@ static unsigned calc_dpb_size(struct radeon_decoder *dec)
dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
break;
 
+   case PIPE_VIDEO_FORMAT_JPEG:
+   dpb_size = 0;
+   break;
+
default:
// something is missing here
assert(0);
@@ -1270,14 +1274,14 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
}
 
dpb_size = calc_dpb_size(dec);
-
-   if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {
-   RVID_ERR("Can't allocated dpb.\n");
-   goto error;
+   if (dpb_size) {
+   if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {
+   RVID_ERR("Can't allocated dpb.\n");
+   goto error;
+   }
+   si_vid_clear_buffer(context, >dpb);
}
 
-   si_vid_clear_buffer(context, >dpb);
-
if (dec->stream_type == RDECODE_CODEC_H264_PERF) {
unsigned ctx_size = calc_ctx_size_h264_perf(dec);
if (!si_vid_create_buffer(dec->screen, >ctx, ctx_size, 
PIPE_USAGE_DEFAULT)) {
@@ -1304,7 +1308,10 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
 
next_buffer(dec);
 
-   dec->send_cmd = send_cmd_dec;
+   if (stream_type == RDECODE_CODEC_JPEG)
+   dec->send_cmd = send_cmd_jpeg;
+   else
+   dec->send_cmd = send_cmd_dec;
 
return >base;
 
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index 05e4847..782eb65 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -627,6 +627,10 @@ void send_cmd_dec(struct radeon_decoder *dec,
  struct pipe_video_buffer *target,
  struct pipe_picture_desc *picture);
 
+void send_cmd_jpeg(struct radeon_decoder *dec,
+ struct pipe_video_buffer *target,
+ struct pipe_picture_desc *picture);
+
 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templat);
 
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
new file mode 100644
index 000..c52ed36
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
@@ -0,0 +1,99 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all 

[Mesa-dev] [PATCH 08/13] radeon/uvd: remove get mjpeg slice header

[boyuan.zhang]

From: Boyuan Zhang 

Move the previous get_mjpeg_slice_heaeder function and eoi from
"radeon/vcn" to "st/va".

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_uvd.c | 147 
 1 file changed, 147 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd.c 
b/src/gallium/drivers/radeon/radeon_uvd.c
index 78ced17..bff48ad 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -965,139 +965,6 @@ static struct ruvd_mpeg4 get_mpeg4_msg(struct 
ruvd_decoder *dec,
return result;
 }
 
-static void get_mjpeg_slice_header(struct ruvd_decoder *dec, struct 
pipe_mjpeg_picture_desc *pic)
-{
-   int size = 0, saved_size, len_pos, i;
-   uint16_t *bs;
-   uint8_t *buf = dec->bs_ptr;
-
-   /* SOI */
-   buf[size++] = 0xff;
-   buf[size++] = 0xd8;
-
-   /* DQT */
-   buf[size++] = 0xff;
-   buf[size++] = 0xdb;
-
-   len_pos = size++;
-   size++;
-
-   for (i = 0; i < 4; ++i) {
-   if (pic->quantization_table.load_quantiser_table[i] == 0)
-   continue;
-
-   buf[size++] = i;
-   memcpy((buf + size), 
>quantization_table.quantiser_table[i], 64);
-   size += 64;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - 4);
-
-   saved_size = size;
-
-   /* DHT */
-   buf[size++] = 0xff;
-   buf[size++] = 0xc4;
-
-   len_pos = size++;
-   size++;
-
-   for (i = 0; i < 2; ++i) {
-   if (pic->huffman_table.load_huffman_table[i] == 0)
-   continue;
-
-   buf[size++] = 0x00 | i;
-   memcpy((buf + size), >huffman_table.table[i].num_dc_codes, 
16);
-   size += 16;
-   memcpy((buf + size), >huffman_table.table[i].dc_values, 
12);
-   size += 12;
-   }
-
-   for (i = 0; i < 2; ++i) {
-   if (pic->huffman_table.load_huffman_table[i] == 0)
-   continue;
-
-   buf[size++] = 0x10 | i;
-   memcpy((buf + size), >huffman_table.table[i].num_ac_codes, 
16);
-   size += 16;
-   memcpy((buf + size), >huffman_table.table[i].ac_values, 
162);
-   size += 162;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   saved_size = size;
-
-   /* DRI */
-   if (pic->slice_parameter.restart_interval) {
-   buf[size++] = 0xff;
-   buf[size++] = 0xdd;
-   buf[size++] = 0x00;
-   buf[size++] = 0x04;
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->slice_parameter.restart_interval);
-   saved_size = ++size;
-   }
-
-   /* SOF */
-   buf[size++] = 0xff;
-   buf[size++] = 0xc0;
-
-   len_pos = size++;
-   size++;
-
-   buf[size++] = 0x08;
-
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->picture_parameter.picture_height);
-   size++;
-
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->picture_parameter.picture_width);
-   size++;
-
-   buf[size++] = pic->picture_parameter.num_components;
-
-   for (i = 0; i < pic->picture_parameter.num_components; ++i) {
-   buf[size++] = pic->picture_parameter.components[i].component_id;
-   buf[size++] = 
pic->picture_parameter.components[i].h_sampling_factor << 4 |
-   pic->picture_parameter.components[i].v_sampling_factor;
-   buf[size++] = 
pic->picture_parameter.components[i].quantiser_table_selector;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   saved_size = size;
-
-   /* SOS */
-   buf[size++] = 0xff;
-   buf[size++] = 0xda;
-
-   len_pos = size++;
-   size++;
-
-   buf[size++] = pic->slice_parameter.num_components;
-
-   for (i = 0; i < pic->slice_parameter.num_components; ++i) {
-   buf[size++] = 
pic->slice_parameter.components[i].component_selector;
-   buf[size++] = 
pic->slice_parameter.components[i].dc_table_selector << 4 |
-   pic->slice_parameter.components[i].ac_table_selector;
-   }
-
-   buf[size++] = 0x00;
-   buf[size++] = 0x3f;
-   buf[size++] = 0x00;
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   dec->bs_ptr += size;
-   dec->bs_size += size;
-}
-
 /**
  * destroy this video decoder
  */
@@ -1176,7 +1043,6 @@ static void ruvd_decode_bitstream(struct pipe_video_codec 
*decoder,
  const unsigned *sizes)
 {
struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
-   enum pipe_video_format format = 
u_reduce_video_profile(picture->profile);
unsigned i;
 
assert(decoder);
@@ -1184,16 +1050,10 @@ 

[Mesa-dev] [PATCH 07/13] st/va: get mjpeg slice header

[boyuan.zhang]

From: Boyuan Zhang 

Move the previous get_mjpeg_slice_heaeder function and eoi from
"radeon/vcn" to "st/va".

Signed-off-by: Boyuan Zhang 
---
 src/gallium/state_trackers/va/picture.c   |  13 ++-
 src/gallium/state_trackers/va/picture_mjpeg.c | 132 ++
 src/gallium/state_trackers/va/va_private.h|  11 +++
 3 files changed, 154 insertions(+), 2 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index f2e9ba8..af136fb 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -251,11 +251,12 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
 {
enum pipe_video_format format;
unsigned num_buffers = 0;
-   void * const *buffers[2];
-   unsigned sizes[2];
+   void * const *buffers[3];
+   unsigned sizes[3];
static const uint8_t start_code_h264[] = { 0x00, 0x00, 0x01 };
static const uint8_t start_code_h265[] = { 0x00, 0x00, 0x01 };
static const uint8_t start_code_vc1[] = { 0x00, 0x00, 0x01, 0x0d };
+   static const uint8_t eoi_jpeg[] = { 0xff, 0xd9 };
 
format = u_reduce_video_profile(context->templat.profile);
switch (format) {
@@ -293,6 +294,9 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
   sizes[num_buffers++] = context->mpeg4.start_code_size;
   break;
case PIPE_VIDEO_FORMAT_JPEG:
+  vlVaGetJpegSliceHeader(context);
+  buffers[num_buffers] = (void *)context->mjpeg.slice_header;
+  sizes[num_buffers++] = context->mjpeg.slice_header_size;
   break;
default:
   break;
@@ -302,6 +306,11 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
sizes[num_buffers] = buf->size;
++num_buffers;
 
+   if (format == PIPE_VIDEO_FORMAT_JPEG) {
+  buffers[num_buffers] = (void *const)_jpeg;
+  sizes[num_buffers++] = sizeof(eoi_jpeg);
+   }
+
if (context->needs_begin_frame) {
   context->decoder->begin_frame(context->decoder, context->target,
  >desc.base);
diff --git a/src/gallium/state_trackers/va/picture_mjpeg.c 
b/src/gallium/state_trackers/va/picture_mjpeg.c
index 396b743..f1292ea 100644
--- a/src/gallium/state_trackers/va/picture_mjpeg.c
+++ b/src/gallium/state_trackers/va/picture_mjpeg.c
@@ -114,3 +114,135 @@ void vlVaHandleSliceParameterBufferMJPEG(vlVaContext 
*context, vlVaBuffer *buf)
context->desc.mjpeg.slice_parameter.restart_interval = 
mjpeg->restart_interval;
context->desc.mjpeg.slice_parameter.num_mcus = mjpeg->num_mcus;
 }
+
+void vlVaGetJpegSliceHeader(vlVaContext *context)
+{
+   int size = 0, saved_size, len_pos, i;
+   uint16_t *bs;
+   uint8_t *p = context->mjpeg.slice_header;
+
+   /* SOI */
+   p[size++] = 0xff;
+   p[size++] = 0xd8;
+
+   /* DQT */
+   p[size++] = 0xff;
+   p[size++] = 0xdb;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 4; ++i) {
+  if (context->desc.mjpeg.quantization_table.load_quantiser_table[i] == 0)
+ continue;
+
+  p[size++] = i;
+  memcpy((p + size), 
>desc.mjpeg.quantization_table.quantiser_table[i], 64);
+  size += 64;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - 4);
+
+   saved_size = size;
+
+   /* DHT */
+   p[size++] = 0xff;
+   p[size++] = 0xc4;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 2; ++i) {
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x00 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_dc_codes, 16);
+  size += 16;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].dc_values, 12);
+  size += 12;
+   }
+
+   for (i = 0; i < 2; ++i) {
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x10 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_ac_codes, 16);
+  size += 16;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].ac_values, 162);
+  size += 162;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - saved_size - 2);
+
+   saved_size = size;
+
+   /* DRI */
+   if (context->desc.mjpeg.slice_parameter.restart_interval) {
+  p[size++] = 0xff;
+  p[size++] = 0xdd;
+  p[size++] = 0x00;
+  p[size++] = 0x04;
+  bs = (uint16_t*)[size++];
+  *bs = util_bswap16(context->desc.mjpeg.slice_parameter.restart_interval);
+  saved_size = ++size;
+   }
+
+   /* SOF */
+   p[size++] = 0xff;
+   p[size++] = 0xc0;
+
+   len_pos = size++;
+   size++;
+
+   p[size++] = 0x08;
+
+   bs = (uint16_t*)[size++];
+   *bs = util_bswap16(context->desc.mjpeg.picture_parameter.picture_height);
+   size++;
+
+   bs = (uint16_t*)[size++];
+   *bs = util_bswap16(context->desc.mjpeg.picture_parameter.picture_width);
+   size++;
+
+   p[size++] = context->desc.mjpeg.picture_parameter.num_components;
+
+   for (i = 0; i < context->desc.mjpeg.picture_parameter.num_components; ++i) 

[Mesa-dev] [PATCH] intel/tools: new i965_disasm tool

[Sagar Ghuge]

Adds a new i965 instruction disassemble tool

Signed-off-by: Sagar Ghuge 
---
 src/intel/Makefile.tools.am   |  15 +++
 src/intel/tools/i965_disasm.c | 202 ++
 src/intel/tools/i965_disasm.h |  46 
 src/intel/tools/meson.build   |  11 ++
 4 files changed, 274 insertions(+)
 create mode 100644 src/intel/tools/i965_disasm.c
 create mode 100644 src/intel/tools/i965_disasm.h

diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am
index 00624084e6..36a3a70a28 100644
--- a/src/intel/Makefile.tools.am
+++ b/src/intel/Makefile.tools.am
@@ -22,6 +22,7 @@
 noinst_PROGRAMS += \
tools/aubinator \
tools/aubinator_error_decode \
+   tools/i965_disasm \
tools/error2aub
 
 
@@ -62,6 +63,20 @@ tools_aubinator_error_decode_CFLAGS = \
$(AM_CFLAGS) \
$(ZLIB_CFLAGS)
 
+tools_i965_disasm_SOURCES = \
+   tools/i965_disasm.c \
+   tools/i965_disasm.h
+
+tools_i965_disasm_LDADD = \
+   common/libintel_common.la \
+   compiler/libintel_compiler.la \
+   dev/libintel_dev.la \
+   $(top_builddir)/src/util/libmesautil.la \
+   $(PTHREAD_LIBS)
+
+tools_i965_disasm_CFLAGS = \
+   $(AM_CFLAGS)
+
 
 tools_error2aub_SOURCES = \
tools/gen_context.h \
diff --git a/src/intel/tools/i965_disasm.c b/src/intel/tools/i965_disasm.c
new file mode 100644
index 00..c880559827
--- /dev/null
+++ b/src/intel/tools/i965_disasm.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+
+#include "compiler/brw_inst.h"
+#include "compiler/brw_eu.h"
+
+#include "i965_disasm.h"
+
+uint64_t INTEL_DEBUG;
+uint16_t pci_id = 0;
+FILE *outfile;
+
+struct i965_disasm {
+struct gen_device_info devinfo;
+};
+
+/* Return size of file in bytes pointed by fp */
+static size_t
+i965_disasm_get_file_size(FILE *fp)
+{
+   size_t size = 0;
+
+   fseek(fp, 0L, SEEK_END);
+   size = ftell(fp);
+   fseek(fp, 0L, SEEK_SET);
+
+   return size;
+}
+
+/* Return number of bytes read */
+static size_t
+i965_disasm_read_binary(FILE *fp, void **assembly)
+{
+   size_t end = i965_disasm_get_file_size(fp);
+   *assembly = malloc(end + 1);
+   fread(*assembly, end, 1, fp);
+   fclose(fp);
+
+   return end;
+}
+
+static void
+print_help(const char *progname, FILE *file)
+{
+   fprintf(file,
+   "Usage: %s [OPTION]...\n"
+   "Disassemble i965 instructions from binary file.\n\n"
+   "  --help display this help and exit\n"
+   "  --binary-path=PATH read binary file from binary file PATH\n"
+   "  --gen=platform disassemble instructions for given \n"
+   " platform (3 letter platform name)\n",
+   progname);
+}
+
+int main(int argc, char *argv[])
+{
+   FILE *fp = NULL;
+   void *assembly = NULL;
+   char *binary_path = NULL;
+   size_t start = 0, end = 0;
+   int c, i;
+   struct i965_disasm *disasm;
+
+   bool help = false;
+   const struct option i965_disasm_opts[] = {
+  { "help",  no_argument,   (int *) ,  true },
+  { "binary-path",   required_argument, NULL,   'b' },
+  { "gen",   required_argument, NULL,   'g'},
+  { NULL,0, NULL,   0 }
+   };
+
+   outfile = stderr;
+   i = 0;
+   while ((c = getopt_long(argc, argv, "", i965_disasm_opts, )) != -1) {
+  switch (c) {
+  case 'g': {
+ const int id = gen_device_name_to_pci_device_id(optarg);
+ if (id < 0) {
+fprintf(outfile, "can't parse gen: '%s', expected ivb, byt, hsw, "
+   "bdw, chv, skl, kbl or bxt\n", optarg);
+/* Clean up binary path if given pci id is wrong */
+if (binary_path) {
+   free(binary_path);
+   fclose(fp);

Re: [Mesa-dev] [PATCH] gallium/winsys/kms: don't unmap what wasn't mapped

[Lepton Wu]

On Thu, Aug 16, 2018 at 1:37 PM Ray Strode  wrote:
>
> From: Ray Strode 
>
> At the moment, depending on pipe transfer flags, the dumb
> buffer map address can end up at either kms_sw_dt->ro_mapped
> or kms_sw_dt->mapped.
>
> When it's time to unmap the dumb buffer, both locations get unmapped,
> even though one is probably initialized to 0.
>
> That leads to the code segment getting unmapped at runtime and
> crashes when trying to call into unrelated code.
>
> This commit addresses the problem by using MAP_FAILED instead of
> NULL for ro_mapped and mapped when the dumb buffer is unmapped,
> and only unmapping mapped addresses at unmap time.
Does https://patchwork.freedesktop.org/patch/238931/ already fix this?
What's the advantage to use MAP_FAILED instead of NULL?

>
> Signed-off-by: Ray Strode 
> ---
>  .../winsys/sw/kms-dri/kms_dri_sw_winsys.c | 19 ++-
>  1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c 
> b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
> index d842fe3257..effa3eb2c8 100644
> --- a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
> +++ b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
> @@ -149,63 +149,65 @@ static struct kms_sw_plane *get_plane(struct 
> kms_sw_displaytarget *kms_sw_dt,
> plane->width = width;
> plane->height = height;
> plane->stride = stride;
> plane->offset = offset;
> plane->dt = kms_sw_dt;
> list_add(>link, _sw_dt->planes);
> return plane;
>  }
>
>  static struct sw_displaytarget *
>  kms_sw_displaytarget_create(struct sw_winsys *ws,
>  unsigned tex_usage,
>  enum pipe_format format,
>  unsigned width, unsigned height,
>  unsigned alignment,
>  const void *front_private,
>  unsigned *stride)
>  {
> struct kms_sw_winsys *kms_sw = kms_sw_winsys(ws);
> struct kms_sw_displaytarget *kms_sw_dt;
> struct drm_mode_create_dumb create_req;
> struct drm_mode_destroy_dumb destroy_req;
> int ret;
>
> kms_sw_dt = CALLOC_STRUCT(kms_sw_displaytarget);
> if (!kms_sw_dt)
>goto no_dt;
>
> list_inithead(_sw_dt->planes);
> kms_sw_dt->ref_count = 1;
> +   kms_sw_dt->mapped = MAP_FAILED;
> +   kms_sw_dt->ro_mapped = MAP_FAILED;
>
> kms_sw_dt->format = format;
>
> memset(_req, 0, sizeof(create_req));
> create_req.bpp = 32;
> create_req.width = width;
> create_req.height = height;
> ret = drmIoctl(kms_sw->fd, DRM_IOCTL_MODE_CREATE_DUMB, _req);
> if (ret)
>goto free_bo;
>
> kms_sw_dt->size = create_req.size;
> kms_sw_dt->handle = create_req.handle;
> struct kms_sw_plane *plane = get_plane(kms_sw_dt, format, width, height,
>create_req.pitch, 0);
> if (!plane)
>goto free_bo;
>
> list_add(_sw_dt->link, _sw->bo_list);
>
> DEBUG_PRINT("KMS-DEBUG: created buffer %u (size %u)\n", 
> kms_sw_dt->handle, kms_sw_dt->size);
>
> *stride = create_req.pitch;
> return sw_displaytarget(plane);
>
>   free_bo:
> memset(_req, 0, sizeof destroy_req);
> destroy_req.handle = create_req.handle;
> drmIoctl(kms_sw->fd, DRM_IOCTL_MODE_DESTROY_DUMB, _req);
> FREE(kms_sw_dt);
>   no_dt:
> return NULL;
>  }
> @@ -235,61 +237,61 @@ kms_sw_displaytarget_destroy(struct sw_winsys *ws,
>
> DEBUG_PRINT("KMS-DEBUG: destroyed buffer %u\n", kms_sw_dt->handle);
>
> struct kms_sw_plane *tmp;
> LIST_FOR_EACH_ENTRY_SAFE(plane, tmp, _sw_dt->planes, link) {
>FREE(plane);
> }
>
> FREE(kms_sw_dt);
>  }
>
>  static void *
>  kms_sw_displaytarget_map(struct sw_winsys *ws,
>   struct sw_displaytarget *dt,
>   unsigned flags)
>  {
> struct kms_sw_winsys *kms_sw = kms_sw_winsys(ws);
> struct kms_sw_plane *plane = kms_sw_plane(dt);
> struct kms_sw_displaytarget *kms_sw_dt = plane->dt;
> struct drm_mode_map_dumb map_req;
> int prot, ret;
>
> memset(_req, 0, sizeof map_req);
> map_req.handle = kms_sw_dt->handle;
> ret = drmIoctl(kms_sw->fd, DRM_IOCTL_MODE_MAP_DUMB, _req);
> if (ret)
>return NULL;
>
> prot = (flags == PIPE_TRANSFER_READ) ? PROT_READ : (PROT_READ | 
> PROT_WRITE);
> void **ptr = (flags == PIPE_TRANSFER_READ) ? _sw_dt->ro_mapped : 
> _sw_dt->mapped;
> -   if (!*ptr) {
> +   if (*ptr == MAP_FAILED) {
>void *tmp = mmap(0, kms_sw_dt->size, prot, MAP_SHARED,
> kms_sw->fd, map_req.offset);
>if (tmp == MAP_FAILED)
>   return NULL;
>*ptr = tmp;
> }
>
> DEBUG_PRINT("KMS-DEBUG: mapped buffer %u (size %u) at %p\n",
>   kms_sw_dt->handle, kms_sw_dt->size, *ptr);
>
> kms_sw_dt->map_count++;
>
> return *ptr + plane->offset;
>  }
>
>  static struct kms_sw_displaytarget *
> 

Re: [Mesa-dev] [PATCH v2 3/5] configure: Enforce python 2.7.x

[Dylan Baker]

Quoting Emil Velikov (2018-08-16 09:19:06)
> On 16 August 2018 at 14:27, Emil Velikov  wrote:
> > On 15 August 2018 at 17:18, Dylan Baker  wrote:
> >> We don't want to support older versions of python 2 anymore, and we
> >> don't support python 3.x in autotools currently.
> >> ---
> >>  configure.ac | 7 +++
> >>  1 file changed, 7 insertions(+)
> >>
> >> diff --git a/configure.ac b/configure.ac
> >> index c2155a541b0..78672734d06 100644
> >> --- a/configure.ac
> >> +++ b/configure.ac
> >> @@ -162,6 +162,13 @@ if test -z "$PYTHON2"; then
> >>  AC_MSG_ERROR([Python not found - unable to generate sources])
> >>  fi
> >>  else
> >> +PYTHON_VERSION=`$PYTHON2 --version |& awk '{print $2}'`  dnl Yes, 
> >> python2 prints it's version to stderr
> >> +PYTHON_MAJOR=`echo $PYTHON_VERSION | cut -d . -f 1`
> >> +PYTHON_MINOR=`echo $PYTHON_VERSION | cut -d . -f 2`
> >> +if test $PYTHON_MAJOR -ne 2 -o $PYTHON_MINOR -ne 7; then
> >> +AC_MSG_ERROR([Python version 2.7.x not found - unable to generate 
> >> sources])
> >> +fi
> >> +
> > A slightly better alternative is to use AM_PATH_PYTHON as seen here [1]
> > Since there's no reason to keep autoconf python2 only, I've prepped a
> > small series [2].

I like your version much better (I secretly was hoping that you'd propose
something less gross than my lame attempt), so I'll drop the autotools patches
and just keep the scons and meson ones.

> >
> > Once everything is green I'll send it out. Until then, feel free to
> > drop this or reuse as much/little from my patch.
> >
> Jfyi, some of the tests not been ported to python2+3, as mentioned here [A].
> Would be great to check why they haven't flagged up in the meson CI.
> 

Because the python file itself is python 2/3 safe (I wrote or re-wrote that when
I did the initial meson port). The shell script invokes $PYTHON2 but that only
exists to make it easier for autotools, meson invokes the underlying python by
calling python3 foo.py.

Dylan


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[Mesa-dev] [PATCH] gallium/winsys/kms: don't unmap what wasn't mapped

[Ray Strode]

From: Ray Strode 

At the moment, depending on pipe transfer flags, the dumb
buffer map address can end up at either kms_sw_dt->ro_mapped
or kms_sw_dt->mapped.

When it's time to unmap the dumb buffer, both locations get unmapped,
even though one is probably initialized to 0.

That leads to the code segment getting unmapped at runtime and
crashes when trying to call into unrelated code.

This commit addresses the problem by using MAP_FAILED instead of
NULL for ro_mapped and mapped when the dumb buffer is unmapped,
and only unmapping mapped addresses at unmap time.

Signed-off-by: Ray Strode 
---
 .../winsys/sw/kms-dri/kms_dri_sw_winsys.c | 19 ++-
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c 
b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
index d842fe3257..effa3eb2c8 100644
--- a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
+++ b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
@@ -149,63 +149,65 @@ static struct kms_sw_plane *get_plane(struct 
kms_sw_displaytarget *kms_sw_dt,
plane->width = width;
plane->height = height;
plane->stride = stride;
plane->offset = offset;
plane->dt = kms_sw_dt;
list_add(>link, _sw_dt->planes);
return plane;
 }
 
 static struct sw_displaytarget *
 kms_sw_displaytarget_create(struct sw_winsys *ws,
 unsigned tex_usage,
 enum pipe_format format,
 unsigned width, unsigned height,
 unsigned alignment,
 const void *front_private,
 unsigned *stride)
 {
struct kms_sw_winsys *kms_sw = kms_sw_winsys(ws);
struct kms_sw_displaytarget *kms_sw_dt;
struct drm_mode_create_dumb create_req;
struct drm_mode_destroy_dumb destroy_req;
int ret;
 
kms_sw_dt = CALLOC_STRUCT(kms_sw_displaytarget);
if (!kms_sw_dt)
   goto no_dt;
 
list_inithead(_sw_dt->planes);
kms_sw_dt->ref_count = 1;
+   kms_sw_dt->mapped = MAP_FAILED;
+   kms_sw_dt->ro_mapped = MAP_FAILED;
 
kms_sw_dt->format = format;
 
memset(_req, 0, sizeof(create_req));
create_req.bpp = 32;
create_req.width = width;
create_req.height = height;
ret = drmIoctl(kms_sw->fd, DRM_IOCTL_MODE_CREATE_DUMB, _req);
if (ret)
   goto free_bo;
 
kms_sw_dt->size = create_req.size;
kms_sw_dt->handle = create_req.handle;
struct kms_sw_plane *plane = get_plane(kms_sw_dt, format, width, height,
   create_req.pitch, 0);
if (!plane)
   goto free_bo;
 
list_add(_sw_dt->link, _sw->bo_list);
 
DEBUG_PRINT("KMS-DEBUG: created buffer %u (size %u)\n", kms_sw_dt->handle, 
kms_sw_dt->size);
 
*stride = create_req.pitch;
return sw_displaytarget(plane);
 
  free_bo:
memset(_req, 0, sizeof destroy_req);
destroy_req.handle = create_req.handle;
drmIoctl(kms_sw->fd, DRM_IOCTL_MODE_DESTROY_DUMB, _req);
FREE(kms_sw_dt);
  no_dt:
return NULL;
 }
@@ -235,61 +237,61 @@ kms_sw_displaytarget_destroy(struct sw_winsys *ws,
 
DEBUG_PRINT("KMS-DEBUG: destroyed buffer %u\n", kms_sw_dt->handle);
 
struct kms_sw_plane *tmp;
LIST_FOR_EACH_ENTRY_SAFE(plane, tmp, _sw_dt->planes, link) {
   FREE(plane);
}
 
FREE(kms_sw_dt);
 }
 
 static void *
 kms_sw_displaytarget_map(struct sw_winsys *ws,
  struct sw_displaytarget *dt,
  unsigned flags)
 {
struct kms_sw_winsys *kms_sw = kms_sw_winsys(ws);
struct kms_sw_plane *plane = kms_sw_plane(dt);
struct kms_sw_displaytarget *kms_sw_dt = plane->dt;
struct drm_mode_map_dumb map_req;
int prot, ret;
 
memset(_req, 0, sizeof map_req);
map_req.handle = kms_sw_dt->handle;
ret = drmIoctl(kms_sw->fd, DRM_IOCTL_MODE_MAP_DUMB, _req);
if (ret)
   return NULL;
 
prot = (flags == PIPE_TRANSFER_READ) ? PROT_READ : (PROT_READ | PROT_WRITE);
void **ptr = (flags == PIPE_TRANSFER_READ) ? _sw_dt->ro_mapped : 
_sw_dt->mapped;
-   if (!*ptr) {
+   if (*ptr == MAP_FAILED) {
   void *tmp = mmap(0, kms_sw_dt->size, prot, MAP_SHARED,
kms_sw->fd, map_req.offset);
   if (tmp == MAP_FAILED)
  return NULL;
   *ptr = tmp;
}
 
DEBUG_PRINT("KMS-DEBUG: mapped buffer %u (size %u) at %p\n",
  kms_sw_dt->handle, kms_sw_dt->size, *ptr);
 
kms_sw_dt->map_count++;
 
return *ptr + plane->offset;
 }
 
 static struct kms_sw_displaytarget *
 kms_sw_displaytarget_find_and_ref(struct kms_sw_winsys *kms_sw,
   unsigned int kms_handle)
 {
struct kms_sw_displaytarget *kms_sw_dt;
 
LIST_FOR_EACH_ENTRY(kms_sw_dt, _sw->bo_list, link) {
   if (kms_sw_dt->handle == kms_handle) {
  kms_sw_dt->ref_count++;
 
  DEBUG_PRINT("KMS-DEBUG: imported buffer %u (size %u)\n",
  kms_sw_dt->handle, 

Re: [Mesa-dev] [PATCH 1/2] configure: use AM_PATH_PYTHON to look for the python version

[Dylan Baker]

Quoting Eric Engestrom (2018-08-16 09:52:05)
> On Thursday, 2018-08-16 17:18:56 +0100, Emil Velikov wrote:
> > From: Emil Velikov 
> > 
> > Currently we use AC_CHECK_PROGS looking for python2.7, python2 and
> > finally python. That is due to the varying names used across the
> > different OS.
> > 
> > Use the handy AM_PATH_PYTHON which finds the correct name and checks for
> > the version.
> > 
> > Note: python2.7 has been an unofficial requirement for quite some time.
> > Update the docs to reflect that.
> > 
> > Cc: Dylan Baker 
> > Signed-off-by: Emil Velikov 
> > ---
> >  configure.ac  | 7 +--
> >  docs/install.html | 2 +-
> >  2 files changed, 6 insertions(+), 3 deletions(-)
> > 
> > diff --git a/configure.ac b/configure.ac
> > index c2155a541b0..57fddb927ce 100644
> > --- a/configure.ac
> > +++ b/configure.ac
> > @@ -125,7 +125,10 @@ AC_PROG_GREP
> >  AC_PROG_NM
> >  AM_PROG_AS
> >  AX_CHECK_GNU_MAKE
> > -AC_CHECK_PROGS([PYTHON2], [python2.7 python2 python])
> > +AM_PATH_PYTHON([2.7],, [:])
> > +PYTHON2=$PYTHON
> > +AC_SUBST([PYTHON2])
> > +
> >  AC_PROG_SED
> >  AC_PROG_MKDIR_P
> >  
> > @@ -157,7 +160,7 @@ fi
> >  
> >  AX_CHECK_PYTHON_MAKO_MODULE($PYTHON_MAKO_REQUIRED)
> >  
> > -if test -z "$PYTHON2"; then
> > +if test "$PYTHON2" = ":"; then
> >  if test ! -f "$srcdir/src/util/format_srgb.c"; then
> >  AC_MSG_ERROR([Python not found - unable to generate sources])
> >  fi
> > diff --git a/docs/install.html b/docs/install.html
> > index 08081944cfc..f6094671cf9 100644
> > --- a/docs/install.html
> > +++ b/docs/install.html
> > @@ -72,7 +72,7 @@ you think you've spotted a bug let developers know by 
> > filing a
> >  
> >  
> >  https://www.python.org/;>Python - Python is required.
> > -Version 2.6.4 or later should work.
> > +Version 2.7 or later should work.

Is this just the autotools build, or is this for all builds? For meson 3.4+ is
required.

> >  
> >  http://www.makotemplates.org/;>Python Mako module -
> >  Python Mako module is required. Version 0.3.4 or later should work.
> Side note: I think this is also wrong  ^
> Should be 0.8.0 I believe.

Yes, it should be 0.8.0, good catch.

Dylan


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Re: [Mesa-dev] [PATCH 2/2] configure: use distutils in ax_check_python_mako_module

[Dylan Baker]

Quoting Emil Velikov (2018-08-16 09:18:57)
> From: Emil Velikov 
> 
> Handling the version comparison by hand is a bad idea. Python has a handy
> module distutils for that - use it.
> 
> Cc: Dylan Baker 
> Signed-off-by: Emil Velikov 
> ---
> Not entirely sure if Loose or Strict version should be used. Input
> highly appreciated.

I believe python uses sym-version for releases, which is what StrictVersion is
for. I'm not sure how they tag pre-release versions (or if we really care about
pre-release versions). You should be fine with LooseVersion,

Reviewed-by: Dylan Baker 

> ---
>  m4/ax_check_python_mako_module.m4 | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/m4/ax_check_python_mako_module.m4 
> b/m4/ax_check_python_mako_module.m4
> index 7d9bb511c09..1d293d821c3 100644
> --- a/m4/ax_check_python_mako_module.m4
> +++ b/m4/ax_check_python_mako_module.m4
> @@ -45,11 +45,12 @@ AC_DEFUN([AX_CHECK_PYTHON_MAKO_MODULE],
>  try:
>  import sys
>  import mako
> +import distutils.version
>  except ImportError as err:
>  sys.exit(err)
>  else:
> -ver_req = map(int, '$1'.split('.'))
> -ver_act = map(int, mako.__version__.split('.'))
> +ver_req = distutils.version.LooseVersion('$1')
> +ver_act = distutils.version.LooseVersion(mako.__version__)
>  sys.exit(int(ver_req > ver_act))
>  " | $PYTHON2 -
>  
> -- 
> 2.18.0
> 


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Re: [Mesa-dev] [PATCH mesa] intel: various python cleanups

[Dylan Baker]

Quoting Eric Engestrom (2018-08-16 07:43:23)
> Signed-off-by: Eric Engestrom 
> ---
> Didn't feel like sending 15 patches for these, but I can split out some
> of it if needed.
> ---
>  src/intel/genxml/gen_bits_header.py |  1 -
>  src/intel/genxml/gen_pack_header.py | 29 ++---
>  src/intel/genxml/gen_zipped_file.py |  1 -
>  src/intel/isl/gen_format_layout.py  |  9 -
>  src/intel/vulkan/anv_extensions.py  |  7 +++
>  5 files changed, 21 insertions(+), 26 deletions(-)
> 
> diff --git a/src/intel/genxml/gen_bits_header.py 
> b/src/intel/genxml/gen_bits_header.py
> index dcd6ccb7d9ec39109cb0..ded2d2dcfcfd74dbec1d 100644
> --- a/src/intel/genxml/gen_bits_header.py
> +++ b/src/intel/genxml/gen_bits_header.py
> @@ -25,7 +25,6 @@
>  
>  import argparse
>  import os
> -import sys
>  import xml.parsers.expat
>  
>  from mako.template import Template
> diff --git a/src/intel/genxml/gen_pack_header.py 
> b/src/intel/genxml/gen_pack_header.py
> index c3d712c7a86e1580ec0f..0bf838de8c60cd8744a6 100644
> --- a/src/intel/genxml/gen_pack_header.py
> +++ b/src/intel/genxml/gen_pack_header.py
> @@ -219,9 +219,9 @@ def safe_name(name):
>  def num_from_str(num_str):
>  if num_str.lower().startswith('0x'):
>  return int(num_str, base=16)
> -else:
> -assert not num_str.startswith('0'), 'octals numbers not allowed'
> -return int(num_str)
> +
> +assert not num_str.startswith('0'), 'octals numbers not allowed'
> +return int(num_str)
>  
>  class Field(object):
>  ufixed_pattern = re.compile(r"u(\d+)\.(\d+)")
> @@ -306,7 +306,7 @@ def emit_template_struct(self, dim):
>  print("   %-36s %s%s;" % (type, self.name, dim))
>  
>  prefix = ""
> -if len(self.values) > 0 and self.default == None:
> +if self.values and self.default == None:

Since you changed the other instances to be correct, 'self.default is None'.

With that change,
Reviewed-by: Dylan Baker 


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[Mesa-dev] [Bug 107563] [RADV] Broken rendering in Unity demos

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107563

--- Comment #8 from Alexander Tsoy  ---
(In reply to Samuel Pitoiset from comment #7)
> 1) RADV_DEBUG=nodcc fixes the rendering issue
Yes. Also your patch [1] fixes it.

> 2) RADV_DEBUG=nohiz seems to fix the VM faults
I confirm that.

[1] https://patchwork.freedesktop.org/patch/244950/

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Re: [Mesa-dev] [PATCH v2 9/9] meson: Build with Python 3

[Mathieu Bridon]

Hi Emil,

On Thu, 2018-08-16 at 17:11 +0100, Emil Velikov wrote:
> On 9 August 2018 at 09:27, Mathieu Bridon 
> wrote:
> > Now that all the build scripts are compatible with both Python 2
> > and 3, we can flip the switch and tell Meson to use the latter.
> > 
> > Since Meson already depends on Python 3 anyway, this means we don't
> > need two different Python stacks to build Mesa.
> 
> Just did a quick test of enabling python3 for the autoconf build and
> noticed that some parts are not converted to python2+3.
> Namely, invoking the following fail.
> glsl/tests/optimization-test.sh
> glsl/glcpp/tests/glcpp-test.sh
> 
> I'm concerned that this didn't flag as failure with meson

Those Bash scripts aren't used anywhere by the meson build.

However, the Python scripts that they run are:

* src/compiler/glsl/tests/optimization_test.py
* src/compiler/glsl/glcpp/tests/glcpp_test.py

Both are run directly (they are executables), and their shebang is
Python 2. :-/

They just aren't hooked up using prog_python like all the build
scripts, so I indeed completely missed them.

Are you already porting them over? Otherwise I'll try to have a look
ASAP.

Thanks,


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Re: [Mesa-dev] [PATCH] gallium/winsys/kms: do not munmap NULL pointers

[Lepton Wu]

Hi Jan,
On Thu, Aug 16, 2018 at 10:37 AM Emil Velikov  wrote:
>
> Hi Jan,
>
> On 13 July 2018 at 20:57, Jan Palus  wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107098
> > Signed-off-by: Jan Palus 
> > ---
Thanks for fixing this, actually after digging in some kernel code, it
seems my original assumation that
munmap(NULL...) should be noop is false.  So linux kernel will dry to
munmap for   address space between
NULL  and NULL + len,  if you happen to have a "low" mapping which
starts before len, then it will unmap
some process memory.
> Thanks for fixing this issue. For the future, feel free to use a fixes
> tag (+cc) as below.
> It provides a nice reference when picking the fix for stable branches,
> plus the author is your first line reviewer ;-)
>
> Fixes: d891f28df9a ("gallium/winsys/kms: Fix possible leak in map/unmap.")
> Cc: Lepton Wu 
>
> Reviewed-by: Emil Velikov 
>
> Just heading out of the office, so I'll push this tomorrow morning.
>
> -Emil
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Re: [Mesa-dev] [PATCH 1/9] util/dynarray: add a clone function

[Caio Marcelo de Oliveira Filho]

On Thu, Aug 16, 2018 at 07:29:40AM +0200, Thomas Helland wrote:
> 2018-08-15 23:56 GMT+02:00 Caio Marcelo de Oliveira Filho
> :
> > ---
> >  src/util/u_dynarray.h | 9 +
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/src/util/u_dynarray.h b/src/util/u_dynarray.h
> > index dcbbc06d161..4920fe04b67 100644
> > --- a/src/util/u_dynarray.h
> > +++ b/src/util/u_dynarray.h
> > @@ -102,6 +102,15 @@ util_dynarray_resize(struct util_dynarray *buf, 
> > unsigned newsize)
> > return p;
> >  }
> >
> > +static inline void
> > +util_dynarray_clone(struct util_dynarray *buf, struct util_dynarray 
> > *mem_ctx,
> 
> I think we should keep the mem_ctx a void *.
> Apart from that this patch is:
> 
> Reviewed-by: Thomas Helland 

Yeah, the intention was to keep it 'void *' :-)

Thanks!
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[Mesa-dev] [Bug 107594] [PATCH] fix crosscompilling with meson

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107594

Bug ID: 107594
   Summary: [PATCH] fix crosscompilling with meson
   Product: Mesa
   Version: git
  Hardware: All
OS: All
Status: NEW
  Severity: blocker
  Priority: medium
 Component: Other
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: s...@sss.chaoslab.ru
QA Contact: mesa-dev@lists.freedesktop.org

Created attachment 141146
  --> https://bugs.freedesktop.org/attachment.cgi?id=141146=edit
this patch fixes crosscompilling mesa with meson

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Re: [Mesa-dev] INTEL_map_texture on i915/i965

[Ian Romanick]

My recollection is that we never implemented this because it required
linear textures instead of tiled textures.  In every speed test we did,
the read performance of tiled textures was so much better than the read
performance of linear textures that it seemed unlikely to be a benefit.
Instead, we chose to spend time making our regular texture upload paths
more performant.

On 08/16/2018 06:23 AM, Phi Nguyen wrote:
> Hi,
> 
> I hope to use the zero-memory copy on the Iris Pro 6200 (Broadwell/Skylake).
> 
> The extension
> 
>  says
> only OpenGL 3.0 is required yet it does not show up on Ubuntu 18.04.  I
> saw a post from 2016
>  
> mentioning
> this feature, but that didn't get any replies.
> 
> Does an implementation of this even exist?  How would I go about getting it?
> 
> Thank you,
> Phi
> 
> 
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Re: [Mesa-dev] [PATCH 13/13] radeonsi: enable vcn jpeg decode for raven

[Leo Liu]

Reviewed-by: Leo Liu 


On 08/16/2018 12:06 PM, boyuan.zh...@amd.com wrote:

From: Boyuan Zhang 

Enable vcn jpeg decode for raven.

Signed-off-by: Boyuan Zhang 
---
  src/gallium/drivers/radeonsi/si_get.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index fc2be33..de587bb 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -640,6 +640,8 @@ static int si_get_video_param(struct pipe_screen *screen,
return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
return false;
case PIPE_VIDEO_FORMAT_JPEG:
+   if (sscreen->info.family == CHIP_RAVEN)
+   return true;
if (sscreen->info.family < CHIP_CARRIZO || 
sscreen->info.family >= CHIP_VEGA10)
return false;
if (!(sscreen->info.drm_major == 3 && 
sscreen->info.drm_minor >= 19)) {


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Re: [Mesa-dev] [PATCH 12/13] winsys/amdgpu: add vcn jpeg cs support

[Leo Liu]

On 08/16/2018 12:06 PM, boyuan.zh...@amd.com wrote:

From: Boyuan Zhang 

Add vcn jpeg cs support, align cs by no-op.

Signed-off-by: Boyuan Zhang 
---
  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 12 
  1 file changed, 12 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index a3feeb9..5092f49 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -840,6 +840,10 @@ static bool amdgpu_init_cs_context(struct 
amdgpu_cs_context *cs,
cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_ENC;
break;
  
+   case RING_VCN_JPEG:

+  cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_JPEG;
+  break;
+
 default:
 case RING_GFX:
cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_GFX;
@@ -1545,6 +1549,14 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
while (rcs->current.cdw & 15)
   radeon_emit(rcs, 0x8000); /* type2 nop packet */
break;
+   case RING_VCN_JPEG:
+  if (rcs->current.cdw % 2)
+ assert(0);
+  while (rcs->current.cdw & 15) {
+ radeon_emit(rcs, 0x6000); /* nop packet */
+ radeon_emit(rcs, 0x);
+  }
+  break;
 case RING_VCN_DEC:
while (rcs->current.cdw & 15)
   radeon_emit(rcs, 0x81ff); /* nop packet */

The patch is:
Reviewed-by: Leo Liu 

BTW, if you got chance, please fix the NOP for VCN DEC here in the same 
way. i.e 0x81ff and 0.


Regards,
Leo






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Re: [Mesa-dev] [PATCH] gallium/winsys/kms: do not munmap NULL pointers

[Emil Velikov]

Hi Jan,

On 13 July 2018 at 20:57, Jan Palus  wrote:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107098
> Signed-off-by: Jan Palus 
> ---
Thanks for fixing this issue. For the future, feel free to use a fixes
tag (+cc) as below.
It provides a nice reference when picking the fix for stable branches,
plus the author is your first line reviewer ;-)

Fixes: d891f28df9a ("gallium/winsys/kms: Fix possible leak in map/unmap.")
Cc: Lepton Wu 

Reviewed-by: Emil Velikov 

Just heading out of the office, so I'll push this tomorrow morning.

-Emil
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Re: [Mesa-dev] [PATCH 11/13] amd/common: add vcn jpeg ip info query

[Leo Liu]

Reviewed-by: Leo Liu 


On 08/16/2018 12:06 PM, boyuan.zh...@amd.com wrote:

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
  src/amd/common/ac_gpu_info.c | 14 --
  1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 73fc362..a1db3b9 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -99,7 +99,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
struct amdgpu_buffer_size_alignments alignment_info = {};
struct amdgpu_heap_info vram, vram_vis, gtt;
struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
-   struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
+   struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, 
vcn_jpeg = {};
struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
struct amdgpu_gds_resource_info gds = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature 
= 0;
@@ -199,6 +199,14 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
}
  
+	if (info->drm_major == 3 && info->drm_minor >= 17) {

+   r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, 
_jpeg);
+   if (r) {
+   fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) 
failed.\n");
+   return false;
+   }
+   }
+
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
>me_fw_version,
>me_fw_feature);
@@ -301,7 +309,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->max_se = amdinfo->num_shader_engines;
info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
info->has_hw_decode =
-   (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
+   (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
+   (vcn_jpeg.available_rings != 0);
info->uvd_fw_version =
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
@@ -368,6 +377,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
ib_align = MAX2(ib_align, vce.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
+   ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
 assert(ib_align);
info->ib_start_alignment = ib_align;
  


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Re: [Mesa-dev] [PATCH 10/13] radeon/vcn: implement jpeg target buffer cmd

[Leo Liu]

Patch 9-10:

Acked-by: Leo Liu 


On 08/16/2018 12:06 PM, boyuan.zh...@amd.com wrote:

From: Boyuan Zhang 

Implement jpeg target buffer cmd by programming registers directly,
since there is no firmware for VCN Jpeg decode.

Signed-off-by: Boyuan Zhang 
---
  src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c | 73 +++-
  1 file changed, 72 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
index d46581c..7ab4e67 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
@@ -116,7 +116,78 @@ static void send_cmd_target(struct radeon_decoder *dec,
 struct pb_buffer* buf, uint32_t off,
 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
  {
-   /* TODO */
+   uint64_t addr;
+
+   set_reg_jpeg(dec, mmUVD_JPEG_PITCH, COND0, TYPE0, (dec->jpg.dt_pitch >> 
4));
+   set_reg_jpeg(dec, mmUVD_JPEG_UV_PITCH, COND0, TYPE0, ((dec->jpg.dt_uv_pitch * 
2) >> 4));
+
+   set_reg_jpeg(dec, mmUVD_JPEG_TILING_CTRL, COND0, TYPE0, 0);
+   set_reg_jpeg(dec, mmUVD_JPEG_UV_TILING_CTRL, COND0, TYPE0, 0);
+
+   dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, RADEON_PRIO_UVD);
+   addr = dec->ws->buffer_get_virtual_address(buf);
+   addr = addr + off;
+
+   // set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer 
address
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0, (addr 
>> 32));
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0, 
addr);
+
+   // set output buffer data address
+   set_reg_jpeg(dec, mmUVD_JPEG_INDEX, COND0, TYPE0, 0);
+   set_reg_jpeg(dec, mmUVD_JPEG_DATA, COND0, TYPE0, 
dec->jpg.dt_luma_top_offset);
+   set_reg_jpeg(dec, mmUVD_JPEG_INDEX, COND0, TYPE0, 1);
+   set_reg_jpeg(dec, mmUVD_JPEG_DATA, COND0, TYPE0, 
dec->jpg.dt_chroma_top_offset);
+   set_reg_jpeg(dec, mmUVD_JPEG_TIER_CNTL2, COND0, TYPE3, 0);
+
+   // set output buffer read pointer
+   set_reg_jpeg(dec, mmUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0);
+
+   // enable error interrupts
+   set_reg_jpeg(dec, mmUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFE);
+
+   // start engine command
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0x6);
+
+   // wait for job completion, wait for job JBSI fetch done
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (dec->jpg.bsd_size >> 
2));
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C2);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x01400200);
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_RPTR, COND0, TYPE3, 0x);
+
+   // wait for job jpeg outbuf idle
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x);
+   set_reg_jpeg(dec, mmUVD_JPEG_OUTBUF_WPTR, COND0, TYPE3, 0x0001);
+
+   // stop engine
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0x4);
+
+   // asserting jpeg lmi drop
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x0005);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 23 | 1 << 0));
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE1, 0);
+
+   // asserting jpeg reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 1);
+
+   // ensure reset is asserted in sclk domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // de-assert jpeg reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0);
+
+   // ensure reset is de-asserted in sclk domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (0 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // de-asserting jpeg lmi drop
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x0005);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0);
  }
  
  /**


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Re: [Mesa-dev] [PATCH 08/13] radeon/uvd: remove get mjpeg slice header

[Leo Liu]

Reviewed-by: Leo Liu 


On 08/16/2018 12:06 PM, boyuan.zh...@amd.com wrote:

From: Boyuan Zhang 

Move the previous get_mjpeg_slice_header function from radeon/vcn to st/va.

Signed-off-by: Boyuan Zhang 
---
  src/gallium/drivers/radeon/radeon_uvd.c | 136 
  1 file changed, 136 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd.c 
b/src/gallium/drivers/radeon/radeon_uvd.c
index 78ced17..78575e7 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -965,139 +965,6 @@ static struct ruvd_mpeg4 get_mpeg4_msg(struct 
ruvd_decoder *dec,
return result;
  }
  
-static void get_mjpeg_slice_header(struct ruvd_decoder *dec, struct pipe_mjpeg_picture_desc *pic)

-{
-   int size = 0, saved_size, len_pos, i;
-   uint16_t *bs;
-   uint8_t *buf = dec->bs_ptr;
-
-   /* SOI */
-   buf[size++] = 0xff;
-   buf[size++] = 0xd8;
-
-   /* DQT */
-   buf[size++] = 0xff;
-   buf[size++] = 0xdb;
-
-   len_pos = size++;
-   size++;
-
-   for (i = 0; i < 4; ++i) {
-   if (pic->quantization_table.load_quantiser_table[i] == 0)
-   continue;
-
-   buf[size++] = i;
-   memcpy((buf + size), 
>quantization_table.quantiser_table[i], 64);
-   size += 64;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - 4);
-
-   saved_size = size;
-
-   /* DHT */
-   buf[size++] = 0xff;
-   buf[size++] = 0xc4;
-
-   len_pos = size++;
-   size++;
-
-   for (i = 0; i < 2; ++i) {
-   if (pic->huffman_table.load_huffman_table[i] == 0)
-   continue;
-
-   buf[size++] = 0x00 | i;
-   memcpy((buf + size), >huffman_table.table[i].num_dc_codes, 
16);
-   size += 16;
-   memcpy((buf + size), >huffman_table.table[i].dc_values, 
12);
-   size += 12;
-   }
-
-   for (i = 0; i < 2; ++i) {
-   if (pic->huffman_table.load_huffman_table[i] == 0)
-   continue;
-
-   buf[size++] = 0x10 | i;
-   memcpy((buf + size), >huffman_table.table[i].num_ac_codes, 
16);
-   size += 16;
-   memcpy((buf + size), >huffman_table.table[i].ac_values, 
162);
-   size += 162;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   saved_size = size;
-
-   /* DRI */
-   if (pic->slice_parameter.restart_interval) {
-   buf[size++] = 0xff;
-   buf[size++] = 0xdd;
-   buf[size++] = 0x00;
-   buf[size++] = 0x04;
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->slice_parameter.restart_interval);
-   saved_size = ++size;
-   }
-
-   /* SOF */
-   buf[size++] = 0xff;
-   buf[size++] = 0xc0;
-
-   len_pos = size++;
-   size++;
-
-   buf[size++] = 0x08;
-
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->picture_parameter.picture_height);
-   size++;
-
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->picture_parameter.picture_width);
-   size++;
-
-   buf[size++] = pic->picture_parameter.num_components;
-
-   for (i = 0; i < pic->picture_parameter.num_components; ++i) {
-   buf[size++] = pic->picture_parameter.components[i].component_id;
-   buf[size++] = pic->picture_parameter.components[i].h_sampling_factor 
<< 4 |
-   pic->picture_parameter.components[i].v_sampling_factor;
-   buf[size++] = 
pic->picture_parameter.components[i].quantiser_table_selector;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   saved_size = size;
-
-   /* SOS */
-   buf[size++] = 0xff;
-   buf[size++] = 0xda;
-
-   len_pos = size++;
-   size++;
-
-   buf[size++] = pic->slice_parameter.num_components;
-
-   for (i = 0; i < pic->slice_parameter.num_components; ++i) {
-   buf[size++] = 
pic->slice_parameter.components[i].component_selector;
-   buf[size++] = pic->slice_parameter.components[i].dc_table_selector 
<< 4 |
-   pic->slice_parameter.components[i].ac_table_selector;
-   }
-
-   buf[size++] = 0x00;
-   buf[size++] = 0x3f;
-   buf[size++] = 0x00;
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   dec->bs_ptr += size;
-   dec->bs_size += size;
-}
-
  /**
   * destroy this video decoder
   */
@@ -1184,9 +1051,6 @@ static void ruvd_decode_bitstream(struct pipe_video_codec 
*decoder,
if (!dec->bs_ptr)
return;
  
-	if (format == PIPE_VIDEO_FORMAT_JPEG)

-   get_mjpeg_slice_header(dec, (struct 
pipe_mjpeg_picture_desc*)picture);
-
for (i = 0; i < 

Re: [Mesa-dev] [PATCH 07/13] st/va: get mjpeg slice header

[Leo Liu]

On 08/16/2018 12:06 PM, boyuan.zh...@amd.com wrote:

From: Boyuan Zhang 

Move the previous get_mjpeg_slice_header function from radeon/vcn to st/va.

Signed-off-by: Boyuan Zhang 
---
  src/gallium/state_trackers/va/picture.c   |   3 +
  src/gallium/state_trackers/va/picture_mjpeg.c | 132 ++
  src/gallium/state_trackers/va/va_private.h|   3 +
  3 files changed, 138 insertions(+)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index f2e9ba8..d326ed4 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -293,6 +293,9 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
sizes[num_buffers++] = context->mpeg4.start_code_size;
break;
 case PIPE_VIDEO_FORMAT_JPEG:
+  vlVaGetJpegSliceHeader(context);
+  buffers[num_buffers] = (void *)context->mjpeg.slice_header;
+  sizes[num_buffers++] = context->mjpeg.slice_header_size;
break;
 default:
break;
diff --git a/src/gallium/state_trackers/va/picture_mjpeg.c 
b/src/gallium/state_trackers/va/picture_mjpeg.c
index 396b743..f1292ea 100644
--- a/src/gallium/state_trackers/va/picture_mjpeg.c
+++ b/src/gallium/state_trackers/va/picture_mjpeg.c
@@ -114,3 +114,135 @@ void vlVaHandleSliceParameterBufferMJPEG(vlVaContext 
*context, vlVaBuffer *buf)
 context->desc.mjpeg.slice_parameter.restart_interval = 
mjpeg->restart_interval;
 context->desc.mjpeg.slice_parameter.num_mcus = mjpeg->num_mcus;
  }
+
+void vlVaGetJpegSliceHeader(vlVaContext *context)
+{
+   int size = 0, saved_size, len_pos, i;
+   uint16_t *bs;
+   uint8_t *p = context->mjpeg.slice_header;
+
+   /* SOI */
+   p[size++] = 0xff;
+   p[size++] = 0xd8;
+
+   /* DQT */
+   p[size++] = 0xff;
+   p[size++] = 0xdb;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 4; ++i) {
+  if (context->desc.mjpeg.quantization_table.load_quantiser_table[i] == 0)
+ continue;
+
+  p[size++] = i;
+  memcpy((p + size), 
>desc.mjpeg.quantization_table.quantiser_table[i], 64);
+  size += 64;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - 4);
+
+   saved_size = size;
+
+   /* DHT */
+   p[size++] = 0xff;
+   p[size++] = 0xc4;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 2; ++i) {
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x00 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_dc_codes, 16);
+  size += 16;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].dc_values, 12);
+  size += 12;
+   }
+
+   for (i = 0; i < 2; ++i) {
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x10 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_ac_codes, 16);
+  size += 16;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].ac_values, 162);
+  size += 162;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - saved_size - 2);
+
+   saved_size = size;
+
+   /* DRI */
+   if (context->desc.mjpeg.slice_parameter.restart_interval) {
+  p[size++] = 0xff;
+  p[size++] = 0xdd;
+  p[size++] = 0x00;
+  p[size++] = 0x04;
+  bs = (uint16_t*)[size++];
+  *bs = util_bswap16(context->desc.mjpeg.slice_parameter.restart_interval);
+  saved_size = ++size;
+   }
+
+   /* SOF */
+   p[size++] = 0xff;
+   p[size++] = 0xc0;
+
+   len_pos = size++;
+   size++;
+
+   p[size++] = 0x08;
+
+   bs = (uint16_t*)[size++];
+   *bs = util_bswap16(context->desc.mjpeg.picture_parameter.picture_height);
+   size++;
+
+   bs = (uint16_t*)[size++];
+   *bs = util_bswap16(context->desc.mjpeg.picture_parameter.picture_width);
+   size++;
+
+   p[size++] = context->desc.mjpeg.picture_parameter.num_components;
+
+   for (i = 0; i < context->desc.mjpeg.picture_parameter.num_components; ++i) {
+  p[size++] = 
context->desc.mjpeg.picture_parameter.components[i].component_id;
+  p[size++] = 
context->desc.mjpeg.picture_parameter.components[i].h_sampling_factor << 4 |
+ 
context->desc.mjpeg.picture_parameter.components[i].v_sampling_factor;
+  p[size++] = 
context->desc.mjpeg.picture_parameter.components[i].quantiser_table_selector;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - saved_size - 2);
+
+   saved_size = size;
+
+   /* SOS */
+   p[size++] = 0xff;
+   p[size++] = 0xda;
+
+   len_pos = size++;
+   size++;
+
+   p[size++] = context->desc.mjpeg.slice_parameter.num_components;
+
+   for (i = 0; i < context->desc.mjpeg.slice_parameter.num_components; ++i) {
+  p[size++] = 
context->desc.mjpeg.slice_parameter.components[i].component_selector;
+  p[size++] = 
context->desc.mjpeg.slice_parameter.components[i].dc_table_selector << 4 |
+ 
context->desc.mjpeg.slice_parameter.components[i].ac_table_selector;

Re: [Mesa-dev] [PATCH 06/13] radeon/vcn: add jpeg decode implementation

[Leo Liu]

On 08/16/2018 12:06 PM, boyuan.zh...@amd.com wrote:

From: Boyuan Zhang 

Add a new file to handle VCN Jpeg decode specific functions. Use Jpeg
specific cmd sending function in end_frame call.

Signed-off-by: Boyuan Zhang 
---
  src/gallium/drivers/radeon/Makefile.sources  |  1 +
  src/gallium/drivers/radeon/meson.build   |  1 +
  src/gallium/drivers/radeon/radeon_vcn_dec.c  | 32 ++--
  src/gallium/drivers/radeon/radeon_vcn_dec.h  |  4 +
  src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c | 99 
  5 files changed, 130 insertions(+), 7 deletions(-)
  create mode 100644 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index f8ee860..e3ee82c 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -10,6 +10,7 @@ C_SOURCES := \
r600_texture.c \
radeon_uvd.c \
radeon_uvd.h \
+   radeon_vcn_dec_jpeg.c \
radeon_vcn_dec.c \
radeon_vcn_dec.h \
radeon_vcn_enc_1_2.c \
diff --git a/src/gallium/drivers/radeon/meson.build 
b/src/gallium/drivers/radeon/meson.build
index 582a5ff..c984a75 100644
--- a/src/gallium/drivers/radeon/meson.build
+++ b/src/gallium/drivers/radeon/meson.build
@@ -33,6 +33,7 @@ files_libradeon = files(
'radeon_vcn_enc_1_2.c',
'radeon_vcn_enc.c',
'radeon_vcn_enc.h',
+  'radeon_vcn_dec_jpeg.c',
'radeon_vcn_dec.c',
'radeon_vcn_dec.h',
'radeon_uvd_enc_1_1.c',
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 30a8952..861a40e 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -991,6 +991,10 @@ static unsigned calc_dpb_size(struct radeon_decoder *dec)
dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
break;
  
+	case PIPE_VIDEO_FORMAT_JPEG:

+   dpb_size = 0;
+   break;
+
default:
// something is missing here
assert(0);
@@ -1078,6 +1082,7 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,
  const unsigned *sizes)
  {
struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
+   enum pipe_video_format format = 
u_reduce_video_profile(picture->profile);
unsigned i;
  
  	assert(decoder);

@@ -1089,6 +1094,9 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,
struct rvid_buffer *buf = >bs_buffers[dec->cur_buffer];
unsigned new_size = dec->bs_size + sizes[i];
  
+		if (format == PIPE_VIDEO_FORMAT_JPEG)

+   new_size += 2; /* save for EOI */
+
if (new_size > buf->res->buf->size) {
dec->ws->buffer_unmap(buf->res->buf);
if (!si_vid_resize_buffer(dec->screen, dec->cs, buf, 
new_size)) {
@@ -1108,6 +1116,13 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,
dec->bs_size += sizes[i];
dec->bs_ptr += sizes[i];
}
+
+   if (format == PIPE_VIDEO_FORMAT_JPEG) {
+   ((uint8_t *)dec->bs_ptr)[0] = 0xff;  /* EOI */
+   ((uint8_t *)dec->bs_ptr)[1] = 0xd9;
+   dec->bs_size += 2;
+   dec->bs_ptr += 2;
+   }

Can this also be moved to ST?

With handleVASliceDataBufferType() after

buffers[num_buffers] = buf->data;
sizes[num_buffers] = buf->size;
++num_buffers;

by increasing the buffers size to 3.


Regards,
Leo




  }
  
  /**

@@ -1270,14 +1285,14 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
}
  
  	dpb_size = calc_dpb_size(dec);

-
-   if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {
-   RVID_ERR("Can't allocated dpb.\n");
-   goto error;
+   if (dpb_size) {
+   if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {
+   RVID_ERR("Can't allocated dpb.\n");
+   goto error;
+   }
+   si_vid_clear_buffer(context, >dpb);
}
  
-	si_vid_clear_buffer(context, >dpb);

-
if (dec->stream_type == RDECODE_CODEC_H264_PERF) {
unsigned ctx_size = calc_ctx_size_h264_perf(dec);
if (!si_vid_create_buffer(dec->screen, >ctx, ctx_size, 
PIPE_USAGE_DEFAULT)) {
@@ -1304,7 +1319,10 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
  
  	next_buffer(dec);
  
-	dec->send_cmd = send_cmd_dec;

+   if (stream_type == RDECODE_CODEC_JPEG)
+   dec->send_cmd = send_cmd_jpeg;
+   else
+   dec->send_cmd = send_cmd_dec;
  
  	return >base;
  
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 

Re: [Mesa-dev] [PATCH 05/13] radeon/vcn: separate send cmd call from end frame

[Leo Liu]

Patch 1-5:

Reviewed-by: Leo Liu 


On 08/16/2018 12:06 PM, boyuan.zh...@amd.com wrote:

From: Boyuan Zhang 

Use function pointer for sending cmd in end_frame call. By doing this, we can
assign different cmd sending logics for Jpeg decode later.

Signed-off-by: Boyuan Zhang 
---
  src/gallium/drivers/radeon/radeon_vcn_dec.c | 30 -
  src/gallium/drivers/radeon/radeon_vcn_dec.h |  7 +++
  2 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index e6c1b67..30a8952 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -,24 +,17 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,
  }
  
  /**

- * end decoding of the current frame
+ * send cmd for vcn dec
   */
-static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
+void send_cmd_dec(struct radeon_decoder *dec,
   struct pipe_video_buffer *target,
   struct pipe_picture_desc *picture)
  {
-   struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
struct pb_buffer *dt;
struct rvid_buffer *msg_fb_it_buf, *bs_buf;
  
-	assert(decoder);

-
-   if (!dec->bs_ptr)
-   return;
-
msg_fb_it_buf = >msg_fb_it_buffers[dec->cur_buffer];
bs_buf = >bs_buffers[dec->cur_buffer];
-
memset(dec->bs_ptr, 0, align(dec->bs_size, 128) - dec->bs_size);
dec->ws->buffer_unmap(bs_buf->res->buf);
  
@@ -1152,6 +1145,23 @@ static void radeon_dec_end_frame(struct pipe_video_codec *decoder,

send_cmd(dec, RDECODE_CMD_IT_SCALING_TABLE_BUFFER, 
msg_fb_it_buf->res->buf,
 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, 
RADEON_DOMAIN_GTT);
set_reg(dec, RDECODE_ENGINE_CNTL, 1);
+}
+
+/**
+ * end decoding of the current frame
+ */
+static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
+  struct pipe_video_buffer *target,
+  struct pipe_picture_desc *picture)
+{
+   struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
+
+   assert(decoder);
+
+   if (!dec->bs_ptr)
+   return;
+
+   dec->send_cmd(dec, target, picture);
  
  	flush(dec, PIPE_FLUSH_ASYNC);

next_buffer(dec);
@@ -1294,6 +1304,8 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
  
  	next_buffer(dec);
  
+	dec->send_cmd = send_cmd_dec;

+
return >base;
  
  error:

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index 399d75c..05e4847 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -618,8 +618,15 @@ struct radeon_decoder {
void*render_pic_list[16];
  
  	struct jpeg_params		jpg;

+   void (*send_cmd)(struct radeon_decoder *dec,
+struct pipe_video_buffer *target,
+struct pipe_picture_desc *picture);
  };
  
+void send_cmd_dec(struct radeon_decoder *dec,

+ struct pipe_video_buffer *target,
+ struct pipe_picture_desc *picture);
+
  struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templat);
  


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[Mesa-dev] [PATCH] docs: update required mako version

[Emil Velikov]

From: Emil Velikov 

The requirement was bumped a while back, but we forgot to update the
docs.

Fixes: ed871af91c2 ("configure.ac: raise Mako required version to
0.8.0")
Cc: Eric Engestrom 
Signed-off-by: Emil Velikov 
---
 docs/install.html | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/install.html b/docs/install.html
index f6094671cf9..d3c53d174a3 100644
--- a/docs/install.html
+++ b/docs/install.html
@@ -75,7 +75,7 @@ you think you've spotted a bug let developers know by filing a
 Version 2.7 or later should work.
 
 http://www.makotemplates.org/;>Python Mako module -
-Python Mako module is required. Version 0.3.4 or later should work.
+Python Mako module is required. Version 0.8.0 or later should work.
 
 lex / yacc - for building the Mesa IR and GLSL compiler.
 
-- 
2.18.0

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[Mesa-dev] [PATCH] radv: do not use CP predication for DCC decompressions

[Samuel Pitoiset]

This fixes a regression with some Unity demos. Not sure
what the root cause of the problem is, especially because
the driver doesn't perform any fast color clears. So, it
shouldn't be needed to decompress DCC. RadeonSI says that
the decompression is relatively cheap if the surface has
been decompressed already.

One possible improvement is to two use predicates, one for
DCC and one for FCE that could be cleared when DCC, FMASK
or CMASK are performed by the driver. That might skip some
unnecessary decompression passes (not DCC though).

Fixes: ff7daadca1 ("radv: enable/disable predication for the DCC decompression 
pass")
CC: 18.2 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107563
Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_meta_fast_clear.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_fast_clear.c 
b/src/amd/vulkan/radv_meta_fast_clear.c
index f469a9ee8f..b4cc900028 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -628,7 +628,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer 
*cmd_buffer,
pipeline = 
cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline;
}
 
-   if (radv_image_has_dcc(image)) {
+   if (!decompress_dcc && radv_image_has_dcc(image)) {
old_predicating = cmd_buffer->state.predicating;
 
radv_emit_set_predication_state_from_image(cmd_buffer, image, 
true);
@@ -696,7 +696,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer 
*cmd_buffer,
_buffer->pool->alloc);
 
}
-   if (radv_image_has_dcc(image)) {
+   if (!decompress_dcc && radv_image_has_dcc(image)) {
cmd_buffer->state.predicating = old_predicating;
 
radv_emit_set_predication_state_from_image(cmd_buffer, image, 
false);
-- 
2.18.0

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Re: [Mesa-dev] INTEL_map_texture on i915/i965

[Phi Nguyen]

Cool.  Thanks Lionel!

Best,
Phi

On Thu, Aug 16, 2018 at 12:03 PM Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> Hey Phi,
>
> I can confirm this extension isn't implemented in Mesa.
> I don't why it wasn't.
>
> Talking briefly with Jason, it seems that mapping texture makes less sense
> on Skylake and above generations.
> There we maintain compressed version of the textures in memory to further
> reduce memory bandwidth.
> This would make the memory mapped mechanism more costly because we would
> need to decompress the texture when you want to access it (probably close
> to a ReadPixels in terms of performance).
>
> -
> Lionel
>
> On 16/08/18 14:23, Phi Nguyen wrote:
>
> Hi,
>
> I hope to use the zero-memory copy on the Iris Pro 6200
> (Broadwell/Skylake).
>
> The extension
> 
>  says
> only OpenGL 3.0 is required yet it does not show up on Ubuntu 18.04.  I saw
> a post from 2016
>  
> mentioning
> this feature, but that didn't get any replies.
>
> Does an implementation of this even exist?  How would I go about getting
> it?
>
> Thank you,
> Phi
>
>
> ___
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> listmesa-dev@lists.freedesktop.orghttps://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
>
>
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Re: [Mesa-dev] [PATCH 1/2] configure: use AM_PATH_PYTHON to look for the python version

[Eric Engestrom]

On Thursday, 2018-08-16 17:18:56 +0100, Emil Velikov wrote:
> From: Emil Velikov 
> 
> Currently we use AC_CHECK_PROGS looking for python2.7, python2 and
> finally python. That is due to the varying names used across the
> different OS.
> 
> Use the handy AM_PATH_PYTHON which finds the correct name and checks for
> the version.
> 
> Note: python2.7 has been an unofficial requirement for quite some time.
> Update the docs to reflect that.
> 
> Cc: Dylan Baker 
> Signed-off-by: Emil Velikov 
> ---
>  configure.ac  | 7 +--
>  docs/install.html | 2 +-
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/configure.ac b/configure.ac
> index c2155a541b0..57fddb927ce 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -125,7 +125,10 @@ AC_PROG_GREP
>  AC_PROG_NM
>  AM_PROG_AS
>  AX_CHECK_GNU_MAKE
> -AC_CHECK_PROGS([PYTHON2], [python2.7 python2 python])
> +AM_PATH_PYTHON([2.7],, [:])
> +PYTHON2=$PYTHON
> +AC_SUBST([PYTHON2])
> +
>  AC_PROG_SED
>  AC_PROG_MKDIR_P
>  
> @@ -157,7 +160,7 @@ fi
>  
>  AX_CHECK_PYTHON_MAKO_MODULE($PYTHON_MAKO_REQUIRED)
>  
> -if test -z "$PYTHON2"; then
> +if test "$PYTHON2" = ":"; then
>  if test ! -f "$srcdir/src/util/format_srgb.c"; then
>  AC_MSG_ERROR([Python not found - unable to generate sources])
>  fi
> diff --git a/docs/install.html b/docs/install.html
> index 08081944cfc..f6094671cf9 100644
> --- a/docs/install.html
> +++ b/docs/install.html
> @@ -72,7 +72,7 @@ you think you've spotted a bug let developers know by 
> filing a
>  
>  
>  https://www.python.org/;>Python - Python is required.
> -Version 2.6.4 or later should work.
> +Version 2.7 or later should work.
>  
>  http://www.makotemplates.org/;>Python Mako module -
>  Python Mako module is required. Version 0.3.4 or later should work.
Side note: I think this is also wrong  ^
Should be 0.8.0 I believe.
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Re: [Mesa-dev] [PATCH mesa] i965: drop duplicate assignments

[Caio Marcelo de Oliveira Filho]

On Thu, Aug 16, 2018 at 04:00:16PM +0100, Eric Engestrom wrote:
> These are all already assigned when declared, a few lines above.
> 
> Signed-off-by: Eric Engestrom 
> ---
> Note: I'm not 100% certain the value can never change by the time this
> second assignment is done, so maybe it's the initial one that should be
> dropped?

It seems to me the initial ones should be dropped, since the value is
not used before the second assignment.


Thanks,
Caio
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[Mesa-dev] [Bug 107098] Segfault after munmap(kms_sw_dt->ro_mapped)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107098

--- Comment #3 from Jan Palus  ---
Note that I ultimately went for "setting AccelMethod=none" since rxvt-unicode
lags pretty badly in VirtualBox with glamor.

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[Mesa-dev] [PATCH 1/2] configure: use AM_PATH_PYTHON to look for the python version

[Emil Velikov]

From: Emil Velikov 

Currently we use AC_CHECK_PROGS looking for python2.7, python2 and
finally python. That is due to the varying names used across the
different OS.

Use the handy AM_PATH_PYTHON which finds the correct name and checks for
the version.

Note: python2.7 has been an unofficial requirement for quite some time.
Update the docs to reflect that.

Cc: Dylan Baker 
Signed-off-by: Emil Velikov 
---
 configure.ac  | 7 +--
 docs/install.html | 2 +-
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/configure.ac b/configure.ac
index c2155a541b0..57fddb927ce 100644
--- a/configure.ac
+++ b/configure.ac
@@ -125,7 +125,10 @@ AC_PROG_GREP
 AC_PROG_NM
 AM_PROG_AS
 AX_CHECK_GNU_MAKE
-AC_CHECK_PROGS([PYTHON2], [python2.7 python2 python])
+AM_PATH_PYTHON([2.7],, [:])
+PYTHON2=$PYTHON
+AC_SUBST([PYTHON2])
+
 AC_PROG_SED
 AC_PROG_MKDIR_P
 
@@ -157,7 +160,7 @@ fi
 
 AX_CHECK_PYTHON_MAKO_MODULE($PYTHON_MAKO_REQUIRED)
 
-if test -z "$PYTHON2"; then
+if test "$PYTHON2" = ":"; then
 if test ! -f "$srcdir/src/util/format_srgb.c"; then
 AC_MSG_ERROR([Python not found - unable to generate sources])
 fi
diff --git a/docs/install.html b/docs/install.html
index 08081944cfc..f6094671cf9 100644
--- a/docs/install.html
+++ b/docs/install.html
@@ -72,7 +72,7 @@ you think you've spotted a bug let developers know by filing a
 
 
 https://www.python.org/;>Python - Python is required.
-Version 2.6.4 or later should work.
+Version 2.7 or later should work.
 
 http://www.makotemplates.org/;>Python Mako module -
 Python Mako module is required. Version 0.3.4 or later should work.
-- 
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[Mesa-dev] [PATCH 2/2] configure: use distutils in ax_check_python_mako_module

[Emil Velikov]

From: Emil Velikov 

Handling the version comparison by hand is a bad idea. Python has a handy
module distutils for that - use it.

Cc: Dylan Baker 
Signed-off-by: Emil Velikov 
---
Not entirely sure if Loose or Strict version should be used. Input
highly appreciated.
---
 m4/ax_check_python_mako_module.m4 | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/m4/ax_check_python_mako_module.m4 
b/m4/ax_check_python_mako_module.m4
index 7d9bb511c09..1d293d821c3 100644
--- a/m4/ax_check_python_mako_module.m4
+++ b/m4/ax_check_python_mako_module.m4
@@ -45,11 +45,12 @@ AC_DEFUN([AX_CHECK_PYTHON_MAKO_MODULE],
 try:
 import sys
 import mako
+import distutils.version
 except ImportError as err:
 sys.exit(err)
 else:
-ver_req = map(int, '$1'.split('.'))
-ver_act = map(int, mako.__version__.split('.'))
+ver_req = distutils.version.LooseVersion('$1')
+ver_act = distutils.version.LooseVersion(mako.__version__)
 sys.exit(int(ver_req > ver_act))
 " | $PYTHON2 -
 
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Re: [Mesa-dev] [PATCH v2 3/5] configure: Enforce python 2.7.x

[Emil Velikov]

On 16 August 2018 at 14:27, Emil Velikov  wrote:
> On 15 August 2018 at 17:18, Dylan Baker  wrote:
>> We don't want to support older versions of python 2 anymore, and we
>> don't support python 3.x in autotools currently.
>> ---
>>  configure.ac | 7 +++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/configure.ac b/configure.ac
>> index c2155a541b0..78672734d06 100644
>> --- a/configure.ac
>> +++ b/configure.ac
>> @@ -162,6 +162,13 @@ if test -z "$PYTHON2"; then
>>  AC_MSG_ERROR([Python not found - unable to generate sources])
>>  fi
>>  else
>> +PYTHON_VERSION=`$PYTHON2 --version |& awk '{print $2}'`  dnl Yes, 
>> python2 prints it's version to stderr
>> +PYTHON_MAJOR=`echo $PYTHON_VERSION | cut -d . -f 1`
>> +PYTHON_MINOR=`echo $PYTHON_VERSION | cut -d . -f 2`
>> +if test $PYTHON_MAJOR -ne 2 -o $PYTHON_MINOR -ne 7; then
>> +AC_MSG_ERROR([Python version 2.7.x not found - unable to generate 
>> sources])
>> +fi
>> +
> A slightly better alternative is to use AM_PATH_PYTHON as seen here [1]
> Since there's no reason to keep autoconf python2 only, I've prepped a
> small series [2].
>
> Once everything is green I'll send it out. Until then, feel free to
> drop this or reuse as much/little from my patch.
>
Jfyi, some of the tests not been ported to python2+3, as mentioned here [A].
Would be great to check why they haven't flagged up in the meson CI.

I'll send the other patches in a moment.

Thanks
Emil

[A] https://lists.freedesktop.org/archives/mesa-dev/2018-August/202764.html
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Re: [Mesa-dev] [PATCH v2 9/9] meson: Build with Python 3

[Emil Velikov]

Hi Mathieu,

On 9 August 2018 at 09:27, Mathieu Bridon  wrote:
> Now that all the build scripts are compatible with both Python 2 and 3,
> we can flip the switch and tell Meson to use the latter.
>
> Since Meson already depends on Python 3 anyway, this means we don't need
> two different Python stacks to build Mesa.
>
Just did a quick test of enabling python3 for the autoconf build and
noticed that some parts are not converted to python2+3.
Namely, invoking the following fail.
glsl/tests/optimization-test.sh
glsl/glcpp/tests/glcpp-test.sh

I'm concerned that this didn't flag as failure with meson - the tests
should be wired and while python2 specifics like basestring are used.
If you want to have a go, you can checkout the following branch.

https://github.com/evelikov/Mesa/compare/autoconf-python3

Thanks
Emil
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[Mesa-dev] [PATCH 08/13] radeon/uvd: remove get mjpeg slice header

[boyuan.zhang]

From: Boyuan Zhang 

Move the previous get_mjpeg_slice_header function from radeon/vcn to st/va.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_uvd.c | 136 
 1 file changed, 136 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd.c 
b/src/gallium/drivers/radeon/radeon_uvd.c
index 78ced17..78575e7 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -965,139 +965,6 @@ static struct ruvd_mpeg4 get_mpeg4_msg(struct 
ruvd_decoder *dec,
return result;
 }
 
-static void get_mjpeg_slice_header(struct ruvd_decoder *dec, struct 
pipe_mjpeg_picture_desc *pic)
-{
-   int size = 0, saved_size, len_pos, i;
-   uint16_t *bs;
-   uint8_t *buf = dec->bs_ptr;
-
-   /* SOI */
-   buf[size++] = 0xff;
-   buf[size++] = 0xd8;
-
-   /* DQT */
-   buf[size++] = 0xff;
-   buf[size++] = 0xdb;
-
-   len_pos = size++;
-   size++;
-
-   for (i = 0; i < 4; ++i) {
-   if (pic->quantization_table.load_quantiser_table[i] == 0)
-   continue;
-
-   buf[size++] = i;
-   memcpy((buf + size), 
>quantization_table.quantiser_table[i], 64);
-   size += 64;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - 4);
-
-   saved_size = size;
-
-   /* DHT */
-   buf[size++] = 0xff;
-   buf[size++] = 0xc4;
-
-   len_pos = size++;
-   size++;
-
-   for (i = 0; i < 2; ++i) {
-   if (pic->huffman_table.load_huffman_table[i] == 0)
-   continue;
-
-   buf[size++] = 0x00 | i;
-   memcpy((buf + size), >huffman_table.table[i].num_dc_codes, 
16);
-   size += 16;
-   memcpy((buf + size), >huffman_table.table[i].dc_values, 
12);
-   size += 12;
-   }
-
-   for (i = 0; i < 2; ++i) {
-   if (pic->huffman_table.load_huffman_table[i] == 0)
-   continue;
-
-   buf[size++] = 0x10 | i;
-   memcpy((buf + size), >huffman_table.table[i].num_ac_codes, 
16);
-   size += 16;
-   memcpy((buf + size), >huffman_table.table[i].ac_values, 
162);
-   size += 162;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   saved_size = size;
-
-   /* DRI */
-   if (pic->slice_parameter.restart_interval) {
-   buf[size++] = 0xff;
-   buf[size++] = 0xdd;
-   buf[size++] = 0x00;
-   buf[size++] = 0x04;
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->slice_parameter.restart_interval);
-   saved_size = ++size;
-   }
-
-   /* SOF */
-   buf[size++] = 0xff;
-   buf[size++] = 0xc0;
-
-   len_pos = size++;
-   size++;
-
-   buf[size++] = 0x08;
-
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->picture_parameter.picture_height);
-   size++;
-
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->picture_parameter.picture_width);
-   size++;
-
-   buf[size++] = pic->picture_parameter.num_components;
-
-   for (i = 0; i < pic->picture_parameter.num_components; ++i) {
-   buf[size++] = pic->picture_parameter.components[i].component_id;
-   buf[size++] = 
pic->picture_parameter.components[i].h_sampling_factor << 4 |
-   pic->picture_parameter.components[i].v_sampling_factor;
-   buf[size++] = 
pic->picture_parameter.components[i].quantiser_table_selector;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   saved_size = size;
-
-   /* SOS */
-   buf[size++] = 0xff;
-   buf[size++] = 0xda;
-
-   len_pos = size++;
-   size++;
-
-   buf[size++] = pic->slice_parameter.num_components;
-
-   for (i = 0; i < pic->slice_parameter.num_components; ++i) {
-   buf[size++] = 
pic->slice_parameter.components[i].component_selector;
-   buf[size++] = 
pic->slice_parameter.components[i].dc_table_selector << 4 |
-   pic->slice_parameter.components[i].ac_table_selector;
-   }
-
-   buf[size++] = 0x00;
-   buf[size++] = 0x3f;
-   buf[size++] = 0x00;
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   dec->bs_ptr += size;
-   dec->bs_size += size;
-}
-
 /**
  * destroy this video decoder
  */
@@ -1184,9 +1051,6 @@ static void ruvd_decode_bitstream(struct pipe_video_codec 
*decoder,
if (!dec->bs_ptr)
return;
 
-   if (format == PIPE_VIDEO_FORMAT_JPEG)
-   get_mjpeg_slice_header(dec, (struct 
pipe_mjpeg_picture_desc*)picture);
-
for (i = 0; i < num_buffers; ++i) {
struct rvid_buffer *buf = 

[Mesa-dev] [PATCH 06/13] radeon/vcn: add jpeg decode implementation

[boyuan.zhang]

From: Boyuan Zhang 

Add a new file to handle VCN Jpeg decode specific functions. Use Jpeg
specific cmd sending function in end_frame call.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/Makefile.sources  |  1 +
 src/gallium/drivers/radeon/meson.build   |  1 +
 src/gallium/drivers/radeon/radeon_vcn_dec.c  | 32 ++--
 src/gallium/drivers/radeon/radeon_vcn_dec.h  |  4 +
 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c | 99 
 5 files changed, 130 insertions(+), 7 deletions(-)
 create mode 100644 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index f8ee860..e3ee82c 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -10,6 +10,7 @@ C_SOURCES := \
r600_texture.c \
radeon_uvd.c \
radeon_uvd.h \
+   radeon_vcn_dec_jpeg.c \
radeon_vcn_dec.c \
radeon_vcn_dec.h \
radeon_vcn_enc_1_2.c \
diff --git a/src/gallium/drivers/radeon/meson.build 
b/src/gallium/drivers/radeon/meson.build
index 582a5ff..c984a75 100644
--- a/src/gallium/drivers/radeon/meson.build
+++ b/src/gallium/drivers/radeon/meson.build
@@ -33,6 +33,7 @@ files_libradeon = files(
   'radeon_vcn_enc_1_2.c',
   'radeon_vcn_enc.c',
   'radeon_vcn_enc.h',
+  'radeon_vcn_dec_jpeg.c',
   'radeon_vcn_dec.c',
   'radeon_vcn_dec.h',
   'radeon_uvd_enc_1_1.c',
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 30a8952..861a40e 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -991,6 +991,10 @@ static unsigned calc_dpb_size(struct radeon_decoder *dec)
dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
break;
 
+   case PIPE_VIDEO_FORMAT_JPEG:
+   dpb_size = 0;
+   break;
+
default:
// something is missing here
assert(0);
@@ -1078,6 +1082,7 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,
  const unsigned *sizes)
 {
struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
+   enum pipe_video_format format = 
u_reduce_video_profile(picture->profile);
unsigned i;
 
assert(decoder);
@@ -1089,6 +1094,9 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,
struct rvid_buffer *buf = >bs_buffers[dec->cur_buffer];
unsigned new_size = dec->bs_size + sizes[i];
 
+   if (format == PIPE_VIDEO_FORMAT_JPEG)
+   new_size += 2; /* save for EOI */
+
if (new_size > buf->res->buf->size) {
dec->ws->buffer_unmap(buf->res->buf);
if (!si_vid_resize_buffer(dec->screen, dec->cs, buf, 
new_size)) {
@@ -1108,6 +1116,13 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,
dec->bs_size += sizes[i];
dec->bs_ptr += sizes[i];
}
+
+   if (format == PIPE_VIDEO_FORMAT_JPEG) {
+   ((uint8_t *)dec->bs_ptr)[0] = 0xff; /* EOI */
+   ((uint8_t *)dec->bs_ptr)[1] = 0xd9;
+   dec->bs_size += 2;
+   dec->bs_ptr += 2;
+   }
 }
 
 /**
@@ -1270,14 +1285,14 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
}
 
dpb_size = calc_dpb_size(dec);
-
-   if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {
-   RVID_ERR("Can't allocated dpb.\n");
-   goto error;
+   if (dpb_size) {
+   if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {
+   RVID_ERR("Can't allocated dpb.\n");
+   goto error;
+   }
+   si_vid_clear_buffer(context, >dpb);
}
 
-   si_vid_clear_buffer(context, >dpb);
-
if (dec->stream_type == RDECODE_CODEC_H264_PERF) {
unsigned ctx_size = calc_ctx_size_h264_perf(dec);
if (!si_vid_create_buffer(dec->screen, >ctx, ctx_size, 
PIPE_USAGE_DEFAULT)) {
@@ -1304,7 +1319,10 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
 
next_buffer(dec);
 
-   dec->send_cmd = send_cmd_dec;
+   if (stream_type == RDECODE_CODEC_JPEG)
+   dec->send_cmd = send_cmd_jpeg;
+   else
+   dec->send_cmd = send_cmd_dec;
 
return >base;
 
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index 05e4847..782eb65 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -627,6 +627,10 @@ void send_cmd_dec(struct radeon_decoder *dec,
  struct 

[Mesa-dev] [PATCH 09/13] radeon/vcn: implement jpeg bitstream buffer cmd

[boyuan.zhang]

From: Boyuan Zhang 

Implement jpeg bitstream buffer cmd by programming registers directly,
since there is no firmware for VCN Jpeg decode.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c | 46 +++-
 1 file changed, 45 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
index c52ed36..d46581c 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
@@ -59,12 +59,56 @@ static struct pb_buffer 
*radeon_jpeg_get_decode_param(struct radeon_decoder *dec
return luma->resource.buf;
 }
 
+/* add a new set register command to the IB */
+static void set_reg_jpeg(struct radeon_decoder *dec, unsigned reg,
+unsigned cond, unsigned type, uint32_t val)
+{
+   radeon_emit(dec->cs, RDECODE_PKTJ(SOC15_REG_ADDR(reg), cond, type));
+   radeon_emit(dec->cs, val);
+}
+
 /* send a bitstream buffer command */
 static void send_cmd_bitstream(struct radeon_decoder *dec,
 struct pb_buffer* buf, uint32_t off,
 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
 {
-   /* TODO */
+   uint64_t addr;
+
+   // jpeg soft reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 1);
+
+   // ensuring the Reset is asserted in SCLK domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C2);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x01400200);
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // wait mem
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0);
+
+   // ensuring the Reset is de-asserted in SCLK domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (0 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, RADEON_PRIO_UVD);
+   addr = dec->ws->buffer_get_virtual_address(buf);
+   addr = addr + off;
+
+   // set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer 
address
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0, 
(addr >> 32));
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0, 
addr);
+
+   // set jpeg_rb_base
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_BASE, COND0, TYPE0, 0);
+
+   // set jpeg_rb_base
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFF0);
+
+   // set jpeg_rb_wptr
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_WPTR, COND0, TYPE0, (dec->jpg.bsd_size 
>> 2));
 }
 
 /* send a target buffer command */
-- 
2.7.4

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[Mesa-dev] [PATCH 13/13] radeonsi: enable vcn jpeg decode for raven

[boyuan.zhang]

From: Boyuan Zhang 

Enable vcn jpeg decode for raven.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeonsi/si_get.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index fc2be33..de587bb 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -640,6 +640,8 @@ static int si_get_video_param(struct pipe_screen *screen,
return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
return false;
case PIPE_VIDEO_FORMAT_JPEG:
+   if (sscreen->info.family == CHIP_RAVEN)
+   return true;
if (sscreen->info.family < CHIP_CARRIZO || 
sscreen->info.family >= CHIP_VEGA10)
return false;
if (!(sscreen->info.drm_major == 3 && 
sscreen->info.drm_minor >= 19)) {
-- 
2.7.4

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[Mesa-dev] [PATCH 10/13] radeon/vcn: implement jpeg target buffer cmd

[boyuan.zhang]

From: Boyuan Zhang 

Implement jpeg target buffer cmd by programming registers directly,
since there is no firmware for VCN Jpeg decode.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c | 73 +++-
 1 file changed, 72 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
index d46581c..7ab4e67 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
@@ -116,7 +116,78 @@ static void send_cmd_target(struct radeon_decoder *dec,
 struct pb_buffer* buf, uint32_t off,
 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
 {
-   /* TODO */
+   uint64_t addr;
+
+   set_reg_jpeg(dec, mmUVD_JPEG_PITCH, COND0, TYPE0, (dec->jpg.dt_pitch >> 
4));
+   set_reg_jpeg(dec, mmUVD_JPEG_UV_PITCH, COND0, TYPE0, 
((dec->jpg.dt_uv_pitch * 2) >> 4));
+
+   set_reg_jpeg(dec, mmUVD_JPEG_TILING_CTRL, COND0, TYPE0, 0);
+   set_reg_jpeg(dec, mmUVD_JPEG_UV_TILING_CTRL, COND0, TYPE0, 0);
+
+   dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, RADEON_PRIO_UVD);
+   addr = dec->ws->buffer_get_virtual_address(buf);
+   addr = addr + off;
+
+   // set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer 
address
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0, 
(addr >> 32));
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0, 
addr);
+
+   // set output buffer data address
+   set_reg_jpeg(dec, mmUVD_JPEG_INDEX, COND0, TYPE0, 0);
+   set_reg_jpeg(dec, mmUVD_JPEG_DATA, COND0, TYPE0, 
dec->jpg.dt_luma_top_offset);
+   set_reg_jpeg(dec, mmUVD_JPEG_INDEX, COND0, TYPE0, 1);
+   set_reg_jpeg(dec, mmUVD_JPEG_DATA, COND0, TYPE0, 
dec->jpg.dt_chroma_top_offset);
+   set_reg_jpeg(dec, mmUVD_JPEG_TIER_CNTL2, COND0, TYPE3, 0);
+
+   // set output buffer read pointer
+   set_reg_jpeg(dec, mmUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0);
+
+   // enable error interrupts
+   set_reg_jpeg(dec, mmUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFE);
+
+   // start engine command
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0x6);
+
+   // wait for job completion, wait for job JBSI fetch done
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (dec->jpg.bsd_size >> 
2));
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C2);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x01400200);
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_RPTR, COND0, TYPE3, 0x);
+
+   // wait for job jpeg outbuf idle
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x);
+   set_reg_jpeg(dec, mmUVD_JPEG_OUTBUF_WPTR, COND0, TYPE3, 0x0001);
+
+   // stop engine
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0x4);
+
+   // asserting jpeg lmi drop
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x0005);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 23 | 1 << 0));
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE1, 0);
+
+   // asserting jpeg reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 1);
+
+   // ensure reset is asserted in sclk domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // de-assert jpeg reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0);
+
+   // ensure reset is de-asserted in sclk domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (0 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // de-asserting jpeg lmi drop
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x0005);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0);
 }
 
 /**
-- 
2.7.4

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[Mesa-dev] [PATCH 12/13] winsys/amdgpu: add vcn jpeg cs support

[boyuan.zhang]

From: Boyuan Zhang 

Add vcn jpeg cs support, align cs by no-op.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index a3feeb9..5092f49 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -840,6 +840,10 @@ static bool amdgpu_init_cs_context(struct 
amdgpu_cs_context *cs,
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_ENC;
   break;
 
+   case RING_VCN_JPEG:
+  cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_JPEG;
+  break;
+
default:
case RING_GFX:
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_GFX;
@@ -1545,6 +1549,14 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
   while (rcs->current.cdw & 15)
  radeon_emit(rcs, 0x8000); /* type2 nop packet */
   break;
+   case RING_VCN_JPEG:
+  if (rcs->current.cdw % 2)
+ assert(0);
+  while (rcs->current.cdw & 15) {
+ radeon_emit(rcs, 0x6000); /* nop packet */
+ radeon_emit(rcs, 0x);
+  }
+  break;
case RING_VCN_DEC:
   while (rcs->current.cdw & 15)
  radeon_emit(rcs, 0x81ff); /* nop packet */
-- 
2.7.4

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[Mesa-dev] [PATCH 11/13] amd/common: add vcn jpeg ip info query

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/amd/common/ac_gpu_info.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 73fc362..a1db3b9 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -99,7 +99,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
struct amdgpu_buffer_size_alignments alignment_info = {};
struct amdgpu_heap_info vram, vram_vis, gtt;
struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
-   struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
+   struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, 
vcn_jpeg = {};
struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
struct amdgpu_gds_resource_info gds = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature 
= 0;
@@ -199,6 +199,14 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
}
 
+   if (info->drm_major == 3 && info->drm_minor >= 17) {
+   r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, 
_jpeg);
+   if (r) {
+   fprintf(stderr, "amdgpu: 
amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
+   return false;
+   }
+   }
+
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
>me_fw_version,
>me_fw_feature);
@@ -301,7 +309,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->max_se = amdinfo->num_shader_engines;
info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
info->has_hw_decode =
-   (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
+   (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
+   (vcn_jpeg.available_rings != 0);
info->uvd_fw_version =
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
@@ -368,6 +377,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
ib_align = MAX2(ib_align, vce.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
+   ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
assert(ib_align);
info->ib_start_alignment = ib_align;
 
-- 
2.7.4

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[Mesa-dev] [PATCH 07/13] st/va: get mjpeg slice header

[boyuan.zhang]

From: Boyuan Zhang 

Move the previous get_mjpeg_slice_header function from radeon/vcn to st/va.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/state_trackers/va/picture.c   |   3 +
 src/gallium/state_trackers/va/picture_mjpeg.c | 132 ++
 src/gallium/state_trackers/va/va_private.h|   3 +
 3 files changed, 138 insertions(+)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index f2e9ba8..d326ed4 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -293,6 +293,9 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
   sizes[num_buffers++] = context->mpeg4.start_code_size;
   break;
case PIPE_VIDEO_FORMAT_JPEG:
+  vlVaGetJpegSliceHeader(context);
+  buffers[num_buffers] = (void *)context->mjpeg.slice_header;
+  sizes[num_buffers++] = context->mjpeg.slice_header_size;
   break;
default:
   break;
diff --git a/src/gallium/state_trackers/va/picture_mjpeg.c 
b/src/gallium/state_trackers/va/picture_mjpeg.c
index 396b743..f1292ea 100644
--- a/src/gallium/state_trackers/va/picture_mjpeg.c
+++ b/src/gallium/state_trackers/va/picture_mjpeg.c
@@ -114,3 +114,135 @@ void vlVaHandleSliceParameterBufferMJPEG(vlVaContext 
*context, vlVaBuffer *buf)
context->desc.mjpeg.slice_parameter.restart_interval = 
mjpeg->restart_interval;
context->desc.mjpeg.slice_parameter.num_mcus = mjpeg->num_mcus;
 }
+
+void vlVaGetJpegSliceHeader(vlVaContext *context)
+{
+   int size = 0, saved_size, len_pos, i;
+   uint16_t *bs;
+   uint8_t *p = context->mjpeg.slice_header;
+
+   /* SOI */
+   p[size++] = 0xff;
+   p[size++] = 0xd8;
+
+   /* DQT */
+   p[size++] = 0xff;
+   p[size++] = 0xdb;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 4; ++i) {
+  if (context->desc.mjpeg.quantization_table.load_quantiser_table[i] == 0)
+ continue;
+
+  p[size++] = i;
+  memcpy((p + size), 
>desc.mjpeg.quantization_table.quantiser_table[i], 64);
+  size += 64;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - 4);
+
+   saved_size = size;
+
+   /* DHT */
+   p[size++] = 0xff;
+   p[size++] = 0xc4;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 2; ++i) {
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x00 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_dc_codes, 16);
+  size += 16;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].dc_values, 12);
+  size += 12;
+   }
+
+   for (i = 0; i < 2; ++i) {
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x10 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_ac_codes, 16);
+  size += 16;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].ac_values, 162);
+  size += 162;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - saved_size - 2);
+
+   saved_size = size;
+
+   /* DRI */
+   if (context->desc.mjpeg.slice_parameter.restart_interval) {
+  p[size++] = 0xff;
+  p[size++] = 0xdd;
+  p[size++] = 0x00;
+  p[size++] = 0x04;
+  bs = (uint16_t*)[size++];
+  *bs = util_bswap16(context->desc.mjpeg.slice_parameter.restart_interval);
+  saved_size = ++size;
+   }
+
+   /* SOF */
+   p[size++] = 0xff;
+   p[size++] = 0xc0;
+
+   len_pos = size++;
+   size++;
+
+   p[size++] = 0x08;
+
+   bs = (uint16_t*)[size++];
+   *bs = util_bswap16(context->desc.mjpeg.picture_parameter.picture_height);
+   size++;
+
+   bs = (uint16_t*)[size++];
+   *bs = util_bswap16(context->desc.mjpeg.picture_parameter.picture_width);
+   size++;
+
+   p[size++] = context->desc.mjpeg.picture_parameter.num_components;
+
+   for (i = 0; i < context->desc.mjpeg.picture_parameter.num_components; ++i) {
+  p[size++] = 
context->desc.mjpeg.picture_parameter.components[i].component_id;
+  p[size++] = 
context->desc.mjpeg.picture_parameter.components[i].h_sampling_factor << 4 |
+ 
context->desc.mjpeg.picture_parameter.components[i].v_sampling_factor;
+  p[size++] = 
context->desc.mjpeg.picture_parameter.components[i].quantiser_table_selector;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - saved_size - 2);
+
+   saved_size = size;
+
+   /* SOS */
+   p[size++] = 0xff;
+   p[size++] = 0xda;
+
+   len_pos = size++;
+   size++;
+
+   p[size++] = context->desc.mjpeg.slice_parameter.num_components;
+
+   for (i = 0; i < context->desc.mjpeg.slice_parameter.num_components; ++i) {
+  p[size++] = 
context->desc.mjpeg.slice_parameter.components[i].component_selector;
+  p[size++] = 
context->desc.mjpeg.slice_parameter.components[i].dc_table_selector << 4 |
+ 
context->desc.mjpeg.slice_parameter.components[i].ac_table_selector;
+   }
+
+   p[size++] = 0x00;
+   p[size++] = 0x3f;
+   p[size++] = 

[Mesa-dev] [PATCH 05/13] radeon/vcn: separate send cmd call from end frame

[boyuan.zhang]

From: Boyuan Zhang 

Use function pointer for sending cmd in end_frame call. By doing this, we can
assign different cmd sending logics for Jpeg decode later.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 30 -
 src/gallium/drivers/radeon/radeon_vcn_dec.h |  7 +++
 2 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index e6c1b67..30a8952 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -,24 +,17 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,
 }
 
 /**
- * end decoding of the current frame
+ * send cmd for vcn dec
  */
-static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
+void send_cmd_dec(struct radeon_decoder *dec,
   struct pipe_video_buffer *target,
   struct pipe_picture_desc *picture)
 {
-   struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
struct pb_buffer *dt;
struct rvid_buffer *msg_fb_it_buf, *bs_buf;
 
-   assert(decoder);
-
-   if (!dec->bs_ptr)
-   return;
-
msg_fb_it_buf = >msg_fb_it_buffers[dec->cur_buffer];
bs_buf = >bs_buffers[dec->cur_buffer];
-
memset(dec->bs_ptr, 0, align(dec->bs_size, 128) - dec->bs_size);
dec->ws->buffer_unmap(bs_buf->res->buf);
 
@@ -1152,6 +1145,23 @@ static void radeon_dec_end_frame(struct pipe_video_codec 
*decoder,
send_cmd(dec, RDECODE_CMD_IT_SCALING_TABLE_BUFFER, 
msg_fb_it_buf->res->buf,
 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, 
RADEON_DOMAIN_GTT);
set_reg(dec, RDECODE_ENGINE_CNTL, 1);
+}
+
+/**
+ * end decoding of the current frame
+ */
+static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
+  struct pipe_video_buffer *target,
+  struct pipe_picture_desc *picture)
+{
+   struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
+
+   assert(decoder);
+
+   if (!dec->bs_ptr)
+   return;
+
+   dec->send_cmd(dec, target, picture);
 
flush(dec, PIPE_FLUSH_ASYNC);
next_buffer(dec);
@@ -1294,6 +1304,8 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
 
next_buffer(dec);
 
+   dec->send_cmd = send_cmd_dec;
+
return >base;
 
 error:
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index 399d75c..05e4847 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -618,8 +618,15 @@ struct radeon_decoder {
void*render_pic_list[16];
 
struct jpeg_params  jpg;
+   void (*send_cmd)(struct radeon_decoder *dec,
+struct pipe_video_buffer *target,
+struct pipe_picture_desc *picture);
 };
 
+void send_cmd_dec(struct radeon_decoder *dec,
+ struct pipe_video_buffer *target,
+ struct pipe_picture_desc *picture);
+
 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templat);
 
-- 
2.7.4

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[Mesa-dev] [PATCH 04/13] radeon/vcn: create cs based on ring type

[boyuan.zhang]

From: Boyuan Zhang 

Add RING_VCN_JPEG for VCN Jpeg decode, and keep RING_VCN_DEC for other codecs.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 8bea704..e6c1b67 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1173,7 +1173,7 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
struct radeon_winsys* ws = ((struct r600_common_context *)context)->ws;
struct r600_common_context *rctx = (struct r600_common_context*)context;
unsigned width = templ->width, height = templ->height;
-   unsigned dpb_size, bs_buf_size, stream_type = 0;
+   unsigned dpb_size, bs_buf_size, stream_type = 0, ring = RING_VCN_DEC;
struct radeon_decoder *dec;
int r, i;
 
@@ -1199,6 +1199,10 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
case PIPE_VIDEO_FORMAT_HEVC:
stream_type = RDECODE_CODEC_H265;
break;
+   case PIPE_VIDEO_FORMAT_JPEG:
+   stream_type = RDECODE_CODEC_JPEG;
+   ring = RING_VCN_JPEG;
+   break;
default:
assert(0);
break;
@@ -1225,7 +1229,7 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
dec->stream_handle = si_vid_alloc_stream_handle();
dec->screen = context->screen;
dec->ws = ws;
-   dec->cs = ws->cs_create(rctx->ctx, RING_VCN_DEC, NULL, NULL);
+   dec->cs = ws->cs_create(rctx->ctx, ring, NULL, NULL);
if (!dec->cs) {
RVID_ERR("Can't get command submission context.\n");
goto error;
-- 
2.7.4

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[Mesa-dev] [PATCH 02/13] radeon/vcn: add vcn jpeg decode interface

[boyuan.zhang]

From: Boyuan Zhang 

Add VCN Jpeg decode interfaces and register defines.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.h | 91 +
 1 file changed, 91 insertions(+)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index 4a90687..399d75c 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -43,6 +43,15 @@
 
 #define RDECODE_PKT2() (RDECODE_PKT_TYPE_S(2))
 
+#define RDECODE_PKT_REG_J(x)   ((unsigned)(x) & 0x3)
+#define RDECODE_PKT_RES_J(x)   (((unsigned)(x) & 0x3F) << 18)
+#define RDECODE_PKT_COND_J(x)  (((unsigned)(x) & 0xF) << 24)
+#define RDECODE_PKT_TYPE_J(x)  (((unsigned)(x) & 0xF) << 28)
+#define RDECODE_PKTJ(reg, cond, type)  (RDECODE_PKT_REG_J(reg) | \
+   RDECODE_PKT_RES_J(0) | \
+   RDECODE_PKT_COND_J(cond) | \
+   RDECODE_PKT_TYPE_J(type))
+
 #define RDECODE_CMD_MSG_BUFFER 0x
 #define RDECODE_CMD_DPB_BUFFER 0x0001
 #define RDECODE_CMD_DECODING_TARGET_BUFFER 0x0002
@@ -61,6 +70,7 @@
 #define RDECODE_CODEC_MPEG2_VLD0x0003
 #define RDECODE_CODEC_MPEG40x0004
 #define RDECODE_CODEC_H264_PERF0x0007
+#define RDECODE_CODEC_JPEG 0x0008
 #define RDECODE_CODEC_H265 0x0010
 
 #define RDECODE_ARRAY_MODE_LINEAR  0x
@@ -107,6 +117,77 @@
 
 #define NUM_BUFFERS4
 
+#define mmUVD_JPEG_CNTL0x0200
+#define mmUVD_JPEG_CNTL_BASE_IDX   1
+#define mmUVD_JPEG_RB_BASE 0x0201
+#define mmUVD_JPEG_RB_BASE_BASE_IDX1
+#define mmUVD_JPEG_RB_WPTR 0x0202
+#define mmUVD_JPEG_RB_WPTR_BASE_IDX1
+#define mmUVD_JPEG_RB_RPTR 0x0203
+#define mmUVD_JPEG_RB_RPTR_BASE_IDX1
+#define mmUVD_JPEG_RB_SIZE 0x0204
+#define mmUVD_JPEG_RB_SIZE_BASE_IDX1
+#define mmUVD_JPEG_TIER_CNTL2  0x021a
+#define mmUVD_JPEG_TIER_CNTL2_BASE_IDX 1
+#define mmUVD_JPEG_UV_TILING_CTRL  0x021c
+#define mmUVD_JPEG_UV_TILING_CTRL_BASE_IDX 1
+#define mmUVD_JPEG_TILING_CTRL 0x021e
+#define mmUVD_JPEG_TILING_CTRL_BASE_IDX1
+#define mmUVD_JPEG_OUTBUF_RPTR 0x0220
+#define mmUVD_JPEG_OUTBUF_RPTR_BASE_IDX1
+#define mmUVD_JPEG_OUTBUF_WPTR 0x0221
+#define mmUVD_JPEG_OUTBUF_WPTR_BASE_IDX1
+#define mmUVD_JPEG_PITCH   0x0222
+#define mmUVD_JPEG_PITCH_BASE_IDX  1
+#define mmUVD_JPEG_INT_EN  0x0229
+#define mmUVD_JPEG_INT_EN_BASE_IDX 1
+#define mmUVD_JPEG_UV_PITCH0x022b
+#define mmUVD_JPEG_UV_PITCH_BASE_IDX   1
+#define mmUVD_JPEG_INDEX   0x023e
+#define mmUVD_JPEG_INDEX_BASE_IDX  1
+#define mmUVD_JPEG_DATA0x023f
+#define mmUVD_JPEG_DATA_BASE_IDX   1
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH0x0438
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX   1
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0439
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX1
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x045a
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX1
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW  0x045b
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_CTX_INDEX0x0528
+#define mmUVD_CTX_INDEX_BASE_IDX   1
+#define mmUVD_CTX_DATA 0x0529
+#define mmUVD_CTX_DATA_BASE_IDX1
+#define mmUVD_SOFT_RESET   0x05a0
+#define mmUVD_SOFT_RESET_BASE_IDX  1
+
+#define UVD_BASE_INST0_SEG00x7800
+#define UVD_BASE_INST0_SEG10x7E00
+#define UVD_BASE_INST0_SEG20
+#define UVD_BASE_INST0_SEG30
+#define UVD_BASE_INST0_SEG40
+
+#define SOC15_REG_ADDR(reg)(UVD_BASE_INST0_SEG1 + reg)
+
+#define COND0  0
+#define COND1  1
+#define COND2  2
+#define COND3  3
+#define COND4  4

[Mesa-dev] [PATCH 03/13] radeon/winsys: add vcn jpeg ring type

[boyuan.zhang]

From: Boyuan Zhang 

Add a new ring type for vcn jpeg.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_winsys.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 0a56539..6290eef 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -78,6 +78,7 @@ enum ring_type {
 RING_UVD_ENC,
 RING_VCN_DEC,
 RING_VCN_ENC,
+RING_VCN_JPEG,
 RING_LAST,
 };
 
-- 
2.7.4

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[Mesa-dev] [PATCH 01/13] radeon/vcn: move radeon decoder define to header file

[boyuan.zhang]

From: Boyuan Zhang 

Move radeon_decoder definition from "radeon_vcn_dec.c" to "radeon_vcn_dec.h",
so that it can be included by other files later.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 28 
 src/gallium/drivers/radeon/radeon_vcn_dec.h | 29 +
 2 files changed, 29 insertions(+), 28 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 4bc922d..8bea704 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -49,38 +49,10 @@
 #define RDECODE_GPCOM_VCPU_DATA1   0x20714
 #define RDECODE_ENGINE_CNTL0x20718
 
-#define NUM_BUFFERS4
 #define NUM_MPEG2_REFS 6
 #define NUM_H264_REFS  17
 #define NUM_VC1_REFS   5
 
-struct radeon_decoder {
-   struct pipe_video_codec base;
-
-   unsignedstream_handle;
-   unsignedstream_type;
-   unsignedframe_number;
-
-   struct pipe_screen  *screen;
-   struct radeon_winsys*ws;
-   struct radeon_winsys_cs *cs;
-
-   void*msg;
-   uint32_t*fb;
-   uint8_t *it;
-   void*bs_ptr;
-
-   struct rvid_buffer  msg_fb_it_buffers[NUM_BUFFERS];
-   struct rvid_buffer  bs_buffers[NUM_BUFFERS];
-   struct rvid_buffer  dpb;
-   struct rvid_buffer  ctx;
-   struct rvid_buffer  sessionctx;
-
-   unsignedbs_size;
-   unsignedcur_buffer;
-   void*render_pic_list[16];
-};
-
 static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
struct pipe_h264_picture_desc *pic)
 {
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index accffef..4a90687 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -105,6 +105,8 @@
 
 #define RDECODE_SPS_INFO_H264_EXTENSION_SUPPORT_FLAG_SHIFT 7
 
+#define NUM_BUFFERS4
+
 typedef struct rvcn_dec_message_index_s {
unsigned intmessage_id;
unsigned intoffset;
@@ -500,6 +502,33 @@ typedef struct rvcn_dec_feedback_profiling_s {
unsigned intdmaHwCrc32Value2;
 } rvcn_dec_feedback_profiling_t;
 
+struct radeon_decoder {
+   struct pipe_video_codec base;
+
+   unsignedstream_handle;
+   unsignedstream_type;
+   unsignedframe_number;
+
+   struct pipe_screen  *screen;
+   struct radeon_winsys*ws;
+   struct radeon_winsys_cs *cs;
+
+   void*msg;
+   uint32_t*fb;
+   uint8_t *it;
+   void*bs_ptr;
+
+   struct rvid_buffer  msg_fb_it_buffers[NUM_BUFFERS];
+   struct rvid_buffer  bs_buffers[NUM_BUFFERS];
+   struct rvid_buffer  dpb;
+   struct rvid_buffer  ctx;
+   struct rvid_buffer  sessionctx;
+
+   unsignedbs_size;
+   unsignedcur_buffer;
+   void*render_pic_list[16];
+};
+
 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templat);
 
-- 
2.7.4

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[Mesa-dev] [Bug 105371] r600_shader_from_tgsi - GPR limit exceeded - shader requires 360 registers

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=105371

--- Comment #12 from amonpaike  ---

> run "apitrace trace blender"), get to the point where things go wrong in
> blender, and after it has made visible you can just close blender and then
> try to attach the resulting blender.trace file to the bug. 
> 
> It is best to open a new bug for each issue. 
> 
> Best, 
> Gert


I created for you a video and the apitrace of two of the scenes where bugs
appear (no shadow ESM) and (transmission on principled BSDF shader)

my video card from glxinfo is AMD TURKS (radeon hd 7670m 2gb videoram) 
(for information, the two scenes work perfectly on the other gpu Mesa DRI
Intel(R) Ivybridge Mobile -intel hd 4000) 

in the compressed file there are the two apitrace and the two blender scenes

https://youtu.be/8p_mU_EPNoo
https://drive.google.com/open?id=1vBJphv68fpdZhdxNu-OvicdTRb6rBiIy


the version of mesa I tried is not the last one, but the one when I reported
you progress on the bug (padoka ppa not updated)
bender is the last night build

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Re: [Mesa-dev] INTEL_map_texture on i915/i965

[Lionel Landwerlin]

Hey Phi,

I can confirm this extension isn't implemented in Mesa.
I don't why it wasn't.

Talking briefly with Jason, it seems that mapping texture makes less 
sense on Skylake and above generations.
There we maintain compressed version of the textures in memory to 
further reduce memory bandwidth.
This would make the memory mapped mechanism more costly because we would 
need to decompress the texture when you want to access it (probably 
close to a ReadPixels in terms of performance).


-
Lionel

On 16/08/18 14:23, Phi Nguyen wrote:

Hi,

I hope to use the zero-memory copy on the Iris Pro 6200 
(Broadwell/Skylake).


The extension 
 says 
only OpenGL 3.0 is required yet it does not show up on Ubuntu 18.04.  
I saw a post from 2016 
 mentioning 
this feature, but that didn't get any replies.


Does an implementation of this even exist?  How would I go about 
getting it?


Thank you,
Phi


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Re: [Mesa-dev] [PATCH mesa] mailmap: add various typos of Emil's address from the log

[Emil Velikov]

On 16 August 2018 at 16:08, Eric Engestrom  wrote:
> Cc: Emil Velikov 
> Signed-off-by: Eric Engestrom 
> ---
>  .mailmap | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/.mailmap b/.mailmap
> index ff60ba7ea8548ee2c6b0..848d71400c0e146c9eab 100644
> --- a/.mailmap
> +++ b/.mailmap
> @@ -145,6 +145,11 @@ Edward O'Callaghan  
> 
>  Emeric Grange  Emeric 
>
>  Emil Velikov  
> +Emil Velikov  
> +Emil Velikov  
> +Emil Velikov  
> +Emil Velikov  
> +Emil Velikov  
>
Seemingly I cannot spell my own name. Good thing "Emil Velcro" never made it.
Thanks Eric.

Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH mesa] intel: various python cleanups

[Emil Velikov]

On 16 August 2018 at 15:43, Eric Engestrom  wrote:
> Signed-off-by: Eric Engestrom 
> ---
> Didn't feel like sending 15 patches for these, but I can split out some
> of it if needed.

Seems like a few C-isms got in there. Fwiw the patch is
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH mesa] egl: check for buffer overflow *before* corrupting our memory

[Emil Velikov]

On 16 August 2018 at 15:35, Eric Engestrom  wrote:
> Signed-off-by: Eric Engestrom 
> ---
It's very unlikely to happen since we have ClientAPIsString[100] and
the supported API are not going to overflow it anytime soon.
Regardless, patch is perfectly valid.

Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH] fixup! anv: Use central api generation scripts.

[Eric Engestrom]

On Thursday, 2018-08-16 15:47:11 +0100, Emil Velikov wrote:
> ---
>  src/intel/Android.vulkan.mk |  8 
>  src/intel/Makefile.vulkan.am| 10 +-
>  src/intel/vulkan/anv_entrypoints_gen.py |  9 ++---
>  src/intel/vulkan/anv_extensions_gen.py  |  9 ++---
>  src/intel/vulkan/anv_icd.py |  7 +--
>  src/intel/vulkan/meson.build| 26 ++---
>  6 files changed, 41 insertions(+), 28 deletions(-)
> 
> diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
> index af59963c66d..2dc9de6b901 100644
> --- a/src/intel/Android.vulkan.mk
> +++ b/src/intel/Android.vulkan.mk
> @@ -70,8 +70,8 @@ $(intermediates)/vulkan/dummy.c:
>   $(hide) touch $@
>  
>  $(intermediates)/vulkan/anv_entrypoints.h: $(intermediates)/vulkan/dummy.c
> - PYTHONPATH=$(MESA_TOP)/src/vulkan/util \
>   $(VK_ENTRYPOINTS_SCRIPT) \
> + --import-pah=$(MESA_TOP)/src/vulkan/util \

"--import-path"

>   --outdir $(dir $@) \
>   --xml $(MESA_TOP)/src/vulkan/registry/vk.xml
>  
> @@ -248,22 +248,22 @@ LOCAL_GENERATED_SOURCES += 
> $(intermediates)/vulkan/anv_extensions.h
>  
>  $(intermediates)/vulkan/anv_entrypoints.c:
>   @mkdir -p $(dir $@)
> - PYTHONPATH=$(MESA_TOP)/src/vulkan/util \
>   $(VK_ENTRYPOINTS_SCRIPT) \
> + --import-pah=$(MESA_TOP)/src/vulkan/util \

ditto

>   --xml $(MESA_TOP)/src/vulkan/registry/vk.xml \
>   --outdir $(dir $@)
>  
>  $(intermediates)/vulkan/anv_extensions.c:
>   @mkdir -p $(dir $@)
> - PYTHONPATH=$(MESA_TOP)/src/vulkan/util \
>   $(VK_EXTENSIONS_SCRIPT) \
> + --import-pah=$(MESA_TOP)/src/vulkan/util \

ditto

>   --xml $(MESA_TOP)/src/vulkan/registry/vk.xml \
>   --out-c $@
>  
>  $(intermediates)/vulkan/anv_extensions.h:
>   @mkdir -p $(dir $@)
> - PYTHONPATH=$(MESA_TOP)/src/vulkan/util \
>   $(VK_EXTENSIONS_SCRIPT) \
> + --import-pah=$(MESA_TOP)/src/vulkan/util \

ditto

>   --xml $(MESA_TOP)/src/vulkan/registry/vk.xml \
>   --out-h $@
>  
> diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
> index 91577bc9026..462ff98d359 100644
> --- a/src/intel/Makefile.vulkan.am
> +++ b/src/intel/Makefile.vulkan.am
> @@ -34,8 +34,8 @@ vulkan/anv_entrypoints.c: vulkan/anv_entrypoints_gen.py \
> $(vulkan_api_xml) \
> $(vulkan_api_generators_py)
>   $(MKDIR_GEN)
> - PYTHONPATH=$(top_srcdir)/src/vulkan/util \
>   $(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_entrypoints_gen.py \
> + --import-path=$(top_srcdir)/src/vulkan/util \
>   --xml $(vulkan_api_xml) \
>   --outdir $(builddir)/vulkan
>  vulkan/anv_entrypoints.h: vulkan/anv_entrypoints.c
> @@ -45,8 +45,8 @@ vulkan/anv_extensions.c: vulkan/anv_extensions_gen.py \
>$(vulkan_api_xml) \
>$(vulkan_api_generators_py)
>   $(MKDIR_GEN)
> - PYTHONPATH=$(top_srcdir)/src/vulkan/util \
>   $(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_extensions_gen.py \
> + --import-path=$(top_srcdir)/src/vulkan/util \
>   --xml $(vulkan_api_xml) \
>   --out-c $@
>  
> @@ -55,8 +55,8 @@ vulkan/anv_extensions.h: vulkan/anv_extensions_gen.py \
>$(vulkan_api_xml) \
>$(vulkan_api_generators_py)
>   $(MKDIR_GEN)
> - PYTHONPATH=$(top_srcdir)/src/vulkan/util \
>   $(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_extensions_gen.py \
> + --import-path=$(top_srcdir)/src/vulkan/util \
>   --xml $(vulkan_api_xml) \
>   --out-h $@
>  
> @@ -77,15 +77,15 @@ EXTRA_DIST += \
>  vulkan/dev_icd.json : vulkan/anv_extensions.py vulkan/anv_icd.py \
> $(vulkan_api_generators_py)
>   $(MKDIR_GEN)
> - PYTHONPATH=$(top_srcdir)/src/vulkan/util \
>   $(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_icd.py \
> + --import-path=$(top_srcdir)/src/vulkan/util \
>   --lib-path="${abs_top_builddir}/${LIB_DIR}" --out $@
>  
>  vulkan/intel_icd.@host_cpu@.json : vulkan/anv_extensions.py 
> vulkan/anv_icd.py \
>  $(vulkan_api_generators_py)
>   $(MKDIR_GEN)
> - PYTHONPATH=$(top_srcdir)/src/vulkan/util \
>   $(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_icd.py \
> + --import-path=$(top_srcdir)/src/vulkan/util \
>   --lib-path="${libdir}" --out $@
>  
>  if HAVE_INTEL_VULKAN
> diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
> b/src/intel/vulkan/anv_entrypoints_gen.py
> index 219369ecc67..e82afd34615 100644
> --- a/src/intel/vulkan/anv_entrypoints_gen.py
> +++ b/src/intel/vulkan/anv_entrypoints_gen.py
> @@ -24,9 +24,7 @@
>  
>  import argparse
>  import os
> -
> -from anv_extensions import MAX_API_VERSION, EXTENSIONS
> -import vk_entrypoints_gen
> 

Re: [Mesa-dev] [PATCH mesa] egl/wayland: remove sign from bitfield `formats`

[Emil Velikov]

On 16 August 2018 at 15:29, Eric Engestrom  wrote:
> Signed-off-by: Eric Engestrom 
> ---
>  src/egl/drivers/dri2/egl_dri2.h |  2 +-
>  src/egl/drivers/dri2/platform_wayland.c | 10 +-
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH mesa] egl/wayland: upcast before bitwise ops

[Emil Velikov]

On 16 August 2018 at 15:23, Eric Engestrom  wrote:
> Signed-off-by: Eric Engestrom 
> ---
>  src/egl/drivers/dri2/platform_wayland.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/egl/drivers/dri2/platform_wayland.c 
> b/src/egl/drivers/dri2/platform_wayland.c
> index 0913394b365255f6af63..f1680495210987d57ba6 100644
> --- a/src/egl/drivers/dri2/platform_wayland.c
> +++ b/src/egl/drivers/dri2/platform_wayland.c
> @@ -818,8 +818,8 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
> __DRI_IMAGE_ATTRIB_MODIFIER_LOWER,
> _lo);
>if (query) {
> - modifier = (uint64_t) mod_hi << 32;
> - modifier |= (uint64_t) (mod_lo & 0x);
> + modifier = ((uint64_t) mod_hi) << 32;
> + modifier |= ((uint64_t) mod_lo) & 0x;
>}
> }
>
> @@ -1192,8 +1192,8 @@ dmabuf_handle_modifier(void *data, struct 
> zwp_linux_dmabuf_v1 *dmabuf,
> dri2_dpy->formats |= (1 << visual_idx);
>
> mod = u_vector_add(_dpy->wl_modifiers[visual_idx]);
> -   *mod = (uint64_t) modifier_hi << 32;
> -   *mod |= (uint64_t) (modifier_lo & 0x);
> +   *mod = ((uint64_t) modifier_hi) << 32u;
> +   *mod |= ((uint64_t) modifier_lo) & 0x;
>  }
>
Since we're bound to make the same mistake again, can we make this an
inline helper in egl_dri2.h and reuse it in here + egl_dri2.c

Thanks
Emil
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Re: [Mesa-dev] [PATCH mesa v2 1/3] git_sha1: simplify logic

[Emil Velikov]

On 16 August 2018 at 14:24, Eric Engestrom  wrote:
> Signed-off-by: Eric Engestrom 
> ---
>  bin/git_sha1_gen.py  | 6 +-
>  src/Makefile.am  | 2 +-
>  src/git_sha1.h.in| 1 -
>  src/mesa/Android.libmesa_git_sha1.mk | 2 +-
>  4 files changed, 3 insertions(+), 8 deletions(-)
>  delete mode 100644 src/git_sha1.h.in
>
> diff --git a/bin/git_sha1_gen.py b/bin/git_sha1_gen.py
> index 77c5fa9d2951c8e10c1c..c6240662df3f6146a57f 100755
> --- a/bin/git_sha1_gen.py
> +++ b/bin/git_sha1_gen.py
> @@ -47,10 +47,6 @@ def write_if_different(contents):
>
>  git_sha1 = os.environ.get('MESA_GIT_SHA1_OVERRIDE', get_git_sha1())[:10]
>  if git_sha1:
> -git_sha1_h_in_path = os.path.join(os.path.dirname(sys.argv[0]),
> -  '..', 'src', 'git_sha1.h.in')
> -with open(git_sha1_h_in_path, 'r') as git_sha1_h_in:
> -new_sha1 = git_sha1_h_in.read().replace('@VCS_TAG@', git_sha1)
> -write_if_different(new_sha1)
> +write_if_different('#define MESA_GIT_SHA1 "git-' + git_sha1 + '"')
>  else:
>  write_if_different('')
Nice call - one file less, no fancy handling, all data side-by-side.
For the series:
Reviewed-by: Emil Velikov 

Thank you
Emil
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[Mesa-dev] [PATCH mesa] mailmap: add various typos of Emil's address from the log

[Eric Engestrom]

Cc: Emil Velikov 
Signed-off-by: Eric Engestrom 
---
 .mailmap | 5 +
 1 file changed, 5 insertions(+)

diff --git a/.mailmap b/.mailmap
index ff60ba7ea8548ee2c6b0..848d71400c0e146c9eab 100644
--- a/.mailmap
+++ b/.mailmap
@@ -145,6 +145,11 @@ Edward O'Callaghan  

 Emeric Grange  Emeric 
 
 Emil Velikov  
+Emil Velikov  
+Emil Velikov  
+Emil Velikov  
+Emil Velikov  
+Emil Velikov  
 
 Eric Anholt  Eric Anholt 
 
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa] util/xmlpool: make indentation coherent

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/util/xmlpool/t_options.h | 26 +-
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index f0537e965b8a3cda894c..a31fafac14c6ffb55bb2 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -53,7 +53,7 @@
  */
 #define DRI_CONF_SECTION_DEBUG \
 DRI_CONF_SECTION_BEGIN \
-   DRI_CONF_DESC(en,gettext("Debugging"))
+DRI_CONF_DESC(en,gettext("Debugging"))
 
 #define DRI_CONF_NO_RAST(def) \
 DRI_CONF_OPT_BEGIN_B(no_rast, def) \
@@ -77,7 +77,7 @@ DRI_CONF_OPT_END
 
 #define DRI_CONF_DISABLE_THROTTLING(def) \
 DRI_CONF_OPT_BEGIN_B(disable_throttling, def) \
-   DRI_CONF_DESC(en,gettext("Disable throttling on first batch after 
flush")) \
+DRI_CONF_DESC(en,gettext("Disable throttling on first batch after 
flush")) \
 DRI_CONF_OPT_END
 
 #define DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN(def) \
@@ -155,11 +155,11 @@ DRI_CONF_OPT_END
  */
 #define DRI_CONF_SECTION_QUALITY \
 DRI_CONF_SECTION_BEGIN \
-   DRI_CONF_DESC(en,gettext("Image Quality"))
+DRI_CONF_DESC(en,gettext("Image Quality"))
 
 #define DRI_CONF_EXCESS_MIPMAP(def) \
 DRI_CONF_OPT_BEGIN_B(excess_mipmap, def) \
-   DRI_CONF_DESC(en,"Enable extra mipmap level") \
+DRI_CONF_DESC(en,"Enable extra mipmap level") \
 DRI_CONF_OPT_END
 
 #define DRI_CONF_TEXTURE_DEPTH_FB   0
@@ -168,7 +168,7 @@ DRI_CONF_OPT_END
 #define DRI_CONF_TEXTURE_DEPTH_FORCE_16 3
 #define DRI_CONF_TEXTURE_DEPTH(def) \
 DRI_CONF_OPT_BEGIN_V(texture_depth,enum,def,"0:3") \
-   DRI_CONF_DESC_BEGIN(en,gettext("Texture color depth")) \
+DRI_CONF_DESC_BEGIN(en,gettext("Texture color depth")) \
 DRI_CONF_ENUM(0,gettext("Prefer frame buffer color depth")) \
 DRI_CONF_ENUM(1,gettext("Prefer 32 bits per texel")) \
 DRI_CONF_ENUM(2,gettext("Prefer 16 bits per texel")) \
@@ -205,7 +205,7 @@ DRI_CONF_OPT_END
 #define DRI_CONF_ROUND_ROUND 1
 #define DRI_CONF_ROUND_MODE(def) \
 DRI_CONF_OPT_BEGIN_V(round_mode,enum,def,"0:1") \
-   DRI_CONF_DESC_BEGIN(en,gettext("Color rounding method")) \
+DRI_CONF_DESC_BEGIN(en,gettext("Color rounding method")) \
 DRI_CONF_ENUM(0,gettext("Round color components downward")) \
 DRI_CONF_ENUM(1,gettext("Round to nearest color")) \
 DRI_CONF_DESC_END \
@@ -216,7 +216,7 @@ DRI_CONF_OPT_END
 #define DRI_CONF_DITHER_ORDERED 2
 #define DRI_CONF_DITHER_MODE(def) \
 DRI_CONF_OPT_BEGIN_V(dither_mode,enum,def,"0:2") \
-   DRI_CONF_DESC_BEGIN(en,gettext("Color dithering method")) \
+DRI_CONF_DESC_BEGIN(en,gettext("Color dithering method")) \
 DRI_CONF_ENUM(0,gettext("Horizontal error diffusion")) \
 DRI_CONF_ENUM(1,gettext("Horizontal error diffusion, reset 
error at line start")) \
 DRI_CONF_ENUM(2,gettext("Ordered 2D color dithering")) \
@@ -321,7 +321,7 @@ DRI_CONF_OPT_END
 
 #define DRI_CONF_TEXTURE_BLEND_QUALITY(def,range) \
 DRI_CONF_OPT_BEGIN_V(texture_blend_quality,float,def,range) \
-   DRI_CONF_DESC(en,gettext("Texture filtering quality vs. speed, AKA 
“brilinear” texture filtering")) \
+DRI_CONF_DESC(en,gettext("Texture filtering quality vs. speed, AKA 
“brilinear” texture filtering")) \
 DRI_CONF_OPT_END
 
 #define DRI_CONF_TEXTURE_HEAPS_ALL 0
@@ -329,11 +329,11 @@ DRI_CONF_OPT_END
 #define DRI_CONF_TEXTURE_HEAPS_GART 2
 #define DRI_CONF_TEXTURE_HEAPS(def) \
 DRI_CONF_OPT_BEGIN_V(texture_heaps,enum,def,"0:2") \
-   DRI_CONF_DESC_BEGIN(en,gettext("Used types of texture memory")) \
-   DRI_CONF_ENUM(0,gettext("All available memory")) \
-   DRI_CONF_ENUM(1,gettext("Only card memory (if available)")) \
-   DRI_CONF_ENUM(2,gettext("Only GART (AGP/PCIE) memory (if 
available)")) \
-   DRI_CONF_DESC_END \
+DRI_CONF_DESC_BEGIN(en,gettext("Used types of texture memory")) \
+DRI_CONF_ENUM(0,gettext("All available memory")) \
+DRI_CONF_ENUM(1,gettext("Only card memory (if available)")) \
+DRI_CONF_ENUM(2,gettext("Only GART (AGP/PCIE) memory (if 
available)")) \
+DRI_CONF_DESC_END \
 DRI_CONF_OPT_END
 
 #define DRI_CONF_MESA_GLTHREAD(def) \
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa] i965: drop duplicate assignments

[Eric Engestrom]

These are all already assigned when declared, a few lines above.

Signed-off-by: Eric Engestrom 
---
Note: I'm not 100% certain the value can never change by the time this
second assignment is done, so maybe it's the initial one that should be
dropped?
---
 src/mesa/drivers/dri/i965/brw_cs.c  | 1 -
 src/mesa/drivers/dri/i965/brw_gs.c  | 1 -
 src/mesa/drivers/dri/i965/brw_tcs.c | 1 -
 src/mesa/drivers/dri/i965/brw_tes.c | 1 -
 src/mesa/drivers/dri/i965/brw_vs.c  | 1 -
 src/mesa/drivers/dri/i965/brw_wm.c  | 1 -
 6 files changed, 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_cs.c 
b/src/mesa/drivers/dri/i965/brw_cs.c
index 498c80d46a529db87cd3..a1ad3ad3436058e246c2 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -176,7 +176,6 @@ brw_upload_cs_prog(struct brw_context *brw)
if (brw_disk_cache_upload_program(brw, MESA_SHADER_COMPUTE))
   return;
 
-   cp = (struct brw_program *) brw->programs[MESA_SHADER_COMPUTE];
cp->id = key.program_string_id;
 
MAYBE_UNUSED bool success = brw_codegen_cs_prog(brw, cp, );
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c 
b/src/mesa/drivers/dri/i965/brw_gs.c
index 7263f6351e92847d603d..186a8946699bd0498b73 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -200,7 +200,6 @@ brw_upload_gs_prog(struct brw_context *brw)
if (brw_disk_cache_upload_program(brw, MESA_SHADER_GEOMETRY))
   return;
 
-   gp = (struct brw_program *) brw->programs[MESA_SHADER_GEOMETRY];
gp->id = key.program_string_id;
 
MAYBE_UNUSED bool success = brw_codegen_gs_prog(brw, gp, );
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c 
b/src/mesa/drivers/dri/i965/brw_tcs.c
index 53611144ff5098060c68..9332e10f76814d7ad24f 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -345,7 +345,6 @@ brw_upload_tcs_prog(struct brw_context *brw)
if (brw_disk_cache_upload_program(brw, MESA_SHADER_TESS_CTRL))
   return;
 
-   tcp = (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
if (tcp)
   tcp->id = key.program_string_id;
 
diff --git a/src/mesa/drivers/dri/i965/brw_tes.c 
b/src/mesa/drivers/dri/i965/brw_tes.c
index b3220a947415ed2e7efc..ace1629e6ace8d9ba4c7 100644
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -203,7 +203,6 @@ brw_upload_tes_prog(struct brw_context *brw)
if (brw_disk_cache_upload_program(brw, MESA_SHADER_TESS_EVAL))
   return;
 
-   tep = (struct brw_program *) brw->programs[MESA_SHADER_TESS_EVAL];
tep->id = key.program_string_id;
 
MAYBE_UNUSED bool success = brw_codegen_tes_prog(brw, tep, );
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c 
b/src/mesa/drivers/dri/i965/brw_vs.c
index 69c0046bbb98c7b283ee..7ffd6bfc482f4e45d81f 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -349,7 +349,6 @@ brw_upload_vs_prog(struct brw_context *brw)
if (brw_disk_cache_upload_program(brw, MESA_SHADER_VERTEX))
   return;
 
-   vp = (struct brw_program *) brw->programs[MESA_SHADER_VERTEX];
vp->id = key.program_string_id;
 
MAYBE_UNUSED bool success = brw_codegen_vs_prog(brw, vp, );
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
b/src/mesa/drivers/dri/i965/brw_wm.c
index db632ed15e1be9b472f7..a78f3d6678eb807ca649 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -603,7 +603,6 @@ brw_upload_wm_prog(struct brw_context *brw)
if (brw_disk_cache_upload_program(brw, MESA_SHADER_FRAGMENT))
   return;
 
-   fp = (struct brw_program *) brw->programs[MESA_SHADER_FRAGMENT];
fp->id = key.program_string_id;
 
MAYBE_UNUSED bool success = brw_codegen_wm_prog(brw, fp, ,
-- 
Cheers,
  Eric

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Re: [Mesa-dev] [PATCH 0/4] Merge vulkan API generators.

[Emil Velikov]

On 8 August 2018 at 00:14, Bas Nieuwenhuizen  wrote:
> radv was always just mirroring a derived version of the anv
> version, sometimes hacked together and sometimes very behind.
>
> As we grow more vulkan drivers this repetition makes even less
> sense, so lets merge them. I took the anv generators as the
> template and made radv use them.
>
> This includes some messy stuff in the build system due to
> difficulties with python includes. I tested with meson and
> autotools. Android.mk is updated but not tested.
>
I've sent out a couple of fixup commits for 3/4 and 4/4.
They remove the hacky PYTHONPATH, by introducing --import-path argument.
An idea shamelessly copied from src/intel/compiler/brw_nir_trig_workarounds.py

I haven't actually tested these - just getting it out to illustrate
what I meant earlier.
Feel free to reuse as much or as little as you like.

HTH
Emil
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Re: [Mesa-dev] [PATCH mesa] i965: drop unused assignment

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin 

On 16/08/18 15:49, Eric Engestrom wrote:

Signed-off-by: Eric Engestrom 
---
  src/mesa/drivers/dri/i965/brw_bufmgr.c | 2 --
  1 file changed, 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index b0f83fb832066094f044..f1675b191c1003883f90 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -980,7 +980,6 @@ brw_bo_map_cpu(struct brw_context *brw, struct brw_bo *bo, 
unsigned flags)
};
int ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP, _arg);
if (ret != 0) {
- ret = -errno;
   DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
   __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
   return NULL;
@@ -1044,7 +1043,6 @@ brw_bo_map_wc(struct brw_context *brw, struct brw_bo *bo, 
unsigned flags)
};
int ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP, _arg);
if (ret != 0) {
- ret = -errno;
   DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
   __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
   return NULL;



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Re: [Mesa-dev] [PATCH mesa] anv: drop cast-to-void of used variable

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin 

On 16/08/18 15:48, Eric Engestrom wrote:

`device` is used 2 lines below, even visible in the diff context printed.

Signed-off-by: Eric Engestrom 
---
  src/intel/vulkan/anv_device.c | 1 -
  1 file changed, 1 deletion(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 897249baa6aea4958c23..d8b67b54d638fb42dcfa 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1445,7 +1445,6 @@ VkResult anv_EnumerateDeviceExtensionProperties(
  {
 ANV_FROM_HANDLE(anv_physical_device, device, physicalDevice);
 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
-   (void)device;
  
 for (int i = 0; i < ANV_DEVICE_EXTENSION_COUNT; i++) {

if (device->supported_extensions.extensions[i]) {



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Re: [Mesa-dev] [PATCH mesa] anv: use safer snprintf() to ensure NULL string-terminator

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin 

On 16/08/18 15:46, Eric Engestrom wrote:

Signed-off-by: Eric Engestrom 
---
  src/intel/vulkan/anv_device.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index c40b94d69f349828b964..897249baa6aea4958c23 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -325,7 +325,7 @@ anv_physical_device_init(struct anv_physical_device *device,
 device->instance = instance;
  
 assert(strlen(path) < ARRAY_SIZE(device->path));

-   strncpy(device->path, path, ARRAY_SIZE(device->path));
+   snprintf(device->path, ARRAY_SIZE(device->path), "%s", path);
  
 device->no_hw = getenv("INTEL_NO_HW") != NULL;
  



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[Mesa-dev] [PATCH] fixup! radv: Integrate with common generators.

[Emil Velikov]

---
 src/amd/vulkan/Android.mk  |  4 ++--
 src/amd/vulkan/Makefile.am | 16 
 src/amd/vulkan/meson.build | 26 --
 src/amd/vulkan/radv_entrypoints_gen.py |  9 ++---
 src/amd/vulkan/radv_extensions_gen.py  |  9 ++---
 src/amd/vulkan/radv_icd.py |  7 +--
 6 files changed, 43 insertions(+), 28 deletions(-)

diff --git a/src/amd/vulkan/Android.mk b/src/amd/vulkan/Android.mk
index 8792b7ade7f..9e9c3dea342 100644
--- a/src/amd/vulkan/Android.mk
+++ b/src/amd/vulkan/Android.mk
@@ -101,8 +101,8 @@ $(intermediates)/radv_entrypoints.c: 
$(RADV_ENTRYPOINTS_SCRIPT) \
$(vulkan_api_xml) \
$(vulkan_api_generators_py)
@mkdir -p $(dir $@)
-   PYTHONPATH=$(MESA_TOP)/src/vulkan/util \
$(MESA_PYTHON2) $(RADV_ENTRYPOINTS_SCRIPT) \
+   --import-path=$(MESA_TOP)/src/vulkan/util \
--xml $(vulkan_api_xml) \
--outdir $(dir $@)
 
@@ -111,8 +111,8 @@ $(intermediates)/radv_entrypoints.h: 
$(intermediates)/radv_entrypoints.c
 $(intermediates)/radv_extensions.c: $(RADV_EXTENSIONS_GEN_SCRIPT) 
$(RADV_EXTENSIONS_SCRIPT) \
$(vulkan_api_xml) 
$(vulkan_api_generators_py)
@mkdir -p $(dir $@)\
-   PYTHONPATH=$(MESA_TOP)/src/vulkan/util \
$(MESA_PYTHON2) $(RADV_EXTENSIONS_SCRIPT) \
+   --import-path=$(MESA_TOP)/src/vulkan/util \
--xml $(vulkan_api_xml) \
--out-c $@ \
--out-h $(addsuffix .h,$(basename $@))
diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index f571903f1a6..84722fbd59d 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -146,8 +146,8 @@ vulkan_api_xml = $(top_srcdir)/src/vulkan/registry/vk.xml
 radv_entrypoints.c: radv_entrypoints_gen.py radv_extensions.py 
$(vulkan_api_xml) \
$(vulkan_api_generators_py)
$(MKDIR_GEN)
-   $(AM_V_GEN) PYTHONPATH=$(top_srcdir)/src/vulkan/util \
-   $(PYTHON2) $(srcdir)/radv_entrypoints_gen.py \
+   $(AM_V_GEN) $(PYTHON2) $(srcdir)/radv_entrypoints_gen.py \
+   --import-path=$(top_srcdir)/src/vulkan/util \
--xml $(vulkan_api_xml) \
--outdir $(builddir)
 radv_entrypoints.h: radv_entrypoints.c
@@ -155,8 +155,8 @@ radv_entrypoints.h: radv_entrypoints.c
 radv_extensions.c: radv_extensions_gen.py radv_extensions.py \
   $(vulkan_api_xml) $(vulkan_api_generators_py)
$(MKDIR_GEN)
-   $(AM_V_GEN) PYTHONPATH=$(top_srcdir)/src/vulkan/util \
-   $(PYTHON2) $(srcdir)/radv_extensions_gen.py \
+   $(AM_V_GEN) $(PYTHON2) $(srcdir)/radv_extensions_gen.py \
+   --import-path=$(top_srcdir)/src/vulkan/util \
--xml $(vulkan_api_xml) \
--out-c radv_extensions.c \
--out-h radv_extensions.h
@@ -199,13 +199,13 @@ icdconf_DATA = radeon_icd.@host_cpu@.json
 noinst_DATA = dev_icd.json
 
 dev_icd.json : radv_extensions.py radv_icd.py  $(vulkan_api_generators_py)
-   $(AM_V_GEN) PYTHONPATH=$(top_srcdir)/src/vulkan/util \
-   $(PYTHON2) $(srcdir)/radv_icd.py \
+   $(AM_V_GEN) $(PYTHON2) $(srcdir)/radv_icd.py \
+   --import-path=$(top_srcdir)/src/vulkan/util \
--lib-path="${abs_top_builddir}/${LIB_DIR}" --out $@
 
 radeon_icd.@host_cpu@.json : radv_extensions.py radv_icd.py  
$(vulkan_api_generators_py)
-   $(AM_V_GEN) PYTHONPATH=$(top_srcdir)/src/vulkan/util \
-   $(PYTHON2) $(srcdir)/radv_icd.py \
+   $(AM_V_GEN) $(PYTHON2) $(srcdir)/radv_icd.py \
+   --import-path=$(top_srcdir)/src/vulkan/util \
--lib-path="${libdir}" --out $@
 
 include $(top_srcdir)/install-lib-links.mk
diff --git a/src/amd/vulkan/meson.build b/src/amd/vulkan/meson.build
index 0f2a29752da..0f46663257a 100644
--- a/src/amd/vulkan/meson.build
+++ b/src/amd/vulkan/meson.build
@@ -25,9 +25,10 @@ radv_entrypoints = custom_target(
   input : ['radv_entrypoints_gen.py', vk_api_xml],
   output : ['radv_entrypoints.h', 'radv_entrypoints.c'],
   command : [
-'env', 'PYTHONPATH=@0@'.format(join_paths(meson.source_root(), 
'src/vulkan/util/')),
-prog_python, '@INPUT0@', '--xml', '@INPUT1@', '--outdir',
-meson.current_build_dir()
+prog_python, '@INPUT0@',
+'--import-path' join_paths(meson.source_root(), 'src/vulkan/util/'),
+'--xml', '@INPUT1@',
+'--outdir', meson.current_build_dir()
   ],
   depend_files : [radv_extensions_py, vk_api_generators_py],
 )
@@ -37,8 +38,10 @@ radv_extensions_c = custom_target(
   input : ['radv_extensions_gen_.py', vk_api_xml],
   output : ['radv_extensions.c'],
   command : [
-'env', 'PYTHONPATH=@0@'.format(join_paths(meson.source_root(), 
'src/vulkan/util/')),
-prog_python, '@INPUT0@', '--xml', '@INPUT1@', '--out-c', '@OUTPUT@'
+prog_python, 

[Mesa-dev] [PATCH] fixup! anv: Use central api generation scripts.

[Emil Velikov]

---
 src/intel/Android.vulkan.mk |  8 
 src/intel/Makefile.vulkan.am| 10 +-
 src/intel/vulkan/anv_entrypoints_gen.py |  9 ++---
 src/intel/vulkan/anv_extensions_gen.py  |  9 ++---
 src/intel/vulkan/anv_icd.py |  7 +--
 src/intel/vulkan/meson.build| 26 ++---
 6 files changed, 41 insertions(+), 28 deletions(-)

diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
index af59963c66d..2dc9de6b901 100644
--- a/src/intel/Android.vulkan.mk
+++ b/src/intel/Android.vulkan.mk
@@ -70,8 +70,8 @@ $(intermediates)/vulkan/dummy.c:
$(hide) touch $@
 
 $(intermediates)/vulkan/anv_entrypoints.h: $(intermediates)/vulkan/dummy.c
-   PYTHONPATH=$(MESA_TOP)/src/vulkan/util \
$(VK_ENTRYPOINTS_SCRIPT) \
+   --import-pah=$(MESA_TOP)/src/vulkan/util \
--outdir $(dir $@) \
--xml $(MESA_TOP)/src/vulkan/registry/vk.xml
 
@@ -248,22 +248,22 @@ LOCAL_GENERATED_SOURCES += 
$(intermediates)/vulkan/anv_extensions.h
 
 $(intermediates)/vulkan/anv_entrypoints.c:
@mkdir -p $(dir $@)
-   PYTHONPATH=$(MESA_TOP)/src/vulkan/util \
$(VK_ENTRYPOINTS_SCRIPT) \
+   --import-pah=$(MESA_TOP)/src/vulkan/util \
--xml $(MESA_TOP)/src/vulkan/registry/vk.xml \
--outdir $(dir $@)
 
 $(intermediates)/vulkan/anv_extensions.c:
@mkdir -p $(dir $@)
-   PYTHONPATH=$(MESA_TOP)/src/vulkan/util \
$(VK_EXTENSIONS_SCRIPT) \
+   --import-pah=$(MESA_TOP)/src/vulkan/util \
--xml $(MESA_TOP)/src/vulkan/registry/vk.xml \
--out-c $@
 
 $(intermediates)/vulkan/anv_extensions.h:
@mkdir -p $(dir $@)
-   PYTHONPATH=$(MESA_TOP)/src/vulkan/util \
$(VK_EXTENSIONS_SCRIPT) \
+   --import-pah=$(MESA_TOP)/src/vulkan/util \
--xml $(MESA_TOP)/src/vulkan/registry/vk.xml \
--out-h $@
 
diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
index 91577bc9026..462ff98d359 100644
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -34,8 +34,8 @@ vulkan/anv_entrypoints.c: vulkan/anv_entrypoints_gen.py \
  $(vulkan_api_xml) \
  $(vulkan_api_generators_py)
$(MKDIR_GEN)
-   PYTHONPATH=$(top_srcdir)/src/vulkan/util \
$(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_entrypoints_gen.py \
+   --import-path=$(top_srcdir)/src/vulkan/util \
--xml $(vulkan_api_xml) \
--outdir $(builddir)/vulkan
 vulkan/anv_entrypoints.h: vulkan/anv_entrypoints.c
@@ -45,8 +45,8 @@ vulkan/anv_extensions.c: vulkan/anv_extensions_gen.py \
 $(vulkan_api_xml) \
 $(vulkan_api_generators_py)
$(MKDIR_GEN)
-   PYTHONPATH=$(top_srcdir)/src/vulkan/util \
$(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_extensions_gen.py \
+   --import-path=$(top_srcdir)/src/vulkan/util \
--xml $(vulkan_api_xml) \
--out-c $@
 
@@ -55,8 +55,8 @@ vulkan/anv_extensions.h: vulkan/anv_extensions_gen.py \
 $(vulkan_api_xml) \
 $(vulkan_api_generators_py)
$(MKDIR_GEN)
-   PYTHONPATH=$(top_srcdir)/src/vulkan/util \
$(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_extensions_gen.py \
+   --import-path=$(top_srcdir)/src/vulkan/util \
--xml $(vulkan_api_xml) \
--out-h $@
 
@@ -77,15 +77,15 @@ EXTRA_DIST += \
 vulkan/dev_icd.json : vulkan/anv_extensions.py vulkan/anv_icd.py \
  $(vulkan_api_generators_py)
$(MKDIR_GEN)
-   PYTHONPATH=$(top_srcdir)/src/vulkan/util \
$(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_icd.py \
+   --import-path=$(top_srcdir)/src/vulkan/util \
--lib-path="${abs_top_builddir}/${LIB_DIR}" --out $@
 
 vulkan/intel_icd.@host_cpu@.json : vulkan/anv_extensions.py vulkan/anv_icd.py \
   $(vulkan_api_generators_py)
$(MKDIR_GEN)
-   PYTHONPATH=$(top_srcdir)/src/vulkan/util \
$(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_icd.py \
+   --import-path=$(top_srcdir)/src/vulkan/util \
--lib-path="${libdir}" --out $@
 
 if HAVE_INTEL_VULKAN
diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index 219369ecc67..e82afd34615 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -24,9 +24,7 @@
 
 import argparse
 import os
-
-from anv_extensions import MAX_API_VERSION, EXTENSIONS
-import vk_entrypoints_gen
+import sys
 
 # We generate a static hash table for entry point lookup
 # (vkGetProcAddress). We use a linear congruential generator for our hash
@@ -45,6 +43,7 @@ LAYERS = [
 
 def main():
 parser = 

[Mesa-dev] [PATCH mesa] i965: drop unused assignment

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/mesa/drivers/dri/i965/brw_bufmgr.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index b0f83fb832066094f044..f1675b191c1003883f90 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -980,7 +980,6 @@ brw_bo_map_cpu(struct brw_context *brw, struct brw_bo *bo, 
unsigned flags)
   };
   int ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP, _arg);
   if (ret != 0) {
- ret = -errno;
  DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
  __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
  return NULL;
@@ -1044,7 +1043,6 @@ brw_bo_map_wc(struct brw_context *brw, struct brw_bo *bo, 
unsigned flags)
   };
   int ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP, _arg);
   if (ret != 0) {
- ret = -errno;
  DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
  __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
  return NULL;
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa] anv: drop cast-to-void of used variable

[Eric Engestrom]

`device` is used 2 lines below, even visible in the diff context printed.

Signed-off-by: Eric Engestrom 
---
 src/intel/vulkan/anv_device.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 897249baa6aea4958c23..d8b67b54d638fb42dcfa 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1445,7 +1445,6 @@ VkResult anv_EnumerateDeviceExtensionProperties(
 {
ANV_FROM_HANDLE(anv_physical_device, device, physicalDevice);
VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
-   (void)device;
 
for (int i = 0; i < ANV_DEVICE_EXTENSION_COUNT; i++) {
   if (device->supported_extensions.extensions[i]) {
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa] anv: use safer snprintf() to ensure NULL string-terminator

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/intel/vulkan/anv_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index c40b94d69f349828b964..897249baa6aea4958c23 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -325,7 +325,7 @@ anv_physical_device_init(struct anv_physical_device *device,
device->instance = instance;
 
assert(strlen(path) < ARRAY_SIZE(device->path));
-   strncpy(device->path, path, ARRAY_SIZE(device->path));
+   snprintf(device->path, ARRAY_SIZE(device->path), "%s", path);
 
device->no_hw = getenv("INTEL_NO_HW") != NULL;
 
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa] intel: various python cleanups

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
Didn't feel like sending 15 patches for these, but I can split out some
of it if needed.
---
 src/intel/genxml/gen_bits_header.py |  1 -
 src/intel/genxml/gen_pack_header.py | 29 ++---
 src/intel/genxml/gen_zipped_file.py |  1 -
 src/intel/isl/gen_format_layout.py  |  9 -
 src/intel/vulkan/anv_extensions.py  |  7 +++
 5 files changed, 21 insertions(+), 26 deletions(-)

diff --git a/src/intel/genxml/gen_bits_header.py 
b/src/intel/genxml/gen_bits_header.py
index dcd6ccb7d9ec39109cb0..ded2d2dcfcfd74dbec1d 100644
--- a/src/intel/genxml/gen_bits_header.py
+++ b/src/intel/genxml/gen_bits_header.py
@@ -25,7 +25,6 @@
 
 import argparse
 import os
-import sys
 import xml.parsers.expat
 
 from mako.template import Template
diff --git a/src/intel/genxml/gen_pack_header.py 
b/src/intel/genxml/gen_pack_header.py
index c3d712c7a86e1580ec0f..0bf838de8c60cd8744a6 100644
--- a/src/intel/genxml/gen_pack_header.py
+++ b/src/intel/genxml/gen_pack_header.py
@@ -219,9 +219,9 @@ def safe_name(name):
 def num_from_str(num_str):
 if num_str.lower().startswith('0x'):
 return int(num_str, base=16)
-else:
-assert not num_str.startswith('0'), 'octals numbers not allowed'
-return int(num_str)
+
+assert not num_str.startswith('0'), 'octals numbers not allowed'
+return int(num_str)
 
 class Field(object):
 ufixed_pattern = re.compile(r"u(\d+)\.(\d+)")
@@ -306,7 +306,7 @@ def emit_template_struct(self, dim):
 print("   %-36s %s%s;" % (type, self.name, dim))
 
 prefix = ""
-if len(self.values) > 0 and self.default == None:
+if self.values and self.default == None:
 if self.prefix:
 prefix = self.prefix + "_"
 
@@ -340,7 +340,7 @@ def __init__(self):
 
 def collect_dwords(self, dwords, start, dim):
 for field in self.fields:
-if type(field) is Group:
+if isinstance(field, Group):
 if field.count == 1:
 field.collect_dwords(dwords, start + field.start, dim)
 else:
@@ -424,7 +424,7 @@ def emit_pack_function(self, dwords, length):
 # to the dword for those fields.
 field_index = 0
 for field in dw.fields:
-if type(field) is Field and field.is_struct_type():
+if isinstance(field, Field) and field.is_struct_type():
 name = field.name + field.dim
 print("")
 print("   uint32_t v%d_%d;" % (index, field_index))
@@ -490,7 +490,7 @@ def emit_pack_function(self, dwords, length):
 non_address_fields.append("/* unhandled field %s, type %s 
*/\n" % \
   (name, field.type))
 
-if len(non_address_fields) > 0:
+if non_address_fields:
 print(" |\n".join("  " + f for f in non_address_fields) + 
";")
 
 if dw.size == 32:
@@ -531,8 +531,7 @@ def __init__(self):
 def gen_prefix(self, name):
 if name[0] == "_":
 return 'GEN%s%s' % (self.gen, name)
-else:
-return 'GEN%s_%s' % (self.gen, name)
+return 'GEN%s_%s' % (self.gen, name)
 
 def gen_guard(self):
 return self.gen_prefix("PACK_H")
@@ -629,7 +628,7 @@ def emit_pack_function(self, name, group):
 
 def emit_instruction(self):
 name = self.instruction
-if not self.length == None:
+if not self.length is None:
 print('#define %-33s %6d' %
   (self.gen_prefix(name + "_length"), self.length))
 print('#define %-33s %6d' %
@@ -637,9 +636,9 @@ def emit_instruction(self):
 
 default_fields = []
 for field in self.group.fields:
-if not type(field) is Field:
+if not isinstance(field, Field):
 continue
-if field.default == None:
+if field.default is None:
 continue
 default_fields.append("   .%-35s = %6d" % (field.name, 
field.default))
 
@@ -654,11 +653,11 @@ def emit_instruction(self):
 
 def emit_register(self):
 name = self.register
-if not self.reg_num == None:
+if not self.reg_num is None:
 print('#define %-33s 0x%04x' %
   (self.gen_prefix(name + "_num"), self.reg_num))
 
-if not self.length == None:
+if not self.length is None:
 print('#define %-33s %6d' %
   (self.gen_prefix(name + "_length"), self.length))
 
@@ -667,7 +666,7 @@ def emit_register(self):
 
 def emit_struct(self):
 name = self.struct
-if not self.length == None:
+if not self.length is None:
 print('#define %-33s %6d' %
   (self.gen_prefix(name + "_length"), self.length))
 
diff --git a/src/intel/genxml/gen_zipped_file.py 
b/src/intel/genxml/gen_zipped_file.py

Re: [Mesa-dev] [PATCH mesa] intel/batch-decoder: replace local ARRAY_LENGTH() macro with global ARRAY_SIZE()

[Lionel Landwerlin]

On 16/08/18 15:38, Eric Engestrom wrote:

Signed-off-by: Eric Engestrom 


Reviewed-by: Lionel Landwerlin 


---
  src/intel/common/gen_batch_decoder.c | 5 ++---
  1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/intel/common/gen_batch_decoder.c 
b/src/intel/common/gen_batch_decoder.c
index f5be0018afce507685b4..f93f4df0066b8191ca5f 100644
--- a/src/intel/common/gen_batch_decoder.c
+++ b/src/intel/common/gen_batch_decoder.c
@@ -23,6 +23,7 @@
  
  #include "common/gen_decoder.h"

  #include "gen_disasm.h"
+#include "util/macros.h"
  
  #include 
  
@@ -65,8 +66,6 @@ gen_batch_decode_ctx_finish(struct gen_batch_decode_ctx *ctx)

  #define GREEN_HEADER CSI "1;42m"
  #define NORMAL   CSI "0m"
  
-#define ARRAY_LENGTH(a) (sizeof (a) / sizeof (a)[0])

-
  static void
  ctx_print_group(struct gen_batch_decode_ctx *ctx,
  struct gen_group *group,
@@ -835,7 +834,7 @@ gen_print_batch(struct gen_batch_decode_ctx *ctx,
if (ctx->flags & GEN_BATCH_DECODE_FULL) {
   ctx_print_group(ctx, inst, offset, p);
  
- for (int i = 0; i < ARRAY_LENGTH(custom_decoders); i++) {

+ for (int i = 0; i < ARRAY_SIZE(custom_decoders); i++) {
  if (strcmp(inst_name, custom_decoders[i].cmd_name) == 0) {
 custom_decoders[i].decode(ctx, p);
 break;



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[Mesa-dev] [PATCH mesa] intel/batch-decoder: replace local ARRAY_LENGTH() macro with global ARRAY_SIZE()

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/intel/common/gen_batch_decoder.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/intel/common/gen_batch_decoder.c 
b/src/intel/common/gen_batch_decoder.c
index f5be0018afce507685b4..f93f4df0066b8191ca5f 100644
--- a/src/intel/common/gen_batch_decoder.c
+++ b/src/intel/common/gen_batch_decoder.c
@@ -23,6 +23,7 @@
 
 #include "common/gen_decoder.h"
 #include "gen_disasm.h"
+#include "util/macros.h"
 
 #include 
 
@@ -65,8 +66,6 @@ gen_batch_decode_ctx_finish(struct gen_batch_decode_ctx *ctx)
 #define GREEN_HEADER CSI "1;42m"
 #define NORMAL   CSI "0m"
 
-#define ARRAY_LENGTH(a) (sizeof (a) / sizeof (a)[0])
-
 static void
 ctx_print_group(struct gen_batch_decode_ctx *ctx,
 struct gen_group *group,
@@ -835,7 +834,7 @@ gen_print_batch(struct gen_batch_decode_ctx *ctx,
   if (ctx->flags & GEN_BATCH_DECODE_FULL) {
  ctx_print_group(ctx, inst, offset, p);
 
- for (int i = 0; i < ARRAY_LENGTH(custom_decoders); i++) {
+ for (int i = 0; i < ARRAY_SIZE(custom_decoders); i++) {
 if (strcmp(inst_name, custom_decoders[i].cmd_name) == 0) {
custom_decoders[i].decode(ctx, p);
break;
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa] egl: check for buffer overflow *before* corrupting our memory

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/egl/main/eglapi.c | 19 +++
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index 19fae12f5b7596e07959..5e5048c4d69fdcf02a15 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -538,19 +538,30 @@ _eglCreateExtensionsString(_EGLDisplay *dpy)
 static void
 _eglCreateAPIsString(_EGLDisplay *dpy)
 {
+#define addstr(str) \
+   { \
+  const size_t old_len = strlen(dpy->ClientAPIsString); \
+  const size_t add_len = sizeof(str); \
+  const size_t max_len = sizeof(dpy->ClientAPIsString) - 1; \
+  if (old_len + add_len <= max_len) \
+ strcat(dpy->ClientAPIsString, str " "); \
+  else \
+ assert(!"dpy->ClientAPIsString is not large enough"); \
+   }
+
if (dpy->ClientAPIs & EGL_OPENGL_BIT)
-  strcat(dpy->ClientAPIsString, "OpenGL ");
+  addstr("OpenGL");
 
if (dpy->ClientAPIs & EGL_OPENGL_ES_BIT ||
dpy->ClientAPIs & EGL_OPENGL_ES2_BIT ||
dpy->ClientAPIs & EGL_OPENGL_ES3_BIT_KHR) {
-  strcat(dpy->ClientAPIsString, "OpenGL_ES ");
+  addstr("OpenGL_ES");
}
 
if (dpy->ClientAPIs & EGL_OPENVG_BIT)
-  strcat(dpy->ClientAPIsString, "OpenVG ");
+  addstr("OpenVG");
 
-   assert(strlen(dpy->ClientAPIsString) < sizeof(dpy->ClientAPIsString));
+#undef addstr
 }
 
 static void
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa] egl/wayland: remove sign from bitfield `formats`

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/egl/drivers/dri2/egl_dri2.h |  2 +-
 src/egl/drivers/dri2/platform_wayland.c | 10 +-
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index f8001ec4b661f6dce20b..a6588632f776de58df48 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -223,7 +223,7 @@ struct dri2_egl_display
struct zwp_linux_dmabuf_v1 *wl_dmabuf;
struct u_vector  *wl_modifiers;
bool  authenticated;
-   int   formats;
+   unsigned  formats;
uint32_t  capabilities;
char *device_name;
 #endif
diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index f1680495210987d57ba6..32330f8b19499fcead55 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -1059,7 +1059,7 @@ dri2_wl_create_wayland_buffer_from_image(_EGLDriver *drv,
if (visual_idx == -1)
   goto bad_format;
 
-   if (!(dri2_dpy->formats & (1 << visual_idx)))
+   if (!(dri2_dpy->formats & (1u << visual_idx)))
   goto bad_format;
 
buffer = create_wl_buffer(dri2_dpy, NULL, image);
@@ -1140,7 +1140,7 @@ drm_handle_format(void *data, struct wl_drm *drm, 
uint32_t format)
if (visual_idx == -1)
   return;
 
-   dri2_dpy->formats |= (1 << visual_idx);
+   dri2_dpy->formats |= (1u << visual_idx);
 }
 
 static void
@@ -1189,7 +1189,7 @@ dmabuf_handle_modifier(void *data, struct 
zwp_linux_dmabuf_v1 *dmabuf,
modifier_lo == (DRM_FORMAT_MOD_INVALID & 0x))
   return;
 
-   dri2_dpy->formats |= (1 << visual_idx);
+   dri2_dpy->formats |= (1u << visual_idx);
 
mod = u_vector_add(_dpy->wl_modifiers[visual_idx]);
*mod = ((uint64_t) modifier_hi) << 32u;
@@ -1288,7 +1288,7 @@ dri2_wl_add_configs_for_visuals(_EGLDriver *drv, 
_EGLDisplay *disp)
   for (unsigned j = 0; j < ARRAY_SIZE(dri2_wl_visuals); j++) {
  struct dri2_egl_config *dri2_conf;
 
- if (!(dri2_dpy->formats & (1 << j)))
+ if (!(dri2_dpy->formats & (1u << j)))
 continue;
 
  dri2_conf = dri2_add_config(disp, dri2_dpy->driver_configs[i],
@@ -1906,7 +1906,7 @@ shm_handle_format(void *data, struct wl_shm *shm, 
uint32_t format)
if (visual_idx == -1)
   return;
 
-   dri2_dpy->formats |= (1 << visual_idx);
+   dri2_dpy->formats |= (1u << visual_idx);
 }
 
 static const struct wl_shm_listener shm_listener = {
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa] egl/wayland: upcast before bitwise ops

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/egl/drivers/dri2/platform_wayland.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 0913394b365255f6af63..f1680495210987d57ba6 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -818,8 +818,8 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
__DRI_IMAGE_ATTRIB_MODIFIER_LOWER,
_lo);
   if (query) {
- modifier = (uint64_t) mod_hi << 32;
- modifier |= (uint64_t) (mod_lo & 0x);
+ modifier = ((uint64_t) mod_hi) << 32;
+ modifier |= ((uint64_t) mod_lo) & 0x;
   }
}
 
@@ -1192,8 +1192,8 @@ dmabuf_handle_modifier(void *data, struct 
zwp_linux_dmabuf_v1 *dmabuf,
dri2_dpy->formats |= (1 << visual_idx);
 
mod = u_vector_add(_dpy->wl_modifiers[visual_idx]);
-   *mod = (uint64_t) modifier_hi << 32;
-   *mod |= (uint64_t) (modifier_lo & 0x);
+   *mod = ((uint64_t) modifier_hi) << 32u;
+   *mod |= ((uint64_t) modifier_lo) & 0x;
 }
 
 static const struct zwp_linux_dmabuf_v1_listener dmabuf_listener = {
-- 
Cheers,
  Eric

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Re: [Mesa-dev] [PATCH v5 1/2] intel/ppgtt: memory address alignment

[Sergii Romantsov]

And also thanks to you :).

On Thu, Aug 16, 2018 at 4:16 PM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> Both patches pushed to master.
>
> Thanks!
>
> -
> Lionel
>
>
> On 15/08/18 16:03, Lionel Landwerlin wrote:
>
>> On 15/08/18 12:23, Sergii Romantsov wrote:
>>
>>> Kernel (for ppgtt) requires memory address to be
>>> aligned to page size (4096).
>>>
>>> -v2: added marking that also fixes initial commit 01058a552294.
>>> -v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
>>> instead of alignment of offsets (Chris Wilson).
>>> -v4: changes related to PAGE_SIZE moved to separate commit
>>> -v5: restored alignment to page-size for 0-size.
>>>
>>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997
>>> Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT
>>> systems.)
>>> Fixes: 01058a552294 (i965: Add virtual memory allocator infrastructure
>>> to brw_bufmgr.)
>>> Signed-off-by: Sergii Romantsov 
>>>
>>
>> CI seems happy this time :
>>
>> Reviewed-by: Lionel Landwerlin 
>>
>> ---
>>>   src/mesa/drivers/dri/i965/brw_bufmgr.c | 7 +++
>>>   1 file changed, 3 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
>>> b/src/mesa/drivers/dri/i965/brw_bufmgr.c
>>> index 09d45e3..19e2d14 100644
>>> --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
>>> +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
>>> @@ -496,7 +496,6 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
>>> uint32_t stride)
>>>   {
>>>  struct brw_bo *bo;
>>> -   unsigned int page_size = getpagesize();
>>>  int ret;
>>>  struct bo_cache_bucket *bucket;
>>>  bool alloc_from_cache;
>>> @@ -522,12 +521,12 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
>>>   * allocation up.
>>>   */
>>>  if (bucket == NULL) {
>>> -  bo_size = size;
>>> -  if (bo_size < page_size)
>>> - bo_size = page_size;
>>> +  unsigned int page_size = getpagesize();
>>> +  bo_size = size == 0 ? page_size : ALIGN(size, page_size);
>>>  } else {
>>> bo_size = bucket->size;
>>>  }
>>> +   assert(bo_size);
>>>mtx_lock(>lock);
>>>  /* Get a buffer out of the cache if available */
>>>
>>
>>
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>
>
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-- 
Sergii Romantsov
GlobalLogic Inc.
www.globallogic.com
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