Re: [Mesa-dev] [PATCH] vulkan: Disable randr lease for libxcb < 1.13

[Stuart Young]

Hi All,

Can we get some feedback on this patch please?

At the moment, we can't compile vulkan using libxcb < 1.13 due to the use
of the RandR lease mechanism. Dave Airlie (cc'd) did some work previously
to allow things to be compiled with libxcb 1.11/1.12, mainly by ifdef'ing
certain code with HAVE_DRI3_MODIFIERS so that it would compile, but without
the extra features that xcb 1.13+ provides. See commit 7aeef2d4efdc809a698e
"dri3: allow building against older xcb (v3)" for that.

The patch (originally provided by Maxime) appears to solve the new build
issue, and in much the same way as Dave Airlie did with his previous patch.

Note: If we "must have" xcb 1.13, then that's fine. But if that is the
case, then we need to update mesa's build deps so that this is explicit
(ie: effectively reverting Dave Airlie's commits on the issue).


On Tue, 25 Sep 2018 at 02:04, Eric Engestrom 
wrote:

> +Cc Keith, Jason & Daniel, who know this code best.
>
> On Monday, 2018-09-24 08:46:22 +1000, Stuart Young wrote:
> > From: Maxime 
> >
> > Since the Randr lease code was added, compiling against libxcb 1.12 no
> > longer works.
> >
> > CC: mesa-sta...@lists.freedesktop.org
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108024
> > Fixes: 7ab1fffcd2a504024b16e408de329f7a94553ecc
>
> Thanks for the `Fixes:` tag, it's really useful :)
> We usually also add the commit title as well, to help humans know what it's
> about without having to look it up (makes no difference to scripts though):
> Fixes: 7ab1fffcd2a504024b16 "vulkan: Add EXT_acquire_xlib_display [v5]"
>
> > Tested-By: Maxime 
> >
> > ---
> >  src/vulkan/wsi/wsi_common_display.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/src/vulkan/wsi/wsi_common_display.c
> b/src/vulkan/wsi/wsi_common_display.c
> > index e99b0465ec..e23d2983c9 100644
> > --- a/src/vulkan/wsi/wsi_common_display.c
> > +++ b/src/vulkan/wsi/wsi_common_display.c
> > @@ -2304,6 +2304,7 @@ wsi_acquire_xlib_display(VkPhysicalDevice
> physical_device,
> > if (!crtc)
> >return VK_ERROR_INITIALIZATION_FAILED;
> >
> > +#ifdef HAVE_DRI3_MODIFIERS
> > xcb_randr_lease_t lease = xcb_generate_id(connection);
> > xcb_randr_create_lease_cookie_t cl_c =
> >xcb_randr_create_lease(connection, root, lease, 1, 1,
> > @@ -2324,6 +2325,7 @@ wsi_acquire_xlib_display(VkPhysicalDevice
> physical_device,
> >return VK_ERROR_INITIALIZATION_FAILED;
> >
> > wsi->fd = fd;
> > +#endif
> >
> > return VK_SUCCESS;
> >  }
> > --
> > 2.11.0
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>


-- 
Stuart Young (aka Cefiar)
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[Mesa-dev] [Bug 108082] warning: unknown warning option '-Wno-format-truncation' [-Wunknown-warning-option]

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=108082

Bug ID: 108082
   Summary: warning: unknown warning option
'-Wno-format-truncation' [-Wunknown-warning-option]
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: All
Status: NEW
  Keywords: bisected, regression
  Severity: normal
  Priority: medium
 Component: Other
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: v...@freedesktop.org
QA Contact: mesa-dev@lists.freedesktop.org
CC: emil.l.veli...@gmail.com, fdo-b...@engestrom.ch

These warning messages are appearing with clang.

warning: unknown warning option '-Wno-format-truncation'
[-Wunknown-warning-option]

Introduced with this commit.

commit 97ae5a858d2a2da9144ea9793b67b360a3a7c5fa
Author: Eric Engestrom 
Date:   Fri Sep 21 11:42:38 2018 +0100

meson+autotools: get rid of spammy GCC warning -Wformat-truncation

That warning fires every time a string function takes an argument that
could possibly be longer than its max output, which triggers all over
the place, especially when working with file paths ("what if every file
path is MAX_PATH long?" is what GCC is saying, which is really annoying
when we *know* that "/dev/dri/cardN" is not gonna be 4096 char long and
it's safe to store it in a 32-char array).

Anyway, we either add a ton of dead code all over the place to make GCC
happy, or we get rid of its spam. I chose the latter.

Signed-off-by: Eric Engestrom 
Reviewed-by: Emil Velikov 

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[Mesa-dev] Where to send Crucible patches?

[Caio Marcelo de Oliveira Filho]

Hi,

I was a bit unsure about where to send Crucible(*) patches, neither
README or HACKING file has the answer.  In #dri-devel channel people
were also not sure.  I've ended up sending to piglit mailing list, but
found out later some potential reviewers don't subscribe to it.

Where should new contributions go?

- pig...@lists.freedesktop.org
- mesa-dev@lists.freedesktop.org
- merge requests in GitLab
- some other place


Thanks,
Caio

(*): https://gitlab.freedesktop.org/mesa/crucible
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Re: [Mesa-dev] [PATCH mesa 4/6] vulkan/wsi/display: add comment

[Keith Packard]

Eric Engestrom  writes:

> -   struct list_head connectors;
> +   struct list_head connectors; /* list of all discovered 
> connectors */

Yeah, definitely not the list of all connectors.

Reviewed-by: Keith Packard 

-- 
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Re: [Mesa-dev] [PATCH mesa 3/6] vulkan/wsi/display: pass the plane's modifiers to the image

[Keith Packard]

Eric Engestrom  writes:

> Signed-off-by: Eric Engestrom 

(I'll have to let someone familiar with the formats and modifiers stuff
review this one; I'm not comfortable with that at all).

-- 
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Re: [Mesa-dev] [PATCH mesa 2/6] vulkan/wsi/display: also select a plane when selecting a crtc

[Keith Packard]

Eric Engestrom  writes:

> +   /* if there's a plane is active on the connector's crtc, pick it */
> +   for (size_t i = 0; i < plane_res->count_planes; i++) {
> +  drmModePlane *plane = drmModeGetPlane(wsi->fd, plane_res->planes[i]);
> +  if (!plane)
> + continue;

I think you can do these three operations in a single walk of the
planes; it's obviously not performance critical, but I think squashing
them together would reduce the amount of duplicate code and make it
at least shorter to read.

Just find three plane ids -- one in use on the crtc, one compatible with
the crtc and one idle one, then select the one to use after the loop is over.


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[Mesa-dev] [PATCH 8/9] i965/surface_state: Use the ASTC shadow_mt if present

[Nanley Chery]

When sampling from an ASTC texture in a shader, make sure to use the
miptree which has had the gen9 void-extent workaround applied to it.
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index e214fae140b..cad0f7faba1 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -573,6 +573,9 @@ static void brw_update_texture_surface(struct gl_context 
*ctx,
  assert(mt->shadow_mt && !mt->shadow_needs_update);
  mt = mt->shadow_mt;
  format = ISL_FORMAT_R8_UINT;
+  } else if (intel_miptree_has_astc_shadow(mt)) {
+ assert(!mt->shadow_needs_update);
+ mt = mt->shadow_mt;
   }
 
   const int surf_index = surf_offset - >wm.base.surf_offset[0];
-- 
2.19.0

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[Mesa-dev] [PATCH 4/9] intel/blorp_blit: Fix ptr deref in convert_to_uncompressed

[Nanley Chery]

Don't access the pointers x and y if they're NULL. Nothing hits this
path currently.
---
 src/intel/blorp/blorp_blit.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index ae3e3c50930..7c4e569e44c 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2456,15 +2456,18 @@ blorp_surf_convert_to_uncompressed(const struct 
isl_device *isl_dev,
 */
blorp_surf_convert_to_single_slice(isl_dev, info);
 
-   if (width && height) {
 #ifndef NDEBUG
+   if (width && height && x && y) {
   uint32_t right_edge_px = info->tile_x_sa + *x + *width;
   uint32_t bottom_edge_px = info->tile_y_sa + *y + *height;
   assert(*width % fmtl->bw == 0 ||
  right_edge_px == info->surf.logical_level0_px.width);
   assert(*height % fmtl->bh == 0 ||
  bottom_edge_px == info->surf.logical_level0_px.height);
+   }
 #endif
+
+   if (width && height) {
   *width = DIV_ROUND_UP(*width, fmtl->bw);
   *height = DIV_ROUND_UP(*height, fmtl->bh);
}
-- 
2.19.0

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[Mesa-dev] [PATCH 2/9] i965/miptree: Allocate a shadow_mt for an ASTC WA

[Nanley Chery]

shadow_mt will hold a miptree with ASTC LDR void extent blocks that are
modified to workaround a sampler bug.
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 25 +++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  1 +
 2 files changed, 26 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 332c5d88f58..5e99b563102 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -354,6 +354,19 @@ needs_separate_stencil(const struct brw_context *brw,
   intel_miptree_supports_hiz(brw, mt);
 }
 
+/* Determine if we may run into a problematic void-extent block for our sampler
+ * (see WA #0300). This isn't 100% accurate because we don't actually inspect
+ * the blocks.
+ */
+static bool
+may_need_astc_shadow(const struct gen_device_info *devinfo,
+ mesa_format format)
+{
+   return devinfo->gen == 9 && !gen_device_info_is_9lp(devinfo) &&
+  _mesa_get_format_layout(format) == MESA_FORMAT_LAYOUT_ASTC &&
+  _mesa_get_format_color_encoding(format) == GL_LINEAR;
+}
+
 /**
  * Choose the aux usage for this miptree.  This function must be called fairly
  * late in the miptree create process after we have a tiling.
@@ -719,6 +732,18 @@ miptree_create(struct brw_context *brw,
   }
}
 
+   if (may_need_astc_shadow(devinfo, format)) {
+  mt->shadow_mt =
+ make_surface(brw, target, format, first_level, last_level,
+  width0, height0, depth0, num_samples,
+  ISL_TILING_Y0_BIT, mt_surf_usage(format),
+  BO_ALLOC_BUSY, 0, NULL);
+  if (mt->shadow_mt == NULL) {
+ intel_miptree_release();
+ return NULL;
+  }
+   }
+
mt->etc_format = (_mesa_is_format_color_format(format) && mt_fmt != format) 
?
 format : MESA_FORMAT_NONE;
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index d75c93b8b42..b22514de386 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -301,6 +301,7 @@ struct intel_mipmap_tree
 *
 * This miptree may be used for:
 * - Stencil texturing (pre-BDW) as required by GL_ARB_stencil_texturing.
+* - Correctly sampling from ASTC LDR blocks on big-core gen9 platforms.
 */
struct intel_mipmap_tree *shadow_mt;
bool shadow_needs_update;
-- 
2.19.0

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[Mesa-dev] [PATCH 6/9] i965/blorp: Drop tmp_surfs from surf_for_miptree

[Nanley Chery]

We've been using intel_mipmap_tree::surf instead. The tmp_surfs param
hasn't been used since commit: bf24c3539e4b6989512968cae12da2f88d2c53e9
("i965/miptree: Clean-up unused").
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 36 +--
 1 file changed, 12 insertions(+), 24 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index ad747e0766e..2ebd35ae49f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -125,8 +125,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
enum isl_aux_usage aux_usage,
bool is_render_target,
unsigned *level,
-   unsigned start_layer, unsigned num_layers,
-   struct isl_surf tmp_surfs[1])
+   unsigned start_layer, unsigned num_layers)
 {
const struct gen_device_info *devinfo = >screen->devinfo;
 
@@ -406,12 +405,11 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
 dst_aux_usage, dst_clear_supported);
 
-   struct isl_surf tmp_surfs[2];
struct blorp_surf src_surf, dst_surf;
blorp_surf_for_miptree(brw, _surf, src_mt, src_aux_usage, false,
-  _level, src_layer, 1, _surfs[0]);
+  _level, src_layer, 1);
blorp_surf_for_miptree(brw, _surf, dst_mt, dst_aux_usage, true,
-  _level, dst_layer, 1, _surfs[1]);
+  _level, dst_layer, 1);
 
struct isl_swizzle src_isl_swizzle = {
   .r = swizzle_to_scs(GET_SWZ(src_swizzle, 0)),
@@ -497,12 +495,11 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
 dst_aux_usage, dst_clear_supported);
 
-   struct isl_surf tmp_surfs[2];
struct blorp_surf src_surf, dst_surf;
blorp_surf_for_miptree(brw, _surf, src_mt, src_aux_usage, false,
-  _level, src_layer, 1, _surfs[0]);
+  _level, src_layer, 1);
blorp_surf_for_miptree(brw, _surf, dst_mt, dst_aux_usage, true,
-  _level, dst_layer, 1, _surfs[1]);
+  _level, dst_layer, 1);
 
/* The hardware seems to have issues with having a two different format
 * views of the same texture in the sampler cache at the same time.  It's
@@ -1300,10 +1297,9 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   irb->mt, irb->mt_level, irb->mt_layer, num_layers);
 
   /* We can't setup the blorp_surf until we've allocated the MCS above */
-  struct isl_surf isl_tmp[2];
   struct blorp_surf surf;
   blorp_surf_for_miptree(brw, , irb->mt, irb->mt->aux_usage, true,
- , irb->mt_layer, num_layers, isl_tmp);
+ , irb->mt_layer, num_layers);
 
   /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
*
@@ -1346,10 +1342,9 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   intel_miptree_prepare_render(brw, irb->mt, level, irb->mt_layer,
num_layers, aux_usage);
 
-  struct isl_surf isl_tmp[2];
   struct blorp_surf surf;
   blorp_surf_for_miptree(brw, , irb->mt, aux_usage, true,
- , irb->mt_layer, num_layers, isl_tmp);
+ , irb->mt_layer, num_layers);
 
   union isl_color_value clear_color;
   memcpy(clear_color.f32, ctx->Color.ClearColor.f, sizeof(float) * 4);
@@ -1444,7 +1439,6 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
   return;
 
uint32_t level, start_layer, num_layers;
-   struct isl_surf isl_tmp[4];
struct blorp_surf depth_surf, stencil_surf;
 
struct intel_mipmap_tree *depth_mt = NULL;
@@ -1461,8 +1455,7 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
 
   unsigned depth_level = level;
   blorp_surf_for_miptree(brw, _surf, depth_mt, depth_mt->aux_usage,
- true, _level, start_layer, num_layers,
- _tmp[0]);
+ true, _level, start_layer, num_layers);
   assert(depth_level == level);
}
 
@@ -1491,8 +1484,7 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
   unsigned stencil_level = level;
   blorp_surf_for_miptree(brw, _surf, stencil_mt,
  ISL_AUX_USAGE_NONE, true,
- _level, start_layer, num_layers,
- _tmp[2]);
+ _level, start_layer, num_layers);
}
 
assert((mask & BUFFER_BIT_DEPTH) || stencil_mask);
@@ -1527,11 +1519,9 @@ brw_blorp_resolve_color(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
 
 

[Mesa-dev] [PATCH 3/9] i965/miptree: Track the staleness of the ASTC shadow

[Nanley Chery]

Track whether or not the ASTC shadow miptree will need to be updated
prior to sampling.
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 -
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 ++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 5e99b563102..090e20e1d70 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2451,8 +2451,11 @@ intel_miptree_finish_write(struct brw_context *brw,
 
switch (mt->aux_usage) {
case ISL_AUX_USAGE_NONE:
-  if (mt->format == MESA_FORMAT_S_UINT8 && devinfo->gen <= 7)
+  if (mt->format == MESA_FORMAT_S_UINT8 && devinfo->gen <= 7) {
  mt->shadow_needs_update = true;
+  } else if (intel_miptree_has_astc_shadow(mt)) {
+ mt->shadow_needs_update = true;
+  }
   break;
 
case ISL_AUX_USAGE_MCS:
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index b22514de386..3ae0117d68f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -726,6 +726,12 @@ intel_miptree_blt_pitch(struct intel_mipmap_tree *mt)
return pitch;
 }
 
+static inline bool
+intel_miptree_has_astc_shadow(const struct intel_mipmap_tree *mt)
+{
+   return _mesa_get_format_layout(mt->format) == MESA_FORMAT_LAYOUT_ASTC &&
+   mt->shadow_mt != NULL;
+}
 #ifdef __cplusplus
 }
 #endif
-- 
2.19.0

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[Mesa-dev] [PATCH 9/9] i965/tex_image: Drop intelCompressedTexSubImage

[Nanley Chery]

Effectively revert 710b1d2e665ed654fb8d52b146fa22469e1dc3a7.

This function was created to perform the ASTC void-extent workaround.
Now that the workaround is handled prior to sampling, this function is
no longer necessary.
---
 src/mesa/drivers/dri/i965/intel_tex_image.c | 87 -
 1 file changed, 87 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c 
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 9775f788788..31ff08217ac 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -843,98 +843,11 @@ intel_get_tex_sub_image(struct gl_context *ctx,
DBG("%s - DONE\n", __func__);
 }
 
-static void
-flush_astc_denorms(struct gl_context *ctx, GLuint dims,
-   struct gl_texture_image *texImage,
-   GLint xoffset, GLint yoffset, GLint zoffset,
-   GLsizei width, GLsizei height, GLsizei depth)
-{
-   struct compressed_pixelstore store;
-   _mesa_compute_compressed_pixelstore(dims, texImage->TexFormat,
-   width, height, depth,
-   >Unpack, );
-
-   for (int slice = 0; slice < store.CopySlices; slice++) {
-
-  /* Map dest texture buffer */
-  GLubyte *dstMap;
-  GLint dstRowStride;
-  ctx->Driver.MapTextureImage(ctx, texImage, slice + zoffset,
-  xoffset, yoffset, width, height,
-  GL_MAP_READ_BIT | GL_MAP_WRITE_BIT,
-  , );
-  if (!dstMap)
- continue;
-
-  for (int i = 0; i < store.CopyRowsPerSlice; i++) {
-
- /* An ASTC block is stored in little endian mode. The byte that
-  * contains bits 0..7 is stored at the lower address in memory.
-  */
- struct astc_void_extent {
-uint16_t header : 12;
-uint16_t dontcare[3];
-uint16_t R;
-uint16_t G;
-uint16_t B;
-uint16_t A;
- } *blocks = (struct astc_void_extent*) dstMap;
-
- /* Iterate over every copied block in the row */
- for (int j = 0; j < store.CopyBytesPerRow / 16; j++) {
-
-/* Check if the header matches that of an LDR void-extent block */
-if (blocks[j].header == 0xDFC) {
-
-   /* Flush UNORM16 values that would be denormalized */
-   if (blocks[j].A < 4) blocks[j].A = 0;
-   if (blocks[j].B < 4) blocks[j].B = 0;
-   if (blocks[j].G < 4) blocks[j].G = 0;
-   if (blocks[j].R < 4) blocks[j].R = 0;
-}
- }
-
- dstMap += dstRowStride;
-  }
-
-  ctx->Driver.UnmapTextureImage(ctx, texImage, slice + zoffset);
-   }
-}
-
-
-static void
-intelCompressedTexSubImage(struct gl_context *ctx, GLuint dims,
-struct gl_texture_image *texImage,
-GLint xoffset, GLint yoffset, GLint zoffset,
-GLsizei width, GLsizei height, GLsizei depth,
-GLenum format,
-GLsizei imageSize, const GLvoid *data)
-{
-   /* Upload the compressed data blocks */
-   _mesa_store_compressed_texsubimage(ctx, dims, texImage,
-  xoffset, yoffset, zoffset,
-  width, height, depth,
-  format, imageSize, data);
-
-   /* Fix up copied ASTC blocks if necessary */
-   GLenum gl_format = _mesa_compressed_format_to_glenum(ctx,
-texImage->TexFormat);
-   bool is_linear_astc = _mesa_is_astc_format(gl_format) &&
-!_mesa_is_srgb_format(gl_format);
-   struct brw_context *brw = (struct brw_context*) ctx;
-   const struct gen_device_info *devinfo = >screen->devinfo;
-   if (devinfo->gen == 9 && !gen_device_info_is_9lp(devinfo) && is_linear_astc)
-  flush_astc_denorms(ctx, dims, texImage,
- xoffset, yoffset, zoffset,
- width, height, depth);
-}
-
 void
 intelInitTextureImageFuncs(struct dd_function_table *functions)
 {
functions->TexImage = intelTexImage;
functions->TexSubImage = intelTexSubImage;
-   functions->CompressedTexSubImage = intelCompressedTexSubImage;
functions->EGLImageTargetTexture2D = intel_image_target_texture_2d;
functions->BindRenderbufferTexImage = intel_bind_renderbuffer_tex_image;
functions->GetTexSubImage = intel_get_tex_sub_image;
-- 
2.19.0

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[Mesa-dev] [PATCH 0/9] i965: Re-implement the gen9 void-extent ASTC WA with BLORP

[Nanley Chery]

The current workaround has two issues. It causes significant slow-downs [1] in
application startup times and uses the modified ASTC blocks for non-sampling
operations. This can result in incorrect texture downloads.

This series addresses the latter issue by keeping two copies of an ASTC
miptree: one that's been modified for the sampler bug (the shadow) and another
that hasn't (the main). The main copy is used for pixel transfer operations and
the shadow is used for sampling within a shader. The former issue is addressed
by exchanging multiple GTT-mapped memory accesses at texture upload time with a
render engine read and write at sampling time.

At the moment, I don't have any empirical data on the performance
implications nor on the bug fixes. I'm trying to get my hands on one of
the affected benchmarks. This series does pass our CI system.

1. 17 seconds were saved by avoiding it in commit:
   3e56e4642fb5875b3f5c4eb34798ba9f3d827705

Nanley Chery (9):
  i965: Rename intel_mipmap_tree::r8stencil_* -> ::shadow_*
  i965/miptree: Allocate a shadow_mt for an ASTC WA
  i965/miptree: Track the staleness of the ASTC shadow
  intel/blorp_blit: Fix ptr deref in convert_to_uncompressed
  intel/blorp_blit: Add blorp_copy_astc_wa
  i965/blorp: Drop tmp_surfs from surf_for_miptree
  i965: Do a WA blit between ASTC main and shadow
  i965/surface_state: Use the ASTC shadow_mt if present
  i965/tex_image: Drop intelCompressedTexSubImage

 src/intel/blorp/blorp.h   |   6 +
 src/intel/blorp/blorp_blit.c  | 158 +-
 src/intel/blorp/blorp_priv.h  |   1 +
 src/mesa/drivers/dri/i965/brw_blorp.c |  56 ---
 src/mesa/drivers/dri/i965/brw_blorp.h |   6 +
 src/mesa/drivers/dri/i965/brw_draw.c  |  16 ++
 .../drivers/dri/i965/brw_wm_surface_state.c   |  11 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  46 -
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  21 ++-
 src/mesa/drivers/dri/i965/intel_tex_image.c   |  87 --
 10 files changed, 276 insertions(+), 132 deletions(-)

-- 
2.19.0

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[Mesa-dev] [PATCH 1/9] i965: Rename intel_mipmap_tree::r8stencil_* -> ::shadow_*

[Nanley Chery]

Use more generic field names. We'll reuse these fields for a workaround
with ASTC miptrees.
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  8 
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 16 
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h| 14 +++---
 3 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 8d21cf5fa70..e214fae140b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -563,15 +563,15 @@ static void brw_update_texture_surface(struct gl_context 
*ctx,
 
   if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) 
{
  if (devinfo->gen <= 7) {
-assert(mt->r8stencil_mt && 
!mt->stencil_mt->r8stencil_needs_update);
-mt = mt->r8stencil_mt;
+assert(mt->shadow_mt && !mt->stencil_mt->shadow_needs_update);
+mt = mt->shadow_mt;
  } else {
 mt = mt->stencil_mt;
  }
  format = ISL_FORMAT_R8_UINT;
   } else if (devinfo->gen <= 7 && mt->format == MESA_FORMAT_S_UINT8) {
- assert(mt->r8stencil_mt && !mt->r8stencil_needs_update);
- mt = mt->r8stencil_mt;
+ assert(mt->shadow_mt && !mt->shadow_needs_update);
+ mt = mt->shadow_mt;
  format = ISL_FORMAT_R8_UINT;
   }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e32641f4098..332c5d88f58 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1214,7 +1214,7 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
 
   brw_bo_unreference((*mt)->bo);
   intel_miptree_release(&(*mt)->stencil_mt);
-  intel_miptree_release(&(*mt)->r8stencil_mt);
+  intel_miptree_release(&(*mt)->shadow_mt);
   intel_miptree_aux_buffer_free((*mt)->aux_buf);
   free_aux_state_map((*mt)->aux_state);
 
@@ -2427,7 +2427,7 @@ intel_miptree_finish_write(struct brw_context *brw,
switch (mt->aux_usage) {
case ISL_AUX_USAGE_NONE:
   if (mt->format == MESA_FORMAT_S_UINT8 && devinfo->gen <= 7)
- mt->r8stencil_needs_update = true;
+ mt->shadow_needs_update = true;
   break;
 
case ISL_AUX_USAGE_MCS:
@@ -2933,9 +2933,9 @@ intel_update_r8stencil(struct brw_context *brw,
 
assert(src->surf.size_B > 0);
 
-   if (!mt->r8stencil_mt) {
+   if (!mt->shadow_mt) {
   assert(devinfo->gen > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
-  mt->r8stencil_mt = make_surface(
+  mt->shadow_mt = make_surface(
 brw,
 src->target,
 MESA_FORMAT_R_UINT8,
@@ -2949,13 +2949,13 @@ intel_update_r8stencil(struct brw_context *brw,
 ISL_TILING_Y0_BIT,
 ISL_SURF_USAGE_TEXTURE_BIT,
 BO_ALLOC_BUSY, 0, NULL);
-  assert(mt->r8stencil_mt);
+  assert(mt->shadow_mt);
}
 
-   if (src->r8stencil_needs_update == false)
+   if (src->shadow_needs_update == false)
   return;
 
-   struct intel_mipmap_tree *dst = mt->r8stencil_mt;
+   struct intel_mipmap_tree *dst = mt->shadow_mt;
 
for (int level = src->first_level; level <= src->last_level; level++) {
   const unsigned depth = src->surf.dim == ISL_SURF_DIM_3D ?
@@ -2975,7 +2975,7 @@ intel_update_r8stencil(struct brw_context *brw,
}
 
brw_cache_flush_for_read(brw, dst->bo);
-   src->r8stencil_needs_update = false;
+   src->shadow_needs_update = false;
 }
 
 static void *
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 708757c47b8..d75c93b8b42 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -294,16 +294,16 @@ struct intel_mipmap_tree
struct intel_mipmap_tree *stencil_mt;
 
/**
-* \brief Stencil texturing miptree for sampling from a stencil texture
+* \brief Shadow miptree for sampling when the main isn't supported by HW.
 *
-* Some hardware doesn't support sampling from the stencil texture as
-* required by the GL_ARB_stencil_texturing extenion. To workaround this we
-* blit the texture into a new texture that can be sampled.
+* To workaround various sampler bugs and limitations, we blit the main
+* texture into a new texture that can be sampled.
 *
-* \see intel_update_r8stencil()
+* This miptree may be used for:
+* - Stencil texturing (pre-BDW) as required by GL_ARB_stencil_texturing.
 */
-   struct intel_mipmap_tree *r8stencil_mt;
-   bool r8stencil_needs_update;
+   struct intel_mipmap_tree *shadow_mt;
+   bool shadow_needs_update;
 
/**
 * \brief CCS, MCS, or HiZ auxiliary buffer.
-- 
2.19.0

[Mesa-dev] [PATCH 7/9] i965: Do a WA blit between ASTC main and shadow

[Nanley Chery]

Perform a workaround blit prior to sampling from the ASTC miptree.
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 20 
 src/mesa/drivers/dri/i965/brw_blorp.h |  6 ++
 src/mesa/drivers/dri/i965/brw_draw.c  | 16 
 3 files changed, 42 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 2ebd35ae49f..6fc0b441cd0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -266,6 +266,26 @@ swizzle_to_scs(GLenum swizzle)
return (enum isl_channel_select)((swizzle + 4) & 7);
 }
 
+void
+brw_blorp_copy_astc_wa(struct brw_context *brw,
+   struct intel_mipmap_tree *src_mt,
+   struct intel_mipmap_tree *dst_mt,
+   unsigned level, unsigned layer)
+{
+   struct blorp_surf src_surf, dst_surf;
+   unsigned src_level = level;
+   unsigned dst_level = level;
+   blorp_surf_for_miptree(brw, _surf, src_mt, ISL_AUX_USAGE_NONE, false,
+  _level, layer, 1);
+   blorp_surf_for_miptree(brw, _surf, dst_mt, ISL_AUX_USAGE_NONE, true,
+  _level, layer, 1);
+
+   struct blorp_batch batch;
+   blorp_batch_init(>blorp, , brw, 0);
+   blorp_copy_astc_wa(, _surf, _surf, dst_level, layer);
+   blorp_batch_finish();
+}
+
 /**
  * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
  * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 551e1fcdcba..ba0d5679a04 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -34,6 +34,12 @@ extern "C" {
 
 void brw_blorp_init(struct brw_context *brw);
 
+void
+brw_blorp_copy_astc_wa(struct brw_context *brw,
+   struct intel_mipmap_tree *src_mt,
+   struct intel_mipmap_tree *dst_mt,
+   unsigned level, unsigned layer);
+
 void
 brw_blorp_blit_miptrees(struct brw_context *brw,
 struct intel_mipmap_tree *src_mt,
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 8536c040109..772f8f8fad7 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -558,6 +558,22 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
rendering,
   if (tex_obj->base.StencilSampling ||
   tex_obj->mt->format == MESA_FORMAT_S_UINT8) {
  intel_update_r8stencil(brw, tex_obj->mt);
+  } else if (intel_miptree_has_astc_shadow(tex_obj->mt) &&
+ tex_obj->mt->shadow_needs_update) {
+ struct intel_mipmap_tree *src = tex_obj->mt;
+ struct intel_mipmap_tree *dst = src->shadow_mt;
+
+ for (int level = src->first_level; level <= src->last_level; level++) 
{
+const unsigned depth = src->surf.dim == ISL_SURF_DIM_3D ?
+   minify(src->surf.logical_level0_px.depth, level) :
+   src->surf.logical_level0_px.array_len;
+
+for (unsigned layer = 0; layer < depth; layer++) {
+   brw_blorp_copy_astc_wa(brw, src, dst, level, layer);
+}
+ }
+ brw_cache_flush_for_read(brw, dst->bo);
+ src->shadow_needs_update = false;
   }
}
 
-- 
2.19.0

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[Mesa-dev] [PATCH 5/9] intel/blorp_blit: Add blorp_copy_astc_wa

[Nanley Chery]

Add a function which copies blocks from one ASTC surface to another,
patching them up as necessary.
---
 src/intel/blorp/blorp.h  |   6 ++
 src/intel/blorp/blorp_blit.c | 153 +++
 src/intel/blorp/blorp_priv.h |   1 +
 3 files changed, 160 insertions(+)

diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index ee343a4a6bb..67df3ff26b0 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -152,6 +152,12 @@ blorp_copy(struct blorp_batch *batch,
uint32_t dst_x, uint32_t dst_y,
uint32_t src_width, uint32_t src_height);
 
+void
+blorp_copy_astc_wa(struct blorp_batch *batch,
+   const struct blorp_surf *src_surf,
+   const struct blorp_surf *dst_surf,
+   unsigned src_level, unsigned src_layer);
+
 void
 blorp_buffer_copy(struct blorp_batch *batch,
   struct blorp_address src,
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 7c4e569e44c..442f7227c0a 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2658,6 +2658,159 @@ blorp_copy(struct blorp_batch *batch,
do_blorp_blit(batch, , _prog_key, );
 }
 
+/* Try to add a pixel shader kernel for the ASTC WA to params. */
+static bool
+get_copy_astc_wa_kernel(struct blorp_context *blorp,
+struct blorp_params *params)
+{
+   /* Use the shader in our cache if it already exists. */
+   enum blorp_shader_type astc_wa_key = BLORP_SHADER_TYPE_ASTC_VOID_EXTENT_WA;
+   if (blorp->lookup_shader(blorp, _wa_key, sizeof(astc_wa_key),
+>wm_prog_kernel, >wm_prog_data))
+  return true;
+
+   /* Otherwise, build the kernel now. */
+   void *mem_ctx = ralloc_context(NULL);
+
+   const unsigned *program;
+   struct brw_wm_prog_data prog_data;
+
+   nir_builder b;
+   nir_builder_init_simple_shader(, mem_ctx, MESA_SHADER_FRAGMENT, NULL);
+   b.shader->info.name =
+  ralloc_strdup(b.shader, "BLORP-ASTC-void-extent-wa-copy");
+
+   /* Input: Perform a texelfetch on the 2D RGBA32UI texture */
+   nir_ssa_def *frag_coord_u = nir_f2i32(, blorp_nir_frag_coord());
+   nir_ssa_def *pos = nir_vec2(, nir_channel(, frag_coord_u, 0),
+   nir_channel(, frag_coord_u, 1));
+   nir_tex_instr *tex = nir_tex_instr_create(b.shader, 2);
+   nir_ssa_dest_init(>instr, >dest, 4, 32, NULL);
+
+   tex->texture_index = 0;
+   tex->sampler_index = 0;
+
+   tex->op = nir_texop_txf;
+   tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
+   tex->dest_type = nir_type_uint;
+   tex->src[0].src_type = nir_tex_src_coord;
+   tex->src[0].src = nir_src_for_ssa(pos);
+   tex->coord_components = 2;
+   tex->src[1].src_type = nir_tex_src_lod;
+   tex->src[1].src = nir_src_for_ssa(nir_imm_int(, 0));
+
+   nir_builder_instr_insert(, >instr);
+
+   /* Output: Declare the fragment color */
+   nir_variable *frag_color =
+  nir_variable_create(b.shader, nir_var_shader_out,
+  glsl_uvec4_type(), "gl_FragColor");
+   frag_color->data.location = FRAG_RESULT_COLOR;
+
+   /* Main: Patch up the fetched block as needed.
+*
+* An ASTC block is stored in little endian mode. The byte that contains
+* bits 0..7 is stored at the lower address in memory.
+*
+* The low 12 bits contain the header which can indicate an LDR void-extent
+* block.
+*
+* If this is such a block, the high 64 bits contain 4 UNORM16s which must
+* be set to 0 if their values are less than 4.
+*
+* The PRMs describe formats as being stored in little-endian pixel order.
+* Since we're viewing this texture as an RGBA32_UINT, this means R will
+* contain bits 31:0 of the ASTC block, G will contain 63:32, and so on.
+*/
+
+   /* Check if the header indicates an LDR void-extent block */
+   nir_ssa_def *header = nir_iand(, nir_channel(, >dest.ssa, 0),
+  nir_imm_int(, 0xFFF));
+   nir_ssa_def *ve_header = nir_imm_int(, 0xDFC);
+   nir_if *if_stmt = nir_if_create(b.shader);
+   if_stmt->condition = nir_src_for_ssa(nir_ieq(, header, ve_header));
+   nir_cf_node_insert(b.cursor, _stmt->cf_node);
+   b.cursor = nir_after_cf_list(_stmt->then_list);
+   
+   /* Go from AB32 to ABGR16 */
+   nir_ssa_def *AB32 = nir_vec2(, nir_channel(, >dest.ssa, 3),
+nir_channel(, >dest.ssa, 2));
+   nir_ssa_def *ABGR16 = nir_format_bitcast_uvec_unmasked(, AB32, 32, 16);
+
+
+   /* Set the channels to 0 if less than 4. */
+   nir_ssa_def *chan_ge_4 = nir_ige(, ABGR16, nir_imm_ivec4(, 4, 4, 4, 4));
+   nir_ssa_def *ABGR16_mod = nir_iand(, ABGR16, chan_ge_4);
+
+
+   /* Store the modified block */
+   nir_ssa_def *AB32_mod =
+  nir_format_bitcast_uvec_unmasked(, ABGR16_mod, 16, 32);
+   nir_ssa_def *color = nir_vec4(, nir_channel(, >dest.ssa, 0),
+ nir_channel(, >dest.ssa, 1),
+ 

Re: [Mesa-dev] [PATCH mesa 1/6] vulkan/wsi/display: setup the connector earlier

[Keith Packard]

Eric Engestrom  writes:

> Instead of setting it up when the swapchain is presented, set it up when
> creating the swapchain. This means that multiple swapchains might use
> the same crtc, but only one can be active at a time, and the connectors
> are now refcounted.
>
> This is necessary for the next commit.
>
> Signed-off-by: Eric Engestrom 
> ---
>  src/vulkan/wsi/wsi_common_display.c | 39 +++--
>  1 file changed, 31 insertions(+), 8 deletions(-)
>
> diff --git a/src/vulkan/wsi/wsi_common_display.c 
> b/src/vulkan/wsi/wsi_common_display.c
> index 1dbed08d8a750ce21846..2d378afe3d36fe7cc177 100644
> --- a/src/vulkan/wsi/wsi_common_display.c
> +++ b/src/vulkan/wsi/wsi_common_display.c
> @@ -20,6 +20,7 @@
>   * OF THIS SOFTWARE.
>   */
>  
> +#include "util/u_atomic.h"
>  #include "util/macros.h"
>  #include 
>  #include 
> @@ -76,6 +77,7 @@ typedef struct wsi_display_connector {
> char *name;
> bool connected;
> bool active;
> +   int  refcount; /* swapchains using this connector 
> */

Given that you're allocating the crtc at the same time you're setting
this value, could you stick the refcount in the crtc structure and avoid
a bunch of list walking?

> for (uint32_t i = 0; i < chain->base.image_count; i++)
>wsi_display_image_finish(drv_chain, allocator, >images[i]);
> +
> +   wsi_display_mode *display_mode =
> +  wsi_display_mode_from_handle(chain->surface->displayMode);
> +   if (p_atomic_dec_zero(_mode->connector->refcount))
> +  display_mode->connector->crtc_id = 0;
> +

I'd suggest just sticking some huge mutexes around the allocation and
free process to make sure we don't have any races. Either that or assert
that the application needs to deal with the problem. In either case,
atomics don't seem indicated here. I fear any careful ordering of
operations will be hard to review and fragile in the face of future
changes.

Thanks for cleaning this up; it's much nicer in this form than what I
did.

-- 
-keith


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Re: [Mesa-dev] [PATCH 1/5] util: import public domain code for integer division by a constant

[Marek Olšák]

On Tue, Sep 25, 2018 at 5:33 AM Jason Ekstrand  wrote:
>
> On Mon, Sep 24, 2018 at 7:15 PM Marek Olšák  wrote:
>>
>> This patch also handles all types, just differently. If you change the
>> typedefs in the header, you'll get a different type and the code is
>> exactly the same for all types, but that's not important (to me
>> anyway).
>>
>> It also supports signed division. (not important to me either, but may
>> be important to you)
>
>
> Mine supported signed division as well though what's here might be a bit more 
> clever.  I'll have to give it some thought.
>
>>
>> Did you figure out the algorithm by yourself or did you copy it from
>> somewhere? The reason I'm asking is that yours only seems to implement
>> the Round-Up algorithm and you said:
>>
>> "In particular, we want to have m < 2^N so that we don't have any
>> overflow problems.  Unfortunately, this isn't always achievable."
>
>
> Yes, mine is based on the round up algorithm.  However, it's not the blind 
> round-up algorithm; it's a bit smarter than that.
>
>>
>> Let me tell you what. This patch achieves it ALWAYS.
>
>
> I don't think that's true.  You still have an N+1 bit multiplier, you just 
> call it the increment bit.  The saturated add, however, is a neat trick that 
> probably lets you avoid the weirness around adding in the increment factor.  
> I'll need to look at the web-site you linked and think about this stuff again 
> before I can verify it.

If your hw doesn't have a saturated add, you can still achieve the result with:

addcarry (32-bit add doing "+1")
subborrow (saturation)

It takes advantage of the fact that increment <= 1. The idea is that
addcarry returns carry=1 if it overflowed, and subborrow subtracts 1
if carry=1. It avoids all 64-bit math and you only need one 32-bit
intermediate register for the division.

>
>>
>> This patch implements 2 algorithms for unsigned division: Round-Up and
>> Round-Down. The paper I linked shows that the Round Down algorithm
>> generates better code for some divisors than the Round Up algorithm,
>> because the multiplier always fits into 32 bits. The most operations
>> you'll ever need are: 2 shifts, 32-bit saturated ADD and UMUL_HI.
>>
>> Marek
>>
>> On Mon, Sep 24, 2018 at 7:41 PM, Marek Olšák  wrote:
>> > Did you copy the code from the same author?
>> >
>> > Does your version also have an interface for dividing by a uniform
>> > instead of a compile time constant?
>> >
>> > Note that this algorithm was originally only written for
>> > non-power-of-two divisors and I extended it to support 1 and
>> > power-of-two divisors in order to support dividing by a uniform in a
>> > generic way. The other two generic variants that I added are also
>> > important. One of them assumes no unsigned wraparounds and the other
>> > one assumes operands have 31 bits and the divisor is >= 2.
>> >
>> > Marek
>> >
>> > On Mon, Sep 24, 2018 at 10:00 AM, Jason Ekstrand  
>> > wrote:
>> >> Very similar And mine handles 8, 16, and 64-bit types. :-D
>> >>
>> >> --Jason
>> >>
>> >> On Mon, Sep 24, 2018 at 8:53 AM Ian Romanick  wrote:
>> >>>
>> >>> I didn't look really closely at either set, but this seems really
>> >>> similar to something Jason sent out a week or two.  Perhaps you guys
>> >>> could unify these?
>> >>>
>> >>> On 09/23/2018 09:57 AM, Marek Olšák wrote:
>> >>> > From: Marek Olšák 
>> >>> >
>> >>> > Compilers can use this to generate optimal code for integer division
>> >>> > by a constant.
>> >>> >
>> >>> > Additionally, an unsigned division by a uniform that is constant but 
>> >>> > not
>> >>> > known at compile time can still be optimized by passing 2-4 division
>> >>> > factors to the shader as uniforms and executing one of the fast_udiv*
>> >>> > variants. The signed division algorithm doesn't have this capability.
>> >>> > ---
>> >>> >  src/util/Makefile.sources |   2 +
>> >>> >  src/util/fast_idiv_by_const.c | 245
>> >>> > ++
>> >>> >  src/util/fast_idiv_by_const.h | 173 +
>> >>> >  src/util/meson.build  |   2 +
>> >>> >  4 files changed, 422 insertions(+)
>> >>> >  create mode 100644 src/util/fast_idiv_by_const.c
>> >>> >  create mode 100644 src/util/fast_idiv_by_const.h
>> >>> >
>> >>> > diff --git a/src/util/Makefile.sources b/src/util/Makefile.sources
>> >>> > index b562d6c..f741b2a 100644
>> >>> > --- a/src/util/Makefile.sources
>> >>> > +++ b/src/util/Makefile.sources
>> >>> > @@ -3,20 +3,22 @@ MESA_UTIL_FILES := \
>> >>> >   bitscan.h \
>> >>> >   bitset.h \
>> >>> >   build_id.c \
>> >>> >   build_id.h \
>> >>> >   crc32.c \
>> >>> >   crc32.h \
>> >>> >   debug.c \
>> >>> >   debug.h \
>> >>> >   disk_cache.c \
>> >>> >   disk_cache.h \
>> >>> > + fast_idiv_by_const.c \
>> >>> > + fast_idiv_by_const.h \
>> >>> >   format_r11g11b10f.h \
>> >>> >   format_rgb9e5.h \
>> >>> >   format_srgb.h \
>> >>> >   futex.h \
>> >>> >   

Re: [Mesa-dev] [PATCH mesa 5/6] vulkan/wsi/display: pass image's DRM modifiers to the kernel

[Jason Ekstrand]

I have a feeling this should go before patch 3

On September 26, 2018 17:38:24 Eric Engestrom  wrote:


Signed-off-by: Eric Engestrom 
---
src/vulkan/wsi/wsi_common_display.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c

index c24b58e8c240f43ac512..0b71932bfa0939039ae3 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -1082,10 +1082,14 @@ wsi_display_image_init(VkDevice device_h,

memset(image->buffer, 0, sizeof (image->buffer));

+   /* The kernel expect a modifier for each plane for historical
+* reasons, but they all have to be the same */
+   uint64_t drm_modifier[4] = {};
for (unsigned int i = 0; i < image->base.num_planes; i++) {
int ret = drmPrimeFDToHandle(wsi->fd, image->base.fds[i],
  >buffer[i]);

+  drm_modifier[i] = image->base.drm_modifier;
close(image->base.fds[i]);
image->base.fds[i] = -1;
if (ret < 0)
@@ -1096,14 +1100,23 @@ wsi_display_image_init(VkDevice device_h,
image->state = WSI_IMAGE_IDLE;
image->fb_id = 0;

-   int ret = drmModeAddFB2(wsi->fd,
+   uint64_t *fb_modifiers = NULL;
+   uint32_t fb_flags = 0;
+   if (drm_modifier[0] != DRM_FORMAT_MOD_INVALID) {
+  fb_modifiers = drm_modifier;
+  fb_flags |= DRM_MODE_FB_MODIFIERS;
+   }
+
+   int ret = drmModeAddFB2WithModifiers(wsi->fd,
  create_info->imageExtent.width,
  create_info->imageExtent.height,
  drm_format,
  image->buffer,
  image->base.row_pitches,
  image->base.offsets,
-   >fb_id, 0);
+   fb_modifiers,
+   >fb_id,
+   fb_flags);

if (ret)
goto fail_fb;
--
Cheers,
Eric




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[Mesa-dev] [PATCH mesa 3/6] vulkan/wsi/display: pass the plane's modifiers to the image

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/vulkan/wsi/wsi_common_display.c | 95 -
 1 file changed, 94 insertions(+), 1 deletion(-)

diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c
index 6c9160a445c8f25a8ad5..2a30b1139f06cbb56769 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -958,6 +958,87 @@ wsi_display_destroy_buffer(struct wsi_display *wsi,
&((struct drm_mode_destroy_dumb) { .handle = buffer }));
 }
 
+static uint64_t*
+wsi_get_modifiers_for_format(const struct wsi_display * const wsi,
+ const uint32_t plane_id,
+ const uint32_t drm_format,
+ uint32_t * const modifiers_count)
+{
+   /* Get the properties of the plane */
+   drmModeObjectProperties *props =
+  drmModeObjectGetProperties(wsi->fd, plane_id,
+ DRM_MODE_OBJECT_PLANE);
+   if (!props)
+  return NULL;
+
+   /* Find the blob the contains the formats and their modifiers */
+   uint32_t blob_id = 0;
+   for (size_t i = 0; i< props->count_props; i++) {
+  const drmModePropertyPtr prop =
+ drmModeGetProperty(wsi->fd, props->props[i]);
+
+  if (!strcmp(prop->name, "IN_FORMATS")) {
+ blob_id = props->prop_values[i];
+ drmModeFreeProperty(prop);
+ break;
+  }
+
+  drmModeFreeProperty(prop);
+   }
+
+   /* Property not found, which means old kernel, so definitely no
+* modifiers support */
+   if (blob_id == 0)
+  return NULL;
+
+   /* Grab the IN_FORMATS blob */
+   drmModePropertyBlobRes *blob = drmModeGetPropertyBlob(wsi->fd, blob_id);
+   if (!blob)
+  return NULL;
+
+   /* Get the formats and modifiers out of the blob */
+   struct drm_format_modifier_blob *fmt_mod_blob = blob->data;
+   uint32_t *blob_formats = (uint32_t*)((char*)fmt_mod_blob +
+fmt_mod_blob->formats_offset);
+   struct drm_format_modifier *blob_modifiers =
+  (struct drm_format_modifier *)((char*)fmt_mod_blob +
+ fmt_mod_blob->modifiers_offset);
+
+   /* Find the format we care about in the list */
+   size_t format_index = 0;
+   for (size_t i = 0; i < fmt_mod_blob->count_formats; i++) {
+  if (blob_formats[i] == drm_format) {
+ format_index = i;
+ break;
+  }
+   }
+
+   /* Get the list of modifiers supported by that format */
+   uint32_t count_modifiers = 0;
+   uint64_t *modifiers = NULL;
+   for (size_t i = 0; i < fmt_mod_blob->count_modifiers; i++) {
+  struct drm_format_modifier *mod = _modifiers[i];
+
+  if ((format_index < mod->offset) || (format_index > mod->offset + 63))
+ continue;
+  if (!(mod->formats & (1 << (format_index - mod->offset
+ continue;
+
+  modifiers = realloc(modifiers,
+  (count_modifiers + 1) *
+  sizeof(modifiers[0]));
+  assert(modifiers);
+  modifiers[count_modifiers++] = mod->modifier;
+   }
+
+   drmModeFreePropertyBlob(blob);
+
+   drmModeFreeObjectProperties(props);
+
+   *modifiers_count = count_modifiers;
+   return modifiers;
+}
+
 static VkResult
 wsi_display_image_init(VkDevice device_h,
struct wsi_swapchain *drv_chain,
@@ -969,6 +1050,10 @@ wsi_display_image_init(VkDevice device_h,
   (struct wsi_display_swapchain *) drv_chain;
struct wsi_display *wsi = chain->wsi;
uint32_t drm_format = 0;
+   VkIcdSurfaceDisplay *surface = chain->surface;
+   wsi_display_mode *display_mode =
+  wsi_display_mode_from_handle(surface->displayMode);
+   wsi_display_connector *connector = display_mode->connector;
 
for (unsigned i = 0; i < ARRAY_SIZE(available_surface_formats); i++) {
   if (create_info->imageFormat == available_surface_formats[i].format) {
@@ -981,9 +1066,17 @@ wsi_display_image_init(VkDevice device_h,
if (drm_format == 0)
   return VK_ERROR_DEVICE_LOST;
 
+   uint32_t modifiers_count = 0;
+   uint64_t *modifiers = wsi_get_modifiers_for_format(wsi, 
connector->plane_id, drm_format,
+  _count);
+   assume(!modifiers || modifiers_count > 0);
+
VkResult result = wsi_create_native_image(>base, create_info,
- 0, NULL, NULL,
+ !!modifiers_count,
+ _count,
+ (const uint64_t * const 
*),
  >base);
+   free(modifiers);
if (result != VK_SUCCESS)
   return result;
 
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 6/6] fixup! vulkan/wsi/display: pass DRM modifiers to the kernel

[Eric Engestrom]

(split out for review)
---
 src/vulkan/wsi/wsi_common_display.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c
index 0b71932bfa0939039ae3..1518a1736e424319ab69 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -1108,15 +1108,15 @@ wsi_display_image_init(VkDevice device_h,
}
 
int ret = drmModeAddFB2WithModifiers(wsi->fd,
-   create_info->imageExtent.width,
-   create_info->imageExtent.height,
-   drm_format,
-   image->buffer,
-   image->base.row_pitches,
-   image->base.offsets,
-   fb_modifiers,
-   >fb_id,
-   fb_flags);
+create_info->imageExtent.width,
+create_info->imageExtent.height,
+drm_format,
+image->buffer,
+image->base.row_pitches,
+image->base.offsets,
+fb_modifiers,
+>fb_id,
+fb_flags);
 
if (ret)
   goto fail_fb;
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 2/6] vulkan/wsi/display: also select a plane when selecting a crtc

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/vulkan/wsi/wsi_common_display.c | 80 +
 1 file changed, 80 insertions(+)

diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c
index 2d378afe3d36fe7cc177..6c9160a445c8f25a8ad5 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -74,6 +74,7 @@ typedef struct wsi_display_connector {
struct wsi_display   *wsi;
uint32_t id;
uint32_t crtc_id;
+   uint32_t plane_id;
char *name;
bool connected;
bool active;
@@ -1348,6 +1349,81 @@ wsi_display_select_crtc(const struct 
wsi_display_connector *connector,
return crtc_id;
 }
 
+/*
+ * Pick a suitable plane for the current CRTC. Prefer a plane currently
+ * active on the CRTC. Settle for a plane which is currently idle but
+ * is compatible with the CRTC. Fall back to the first idle plane found.
+ */
+static uint32_t
+wsi_display_select_plane(const struct wsi_display_connector * const connector)
+{
+   struct wsi_display *wsi = connector->wsi;
+   uint32_t plane_id = connector->plane_id;
+
+   if (plane_id)
+  return plane_id;
+
+   /* We understand universal planes */
+   drmSetClientCap(wsi->fd, DRM_CLIENT_CAP_UNIVERSAL_PLANES, 1);
+
+   drmModePlaneRes *plane_res = drmModeGetPlaneResources(wsi->fd);
+   if (!plane_res)
+  return 0;
+
+   /* if there's a plane is active on the connector's crtc, pick it */
+   for (size_t i = 0; i < plane_res->count_planes; i++) {
+  drmModePlane *plane = drmModeGetPlane(wsi->fd, plane_res->planes[i]);
+  if (!plane)
+ continue;
+
+  if (plane->crtc_id != connector->crtc_id) {
+ drmModeFreePlane(plane);
+ continue;
+  }
+
+  plane_id = plane->plane_id;
+  drmModeFreePlane(plane);
+  goto success;
+   }
+
+   /* if a plane is not active on any crtc but the connector's crtc is
+* in the plane's possible_crtcs, pick it */
+   for (size_t i = 0; i < plane_res->count_planes; i++) {
+  drmModePlane *plane = drmModeGetPlane(wsi->fd, plane_res->planes[i]);
+  if (!plane)
+ continue;
+
+  if (!(plane->possible_crtcs & (1u << connector->crtc_id))) {
+ drmModeFreePlane(plane);
+ continue;
+  }
+
+  plane_id = plane->plane_id;
+  drmModeFreePlane(plane);
+  goto success;
+   }
+
+   /* if all else fails, pick a plane not active on any crtc */
+   for (size_t i = 0; i < plane_res->count_planes; i++) {
+  drmModePlane *plane = drmModeGetPlane(wsi->fd, plane_res->planes[i]);
+  if (!plane)
+ continue;
+
+  if (plane->crtc_id) {
+ drmModeFreePlane(plane);
+ continue;
+  }
+
+  plane_id = plane->plane_id;
+  drmModeFreePlane(plane);
+  goto success;
+   }
+
+success:
+   drmModeFreePlaneResources(plane_res);
+   return plane_id;
+}
+
 static VkResult
 wsi_display_setup_connector(wsi_display_connector *connector,
 wsi_display_mode *display_mode)
@@ -1387,6 +1463,10 @@ wsi_display_setup_connector(wsi_display_connector 
*connector,
  result = VK_ERROR_SURFACE_LOST_KHR;
  goto bail_connector;
   }
+
+  /* Select the primary plane of that CRTC, and populate the
+   * format/modifier lists for that plane */
+  connector->plane_id = wsi_display_select_plane(connector);
}
 
if (connector->current_mode != display_mode) {
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 5/6] vulkan/wsi/display: pass image's DRM modifiers to the kernel

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/vulkan/wsi/wsi_common_display.c | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c
index c24b58e8c240f43ac512..0b71932bfa0939039ae3 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -1082,10 +1082,14 @@ wsi_display_image_init(VkDevice device_h,
 
memset(image->buffer, 0, sizeof (image->buffer));
 
+   /* The kernel expect a modifier for each plane for historical
+* reasons, but they all have to be the same */
+   uint64_t drm_modifier[4] = {};
for (unsigned int i = 0; i < image->base.num_planes; i++) {
   int ret = drmPrimeFDToHandle(wsi->fd, image->base.fds[i],
>buffer[i]);
 
+  drm_modifier[i] = image->base.drm_modifier;
   close(image->base.fds[i]);
   image->base.fds[i] = -1;
   if (ret < 0)
@@ -1096,14 +1100,23 @@ wsi_display_image_init(VkDevice device_h,
image->state = WSI_IMAGE_IDLE;
image->fb_id = 0;
 
-   int ret = drmModeAddFB2(wsi->fd,
+   uint64_t *fb_modifiers = NULL;
+   uint32_t fb_flags = 0;
+   if (drm_modifier[0] != DRM_FORMAT_MOD_INVALID) {
+  fb_modifiers = drm_modifier;
+  fb_flags |= DRM_MODE_FB_MODIFIERS;
+   }
+
+   int ret = drmModeAddFB2WithModifiers(wsi->fd,
create_info->imageExtent.width,
create_info->imageExtent.height,
drm_format,
image->buffer,
image->base.row_pitches,
image->base.offsets,
-   >fb_id, 0);
+   fb_modifiers,
+   >fb_id,
+   fb_flags);
 
if (ret)
   goto fail_fb;
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 4/6] vulkan/wsi/display: add comment

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/vulkan/wsi/wsi_common_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c
index 2a30b1139f06cbb56769..c24b58e8c240f43ac512 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -99,7 +99,7 @@ struct wsi_display {
pthread_cond_t   wait_cond;
pthread_twait_thread;
 
-   struct list_head connectors;
+   struct list_head connectors; /* list of all discovered 
connectors */
 };
 
 #define wsi_for_each_display_mode(_mode, _conn) \
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 1/6] vulkan/wsi/display: setup the connector earlier

[Eric Engestrom]

Instead of setting it up when the swapchain is presented, set it up when
creating the swapchain. This means that multiple swapchains might use
the same crtc, but only one can be active at a time, and the connectors
are now refcounted.

This is necessary for the next commit.

Signed-off-by: Eric Engestrom 
---
 src/vulkan/wsi/wsi_common_display.c | 39 +++--
 1 file changed, 31 insertions(+), 8 deletions(-)

diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c
index 1dbed08d8a750ce21846..2d378afe3d36fe7cc177 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -20,6 +20,7 @@
  * OF THIS SOFTWARE.
  */
 
+#include "util/u_atomic.h"
 #include "util/macros.h"
 #include 
 #include 
@@ -76,6 +77,7 @@ typedef struct wsi_display_connector {
char *name;
bool connected;
bool active;
+   int  refcount; /* swapchains using this connector */
struct list_head display_modes;
wsi_display_mode *current_mode;
drmModeModeInfo  current_drm_mode;
@@ -270,6 +272,18 @@ wsi_display_find_connector(struct wsi_device *wsi_device,
return NULL;
 }
 
+
+static uint32_t
+wsi_display_is_crtc_available(const struct wsi_display * const wsi,
+ const uint32_t crtc_id)
+{
+   wsi_for_each_connector(connector, wsi)
+  if (connector->crtc_id == crtc_id)
+ return false;
+
+   return true;
+}
+
 static struct wsi_display_connector *
 wsi_display_alloc_connector(struct wsi_display *wsi,
 uint32_t connector_id)
@@ -1042,6 +1056,12 @@ wsi_display_swapchain_destroy(struct wsi_swapchain 
*drv_chain,
 
for (uint32_t i = 0; i < chain->base.image_count; i++)
   wsi_display_image_finish(drv_chain, allocator, >images[i]);
+
+   wsi_display_mode *display_mode =
+  wsi_display_mode_from_handle(chain->surface->displayMode);
+   if (p_atomic_dec_zero(_mode->connector->refcount))
+  display_mode->connector->crtc_id = 0;
+
vk_free(allocator, chain);
return VK_SUCCESS;
 }
@@ -1320,7 +1340,8 @@ wsi_display_select_crtc(const struct 
wsi_display_connector *connector,
uint32_t crtc_id = 0;
for (int c = 0; crtc_id == 0 && c < mode_res->count_crtcs; c++) {
   drmModeCrtcPtr crtc = drmModeGetCrtc(wsi->fd, mode_res->crtcs[c]);
-  if (crtc && crtc->buffer_id == 0)
+  if (crtc && crtc->buffer_id == 0 &&
+  wsi_display_is_crtc_available(wsi, crtc->crtc_id))
  crtc_id = crtc->crtc_id;
   drmModeFreeCrtc(crtc);
}
@@ -1614,13 +1635,6 @@ _wsi_display_queue_next(struct wsi_swapchain *drv_chain)
   }
 
   if (ret == -EINVAL) {
- VkResult result = wsi_display_setup_connector(connector, 
display_mode);
-
- if (result != VK_SUCCESS) {
-image->state = WSI_IMAGE_IDLE;
-return result;
- }
-
  /* XXX allow setting of position */
  ret = drmModeSetCrtc(wsi->fd, connector->crtc_id,
   image->fb_id, 0, 0,
@@ -1729,6 +1743,15 @@ wsi_display_surface_create_swapchain(
 
chain->surface = (VkIcdSurfaceDisplay *) icd_surface;
 
+   wsi_display_mode *display_mode =
+  wsi_display_mode_from_handle(chain->surface->displayMode);
+
+   result = wsi_display_setup_connector(display_mode->connector, display_mode);
+   if (result != VK_SUCCESS)
+  return result;
+
+   p_atomic_inc(_mode->connector->refcount);
+
for (uint32_t image = 0; image < chain->base.image_count; image++) {
   result = wsi_display_image_init(device, >base,
   create_info, allocator,
-- 
Cheers,
  Eric

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Re: [Mesa-dev] [PATCH 1/2] anv: s/batch/value_bo/ on anv_device_init_hiz_clear_batch

[Nanley Chery]

On Tue, Sep 25, 2018 at 04:26:57PM -0700, Jordan Justen wrote:
> Signed-off-by: Jordan Justen 
> Cc: Jason Ekstrand 
> ---
>  src/intel/vulkan/anv_device.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

This series is
Reviewed-by: Nanley Chery 

> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index 4219a073d2d..265fc4a3347 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -1566,7 +1566,7 @@ vk_priority_to_gen(int priority)
>  }
>  
>  static void
> -anv_device_init_hiz_clear_batch(struct anv_device *device)
> +anv_device_init_hiz_clear_value_bo(struct anv_device *device)
>  {
> anv_bo_init_new(>hiz_clear_bo, device, 4096);
> uint32_t *map = anv_gem_mmap(device, device->hiz_clear_bo.gem_handle,
> @@ -1802,7 +1802,7 @@ VkResult anv_CreateDevice(
> anv_device_init_trivial_batch(device);
>  
> if (device->info.gen >= 10)
> -  anv_device_init_hiz_clear_batch(device);
> +  anv_device_init_hiz_clear_value_bo(device);
>  
> anv_scratch_pool_init(device, >scratch_pool);
>  
> -- 
> 2.18.0
> 
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Re: [Mesa-dev] [PATCH] vl: reorder H264 profiles

[Zhang, Boyuan]

Yes, I was thinking either using a switch helper function or doing this 1 line 
change since there will be no more profile to be added.

But no problem, I agree that using switch helper function is a safer way.

New patch just sent.

Regards,
Boyuan


-Original Message-
From: Christian König  
Sent: September 26, 2018 4:05 AM
To: Zhang, Boyuan ; mesa-dev@lists.freedesktop.org
Subject: Re: [PATCH] vl: reorder H264 profiles

Am 26.09.2018 um 00:11 schrieb boyuan.zh...@amd.com:
> From: Boyuan Zhang 
>
> Fix the wrong h264 profiles order. Previously, the constrained 
> baseline was added in between baseline and main profiles, which 
> breaked the logic in radeon/vce when converting from 
> pipe_video_profile to profile_idc

I think it would be better to use a switch/case in radeon/vce or even better 
make a helper function which converts between
PIPE_VIDEO_PROFILE_MPEG4_AVC_* and the profile_idc from the specification.

Christian.

>
> Signed-off-by: Boyuan Zhang 
> ---
>   src/gallium/include/pipe/p_video_enums.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/include/pipe/p_video_enums.h 
> b/src/gallium/include/pipe/p_video_enums.h
> index b5b8b06228..260f47ea8a 100644
> --- a/src/gallium/include/pipe/p_video_enums.h
> +++ b/src/gallium/include/pipe/p_video_enums.h
> @@ -55,8 +55,8 @@ enum pipe_video_profile
>  PIPE_VIDEO_PROFILE_VC1_SIMPLE,
>  PIPE_VIDEO_PROFILE_VC1_MAIN,
>  PIPE_VIDEO_PROFILE_VC1_ADVANCED,
> -   PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE,
>  PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE,
> +   PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE,
>  PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN,
>  PIPE_VIDEO_PROFILE_MPEG4_AVC_EXTENDED,
>  PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH,

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[Mesa-dev] [PATCH] radeon/vce: use switch to convert profile idc

[boyuan.zhang]

From: Boyuan Zhang 

The previous array logic for converting pipe video profile to profile idc
relies on the order of pipe_video_profile enum defines. Adding new profile
to enum defines may break the logic. Therefore, it's better to use switch
helper function to acheive the same goal.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vce.c   | 24 +++
 src/gallium/drivers/radeon/radeon_vce.h   |  3 +++
 .../drivers/radeon/radeon_vce_40_2_2.c|  5 +---
 src/gallium/drivers/radeon/radeon_vce_52.c|  5 +---
 4 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vce.c 
b/src/gallium/drivers/radeon/radeon_vce.c
index 8972253c7c..6b9f2ab37b 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -572,3 +572,27 @@ void si_vce_add_buffer(struct rvce_encoder *enc, struct 
pb_buffer *buf,
RVCE_CS(offset);
}
 }
+
+unsigned si_vce_get_profile_idc(enum pipe_video_profile profile)
+{
+   switch (profile) {
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE:
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
+   return 66;
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
+   return 77;
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_EXTENDED:
+   return 88;
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
+   return 100;
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH10:
+   return 110;
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH422:
+   return 122;
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH444:
+   return 244;
+   default:
+   RVID_ERR("Unsupported profile! Use baseline profile 
instead.\n");
+   return 66;
+   }
+}
diff --git a/src/gallium/drivers/radeon/radeon_vce.h 
b/src/gallium/drivers/radeon/radeon_vce.h
index cf625e6fed..255a3bf200 100644
--- a/src/gallium/drivers/radeon/radeon_vce.h
+++ b/src/gallium/drivers/radeon/radeon_vce.h
@@ -453,4 +453,7 @@ void si_vce_50_get_param(struct rvce_encoder *enc,
 void si_vce_52_get_param(struct rvce_encoder *enc,
 struct pipe_h264_enc_picture_desc *pic);
 
+/* convert pipe video profile to profile idc */
+unsigned si_vce_get_profile_idc(enum pipe_video_profile profile);
+
 #endif
diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c 
b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
index 66b54dab25..925480e4af 100644
--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
@@ -38,8 +38,6 @@
 #include "radeon_video.h"
 #include "radeon_vce.h"
 
-static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
-
 static void session(struct rvce_encoder *enc)
 {
RVCE_BEGIN(0x0001); // session cmd
@@ -82,8 +80,7 @@ static void create(struct rvce_encoder *enc)
 
RVCE_BEGIN(0x0101); // create cmd
RVCE_CS(0x); // encUseCircularBuffer
-   RVCE_CS(profiles[enc->base.profile -
-   PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]); // encProfile
+   RVCE_CS(si_vce_get_profile_idc(enc->base.profile)); // encProfile
RVCE_CS(enc->base.level); // encLevel
RVCE_CS(0x); // encPicStructRestriction
RVCE_CS(enc->base.width); // encImageWidth
diff --git a/src/gallium/drivers/radeon/radeon_vce_52.c 
b/src/gallium/drivers/radeon/radeon_vce_52.c
index 421539c4bd..bf7c5d6ff2 100644
--- a/src/gallium/drivers/radeon/radeon_vce_52.c
+++ b/src/gallium/drivers/radeon/radeon_vce_52.c
@@ -38,8 +38,6 @@
 #include "radeon_video.h"
 #include "radeon_vce.h"
 
-static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
-
 static void get_rate_control_param(struct rvce_encoder *enc, struct 
pipe_h264_enc_picture_desc *pic)
 {
enc->enc_pic.rc.rc_method = pic->rate_ctrl.rate_ctrl_method;
@@ -172,8 +170,7 @@ static void create(struct rvce_encoder *enc)
 
RVCE_BEGIN(0x0101); // create cmd
RVCE_CS(enc->enc_pic.ec.enc_use_circular_buffer);
-   RVCE_CS(profiles[enc->base.profile -
-   PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]); // encProfile
+   RVCE_CS(si_vce_get_profile_idc(enc->base.profile)); // encProfile
RVCE_CS(enc->base.level); // encLevel
RVCE_CS(enc->enc_pic.ec.enc_pic_struct_restriction);
RVCE_CS(enc->base.width); // encImageWidth
-- 
2.17.1

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Re: [Mesa-dev] [PATCH 3/8] anv/android: add GetAndroidHardwareBufferPropertiesANDROID

[Tapani Pälli]

On 9/26/18 4:46 PM, Jason Ekstrand wrote:
On Wed, Sep 26, 2018 at 8:29 AM Tapani Pälli > wrote:




On 9/26/18 10:46 AM, Jason Ekstrand wrote:
 > On Mon, Aug 27, 2018 at 2:22 AM Jason Ekstrand
mailto:ja...@jlekstrand.net>
 > >> wrote:
 >
 >     On Sun, Aug 26, 2018 at 11:54 PM Tapani Pälli
 >     mailto:tapani.pa...@intel.com>
>> wrote:
 >
 >
 >
 >         On 08/24/2018 05:04 PM, Jason Ekstrand wrote:
 >          > On Fri, Aug 24, 2018 at 12:08 AM Tapani Pälli
 >         mailto:tapani.pa...@intel.com>
>
 >          > 
 >                   >
 >          >
 >          >
 >          >     On 08/22/2018 05:18 PM, Jason Ekstrand wrote:
 >          >      > On Tue, Aug 21, 2018 at 3:27 AM Tapani Pälli
 >          >     mailto:tapani.pa...@intel.com> >
 >          >>
 >          >      > 
 >         > 
 >         
 >          >     wrote:
 >          >      >
 >          >      >     When adding YUV support, we need to figure out
 >          >     implementation-defined
 >          >      >     external format identifier.
 >          >      >
 >          >      >     Signed-off-by: Tapani Pälli
 >         mailto:tapani.pa...@intel.com>
>
 >          >     
 >         >>
 >          >      >     
 >         > 
 >         
 >          >      >     ---
 >          >      >       src/intel/vulkan/anv_android.c | 99
 >          >      >     ++
 >          >      >       1 file changed, 99 insertions(+)
 >          >      >
 >          >      >     diff --git a/src/intel/vulkan/anv_android.c
 >          >      >     b/src/intel/vulkan/anv_android.c
 >          >      >     index 46c41d57861..7d0eb588e2b 100644
 >          >      >     --- a/src/intel/vulkan/anv_android.c
 >          >      >     +++ b/src/intel/vulkan/anv_android.c
 >          >      >     @@ -29,6 +29,8 @@
 >          >      >       #include 
 >          >      >
 >          >      >       #include "anv_private.h"
 >          >      >     +#include "vk_format_info.h"
 >          >      >     +#include "vk_util.h"
 >          >      >
 >          >      >       static int anv_hal_open(const struct
 >         hw_module_t* mod,
 >          >     const char*
 >          >      >     id, struct hw_device_t** dev);
 >          >      >       static int anv_hal_close(struct
hw_device_t *dev);
 >          >      >     @@ -96,6 +98,103 @@ anv_hal_close(struct
 >         hw_device_t *dev)
 >          >      >          return -1;
 >          >      >       }
 >          >      >
 >          >      >     +static VkResult
 >          >      >     +get_ahw_buffer_format_properties(
 >          >      >     +   VkDevice device_h,
 >          >      >     +   const struct AHardwareBuffer *buffer,
 >          >      >     + 
  VkAndroidHardwareBufferFormatPropertiesANDROID

 >         *pProperties)
 >          >      >     +{
 >          >      >     +   ANV_FROM_HANDLE(anv_device, device,
device_h);
 >          >      >     +
 >          >      >     +   /* Get a description of buffer contents
. */
 >          >      >     +   AHardwareBuffer_Desc desc;
 >          >      >     +   AHardwareBuffer_describe(buffer, );
 >          >      >     +
 >          >      >     +   /* Verify description. */
 >          >      >     +   uint64_t gpu_usage =
 >          >      >     + 

Re: [Mesa-dev] [PATCH 3/8] anv/android: add GetAndroidHardwareBufferPropertiesANDROID

[Jason Ekstrand]

On Wed, Sep 26, 2018 at 8:29 AM Tapani Pälli  wrote:

>
>
> On 9/26/18 10:46 AM, Jason Ekstrand wrote:
> > On Mon, Aug 27, 2018 at 2:22 AM Jason Ekstrand  > > wrote:
> >
> > On Sun, Aug 26, 2018 at 11:54 PM Tapani Pälli
> > mailto:tapani.pa...@intel.com>> wrote:
> >
> >
> >
> > On 08/24/2018 05:04 PM, Jason Ekstrand wrote:
> >  > On Fri, Aug 24, 2018 at 12:08 AM Tapani Pälli
> > mailto:tapani.pa...@intel.com>
> >  >  > >> wrote:
> >  >
> >  >
> >  >
> >  > On 08/22/2018 05:18 PM, Jason Ekstrand wrote:
> >  >  > On Tue, Aug 21, 2018 at 3:27 AM Tapani Pälli
> >  > mailto:tapani.pa...@intel.com>
> > >
> >  >  >  >   >  >  > wrote:
> >  >  >
> >  >  > When adding YUV support, we need to figure out
> >  > implementation-defined
> >  >  > external format identifier.
> >  >  >
> >  >  > Signed-off-by: Tapani Pälli
> > mailto:tapani.pa...@intel.com>
> >  >  > >
> >  >  >  >   >  >  >  > ---
> >  >  >   src/intel/vulkan/anv_android.c | 99
> >  >  > ++
> >  >  >   1 file changed, 99 insertions(+)
> >  >  >
> >  >  > diff --git a/src/intel/vulkan/anv_android.c
> >  >  > b/src/intel/vulkan/anv_android.c
> >  >  > index 46c41d57861..7d0eb588e2b 100644
> >  >  > --- a/src/intel/vulkan/anv_android.c
> >  >  > +++ b/src/intel/vulkan/anv_android.c
> >  >  > @@ -29,6 +29,8 @@
> >  >  >   #include 
> >  >  >
> >  >  >   #include "anv_private.h"
> >  >  > +#include "vk_format_info.h"
> >  >  > +#include "vk_util.h"
> >  >  >
> >  >  >   static int anv_hal_open(const struct
> > hw_module_t* mod,
> >  > const char*
> >  >  > id, struct hw_device_t** dev);
> >  >  >   static int anv_hal_close(struct hw_device_t
> *dev);
> >  >  > @@ -96,6 +98,103 @@ anv_hal_close(struct
> > hw_device_t *dev)
> >  >  >  return -1;
> >  >  >   }
> >  >  >
> >  >  > +static VkResult
> >  >  > +get_ahw_buffer_format_properties(
> >  >  > +   VkDevice device_h,
> >  >  > +   const struct AHardwareBuffer *buffer,
> >  >  > +   VkAndroidHardwareBufferFormatPropertiesANDROID
> > *pProperties)
> >  >  > +{
> >  >  > +   ANV_FROM_HANDLE(anv_device, device, device_h);
> >  >  > +
> >  >  > +   /* Get a description of buffer contents . */
> >  >  > +   AHardwareBuffer_Desc desc;
> >  >  > +   AHardwareBuffer_describe(buffer, );
> >  >  > +
> >  >  > +   /* Verify description. */
> >  >  > +   uint64_t gpu_usage =
> >  >  > +  AHARDWAREBUFFER_USAGE_GPU_SAMPLED_IMAGE |
> >  >  > +  AHARDWAREBUFFER_USAGE_GPU_COLOR_OUTPUT |
> >  >  > +  AHARDWAREBUFFER_USAGE_GPU_DATA_BUFFER;
> >  >  > +
> >  >  > +   /* "Buffer must be a valid Android hardware
> > buffer object
> >  > with
> >  >  > at least
> >  >  > +* one of the AHARDWAREBUFFER_USAGE_GPU_*
> > usage flags."
> >  >  > +*/
> >  >  > +   if (!(desc.usage & (gpu_usage)))
> >  >  > +  return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
> >  >  > +
> >  >  > +   /* Fill properties fields based on
> description. */
> >  >  > +   VkAndroidHardwareBufferFormatPropertiesANDROID
> > *p =
> >  > pProperties;
> >  >  > +
> >  >  > +   p->pNext = NULL;
> >  >  >
> >  >  >
> >  >  > You shouldn't be overwriting pNext.  That's used by
> > the client to
> >  > let
> >  >  > them chain in multiple structs to fill out in case
> > 

Re: [Mesa-dev] [PATCH 3/8] anv/android: add GetAndroidHardwareBufferPropertiesANDROID

[Tapani Pälli]

On 9/26/18 10:46 AM, Jason Ekstrand wrote:
On Mon, Aug 27, 2018 at 2:22 AM Jason Ekstrand > wrote:


On Sun, Aug 26, 2018 at 11:54 PM Tapani Pälli
mailto:tapani.pa...@intel.com>> wrote:



On 08/24/2018 05:04 PM, Jason Ekstrand wrote:
 > On Fri, Aug 24, 2018 at 12:08 AM Tapani Pälli
mailto:tapani.pa...@intel.com>
 > >> wrote:
 >
 >
 >
 >     On 08/22/2018 05:18 PM, Jason Ekstrand wrote:
 >      > On Tue, Aug 21, 2018 at 3:27 AM Tapani Pälli
 >     mailto:tapani.pa...@intel.com>
>
 >      >       wrote:
 >      >
 >      >     When adding YUV support, we need to figure out
 >     implementation-defined
 >      >     external format identifier.
 >      >
 >      >     Signed-off-by: Tapani Pälli
mailto:tapani.pa...@intel.com>
 >     >
 >      >            >     ---
 >      >       src/intel/vulkan/anv_android.c | 99
 >      >     ++
 >      >       1 file changed, 99 insertions(+)
 >      >
 >      >     diff --git a/src/intel/vulkan/anv_android.c
 >      >     b/src/intel/vulkan/anv_android.c
 >      >     index 46c41d57861..7d0eb588e2b 100644
 >      >     --- a/src/intel/vulkan/anv_android.c
 >      >     +++ b/src/intel/vulkan/anv_android.c
 >      >     @@ -29,6 +29,8 @@
 >      >       #include 
 >      >
 >      >       #include "anv_private.h"
 >      >     +#include "vk_format_info.h"
 >      >     +#include "vk_util.h"
 >      >
 >      >       static int anv_hal_open(const struct
hw_module_t* mod,
 >     const char*
 >      >     id, struct hw_device_t** dev);
 >      >       static int anv_hal_close(struct hw_device_t *dev);
 >      >     @@ -96,6 +98,103 @@ anv_hal_close(struct
hw_device_t *dev)
 >      >          return -1;
 >      >       }
 >      >
 >      >     +static VkResult
 >      >     +get_ahw_buffer_format_properties(
 >      >     +   VkDevice device_h,
 >      >     +   const struct AHardwareBuffer *buffer,
 >      >     +   VkAndroidHardwareBufferFormatPropertiesANDROID
*pProperties)
 >      >     +{
 >      >     +   ANV_FROM_HANDLE(anv_device, device, device_h);
 >      >     +
 >      >     +   /* Get a description of buffer contents . */
 >      >     +   AHardwareBuffer_Desc desc;
 >      >     +   AHardwareBuffer_describe(buffer, );
 >      >     +
 >      >     +   /* Verify description. */
 >      >     +   uint64_t gpu_usage =
 >      >     +      AHARDWAREBUFFER_USAGE_GPU_SAMPLED_IMAGE |
 >      >     +      AHARDWAREBUFFER_USAGE_GPU_COLOR_OUTPUT |
 >      >     +      AHARDWAREBUFFER_USAGE_GPU_DATA_BUFFER;
 >      >     +
 >      >     +   /* "Buffer must be a valid Android hardware
buffer object
 >     with
 >      >     at least
 >      >     +    * one of the AHARDWAREBUFFER_USAGE_GPU_*
usage flags."
 >      >     +    */
 >      >     +   if (!(desc.usage & (gpu_usage)))
 >      >     +      return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
 >      >     +
 >      >     +   /* Fill properties fields based on description. */
 >      >     +   VkAndroidHardwareBufferFormatPropertiesANDROID
*p =
 >     pProperties;
 >      >     +
 >      >     +   p->pNext = NULL;
 >      >
 >      >
 >      > You shouldn't be overwriting pNext.  That's used by
the client to
 >     let
 >      > them chain in multiple structs to fill out in case
Google ever
 >     extends
 >      > this extension.  Also, while we're here, it'd be good
to throw in an
 >      > assert that p->sType is the right thing.
 >
 >     Yes of course, will remove.
 >
 >      >     +   p->format = vk_format_from_android(desc.format);
 >      >     +   p->externalFormat = 1; /* XXX */
 >      >     +
 >      >     +   const struct anv_format *anv_format 

Re: [Mesa-dev] [PATCH v2 1/4] util: Get program name based on path when possible

[Kazlauskas, Nicholas]

On 09/25/2018 06:01 PM, Emil Velikov wrote:

On 24 September 2018 at 19:18, Nicholas Kazlauskas
 wrote:

Some programs start with the path and command line arguments in
argv[0] (program_invocation_name). Chromium is an example of
an application using mesa that does this.

This tries to query the real path for the symbolic link /proc/self/exe
to find the program name instead.


Out of curiosity: did you sent a patch to Chromium to fix this?
I'm not quite sure if that (arguments passed in argv[0]) is supposed
to work, reliably.

-Emil



I don't think it's expected behavior when it comes to the rest of 
userspace but I'm not familiar enough with Chromium's multiprocess model 
to say for sure. I haven't reported this as a bug.


Anything that uses Chromium as a base exhibits this behavior as well - 
pretty much anything that uses Electron.


Nicholas Kazlauskas
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Re: [Mesa-dev] [PATCH 2/2] anv: If softpin is supported, use it with the hiz clear value bo

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Tue, Sep 25, 2018 at 6:27 PM Jordan Justen 
wrote:

> Signed-off-by: Jordan Justen 
> Cc: Nanley Chery 
> Cc: Jason Ekstrand 
> ---
>  src/intel/vulkan/anv_device.c | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index 265fc4a3347..4e64f595650 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -1569,6 +1569,15 @@ static void
>  anv_device_init_hiz_clear_value_bo(struct anv_device *device)
>  {
> anv_bo_init_new(>hiz_clear_bo, device, 4096);
> +
> +   if (device->instance->physicalDevice.has_exec_async)
> +  device->hiz_clear_bo.flags |= EXEC_OBJECT_ASYNC;
> +
> +   if (device->instance->physicalDevice.use_softpin)
> +  device->hiz_clear_bo.flags |= EXEC_OBJECT_PINNED;
> +
> +   anv_vma_alloc(device, >hiz_clear_bo);
> +
> uint32_t *map = anv_gem_mmap(device, device->hiz_clear_bo.gem_handle,
>  0, 4096, 0);
>
> --
> 2.18.0
>
>
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[Mesa-dev] [PATCH] radv: do not sync CP DMA when copying buffers

[Samuel Pitoiset]

We already track if the DMA engine is busy/idle with a flag,
and we emit a packet that waits for all CP DMA operations
to be complete. This is done at end of command buffer because
the kernel doesn't wait for them, and also when emitting
barriers, so it should be safe.

This improves small copies for both aligned and unaligned sizes.

Aligned sizes:
BEFORE:
1 KB: 59.84 ms
2 KB: 71.20 ms
AFTER:
1 KB: 31.20 ms
2 KB: 31.04 ms

Unaligned sizes:
BEFORE:
2 KB: 68.3200 ms
3 KB: 79.3600 ms
5 KB: 76.6400 ms
9 KB: 90.8800 ms
17 KB: 116. ms
AFTER:
2 KB: 31.0400 ms
3 KB: 32. ms
5 KB: 30.8800 ms
9 KB: 30.5600 ms
17 KB: 29.6000 ms

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/si_cmd_buffer.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 7ff1717022..a0562f9cb5 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1215,6 +1215,8 @@ void si_cp_dma_buffer_copy(struct radv_cmd_buffer 
*cmd_buffer,
  size + skipped_size + realign_size,
  _flags);
 
+   dma_flags &= ~CP_DMA_SYNC;
+
si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
   byte_count, dma_flags);
 
-- 
2.19.0

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[Mesa-dev] [PATCH] radv: adjust the CmdUpdateBuffer threshold for optimal performance

[Samuel Pitoiset]

According to my benchmark results, it appears that we should
reduce the threshold to 1024.

BEFORE:
1 KB: 68.656000 ms
2 KB: 118.368000 ms

AFTER:
1 KB: 31.76 ms
2 KB: 29.84 ms

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_meta_buffer.c | 2 +-
 src/amd/vulkan/radv_private.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_meta_buffer.c 
b/src/amd/vulkan/radv_meta_buffer.c
index f1887e3318..8726d36f5f 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -513,7 +513,7 @@ void radv_CmdUpdateBuffer(
if (!dataSize)
return;
 
-   if (dataSize < RADV_BUFFER_OPS_CS_THRESHOLD) {
+   if (dataSize < RADV_BUFFER_UPDATE_THRESHOLD) {
si_emit_cache_flush(cmd_buffer);
 
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, 
dst_buffer->bo);
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index a649835959..15a66bdc1b 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -108,6 +108,8 @@ typedef uint32_t xcb_window_t;
  */
 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
 
+#define RADV_BUFFER_UPDATE_THRESHOLD 1024
+
 enum radv_mem_heap {
RADV_MEM_HEAP_VRAM,
RADV_MEM_HEAP_VRAM_CPU_ACCESS,
-- 
2.19.0

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Re: [Mesa-dev] [PATCH] vl: reorder H264 profiles

[Christian König]

Am 26.09.2018 um 00:11 schrieb boyuan.zh...@amd.com:

From: Boyuan Zhang 

Fix the wrong h264 profiles order. Previously, the constrained baseline was
added in between baseline and main profiles, which breaked the logic in
radeon/vce when converting from pipe_video_profile to profile_idc


I think it would be better to use a switch/case in radeon/vce or even 
better make a helper function which converts between 
PIPE_VIDEO_PROFILE_MPEG4_AVC_* and the profile_idc from the specification.


Christian.



Signed-off-by: Boyuan Zhang 
---
  src/gallium/include/pipe/p_video_enums.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/include/pipe/p_video_enums.h 
b/src/gallium/include/pipe/p_video_enums.h
index b5b8b06228..260f47ea8a 100644
--- a/src/gallium/include/pipe/p_video_enums.h
+++ b/src/gallium/include/pipe/p_video_enums.h
@@ -55,8 +55,8 @@ enum pipe_video_profile
 PIPE_VIDEO_PROFILE_VC1_SIMPLE,
 PIPE_VIDEO_PROFILE_VC1_MAIN,
 PIPE_VIDEO_PROFILE_VC1_ADVANCED,
-   PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE,
 PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE,
+   PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE,
 PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN,
 PIPE_VIDEO_PROFILE_MPEG4_AVC_EXTENDED,
 PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH,


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Re: [Mesa-dev] [PATCH] radv: Do not use multiple draws for multisample copies.

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 9/26/18 8:32 AM, Bas Nieuwenhuizen wrote:

Use sample rate shading instead, should give better locality.
---
  src/amd/vulkan/radv_meta_blit2d.c | 62 +++
  1 file changed, 5 insertions(+), 57 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_blit2d.c 
b/src/amd/vulkan/radv_meta_blit2d.c
index d2975532d4b..45eb4b309e4 100644
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -379,24 +379,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer 
*cmd_buffer,
  
  
  
-			if (log2_samples > 0) {

-   for (uint32_t sample = 0; sample < 
src_img->image->info.samples; sample++) {
-   uint32_t sample_mask = 1 << sample;
-   
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
- 
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
- 
VK_SHADER_STAGE_FRAGMENT_BIT, 20, 4,
- );
-
-   
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
- 
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
- 
VK_SHADER_STAGE_FRAGMENT_BIT, 24, 4,
- _mask);
-
-   
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
-   }
-   }
-   else
-   
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
+   radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 
1, 0, 0);

radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
  
  fail_pipeline:

@@ -520,10 +503,7 @@ build_nir_texel_fetch(struct nir_builder *b, struct 
radv_device *device,
tex_pos_3d = nir_vec(b, chans, 3);
}
if (is_multisampled) {
-   sample_idx = nir_intrinsic_instr_create(b->shader, 
nir_intrinsic_load_push_constant);
-   nir_intrinsic_set_base(sample_idx, 20);
-   nir_intrinsic_set_range(sample_idx, 4);
-   sample_idx->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
+   sample_idx = nir_intrinsic_instr_create(b->shader, 
nir_intrinsic_load_sample_id);
sample_idx->num_components = 1;
nir_ssa_dest_init(_idx->instr, _idx->dest, 1, 32, 
"sample_idx");
nir_builder_instr_insert(b, _idx->instr);
@@ -605,27 +585,6 @@ static const VkPipelineVertexInputStateCreateInfo 
normal_vi_create_info = {
.vertexAttributeDescriptionCount = 0,
  };
  
-static void

-build_nir_store_sample_mask(struct nir_builder *b)
-{
-   nir_intrinsic_instr *sample_mask = 
nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
-   nir_intrinsic_set_base(sample_mask, 24);
-   nir_intrinsic_set_range(sample_mask, 4);
-   sample_mask->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
-   sample_mask->num_components = 1;
-   nir_ssa_dest_init(_mask->instr, _mask->dest, 1, 32, 
"sample_mask");
-   nir_builder_instr_insert(b, _mask->instr);
-
-   const struct glsl_type *sample_mask_out_type = glsl_uint_type();
-
-   nir_variable *sample_mask_out =
-   nir_variable_create(b->shader, nir_var_shader_out,
-   sample_mask_out_type, "sample_mask_out");
-   sample_mask_out->data.location = FRAG_RESULT_SAMPLE_MASK;
-
-   nir_store_var(b, sample_mask_out, _mask->dest.ssa, 0x1);
-}
-
  static nir_shader *
  build_nir_copy_fragment_shader(struct radv_device *device,
 texel_fetch_build_func txf_func, const char* 
name, bool is_3d,
@@ -646,10 +605,6 @@ build_nir_copy_fragment_shader(struct radv_device *device,
  vec4, "f_color");
color_out->data.location = FRAG_RESULT_DATA0;
  
-	if (is_multisampled) {

-   build_nir_store_sample_mask();
-   }
-
nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(, tex_pos_in));
nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
  
@@ -679,10 +634,6 @@ build_nir_copy_fragment_shader_depth(struct radv_device *device,

  vec4, "f_color");
color_out->data.location = FRAG_RESULT_DEPTH;
  
-	if (is_multisampled) {

-   build_nir_store_sample_mask();
-   }
-
nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(, tex_pos_in));
nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
  
@@ -712,10 +663,6 @@ 

Re: [Mesa-dev] [PATCH 3/8] anv/android: add GetAndroidHardwareBufferPropertiesANDROID

[Jason Ekstrand]

On Mon, Aug 27, 2018 at 2:22 AM Jason Ekstrand  wrote:

> On Sun, Aug 26, 2018 at 11:54 PM Tapani Pälli 
> wrote:
>
>>
>>
>> On 08/24/2018 05:04 PM, Jason Ekstrand wrote:
>> > On Fri, Aug 24, 2018 at 12:08 AM Tapani Pälli > > > wrote:
>> >
>> >
>> >
>> > On 08/22/2018 05:18 PM, Jason Ekstrand wrote:
>> >  > On Tue, Aug 21, 2018 at 3:27 AM Tapani Pälli
>> > mailto:tapani.pa...@intel.com>
>> >  > >>
>> > wrote:
>> >  >
>> >  > When adding YUV support, we need to figure out
>> > implementation-defined
>> >  > external format identifier.
>> >  >
>> >  > Signed-off-by: Tapani Pälli > > 
>> >  >  tapani.pa...@intel.com>>>
>> >  > ---
>> >  >   src/intel/vulkan/anv_android.c | 99
>> >  > ++
>> >  >   1 file changed, 99 insertions(+)
>> >  >
>> >  > diff --git a/src/intel/vulkan/anv_android.c
>> >  > b/src/intel/vulkan/anv_android.c
>> >  > index 46c41d57861..7d0eb588e2b 100644
>> >  > --- a/src/intel/vulkan/anv_android.c
>> >  > +++ b/src/intel/vulkan/anv_android.c
>> >  > @@ -29,6 +29,8 @@
>> >  >   #include 
>> >  >
>> >  >   #include "anv_private.h"
>> >  > +#include "vk_format_info.h"
>> >  > +#include "vk_util.h"
>> >  >
>> >  >   static int anv_hal_open(const struct hw_module_t* mod,
>> > const char*
>> >  > id, struct hw_device_t** dev);
>> >  >   static int anv_hal_close(struct hw_device_t *dev);
>> >  > @@ -96,6 +98,103 @@ anv_hal_close(struct hw_device_t *dev)
>> >  >  return -1;
>> >  >   }
>> >  >
>> >  > +static VkResult
>> >  > +get_ahw_buffer_format_properties(
>> >  > +   VkDevice device_h,
>> >  > +   const struct AHardwareBuffer *buffer,
>> >  > +   VkAndroidHardwareBufferFormatPropertiesANDROID
>> *pProperties)
>> >  > +{
>> >  > +   ANV_FROM_HANDLE(anv_device, device, device_h);
>> >  > +
>> >  > +   /* Get a description of buffer contents . */
>> >  > +   AHardwareBuffer_Desc desc;
>> >  > +   AHardwareBuffer_describe(buffer, );
>> >  > +
>> >  > +   /* Verify description. */
>> >  > +   uint64_t gpu_usage =
>> >  > +  AHARDWAREBUFFER_USAGE_GPU_SAMPLED_IMAGE |
>> >  > +  AHARDWAREBUFFER_USAGE_GPU_COLOR_OUTPUT |
>> >  > +  AHARDWAREBUFFER_USAGE_GPU_DATA_BUFFER;
>> >  > +
>> >  > +   /* "Buffer must be a valid Android hardware buffer object
>> > with
>> >  > at least
>> >  > +* one of the AHARDWAREBUFFER_USAGE_GPU_* usage flags."
>> >  > +*/
>> >  > +   if (!(desc.usage & (gpu_usage)))
>> >  > +  return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
>> >  > +
>> >  > +   /* Fill properties fields based on description. */
>> >  > +   VkAndroidHardwareBufferFormatPropertiesANDROID *p =
>> > pProperties;
>> >  > +
>> >  > +   p->pNext = NULL;
>> >  >
>> >  >
>> >  > You shouldn't be overwriting pNext.  That's used by the client to
>> > let
>> >  > them chain in multiple structs to fill out in case Google ever
>> > extends
>> >  > this extension.  Also, while we're here, it'd be good to throw
>> in an
>> >  > assert that p->sType is the right thing.
>> >
>> > Yes of course, will remove.
>> >
>> >  > +   p->format = vk_format_from_android(desc.format);
>> >  > +   p->externalFormat = 1; /* XXX */
>> >  > +
>> >  > +   const struct anv_format *anv_format =
>> > anv_get_format(p->format);
>> >  > +   struct anv_physical_device *physical_device =
>> >  > +  >instance->physicalDevice;
>> >  > +   const struct gen_device_info *devinfo =
>> > _device->info;
>> >  >
>> >  >
>> >  > If all you need is devinfo, that's avilable in the device; you
>> don't
>> >  > need to get the physical device for it.  Should be device->info.
>> >
>> > OK
>> >
>> >  > +
>> >  > +   p->formatFeatures =
>> >  > +  anv_get_image_format_features(devinfo, p->format,
>> >  > +anv_format,
>> >  > VK_IMAGE_TILING_OPTIMAL);
>> >  > +
>> >  > +   /* "The formatFeatures member *must* include
>> >  > +*  VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT and at least one
>> of
>> >  > +*  VK_FORMAT_FEATURE_MIDPOINT_CHROMA_SAMPLES_BIT or
>> >  > +*  VK_FORMAT_FEATURE_COSITED_CHROMA_SAMPLES_BIT"
>> >  > +*/
>> >  > +   p->formatFeatures |=
>> >  > +  

Re: [Mesa-dev] [PATCH] mesa/st: In the precense of integer buffers enable per buffer blending

[Gert Wollny]

Am Dienstag, den 25.09.2018, 10:20 -0400 schrieb Ilia Mirkin:
> I haven't double-checked yet, but doesn't this result in a reduction
> of functionality for pre-independent-blend GPUs (like the early
> NVIDIA
> Tesla series)? Configuring blending for an integer RT does nothing on
> NVIDIA hardware, so it all works out there just fine...
Unfortunately I can't test this ...

> 
> Perhaps both patches should just be reverted and keep things as they
> were, and let drivers worry about this?
Do as you see fit, my only concern is that there are no regressions,
and if the two patches together still result in regressions then it is
indeed better to revert, 

best, 
Gert


> 
> On Mon, Sep 17, 2018 at 10:06 PM, Marek Olšák 
> wrote:
> > Reviewed-by: Marek Olšák 
> > 
> > Marek
> > 
> > On Thu, Sep 13, 2018 at 4:06 AM, Gert Wollny 
> > wrote:
> > > From: Gert Wollny 
> > > 
> > > Since blending will be disabled later for integer formats we have
> > > to
> > > consider that in the case of a mixed set of integer/non-integer
> > > format
> > > buffers blending must be handled on a per buffer basis.
> > > 
> > > Fixes on r600:
> > >   dEQP-GLES31.functional.draw_buffers_indexed.random.
> > >   max_required_draw_buffers.13
> > > 
> > > Fixes:  8fb966688bc1053a48e8ee7f7394ce030bcfd345
> > >   st/mesa: Disable blending for integer formats.
> > > Signed-off-by: Gert Wollny 
> > > ---
> > >  src/mesa/state_tracker/st_atom_blend.c | 6 ++
> > >  1 file changed, 6 insertions(+)
> > > 
> > > diff --git a/src/mesa/state_tracker/st_atom_blend.c
> > > b/src/mesa/state_tracker/st_atom_blend.c
> > > index 804de2f154..d6a9562d25 100644
> > > --- a/src/mesa/state_tracker/st_atom_blend.c
> > > +++ b/src/mesa/state_tracker/st_atom_blend.c
> > > @@ -139,6 +139,12 @@ blend_per_rt(const struct gl_context *ctx,
> > > unsigned num_cb)
> > >/* this can only happen if GL_ARB_draw_buffers_blend is
> > > enabled */
> > >return GL_TRUE;
> > > }
> > > +   if (ctx->DrawBuffer->_IntegerBuffers &&
> > > +   (ctx->DrawBuffer->_IntegerBuffers != cb_mask)) {
> > > +  /* If there is a mix of integer/non-integer buffers then
> > > blending
> > > +   * must be handled on a per buffer basis. */
> > > +  return GL_TRUE;
> > > +   }
> > > return GL_FALSE;
> > >  }
> > > 
> > > --
> > > 2.16.4
> > > 
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[Mesa-dev] [Bug 108062] Mesa 18.2.0 and Mesa 18.2.1 RADV Freeze

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=108062

Andreas Radke  changed:

   What|Removed |Added

 CC||andy...@archlinux.org

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[Mesa-dev] [PATCH] radv: Do not use multiple draws for multisample copies.

[Bas Nieuwenhuizen]

Use sample rate shading instead, should give better locality.
---
 src/amd/vulkan/radv_meta_blit2d.c | 62 +++
 1 file changed, 5 insertions(+), 57 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_blit2d.c 
b/src/amd/vulkan/radv_meta_blit2d.c
index d2975532d4b..45eb4b309e4 100644
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -379,24 +379,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer 
*cmd_buffer,
 
 
 
-   if (log2_samples > 0) {
-   for (uint32_t sample = 0; sample < 
src_img->image->info.samples; sample++) {
-   uint32_t sample_mask = 1 << sample;
-   
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
- 
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
- 
VK_SHADER_STAGE_FRAGMENT_BIT, 20, 4,
- );
-
-   
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
- 
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
- 
VK_SHADER_STAGE_FRAGMENT_BIT, 24, 4,
- _mask);
-
-   
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
-   }
-   }
-   else
-   
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
+   radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 
1, 0, 0);

radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
 
 fail_pipeline:
@@ -520,10 +503,7 @@ build_nir_texel_fetch(struct nir_builder *b, struct 
radv_device *device,
tex_pos_3d = nir_vec(b, chans, 3);
}
if (is_multisampled) {
-   sample_idx = nir_intrinsic_instr_create(b->shader, 
nir_intrinsic_load_push_constant);
-   nir_intrinsic_set_base(sample_idx, 20);
-   nir_intrinsic_set_range(sample_idx, 4);
-   sample_idx->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
+   sample_idx = nir_intrinsic_instr_create(b->shader, 
nir_intrinsic_load_sample_id);
sample_idx->num_components = 1;
nir_ssa_dest_init(_idx->instr, _idx->dest, 1, 32, 
"sample_idx");
nir_builder_instr_insert(b, _idx->instr);
@@ -605,27 +585,6 @@ static const VkPipelineVertexInputStateCreateInfo 
normal_vi_create_info = {
.vertexAttributeDescriptionCount = 0,
 };
 
-static void
-build_nir_store_sample_mask(struct nir_builder *b)
-{
-   nir_intrinsic_instr *sample_mask = 
nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
-   nir_intrinsic_set_base(sample_mask, 24);
-   nir_intrinsic_set_range(sample_mask, 4);
-   sample_mask->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
-   sample_mask->num_components = 1;
-   nir_ssa_dest_init(_mask->instr, _mask->dest, 1, 32, 
"sample_mask");
-   nir_builder_instr_insert(b, _mask->instr);
-
-   const struct glsl_type *sample_mask_out_type = glsl_uint_type();
-
-   nir_variable *sample_mask_out =
-   nir_variable_create(b->shader, nir_var_shader_out,
-   sample_mask_out_type, "sample_mask_out");
-   sample_mask_out->data.location = FRAG_RESULT_SAMPLE_MASK;
-
-   nir_store_var(b, sample_mask_out, _mask->dest.ssa, 0x1);
-}
-
 static nir_shader *
 build_nir_copy_fragment_shader(struct radv_device *device,
texel_fetch_build_func txf_func, const char* 
name, bool is_3d,
@@ -646,10 +605,6 @@ build_nir_copy_fragment_shader(struct radv_device *device,
  vec4, "f_color");
color_out->data.location = FRAG_RESULT_DATA0;
 
-   if (is_multisampled) {
-   build_nir_store_sample_mask();
-   }
-
nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(, tex_pos_in));
nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
 
@@ -679,10 +634,6 @@ build_nir_copy_fragment_shader_depth(struct radv_device 
*device,
  vec4, "f_color");
color_out->data.location = FRAG_RESULT_DEPTH;
 
-   if (is_multisampled) {
-   build_nir_store_sample_mask();
-   }
-
nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(, tex_pos_in));
nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
 
@@ -712,10 +663,6 @@ build_nir_copy_fragment_shader_stencil(struct radv_device 
*device,
  

Re: [Mesa-dev] [PATCH 1/2] anv: s/batch/value_bo/ on anv_device_init_hiz_clear_batch

[Jason Ekstrand]

Rb

On September 26, 2018 01:27:05 Jordan Justen  wrote:


Signed-off-by: Jordan Justen 
Cc: Jason Ekstrand 
---
src/intel/vulkan/anv_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 4219a073d2d..265fc4a3347 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1566,7 +1566,7 @@ vk_priority_to_gen(int priority)
}

static void
-anv_device_init_hiz_clear_batch(struct anv_device *device)
+anv_device_init_hiz_clear_value_bo(struct anv_device *device)
{
   anv_bo_init_new(>hiz_clear_bo, device, 4096);
   uint32_t *map = anv_gem_mmap(device, device->hiz_clear_bo.gem_handle,
@@ -1802,7 +1802,7 @@ VkResult anv_CreateDevice(
   anv_device_init_trivial_batch(device);

   if (device->info.gen >= 10)
-  anv_device_init_hiz_clear_batch(device);
+  anv_device_init_hiz_clear_value_bo(device);

   anv_scratch_pool_init(device, >scratch_pool);

--
2.18.0




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Re: [Mesa-dev] [RESEND PATCH 0/5] i965: More cmod propagation

[Thomas Helland]

Hi Ian,

Do you have these in a branch somewhere?
Do you also have a branch somewhere of the PRE for compares?
I'll try to have a look at these, and the sign(x)*y series this evening.
I will probably only be able to review the simplest patches,
but something is probably better than nothing, I guess.

- Thomas

Den tir. 11. sep. 2018 kl. 01:32 skrev Ian Romanick :
>
> Bump
>
> On 08/29/2018 11:40 AM, Ian Romanick wrote:
> > This is mostly a resend of a series that I originally sent out around
> > the end of June.  I updated some of the shader-db results, and I dropped
> > one patch (i965/fs: Allow Boolean conditions in CSEL generation).  I
> > decided that I want to try to acomplish that with a different method.
> > That's going to take a bit more work, and I didn't want to hold up the
> > rest of the series.
> >
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