Re: [Mesa-dev] [PATCH 1/2] Change a few frequented uses of DEBUG to !NDEBUG
Marek,
sure, for that part:
Reviewed-by: Mathias Fröhlich
Well, there are really magnitudes of DEBUG defines that are inactive since
meson.
Either let meson builds also define DEBUG or lets
sed -i 's,#ifdef DEBUG,#ifndef NDEBUG,g'
them now?
best
Mathias
On Friday, 10 May 2019 07:21:15 CEST Marek Olšák wrote:
> From: Marek Olšák
>
> debugoptimized builds don't define NDEBUG, but they also don't define
> DEBUG. We want to enable cheap debug code for these builds.
> I only chose those occurences that I care about.
> ---
> src/gallium/auxiliary/tgsi/tgsi_ureg.c | 2 +-
> src/gallium/drivers/radeonsi/si_descriptors.c | 2 +-
> src/gallium/drivers/radeonsi/si_pipe.h | 2 +-
> src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 6 +++---
> src/gallium/drivers/radeonsi/si_state.c | 4 ++--
> src/mesa/main/context.c | 2 +-
> src/mesa/main/debug.c | 4 ++--
> src/mesa/main/errors.c | 6 +++---
> src/mesa/main/feedback.c| 2 +-
> src/mesa/main/formats.c | 2 --
> src/mesa/main/imports.c | 4 ++--
> src/mesa/main/mtypes.h | 2 +-
> src/mesa/main/shaderapi.c | 2 +-
> src/mesa/state_tracker/st_atom_framebuffer.c| 2 +-
> src/mesa/state_tracker/st_format.c | 2 +-
> src/mesa/vbo/vbo_exec.h | 2 +-
> src/mesa/vbo/vbo_exec_api.c | 6 +++---
> src/util/slab.c | 4 ++--
> 18 files changed, 27 insertions(+), 29 deletions(-)
>
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
> b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
> index c1c8851486e..55ed7fc62b4 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
> @@ -1234,21 +1234,21 @@ ureg_emit_dst( struct ureg_program *ureg,
> }
>
> assert(n == size);
> }
>
>
> static void validate( enum tgsi_opcode opcode,
>unsigned nr_dst,
>unsigned nr_src )
> {
> -#ifdef DEBUG
> +#ifndef NDEBUG
> const struct tgsi_opcode_info *info = tgsi_get_opcode_info( opcode );
> assert(info);
> if (info) {
>assert(nr_dst == info->num_dst);
>assert(nr_src == info->num_src);
> }
> #endif
> }
>
> struct ureg_emit_insn_result
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
> b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 6a4dcacc0f3..68b5430446e 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -953,21 +953,21 @@ static void si_bind_sampler_states(struct pipe_context
> *ctx,
> return;
>
> for (i = 0; i < count; i++) {
> unsigned slot = start + i;
> unsigned desc_slot = si_get_sampler_slot(slot);
>
> if (!sstates[i] ||
> sstates[i] == samplers->sampler_states[slot])
> continue;
>
> -#ifdef DEBUG
> +#ifndef NDEBUG
> assert(sstates[i]->magic == SI_SAMPLER_STATE_MAGIC);
> #endif
> samplers->sampler_states[slot] = sstates[i];
>
> /* If FMASK is bound, don't overwrite it.
>* The sampler state will be set after FMASK is unbound.
>*/
> struct si_sampler_view *sview =
> (struct si_sampler_view *)samplers->views[slot];
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
> b/src/gallium/drivers/radeonsi/si_pipe.h
> index 4061bf139fb..2f1acec8ef2 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.h
> +++ b/src/gallium/drivers/radeonsi/si_pipe.h
> @@ -596,21 +596,21 @@ struct si_sampler_view {
> ubyte base_level;
> ubyte block_width;
> bool is_stencil_sampler;
> bool is_integer;
> bool dcc_incompatible;
> };
>
> #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
>
> struct si_sampler_state {
> -#ifdef DEBUG
> +#ifndef NDEBUG
> unsignedmagic;
> #endif
> uint32_tval[4];
> uint32_tinteger_val[4];
> uint32_tupgraded_depth_val[4];
> };
>
> struct si_cs_shader_state {
> struct si_compute *program;
> struct si_compute *emitted_program;
> diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
> b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
> index 3ec919dd23b..f70c41ca8c4 100644
> --- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
> +++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
> @@ -644,21 +644,21 @@ static void emit_declaration(struct
> lp_build_tgsi_context *bld_base,
>
[Mesa-dev] [Bug 110673] amdgpu hevc encoding problems: segment fault and contents of garbage
https://bugs.freedesktop.org/show_bug.cgi?id=110673 --- Comment #4 from zhoulei --- (In reply to Boyuan Zhang from comment #3) > Hi Zhoulei, > > Please use the latest patch to test again: > https://lists.freedesktop.org/archives/mesa-dev/2019-May/219613.html > > Regards, > Boyuan I have tested this patch on RX580, it works. Issue#1 has been fixed. Thanks. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radeonsi: fix timestamp queries for compute-only contexts
On Mon, 2019-05-27 at 16:10 -0400, Marek Olšák wrote:
> From: Marek Olšák
>
> ---
> src/gallium/drivers/radeonsi/si_fence.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_fence.c
> b/src/gallium/drivers/radeonsi/si_fence.c
> index 1d67fd87b90..6d914a1b184 100644
> --- a/src/gallium/drivers/radeonsi/si_fence.c
> +++ b/src/gallium/drivers/radeonsi/si_fence.c
> @@ -72,31 +72,33 @@ void si_cp_release_mem(struct si_context *ctx, struct
> radeon_cmdbuf *cs,
> struct si_resource *buf, uint64_t va,
> uint32_t new_fence, unsigned query_type)
> {
> unsigned op = EVENT_TYPE(event) |
> EVENT_INDEX(event == V_028A90_CS_DONE ||
> event == V_028A90_PS_DONE ? 6 : 5) |
> event_flags;
> unsigned sel = EOP_DST_SEL(dst_sel) |
> EOP_INT_SEL(int_sel) |
> EOP_DATA_SEL(data_sel);
> + bool compute_ib = !ctx->has_graphics ||
> + cs == ctx->prim_discard_compute_cs;
>
> - if (ctx->chip_class >= GFX9 || cs == ctx->prim_discard_compute_cs) {
> + if (ctx->chip_class >= GFX9 ||
> + (compute_ib && ctx->chip_class >= GFX7)) {
> /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
>* counters) must immediately precede every timestamp event to
>* prevent a GPU hang on GFX9.
>*
>* Occlusion queries don't need to do it here, because they
>* always do ZPASS_DONE before the timestamp.
>*/
> - if (ctx->chip_class == GFX9 &&
> - cs != ctx->prim_discard_compute_cs &&
> + if (ctx->chip_class == GFX9 && !compute_ib &&
> query_type != PIPE_QUERY_OCCLUSION_COUNTER &&
> query_type != PIPE_QUERY_OCCLUSION_PREDICATE &&
> query_type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
> struct si_resource *scratch = ctx->eop_bug_scratch;
>
> assert(16 * ctx->screen->info.num_render_backends <=
> scratch->b.b.width0);
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
> radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) |
> EVENT_INDEX(1));
> radeon_emit(cs, scratch->gpu_address);
Fixes clover timestamp queries, at least on raven.
Tested-by: Jan Vesely
Jan
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Re: [Mesa-dev] [PATCH] gallivm: fix default cbuf info.
Am 27.05.19 um 11:39 schrieb Juan A. Suarez Romero:
> On Fri, 2019-05-24 at 03:08 +0200, srol...@vmware.com wrote:
>> From: Roland Scheidegger
>>
>> The default null_output really needs to be static, otherwise the values
>> we'll eventually get later are doubly random (they are not initialized,
>> and even if they were it's a pointer to a local stack variable).
>> VMware bug 2349556.
>
>
> Shouldn't this be CC to @stable ?
I forgot to mention this, but it should not actually be an issue in the
public branch, since that part of the information gathered there isn't
actually used by llvmpipe, hence if it contains garbage or not doesn't
matter. So there isn't really any need for stable.
But we have a branch where llvmpipe uses it.
Roland
>
>
>> ---
>> src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
>> b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
>> index b4e3c2fbc8..9fc9b8c77e 100644
>> --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
>> +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
>> @@ -608,7 +608,7 @@ finished:
>> */
>>
>> for (index = 0; index < PIPE_MAX_COLOR_BUFS; ++index) {
>> - const struct lp_tgsi_channel_info null_output[4];
>> + static const struct lp_tgsi_channel_info null_output[4];
>>info->cbuf[index] = null_output;
>> }
>>
>
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Re: [Mesa-dev] [PATCH] radeonsi: allow query functions for compute-only contexts
On Mon, May 20, 2019 at 1:04 PM Jan Vesely wrote:
> On Mon, May 13, 2019 at 6:40 PM Marek Olšák wrote:
> >
> > From: Marek Olšák
> >
> > ---
> > src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
> > src/gallium/drivers/radeonsi/si_query.c | 7 ---
> > 2 files changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
> b/src/gallium/drivers/radeonsi/si_pipe.c
> > index aa7f012f071..95280675506 100644
> > --- a/src/gallium/drivers/radeonsi/si_pipe.c
> > +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> > @@ -482,29 +482,29 @@ static struct pipe_context
> *si_create_context(struct pipe_screen *screen,
> > sctx->b.set_device_reset_callback = si_set_device_reset_callback;
> >
> > si_init_all_descriptors(sctx);
> > si_init_buffer_functions(sctx);
> > si_init_clear_functions(sctx);
> > si_init_blit_functions(sctx);
> > si_init_compute_functions(sctx);
> > si_init_compute_blit_functions(sctx);
> > si_init_debug_functions(sctx);
> > si_init_fence_functions(sctx);
> > + si_init_query_functions(sctx);
> > si_init_state_compute_functions(sctx);
> >
> > if (sscreen->debug_flags & DBG(FORCE_DMA))
> > sctx->b.resource_copy_region = sctx->dma_copy;
> >
> > /* Initialize graphics-only context functions. */
> > if (sctx->has_graphics) {
> > si_init_context_texture_functions(sctx);
> > - si_init_query_functions(sctx);
> > si_init_msaa_functions(sctx);
> > si_init_shader_functions(sctx);
> > si_init_state_functions(sctx);
> > si_init_streamout_functions(sctx);
> > si_init_viewport_functions(sctx);
> >
> > sctx->blitter = util_blitter_create(>b);
> > if (sctx->blitter == NULL)
> > goto fail;
> > sctx->blitter->skip_viewport_restore = true;
> > diff --git a/src/gallium/drivers/radeonsi/si_query.c
> b/src/gallium/drivers/radeonsi/si_query.c
> > index d98bea2eeb3..3e357e8b6c0 100644
> > --- a/src/gallium/drivers/radeonsi/si_query.c
> > +++ b/src/gallium/drivers/radeonsi/si_query.c
> > @@ -1879,23 +1879,24 @@ static int si_get_driver_query_group_info(struct
> pipe_screen *screen,
> >
> > void si_init_query_functions(struct si_context *sctx)
> > {
> > sctx->b.create_query = si_create_query;
> > sctx->b.create_batch_query = si_create_batch_query;
> > sctx->b.destroy_query = si_destroy_query;
> > sctx->b.begin_query = si_begin_query;
> > sctx->b.end_query = si_end_query;
> > sctx->b.get_query_result = si_get_query_result;
> > sctx->b.get_query_result_resource = si_get_query_result_resource;
> > - sctx->atoms.s.render_cond.emit = si_emit_query_predication;
> >
> > - if (((struct
> si_screen*)sctx->b.screen)->info.num_render_backends > 0)
> > - sctx->b.render_condition = si_render_condition;
> > + if (sctx->has_graphics) {
> > + sctx->atoms.s.render_cond.emit =
> si_emit_query_predication;
> > + sctx->b.render_condition = si_render_condition;
> > + }
> >
> > LIST_INITHEAD(>active_queries);
> > }
> >
> > void si_init_screen_query_functions(struct si_screen *sscreen)
> > {
> > sscreen->b.get_driver_query_info = si_get_driver_query_info;
> > sscreen->b.get_driver_query_group_info =
> si_get_driver_query_group_info;
> > }
> > --
> > 2.17.1
>
> Hi,
>
> this patch hangs query requests (tested on carrizo and raven).
>
I've sent a possible fix to mesa-dev: "radeonsi: fix timestamp queries for
compute-only contexts"
Marek
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[Mesa-dev] [PATCH] u_blitter: don't fail mipmap generation for depth formats containing stencil
From: Marek Olšák Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=109754 Cc: 19.0 19.1 --- src/gallium/auxiliary/util/u_blitter.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/util/u_blitter.c b/src/gallium/auxiliary/util/u_blitter.c index e19fde9873d..3dc49cd0958 100644 --- a/src/gallium/auxiliary/util/u_blitter.c +++ b/src/gallium/auxiliary/util/u_blitter.c @@ -2052,21 +2052,22 @@ void util_blitter_generate_mipmap(struct blitter_context *blitter, const struct util_format_description *desc = util_format_description(format); unsigned src_level; unsigned target = tex->target; if (ctx->cube_as_2darray && (target == PIPE_TEXTURE_CUBE || target == PIPE_TEXTURE_CUBE_ARRAY)) target = PIPE_TEXTURE_2D_ARRAY; assert(tex->nr_samples <= 1); - assert(!util_format_has_stencil(desc)); + /* Disallow stencil formats without depth. */ + assert(!util_format_has_stencil(desc) || util_format_has_depth(desc)); is_depth = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS; /* Check whether the states are properly saved. */ util_blitter_set_running_flag(blitter); blitter_check_saved_vertex_states(ctx); blitter_check_saved_fragment_states(ctx); blitter_check_saved_textures(ctx); blitter_check_saved_fb_state(ctx); blitter_disable_render_cond(ctx); -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] radv add radv_get_resolve_pipeline() in the compute path
r-b for the series
On Mon, May 27, 2019 at 5:39 PM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_meta_resolve_cs.c | 56 +--
> 1 file changed, 36 insertions(+), 20 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c
> b/src/amd/vulkan/radv_meta_resolve_cs.c
> index 76612672b1c..67df4800023 100644
> --- a/src/amd/vulkan/radv_meta_resolve_cs.c
> +++ b/src/amd/vulkan/radv_meta_resolve_cs.c
> @@ -313,6 +313,39 @@ radv_device_finish_meta_resolve_compute_state(struct
> radv_device *device)
>>alloc);
> }
>
> +static VkPipeline *
> +radv_get_resolve_pipeline(struct radv_cmd_buffer *cmd_buffer,
> + struct radv_image *src_image)
> +{
> + struct radv_device *device = cmd_buffer->device;
> + struct radv_meta_state *state = >meta_state;
> + uint32_t samples = src_image->info.samples;
> + uint32_t samples_log2 = ffs(samples) - 1;
> + VkPipeline *pipeline;
> +
> + if (vk_format_is_int(src_image->vk_format))
> + pipeline =
> >resolve_compute.rc[samples_log2].i_pipeline;
> + else if (vk_format_is_srgb(src_image->vk_format))
> + pipeline =
> >resolve_compute.rc[samples_log2].srgb_pipeline;
> + else
> + pipeline = >resolve_compute.rc[samples_log2].pipeline;
> +
> + if (!*pipeline) {
> + VkResult ret;
> +
> + ret = create_resolve_pipeline(device, samples,
> +
> vk_format_is_int(src_image->vk_format),
> +
> vk_format_is_srgb(src_image->vk_format),
> + pipeline);
> + if (ret != VK_SUCCESS) {
> + cmd_buffer->record_result = ret;
> + return NULL;
> + }
> + }
> +
> + return pipeline;
> +}
> +
> static void
> emit_resolve(struct radv_cmd_buffer *cmd_buffer,
> struct radv_image_view *src_iview,
> @@ -322,8 +355,8 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
> const VkExtent2D *resolve_extent)
> {
> struct radv_device *device = cmd_buffer->device;
> - const uint32_t samples = src_iview->image->info.samples;
> - const uint32_t samples_log2 = ffs(samples) - 1;
> + VkPipeline *pipeline;
> +
> radv_meta_push_descriptor_set(cmd_buffer,
> VK_PIPELINE_BIND_POINT_COMPUTE,
>
> device->meta_state.resolve_compute.p_layout,
> @@ -359,24 +392,7 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
> }
> });
>
> - VkPipeline *pipeline;
> - if (vk_format_is_int(src_iview->image->vk_format))
> - pipeline =
> >meta_state.resolve_compute.rc[samples_log2].i_pipeline;
> - else if (vk_format_is_srgb(src_iview->image->vk_format))
> - pipeline =
> >meta_state.resolve_compute.rc[samples_log2].srgb_pipeline;
> - else
> - pipeline =
> >meta_state.resolve_compute.rc[samples_log2].pipeline;
> -
> - if (!*pipeline) {
> - VkResult ret = create_resolve_pipeline(device, samples,
> -
> vk_format_is_int(src_iview->image->vk_format),
> -
> vk_format_is_srgb(src_iview->image->vk_format),
> - pipeline);
> - if (ret != VK_SUCCESS) {
> - cmd_buffer->record_result = ret;
> - return;
> - }
> - }
> + pipeline = radv_get_resolve_pipeline(cmd_buffer, src_iview->image);
>
> radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
> VK_PIPELINE_BIND_POINT_COMPUTE, *pipeline);
> --
> 2.21.0
>
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Re: [Mesa-dev] [PATCH] radeonsi: fix timestamp queries for compute-only contexts
Reviewed-by: Bas Nieuwenhuizen
On Mon, May 27, 2019 at 10:10 PM Marek Olšák wrote:
>
> From: Marek Olšák
>
> ---
> src/gallium/drivers/radeonsi/si_fence.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_fence.c
> b/src/gallium/drivers/radeonsi/si_fence.c
> index 1d67fd87b90..6d914a1b184 100644
> --- a/src/gallium/drivers/radeonsi/si_fence.c
> +++ b/src/gallium/drivers/radeonsi/si_fence.c
> @@ -72,31 +72,33 @@ void si_cp_release_mem(struct si_context *ctx, struct
> radeon_cmdbuf *cs,
>struct si_resource *buf, uint64_t va,
>uint32_t new_fence, unsigned query_type)
> {
> unsigned op = EVENT_TYPE(event) |
> EVENT_INDEX(event == V_028A90_CS_DONE ||
> event == V_028A90_PS_DONE ? 6 : 5) |
> event_flags;
> unsigned sel = EOP_DST_SEL(dst_sel) |
>EOP_INT_SEL(int_sel) |
>EOP_DATA_SEL(data_sel);
> + bool compute_ib = !ctx->has_graphics ||
> + cs == ctx->prim_discard_compute_cs;
>
> - if (ctx->chip_class >= GFX9 || cs == ctx->prim_discard_compute_cs) {
> + if (ctx->chip_class >= GFX9 ||
> + (compute_ib && ctx->chip_class >= GFX7)) {
> /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
> * counters) must immediately precede every timestamp event to
> * prevent a GPU hang on GFX9.
> *
> * Occlusion queries don't need to do it here, because they
> * always do ZPASS_DONE before the timestamp.
> */
> - if (ctx->chip_class == GFX9 &&
> - cs != ctx->prim_discard_compute_cs &&
> + if (ctx->chip_class == GFX9 && !compute_ib &&
> query_type != PIPE_QUERY_OCCLUSION_COUNTER &&
> query_type != PIPE_QUERY_OCCLUSION_PREDICATE &&
> query_type !=
> PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
> struct si_resource *scratch = ctx->eop_bug_scratch;
>
> assert(16 * ctx->screen->info.num_render_backends <=
>scratch->b.b.width0);
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
> radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) |
> EVENT_INDEX(1));
> radeon_emit(cs, scratch->gpu_address);
> --
> 2.17.1
>
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[Mesa-dev] [PATCH] radeonsi: fix timestamp queries for compute-only contexts
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_fence.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_fence.c
b/src/gallium/drivers/radeonsi/si_fence.c
index 1d67fd87b90..6d914a1b184 100644
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -72,31 +72,33 @@ void si_cp_release_mem(struct si_context *ctx, struct
radeon_cmdbuf *cs,
struct si_resource *buf, uint64_t va,
uint32_t new_fence, unsigned query_type)
{
unsigned op = EVENT_TYPE(event) |
EVENT_INDEX(event == V_028A90_CS_DONE ||
event == V_028A90_PS_DONE ? 6 : 5) |
event_flags;
unsigned sel = EOP_DST_SEL(dst_sel) |
EOP_INT_SEL(int_sel) |
EOP_DATA_SEL(data_sel);
+ bool compute_ib = !ctx->has_graphics ||
+ cs == ctx->prim_discard_compute_cs;
- if (ctx->chip_class >= GFX9 || cs == ctx->prim_discard_compute_cs) {
+ if (ctx->chip_class >= GFX9 ||
+ (compute_ib && ctx->chip_class >= GFX7)) {
/* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
* counters) must immediately precede every timestamp event to
* prevent a GPU hang on GFX9.
*
* Occlusion queries don't need to do it here, because they
* always do ZPASS_DONE before the timestamp.
*/
- if (ctx->chip_class == GFX9 &&
- cs != ctx->prim_discard_compute_cs &&
+ if (ctx->chip_class == GFX9 && !compute_ib &&
query_type != PIPE_QUERY_OCCLUSION_COUNTER &&
query_type != PIPE_QUERY_OCCLUSION_PREDICATE &&
query_type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
struct si_resource *scratch = ctx->eop_bug_scratch;
assert(16 * ctx->screen->info.num_render_backends <=
scratch->b.b.width0);
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) |
EVENT_INDEX(1));
radeon_emit(cs, scratch->gpu_address);
--
2.17.1
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Re: [Mesa-dev] [PATCH 1/2] Change a few frequented uses of DEBUG to !NDEBUG
Ping On Fri, May 10, 2019 at 1:21 AM Marek Olšák wrote: > From: Marek Olšák > > debugoptimized builds don't define NDEBUG, but they also don't define > DEBUG. We want to enable cheap debug code for these builds. > I only chose those occurences that I care about. > --- > src/gallium/auxiliary/tgsi/tgsi_ureg.c | 2 +- > src/gallium/drivers/radeonsi/si_descriptors.c | 2 +- > src/gallium/drivers/radeonsi/si_pipe.h | 2 +- > src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 6 +++--- > src/gallium/drivers/radeonsi/si_state.c | 4 ++-- > src/mesa/main/context.c | 2 +- > src/mesa/main/debug.c | 4 ++-- > src/mesa/main/errors.c | 6 +++--- > src/mesa/main/feedback.c| 2 +- > src/mesa/main/formats.c | 2 -- > src/mesa/main/imports.c | 4 ++-- > src/mesa/main/mtypes.h | 2 +- > src/mesa/main/shaderapi.c | 2 +- > src/mesa/state_tracker/st_atom_framebuffer.c| 2 +- > src/mesa/state_tracker/st_format.c | 2 +- > src/mesa/vbo/vbo_exec.h | 2 +- > src/mesa/vbo/vbo_exec_api.c | 6 +++--- > src/util/slab.c | 4 ++-- > 18 files changed, 27 insertions(+), 29 deletions(-) > > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] Revert "st/mesa: expose 0 shader binary formats for compat profiles for Qt"
Reviewed-by: Marek Olšák
Marek
On Mon, May 27, 2019 at 6:07 AM Timothy Arceri
wrote:
> This reverts commit 55376cb31e2f495a4d872b4ffce2135c3365b873.
>
> It's been over a year and both QT 5.9.5 and 5.11.0 contained a fix for the
> original issue. It seems i965 only ever applied this workaround to the
> 18.0 branch.
> ---
> src/mesa/state_tracker/st_context.c| 2 +-
> src/mesa/state_tracker/st_extensions.c | 13 +++--
> src/mesa/state_tracker/st_extensions.h | 3 +--
> src/mesa/state_tracker/st_manager.c| 2 +-
> 4 files changed, 6 insertions(+), 14 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_context.c
> b/src/mesa/state_tracker/st_context.c
> index 8f2acafbca3..875be9d0029 100644
> --- a/src/mesa/state_tracker/st_context.c
> +++ b/src/mesa/state_tracker/st_context.c
> @@ -645,7 +645,7 @@ st_create_context_priv(struct gl_context *ctx, struct
> pipe_context *pipe,
>
> PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET));
>
> /* GL limits and extensions */
> - st_init_limits(pipe->screen, >Const, >Extensions, ctx->API);
> + st_init_limits(pipe->screen, >Const, >Extensions);
> st_init_extensions(pipe->screen, >Const,
>>Extensions, >options, ctx->API);
>
> diff --git a/src/mesa/state_tracker/st_extensions.c
> b/src/mesa/state_tracker/st_extensions.c
> index 3d5b0fa5836..f930d3caff9 100644
> --- a/src/mesa/state_tracker/st_extensions.c
> +++ b/src/mesa/state_tracker/st_extensions.c
> @@ -76,8 +76,7 @@ static int _clamp(int a, int min, int max)
> * Note that we have to limit/clamp against Mesa's internal limits too.
> */
> void st_init_limits(struct pipe_screen *screen,
> -struct gl_constants *c, struct gl_extensions
> *extensions,
> -gl_api api)
> +struct gl_constants *c, struct gl_extensions
> *extensions)
> {
> int supported_irs;
> unsigned sh;
> @@ -447,14 +446,8 @@ void st_init_limits(struct pipe_screen *screen,
> c->GLSLFrontFacingIsSysVal =
>screen->get_param(screen, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL);
>
> - /* GL_ARB_get_program_binary
> -*
> -* The QT framework has a bug in their shader program cache, which is
> built
> -* on GL_ARB_get_program_binary. In an effort to allow them to fix the
> bug
> -* we don't enable more than 1 binary format for compatibility
> profiles.
> -*/
> - if (api != API_OPENGL_COMPAT &&
> - screen->get_disk_shader_cache &&
> screen->get_disk_shader_cache(screen))
> + /* GL_ARB_get_program_binary */
> + if (screen->get_disk_shader_cache &&
> screen->get_disk_shader_cache(screen))
>c->NumProgramBinaryFormats = 1;
>
> c->MaxAtomicBufferBindings =
> diff --git a/src/mesa/state_tracker/st_extensions.h
> b/src/mesa/state_tracker/st_extensions.h
> index fdfac7ece70..7bf1aa8c8cb 100644
> --- a/src/mesa/state_tracker/st_extensions.h
> +++ b/src/mesa/state_tracker/st_extensions.h
> @@ -35,8 +35,7 @@ struct pipe_screen;
>
> extern void st_init_limits(struct pipe_screen *screen,
> struct gl_constants *c,
> - struct gl_extensions *extensions,
> - gl_api api);
> + struct gl_extensions *extensions);
>
> extern void st_init_extensions(struct pipe_screen *screen,
> struct gl_constants *consts,
> diff --git a/src/mesa/state_tracker/st_manager.c
> b/src/mesa/state_tracker/st_manager.c
> index 35d41f0a2c1..ff0bec8f569 100644
> --- a/src/mesa/state_tracker/st_manager.c
> +++ b/src/mesa/state_tracker/st_manager.c
> @@ -1269,7 +1269,7 @@ get_version(struct pipe_screen *screen,
> _mesa_init_constants(, api);
> _mesa_init_extensions();
>
> - st_init_limits(screen, , , api);
> + st_init_limits(screen, , );
> st_init_extensions(screen, , , options, api);
>
> return _mesa_get_version(, , api);
> --
> 2.20.1
>
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Re: [Mesa-dev] [PATCH] radeonsi: add drirc workaround for American Truck Simulator
Reviewed-by: Marek Olšák Marek On Sun, May 26, 2019 at 9:57 PM Timothy Arceri wrote: > Cc: "19.0" "19.1" > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110711 > --- > src/util/00-mesa-defaults.conf | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/src/util/00-mesa-defaults.conf > b/src/util/00-mesa-defaults.conf > index 3c459f3dec4..e36190f61c8 100644 > --- a/src/util/00-mesa-defaults.conf > +++ b/src/util/00-mesa-defaults.conf > @@ -471,6 +471,9 @@ TODO: document the other workarounds. > > value="true" /> > > + executable="amtrucks"> > + > + > executable="csgo_linux64"> > > > -- > 2.20.1 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110673] amdgpu hevc encoding problems: segment fault and contents of garbage
https://bugs.freedesktop.org/show_bug.cgi?id=110673 --- Comment #3 from Boyuan Zhang --- Hi Zhoulei, Please use the latest patch to test again: https://lists.freedesktop.org/archives/mesa-dev/2019-May/219613.html Regards, Boyuan -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] etnaviv: drop a bunch of duplicated gallium PIPE_CAP default code
Now that we have the util function for the default values, we can get rid of the boilerplate. Signed-off-by: Christian Gmeiner --- src/gallium/drivers/etnaviv/etnaviv_screen.c | 157 --- 1 file changed, 157 deletions(-) diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c index f245127d2d9..0398a0fb39b 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c @@ -158,9 +158,6 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 256; case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: return 4; /* XXX could easily be supported */ - case PIPE_CAP_GLSL_FEATURE_LEVEL: - case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: - return 120; case PIPE_CAP_NPOT_TEXTURES: return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1, @@ -170,148 +167,17 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_PRIMITIVE_RESTART: return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); - case PIPE_CAP_ENDIANNESS: - return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature -ENDIANNESS_CONFIG) */ - /* Unsupported features. */ - case PIPE_CAP_SEAMLESS_CUBE_MAP: - case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */ - case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */ - case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */ - case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */ - case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */ - case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */ - case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */ - case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */ - case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */ - case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */ - case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: /* only mirrored repeat */ - case PIPE_CAP_INDEP_BLEND_ENABLE: - case PIPE_CAP_INDEP_BLEND_FUNC: - case PIPE_CAP_DEPTH_CLIP_DISABLE: - case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE: - case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: - case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: - case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: - case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */ - case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: - case PIPE_CAP_VERTEX_COLOR_CLAMPED: - case PIPE_CAP_USER_VERTEX_BUFFERS: - case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: - case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: - case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */ - case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: - case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: - case PIPE_CAP_TEXTURE_GATHER_SM5: - case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: - case PIPE_CAP_FAKE_SW_MSAA: - case PIPE_CAP_TEXTURE_QUERY_LOD: - case PIPE_CAP_SAMPLE_SHADING: - case PIPE_CAP_TEXTURE_GATHER_OFFSETS: - case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: - case PIPE_CAP_DRAW_INDIRECT: - case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: - case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: - case PIPE_CAP_SAMPLER_VIEW_TARGET: - case PIPE_CAP_CLIP_HALFZ: - case PIPE_CAP_VERTEXID_NOBASE: - case PIPE_CAP_POLYGON_OFFSET_CLAMP: - case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: - case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: - case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: - case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: - case PIPE_CAP_TEXTURE_FLOAT_LINEAR: - case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: - case PIPE_CAP_DEPTH_BOUNDS_TEST: - case PIPE_CAP_TGSI_TXQS: - case PIPE_CAP_FORCE_PERSAMPLE_INTERP: - case PIPE_CAP_SHAREABLE_SHADERS: - case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: - case PIPE_CAP_CLEAR_TEXTURE: - case PIPE_CAP_DRAW_PARAMETERS: - case PIPE_CAP_TGSI_PACK_HALF_FLOAT: - case PIPE_CAP_MULTI_DRAW_INDIRECT: - case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: - case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: - case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: - case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: - case PIPE_CAP_INVALIDATE_BUFFER: - case PIPE_CAP_GENERATE_MIPMAP: - case PIPE_CAP_STRING_MARKER: - case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: - case PIPE_CAP_QUERY_BUFFER_OBJECT: - case PIPE_CAP_QUERY_MEMORY_INFO: - case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: - case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: - case PIPE_CAP_CULL_DISTANCE: - case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: - case PIPE_CAP_TGSI_VOTE: - case PIPE_CAP_MAX_WINDOW_RECTANGLES: - case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: - case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: - case PIPE_CAP_TGSI_ARRAY_COMPONENTS: - case
[Mesa-dev] [PATCH] radeon/uvd: fix poc for hevc encode
From: Boyuan Zhang
MaxPicOrderCntLsb should be at least 16 according to the spec,
therefore add minimum value check.
Also use poc value passed from st instead of calculation
in slice header encoding.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org
V2: fix typo
Signed-off-by: Boyuan Zhang
---
src/gallium/drivers/radeon/radeon_uvd_enc.c | 3 ++-
src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 3 +--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
index 521d08f304..9256e43a08 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -73,7 +73,8 @@ radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
- enc->enc_pic.max_poc = pic->seq.intra_period;
+ enc->enc_pic.max_poc =
+ (pic->seq.intra_period >= 16) ? pic->seq.intra_period : 16;
enc->enc_pic.log2_max_poc = 0;
for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
i = (i >> 1);
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
index ddb219792a..8f0e0099e7 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -768,8 +768,7 @@ radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder
*enc)
if ((enc->enc_pic.nal_unit_type != 19)
&& (enc->enc_pic.nal_unit_type != 20)) {
radeon_uvd_enc_code_fixed_bits(enc,
- enc->enc_pic.frame_num %
- enc->enc_pic.max_poc,
+ enc->enc_pic.pic_order_cnt,
enc->enc_pic.log2_max_poc);
if (enc->enc_pic.picture_type == PIPE_H265_ENC_PICTURE_TYPE_P)
radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
--
2.17.1
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[Mesa-dev] [PATCH] radeon/vcn: fix poc for hevc encode
From: Boyuan Zhang
MaxPicOrderCntLsb should be at least 16 according to the spec,
therefore add minimum value check.
Also use poc value passed from st instead of calculation
in slice header encoding.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org
V2: fix typo
Signed-off-by: Boyuan Zhang
---
src/gallium/drivers/radeon/radeon_vcn_enc.c | 3 ++-
src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c
b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index 8f9af73c66..e949b7b3a9 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -72,7 +72,8 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder
*enc, struct pipe_pic
enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
- enc->enc_pic.max_poc = pic->seq.intra_period;
+ enc->enc_pic.max_poc =
+ (pic->seq.intra_period >= 16) ? pic->seq.intra_period : 16;
enc->enc_pic.log2_max_poc = 0;
for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
i = (i >> 1);
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 7f5b190934..3302ed7524 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -988,7 +988,7 @@ static void radeon_enc_slice_header_hevc(struct
radeon_encoder *enc)
}
if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type
!= 20)) {
- radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num %
enc->enc_pic.max_poc, enc->enc_pic.log2_max_poc);
+ radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt,
enc->enc_pic.log2_max_poc);
if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P)
radeon_enc_code_fixed_bits(enc, 0x1, 1);
else {
--
2.17.1
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[Mesa-dev] [PATCH] radeon/vcn: fix poc for hevc encode
From: Boyuan Zhang
MaxPicOrderCntLsb should be at 16 according to the spec,
therefore add minimum value check.
Also use poc value passed from st instead of calculation
in slice header encoding.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Boyuan Zhang
---
src/gallium/drivers/radeon/radeon_vcn_enc.c | 3 ++-
src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c
b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index 8f9af73c66..e949b7b3a9 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -72,7 +72,8 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder
*enc, struct pipe_pic
enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
- enc->enc_pic.max_poc = pic->seq.intra_period;
+ enc->enc_pic.max_poc =
+ (pic->seq.intra_period >= 16) ? pic->seq.intra_period : 16;
enc->enc_pic.log2_max_poc = 0;
for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
i = (i >> 1);
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 7f5b190934..3302ed7524 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -988,7 +988,7 @@ static void radeon_enc_slice_header_hevc(struct
radeon_encoder *enc)
}
if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type
!= 20)) {
- radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num %
enc->enc_pic.max_poc, enc->enc_pic.log2_max_poc);
+ radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt,
enc->enc_pic.log2_max_poc);
if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P)
radeon_enc_code_fixed_bits(enc, 0x1, 1);
else {
--
2.17.1
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[Mesa-dev] [PATCH] radeon/uvd: fix poc for hevc encode
From: Boyuan Zhang
MaxPicOrderCntLsb should be at 16 according to the spec,
therefore add minimum value check.
Also use poc value passed from st instead of calculation
in slice header encoding.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Boyuan Zhang
---
src/gallium/drivers/radeon/radeon_uvd_enc.c | 3 ++-
src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 3 +--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
index 521d08f304..9256e43a08 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -73,7 +73,8 @@ radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
- enc->enc_pic.max_poc = pic->seq.intra_period;
+ enc->enc_pic.max_poc =
+ (pic->seq.intra_period >= 16) ? pic->seq.intra_period : 16;
enc->enc_pic.log2_max_poc = 0;
for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
i = (i >> 1);
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
index ddb219792a..8f0e0099e7 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -768,8 +768,7 @@ radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder
*enc)
if ((enc->enc_pic.nal_unit_type != 19)
&& (enc->enc_pic.nal_unit_type != 20)) {
radeon_uvd_enc_code_fixed_bits(enc,
- enc->enc_pic.frame_num %
- enc->enc_pic.max_poc,
+ enc->enc_pic.pic_order_cnt,
enc->enc_pic.log2_max_poc);
if (enc->enc_pic.picture_type == PIPE_H265_ENC_PICTURE_TYPE_P)
radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
--
2.17.1
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Re: [Mesa-dev] [PATCH] mesa: Prevent classic swrast crash on a surfaceless context v2.
On 2019/05/27, mathias.froehl...@gmx.net wrote:
> From: Mathias Fröhlich
>
> Hi Emil,
>
> thanks for that hint to look at _mesa_get_incomplete_framebuffer.
> That one seems definitely more appropriate!
>
> Though, I miss a bit the idea how I can create either a sensible
> helper function for that task or how I can create something above
> in the call stack to the MakeCurrent call that already catches
> this case. Since that incomplete framebuffer is a mesa side thing I
> cannot easily pull that above the __DriverAPIRec::MakeCurrent call.
> But really putting those hand full lines of code into a helper does
> as well not gain much. So I implemented that for the swrast case
> directly.
>
>
For the patch:
Reviewed-by: Emil Velikov
Here is a quick and dirty example. Feel free to follow-up if you like
the idea.
Note: it also updates/considers the fact that only one of the two
drawables can be NULL. Technically a bugfix - not sure if many tests
flex that code-path.
diff --git a/src/mesa/drivers/dri/i915/intel_context.c
b/src/mesa/drivers/dri/i915/intel_context.c
index aa3175816cf..035abe13ff8 100644
--- a/src/mesa/drivers/dri/i915/intel_context.c
+++ b/src/mesa/drivers/dri/i915/intel_context.c
@@ -617,45 +617,62 @@ intelUnbindContext(__DRIcontext * driContextPriv)
return true;
}
+/* XXX: make me public - aka move to src/mesa/ or sr/mesa/main even */
+/* when TRUE is returned read/writeFb are set. on FALSE we should call
make_current(null...) */
+bool
+make_current_setup(__DRIcontext * driContextPriv,
+ __DRIdrawable * driDrawPriv,
+ __DRIdrawable * driReadPriv,
+struct **gl_framebuffer readFb,
+struct **gl_framebuffer writeFb)
+{
+ if (!driContextPriv)
+ return false;
+
+ struct *gl_framebuffer incomplete = _mesa_get_incomplete_framebuffer();
+
+ if (driReadPriv == NULL) {
+ *readFb = incomplete;
+ } else {
+ *readFb = driReadPriv->driverPrivate;
+ driContextPriv->dri2.read_stamp = driReadPriv->dri2.stamp - 1;
+}
+
+ if (driDrawPriv == NULL) {
+ *writeFb = incomplete;
+ } else {
+ *writeFb = driDrawPriv->driverPrivate;
+ driContextPriv->dri2.draw_stamp = driDrawPriv->dri2.stamp - 1;
+ }
+
+ return true;
+}
+
GLboolean
intelMakeCurrent(__DRIcontext * driContextPriv,
__DRIdrawable * driDrawPriv,
__DRIdrawable * driReadPriv)
{
struct intel_context *intel;
+ struct gl_framebuffer *fb, *readFb;
- if (driContextPriv)
- intel = (struct intel_context *) driContextPriv->driverPrivate;
- else
- intel = NULL;
-
- if (driContextPriv) {
- struct gl_context *ctx = >ctx;
- struct gl_framebuffer *fb, *readFb;
-
- if (driDrawPriv == NULL && driReadPriv == NULL) {
-fb = _mesa_get_incomplete_framebuffer();
-readFb = _mesa_get_incomplete_framebuffer();
- } else {
-fb = driDrawPriv->driverPrivate;
-readFb = driReadPriv->driverPrivate;
-driContextPriv->dri2.draw_stamp = driDrawPriv->dri2.stamp - 1;
-driContextPriv->dri2.read_stamp = driReadPriv->dri2.stamp - 1;
- }
-
- intel_prepare_render(intel);
- _mesa_make_current(ctx, fb, readFb);
-
- /* We do this in intel_prepare_render() too, but intel->ctx.DrawBuffer
- * is NULL at that point. We can't call _mesa_makecurrent()
- * first, since we need the buffer size for the initial
- * viewport. So just call intel_draw_buffer() again here. */
- intel_draw_buffer(ctx);
- }
- else {
+ if (!make_current_setup(driContextPriv, driDrawPriv, driReadPriv, ,
)) {
_mesa_make_current(NULL, NULL, NULL);
+ return true;
}
+ intel = (struct intel_context *) driContextPriv->driverPrivate;
+ struct gl_context *ctx = >ctx;
+
+ intel_prepare_render(intel);
+ _mesa_make_current(ctx, fb, readFb);
+
+ /* We do this in intel_prepare_render() too, but intel->ctx.DrawBuffer
+* is NULL at that point. We can't call _mesa_makecurrent()
+* first, since we need the buffer size for the initial
+* viewport. So just call intel_draw_buffer() again here. */
+ intel_draw_buffer(ctx);
+
return true;
}
> So, to mention, I sent that change including our egl device code
> with some unrelated egl device fixes through intels CI and did not
> get regressions.
>
Thanks, having a look. Too many fires going at the same time :-\
-Emil
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Re: [Mesa-dev] [PATCH 1/7] radv: record if a render pass has depth/stencil resolve attachments
On Mon, May 27, 2019 at 5:38 PM Samuel Pitoiset
wrote:
>
> Only supported with vkCreateRenderPass2().
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_pass.c| 30 +-
> src/amd/vulkan/radv_private.h | 3 +++
> 2 files changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan/radv_pass.c
> index 4d1e38a780e..b21bf37e401 100644
> --- a/src/amd/vulkan/radv_pass.c
> +++ b/src/amd/vulkan/radv_pass.c
> @@ -75,6 +75,10 @@ radv_render_pass_compile(struct radv_render_pass *pass)
> subpass->depth_stencil_attachment->attachment ==
> VK_ATTACHMENT_UNUSED)
> subpass->depth_stencil_attachment = NULL;
>
> + if (subpass->ds_resolve_attachment &&
> + subpass->ds_resolve_attachment->attachment ==
> VK_ATTACHMENT_UNUSED)
> + subpass->ds_resolve_attachment = NULL;
> +
> for (uint32_t j = 0; j < subpass->attachment_count; j++) {
> struct radv_subpass_attachment *subpass_att =
> >attachments[j];
> @@ -126,6 +130,9 @@ radv_render_pass_compile(struct radv_render_pass *pass)
> subpass->has_resolve = true;
> }
> }
> +
> + if (subpass->ds_resolve_attachment)
> + subpass->has_resolve = true;
I think this makes the code assume that there are also color resolves
to be done, which might not be the case?
> }
> }
>
> @@ -291,10 +298,15 @@ VkResult radv_CreateRenderPass(
> static unsigned
> radv_num_subpass_attachments2(const VkSubpassDescription2KHR *desc)
> {
> + const VkSubpassDescriptionDepthStencilResolveKHR *ds_resolve =
> + vk_find_struct_const(desc->pNext,
> +
> SUBPASS_DESCRIPTION_DEPTH_STENCIL_RESOLVE_KHR);
> +
> return desc->inputAttachmentCount +
>desc->colorAttachmentCount +
>(desc->pResolveAttachments ? desc->colorAttachmentCount : 0) +
> - (desc->pDepthStencilAttachment != NULL);
> + (desc->pDepthStencilAttachment != NULL) +
> + (ds_resolve && ds_resolve->pDepthStencilResolveAttachment);
> }
>
> VkResult radv_CreateRenderPass2KHR(
> @@ -411,6 +423,22 @@ VkResult radv_CreateRenderPass2KHR(
> .layout =
> desc->pDepthStencilAttachment->layout,
> };
> }
> +
> + const VkSubpassDescriptionDepthStencilResolveKHR *ds_resolve =
> + vk_find_struct_const(desc->pNext,
> +
> SUBPASS_DESCRIPTION_DEPTH_STENCIL_RESOLVE_KHR);
> +
> + if (ds_resolve && ds_resolve->pDepthStencilResolveAttachment)
> {
> + subpass->ds_resolve_attachment = p++;
> +
> + *subpass->ds_resolve_attachment = (struct
> radv_subpass_attachment) {
> + .attachment =
> ds_resolve->pDepthStencilResolveAttachment->attachment,
> + .layout =
> ds_resolve->pDepthStencilResolveAttachment->layout,
> + };
> +
> + subpass->depth_resolve_mode =
> ds_resolve->depthResolveMode;
> + subpass->stencil_resolve_mode =
> ds_resolve->stencilResolveMode;
> + }
> }
>
> for (unsigned i = 0; i < pCreateInfo->dependencyCount; ++i) {
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index 7834a505562..e826740bc9f 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -1882,6 +1882,9 @@ struct radv_subpass {
> struct radv_subpass_attachment * color_attachments;
> struct radv_subpass_attachment * resolve_attachments;
> struct radv_subpass_attachment * depth_stencil_attachment;
> + struct radv_subpass_attachment * ds_resolve_attachment;
> + VkResolveModeFlagBitsKHR depth_resolve_mode;
> + VkResolveModeFlagBitsKHR stencil_resolve_mode;
>
> /** Subpass has at least one resolve attachment */
> bool has_resolve;
> --
> 2.21.0
>
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[Mesa-dev] [PATCH 2/2] radv add radv_get_resolve_pipeline() in the compute path
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_resolve_cs.c | 56 +--
1 file changed, 36 insertions(+), 20 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c
b/src/amd/vulkan/radv_meta_resolve_cs.c
index 76612672b1c..67df4800023 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -313,6 +313,39 @@ radv_device_finish_meta_resolve_compute_state(struct
radv_device *device)
>alloc);
}
+static VkPipeline *
+radv_get_resolve_pipeline(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *src_image)
+{
+ struct radv_device *device = cmd_buffer->device;
+ struct radv_meta_state *state = >meta_state;
+ uint32_t samples = src_image->info.samples;
+ uint32_t samples_log2 = ffs(samples) - 1;
+ VkPipeline *pipeline;
+
+ if (vk_format_is_int(src_image->vk_format))
+ pipeline = >resolve_compute.rc[samples_log2].i_pipeline;
+ else if (vk_format_is_srgb(src_image->vk_format))
+ pipeline =
>resolve_compute.rc[samples_log2].srgb_pipeline;
+ else
+ pipeline = >resolve_compute.rc[samples_log2].pipeline;
+
+ if (!*pipeline) {
+ VkResult ret;
+
+ ret = create_resolve_pipeline(device, samples,
+
vk_format_is_int(src_image->vk_format),
+
vk_format_is_srgb(src_image->vk_format),
+ pipeline);
+ if (ret != VK_SUCCESS) {
+ cmd_buffer->record_result = ret;
+ return NULL;
+ }
+ }
+
+ return pipeline;
+}
+
static void
emit_resolve(struct radv_cmd_buffer *cmd_buffer,
struct radv_image_view *src_iview,
@@ -322,8 +355,8 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
const VkExtent2D *resolve_extent)
{
struct radv_device *device = cmd_buffer->device;
- const uint32_t samples = src_iview->image->info.samples;
- const uint32_t samples_log2 = ffs(samples) - 1;
+ VkPipeline *pipeline;
+
radv_meta_push_descriptor_set(cmd_buffer,
VK_PIPELINE_BIND_POINT_COMPUTE,
device->meta_state.resolve_compute.p_layout,
@@ -359,24 +392,7 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
}
});
- VkPipeline *pipeline;
- if (vk_format_is_int(src_iview->image->vk_format))
- pipeline =
>meta_state.resolve_compute.rc[samples_log2].i_pipeline;
- else if (vk_format_is_srgb(src_iview->image->vk_format))
- pipeline =
>meta_state.resolve_compute.rc[samples_log2].srgb_pipeline;
- else
- pipeline =
>meta_state.resolve_compute.rc[samples_log2].pipeline;
-
- if (!*pipeline) {
- VkResult ret = create_resolve_pipeline(device, samples,
-
vk_format_is_int(src_iview->image->vk_format),
-
vk_format_is_srgb(src_iview->image->vk_format),
- pipeline);
- if (ret != VK_SUCCESS) {
- cmd_buffer->record_result = ret;
- return;
- }
- }
+ pipeline = radv_get_resolve_pipeline(cmd_buffer, src_iview->image);
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
VK_PIPELINE_BIND_POINT_COMPUTE, *pipeline);
--
2.21.0
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[Mesa-dev] [PATCH 1/2] radv: cleanup the compute resolve path for subpass
This makes use of radv_meta_resolve_compute_image() by filling
a VkImageResolve region instead of duplicating code.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_resolve_cs.c | 85 +--
1 file changed, 29 insertions(+), 56 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c
b/src/amd/vulkan/radv_meta_resolve_cs.c
index 1b786526cf2..76612672b1c 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -489,7 +489,6 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer)
{
struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
- struct radv_meta_saved_state saved_state;
struct radv_subpass_barrier barrier;
/* Resolves happen before the end-of-subpass barriers get executed, so
@@ -500,67 +499,41 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer)
barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT;
radv_subpass_barrier(cmd_buffer, );
- radv_decompress_resolve_subpass_src(cmd_buffer);
-
- radv_meta_save(_state, cmd_buffer,
- RADV_META_SAVE_COMPUTE_PIPELINE |
- RADV_META_SAVE_CONSTANTS |
- RADV_META_SAVE_DESCRIPTORS);
-
for (uint32_t i = 0; i < subpass->color_count; ++i) {
struct radv_subpass_attachment src_att =
subpass->color_attachments[i];
- struct radv_subpass_attachment dest_att =
subpass->resolve_attachments[i];
- struct radv_image_view *src_iview =
cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
- struct radv_image_view *dst_iview =
cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
- if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
- continue;
-
- struct radv_image *src_image = src_iview->image;
- struct radv_image *dst_image = dst_iview->image;
- for (uint32_t layer = 0; layer < src_image->info.array_size;
layer++) {
+ struct radv_subpass_attachment dst_att =
subpass->resolve_attachments[i];
+ struct radv_image_view *src_iview =
fb->attachments[src_att.attachment].attachment;
+ struct radv_image_view *dst_iview =
fb->attachments[dst_att.attachment].attachment;
- struct radv_image_view tsrc_iview;
- radv_image_view_init(_iview, cmd_buffer->device,
-&(VkImageViewCreateInfo) {
-.sType =
VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
-.image =
radv_image_to_handle(src_image),
-.viewType =
radv_meta_get_view_type(src_image),
-.format =
src_image->vk_format,
-.subresourceRange
= {
-.aspectMask =
VK_IMAGE_ASPECT_COLOR_BIT,
-.baseMipLevel =
src_iview->base_mip,
-.levelCount = 1,
-.baseArrayLayer =
layer,
-.layerCount = 1,
-},
-});
+ if (dst_att.attachment == VK_ATTACHMENT_UNUSED)
+ continue;
- struct radv_image_view tdst_iview;
- radv_image_view_init(_iview, cmd_buffer->device,
-&(VkImageViewCreateInfo) {
-.sType =
VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
-.image =
radv_image_to_handle(dst_image),
-.viewType =
radv_meta_get_view_type(dst_image),
-.format =
vk_to_non_srgb_format(dst_image->vk_format),
-.subresourceRange
= {
-.aspectMask =
VK_IMAGE_ASPECT_COLOR_BIT,
-.baseMipLevel =
dst_iview->base_mip,
-.levelCount = 1,
-.baseArrayLayer =
layer,
-
[Mesa-dev] [PATCH 3/7] radv: implement all depth/stencil resolve modes using compute
This path supports layers but it requires to decompress HTILE
before resolving. The driver also needs to fixup HTILE after
the resolve. This path is probably slower than the graphics one.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_resolve_cs.c | 491 ++
src/amd/vulkan/radv_private.h | 16 +
2 files changed, 507 insertions(+)
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c
b/src/amd/vulkan/radv_meta_resolve_cs.c
index 1b786526cf2..c0091bd9292 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -139,6 +139,165 @@ build_resolve_compute_shader(struct radv_device *dev,
bool is_integer, bool is_s
return b.shader;
}
+enum {
+ DEPTH_RESOLVE,
+ STENCIL_RESOLVE,
+};
+
+static const char *
+get_resolve_mode_str(VkResolveModeFlagBitsKHR resolve_mode)
+{
+ switch (resolve_mode) {
+ case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
+ return "zero";
+ case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
+ return "average";
+ case VK_RESOLVE_MODE_MIN_BIT_KHR:
+ return "min";
+ case VK_RESOLVE_MODE_MAX_BIT_KHR:
+ return "max";
+ default:
+ unreachable("invalid resolve mode");
+ }
+}
+
+static nir_shader *
+build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int
samples,
+ int index,
+ VkResolveModeFlagBitsKHR
resolve_mode)
+{
+ nir_builder b;
+ char name[64];
+ const struct glsl_type *sampler_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
+false,
+false,
+
GLSL_TYPE_FLOAT);
+ const struct glsl_type *img_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
+false,
+false,
+GLSL_TYPE_FLOAT);
+ snprintf(name, 64, "meta_resolve_cs_%s-%s-%d",
+index == DEPTH_RESOLVE ? "depth" : "stencil",
+get_resolve_mode_str(resolve_mode), samples);
+
+ nir_builder_init_simple_shader(, NULL, MESA_SHADER_COMPUTE, NULL);
+ b.shader->info.name = ralloc_strdup(b.shader, name);
+ b.shader->info.cs.local_size[0] = 16;
+ b.shader->info.cs.local_size[1] = 16;
+ b.shader->info.cs.local_size[2] = 1;
+
+ nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
+ sampler_type, "s_tex");
+ input_img->data.descriptor_set = 0;
+ input_img->data.binding = 0;
+
+ nir_variable *output_img = nir_variable_create(b.shader,
nir_var_uniform,
+ img_type, "out_img");
+ output_img->data.descriptor_set = 0;
+ output_img->data.binding = 1;
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id();
+ nir_ssa_def *wg_id = nir_load_work_group_id();
+ nir_ssa_def *block_size = nir_imm_ivec4(,
+ b.shader->info.cs.local_size[0],
+ b.shader->info.cs.local_size[1],
+
b.shader->info.cs.local_size[2], 0);
+
+ nir_ssa_def *global_id = nir_iadd(, nir_imul(, wg_id, block_size),
invoc_id);
+
+ nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader,
nir_intrinsic_load_push_constant);
+ nir_intrinsic_set_base(src_offset, 0);
+ nir_intrinsic_set_range(src_offset, 16);
+ src_offset->src[0] = nir_src_for_ssa(nir_imm_int(, 0));
+ src_offset->num_components = 2;
+ nir_ssa_dest_init(_offset->instr, _offset->dest, 2, 32,
"src_offset");
+ nir_builder_instr_insert(, _offset->instr);
+
+ nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader,
nir_intrinsic_load_push_constant);
+ nir_intrinsic_set_base(dst_offset, 0);
+ nir_intrinsic_set_range(dst_offset, 16);
+ dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(, 8));
+ dst_offset->num_components = 2;
+ nir_ssa_dest_init(_offset->instr, _offset->dest, 2, 32,
"dst_offset");
+ nir_builder_instr_insert(, _offset->instr);
+
+ nir_ssa_def *img_coord = nir_channels(, nir_iadd(, global_id,
_offset->dest.ssa), 0x3);
+
+ nir_ssa_def *input_img_deref = _build_deref_var(,
input_img)->dest.ssa;
+
+ nir_alu_type type = index == DEPTH_RESOLVE ? nir_type_float :
nir_type_uint;
+
+ nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
+ tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
+ tex->op = nir_texop_txf_ms;
+
[Mesa-dev] [PATCH 6/7] radv: clear the depth/stencil resolve attachment if necessary
The driver might need to clear one aspect of the depth/stencil
resolve attachment before performing the resolve itself.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_clear.c | 73
1 file changed, 55 insertions(+), 18 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 313e80d5cb7..386879e9cd5 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -714,13 +714,14 @@ static void
emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
const VkClearAttachment *clear_att,
const VkClearRect *clear_rect,
+ struct radv_subpass_attachment *ds_att,
uint32_t view_mask)
{
struct radv_device *device = cmd_buffer->device;
struct radv_meta_state *meta_state = >meta_state;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
- const uint32_t pass_att = subpass->depth_stencil_attachment->attachment;
+ const uint32_t pass_att = ds_att->attachment;
VkClearDepthStencilValue clear_value =
clear_att->clearValue.depthStencil;
VkImageAspectFlags aspects = clear_att->aspectMask;
const struct radv_image_view *iview = fb ?
fb->attachments[pass_att].attachment : NULL;
@@ -760,18 +761,25 @@ emit_depthstencil_clear(struct radv_cmd_buffer
*cmd_buffer,
iview,
samples_log2,
aspects,
-
subpass->depth_stencil_attachment->layout,
+ds_att->layout,
clear_rect,
clear_value);
if (!pipeline)
return;
+ struct radv_subpass clear_subpass = {
+ .color_count = 0,
+ .color_attachments = NULL,
+ .depth_stencil_attachment = ds_att,
+ };
+
+ radv_cmd_buffer_set_subpass(cmd_buffer, _subpass);
+
radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
pipeline);
if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
- subpass->depth_stencil_attachment->layout,
- clear_rect, clear_value))
+ ds_att->layout, clear_rect, clear_value))
radv_update_ds_clear_metadata(cmd_buffer, iview->image,
clear_value, aspects);
@@ -798,6 +806,8 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
radv_CmdSetStencilReference(cmd_buffer_h,
VK_STENCIL_FACE_FRONT_BIT,
prev_reference);
}
+
+ radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
}
static uint32_t
@@ -1561,7 +1571,8 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer,
const VkClearRect *clear_rect,
enum radv_cmd_flush_bits *pre_flush,
enum radv_cmd_flush_bits *post_flush,
- uint32_t view_mask)
+ uint32_t view_mask,
+ bool ds_resolve_clear)
{
const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
@@ -1587,12 +1598,16 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer,
emit_color_clear(cmd_buffer, clear_att, clear_rect,
view_mask);
}
} else {
- const uint32_t pass_att =
subpass->depth_stencil_attachment->attachment;
- if (pass_att == VK_ATTACHMENT_UNUSED)
+ struct radv_subpass_attachment *ds_att =
subpass->depth_stencil_attachment;
+
+ if (ds_resolve_clear)
+ ds_att = subpass->ds_resolve_attachment;
+
+ if (ds_att->attachment == VK_ATTACHMENT_UNUSED)
return;
- VkImageLayout image_layout =
subpass->depth_stencil_attachment->layout;
- const struct radv_image_view *iview = fb ?
fb->attachments[pass_att].attachment : NULL;
+ VkImageLayout image_layout = ds_att->layout;
+ const struct radv_image_view *iview = fb ?
fb->attachments[ds_att->attachment].attachment : NULL;
VkClearDepthStencilValue clear_value =
clear_att->clearValue.depthStencil;
assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
@@ -1605,7 +1620,7 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer,
pre_flush, post_flush);
} else {
[Mesa-dev] [PATCH 1/7] radv: record if a render pass has depth/stencil resolve attachments
Only supported with vkCreateRenderPass2().
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pass.c| 30 +-
src/amd/vulkan/radv_private.h | 3 +++
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan/radv_pass.c
index 4d1e38a780e..b21bf37e401 100644
--- a/src/amd/vulkan/radv_pass.c
+++ b/src/amd/vulkan/radv_pass.c
@@ -75,6 +75,10 @@ radv_render_pass_compile(struct radv_render_pass *pass)
subpass->depth_stencil_attachment->attachment ==
VK_ATTACHMENT_UNUSED)
subpass->depth_stencil_attachment = NULL;
+ if (subpass->ds_resolve_attachment &&
+ subpass->ds_resolve_attachment->attachment ==
VK_ATTACHMENT_UNUSED)
+ subpass->ds_resolve_attachment = NULL;
+
for (uint32_t j = 0; j < subpass->attachment_count; j++) {
struct radv_subpass_attachment *subpass_att =
>attachments[j];
@@ -126,6 +130,9 @@ radv_render_pass_compile(struct radv_render_pass *pass)
subpass->has_resolve = true;
}
}
+
+ if (subpass->ds_resolve_attachment)
+ subpass->has_resolve = true;
}
}
@@ -291,10 +298,15 @@ VkResult radv_CreateRenderPass(
static unsigned
radv_num_subpass_attachments2(const VkSubpassDescription2KHR *desc)
{
+ const VkSubpassDescriptionDepthStencilResolveKHR *ds_resolve =
+ vk_find_struct_const(desc->pNext,
+
SUBPASS_DESCRIPTION_DEPTH_STENCIL_RESOLVE_KHR);
+
return desc->inputAttachmentCount +
desc->colorAttachmentCount +
(desc->pResolveAttachments ? desc->colorAttachmentCount : 0) +
- (desc->pDepthStencilAttachment != NULL);
+ (desc->pDepthStencilAttachment != NULL) +
+ (ds_resolve && ds_resolve->pDepthStencilResolveAttachment);
}
VkResult radv_CreateRenderPass2KHR(
@@ -411,6 +423,22 @@ VkResult radv_CreateRenderPass2KHR(
.layout = desc->pDepthStencilAttachment->layout,
};
}
+
+ const VkSubpassDescriptionDepthStencilResolveKHR *ds_resolve =
+ vk_find_struct_const(desc->pNext,
+
SUBPASS_DESCRIPTION_DEPTH_STENCIL_RESOLVE_KHR);
+
+ if (ds_resolve && ds_resolve->pDepthStencilResolveAttachment) {
+ subpass->ds_resolve_attachment = p++;
+
+ *subpass->ds_resolve_attachment = (struct
radv_subpass_attachment) {
+ .attachment =
ds_resolve->pDepthStencilResolveAttachment->attachment,
+ .layout =
ds_resolve->pDepthStencilResolveAttachment->layout,
+ };
+
+ subpass->depth_resolve_mode =
ds_resolve->depthResolveMode;
+ subpass->stencil_resolve_mode =
ds_resolve->stencilResolveMode;
+ }
}
for (unsigned i = 0; i < pCreateInfo->dependencyCount; ++i) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 7834a505562..e826740bc9f 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1882,6 +1882,9 @@ struct radv_subpass {
struct radv_subpass_attachment * color_attachments;
struct radv_subpass_attachment * resolve_attachments;
struct radv_subpass_attachment * depth_stencil_attachment;
+ struct radv_subpass_attachment * ds_resolve_attachment;
+ VkResolveModeFlagBitsKHR depth_resolve_mode;
+ VkResolveModeFlagBitsKHR stencil_resolve_mode;
/** Subpass has at least one resolve attachment */
bool has_resolve;
--
2.21.0
___
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[Mesa-dev] [PATCH 5/7] radv: decompress HTILE if the resolve src image is compressed
It's required to decompress HTILE before resolving with the
compute path.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_resolve.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/src/amd/vulkan/radv_meta_resolve.c
b/src/amd/vulkan/radv_meta_resolve.c
index 2d048207b7a..8891a98e4d7 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -769,6 +769,32 @@ radv_decompress_resolve_subpass_src(struct radv_cmd_buffer
*cmd_buffer)
radv_decompress_resolve_src(cmd_buffer, src_image,
src_att.layout, 1, );
}
+
+ if (subpass->ds_resolve_attachment) {
+ struct radv_subpass_attachment src_att =
*subpass->depth_stencil_attachment;
+ struct radv_image *src_image =
+ fb->attachments[src_att.attachment].attachment->image;
+ uint32_t queue_mask =
+ radv_image_queue_family_mask(src_image,
+
cmd_buffer->queue_family_index,
+
cmd_buffer->queue_family_index);
+
+ VkImageSubresourceRange range;
+ range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
+ range.baseMipLevel = 0;
+ range.levelCount = 1;
+ range.baseArrayLayer = 0;
+ range.layerCount = src_image->info.array_size;
+
+ if (radv_layout_is_htile_compressed(src_image, src_att.layout,
+ queue_mask)) {
+ radv_decompress_depth_image_inplace(cmd_buffer,
src_image,
+ );
+
+ cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_FLUSH_AND_INV_DB |
+
RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
+ }
+ }
}
/**
--
2.21.0
___
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[Mesa-dev] [PATCH 7/7] radv: add support for VK_KHR_depth_stencil_resolve
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 21 +
src/amd/vulkan/radv_extensions.py | 1 +
2 files changed, 22 insertions(+)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 4203074a4cd..ead6d63f1c5 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1368,6 +1368,27 @@ void radv_GetPhysicalDeviceProperties2(
props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks =
MAX_INLINE_UNIFORM_BLOCK_COUNT;
break;
}
+ case
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
+ VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*properties =
+
(VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
+
+ /* We support all of the depth resolve modes */
+ properties->supportedDepthResolveModes =
+ VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
+ VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
+ VK_RESOLVE_MODE_MIN_BIT_KHR |
+ VK_RESOLVE_MODE_MAX_BIT_KHR;
+
+ /* Average doesn't make sense for stencil so we don't
support that */
+ properties->supportedStencilResolveModes =
+ VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
+ VK_RESOLVE_MODE_MIN_BIT_KHR |
+ VK_RESOLVE_MODE_MAX_BIT_KHR;
+
+ properties->independentResolveNone = VK_TRUE;
+ properties->independentResolve = VK_TRUE;
+ break;
+ }
default:
break;
}
diff --git a/src/amd/vulkan/radv_extensions.py
b/src/amd/vulkan/radv_extensions.py
index 0b5af56a435..f61cd22982d 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -55,6 +55,7 @@ EXTENSIONS = [
Extension('VK_KHR_bind_memory2', 1, True),
Extension('VK_KHR_create_renderpass2',1, True),
Extension('VK_KHR_dedicated_allocation', 1, True),
+Extension('VK_KHR_depth_stencil_resolve', 1, True),
Extension('VK_KHR_descriptor_update_template',1, True),
Extension('VK_KHR_device_group', 1, True),
Extension('VK_KHR_device_group_creation', 1, True),
--
2.21.0
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[Mesa-dev] [PATCH 2/7] radv: implement all depth/stencil resolve modes using graphics
When using graphics, the driver doesn't need to decompress HTILE
before resolving. This path currently doesn't support layers
so we have to fallback to the compute path.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_resolve_fs.c | 597 +-
src/amd/vulkan/radv_private.h | 18 +
2 files changed, 613 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c
b/src/amd/vulkan/radv_meta_resolve_fs.c
index 9f20f6753e2..def5eeb867b 100644
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -316,6 +316,356 @@ create_resolve_pipeline(struct radv_device *device,
return result;
}
+enum {
+ DEPTH_RESOLVE,
+ STENCIL_RESOLVE
+};
+
+static const char *
+get_resolve_mode_str(VkResolveModeFlagBitsKHR resolve_mode)
+{
+ switch (resolve_mode) {
+ case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
+ return "zero";
+ case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
+ return "average";
+ case VK_RESOLVE_MODE_MIN_BIT_KHR:
+ return "min";
+ case VK_RESOLVE_MODE_MAX_BIT_KHR:
+ return "max";
+ default:
+ unreachable("invalid resolve mode");
+ }
+}
+
+static nir_shader *
+build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int
samples,
+ int index,
+ VkResolveModeFlagBitsKHR
resolve_mode)
+{
+ nir_builder b;
+ char name[64];
+ const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
+ const struct glsl_type *vec4 = glsl_vec4_type();
+ const struct glsl_type *sampler_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
+false,
+false,
+
GLSL_TYPE_FLOAT);
+
+ snprintf(name, 64, "meta_resolve_fs_%s-%s-%d",
+index == DEPTH_RESOLVE ? "depth" : "stencil",
+get_resolve_mode_str(resolve_mode), samples);
+
+ nir_builder_init_simple_shader(, NULL, MESA_SHADER_FRAGMENT, NULL);
+ b.shader->info.name = ralloc_strdup(b.shader, name);
+
+ nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
+ sampler_type, "s_tex");
+ input_img->data.descriptor_set = 0;
+ input_img->data.binding = 0;
+
+ nir_variable *fs_pos_in = nir_variable_create(b.shader,
nir_var_shader_in, vec2, "fs_pos_in");
+ fs_pos_in->data.location = VARYING_SLOT_POS;
+
+ nir_variable *fs_out = nir_variable_create(b.shader,
+ nir_var_shader_out, vec4,
+ "f_out");
+ fs_out->data.location =
+ index == DEPTH_RESOLVE ? FRAG_RESULT_DEPTH :
FRAG_RESULT_STENCIL;
+
+ nir_ssa_def *pos_in = nir_load_var(, fs_pos_in);
+
+ nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader,
nir_intrinsic_load_push_constant);
+ nir_intrinsic_set_base(src_offset, 0);
+ nir_intrinsic_set_range(src_offset, 8);
+ src_offset->src[0] = nir_src_for_ssa(nir_imm_int(, 0));
+ src_offset->num_components = 2;
+ nir_ssa_dest_init(_offset->instr, _offset->dest, 2, 32,
"src_offset");
+ nir_builder_instr_insert(, _offset->instr);
+
+ nir_ssa_def *pos_int = nir_f2i32(, pos_in);
+
+ nir_ssa_def *img_coord = nir_channels(, nir_iadd(, pos_int,
_offset->dest.ssa), 0x3);
+
+ nir_ssa_def *input_img_deref = _build_deref_var(,
input_img)->dest.ssa;
+
+ nir_alu_type type = index == DEPTH_RESOLVE ? nir_type_float :
nir_type_uint;
+
+ nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
+ tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
+ tex->op = nir_texop_txf_ms;
+ tex->src[0].src_type = nir_tex_src_coord;
+ tex->src[0].src = nir_src_for_ssa(img_coord);
+ tex->src[1].src_type = nir_tex_src_ms_index;
+ tex->src[1].src = nir_src_for_ssa(nir_imm_int(, 0));
+ tex->src[2].src_type = nir_tex_src_texture_deref;
+ tex->src[2].src = nir_src_for_ssa(input_img_deref);
+ tex->dest_type = type;
+ tex->is_array = false;
+ tex->coord_components = 2;
+
+ nir_ssa_dest_init(>instr, >dest, 4, 32, "tex");
+ nir_builder_instr_insert(, >instr);
+
+ nir_ssa_def *outval = >dest.ssa;
+
+ if (resolve_mode != VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR) {
+ for (int i = 1; i < samples; i++) {
+ nir_tex_instr *tex_add = nir_tex_instr_create(b.shader,
3);
+ tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
+ tex_add->op = nir_texop_txf_ms;
+ tex_add->src[0].src_type =
[Mesa-dev] [PATCH 4/7] radv: select the depth/stencil resolve method based on some conditions
Only fallback to the compute path for layers.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_resolve.c | 77 +-
1 file changed, 64 insertions(+), 13 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_resolve.c
b/src/amd/vulkan/radv_meta_resolve.c
index 1544513a9bc..2d048207b7a 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -341,20 +341,28 @@ static void radv_pick_resolve_method_images(struct
radv_image *src_image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
- if (src_image->vk_format == VK_FORMAT_R16G16_UNORM ||
- src_image->vk_format == VK_FORMAT_R16G16_SNORM)
- *method = RESOLVE_COMPUTE;
- else if (vk_format_is_int(src_image->vk_format))
- *method = RESOLVE_COMPUTE;
- else if (src_image->info.array_size > 1 ||
-dest_image->info.array_size > 1)
- *method = RESOLVE_COMPUTE;
+ if (vk_format_is_color(src_image->vk_format)) {
+ if (src_image->vk_format == VK_FORMAT_R16G16_UNORM ||
+ src_image->vk_format == VK_FORMAT_R16G16_SNORM)
+ *method = RESOLVE_COMPUTE;
+ else if (vk_format_is_int(src_image->vk_format))
+ *method = RESOLVE_COMPUTE;
+ else if (src_image->info.array_size > 1 ||
+dest_image->info.array_size > 1)
+ *method = RESOLVE_COMPUTE;
- if (radv_layout_dcc_compressed(dest_image, dest_image_layout,
queue_mask)) {
- *method = RESOLVE_FRAGMENT;
- } else if (dest_image->planes[0].surface.micro_tile_mode !=
- src_image->planes[0].surface.micro_tile_mode) {
- *method = RESOLVE_COMPUTE;
+ if (radv_layout_dcc_compressed(dest_image, dest_image_layout,
queue_mask)) {
+ *method = RESOLVE_FRAGMENT;
+ } else if (dest_image->planes[0].surface.micro_tile_mode !=
+ src_image->planes[0].surface.micro_tile_mode) {
+ *method = RESOLVE_COMPUTE;
+ }
+ } else {
+ if (src_image->info.array_size > 1 ||
+ dest_image->info.array_size > 1)
+ *method = RESOLVE_COMPUTE;
+ else
+ *method = RESOLVE_FRAGMENT;
}
}
@@ -621,6 +629,49 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer)
if (!subpass->has_resolve)
return;
+ if (subpass->ds_resolve_attachment) {
+ struct radv_subpass_attachment src_att =
*subpass->depth_stencil_attachment;
+ struct radv_subpass_attachment dst_att =
*subpass->ds_resolve_attachment;
+ struct radv_image_view *src_iview =
+
cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
+ struct radv_image_view *dst_iview =
+
cmd_buffer->state.framebuffer->attachments[dst_att.attachment].attachment;
+
+ radv_pick_resolve_method_images(src_iview->image,
+ dst_iview->image,
+ dst_att.layout,
+ cmd_buffer,
+ _method);
+
+ if ((src_iview->aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) &&
+ subpass->depth_resolve_mode != VK_RESOLVE_MODE_NONE_KHR) {
+ if (resolve_method == RESOLVE_FRAGMENT) {
+
radv_depth_stencil_resolve_subpass_fs(cmd_buffer,
+
VK_IMAGE_ASPECT_DEPTH_BIT,
+
subpass->depth_resolve_mode);
+ } else {
+ assert(resolve_method == RESOLVE_COMPUTE);
+
radv_depth_stencil_resolve_subpass_cs(cmd_buffer,
+
VK_IMAGE_ASPECT_DEPTH_BIT,
+
subpass->depth_resolve_mode);
+ }
+ }
+
+ if ((src_iview->aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) &&
+ subpass->stencil_resolve_mode != VK_RESOLVE_MODE_NONE_KHR) {
+ if (resolve_method == RESOLVE_FRAGMENT) {
+
radv_depth_stencil_resolve_subpass_fs(cmd_buffer,
+
VK_IMAGE_ASPECT_STENCIL_BIT,
+
[Mesa-dev] [PATCH 0/7] radv: implement VK_KHR_depth_stencil_resolve
Hi, This series implements depth/stencil resolves inside a subpass as required by VK_KHR_depth_stencil_resolve. I implemented all resolve modes with graphics and compute. Graphics doesn't support layers but it's not required to decompress HiZ before resolving. While compute supports layers but it requires a decompression pass. All CTS tests pass on Polaris10 and Vega10. Please review, Thanks! Samuel Pitoiset (7): radv: record if a render pass has depth/stencil resolve attachments radv: implement all depth/stencil resolve modes using graphics radv: implement all depth/stencil resolve modes using compute radv: select the depth/stencil resolve method based on some conditions radv: decompress HTILE if the resolve src image is compressed radv: clear the depth/stencil resolve attachment if necessary radv: add support for VK_KHR_depth_stencil_resolve src/amd/vulkan/radv_device.c | 21 + src/amd/vulkan/radv_extensions.py | 1 + src/amd/vulkan/radv_meta_clear.c | 73 +++- src/amd/vulkan/radv_meta_resolve.c| 103 - src/amd/vulkan/radv_meta_resolve_cs.c | 491 + src/amd/vulkan/radv_meta_resolve_fs.c | 597 +- src/amd/vulkan/radv_pass.c| 30 +- src/amd/vulkan/radv_private.h | 37 ++ 8 files changed, 1319 insertions(+), 34 deletions(-) -- 2.21.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: Prevent classic swrast crash on a surfaceless context v2.
Reviewed-by: Marek Olšák
M.
On Mon, May 27, 2019, 4:17 AM wrote:
> From: Mathias Fröhlich
>
> Hi Emil,
>
> thanks for that hint to look at _mesa_get_incomplete_framebuffer.
> That one seems definitely more appropriate!
>
> Though, I miss a bit the idea how I can create either a sensible
> helper function for that task or how I can create something above
> in the call stack to the MakeCurrent call that already catches
> this case. Since that incomplete framebuffer is a mesa side thing I
> cannot easily pull that above the __DriverAPIRec::MakeCurrent call.
> But really putting those hand full lines of code into a helper does
> as well not gain much. So I implemented that for the swrast case
> directly.
>
> So, to mention, I sent that change including our egl device code
> with some unrelated egl device fixes through intels CI and did not
> get regressions.
>
> please review
>
> thanks and best
> Mathias
>
>
>
>
>
> This fixes the egl_mesa_platform_surfaceless piglit test as well
> as the new device egl extensions piglit test on classic swrast.
>
> v2: Fix swrast surfaceless contexts on the driver side.
>
> Signed-off-by: Mathias Fröhlich
> ---
> src/mesa/drivers/dri/swrast/swrast.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/swrast/swrast.c
> b/src/mesa/drivers/dri/swrast/swrast.c
> index 36cf11334cb..4899fb2df95 100644
> --- a/src/mesa/drivers/dri/swrast/swrast.c
> +++ b/src/mesa/drivers/dri/swrast/swrast.c
> @@ -36,6 +36,7 @@
> #include "main/api_exec.h"
> #include "main/context.h"
> #include "main/extensions.h"
> +#include "main/fbobject.h"
> #include "main/formats.h"
> #include "main/framebuffer.h"
> #include "main/imports.h"
> @@ -686,7 +687,7 @@ swrast_check_and_update_window_size( struct gl_context
> *ctx, struct gl_framebuff
> {
> GLsizei width, height;
>
> -if (!fb)
> +if (!fb || fb == _mesa_get_incomplete_framebuffer())
> return;
>
> get_window_size(fb, , );
> @@ -884,6 +885,12 @@ dri_make_current(__DRIcontext * cPriv,
> mesaDraw = >Base;
> mesaRead = >Base;
> }
> +else {
> + struct gl_framebuffer *incomplete
> + = _mesa_get_incomplete_framebuffer();
> + mesaDraw = incomplete;
> + mesaRead = incomplete;
> +}
>
> /* check for same context and buffer */
> if (mesaCtx == _mesa_get_current_context()
> --
> 2.21.0
>
>
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[Mesa-dev] [Bug 110761] Huge problems between Mesa and Electron engine apps
https://bugs.freedesktop.org/show_bug.cgi?id=110761 Jakub Okoński changed: What|Removed |Added CC||ja...@okonski.org -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] list: add some iterator debug
On Mon, May 27, 2019 at 4:39 AM Erik Faye-Lund wrote: > > On Mon, 2019-05-27 at 13:37 +0200, Erik Faye-Lund wrote: > > On Mon, 2019-05-27 at 04:23 -0700, Rob Clark wrote: > > > On Mon, May 27, 2019 at 2:50 AM Erik Faye-Lund > > > wrote: > > > > On Sat, 2019-05-25 at 15:44 -0700, Rob Clark wrote: > > > > > This ends up embedded in a for loop expression, ie. the C part > > > > > in > > > > > an > > > > > for (A;B;C) > > > > > > > > > > iirc, that means it needs to be a C expr rather than > > > > > statement.. > > > > > or > > > > > something roughly like that, I'm too lazy to dig out my C > > > > > grammar > > > > > > > > > > > > > Can't you just call a static helper function to do the > > > > validation? > > > > Function calls are valid expressions... > > > > > > I do like the fact that with the current patch I get the correct > > > line > > > # in the assert msg.. but perhaps #ifdef MSVC we can make it a > > > static > > > inline instead? I'm not sure how many people do active feature dev > > > of > > > mesa on windows (as opposed to doing dev on linux and then > > > compiling/shipping non-debug builds on windows), so maybe just > > > disabling the list debug on MSVC is fine. > > > > > > BR, > > > -R > > I guess I should also have mentioned that I *do* sometimes do feature > development for Mesa on Windows, so I'd really like to get to benefit > from debug-helpers. > ok, that was the answer I was looking for, whether it actually benefits anyone to re-invent assert BR, -R ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] list: add some iterator debug
On Mon, 2019-05-27 at 13:37 +0200, Erik Faye-Lund wrote: > On Mon, 2019-05-27 at 04:23 -0700, Rob Clark wrote: > > On Mon, May 27, 2019 at 2:50 AM Erik Faye-Lund > > wrote: > > > On Sat, 2019-05-25 at 15:44 -0700, Rob Clark wrote: > > > > This ends up embedded in a for loop expression, ie. the C part > > > > in > > > > an > > > > for (A;B;C) > > > > > > > > iirc, that means it needs to be a C expr rather than > > > > statement.. > > > > or > > > > something roughly like that, I'm too lazy to dig out my C > > > > grammar > > > > > > > > > > Can't you just call a static helper function to do the > > > validation? > > > Function calls are valid expressions... > > > > I do like the fact that with the current patch I get the correct > > line > > # in the assert msg.. but perhaps #ifdef MSVC we can make it a > > static > > inline instead? I'm not sure how many people do active feature dev > > of > > mesa on windows (as opposed to doing dev on linux and then > > compiling/shipping non-debug builds on windows), so maybe just > > disabling the list debug on MSVC is fine. > > > > BR, > > -R I guess I should also have mentioned that I *do* sometimes do feature development for Mesa on Windows, so I'd really like to get to benefit from debug-helpers. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] list: add some iterator debug
On Mon, 2019-05-27 at 04:23 -0700, Rob Clark wrote:
> On Mon, May 27, 2019 at 2:50 AM Erik Faye-Lund
> wrote:
> > On Sat, 2019-05-25 at 15:44 -0700, Rob Clark wrote:
> > > This ends up embedded in a for loop expression, ie. the C part in
> > > an
> > > for (A;B;C)
> > >
> > > iirc, that means it needs to be a C expr rather than statement..
> > > or
> > > something roughly like that, I'm too lazy to dig out my C grammar
> > >
> >
> > Can't you just call a static helper function to do the validation?
> > Function calls are valid expressions...
>
> I do like the fact that with the current patch I get the correct line
> # in the assert msg.. but perhaps #ifdef MSVC we can make it a static
> inline instead? I'm not sure how many people do active feature dev
> of
> mesa on windows (as opposed to doing dev on linux and then
> compiling/shipping non-debug builds on windows), so maybe just
> disabling the list debug on MSVC is fine.
>
> BR,
> -R
You can just pass __FILE__ and __LINE__ as arguments to the helper, and
not use assert directy but rather fprintf(stderr, ...) and abort. This
is in fact how most custom assert-macros are implemented.
Something like this:
static void
list_assert_helper(bool cond, const char *expr, const char *msg,
const char *file, int line)
{
if (cond) {
fprintf(stderr, "list_assert failed: %s:%d: %s",
file, line, expr);
abort();
}
}
#define list_assert(cond, msg) \
list_assert_helper(LIST_DEBUG && cond, #cond, msg, \
__FILE__, __LINE__)
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Re: [Mesa-dev] [PATCH] list: add some iterator debug
On Mon, May 27, 2019 at 2:50 AM Erik Faye-Lund wrote: > > On Sat, 2019-05-25 at 15:44 -0700, Rob Clark wrote: > > This ends up embedded in a for loop expression, ie. the C part in an > > for (A;B;C) > > > > iirc, that means it needs to be a C expr rather than statement.. or > > something roughly like that, I'm too lazy to dig out my C grammar > > > > Can't you just call a static helper function to do the validation? > Function calls are valid expressions... I do like the fact that with the current patch I get the correct line # in the assert msg.. but perhaps #ifdef MSVC we can make it a static inline instead? I'm not sure how many people do active feature dev of mesa on windows (as opposed to doing dev on linux and then compiling/shipping non-debug builds on windows), so maybe just disabling the list debug on MSVC is fine. BR, -R ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: add radv_clear_htile() helper
r-b
On Wed, May 22, 2019 at 3:35 PM Samuel Pitoiset
wrote:
>
> This helper will be useful for clearing HTILE after some
> depth/stencil resolves.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 7 +--
> src/amd/vulkan/radv_meta.h | 3 +++
> src/amd/vulkan/radv_meta_clear.c | 12
> 3 files changed, 16 insertions(+), 6 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 4f592bc7f68..43730f0568c 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -4389,19 +4389,14 @@ static void radv_initialize_htile(struct
> radv_cmd_buffer *cmd_buffer,
> {
> assert(range->baseMipLevel == 0);
> assert(range->levelCount == 1 || range->levelCount ==
> VK_REMAINING_ARRAY_LAYERS);
> - unsigned layer_count = radv_get_layerCount(image, range);
> - uint64_t size = image->planes[0].surface.htile_slice_size *
> layer_count;
> VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
> - uint64_t offset = image->offset + image->htile_offset +
> - image->planes[0].surface.htile_slice_size *
> range->baseArrayLayer;
> struct radv_cmd_state *state = _buffer->state;
> VkClearDepthStencilValue value = {};
>
> state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
> RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
>
> - state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
> - size, clear_word);
> + state->flush_bits |= radv_clear_htile(cmd_buffer, image, range,
> clear_word);
>
> state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
>
> diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
> index 5e0afd11a00..0bd75d6c207 100644
> --- a/src/amd/vulkan/radv_meta.h
> +++ b/src/amd/vulkan/radv_meta.h
> @@ -211,6 +211,9 @@ uint32_t radv_clear_fmask(struct radv_cmd_buffer
> *cmd_buffer,
> struct radv_image *image, uint32_t value);
> uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
> struct radv_image *image, uint32_t value);
> +uint32_t radv_clear_htile(struct radv_cmd_buffer *cmd_buffer,
> + struct radv_image *image,
> + const VkImageSubresourceRange *range, uint32_t
> value);
>
> /* common nir builder helpers */
> #include "nir/nir_builder.h"
> diff --git a/src/amd/vulkan/radv_meta_clear.c
> b/src/amd/vulkan/radv_meta_clear.c
> index 6c038fa779d..0db5e1db05f 100644
> --- a/src/amd/vulkan/radv_meta_clear.c
> +++ b/src/amd/vulkan/radv_meta_clear.c
> @@ -1344,6 +1344,18 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
> image->planes[0].surface.dcc_size, value);
> }
>
> +uint32_t
> +radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image
> *image,
> +const VkImageSubresourceRange *range, uint32_t value)
> +{
> + unsigned layer_count = radv_get_layerCount(image, range);
> + uint64_t size = image->planes[0].surface.htile_slice_size *
> layer_count;
> + uint64_t offset = image->offset + image->htile_offset +
> + image->planes[0].surface.htile_slice_size *
> range->baseArrayLayer;
> +
> + return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
> +}
> +
> static void vi_get_fast_clear_parameters(VkFormat format,
> const VkClearColorValue *clear_value,
> uint32_t* reset_value,
> --
> 2.21.0
>
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Re: [Mesa-dev] [PATCH] radv: always dirty the framebuffer when restoring a subpass
r-b
On Thu, May 23, 2019 at 2:53 PM Samuel Pitoiset
wrote:
>
> The old code was not wrong because the transitions performed
> after the resolves should re-emit the framebuffer if needed.
>
> This change is mostly a no-op but it improves consistency
> regarding other meta operations that need to save/restore subpasses.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_meta_resolve.c| 3 ++-
> src/amd/vulkan/radv_meta_resolve_fs.c | 3 ++-
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_meta_resolve.c
> b/src/amd/vulkan/radv_meta_resolve.c
> index ade5d438438..b9f5106ef01 100644
> --- a/src/amd/vulkan/radv_meta_resolve.c
> +++ b/src/amd/vulkan/radv_meta_resolve.c
> @@ -691,7 +691,8 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
> *cmd_buffer)
> &(VkExtent2D) { fb->width, fb->height });
> }
>
> - cmd_buffer->state.subpass = subpass;
> + radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
> +
> radv_meta_restore(_state, cmd_buffer);
> }
>
> diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c
> b/src/amd/vulkan/radv_meta_resolve_fs.c
> index 3c63195f48f..9f20f6753e2 100644
> --- a/src/amd/vulkan/radv_meta_resolve_fs.c
> +++ b/src/amd/vulkan/radv_meta_resolve_fs.c
> @@ -632,6 +632,7 @@ radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
> *cmd_buffer)
> &(VkExtent2D) { fb->width, fb->height });
> }
>
> - cmd_buffer->state.subpass = subpass;
> + radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
> +
> radv_meta_restore(_state, cmd_buffer);
> }
> --
> 2.21.0
>
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[Mesa-dev] [PATCH] Revert "st/mesa: expose 0 shader binary formats for compat profiles for Qt"
This reverts commit 55376cb31e2f495a4d872b4ffce2135c3365b873.
It's been over a year and both QT 5.9.5 and 5.11.0 contained a fix for the
original issue. It seems i965 only ever applied this workaround to the
18.0 branch.
---
src/mesa/state_tracker/st_context.c| 2 +-
src/mesa/state_tracker/st_extensions.c | 13 +++--
src/mesa/state_tracker/st_extensions.h | 3 +--
src/mesa/state_tracker/st_manager.c| 2 +-
4 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/src/mesa/state_tracker/st_context.c
b/src/mesa/state_tracker/st_context.c
index 8f2acafbca3..875be9d0029 100644
--- a/src/mesa/state_tracker/st_context.c
+++ b/src/mesa/state_tracker/st_context.c
@@ -645,7 +645,7 @@ st_create_context_priv(struct gl_context *ctx, struct
pipe_context *pipe,
PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET));
/* GL limits and extensions */
- st_init_limits(pipe->screen, >Const, >Extensions, ctx->API);
+ st_init_limits(pipe->screen, >Const, >Extensions);
st_init_extensions(pipe->screen, >Const,
>Extensions, >options, ctx->API);
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 3d5b0fa5836..f930d3caff9 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -76,8 +76,7 @@ static int _clamp(int a, int min, int max)
* Note that we have to limit/clamp against Mesa's internal limits too.
*/
void st_init_limits(struct pipe_screen *screen,
-struct gl_constants *c, struct gl_extensions *extensions,
-gl_api api)
+struct gl_constants *c, struct gl_extensions *extensions)
{
int supported_irs;
unsigned sh;
@@ -447,14 +446,8 @@ void st_init_limits(struct pipe_screen *screen,
c->GLSLFrontFacingIsSysVal =
screen->get_param(screen, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL);
- /* GL_ARB_get_program_binary
-*
-* The QT framework has a bug in their shader program cache, which is built
-* on GL_ARB_get_program_binary. In an effort to allow them to fix the bug
-* we don't enable more than 1 binary format for compatibility profiles.
-*/
- if (api != API_OPENGL_COMPAT &&
- screen->get_disk_shader_cache && screen->get_disk_shader_cache(screen))
+ /* GL_ARB_get_program_binary */
+ if (screen->get_disk_shader_cache && screen->get_disk_shader_cache(screen))
c->NumProgramBinaryFormats = 1;
c->MaxAtomicBufferBindings =
diff --git a/src/mesa/state_tracker/st_extensions.h
b/src/mesa/state_tracker/st_extensions.h
index fdfac7ece70..7bf1aa8c8cb 100644
--- a/src/mesa/state_tracker/st_extensions.h
+++ b/src/mesa/state_tracker/st_extensions.h
@@ -35,8 +35,7 @@ struct pipe_screen;
extern void st_init_limits(struct pipe_screen *screen,
struct gl_constants *c,
- struct gl_extensions *extensions,
- gl_api api);
+ struct gl_extensions *extensions);
extern void st_init_extensions(struct pipe_screen *screen,
struct gl_constants *consts,
diff --git a/src/mesa/state_tracker/st_manager.c
b/src/mesa/state_tracker/st_manager.c
index 35d41f0a2c1..ff0bec8f569 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -1269,7 +1269,7 @@ get_version(struct pipe_screen *screen,
_mesa_init_constants(, api);
_mesa_init_extensions();
- st_init_limits(screen, , , api);
+ st_init_limits(screen, , );
st_init_extensions(screen, , , options, api);
return _mesa_get_version(, , api);
--
2.20.1
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Re: [Mesa-dev] [PATCH] list: add some iterator debug
On Sat, 2019-05-25 at 15:44 -0700, Rob Clark wrote:
> This ends up embedded in a for loop expression, ie. the C part in an
> for (A;B;C)
>
> iirc, that means it needs to be a C expr rather than statement.. or
> something roughly like that, I'm too lazy to dig out my C grammar
>
Can't you just call a static helper function to do the validation?
Function calls are valid expressions...
> BR,
> -R
>
>
> On Sat, May 25, 2019 at 3:39 PM Ilia Mirkin
> wrote:
> > Why not just do it in a way that works for everyone? Both the
> > do/while
> > method and the ifdef-based method that I suggested work everywhere.
> > Or
> > is there another reason you prefer to use those statement
> > expressions?
> >
> > On Sat, May 25, 2019 at 6:21 PM Rob Clark
> > wrote:
> > > Is there a convenient #ifdef I can use to guard the list_assert()
> > > macro.. I don't really mind if MSVC can't have this, but would
> > > rather
> > > not let it prevent the rest of us from having nice things
> > >
> > > BR,
> > > -R
> > >
> > > On Sat, May 25, 2019 at 1:23 PM Jason Ekstrand <
> > > ja...@jlekstrand.net> wrote:
> > > > Yeah, that's a GNU extension. It also works in clang but not
> > > > MSVC which is
> > > > used to build NIR.
> > > >
> > > > On May 25, 2019 13:30:29 Rob Clark wrote:
> > > >
> > > > > On Sat, May 25, 2019 at 11:13 AM Ilia Mirkin <
> > > > > imir...@alum.mit.edu> wrote:
> > > > > > On Sat, May 25, 2019 at 2:03 PM Rob Clark <
> > > > > > robdcl...@gmail.com> wrote:
> > > > > > > From: Rob Clark
> > > > > > >
> > > > > > > Debugging use of unsafe iterators when you should have
> > > > > > > used the _safe
> > > > > > > version sucks. Add some DEBUG build support to catch and
> > > > > > > assert if
> > > > > > > someone does that.
> > > > > > >
> > > > > > > I didn't update the UPPERCASE verions of the
> > > > > > > iterators. They should
> > > > > > > probably be deprecated/removed.
> > > > > > >
> > > > > > > Signed-off-by: Rob Clark
> > > > > > > ---
> > > > > > > src/util/list.h | 23 ++-
> > > > > > > 1 file changed, 18 insertions(+), 5 deletions(-)
> > > > > > >
> > > > > > > diff --git a/src/util/list.h b/src/util/list.h
> > > > > > > index 09d1b4cae64..6d89a42b226 100644
> > > > > > > --- a/src/util/list.h
> > > > > > > +++ b/src/util/list.h
> > > > > > > @@ -43,6 +43,13 @@
> > > > > > > #include
> > > > > > > #include "c99_compat.h"
> > > > > > >
> > > > > > > +#ifdef DEBUG
> > > > > > > +# define LIST_DEBUG 1
> > > > > > > +#else
> > > > > > > +# define LIST_DEBUG 0
> > > > > > > +#endif
> > > > > > > +
> > > > > > > +#define list_assert(cond, msg) ({ if (LIST_DEBUG)
> > > > > > > assert((cond) && msg); })
> > > > > >
> > > > > > Not sure if it's worth worrying about, but this style of
> > > > > > macro
> > > > > > definition can be dangerous. One might use it as
> > > > > >
> > > > > > if (x) list_assert()
> > > > > > else blah;
> > > > > >
> > > > > > With the macro defined as-is, the "else blah" will get
> > > > > > attached to the
> > > > > > if in the macro. I believe the common style is to do do
> > > > > > {}while(0) to
> > > > > > avoid such issues (or to use an inline function).
> > > > > > Alternatively, just
> > > > > > define it differently for LIST_DEBUG vs not.
> > > > > >
> > > > >
> > > > > I think the ({ ... }) should save the day..
> > > > >
> > > > > (hmm, is that c99 or a gnu thing? I've it isn't avail on
> > > > > some
> > > > > compilers I guess we should disable list_assert() for those?)
> > > > >
> > > > > BR,
> > > > > -R
> > > > > ___
> > > > > mesa-dev mailing list
> > > > > mesa-dev@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > > >
> > > >
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Re: [Mesa-dev] [PATCH] gallivm: fix default cbuf info.
On Fri, 2019-05-24 at 03:08 +0200, srol...@vmware.com wrote:
> From: Roland Scheidegger
>
> The default null_output really needs to be static, otherwise the values
> we'll eventually get later are doubly random (they are not initialized,
> and even if they were it's a pointer to a local stack variable).
> VMware bug 2349556.
Shouldn't this be CC to @stable ?
> ---
> src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
> b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
> index b4e3c2fbc8..9fc9b8c77e 100644
> --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
> +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
> @@ -608,7 +608,7 @@ finished:
> */
>
> for (index = 0; index < PIPE_MAX_COLOR_BUFS; ++index) {
> - const struct lp_tgsi_channel_info null_output[4];
> + static const struct lp_tgsi_channel_info null_output[4];
>info->cbuf[index] = null_output;
> }
>
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Re: [Mesa-dev] [PATCH v2 1/2] nir/algebraic: Simplify max(abs(a), 0.0) -> abs(a)
On Sun, May 26, 2019 at 01:52:44AM +, Alyssa Rosenzweig wrote:
> I noticed this pattern in glmark's jellyfish scene.
>
> v2: Add inexact qualifier to avoid changing NaN behaviour
>
> I would appreciate if someone did a shader-db run.
>
> Signed-off-by: Alyssa Rosenzweig
Reviewed-by: Elie Tournier
For the shader-db, I got:
total instructions in shared programs: 12839341 -> 12839254 (<.01%)
instructions in affected programs: 5885 -> 5798 (-1.48%)
helped: 41
HURT: 0
total cycles in shared programs: 302490031 -> 302487788 (<.01%)
cycles in affected programs: 485428 -> 483185 (-0.46%)
helped: 20
HURT: 1
> Cc: Ilia Mirkin
> Cc: Ian Romanick
> Cc: Elie Tournier
> ---
> src/compiler/nir/nir_opt_algebraic.py | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/compiler/nir/nir_opt_algebraic.py
> b/src/compiler/nir/nir_opt_algebraic.py
> index 89d07aa1261..e607e5b6fe2 100644
> --- a/src/compiler/nir/nir_opt_algebraic.py
> +++ b/src/compiler/nir/nir_opt_algebraic.py
> @@ -397,6 +397,7 @@ optimizations = [
> (('imax', a, ('iabs', a)), ('iabs', a)),
> (('fmax', a, ('fneg', a)), ('fabs', a)),
> (('imax', a, ('ineg', a)), ('iabs', a)),
> + (('~fmax', ('fabs', a), 0.0), ('fabs', a)),
> (('~fmin', ('fmax', a, 0.0), 1.0), ('fsat', a), '!options->lower_fsat'),
> (('~fmax', ('fmin', a, 1.0), 0.0), ('fsat', a), '!options->lower_fsat'),
> (('~fmin', ('fmax', a, -1.0), 0.0), ('fneg', ('fsat', ('fneg', a))),
> '!options->lower_negate && !options->lower_fsat'),
> --
> 2.20.1
>
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Re: [Mesa-dev] [PATCH] etnaviv: rs: choose clear format based on block size
Am Sonntag, den 26.05.2019, 21:06 +0200 schrieb Christian Gmeiner:
> Fixes following piglit and does not introduce any regressions.
> spec@ext_packed_depth_stencil@fbo-depth-gl_depth24_stencil8-blit
>
> Signed-off-by: Christian Gmeiner
Reviewed-by: Lucas Stach
> ---
> src/gallium/drivers/etnaviv/etnaviv_rs.c | 14 +-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_rs.c
> b/src/gallium/drivers/etnaviv/etnaviv_rs.c
> index e64babfdd0a..8c85f329f76 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_rs.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_rs.c
> @@ -254,7 +254,19 @@ etna_rs_gen_clear_surface(struct etna_context *ctx,
> struct etna_surface *surf,
> uint32_t clear_value)
> {
> struct etna_resource *dst = etna_resource(surf->base.texture);
> - uint32_t format = translate_rs_format(surf->base.format);
> + uint32_t format;
> +
> + switch (util_format_get_blocksizebits(surf->base.format)) {
> + case 16:
> + format = RS_FORMAT_A4R4G4B4;
> + break;
> + case 32:
> + format = RS_FORMAT_A8R8G8B8;
> + break;
> + default:
> + format = ETNA_NO_MATCH;
> + break;
> + }
>
> if (format == ETNA_NO_MATCH) {
> BUG("etna_rs_gen_clear_surface: Unhandled clear fmt %s",
> util_format_name(surf->base.format));
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Re: [Mesa-dev] [PATCH v2] radv: ignore the loadOp if the first use of an attachment is a resolve
R-b On Mon, May 27, 2019, 10:16 AM Samuel Pitoiset wrote: > Based on ANV. > > v2: - remove the if statement > - update the comment > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_meta_resolve.c | 12 +++- > 1 file changed, 3 insertions(+), 9 deletions(-) > > diff --git a/src/amd/vulkan/radv_meta_resolve.c > b/src/amd/vulkan/radv_meta_resolve.c > index ade5d438438..ca5cf22f0d7 100644 > --- a/src/amd/vulkan/radv_meta_resolve.c > +++ b/src/amd/vulkan/radv_meta_resolve.c > @@ -618,15 +618,6 @@ radv_cmd_buffer_resolve_subpass(struct > radv_cmd_buffer *cmd_buffer) > struct radv_meta_saved_state saved_state; > enum radv_resolve_method resolve_method = RESOLVE_HW; > > - /* FINISHME(perf): Skip clears for resolve attachments. > -* > -* From the Vulkan 1.0 spec: > -* > -*If the first use of an attachment in a render pass is as a > resolve > -*attachment, then the loadOp is effectively ignored as the > resolve is > -*guaranteed to overwrite all pixels in the render area. > -*/ > - > if (!subpass->has_resolve) > return; > > @@ -637,6 +628,9 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer > *cmd_buffer) > if (dest_att.attachment == VK_ATTACHMENT_UNUSED) > continue; > > + /* Make sure to not clear color attachments after > resolves. */ > + > cmd_buffer->state.attachments[dest_att.attachment].pending_clear_aspects = > 0; > + > struct radv_image *dst_img = > cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image; > struct radv_image *src_img = > cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment->image; > > -- > 2.21.0 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa: Prevent classic swrast crash on a surfaceless context v2.
From: Mathias Fröhlich
Hi Emil,
thanks for that hint to look at _mesa_get_incomplete_framebuffer.
That one seems definitely more appropriate!
Though, I miss a bit the idea how I can create either a sensible
helper function for that task or how I can create something above
in the call stack to the MakeCurrent call that already catches
this case. Since that incomplete framebuffer is a mesa side thing I
cannot easily pull that above the __DriverAPIRec::MakeCurrent call.
But really putting those hand full lines of code into a helper does
as well not gain much. So I implemented that for the swrast case
directly.
So, to mention, I sent that change including our egl device code
with some unrelated egl device fixes through intels CI and did not
get regressions.
please review
thanks and best
Mathias
This fixes the egl_mesa_platform_surfaceless piglit test as well
as the new device egl extensions piglit test on classic swrast.
v2: Fix swrast surfaceless contexts on the driver side.
Signed-off-by: Mathias Fröhlich
---
src/mesa/drivers/dri/swrast/swrast.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/swrast/swrast.c
b/src/mesa/drivers/dri/swrast/swrast.c
index 36cf11334cb..4899fb2df95 100644
--- a/src/mesa/drivers/dri/swrast/swrast.c
+++ b/src/mesa/drivers/dri/swrast/swrast.c
@@ -36,6 +36,7 @@
#include "main/api_exec.h"
#include "main/context.h"
#include "main/extensions.h"
+#include "main/fbobject.h"
#include "main/formats.h"
#include "main/framebuffer.h"
#include "main/imports.h"
@@ -686,7 +687,7 @@ swrast_check_and_update_window_size( struct gl_context
*ctx, struct gl_framebuff
{
GLsizei width, height;
-if (!fb)
+if (!fb || fb == _mesa_get_incomplete_framebuffer())
return;
get_window_size(fb, , );
@@ -884,6 +885,12 @@ dri_make_current(__DRIcontext * cPriv,
mesaDraw = >Base;
mesaRead = >Base;
}
+else {
+ struct gl_framebuffer *incomplete
+ = _mesa_get_incomplete_framebuffer();
+ mesaDraw = incomplete;
+ mesaRead = incomplete;
+}
/* check for same context and buffer */
if (mesaCtx == _mesa_get_current_context()
--
2.21.0
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[Mesa-dev] [PATCH v2] radv: ignore the loadOp if the first use of an attachment is a resolve
Based on ANV. v2: - remove the if statement - update the comment Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_resolve.c | 12 +++- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c index ade5d438438..ca5cf22f0d7 100644 --- a/src/amd/vulkan/radv_meta_resolve.c +++ b/src/amd/vulkan/radv_meta_resolve.c @@ -618,15 +618,6 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer) struct radv_meta_saved_state saved_state; enum radv_resolve_method resolve_method = RESOLVE_HW; - /* FINISHME(perf): Skip clears for resolve attachments. -* -* From the Vulkan 1.0 spec: -* -*If the first use of an attachment in a render pass is as a resolve -*attachment, then the loadOp is effectively ignored as the resolve is -*guaranteed to overwrite all pixels in the render area. -*/ - if (!subpass->has_resolve) return; @@ -637,6 +628,9 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer) if (dest_att.attachment == VK_ATTACHMENT_UNUSED) continue; + /* Make sure to not clear color attachments after resolves. */ + cmd_buffer->state.attachments[dest_att.attachment].pending_clear_aspects = 0; + struct radv_image *dst_img = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image; struct radv_image *src_img = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment->image; -- 2.21.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: ignore the loadOp if the first use of an attachment is a resolve
On 5/26/19 2:50 PM, Bas Nieuwenhuizen wrote:
On Wed, May 22, 2019 at 11:20 AM Samuel Pitoiset
wrote:
Based on ANV.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_resolve.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_resolve.c
b/src/amd/vulkan/radv_meta_resolve.c
index ade5d438438..6a8abce1ddb 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -618,15 +618,6 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer)
struct radv_meta_saved_state saved_state;
enum radv_resolve_method resolve_method = RESOLVE_HW;
- /* FINISHME(perf): Skip clears for resolve attachments.
-*
-* From the Vulkan 1.0 spec:
-*
-*If the first use of an attachment in a render pass is as a resolve
-*attachment, then the loadOp is effectively ignored as the resolve
is
-*guaranteed to overwrite all pixels in the render area.
-*/
-
if (!subpass->has_resolve)
return;
@@ -637,6 +628,18 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer)
if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
continue;
+ if
(cmd_buffer->state.attachments[dest_att.attachment].pending_clear_aspects) {
+ /* From the Vulkan 1.0 spec:
+*
+*If the first use of an attachment in a render
+*pass is as a resolve attachment, then the loadOp
+*is effectively ignored as the resolve is
+*guaranteed to overwrite all pixels in the render
+*area.
+ */
+
cmd_buffer->state.attachments[dest_att.attachment].pending_clear_aspects = 0;
+ }
+
You can drop the if statement. Also this seems like a correctness
issue, as we only cleared the first time it was used as a color
attachment, which might happen after a resolve?
Yeah, looks good to me.
I will remove the if statement and update the comment too because the
spec no longer says that since VK_KHR_depth_stencil_resolve.
Though, we should still make sure that clears don't happen after resolves.
struct radv_image *dst_img =
cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image;
struct radv_image *src_img =
cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment->image;
--
2.21.0
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Re: [Mesa-dev] [PATCH] r600: Cleanup "nir" debug option.
On So, 2019-05-26 at 21:45 +0200, Bas Nieuwenhuizen wrote:
> r600g does not have a nir compiler,
I'm working on this in an out of tree bruch, but well, I can always re-
introduce the flag when I start to upstream this, so keep it or leave
it.
Ack-by: Gert Wollny
> and radeonsi does not use the
> option either.
> ---
> src/gallium/drivers/r600/r600_pipe_common.c | 1 -
> src/gallium/drivers/r600/r600_pipe_common.h | 2 +-
> 2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/r600_pipe_common.c
> b/src/gallium/drivers/r600/r600_pipe_common.c
> index 5177ff4e1c6..b1ad0d7d23b 100644
> --- a/src/gallium/drivers/r600/r600_pipe_common.c
> +++ b/src/gallium/drivers/r600/r600_pipe_common.c
> @@ -741,7 +741,6 @@ void r600_common_context_cleanup(struct
> r600_common_context *rctx)
> static const struct debug_named_value common_debug_options[] = {
> /* logging */
> { "tex", DBG_TEX, "Print texture info" },
> - { "nir", DBG_NIR, "Enable experimental NIR shaders" },
> { "compute", DBG_COMPUTE, "Print compute info" },
> { "vm", DBG_VM, "Print virtual addresses when creating
> resources" },
> { "info", DBG_INFO, "Print driver information" },
> diff --git a/src/gallium/drivers/r600/r600_pipe_common.h
> b/src/gallium/drivers/r600/r600_pipe_common.h
> index b43b7eecd10..4136ba5b565 100644
> --- a/src/gallium/drivers/r600/r600_pipe_common.h
> +++ b/src/gallium/drivers/r600/r600_pipe_common.h
> @@ -78,7 +78,7 @@ struct u_log_context;
> #define DBG_ALL_SHADERS (DBG_FS - 1)
> #define DBG_FS (1 << 6) /* fetch shader */
> #define DBG_TEX (1 << 7)
> -#define DBG_NIR (1 << 8)
> +/* gap */
> #define DBG_COMPUTE (1 << 9)
> /* gap */
> #define DBG_VM (1 << 11)
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