Re: [Mesa-dev] [PATCH] radv: Only save the descriptor set if we have one.
Reviewed-by: Dave Airlie
On Wed, 17 Jul 2019 at 11:01, Bas Nieuwenhuizen
wrote:
>
> After reset, if valid does not contain the relevant bit the descriptor
> can be != NULL but still not be valid.
>
> CC:
> ---
> src/amd/vulkan/radv_meta.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
> index 5e619c2f181..448a6168bd2 100644
> --- a/src/amd/vulkan/radv_meta.c
> +++ b/src/amd/vulkan/radv_meta.c
> @@ -86,7 +86,7 @@ radv_meta_save(struct radv_meta_saved_state *state,
>
> if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
> state->old_descriptor_set0 = descriptors_state->sets[0];
> - if (!state->old_descriptor_set0)
> + if (!(descriptors_state->valid & 1) ||
> !state->old_descriptor_set0)
> state->flags &= ~RADV_META_SAVE_DESCRIPTORS;
> }
>
> --
> 2.21.0
>
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[Mesa-dev] [PATCH] radv: use correct register setter for ngg hw addr
From: Dave Airlie this shouldn't matter, but it's good to be correct. --- src/amd/vulkan/radv_pipeline.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 5cdfe6d24eb..c7660c2900c 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3408,7 +3408,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2); radeon_emit(cs, va >> 8); - radeon_emit(cs, va >> 40); + radeon_emit(cs, S_00B324_MEM_BASE(va >> 40)); radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2); radeon_emit(cs, shader->config.rsrc1); radeon_emit(cs, shader->config.rsrc2); -- 2.21.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111107] 726a31df705b causes pipeline creation to use up to 5x more memory (which is not freed on pipeline destruction)
https://bugs.freedesktop.org/show_bug.cgi?id=07 --- Comment #2 from Timothy Arceri --- Fix: https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1360 -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv: Only save the descriptor set if we have one.
After reset, if valid does not contain the relevant bit the descriptor
can be != NULL but still not be valid.
CC:
---
src/amd/vulkan/radv_meta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index 5e619c2f181..448a6168bd2 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -86,7 +86,7 @@ radv_meta_save(struct radv_meta_saved_state *state,
if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
state->old_descriptor_set0 = descriptors_state->sets[0];
- if (!state->old_descriptor_set0)
+ if (!(descriptors_state->valid & 1) ||
!state->old_descriptor_set0)
state->flags &= ~RADV_META_SAVE_DESCRIPTORS;
}
--
2.21.0
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[Mesa-dev] [Bug 110703] libGL conflicts with Exagear's X11
https://bugs.freedesktop.org/show_bug.cgi?id=110703 Timothy Arceri changed: What|Removed |Added Product|Mesa|Spam QA Contact|mesa-dev@lists.freedesktop. | |org | Component|GLX |Two Version|git |unspecified Assignee|mesa-dev@lists.freedesktop. |dan...@fooishbar.org |org | --- Comment #10 from Timothy Arceri --- I don't think this is a Mesa bug. I suggest you try wine for android instead [1]. Marking this bug as spam because you added a link to pirated software. [1] https://dl.winehq.org/wine-builds/android/ -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv/gfx10: implement VK_EXT_post_depth_coverage
r-b
On Tue, Jul 16, 2019 at 5:11 PM Samuel Pitoiset
wrote:
>
> I did implement this extension a while ago but it didn't work
> on pre GFX10 for some reasons. Now all CTS pass.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_extensions.py | 1 +
> src/amd/vulkan/radv_nir_to_llvm.c | 1 +
> src/amd/vulkan/radv_pipeline.c| 1 +
> src/amd/vulkan/radv_shader.c | 1 +
> src/amd/vulkan/radv_shader.h | 1 +
> 5 files changed, 5 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_extensions.py
> b/src/amd/vulkan/radv_extensions.py
> index 8b6ba6a4df0..e9addad0035 100644
> --- a/src/amd/vulkan/radv_extensions.py
> +++ b/src/amd/vulkan/radv_extensions.py
> @@ -120,6 +120,7 @@ EXTENSIONS = [
> Extension('VK_EXT_memory_priority', 1, True),
> Extension('VK_EXT_pci_bus_info', 2, True),
> Extension('VK_EXT_pipeline_creation_feedback',1, True),
> +Extension('VK_EXT_post_depth_coverage', 1,
> 'device->rad_info.chip_class >= GFX10'),
> Extension('VK_EXT_queue_family_foreign', 1, True),
> Extension('VK_EXT_sample_locations', 1, True),
> Extension('VK_EXT_sampler_filter_minmax', 1,
> 'device->rad_info.chip_class >= GFX7'),
> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
> b/src/amd/vulkan/radv_nir_to_llvm.c
> index a689003d473..3e18303879e 100644
> --- a/src/amd/vulkan/radv_nir_to_llvm.c
> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> @@ -4637,6 +4637,7 @@ ac_fill_shader_info(struct radv_shader_variant_info
> *shader_info, struct nir_sha
> break;
> case MESA_SHADER_FRAGMENT:
> shader_info->fs.early_fragment_test =
> nir->info.fs.early_fragment_tests;
> +shader_info->fs.post_depth_coverage =
> nir->info.fs.post_depth_coverage;
> break;
> case MESA_SHADER_GEOMETRY:
> shader_info->gs.vertices_in = nir->info.gs.vertices_in;
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index 31495ec078d..7056ac8ca60 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -3822,6 +3822,7 @@ radv_compute_db_shader_control(const struct radv_device
> *device,
> S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
> S_02880C_Z_ORDER(z_order) |
> S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test)
> |
> +
> S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.fs.post_depth_coverage) |
> S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
> S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
> S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index 1e9399de193..75f1ce3e869 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -270,6 +270,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
> .int64_atomics = true,
> .multiview = true,
> .physical_storage_buffer_address = true,
> + .post_depth_coverage = true,
> .runtime_descriptor_array = true,
> .shader_viewport_index_layer = true,
> .stencil_export = true,
> diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
> index 360591349a8..fea0d1c8df1 100644
> --- a/src/amd/vulkan/radv_shader.h
> +++ b/src/amd/vulkan/radv_shader.h
> @@ -283,6 +283,7 @@ struct radv_shader_variant_info {
> uint32_t float16_shaded_mask;
> bool can_discard;
> bool early_fragment_test;
> + bool post_depth_coverage;
> } fs;
> struct {
> unsigned block_size[3];
> --
> 2.22.0
>
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Re: [Mesa-dev] [PATCH 2/2] radv/gfx10: fallback to the legacy path if tess and extreme geometry
r-b for the series
On Tue, Jul 16, 2019 at 4:39 PM Samuel Pitoiset
wrote:
>
> This is unsupported and hangs.
>
> This fixes GPU hangs with
> dEQP-VK.tessellation.geometry_interaction.limits.output_required_*.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_pipeline.c | 12
> src/amd/vulkan/radv_shader.c | 2 +-
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index d1eede172dc..a22e605ca1c 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -2306,6 +2306,18 @@ radv_fill_shader_keys(struct radv_device *device,
> } else {
> keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
> }
> +
> + if (nir[MESA_SHADER_TESS_CTRL] &&
> + nir[MESA_SHADER_GEOMETRY] &&
> + nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
> + nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
> + /* Fallback to the legacy path if tessellation is
> +* enabled with extreme geometry because
> +* EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
> +* might hang.
> +*/
> + keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg =
> false;
> + }
> }
>
> for(int i = 0; i < MESA_SHADER_STAGES; ++i)
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index 1e9399de193..6bafcb2f869 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -796,7 +796,7 @@ static void radv_postprocess_config(const struct
> radv_physical_device *pdevice,
> break;
> }
>
> - if (pdevice->rad_info.chip_class >= GFX10 &&
> + if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
> (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL ||
> stage == MESA_SHADER_GEOMETRY)) {
> unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
> gl_shader_stage es_stage = stage;
> --
> 2.22.0
>
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Re: [Mesa-dev] [PATCH] radv/gfx10: disable the TC compat zrange workaround
r-b
On Tue, Jul 16, 2019 at 5:35 PM Samuel Pitoiset
wrote:
>
> Unnecessary.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 7 ++-
> src/amd/vulkan/radv_device.c | 2 ++
> src/amd/vulkan/radv_image.c | 7 ---
> src/amd/vulkan/radv_private.h| 1 +
> 4 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/radv_cmd_buffer.c
> index a6d4e0d0e21..b4301c0da15 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1356,7 +1356,8 @@ radv_update_zrange_precision(struct radv_cmd_buffer
> *cmd_buffer,
> uint32_t db_z_info = ds->db_z_info;
> uint32_t db_z_info_reg;
>
> - if (!radv_image_is_tc_compat_htile(image))
> + if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug ||
> + !radv_image_is_tc_compat_htile(image))
> return;
>
> if (!radv_layout_has_htile(image, layout,
> @@ -1566,6 +1567,10 @@ radv_set_tc_compat_zrange_metadata(struct
> radv_cmd_buffer *cmd_buffer,
> {
> struct radeon_cmdbuf *cs = cmd_buffer->cs;
> uint64_t va = radv_buffer_get_va(image->bo);
> +
> + if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug)
> + return;
> +
> va += image->offset + image->tc_compat_zrange_offset;
>
> radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3,
> cmd_buffer->state.predicating));
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 9d75305fc2b..b397a9a8aa0 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -363,6 +363,8 @@ radv_physical_device_init(struct radv_physical_device
> *device,
> device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
> device->rad_info.family == CHIP_RAVEN;
>
> + device->has_tc_compat_zrange_bug = device->rad_info.chip_class <
> GFX10;
> +
> /* Out-of-order primitive rasterization. */
> device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
> device->rad_info.max_se >= 2;
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index ccbec36849e..4d3ed71c23c 100644
> --- a/src/amd/vulkan/radv_image.c
> +++ b/src/amd/vulkan/radv_image.c
> @@ -1186,14 +1186,15 @@ radv_image_alloc_dcc(struct radv_image *image)
> }
>
> static void
> -radv_image_alloc_htile(struct radv_image *image)
> +radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
> {
> image->htile_offset = align64(image->size,
> image->planes[0].surface.htile_alignment);
>
> /* + 8 for storing the clear values */
> image->clear_value_offset = image->htile_offset +
> image->planes[0].surface.htile_size;
> image->size = image->clear_value_offset + 8;
> - if (radv_image_is_tc_compat_htile(image)) {
> + if (radv_image_is_tc_compat_htile(image) &&
> + device->physical_device->has_tc_compat_zrange_bug) {
> /* Metadata for the TC-compatible HTILE hardware bug which
> * have to be fixed by updating ZRANGE_PRECISION when doing
> * fast depth clears to 0.0f.
> @@ -1402,7 +1403,7 @@ radv_image_create(VkDevice _device,
> if (radv_image_can_enable_htile(image) &&
> !(device->instance->debug_flags &
> RADV_DEBUG_NO_HIZ)) {
> image->tc_compatible_htile =
> image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
> - radv_image_alloc_htile(image);
> + radv_image_alloc_htile(device, image);
> } else {
> radv_image_disable_htile(image);
> }
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index e1b5b456ef3..931d4039397 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -317,6 +317,7 @@ struct radv_physical_device {
> bool has_clear_state;
> bool cpdma_prefetch_writes_memory;
> bool has_scissor_bug;
> + bool has_tc_compat_zrange_bug;
>
> bool has_out_of_order_rast;
> bool out_of_order_rast_allowed;
> --
> 2.22.0
>
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[Mesa-dev] [Bug 111151] vkGetRandROutputDisplayEXT returns VK_SUCCESS on failure
https://bugs.freedesktop.org/show_bug.cgi?id=51 Drew DeVault changed: What|Removed |Added CC||kei...@keithp.com, ||s...@cmpwn.com -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111151] vkGetRandROutputDisplayEXT returns VK_SUCCESS on failure
https://bugs.freedesktop.org/show_bug.cgi?id=51 Bug ID: 51 Summary: vkGetRandROutputDisplayEXT returns VK_SUCCESS on failure Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/Vulkan/Common Assignee: mesa-dev@lists.freedesktop.org Reporter: s...@cmpwn.com CC: airl...@freedesktop.org, chadvers...@chromium.org, ja...@jlekstrand.net If the output does not have a CONNECTOR_ID atom, then this function fails (giving back a 0 VkDisplayKHR) but it returns VK_SUCCESS nonetheless. Passing this VkDisplayKHR into vkAcquireXlibDisplayEXT later then segfaults mesa. -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [AppVeyor] mesa master #11902 failed
Build mesa 11902 failed Commit 856e84083e by Rob Clark on 7/15/2019 4:05 PM: mesa/st: add sampler uniforms\n\nAdd sampler uniforms for the UV plane(s), so driver can count the\nuniforms and get the correct sampler count.\n\nFixes lowered YUV on a6xx which actually wants to know # of samplers.\n\nSigned-off-by: Rob Clark \nReviewed-by: Kristian H. Kristensen \nReviewed-by: Eric Anholt Configure your notification preferences ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111150] [BRW] WRC 5 asserts with gallium nine and iris.
https://bugs.freedesktop.org/show_bug.cgi?id=50 --- Comment #1 from Nanley Chery --- Is the tiling of the surface X-tiled? My guess is that this commit enables CCS for X-tiled images used for display. This now causes us to fast-clear the image in NineSurface9_ctor. When resource_get_handle is called (from D3DWindowBuffer_create?) we're not flushing/resolving as expected when PIPE_HANDLE_USAGE_EXPLICIT_FLUSH flag is passed in as an argument. Does adding the following in iris_resource_get_handle fix it? if ((usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0) iris_flush_resource(ctx, res); -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv/gfx10: disable the TC compat zrange workaround
Unnecessary.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 7 ++-
src/amd/vulkan/radv_device.c | 2 ++
src/amd/vulkan/radv_image.c | 7 ---
src/amd/vulkan/radv_private.h| 1 +
4 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index a6d4e0d0e21..b4301c0da15 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1356,7 +1356,8 @@ radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer,
uint32_t db_z_info = ds->db_z_info;
uint32_t db_z_info_reg;
- if (!radv_image_is_tc_compat_htile(image))
+ if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug ||
+ !radv_image_is_tc_compat_htile(image))
return;
if (!radv_layout_has_htile(image, layout,
@@ -1566,6 +1567,10 @@ radv_set_tc_compat_zrange_metadata(struct
radv_cmd_buffer *cmd_buffer,
{
struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(image->bo);
+
+ if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug)
+ return;
+
va += image->offset + image->tc_compat_zrange_offset;
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3,
cmd_buffer->state.predicating));
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 9d75305fc2b..b397a9a8aa0 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -363,6 +363,8 @@ radv_physical_device_init(struct radv_physical_device
*device,
device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
device->rad_info.family == CHIP_RAVEN;
+ device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
+
/* Out-of-order primitive rasterization. */
device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
device->rad_info.max_se >= 2;
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index ccbec36849e..4d3ed71c23c 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -1186,14 +1186,15 @@ radv_image_alloc_dcc(struct radv_image *image)
}
static void
-radv_image_alloc_htile(struct radv_image *image)
+radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
{
image->htile_offset = align64(image->size,
image->planes[0].surface.htile_alignment);
/* + 8 for storing the clear values */
image->clear_value_offset = image->htile_offset +
image->planes[0].surface.htile_size;
image->size = image->clear_value_offset + 8;
- if (radv_image_is_tc_compat_htile(image)) {
+ if (radv_image_is_tc_compat_htile(image) &&
+ device->physical_device->has_tc_compat_zrange_bug) {
/* Metadata for the TC-compatible HTILE hardware bug which
* have to be fixed by updating ZRANGE_PRECISION when doing
* fast depth clears to 0.0f.
@@ -1402,7 +1403,7 @@ radv_image_create(VkDevice _device,
if (radv_image_can_enable_htile(image) &&
!(device->instance->debug_flags &
RADV_DEBUG_NO_HIZ)) {
image->tc_compatible_htile =
image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
- radv_image_alloc_htile(image);
+ radv_image_alloc_htile(device, image);
} else {
radv_image_disable_htile(image);
}
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index e1b5b456ef3..931d4039397 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -317,6 +317,7 @@ struct radv_physical_device {
bool has_clear_state;
bool cpdma_prefetch_writes_memory;
bool has_scissor_bug;
+ bool has_tc_compat_zrange_bug;
bool has_out_of_order_rast;
bool out_of_order_rast_allowed;
--
2.22.0
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[Mesa-dev] [PATCH] radv/gfx10: implement VK_EXT_post_depth_coverage
I did implement this extension a while ago but it didn't work
on pre GFX10 for some reasons. Now all CTS pass.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_extensions.py | 1 +
src/amd/vulkan/radv_nir_to_llvm.c | 1 +
src/amd/vulkan/radv_pipeline.c| 1 +
src/amd/vulkan/radv_shader.c | 1 +
src/amd/vulkan/radv_shader.h | 1 +
5 files changed, 5 insertions(+)
diff --git a/src/amd/vulkan/radv_extensions.py
b/src/amd/vulkan/radv_extensions.py
index 8b6ba6a4df0..e9addad0035 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -120,6 +120,7 @@ EXTENSIONS = [
Extension('VK_EXT_memory_priority', 1, True),
Extension('VK_EXT_pci_bus_info', 2, True),
Extension('VK_EXT_pipeline_creation_feedback',1, True),
+Extension('VK_EXT_post_depth_coverage', 1,
'device->rad_info.chip_class >= GFX10'),
Extension('VK_EXT_queue_family_foreign', 1, True),
Extension('VK_EXT_sample_locations', 1, True),
Extension('VK_EXT_sampler_filter_minmax', 1,
'device->rad_info.chip_class >= GFX7'),
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index a689003d473..3e18303879e 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -4637,6 +4637,7 @@ ac_fill_shader_info(struct radv_shader_variant_info
*shader_info, struct nir_sha
break;
case MESA_SHADER_FRAGMENT:
shader_info->fs.early_fragment_test =
nir->info.fs.early_fragment_tests;
+shader_info->fs.post_depth_coverage =
nir->info.fs.post_depth_coverage;
break;
case MESA_SHADER_GEOMETRY:
shader_info->gs.vertices_in = nir->info.gs.vertices_in;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 31495ec078d..7056ac8ca60 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3822,6 +3822,7 @@ radv_compute_db_shader_control(const struct radv_device
*device,
S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
S_02880C_Z_ORDER(z_order) |
S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
+
S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.fs.post_depth_coverage) |
S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 1e9399de193..75f1ce3e869 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -270,6 +270,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
.int64_atomics = true,
.multiview = true,
.physical_storage_buffer_address = true,
+ .post_depth_coverage = true,
.runtime_descriptor_array = true,
.shader_viewport_index_layer = true,
.stencil_export = true,
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 360591349a8..fea0d1c8df1 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -283,6 +283,7 @@ struct radv_shader_variant_info {
uint32_t float16_shaded_mask;
bool can_discard;
bool early_fragment_test;
+ bool post_depth_coverage;
} fs;
struct {
unsigned block_size[3];
--
2.22.0
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[Mesa-dev] [PATCH 2/2] radv/gfx10: fallback to the legacy path if tess and extreme geometry
This is unsupported and hangs.
This fixes GPU hangs with
dEQP-VK.tessellation.geometry_interaction.limits.output_required_*.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 12
src/amd/vulkan/radv_shader.c | 2 +-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index d1eede172dc..a22e605ca1c 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2306,6 +2306,18 @@ radv_fill_shader_keys(struct radv_device *device,
} else {
keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
}
+
+ if (nir[MESA_SHADER_TESS_CTRL] &&
+ nir[MESA_SHADER_GEOMETRY] &&
+ nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
+ nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
+ /* Fallback to the legacy path if tessellation is
+* enabled with extreme geometry because
+* EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
+* might hang.
+*/
+ keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg =
false;
+ }
}
for(int i = 0; i < MESA_SHADER_STAGES; ++i)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 1e9399de193..6bafcb2f869 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -796,7 +796,7 @@ static void radv_postprocess_config(const struct
radv_physical_device *pdevice,
break;
}
- if (pdevice->rad_info.chip_class >= GFX10 &&
+ if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL ||
stage == MESA_SHADER_GEOMETRY)) {
unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
gl_shader_stage es_stage = stage;
--
2.22.0
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[Mesa-dev] [PATCH 1/2] radv/gfx10: always build the GS copy shader but uses it on-demand
It should be possible to build it on-demand too but it requires
more work. On GFX10, the GS copy shader is required when tess
is enabled with extreme geometry.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 8
src/amd/vulkan/radv_pipeline.c | 21 ++---
src/amd/vulkan/radv_private.h| 2 ++
3 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 6a0db2b67e9..a6d4e0d0e21 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -929,7 +929,7 @@ radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
if (mask & RADV_PREFETCH_GS) {
radv_emit_shader_prefetch(cmd_buffer,
pipeline->shaders[MESA_SHADER_GEOMETRY]);
- if (pipeline->gs_copy_shader)
+ if (radv_pipeline_has_gs_copy_shader(pipeline))
radv_emit_shader_prefetch(cmd_buffer,
pipeline->gs_copy_shader);
}
@@ -1124,7 +1124,7 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer)
pipeline->shaders[i]->bo);
}
- if (radv_pipeline_has_gs(pipeline) && pipeline->gs_copy_shader)
+ if (radv_pipeline_has_gs_copy_shader(pipeline))
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
pipeline->gs_copy_shader->bo);
@@ -2362,7 +2362,7 @@ radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer, uint64_t va)
base_reg + loc->sgpr_idx * 4, va,
false);
}
- if (pipeline->gs_copy_shader) {
+ if (radv_pipeline_has_gs_copy_shader(pipeline)) {
loc =
>gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
if (loc->sgpr_idx != -1) {
base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
@@ -4071,7 +4071,7 @@ static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer, unsigned in
radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
index);
}
- if (pipeline->gs_copy_shader) {
+ if (radv_pipeline_has_gs_copy_shader(pipeline)) {
struct radv_userdata_info *loc =
>gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
if (loc->sgpr_idx != -1) {
uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 31495ec078d..d1eede172dc 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -120,6 +120,22 @@ bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline)
return variant->info.is_ngg;
}
+bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
+{
+ if (!radv_pipeline_has_gs(pipeline))
+ return false;
+
+ /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
+* On GFX10, it might be required in rare cases if it's not possible to
+* enable NGG.
+*/
+ if (radv_pipeline_has_ngg(pipeline))
+ return false;
+
+ assert(pipeline->gs_copy_shader);
+ return true;
+}
+
static void
radv_pipeline_destroy(struct radv_device *device,
struct radv_pipeline *pipeline,
@@ -2395,7 +2411,6 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {0};
unsigned char hash[20], gs_copy_hash[20];
- bool use_ngg = device->physical_device->rad_info.chip_class >= GFX10;
radv_start_feedback(pipeline_feedback);
@@ -2416,7 +2431,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
gs_copy_hash[0] ^= 1;
bool found_in_application_cache = true;
- if (modules[MESA_SHADER_GEOMETRY] && !use_ngg) {
+ if (modules[MESA_SHADER_GEOMETRY]) {
struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
radv_create_shader_variants_from_pipeline_cache(device, cache,
gs_copy_hash, variants,
_in_application_cache);
@@ -2567,7 +2582,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
}
}
- if(modules[MESA_SHADER_GEOMETRY] && !use_ngg) {
+ if(modules[MESA_SHADER_GEOMETRY]) {
struct radv_shader_binary *gs_copy_binary = NULL;
if (!pipeline->gs_copy_shader) {
pipeline->gs_copy_shader = radv_create_gs_copy_shader(
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 08c2abef7ab..b9ac97249d3 100644
--- a/src/amd/vulkan/radv_private.h
+++
[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization
https://bugs.freedesktop.org/show_bug.cgi?id=41 --- Comment #6 from Steven Newbury --- GPU is a POLARIS10 (RX470) -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111150] [BRW] WRC 5 asserts with gallium nine and iris.
https://bugs.freedesktop.org/show_bug.cgi?id=50 Illia Iorin changed: What|Removed |Added CC||illia.io...@gmail.com, ||nanleych...@gmail.com -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111150] [BRW] WRC 5 asserts with gallium nine and iris.
https://bugs.freedesktop.org/show_bug.cgi?id=50 Bug ID: 50 Summary: [BRW] WRC 5 asserts with gallium nine and iris. Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Gallium/StateTracker/galliumnine Assignee: mesa-dev@lists.freedesktop.org Reporter: illia.io...@gmail.com QA Contact: mesa-dev@lists.freedesktop.org When I launch WRC 5 with master mesa(b393b2ce955) I get the message: ../src/gallium/drivers/iris/iris_resource.c:855: iris_resource_get_handle: Assertion `aux_state == ISL_AUX_STATE_RESOLVED || aux_state == ISL_AUX_STATE_PASS_THROUGH' failed. Bisect leads to this commit: __ commit e81392868e6827360762fff38baf2c10c1f3b7f0 Author: Nanley Chery Date: Wed May 1 14:57:23 2019 -0700iris/resource: Drop redundant checks for aux support Drop some checks that are already done by ISL. Reviewed-by: Rafael Antognolli __ This commit dropped the following condition: /* Gen9+ only supports CCS for Y-tiled buffers. */ if (surf->tiling != ISL_TILING_Y0) return false; It prohibited ccs when spec allows it so the condition was indeed correctly removed. Next I investigated why aux_state is ISL_AUX_STATE_CLEAR in iris_resource_get_handle. It is because NineSurface9_ctor calls nine_context_clear_render_target and it sets aux_state to ISL_AUX_STATE_CLEAR and again it looks logical for me. I don’t know what should be done. Also removing optimization doesn’t fix the game it just leads to a black screen and game being stuck. Discussion about this bug can be found there: https://github.com/iXit/wine-nine-standalone/issues/46 -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization
https://bugs.freedesktop.org/show_bug.cgi?id=41 --- Comment #5 from Jason Ekstrand --- Could you also please say what GPU you're seeing the corruption on? It might matter and it's certainly needed in order for the RenderDoc taxes to be off any use. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization
https://bugs.freedesktop.org/show_bug.cgi?id=41 --- Comment #4 from Steven Newbury --- Created attachment 144802 --> https://bugs.freedesktop.org/attachment.cgi?id=144802=edit RenderDoc capture before commit -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization
https://bugs.freedesktop.org/show_bug.cgi?id=41 --- Comment #3 from Steven Newbury --- Created attachment 144801 --> https://bugs.freedesktop.org/attachment.cgi?id=144801=edit RenderDoc capture after commit -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111146] Problems with windows full version
https://bugs.freedesktop.org/show_bug.cgi?id=46 Timothy Arceri changed: What|Removed |Added Resolution|--- |DUPLICATE Status|NEW |RESOLVED --- Comment #1 from Timothy Arceri --- *** This bug has been marked as a duplicate of bug 110703 *** -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110703] libGL conflicts with Exagear's X11
https://bugs.freedesktop.org/show_bug.cgi?id=110703 Timothy Arceri changed: What|Removed |Added CC||neonp...@ya.ru --- Comment #9 from Timothy Arceri --- *** Bug 46 has been marked as a duplicate of this bug. *** -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111147] Processing of SPIR-V shader leads to display/machine freeze
https://bugs.freedesktop.org/show_bug.cgi?id=47 --- Comment #1 from Alastair Donaldson --- Running the attached test using Amber (https://github.com/google/amber): amber -d unreachable-barrier-in-loops.amber should lead to the test passing. Instead, I find that my system immediately locks up. I believe it is a whole system freeze, rather than just a display freeze. Build: Mesa 19.2.0-devel (git-a110a8090d) (Debug) Device: Radeon RX Vega -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111147] Processing of SPIR-V shader leads to display/machine freeze
https://bugs.freedesktop.org/show_bug.cgi?id=47 Bug ID: 47 Summary: Processing of SPIR-V shader leads to display/machine freeze Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/Vulkan/radeon Assignee: mesa-dev@lists.freedesktop.org Reporter: a...@google.com QA Contact: mesa-dev@lists.freedesktop.org Created attachment 144796 --> https://bugs.freedesktop.org/attachment.cgi?id=144796=edit A -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111146] Problems with windows full version
https://bugs.freedesktop.org/show_bug.cgi?id=46 Bug ID: 46 Summary: Problems with windows full version Product: Mesa Version: unspecified Hardware: Other OS: Windows (All) Status: NEW Severity: normal Priority: medium Component: GLX Assignee: mesa-dev@lists.freedesktop.org Reporter: neonp...@ya.ru QA Contact: mesa-dev@lists.freedesktop.org Sorry that in the past the ticket gave so little information. So, what is the essence of the bug, I downloaded exagear and ran into the same problem as this guy "https://bugs.freedeskt…show_bug.cgi?id=110703;. You did not answer him and rewrite the court that he wrote, I will not. Sorry for the second ticket in a row. :-) -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111145] Problems with windows
https://bugs.freedesktop.org/show_bug.cgi?id=45 Timothy Arceri changed: What|Removed |Added Resolution|--- |NOTABUG Status|NEW |RESOLVED -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111145] Problems with windows
https://bugs.freedesktop.org/show_bug.cgi?id=45 Bug ID: 45 Summary: Problems with windows Product: Mesa Version: unspecified Hardware: Other OS: Windows (All) Status: NEW Severity: normal Priority: medium Component: GLX Assignee: mesa-dev@lists.freedesktop.org Reporter: neonp...@ya.ru QA Contact: mesa-dev@lists.freedesktop.org Hi developers, I have some problems with windows in mesa. could you help me? -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] android: radv/gfx10: generate gfx10_format_table.h
Acked-by: Samuel Pitoiset
On 7/10/19 9:13 AM, Mauro Rossi wrote:
This patch adds gfx10_format_table.h in Makefile.sources
and the rules for Android to fix following building errors:
In file included from external/mesa/src/amd/vulkan/radv_debug.c:35:
In file included from external/mesa/src/amd/vulkan/radv_debug.h:27:
external/mesa/src/amd/vulkan/radv_private.h:95:10:
fatal error: 'gfx10_format_table.h' file not found
^~
1 error generated.
In file included from external/mesa/src/amd/vulkan/radv_android.c:31:
external/mesa/src/amd/vulkan/radv_private.h:95:10:
fatal error: 'gfx10_format_table.h' file not found
^~
1 error generated.
Fixes: 3dc5ec5d16 ("radv/gfx10: generate gfx10_format_table.h")
Signed-off-by: Mauro Rossi
---
src/amd/vulkan/Android.mk | 15 +++
src/amd/vulkan/Makefile.sources | 3 ++-
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/Android.mk b/src/amd/vulkan/Android.mk
index 0725feacb5..23cebb1ec8 100644
--- a/src/amd/vulkan/Android.mk
+++ b/src/amd/vulkan/Android.mk
@@ -83,6 +83,7 @@ LOCAL_GENERATED_SOURCES += $(intermediates)/radv_entrypoints.h
LOCAL_GENERATED_SOURCES += $(intermediates)/radv_extensions.c
LOCAL_GENERATED_SOURCES += $(intermediates)/radv_extensions.h
LOCAL_GENERATED_SOURCES += $(intermediates)/vk_format_table.c
+LOCAL_GENERATED_SOURCES += $(intermediates)/gfx10_format_table.h
RADV_ENTRYPOINTS_SCRIPT := $(MESA_TOP)/src/amd/vulkan/radv_entrypoints_gen.py
RADV_EXTENSIONS_SCRIPT := $(MESA_TOP)/src/amd/vulkan/radv_extensions.py
@@ -117,6 +118,20 @@ $(intermediates)/vk_format_table.c:
$(VK_FORMAT_TABLE_SCRIPT) \
@mkdir -p $(dir $@)
$(MESA_PYTHON2) $(VK_FORMAT_TABLE_SCRIPT) $(vk_format_layout_csv) > $@
+RADV_GEN10_FORMAT_TABLE_INPUTS := \
+ $(MESA_TOP)/src/amd/vulkan/vk_format_layout.csv \
+ $(MESA_TOP)/src/amd/registers/gfx10-rsrc.json
+
+RADV_GEN10_FORMAT_TABLE_DEP := \
+ $(MESA_TOP)/src/amd/registers/regdb.py
+
+RADV_GEN10_FORMAT_TABLE := $(LOCAL_PATH)/gfx10_format_table.py
+
+$(intermediates)/gfx10_format_table.h: $(RADV_GEN10_FORMAT_TABLE)
$(RADV_GEN10_FORMAT_TABLE_INPUTS) $(RADV_GEN10_FORMAT_TABLE_DEP)
+ @mkdir -p $(dir $@)
+ @echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))"
+ $(hide) $(MESA_PYTHON2) $(RADV_GEN10_FORMAT_TABLE)
$(RADV_GEN10_FORMAT_TABLE_INPUTS) > $@ || ($(RM) $@; false)
+
LOCAL_SHARED_LIBRARIES += $(RADV_SHARED_LIBRARIES)
LOCAL_EXPORT_C_INCLUDE_DIRS := \
diff --git a/src/amd/vulkan/Makefile.sources b/src/amd/vulkan/Makefile.sources
index df90c1150a..312cd0b1e9 100644
--- a/src/amd/vulkan/Makefile.sources
+++ b/src/amd/vulkan/Makefile.sources
@@ -91,5 +91,6 @@ VULKAN_GENERATED_FILES := \
radv_entrypoints.h \
radv_extensions.c \
radv_extensions.h \
- vk_format_table.c
+ vk_format_table.c \
+ gfx10_format_table.h
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Re: [Mesa-dev] [PATCH] android: radv/gfx10: generate gfx10_format_table.h
Hi,
kind reminder for Review or Ack,
apart from Android makefile changes Makefile.sources was modified
to add gfx10_format_table.h generated file.
Mauro
On Wed, Jul 10, 2019 at 9:13 AM Mauro Rossi wrote:
> This patch adds gfx10_format_table.h in Makefile.sources
> and the rules for Android to fix following building errors:
>
> In file included from external/mesa/src/amd/vulkan/radv_debug.c:35:
> In file included from external/mesa/src/amd/vulkan/radv_debug.h:27:
> external/mesa/src/amd/vulkan/radv_private.h:95:10:
> fatal error: 'gfx10_format_table.h' file not found
> ^~
> 1 error generated.
>
> In file included from external/mesa/src/amd/vulkan/radv_android.c:31:
> external/mesa/src/amd/vulkan/radv_private.h:95:10:
> fatal error: 'gfx10_format_table.h' file not found
> ^~
> 1 error generated.
>
> Fixes: 3dc5ec5d16 ("radv/gfx10: generate gfx10_format_table.h")
> Signed-off-by: Mauro Rossi
> ---
> src/amd/vulkan/Android.mk | 15 +++
> src/amd/vulkan/Makefile.sources | 3 ++-
> 2 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/Android.mk b/src/amd/vulkan/Android.mk
> index 0725feacb5..23cebb1ec8 100644
> --- a/src/amd/vulkan/Android.mk
> +++ b/src/amd/vulkan/Android.mk
> @@ -83,6 +83,7 @@ LOCAL_GENERATED_SOURCES +=
> $(intermediates)/radv_entrypoints.h
> LOCAL_GENERATED_SOURCES += $(intermediates)/radv_extensions.c
> LOCAL_GENERATED_SOURCES += $(intermediates)/radv_extensions.h
> LOCAL_GENERATED_SOURCES += $(intermediates)/vk_format_table.c
> +LOCAL_GENERATED_SOURCES += $(intermediates)/gfx10_format_table.h
>
> RADV_ENTRYPOINTS_SCRIPT :=
> $(MESA_TOP)/src/amd/vulkan/radv_entrypoints_gen.py
> RADV_EXTENSIONS_SCRIPT := $(MESA_TOP)/src/amd/vulkan/radv_extensions.py
> @@ -117,6 +118,20 @@ $(intermediates)/vk_format_table.c:
> $(VK_FORMAT_TABLE_SCRIPT) \
> @mkdir -p $(dir $@)
> $(MESA_PYTHON2) $(VK_FORMAT_TABLE_SCRIPT) $(vk_format_layout_csv)
> > $@
>
> +RADV_GEN10_FORMAT_TABLE_INPUTS := \
> + $(MESA_TOP)/src/amd/vulkan/vk_format_layout.csv \
> + $(MESA_TOP)/src/amd/registers/gfx10-rsrc.json
> +
> +RADV_GEN10_FORMAT_TABLE_DEP := \
> + $(MESA_TOP)/src/amd/registers/regdb.py
> +
> +RADV_GEN10_FORMAT_TABLE := $(LOCAL_PATH)/gfx10_format_table.py
> +
> +$(intermediates)/gfx10_format_table.h: $(RADV_GEN10_FORMAT_TABLE)
> $(RADV_GEN10_FORMAT_TABLE_INPUTS) $(RADV_GEN10_FORMAT_TABLE_DEP)
> + @mkdir -p $(dir $@)
> + @echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))"
> + $(hide) $(MESA_PYTHON2) $(RADV_GEN10_FORMAT_TABLE)
> $(RADV_GEN10_FORMAT_TABLE_INPUTS) > $@ || ($(RM) $@; false)
> +
> LOCAL_SHARED_LIBRARIES += $(RADV_SHARED_LIBRARIES)
>
> LOCAL_EXPORT_C_INCLUDE_DIRS := \
> diff --git a/src/amd/vulkan/Makefile.sources
> b/src/amd/vulkan/Makefile.sources
> index df90c1150a..312cd0b1e9 100644
> --- a/src/amd/vulkan/Makefile.sources
> +++ b/src/amd/vulkan/Makefile.sources
> @@ -91,5 +91,6 @@ VULKAN_GENERATED_FILES := \
> radv_entrypoints.h \
> radv_extensions.c \
> radv_extensions.h \
> - vk_format_table.c
> + vk_format_table.c \
> + gfx10_format_table.h
>
> --
> 2.20.1
>
>
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[Mesa-dev] [PATCH 2/2] radv: update LATE_ALLOC_VS.LIMIT
Mirror RadeonSI.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/si_cmd_buffer.c | 60 --
1 file changed, 42 insertions(+), 18 deletions(-)
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index a832dbd89eb..e996fa250a9 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -264,9 +264,6 @@ si_emit_graphics(struct radv_physical_device
*physical_device,
/* Logical CUs 16 - 31 */
radeon_set_sh_reg(cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
S_00B404_CU_EN(0x));
- radeon_set_sh_reg(cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
- S_00B204_CU_EN(0x) |
-
S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
radeon_set_sh_reg(cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
S_00B104_CU_EN(0x));
radeon_set_sh_reg(cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
@@ -291,28 +288,55 @@ si_emit_graphics(struct radv_physical_device
*physical_device,
S_028A44_ES_VERTS_PER_SUBGRP(64)
|
S_028A44_GS_PRIMS_PER_SUBGRP(4));
}
- radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
- S_00B21C_CU_EN(0x) |
S_00B21C_WAVE_LIMIT(0x3F));
- if (physical_device->rad_info.num_good_cu_per_sh <= 4) {
+ /* Compute LATE_ALLOC_VS.LIMIT. */
+ unsigned num_cu_per_sh =
physical_device->rad_info.num_good_cu_per_sh;
+ unsigned late_alloc_limit; /* The limit is per SH. */
+
+ if (physical_device->rad_info.family == CHIP_KABINI) {
+ late_alloc_limit = 0; /* Potential hang on Kabini. */
+ } else if (num_cu_per_sh <= 4) {
/* Too few available compute units per SH. Disallowing
-* VS to run on CU0 could hurt us more than late VS
+* VS to run on one CU could hurt us more than late VS
* allocation would help.
*
-* LATE_ALLOC_VS = 2 is the highest safe number.
+* 2 is the highest safe number that allows us to keep
+* all CUs enabled.
*/
- radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
- S_00B118_CU_EN(0x) |
S_00B118_WAVE_LIMIT(0x3F) );
- radeon_set_sh_reg(cs,
R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
+ late_alloc_limit = 2;
} else {
- /* Set LATE_ALLOC_VS == 31. It should be less than
-* the number of scratch waves. Limitations:
-* - VS can't execute on CU0.
-* - If HS writes outputs to LDS, LS can't execute on
CU0.
+ /* This is a good initial value, allowing 1 late_alloc
+* wave per SIMD on num_cu - 2.
*/
- radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
- S_00B118_CU_EN(0xfffe) |
S_00B118_WAVE_LIMIT(0x3F));
- radeon_set_sh_reg(cs,
R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
+ late_alloc_limit = (num_cu_per_sh - 2) * 4;
+ }
+
+ unsigned cu_mask_vs = 0x;
+ unsigned cu_mask_gs = 0x;
+
+ if (late_alloc_limit > 2) {
+ if (physical_device->rad_info.chip_class >= GFX10) {
+ /* CU2 & CU3 disabled because of the dual CU
design */
+ cu_mask_vs = 0xfff3;
+ cu_mask_gs = 0xfff3; /* NGG only */
+ } else {
+ cu_mask_vs = 0xfffe; /* 1 CU disabled */
+ }
+ }
+
+ radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
+ S_00B118_CU_EN(cu_mask_vs) |
+ S_00B118_WAVE_LIMIT(0x3F));
+ radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
+ S_00B11C_LIMIT(late_alloc_limit));
+
+ radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
+ S_00B21C_CU_EN(cu_mask_gs) |
S_00B21C_WAVE_LIMIT(0x3F));
+
+ if (physical_device->rad_info.chip_class >= GFX10) {
+ radeon_set_sh_reg(cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
+
Re: [Mesa-dev] [PATCH] pipe-loader: use radeonsi for MM if amdgpu dri is used
Sorry about that, I've only used git email maybe three times in my life :)
On 2019-07-15 10:09 a.m., Michel Dänzer wrote:
> On 2019-07-15 3:58 p.m., Jeremy Newton wrote:
>> Thanks Marek and Michel, see the updated patch below:
> FYI, this kind of commentary should be after the --- line, or it will be
> included as part of the Git commit log by tools like "git am".
>
>
>> The amdgpu dri is used for the closed source AMD driver. Since this driver
>> does not implement multimedia, we fall back to radeonsi in mesa to do
>> multimedia. This corrects the Gallium driver name for when it is set to
>> amdgpu.
>>
>> This will allow dropping the amdgpu-pro specific GBM implementation in
>> favour of Mesa's libgbm.
>>
>> Signed-off-by: Jeremy Newton
>> Signed-off-by: Marek Olšák
>> Reviewed-by: Michel Dänzer
>> ---
>> src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c | 5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
>> b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
>> index 960d63b2c31..6e889539c92 100644
>> --- a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
>> +++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
>> @@ -194,6 +194,11 @@ pipe_loader_drm_probe_fd_nodup(struct
>> pipe_loader_device **dev, int fd)
>> if (!ddev->base.driver_name)
>> goto fail;
>>
>> + if (strcmp(ddev->base.driver_name, "amdgpu") == 0) {
>> + FREE(ddev->base.driver_name);
>> + ddev->base.driver_name = strdup("radeonsi");
>> + }
>> +
>> struct util_dl_library **plib = NULL;
>> #ifndef GALLIUM_STATIC_TARGETS
>> plib = >lib;
>>
>
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[Mesa-dev] [PATCH 1/2] radv/gfx10: support pixel shaders without exports
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index fdb0ed29ea4..31495ec078d 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4283,9 +4283,15 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
*stalls without this setting.
*
* Don't add this to CB_SHADER_MASK.
+*
+* GFX10 supports pixel shaders without exports by setting both the
+* color and Z formats to SPI_SHADER_ZERO. The hw will skip export
+* instructions if any are present.
*/
struct radv_shader_variant *ps =
pipeline->shaders[MESA_SHADER_FRAGMENT];
- if (!blend.spi_shader_col_format) {
+ if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
+ps->info.fs.can_discard) &&
+ !blend.spi_shader_col_format) {
if (!ps->info.info.ps.writes_z &&
!ps->info.info.ps.writes_stencil &&
!ps->info.info.ps.writes_sample_mask)
--
2.22.0
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[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization
https://bugs.freedesktop.org/show_bug.cgi?id=41 --- Comment #2 from Steven Newbury --- Created attachment 144794 --> https://bugs.freedesktop.org/attachment.cgi?id=144794=edit Before commit 3b3081479163475f25b908008250d83c31716c34 -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization
https://bugs.freedesktop.org/show_bug.cgi?id=41 --- Comment #1 from Steven Newbury --- Created attachment 144793 --> https://bugs.freedesktop.org/attachment.cgi?id=144793=edit After commit 3b3081479163475f25b908008250d83c31716c34 -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv: fix gathering clip/cull distance masks for GS
For NGG, the driver relies on the VS outinfo struct.
This fixes
dEQP-VK.clipping.user_defined.clip_*_vert_tess_geom_*
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 76d784b3374..b890ce56f16 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2407,6 +2407,11 @@ scan_shader_output_decl(struct radv_shader_context *ctx,
ctx->shader_info->tes.outinfo.cull_dist_mask =
(1 << shader->info.cull_distance_array_size) - 1;
ctx->shader_info->tes.outinfo.cull_dist_mask
<<= shader->info.clip_distance_array_size;
}
+ if (stage == MESA_SHADER_GEOMETRY) {
+ ctx->shader_info->vs.outinfo.clip_dist_mask =
(1 << shader->info.clip_distance_array_size) - 1;
+ ctx->shader_info->vs.outinfo.cull_dist_mask =
(1 << shader->info.cull_distance_array_size) - 1;
+ ctx->shader_info->vs.outinfo.cull_dist_mask <<=
shader->info.clip_distance_array_size;
+ }
}
}
--
2.22.0
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