[Mesa-dev] [PATCH] radeon/vcn: Handle crop parameters for encoder
Set proper cropping parameter if frame cropping is enabled
Signed-off-by: Satyajit Sahu
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c
b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index aa9182f273b..0bcce867327 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -52,10 +52,17 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder
*enc, struct pipe_pic
enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
enc->enc_pic.not_referenced = pic->not_referenced;
enc->enc_pic.is_idr = (pic->picture_type ==
PIPE_H264_ENC_PICTURE_TYPE_IDR);
- enc->enc_pic.crop_left = 0;
- enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width)
/ 2;
- enc->enc_pic.crop_top = 0;
- enc->enc_pic.crop_bottom = (align(enc->base.height, 16) -
enc->base.height) / 2;
+ if (pic->pic_ctrl.enc_frame_cropping_flag) {
+ enc->enc_pic.crop_left = pic->pic_ctrl.enc_frame_crop_left_offset;
+ enc->enc_pic.crop_right = pic->pic_ctrl.enc_frame_crop_right_offset;
+ enc->enc_pic.crop_top = pic->pic_ctrl.enc_frame_crop_top_offset;
+ enc->enc_pic.crop_bottom =
pic->pic_ctrl.enc_frame_crop_bottom_offset;
+ } else {
+ enc->enc_pic.crop_left = 0;
+ enc->enc_pic.crop_right = (align(enc->base.width, 16) -
enc->base.width) / 2;
+ enc->enc_pic.crop_top = 0;
+ enc->enc_pic.crop_bottom = (align(enc->base.height, 16) -
enc->base.height) / 2;
+ }
enc->enc_pic.rc_layer_init.target_bit_rate =
pic->rate_ctrl.target_bitrate;
enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rate_ctrl.peak_bitrate;
enc->enc_pic.rc_layer_init.frame_rate_num =
pic->rate_ctrl.frame_rate_num;
--
2.17.1
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[Mesa-dev] [PATCH] radeonsi: Add support for midstream bitrate change in encoder
Added support for bitrate change in between encoding.
Signed-off-by: Satyajit Sahu
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index 84d3c1e2fa4..7d7a2fa4eb3 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -268,7 +268,8 @@ static void rvce_begin_frame(struct pipe_video_codec
*encoder,
enc->pic.rate_ctrl.rate_ctrl_method !=
pic->rate_ctrl.rate_ctrl_method ||
enc->pic.quant_i_frames != pic->quant_i_frames ||
enc->pic.quant_p_frames != pic->quant_p_frames ||
- enc->pic.quant_b_frames != pic->quant_b_frames;
+ enc->pic.quant_b_frames != pic->quant_b_frames ||
+ enc->pic.rate_ctrl.target_bitrate !=
pic->rate_ctrl.target_bitrate;
enc->pic = *pic;
si_get_pic_param(enc, pic);
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c
b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index aa9182f273b..c4fb9a7bd92 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -247,6 +247,17 @@ static void radeon_enc_begin_frame(struct pipe_video_codec
*encoder,
{
struct radeon_encoder *enc = (struct radeon_encoder*)encoder;
struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
+ bool need_rate_control = false;
+
+ if (u_reduce_video_profile(enc->base.profile) ==
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
+ struct pipe_h264_enc_picture_desc *pic = (struct
pipe_h264_enc_picture_desc *)picture;
+ need_rate_control =
+ enc->enc_pic.rc_layer_init.target_bit_rate !=
pic->rate_ctrl.target_bitrate;
+ } else if (u_reduce_video_profile(picture->profile) ==
PIPE_VIDEO_FORMAT_HEVC) {
+struct pipe_h265_enc_picture_desc *pic = (struct
pipe_h265_enc_picture_desc *)picture;
+ need_rate_control =
+ enc->enc_pic.rc_layer_init.target_bit_rate !=
pic->rc.target_bitrate;
+ }
radeon_vcn_enc_get_param(enc, picture);
@@ -266,6 +277,10 @@ static void radeon_enc_begin_frame(struct pipe_video_codec
*encoder,
flush(enc);
si_vid_destroy_buffer();
}
+ if (need_rate_control) {
+ enc->begin(enc, picture);
+ flush(enc);
+ }
}
static void radeon_enc_encode_bitstream(struct pipe_video_codec *encoder,
--
2.17.1
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[Mesa-dev] [PATCH v2] radeonsi: Adding tiled to linear conversion functionality
Add tiled to linear conversion and expose outside mesa. This function converts
tiled image to linear and vice versa.
One of the use-case is, a chromiumos test case where the captured fb is
compared against a reference image. As the fb is tiled mode it needs to
be converted before comparision.
Also exposing create, compute and destroy surface functions outside. These
functions are also used when accessing addrlib outside of mesa.
Signed-off-by: Satyajit Sahu <satyajit.s...@amd.com>
---
src/amd/Makefile.common.am | 4 ++
src/amd/common/ac_gpu_info.c| 2 +
src/amd/common/ac_surface.c | 102
src/amd/common/ac_surface.h | 9
src/gallium/targets/dri/Makefile.am | 1 +
src/gallium/targets/dri/dri.sym | 5 ++
6 files changed, 123 insertions(+)
diff --git a/src/amd/Makefile.common.am b/src/amd/Makefile.common.am
index d62e9d4..651b3c7 100644
--- a/src/amd/Makefile.common.am
+++ b/src/amd/Makefile.common.am
@@ -53,6 +53,10 @@ common_libamd_common_la_CXXFLAGS = \
$(LLVM_CXXFLAGS)
noinst_LTLIBRARIES += $(COMMON_LIBS)
+include_HEADERS = $(top_srcdir)/src/amd/common/ac_surface.h \
+ $(top_srcdir)/src/amd/common/ac_gpu_info.h \
+ $(top_srcdir)/src/amd/common/amd_family.h
+
common_libamd_common_la_SOURCES = \
$(AMD_COMMON_FILES) \
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 6e34a07..bb4f03f 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -28,6 +28,7 @@
#include "gfx9d.h"
#include "util/u_math.h"
+#include "util/macros.h"
#include
@@ -92,6 +93,7 @@ static bool has_syncobj(int fd)
return value ? true : false;
}
+PUBLIC
bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
struct radeon_info *info,
struct amdgpu_gpu_info *amdinfo)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index f7600a3..67bf28a 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -155,6 +155,7 @@ static ADDR_E_RETURNCODE ADDR_API freeSysMem(const
ADDR_FREESYSMEM_INPUT * pInpu
return ADDR_OK;
}
+PUBLIC
ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
const struct amdgpu_gpu_info *amdinfo,
uint64_t *max_alignment)
@@ -219,6 +220,15 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info
*info,
return addrCreateOutput.hLib;
}
+PUBLIC
+int amdgpu_addr_destroy(ADDR_HANDLE handle) {
+ ADDR_E_RETURNCODE ret = AddrDestroy(handle);
+ if(ret = ADDR_OK)
+ return 0;
+ else
+ return -((int)ret);
+}
+
static int surf_config_sanity(const struct ac_surf_config *config)
{
/* all dimension must be at least 1 ! */
@@ -1246,6 +1256,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
return 0;
}
+PUBLIC
int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
const struct ac_surf_config *config,
enum radeon_surf_mode mode,
@@ -1262,3 +1273,94 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct
radeon_info *info,
else
return gfx6_compute_surface(addrlib, info, config, mode, surf);
}
+
+PUBLIC
+int ac_read_write_tiled_data(ADDR_HANDLE addrlib,
+ struct ac_surf_config * config,
+ struct radeon_surf * surf,
+ void * addr, uint8_t * linear_ptr,
+ bool write_to_tiled_buf) {
+ ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT in_param = { 0 };
+ ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT out_param;
+ const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT *in_param_ptr =
_param;
+ ADDR_TILEINFO tile_info = {0};
+ ADDR_E_RETURNCODE ret = ADDR_OK;
+ uint8_t *tiled_ptr;
+
+ if (!addr || !linear_ptr)
+ return -EINVAL;
+ out_param.size = sizeof(ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT);
+ in_param.size = sizeof(ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT);
+ tile_info.banks = surf->u.legacy.num_banks;
+ tile_info.bankWidth = surf->u.legacy.bankw;
+ tile_info.bankHeight = surf->u.legacy.bankh;
+ tile_info.macroAspectRatio = surf->u.legacy.mtilea;
+ tile_info.tileSplitBytes = surf->u.legacy.tile_split;
+ tile_info.pipeConfig = surf->u.legacy.pipe_config;
+ /* bpp in bytes */
+ in_param.bpp = surf->bpe << 3;
+ in_param.pitch = surf->u.legacy.level[0].nblk_x;
+ in_param.height = surf->u.legacy.level[0].nblk_y;
+ in_param.numSlices = config->info.depth;
+ in_param.numSamples = config->info.samples;
+switch (surf->u.legacy.level[0].mode) {
+ case RADEON_SURF_MODE_LINE
[Mesa-dev] [PATCH] Adding tiled to linear conversion functionality
Add tiled to linear conversion and expose outside mesa.
Also exposing the create compute and destroy surface fucntions outside.
Change-Id: Ie464ba0eac5d80048797bef1f6ad730c22947601
Signed-off-by: Satyajit Sahu <satyajit.s...@amd.com>
---
src/amd/Makefile.common.am | 4 ++
src/amd/common/ac_gpu_info.c| 2 +
src/amd/common/ac_surface.c | 102
src/amd/common/ac_surface.h | 9
src/gallium/targets/dri/dri.sym | 5 ++
5 files changed, 122 insertions(+)
diff --git a/src/amd/Makefile.common.am b/src/amd/Makefile.common.am
index d62e9d41cf..651b3c7be0 100644
--- a/src/amd/Makefile.common.am
+++ b/src/amd/Makefile.common.am
@@ -53,6 +53,10 @@ common_libamd_common_la_CXXFLAGS = \
$(LLVM_CXXFLAGS)
noinst_LTLIBRARIES += $(COMMON_LIBS)
+include_HEADERS = $(top_srcdir)/src/amd/common/ac_surface.h \
+ $(top_srcdir)/src/amd/common/ac_gpu_info.h \
+ $(top_srcdir)/src/amd/common/amd_family.h
+
common_libamd_common_la_SOURCES = \
$(AMD_COMMON_FILES) \
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 82ff18d436..89dc7fd683 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -28,6 +28,7 @@
#include "gfx9d.h"
#include "util/u_math.h"
+#include "util/macros.h"
#include
@@ -92,6 +93,7 @@ static bool has_syncobj(int fd)
return value ? true : false;
}
+PUBLIC
bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
struct radeon_info *info,
struct amdgpu_gpu_info *amdinfo)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index f956c14a10..179043f6ff 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -150,6 +150,7 @@ static ADDR_E_RETURNCODE ADDR_API freeSysMem(const
ADDR_FREESYSMEM_INPUT * pInpu
return ADDR_OK;
}
+PUBLIC
ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
const struct amdgpu_gpu_info *amdinfo,
uint64_t *max_alignment)
@@ -214,6 +215,15 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info
*info,
return addrCreateOutput.hLib;
}
+PUBLIC
+int amdgpu_addr_destroy(ADDR_HANDLE handle) {
+ ADDR_E_RETURNCODE ret = AddrDestroy(handle);
+ if(ret = ADDR_OK)
+ return 0;
+ else
+ return -((int)ret);
+}
+
static int surf_config_sanity(const struct ac_surf_config *config)
{
/* all dimension must be at least 1 ! */
@@ -1223,6 +1233,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
return 0;
}
+PUBLIC
int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
const struct ac_surf_config *config,
enum radeon_surf_mode mode,
@@ -1239,3 +1250,94 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct
radeon_info *info,
else
return gfx6_compute_surface(addrlib, info, config, mode, surf);
}
+
+PUBLIC
+int ac_read_write_tiled_data(ADDR_HANDLE addrlib,
+ struct ac_surf_config * config,
+ struct radeon_surf * surf,
+ void * addr, uint8_t * linear_ptr,
+ bool write_to_tiled_buf) {
+ ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT in_param = { 0 };
+ ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT out_param;
+ const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT *in_param_ptr =
_param;
+ ADDR_TILEINFO tile_info = {0};
+ ADDR_E_RETURNCODE ret = ADDR_OK;
+ uint8_t *tiled_ptr;
+
+ if (!addr || !linear_ptr)
+ return -EINVAL;
+ out_param.size = sizeof(ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT);
+ in_param.size = sizeof(ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT);
+ tile_info.banks = surf->u.legacy.num_banks;
+ tile_info.bankWidth = surf->u.legacy.bankw;
+ tile_info.bankHeight = surf->u.legacy.bankh;
+ tile_info.macroAspectRatio = surf->u.legacy.mtilea;
+ tile_info.tileSplitBytes = surf->u.legacy.tile_split;
+ tile_info.pipeConfig = surf->u.legacy.pipe_config;
+ /* bpp in bytes */
+ in_param.bpp = surf->bpe << 3;
+ in_param.pitch = surf->u.legacy.level[0].nblk_x;
+ in_param.height = surf->u.legacy.level[0].nblk_y;
+ in_param.numSlices = config->info.depth;
+ in_param.numSamples = config->info.samples;
+switch (surf->u.legacy.level[0].mode) {
+ case RADEON_SURF_MODE_LINEAR_ALIGNED:
+ in_param.tileMode = ADDR_TM_LINEAR_ALIGNED;
+ break;
+ case RADEON_SURF_MODE_1D:
+ in_param.tileMode = ADDR_TM_1D_TILED_THIN1;
+ break;
+ case RADEON_SU
