[Mesa-dev] [PATCH] radeon/vcn: adding engine type for new fw interface

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc.h | 2 ++
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 1 +
 src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c | 4 ++--
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.h 
b/src/gallium/drivers/radeon/radeon_vcn_enc.h
index fb800c3c6a3..bcff114ff18 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.h
@@ -42,6 +42,8 @@
 #define RENCODE_IF_MINOR_VERSION_MASK  0x
 #define RENCODE_IF_MINOR_VERSION_SHIFT 0
 
+#define RENCODE_ENGINE_TYPE_ENCODE 1
+
 #define RENCODE_ENCODE_STANDARD_HEVC   0
 #define RENCODE_ENCODE_STANDARD_H264   1
 
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 9a47affd14b..a437add48ee 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -69,6 +69,7 @@ static void radeon_enc_session_info(struct radeon_encoder 
*enc)
RADEON_ENC_BEGIN(enc->cmd.session_info);
RADEON_ENC_CS(enc->enc_pic.session_info.interface_version);
RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
+   RADEON_ENC_CS(RENCODE_ENGINE_TYPE_ENCODE);
RADEON_ENC_END();
 }
 
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
index dfad95a4dd9..d2c6378a055 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
@@ -35,8 +35,8 @@
 #include "radeon_video.h"
 #include "radeon_vcn_enc.h"
 
-#define RENCODE_FW_INTERFACE_MAJOR_VERSION 0
-#define RENCODE_FW_INTERFACE_MINOR_VERSION 2
+#define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
+#define RENCODE_FW_INTERFACE_MINOR_VERSION 1
 
 #define RENCODE_IB_PARAM_SESSION_INFO  0x0001
 #define RENCODE_IB_PARAM_TASK_INFO 0x0002
-- 
2.17.1

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[Mesa-dev] [PATCH] radeon/uvd: enable rate control for hevc encoding

[boyuan.zhang]

From: Boyuan Zhang 

Set cu_qp_delta_enable_flag on when rate control is enabled, and set it
off when rate control is disabled (e.g. constant qp).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org

V2: fix typo and add bugzilla info

Signed-off-by: Boyuan Zhang 
Acked-by: Leo Liu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
index 8f0e0099e7..9acc33d906 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -573,7 +573,13 @@ radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder 
*enc)
   enc->enc_pic.hevc_spec_misc.
   constrained_intra_pred_flag, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
-   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
+   if (enc->enc_pic.rc_session_init.rate_control_method ==
+  RENC_UVD_RATE_CONTROL_METHOD_NONE)
+  radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
+   else {
+  radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
+  radeon_uvd_enc_code_ue(enc, 0x0);
+   }
radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
-- 
2.17.1

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[Mesa-dev] [PATCH] radeon/vcn: enable rate control for hevc encoding

[boyuan.zhang]

From: Boyuan Zhang 

Set cu_qp_delta_enable_flag on when rate control is enabled, and set it
off when rate control is disabled (e.g. constant qp).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org

V2: fix typo and add bugzilla info

Signed-off-by: Boyuan Zhang 
Acked-by: Leo Liu 
---
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 3302ed7524..e4b9162034 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -687,7 +687,13 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder 
*enc)
radeon_enc_code_se(enc, 0x0);
radeon_enc_code_fixed_bits(enc, 
enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
-   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+   if (enc->enc_pic.rc_session_init.rate_control_method ==
+   RENCODE_RATE_CONTROL_METHOD_NONE)
+   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+   else {
+   radeon_enc_code_fixed_bits(enc, 0x1, 1);
+   radeon_enc_code_ue(enc, 0x0);
+   }
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
-- 
2.17.1

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[Mesa-dev] [PATCH] radeon/uvd: enable rate control for hevc encoding

[boyuan.zhang]

From: Boyuan Zhang 

Set cu_qp_delta_enable_flag on when rate control is enabled, and it
off when no rate control is disabled (constant qp).

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
index 8f0e0099e7..9acc33d906 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -573,7 +573,13 @@ radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder 
*enc)
   enc->enc_pic.hevc_spec_misc.
   constrained_intra_pred_flag, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
-   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
+   if (enc->enc_pic.rc_session_init.rate_control_method ==
+  RENC_UVD_RATE_CONTROL_METHOD_NONE)
+  radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
+   else {
+  radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
+  radeon_uvd_enc_code_ue(enc, 0x0);
+   }
radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
-- 
2.17.1

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[Mesa-dev] [PATCH] radeon/vcn: enable rate control for hevc encoding

[boyuan.zhang]

From: Boyuan Zhang 

Set cu_qp_delta_enable_flag on when rate control is enabled, and it
off when no rate control is disabled (constant qp).

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 3302ed7524..e4b9162034 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -687,7 +687,13 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder 
*enc)
radeon_enc_code_se(enc, 0x0);
radeon_enc_code_fixed_bits(enc, 
enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
-   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+   if (enc->enc_pic.rc_session_init.rate_control_method ==
+   RENC_UVD_RATE_CONTROL_METHOD_NONE)
+   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
+   else {
+   radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
+   radeon_uvd_enc_code_ue(enc, 0x0);
+   }
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
-- 
2.17.1

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[Mesa-dev] [PATCH] radeon/uvd: fix poc for hevc encode

[boyuan.zhang]

From: Boyuan Zhang 

MaxPicOrderCntLsb should be at least 16 according to the spec,
therefore add minimum value check.

Also use poc value passed from st instead of calculation
in slice header encoding.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org

V2: Fix typo

V3: Use MAX2 macro instead of coding. Also MaxPicOrderCntLsb
should be power of 2 according to spec.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.c | 3 ++-
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 3 +--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
index 521d08f304..3bceaccb70 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -73,7 +73,8 @@ radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
-   enc->enc_pic.max_poc = pic->seq.intra_period;
+   enc->enc_pic.max_poc =
+  MAX2(16, util_next_power_of_two(pic->seq.intra_period));
enc->enc_pic.log2_max_poc = 0;
for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
   i = (i >> 1);
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
index ddb219792a..8f0e0099e7 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -768,8 +768,7 @@ radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder 
*enc)
if ((enc->enc_pic.nal_unit_type != 19)
&& (enc->enc_pic.nal_unit_type != 20)) {
   radeon_uvd_enc_code_fixed_bits(enc,
- enc->enc_pic.frame_num %
- enc->enc_pic.max_poc,
+ enc->enc_pic.pic_order_cnt,
  enc->enc_pic.log2_max_poc);
   if (enc->enc_pic.picture_type == PIPE_H265_ENC_PICTURE_TYPE_P)
  radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
-- 
2.17.1

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[Mesa-dev] [PATCH] radeon/vcn: fix poc for hevc encode

[boyuan.zhang]

From: Boyuan Zhang 

MaxPicOrderCntLsb should be at least 16 according to the spec,
therefore add minimum value check.

Also use poc value passed from st instead of calculation
in slice header encoding.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org

V2: Fix typo

V3: Use MAX2 macro instead of coding. Also MaxPicOrderCntLsb
should be power of 2 according to spec.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc.c | 3 ++-
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index 8f9af73c66..3651d8a86b 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -72,7 +72,8 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder 
*enc, struct pipe_pic
   enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
   enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
   enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
-  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.max_poc =
+ MAX2(16, util_next_power_of_two(pic->seq.intra_period));
   enc->enc_pic.log2_max_poc = 0;
   for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
  i = (i >> 1);
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 7f5b190934..3302ed7524 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -988,7 +988,7 @@ static void radeon_enc_slice_header_hevc(struct 
radeon_encoder *enc)
}
 
if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type 
!= 20)) {
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 
enc->enc_pic.max_poc, enc->enc_pic.log2_max_poc);
+   radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, 
enc->enc_pic.log2_max_poc);
if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P)
radeon_enc_code_fixed_bits(enc, 0x1, 1);
else {
-- 
2.17.1

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[Mesa-dev] [PATCH] radeon/uvd: fix poc for hevc encode

[boyuan.zhang]

From: Boyuan Zhang 

MaxPicOrderCntLsb should be at least 16 according to the spec,
therefore add minimum value check.

Also use poc value passed from st instead of calculation
in slice header encoding.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org

V2: fix typo

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.c | 3 ++-
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 3 +--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
index 521d08f304..9256e43a08 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -73,7 +73,8 @@ radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
-   enc->enc_pic.max_poc = pic->seq.intra_period;
+   enc->enc_pic.max_poc =
+  (pic->seq.intra_period >= 16) ? pic->seq.intra_period : 16;
enc->enc_pic.log2_max_poc = 0;
for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
   i = (i >> 1);
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
index ddb219792a..8f0e0099e7 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -768,8 +768,7 @@ radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder 
*enc)
if ((enc->enc_pic.nal_unit_type != 19)
&& (enc->enc_pic.nal_unit_type != 20)) {
   radeon_uvd_enc_code_fixed_bits(enc,
- enc->enc_pic.frame_num %
- enc->enc_pic.max_poc,
+ enc->enc_pic.pic_order_cnt,
  enc->enc_pic.log2_max_poc);
   if (enc->enc_pic.picture_type == PIPE_H265_ENC_PICTURE_TYPE_P)
  radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
-- 
2.17.1

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[Mesa-dev] [PATCH] radeon/vcn: fix poc for hevc encode

[boyuan.zhang]

From: Boyuan Zhang 

MaxPicOrderCntLsb should be at least 16 according to the spec,
therefore add minimum value check.

Also use poc value passed from st instead of calculation
in slice header encoding.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org

V2: fix typo

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc.c | 3 ++-
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index 8f9af73c66..e949b7b3a9 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -72,7 +72,8 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder 
*enc, struct pipe_pic
   enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
   enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
   enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
-  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.max_poc =
+ (pic->seq.intra_period >= 16) ? pic->seq.intra_period : 16;
   enc->enc_pic.log2_max_poc = 0;
   for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
  i = (i >> 1);
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 7f5b190934..3302ed7524 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -988,7 +988,7 @@ static void radeon_enc_slice_header_hevc(struct 
radeon_encoder *enc)
}
 
if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type 
!= 20)) {
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 
enc->enc_pic.max_poc, enc->enc_pic.log2_max_poc);
+   radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, 
enc->enc_pic.log2_max_poc);
if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P)
radeon_enc_code_fixed_bits(enc, 0x1, 1);
else {
-- 
2.17.1

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[Mesa-dev] [PATCH] radeon/vcn: fix poc for hevc encode

[boyuan.zhang]

From: Boyuan Zhang 

MaxPicOrderCntLsb should be at 16 according to the spec,
therefore add minimum value check.

Also use poc value passed from st instead of calculation
in slice header encoding.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc.c | 3 ++-
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index 8f9af73c66..e949b7b3a9 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -72,7 +72,8 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder 
*enc, struct pipe_pic
   enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
   enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
   enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
-  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.max_poc =
+ (pic->seq.intra_period >= 16) ? pic->seq.intra_period : 16;
   enc->enc_pic.log2_max_poc = 0;
   for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
  i = (i >> 1);
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 7f5b190934..3302ed7524 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -988,7 +988,7 @@ static void radeon_enc_slice_header_hevc(struct 
radeon_encoder *enc)
}
 
if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type 
!= 20)) {
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 
enc->enc_pic.max_poc, enc->enc_pic.log2_max_poc);
+   radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, 
enc->enc_pic.log2_max_poc);
if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P)
radeon_enc_code_fixed_bits(enc, 0x1, 1);
else {
-- 
2.17.1

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[Mesa-dev] [PATCH] radeon/uvd: fix poc for hevc encode

[boyuan.zhang]

From: Boyuan Zhang 

MaxPicOrderCntLsb should be at 16 according to the spec,
therefore add minimum value check.

Also use poc value passed from st instead of calculation
in slice header encoding.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.c | 3 ++-
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 3 +--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
index 521d08f304..9256e43a08 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -73,7 +73,8 @@ radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
-   enc->enc_pic.max_poc = pic->seq.intra_period;
+   enc->enc_pic.max_poc =
+  (pic->seq.intra_period >= 16) ? pic->seq.intra_period : 16;
enc->enc_pic.log2_max_poc = 0;
for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
   i = (i >> 1);
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
index ddb219792a..8f0e0099e7 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -768,8 +768,7 @@ radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder 
*enc)
if ((enc->enc_pic.nal_unit_type != 19)
&& (enc->enc_pic.nal_unit_type != 20)) {
   radeon_uvd_enc_code_fixed_bits(enc,
- enc->enc_pic.frame_num %
- enc->enc_pic.max_poc,
+ enc->enc_pic.pic_order_cnt,
  enc->enc_pic.log2_max_poc);
   if (enc->enc_pic.picture_type == PIPE_H265_ENC_PICTURE_TYPE_P)
  radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
-- 
2.17.1

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[Mesa-dev] [PATCH] radeon/uvd: fix max poc for hevc encode

[boyuan.zhang]

From: Boyuan Zhang 

Fix max poc value with hardcoded value until new feature requires
to change this in the future.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.c | 4 +++-
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1 -
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
index 3164dbb2c20..2bfb5215be1 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -73,7 +73,9 @@ radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
-   enc->enc_pic.max_poc = pic->seq.intra_period;
+   enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
+   enc->enc_pic.max_poc =
+  (enc->enc_pic.layer_ctrl.max_num_temporal_layers == 4) ? 32 : 16;
enc->enc_pic.log2_max_poc = 0;
for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
   i = (i >> 1);
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
index 1f41b09472f..87d3d269cb1 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -262,7 +262,6 @@ radeon_uvd_enc_session_init_hevc(struct radeon_uvd_encoder 
*enc)
 static void
 radeon_uvd_enc_layer_control(struct radeon_uvd_encoder *enc)
 {
-   enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
 
RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_LAYER_CONTROL);
-- 
2.17.1

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[Mesa-dev] [PATCH] radeon/vcn: fix max poc for hevc encode

[boyuan.zhang]

From: Boyuan Zhang 

Fix max poc value with hardcoded value until new feature requires
to change this in the future.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc.c | 4 +++-
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 1 -
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index 7d64a28a405..b8c73227929 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -72,7 +72,9 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder 
*enc, struct pipe_pic
   enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
   enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
   enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
-  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
+  enc->enc_pic.max_poc =
+ (enc->enc_pic.layer_ctrl.max_num_temporal_layers == 4) ? 32 : 16;
   enc->enc_pic.log2_max_poc = 0;
   for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
  i = (i >> 1);
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 7f5b1909344..c489de39a89 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -253,7 +253,6 @@ static void radeon_enc_session_init_hevc(struct 
radeon_encoder *enc)
 
 static void radeon_enc_layer_control(struct radeon_encoder *enc)
 {
-   enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
 
RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_CONTROL);
-- 
2.17.1

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[Mesa-dev] [PATCH] st/va: reverse qt matrix back to its original order

[boyuan.zhang]

From: Boyuan Zhang 

The quantiser matrix that VAAPI provides has been applied with inverse z-scan.
However, what we expect in MPEG2 picture description is the original order.
Therefore, we need to reverse it back to its original order.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110257
Cc: mesa-sta...@lists.freedesktop.org

Signed-off-by: Boyuan Zhang 
Acked-by: Alex Deucher 
---
 src/gallium/state_trackers/va/picture_mpeg12.c | 38 ++
 1 file changed, 32 insertions(+), 6 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture_mpeg12.c 
b/src/gallium/state_trackers/va/picture_mpeg12.c
index 1e5a9c7..daf95f7 100644
--- a/src/gallium/state_trackers/va/picture_mpeg12.c
+++ b/src/gallium/state_trackers/va/picture_mpeg12.c
@@ -27,6 +27,19 @@
 
 #include "va_private.h"
 
+const int reverse_inverse_zscan[] =
+{
+   /* Reverse inverse z scan pattern */
+0,  2,  3,  9, 10, 20, 21, 35,
+1,  4,  8, 11, 19, 22, 34, 36,
+5,  7, 12, 18, 23, 33, 37, 48,
+6, 13, 17, 24, 32, 38, 47, 49,
+   14, 16, 25, 31, 39, 46, 50, 57,
+   15, 26, 30, 40, 45, 51, 56, 58,
+   27, 29, 41, 44, 52, 55, 59, 62,
+   28, 42, 43, 53, 54, 60, 61, 63,
+};
+
 void vlVaHandlePictureParameterBufferMPEG12(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *buf)
 {
VAPictureParameterBufferMPEG2 *mpeg2 = buf->data;
@@ -66,16 +79,29 @@ void vlVaHandlePictureParameterBufferMPEG12(vlVaDriver 
*drv, vlVaContext *contex
 void vlVaHandleIQMatrixBufferMPEG12(vlVaContext *context, vlVaBuffer *buf)
 {
VAIQMatrixBufferMPEG2 *mpeg2 = buf->data;
+   static uint8_t temp_intra_matrix[64];
+   static uint8_t temp_nonintra_matrix[64];
 
assert(buf->size >= sizeof(VAIQMatrixBufferMPEG2) && buf->num_elements == 
1);
-   if (mpeg2->load_intra_quantiser_matrix)
-  context->desc.mpeg12.intra_matrix = mpeg2->intra_quantiser_matrix;
-   else
+   if (mpeg2->load_intra_quantiser_matrix) {
+  /* The quantiser matrix that VAAPI provides has been applied
+ with inverse z-scan. However, what we expect in MPEG2
+ picture description is the original order. Therefore,
+ we need to reverse it back to its original order.
+  */
+  for (int i = 0; i < 64; i++)
+ temp_intra_matrix[i] =
+mpeg2->intra_quantiser_matrix[reverse_inverse_zscan[i]];
+  context->desc.mpeg12.intra_matrix = temp_intra_matrix;
+   } else
   context->desc.mpeg12.intra_matrix = NULL;
 
-   if (mpeg2->load_non_intra_quantiser_matrix)
-  context->desc.mpeg12.non_intra_matrix = 
mpeg2->non_intra_quantiser_matrix;
-   else
+   if (mpeg2->load_non_intra_quantiser_matrix) {
+  for (int i = 0; i < 64; i++)
+ temp_nonintra_matrix[i] =
+mpeg2->non_intra_quantiser_matrix[reverse_inverse_zscan[i]];
+  context->desc.mpeg12.non_intra_matrix = temp_nonintra_matrix;
+   } else
   context->desc.mpeg12.non_intra_matrix = NULL;
 }
 
-- 
2.7.4

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[Mesa-dev] [PATCH 3/3] radeon/vcn: use util function to get h264 profile idc

[boyuan.zhang]

From: Boyuan Zhang 

Use utility function for converting h264 pipe video profile to profile idc,
instead of using array.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 143721211db..a29c0a0150d 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -48,7 +48,6 @@ RADEON_ENC_CS(cmd)
 #define RADEON_ENC_END() *begin = (>cs->current.buf[enc->cs->current.cdw] 
- begin) * 4; \
enc->total_task_size += *begin;}
 
-static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
 static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
 
 static void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer 
*buf,
@@ -303,7 +302,7 @@ static void radeon_enc_spec_misc(struct radeon_encoder *enc)
enc->enc_pic.spec_misc.cabac_init_idc = 0;
enc->enc_pic.spec_misc.half_pel_enabled = 1;
enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
-   enc->enc_pic.spec_misc.profile_idc = profiles[enc->base.profile - 
PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE];
+   enc->enc_pic.spec_misc.profile_idc = 
u_get_h264_profile_idc(enc->base.profile);
enc->enc_pic.spec_misc.level_idc = enc->base.level;
 
RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SPEC_MISC);
-- 
2.17.1

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[Mesa-dev] [PATCH 2/3] radeon/vce: use util function to get h264 profile idc

[boyuan.zhang]

From: Boyuan Zhang 

Use utility function for converting h264 pipe video profile to profile idc,
instead of using array.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 5 +
 src/gallium/drivers/radeon/radeon_vce_52.c | 5 +
 2 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c 
b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
index 66b54dab25a..e17468c9097 100644
--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
@@ -38,8 +38,6 @@
 #include "radeon_video.h"
 #include "radeon_vce.h"
 
-static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
-
 static void session(struct rvce_encoder *enc)
 {
RVCE_BEGIN(0x0001); // session cmd
@@ -82,8 +80,7 @@ static void create(struct rvce_encoder *enc)
 
RVCE_BEGIN(0x0101); // create cmd
RVCE_CS(0x); // encUseCircularBuffer
-   RVCE_CS(profiles[enc->base.profile -
-   PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]); // encProfile
+   RVCE_CS(u_get_h264_profile_idc(enc->base.profile)); // encProfile
RVCE_CS(enc->base.level); // encLevel
RVCE_CS(0x); // encPicStructRestriction
RVCE_CS(enc->base.width); // encImageWidth
diff --git a/src/gallium/drivers/radeon/radeon_vce_52.c 
b/src/gallium/drivers/radeon/radeon_vce_52.c
index 421539c4bdc..fc7ddc62a90 100644
--- a/src/gallium/drivers/radeon/radeon_vce_52.c
+++ b/src/gallium/drivers/radeon/radeon_vce_52.c
@@ -38,8 +38,6 @@
 #include "radeon_video.h"
 #include "radeon_vce.h"
 
-static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
-
 static void get_rate_control_param(struct rvce_encoder *enc, struct 
pipe_h264_enc_picture_desc *pic)
 {
enc->enc_pic.rc.rc_method = pic->rate_ctrl.rate_ctrl_method;
@@ -172,8 +170,7 @@ static void create(struct rvce_encoder *enc)
 
RVCE_BEGIN(0x0101); // create cmd
RVCE_CS(enc->enc_pic.ec.enc_use_circular_buffer);
-   RVCE_CS(profiles[enc->base.profile -
-   PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]); // encProfile
+   RVCE_CS(u_get_h264_profile_idc(enc->base.profile)); // encProfile
RVCE_CS(enc->base.level); // encLevel
RVCE_CS(enc->enc_pic.ec.enc_pic_struct_restriction);
RVCE_CS(enc->base.width); // encImageWidth
-- 
2.17.1

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[Mesa-dev] [PATCH 1/3] vl: get h264 profile idc

[boyuan.zhang]

From: Boyuan Zhang 

Adding a function for converting h264 pipe video profile to profile idc

Signed-off-by: Boyuan Zhang 
---
 src/gallium/auxiliary/util/u_video.h | 24 
 1 file changed, 24 insertions(+)

diff --git a/src/gallium/auxiliary/util/u_video.h 
b/src/gallium/auxiliary/util/u_video.h
index 967ebc57489..f6e93dd0387 100644
--- a/src/gallium/auxiliary/util/u_video.h
+++ b/src/gallium/auxiliary/util/u_video.h
@@ -239,6 +239,30 @@ u_get_h264_level(uint32_t width, uint32_t height, uint32_t 
*max_reference)
   return 52;
 }
 
+static inline uint32_t
+u_get_h264_profile_idc(enum pipe_video_profile profile)
+{
+   switch (profile) {
+  case PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE:
+  case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
+ return 66;
+  case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
+ return 77;
+  case PIPE_VIDEO_PROFILE_MPEG4_AVC_EXTENDED:
+ return 88;
+  case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
+ return 100;
+  case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH10:
+ return 110;
+  case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH422:
+ return 122;
+  case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH444:
+ return 244;
+  default:
+ return 66; //use baseline profile instead
+   }
+}
+
 #ifdef __cplusplus
 }
 #endif
-- 
2.17.1

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[Mesa-dev] [PATCH 15/15] radeonsi: enable vcn jpeg decode for raven

[boyuan.zhang]

From: Boyuan Zhang 

Enable vcn jpeg decode for raven.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/gallium/drivers/radeonsi/si_get.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index a87cb3cbc8..9b995bbcbf 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -628,6 +628,8 @@ static int si_get_video_param(struct pipe_screen *screen,
return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
return false;
case PIPE_VIDEO_FORMAT_JPEG:
+   if (sscreen->info.family == CHIP_RAVEN)
+   return true;
if (sscreen->info.family < CHIP_CARRIZO || 
sscreen->info.family >= CHIP_VEGA10)
return false;
if (!(sscreen->info.drm_major == 3 && 
sscreen->info.drm_minor >= 19)) {
-- 
2.17.1

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[Mesa-dev] [PATCH 13/15] amd/common: add vcn jpeg ip info query

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/amd/common/ac_gpu_info.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 766ad83547..8c50738c3f 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -99,7 +99,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
struct drm_amdgpu_info_device device_info = {};
struct amdgpu_buffer_size_alignments alignment_info = {};
struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
-   struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
+   struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, 
vcn_jpeg = {};
struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
struct amdgpu_gds_resource_info gds = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature 
= 0;
@@ -186,6 +186,14 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
}
 
+   if (info->drm_major == 3 && info->drm_minor >= 17) {
+   r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, 
_jpeg);
+   if (r) {
+   fprintf(stderr, "amdgpu: 
amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
+   return false;
+   }
+   }
+
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
>me_fw_version,
>me_fw_feature);
@@ -340,7 +348,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->max_se = amdinfo->num_shader_engines;
info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
info->has_hw_decode =
-   (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
+   (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
+   (vcn_jpeg.available_rings != 0);
info->uvd_fw_version =
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
@@ -439,6 +448,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
ib_align = MAX2(ib_align, vce.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
+   ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
assert(ib_align);
info->ib_start_alignment = ib_align;
 
-- 
2.17.1

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[Mesa-dev] [PATCH 14/15] winsys/amdgpu: add vcn jpeg cs support

[boyuan.zhang]

From: Boyuan Zhang 

Add vcn jpeg cs support, align cs by no-op.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index c0f8b442b1..5986810d4e 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -845,6 +845,10 @@ static bool amdgpu_init_cs_context(struct amdgpu_winsys 
*ws,
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_ENC;
   break;
 
+   case RING_VCN_JPEG:
+  cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_JPEG;
+  break;
+
case RING_COMPUTE:
case RING_GFX:
   cs->ib[IB_MAIN].ip_type = ring_type == RING_GFX ? AMDGPU_HW_IP_GFX :
@@ -1589,6 +1593,14 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
   while (rcs->current.cdw & 15)
  radeon_emit(rcs, 0x8000); /* type2 nop packet */
   break;
+   case RING_VCN_JPEG:
+  if (rcs->current.cdw % 2)
+ assert(0);
+  while (rcs->current.cdw & 15) {
+ radeon_emit(rcs, 0x6000); /* nop packet */
+ radeon_emit(rcs, 0x);
+  }
+  break;
case RING_VCN_DEC:
   while (rcs->current.cdw & 15)
  radeon_emit(rcs, 0x81ff); /* nop packet */
-- 
2.17.1

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[Mesa-dev] [PATCH 12/15] radeon/vcn: implement jpeg target buffer cmd

[boyuan.zhang]

From: Boyuan Zhang 

Implement jpeg target buffer cmd by programming registers directly,
since there is no firmware for VCN Jpeg decode.

Signed-off-by: Boyuan Zhang 
Acked-by: Leo Liu 
---
 .../drivers/radeon/radeon_vcn_dec_jpeg.c  | 73 ++-
 1 file changed, 72 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
index 0d96acfcd2..afa2015b09 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
@@ -116,7 +116,78 @@ static void send_cmd_target(struct radeon_decoder *dec,
 struct pb_buffer* buf, uint32_t off,
 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
 {
-   /* TODO */
+   uint64_t addr;
+
+   set_reg_jpeg(dec, mmUVD_JPEG_PITCH, COND0, TYPE0, (dec->jpg.dt_pitch >> 
4));
+   set_reg_jpeg(dec, mmUVD_JPEG_UV_PITCH, COND0, TYPE0, 
((dec->jpg.dt_uv_pitch * 2) >> 4));
+
+   set_reg_jpeg(dec, mmUVD_JPEG_TILING_CTRL, COND0, TYPE0, 0);
+   set_reg_jpeg(dec, mmUVD_JPEG_UV_TILING_CTRL, COND0, TYPE0, 0);
+
+   dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, 0);
+   addr = dec->ws->buffer_get_virtual_address(buf);
+   addr = addr + off;
+
+   // set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer 
address
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0, 
(addr >> 32));
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0, 
addr);
+
+   // set output buffer data address
+   set_reg_jpeg(dec, mmUVD_JPEG_INDEX, COND0, TYPE0, 0);
+   set_reg_jpeg(dec, mmUVD_JPEG_DATA, COND0, TYPE0, 
dec->jpg.dt_luma_top_offset);
+   set_reg_jpeg(dec, mmUVD_JPEG_INDEX, COND0, TYPE0, 1);
+   set_reg_jpeg(dec, mmUVD_JPEG_DATA, COND0, TYPE0, 
dec->jpg.dt_chroma_top_offset);
+   set_reg_jpeg(dec, mmUVD_JPEG_TIER_CNTL2, COND0, TYPE3, 0);
+
+   // set output buffer read pointer
+   set_reg_jpeg(dec, mmUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0);
+
+   // enable error interrupts
+   set_reg_jpeg(dec, mmUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFE);
+
+   // start engine command
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0x6);
+
+   // wait for job completion, wait for job JBSI fetch done
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (dec->jpg.bsd_size >> 
2));
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C2);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x01400200);
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_RPTR, COND0, TYPE3, 0x);
+
+   // wait for job jpeg outbuf idle
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x);
+   set_reg_jpeg(dec, mmUVD_JPEG_OUTBUF_WPTR, COND0, TYPE3, 0x0001);
+
+   // stop engine
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0x4);
+
+   // asserting jpeg lmi drop
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x0005);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 23 | 1 << 0));
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE1, 0);
+
+   // asserting jpeg reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 1);
+
+   // ensure reset is asserted in sclk domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // de-assert jpeg reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0);
+
+   // ensure reset is de-asserted in sclk domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (0 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // de-asserting jpeg lmi drop
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x0005);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0);
 }
 
 /**
-- 
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[Mesa-dev] [PATCH 09/15] st/va: get mjpeg slice header

[boyuan.zhang]

From: Boyuan Zhang 

Move the previous get_mjpeg_slice_heaeder function and eoi from
"radeon/vcn" to "st/va".

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/gallium/state_trackers/va/picture.c   |  13 +-
 src/gallium/state_trackers/va/picture_mjpeg.c | 142 ++
 src/gallium/state_trackers/va/va_private.h|  11 ++
 3 files changed, 164 insertions(+), 2 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index e2cdb2b40c..04d2da0afe 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -259,11 +259,12 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
 {
enum pipe_video_format format;
unsigned num_buffers = 0;
-   void * const *buffers[2];
-   unsigned sizes[2];
+   void * const *buffers[3];
+   unsigned sizes[3];
static const uint8_t start_code_h264[] = { 0x00, 0x00, 0x01 };
static const uint8_t start_code_h265[] = { 0x00, 0x00, 0x01 };
static const uint8_t start_code_vc1[] = { 0x00, 0x00, 0x01, 0x0d };
+   static const uint8_t eoi_jpeg[] = { 0xff, 0xd9 };
 
format = u_reduce_video_profile(context->templat.profile);
switch (format) {
@@ -301,6 +302,9 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
   sizes[num_buffers++] = context->mpeg4.start_code_size;
   break;
case PIPE_VIDEO_FORMAT_JPEG:
+  vlVaGetJpegSliceHeader(context);
+  buffers[num_buffers] = (void *)context->mjpeg.slice_header;
+  sizes[num_buffers++] = context->mjpeg.slice_header_size;
   break;
case PIPE_VIDEO_FORMAT_VP9:
   vlVaDecoderVP9BitstreamHeader(context, buf);
@@ -313,6 +317,11 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
sizes[num_buffers] = buf->size;
++num_buffers;
 
+   if (format == PIPE_VIDEO_FORMAT_JPEG) {
+  buffers[num_buffers] = (void *const)_jpeg;
+  sizes[num_buffers++] = sizeof(eoi_jpeg);
+   }
+
if (context->needs_begin_frame) {
   context->decoder->begin_frame(context->decoder, context->target,
  >desc.base);
diff --git a/src/gallium/state_trackers/va/picture_mjpeg.c 
b/src/gallium/state_trackers/va/picture_mjpeg.c
index 396b743442..defb0b546d 100644
--- a/src/gallium/state_trackers/va/picture_mjpeg.c
+++ b/src/gallium/state_trackers/va/picture_mjpeg.c
@@ -114,3 +114,145 @@ void vlVaHandleSliceParameterBufferMJPEG(vlVaContext 
*context, vlVaBuffer *buf)
context->desc.mjpeg.slice_parameter.restart_interval = 
mjpeg->restart_interval;
context->desc.mjpeg.slice_parameter.num_mcus = mjpeg->num_mcus;
 }
+
+void vlVaGetJpegSliceHeader(vlVaContext *context)
+{
+   int size = 0, saved_size, len_pos, i;
+   uint16_t *bs;
+   uint8_t *p = context->mjpeg.slice_header;
+
+   /* SOI */
+   p[size++] = 0xff;
+   p[size++] = 0xd8;
+
+   /* DQT */
+   p[size++] = 0xff;
+   p[size++] = 0xdb;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 4; ++i) {
+  if (context->desc.mjpeg.quantization_table.load_quantiser_table[i] == 0)
+ continue;
+
+  p[size++] = i;
+  memcpy((p + size), 
>desc.mjpeg.quantization_table.quantiser_table[i], 64);
+  size += 64;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - 4);
+
+   saved_size = size;
+
+   /* DHT */
+   p[size++] = 0xff;
+   p[size++] = 0xc4;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 2; ++i) {
+  int num = 0, j;
+
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x00 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_dc_codes, 16);
+  size += 16;
+  for (j = 0; j < 16; ++j)
+ num += context->desc.mjpeg.huffman_table.table[i].num_dc_codes[j];
+  assert(num <= 12);
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].dc_values, num);
+  size += num;
+   }
+
+   for (i = 0; i < 2; ++i) {
+  int num = 0, j;
+
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x10 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_ac_codes, 16);
+  size += 16;
+  for (j = 0; j < 16; ++j)
+ num += context->desc.mjpeg.huffman_table.table[i].num_ac_codes[j];
+  assert(num <= 162);
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].ac_values, num);
+  size += num;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - saved_size - 2);
+
+   saved_size = size;
+
+   /* DRI */
+   if (context->desc.mjpeg.slice_parameter.restart_interval) {
+  p[size++] = 0xff;
+  p[size++] = 0xdd;
+  p[size++] = 0x00;
+  p[size++] = 0x04;
+  bs = (uint16_t*)[size++];
+  *bs = util_bswap16(context->desc.mjpeg.slice_parameter.restart_interval);
+  saved_size = ++size;
+   }
+
+   /* SOF */
+   p[size++] = 0xff;
+   p[size++] = 0xc0;
+
+   len_pos = size++;
+   size++;
+
+   p[size++] 

[Mesa-dev] [PATCH 08/15] radeon/vcn: add jpeg decode implementation

[boyuan.zhang]

From: Boyuan Zhang 

Add a new file to handle VCN Jpeg decode specific functions. Use Jpeg
specific cmd sending function in end_frame call.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c   | 21 ++--
 src/gallium/drivers/radeon/radeon_vcn_dec.h   |  4 +
 .../drivers/radeon/radeon_vcn_dec_jpeg.c  | 99 +++
 src/gallium/drivers/radeonsi/Makefile.sources |  1 +
 src/gallium/drivers/radeonsi/meson.build  |  1 +
 5 files changed, 119 insertions(+), 7 deletions(-)
 create mode 100644 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 30a98c2786..75ef4a5d40 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1247,6 +1247,10 @@ static unsigned calc_dpb_size(struct radeon_decoder *dec)
dpb_size *= (3 / 2);
break;
 
+   case PIPE_VIDEO_FORMAT_JPEG:
+   dpb_size = 0;
+   break;
+
default:
// something is missing here
assert(0);
@@ -1547,14 +1551,14 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
}
 
dpb_size = calc_dpb_size(dec);
-
-   if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {
-   RVID_ERR("Can't allocated dpb.\n");
-   goto error;
+   if (dpb_size) {
+   if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {
+   RVID_ERR("Can't allocated dpb.\n");
+   goto error;
+   }
+   si_vid_clear_buffer(context, >dpb);
}
 
-   si_vid_clear_buffer(context, >dpb);
-
if (dec->stream_type == RDECODE_CODEC_H264_PERF) {
unsigned ctx_size = calc_ctx_size_h264_perf(dec);
if (!si_vid_create_buffer(dec->screen, >ctx, ctx_size, 
PIPE_USAGE_DEFAULT)) {
@@ -1581,7 +1585,10 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
 
next_buffer(dec);
 
-   dec->send_cmd = send_cmd_dec;
+   if (stream_type == RDECODE_CODEC_JPEG)
+   dec->send_cmd = send_cmd_jpeg;
+   else
+   dec->send_cmd = send_cmd_dec;
 
return >base;
 
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index 37c0503377..a6a726f46d 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -768,6 +768,10 @@ void send_cmd_dec(struct radeon_decoder *dec,
  struct pipe_video_buffer *target,
  struct pipe_picture_desc *picture);
 
+void send_cmd_jpeg(struct radeon_decoder *dec,
+ struct pipe_video_buffer *target,
+ struct pipe_picture_desc *picture);
+
 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templat);
 
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
new file mode 100644
index 00..7c078a0964
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
@@ -0,0 +1,99 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_memory.h"
+#include "util/u_video.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_vcn_dec.h"
+
+static struct pb_buffer 

[Mesa-dev] [PATCH 07/15] radeon/vcn: separate send cmd call from end frame

[boyuan.zhang]

From: Boyuan Zhang 

Use function pointer for sending cmd in end_frame call. By doing this, we can
assign different cmd sending logics for Jpeg decode later.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 29 +++--
 src/gallium/drivers/radeon/radeon_vcn_dec.h |  7 +
 2 files changed, 28 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 26ea1f82ff..30a98c2786 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1368,21 +1368,15 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,
 }
 
 /**
- * end decoding of the current frame
+ * send cmd for vcn dec
  */
-static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
+void send_cmd_dec(struct radeon_decoder *dec,
   struct pipe_video_buffer *target,
   struct pipe_picture_desc *picture)
 {
-   struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
struct pb_buffer *dt;
struct rvid_buffer *msg_fb_it_probs_buf, *bs_buf;
 
-   assert(decoder);
-
-   if (!dec->bs_ptr)
-   return;
-
msg_fb_it_probs_buf = >msg_fb_it_probs_buffers[dec->cur_buffer];
bs_buf = >bs_buffers[dec->cur_buffer];
 
@@ -1412,6 +1406,23 @@ static void radeon_dec_end_frame(struct pipe_video_codec 
*decoder,
send_cmd(dec, RDECODE_CMD_PROB_TBL_BUFFER, 
msg_fb_it_probs_buf->res->buf,
 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, 
RADEON_DOMAIN_GTT);
set_reg(dec, RDECODE_ENGINE_CNTL, 1);
+}
+
+/**
+ * end decoding of the current frame
+ */
+static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
+  struct pipe_video_buffer *target,
+  struct pipe_picture_desc *picture)
+{
+   struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
+
+   assert(decoder);
+
+   if (!dec->bs_ptr)
+   return;
+
+   dec->send_cmd(dec, target, picture);
 
flush(dec, PIPE_FLUSH_ASYNC);
next_buffer(dec);
@@ -1570,6 +1581,8 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
 
next_buffer(dec);
 
+   dec->send_cmd = send_cmd_dec;
+
return >base;
 
 error:
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index 2bcc1bb542..37c0503377 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -759,8 +759,15 @@ struct radeon_decoder {
boolshow_frame;
unsignedref_idx;
struct jpeg_params  jpg;
+   void (*send_cmd)(struct radeon_decoder *dec,
+struct pipe_video_buffer *target,
+struct pipe_picture_desc *picture);
 };
 
+void send_cmd_dec(struct radeon_decoder *dec,
+ struct pipe_video_buffer *target,
+ struct pipe_picture_desc *picture);
+
 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templat);
 
-- 
2.17.1

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[Mesa-dev] [PATCH 11/15] radeon/vcn: implement jpeg bitstream buffer cmd

[boyuan.zhang]

From: Boyuan Zhang 

Implement jpeg bitstream buffer cmd by programming registers directly,
since there is no firmware for VCN Jpeg decode.

Signed-off-by: Boyuan Zhang 
Acked-by: Leo Liu 
---
 .../drivers/radeon/radeon_vcn_dec_jpeg.c  | 46 ++-
 1 file changed, 45 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
index 7c078a0964..0d96acfcd2 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
@@ -59,12 +59,56 @@ static struct pb_buffer 
*radeon_jpeg_get_decode_param(struct radeon_decoder *dec
return luma->buffer.buf;
 }
 
+/* add a new set register command to the IB */
+static void set_reg_jpeg(struct radeon_decoder *dec, unsigned reg,
+unsigned cond, unsigned type, uint32_t val)
+{
+   radeon_emit(dec->cs, RDECODE_PKTJ(SOC15_REG_ADDR(reg), cond, type));
+   radeon_emit(dec->cs, val);
+}
+
 /* send a bitstream buffer command */
 static void send_cmd_bitstream(struct radeon_decoder *dec,
 struct pb_buffer* buf, uint32_t off,
 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
 {
-   /* TODO */
+   uint64_t addr;
+
+   // jpeg soft reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 1);
+
+   // ensuring the Reset is asserted in SCLK domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C2);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x01400200);
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // wait mem
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0);
+
+   // ensuring the Reset is de-asserted in SCLK domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (0 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, 0);
+   addr = dec->ws->buffer_get_virtual_address(buf);
+   addr = addr + off;
+
+   // set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer 
address
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0, 
(addr >> 32));
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0, 
addr);
+
+   // set jpeg_rb_base
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_BASE, COND0, TYPE0, 0);
+
+   // set jpeg_rb_base
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFF0);
+
+   // set jpeg_rb_wptr
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_WPTR, COND0, TYPE0, (dec->jpg.bsd_size 
>> 2));
 }
 
 /* send a target buffer command */
-- 
2.17.1

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[Mesa-dev] [PATCH 10/15] radeon/uvd: remove get mjpeg slice header

[boyuan.zhang]

From: Boyuan Zhang 

Move the previous get_mjpeg_slice_heaeder function and eoi from
"radeon/vcn" to "st/va".

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/gallium/drivers/radeon/radeon_uvd.c | 157 
 1 file changed, 157 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd.c 
b/src/gallium/drivers/radeon/radeon_uvd.c
index a7ef4252ee..0f3b43de81 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -964,149 +964,6 @@ static struct ruvd_mpeg4 get_mpeg4_msg(struct 
ruvd_decoder *dec,
return result;
 }
 
-static void get_mjpeg_slice_header(struct ruvd_decoder *dec, struct 
pipe_mjpeg_picture_desc *pic)
-{
-   int size = 0, saved_size, len_pos, i;
-   uint16_t *bs;
-   uint8_t *buf = dec->bs_ptr;
-
-   /* SOI */
-   buf[size++] = 0xff;
-   buf[size++] = 0xd8;
-
-   /* DQT */
-   buf[size++] = 0xff;
-   buf[size++] = 0xdb;
-
-   len_pos = size++;
-   size++;
-
-   for (i = 0; i < 4; ++i) {
-   if (pic->quantization_table.load_quantiser_table[i] == 0)
-   continue;
-
-   buf[size++] = i;
-   memcpy((buf + size), 
>quantization_table.quantiser_table[i], 64);
-   size += 64;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - 4);
-
-   saved_size = size;
-
-   /* DHT */
-   buf[size++] = 0xff;
-   buf[size++] = 0xc4;
-
-   len_pos = size++;
-   size++;
-
-   for (i = 0; i < 2; ++i) {
-   int num = 0, j;
-
-   if (pic->huffman_table.load_huffman_table[i] == 0)
-   continue;
-
-   buf[size++] = 0x00 | i;
-   memcpy((buf + size), >huffman_table.table[i].num_dc_codes, 
16);
-   size += 16;
-   for (j = 0; j < 16; ++j)
-   num += pic->huffman_table.table[i].num_dc_codes[j];
-   assert(num <= 12);
-   memcpy((buf + size), >huffman_table.table[i].dc_values, 
num);
-   size += num;
-   }
-
-   for (i = 0; i < 2; ++i) {
-   int num = 0, j;
-
-   if (pic->huffman_table.load_huffman_table[i] == 0)
-   continue;
-
-   buf[size++] = 0x10 | i;
-   memcpy((buf + size), >huffman_table.table[i].num_ac_codes, 
16);
-   size += 16;
-   for (j = 0; j < 16; ++j)
-   num += pic->huffman_table.table[i].num_ac_codes[j];
-   assert(num <= 162);
-   memcpy((buf + size), >huffman_table.table[i].ac_values, 
num);
-   size += num;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   saved_size = size;
-
-   /* DRI */
-   if (pic->slice_parameter.restart_interval) {
-   buf[size++] = 0xff;
-   buf[size++] = 0xdd;
-   buf[size++] = 0x00;
-   buf[size++] = 0x04;
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->slice_parameter.restart_interval);
-   saved_size = ++size;
-   }
-
-   /* SOF */
-   buf[size++] = 0xff;
-   buf[size++] = 0xc0;
-
-   len_pos = size++;
-   size++;
-
-   buf[size++] = 0x08;
-
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->picture_parameter.picture_height);
-   size++;
-
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->picture_parameter.picture_width);
-   size++;
-
-   buf[size++] = pic->picture_parameter.num_components;
-
-   for (i = 0; i < pic->picture_parameter.num_components; ++i) {
-   buf[size++] = pic->picture_parameter.components[i].component_id;
-   buf[size++] = 
pic->picture_parameter.components[i].h_sampling_factor << 4 |
-   pic->picture_parameter.components[i].v_sampling_factor;
-   buf[size++] = 
pic->picture_parameter.components[i].quantiser_table_selector;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   saved_size = size;
-
-   /* SOS */
-   buf[size++] = 0xff;
-   buf[size++] = 0xda;
-
-   len_pos = size++;
-   size++;
-
-   buf[size++] = pic->slice_parameter.num_components;
-
-   for (i = 0; i < pic->slice_parameter.num_components; ++i) {
-   buf[size++] = 
pic->slice_parameter.components[i].component_selector;
-   buf[size++] = 
pic->slice_parameter.components[i].dc_table_selector << 4 |
-   pic->slice_parameter.components[i].ac_table_selector;
-   }
-
-   buf[size++] = 0x00;
-   buf[size++] = 0x3f;
-   buf[size++] = 0x00;
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   dec->bs_ptr += size;
-   dec->bs_size += size;
-}
-
 /**
  * destroy this 

[Mesa-dev] [PATCH 06/15] radeon/vcn: create cs based on ring type

[boyuan.zhang]

From: Boyuan Zhang 

Add RING_VCN_JPEG for VCN Jpeg decode, and keep RING_VCN_DEC for other codecs.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index fbfef6d273..26ea1f82ff 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1433,7 +1433,7 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
struct si_context *sctx = (struct si_context*)context;
struct radeon_winsys *ws = sctx->ws;
unsigned width = templ->width, height = templ->height;
-   unsigned dpb_size, bs_buf_size, stream_type = 0;
+   unsigned dpb_size, bs_buf_size, stream_type = 0, ring = RING_VCN_DEC;
struct radeon_decoder *dec;
int r, i;
 
@@ -1462,6 +1462,10 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
case PIPE_VIDEO_FORMAT_VP9:
stream_type = RDECODE_CODEC_VP9;
break;
+   case PIPE_VIDEO_FORMAT_JPEG:
+   stream_type = RDECODE_CODEC_JPEG;
+   ring = RING_VCN_JPEG;
+   break;
default:
assert(0);
break;
@@ -1488,7 +1492,7 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
dec->stream_handle = si_vid_alloc_stream_handle();
dec->screen = context->screen;
dec->ws = ws;
-   dec->cs = ws->cs_create(sctx->ctx, RING_VCN_DEC, NULL, NULL);
+   dec->cs = ws->cs_create(sctx->ctx, ring, NULL, NULL);
if (!dec->cs) {
RVID_ERR("Can't get command submission context.\n");
goto error;
-- 
2.17.1

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[Mesa-dev] [PATCH 05/15] radeon/winsys: add vcn jpeg ring type

[boyuan.zhang]

From: Boyuan Zhang 

Add a new ring type for vcn jpeg.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/gallium/drivers/radeon/radeon_winsys.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index bb732ab314..c6800808cb 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -87,6 +87,7 @@ enum ring_type {
 RING_UVD_ENC,
 RING_VCN_DEC,
 RING_VCN_ENC,
+RING_VCN_JPEG,
 RING_LAST,
 };
 
-- 
2.17.1

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[Mesa-dev] [PATCH 04/15] radeon/vcn: add vcn jpeg decode interface

[boyuan.zhang]

From: Boyuan Zhang 

Add VCN Jpeg decode interfaces and register defines.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.h | 90 +
 1 file changed, 90 insertions(+)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index c6c2a933cc..2bcc1bb542 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -43,6 +43,15 @@
 
 #define RDECODE_PKT2() (RDECODE_PKT_TYPE_S(2))
 
+#define RDECODE_PKT_REG_J(x)   ((unsigned)(x) & 0x3)
+#define RDECODE_PKT_RES_J(x)   (((unsigned)(x) & 0x3F) << 18)
+#define RDECODE_PKT_COND_J(x)  (((unsigned)(x) & 0xF) << 24)
+#define RDECODE_PKT_TYPE_J(x)  (((unsigned)(x) & 0xF) << 28)
+#define RDECODE_PKTJ(reg, cond, type)  (RDECODE_PKT_REG_J(reg) | \
+   RDECODE_PKT_RES_J(0) | \
+   RDECODE_PKT_COND_J(cond) | \
+   RDECODE_PKT_TYPE_J(type))
+
 #define RDECODE_CMD_MSG_BUFFER 0x
 #define RDECODE_CMD_DPB_BUFFER 0x0001
 #define RDECODE_CMD_DECODING_TARGET_BUFFER 0x0002
@@ -62,6 +71,7 @@
 #define RDECODE_CODEC_MPEG2_VLD0x0003
 #define RDECODE_CODEC_MPEG40x0004
 #define RDECODE_CODEC_H264_PERF0x0007
+#define RDECODE_CODEC_JPEG 0x0008
 #define RDECODE_CODEC_H265 0x0010
 #define RDECODE_CODEC_VP9  0x0011
 
@@ -112,6 +122,77 @@
 
 #define RDECODE_VP9_PROBS_DATA_SIZE2304
 
+#define mmUVD_JPEG_CNTL0x0200
+#define mmUVD_JPEG_CNTL_BASE_IDX   1
+#define mmUVD_JPEG_RB_BASE 0x0201
+#define mmUVD_JPEG_RB_BASE_BASE_IDX1
+#define mmUVD_JPEG_RB_WPTR 0x0202
+#define mmUVD_JPEG_RB_WPTR_BASE_IDX1
+#define mmUVD_JPEG_RB_RPTR 0x0203
+#define mmUVD_JPEG_RB_RPTR_BASE_IDX1
+#define mmUVD_JPEG_RB_SIZE 0x0204
+#define mmUVD_JPEG_RB_SIZE_BASE_IDX1
+#define mmUVD_JPEG_TIER_CNTL2  0x021a
+#define mmUVD_JPEG_TIER_CNTL2_BASE_IDX 1
+#define mmUVD_JPEG_UV_TILING_CTRL  0x021c
+#define mmUVD_JPEG_UV_TILING_CTRL_BASE_IDX 1
+#define mmUVD_JPEG_TILING_CTRL 0x021e
+#define mmUVD_JPEG_TILING_CTRL_BASE_IDX1
+#define mmUVD_JPEG_OUTBUF_RPTR 0x0220
+#define mmUVD_JPEG_OUTBUF_RPTR_BASE_IDX1
+#define mmUVD_JPEG_OUTBUF_WPTR 0x0221
+#define mmUVD_JPEG_OUTBUF_WPTR_BASE_IDX1
+#define mmUVD_JPEG_PITCH   0x0222
+#define mmUVD_JPEG_PITCH_BASE_IDX  1
+#define mmUVD_JPEG_INT_EN  0x0229
+#define mmUVD_JPEG_INT_EN_BASE_IDX 1
+#define mmUVD_JPEG_UV_PITCH0x022b
+#define mmUVD_JPEG_UV_PITCH_BASE_IDX   1
+#define mmUVD_JPEG_INDEX   0x023e
+#define mmUVD_JPEG_INDEX_BASE_IDX  1
+#define mmUVD_JPEG_DATA0x023f
+#define mmUVD_JPEG_DATA_BASE_IDX   1
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH0x0438
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX   1
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0439
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX1
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x045a
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX1
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW  0x045b
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_CTX_INDEX0x0528
+#define mmUVD_CTX_INDEX_BASE_IDX   1
+#define mmUVD_CTX_DATA 0x0529
+#define mmUVD_CTX_DATA_BASE_IDX1
+#define mmUVD_SOFT_RESET   0x05a0
+#define mmUVD_SOFT_RESET_BASE_IDX  1
+
+#define UVD_BASE_INST0_SEG00x7800
+#define UVD_BASE_INST0_SEG10x7E00
+#define UVD_BASE_INST0_SEG20
+#define UVD_BASE_INST0_SEG30
+#define UVD_BASE_INST0_SEG40
+
+#define SOC15_REG_ADDR(reg)(UVD_BASE_INST0_SEG1 + reg)
+
+#define COND0  0
+#define COND1  1
+#define COND2  2

[Mesa-dev] [PATCH 03/15] radeon/vcn: move radeon decoder define to header file

[boyuan.zhang]

From: Boyuan Zhang 

Move radeon_decoder definition from "radeon_vcn_dec.c" to "radeon_vcn_dec.h",
so that it can be included by other files later.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 31 
 src/gallium/drivers/radeon/radeon_vcn_dec.h | 32 +
 2 files changed, 32 insertions(+), 31 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index c2e22048ce..fbfef6d273 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -51,42 +51,11 @@
 #define RDECODE_GPCOM_VCPU_DATA1   0x20714
 #define RDECODE_ENGINE_CNTL0x20718
 
-#define NUM_BUFFERS4
 #define NUM_MPEG2_REFS 6
 #define NUM_H264_REFS  17
 #define NUM_VC1_REFS   5
 #define NUM_VP9_REFS   8
 
-struct radeon_decoder {
-   struct pipe_video_codec base;
-
-   unsignedstream_handle;
-   unsignedstream_type;
-   unsignedframe_number;
-
-   struct pipe_screen  *screen;
-   struct radeon_winsys*ws;
-   struct radeon_cmdbuf*cs;
-
-   void*msg;
-   uint32_t*fb;
-   uint8_t *it;
-   uint8_t *probs;
-   void*bs_ptr;
-
-   struct rvid_buffer  msg_fb_it_probs_buffers[NUM_BUFFERS];
-   struct rvid_buffer  bs_buffers[NUM_BUFFERS];
-   struct rvid_buffer  dpb;
-   struct rvid_buffer  ctx;
-   struct rvid_buffer  sessionctx;
-
-   unsignedbs_size;
-   unsignedcur_buffer;
-   void*render_pic_list[16];
-   boolshow_frame;
-   unsignedref_idx;
-};
-
 static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
struct pipe_h264_picture_desc *pic)
 {
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index 7a07ad0637..c6c2a933cc 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -108,6 +108,8 @@
 
 #define RDECODE_SPS_INFO_H264_EXTENSION_SUPPORT_FLAG_SHIFT 7
 
+#define NUM_BUFFERS4
+
 #define RDECODE_VP9_PROBS_DATA_SIZE2304
 
 /* VP9 Frame header flags */
@@ -639,6 +641,36 @@ typedef struct rvcn_dec_vp9_probs_segment_s {
 };
 } rvcn_dec_vp9_probs_segment_t;
 
+struct radeon_decoder {
+   struct pipe_video_codec base;
+
+   unsignedstream_handle;
+   unsignedstream_type;
+   unsignedframe_number;
+
+   struct pipe_screen  *screen;
+   struct radeon_winsys*ws;
+   struct radeon_cmdbuf*cs;
+
+   void*msg;
+   uint32_t*fb;
+   uint8_t *it;
+   uint8_t *probs;
+   void*bs_ptr;
+
+   struct rvid_buffer  msg_fb_it_probs_buffers[NUM_BUFFERS];
+   struct rvid_buffer  bs_buffers[NUM_BUFFERS];
+   struct rvid_buffer  dpb;
+   struct rvid_buffer  ctx;
+   struct rvid_buffer  sessionctx;
+
+   unsignedbs_size;
+   unsignedcur_buffer;
+   void*render_pic_list[16];
+   boolshow_frame;
+   unsignedref_idx;
+};
+
 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templat);
 
-- 
2.17.1

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[Mesa-dev] [PATCH 02/15] meson: update required amdgpu version to 2.4.95

[boyuan.zhang]

From: Boyuan Zhang 

VCN jpeg requires new hw ip

Signed-off-by: Boyuan Zhang 
---
 meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index 002ce35a60..35e3e934a3 100644
--- a/meson.build
+++ b/meson.build
@@ -1108,7 +1108,7 @@ dep_libdrm_etnaviv = null_dep
 dep_libdrm_freedreno = null_dep
 dep_libdrm_intel = null_dep
 
-_drm_amdgpu_ver = '2.4.93'
+_drm_amdgpu_ver = '2.4.95'
 _drm_radeon_ver = '2.4.71'
 _drm_nouveau_ver = '2.4.66'
 _drm_etnaviv_ver = '2.4.89'
-- 
2.17.1

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[Mesa-dev] [PATCH 01/15] configure.ac: update libdrm amdgpu version to 2.4.95

[boyuan.zhang]

From: Boyuan Zhang 

VCN jpeg requires new hw ip

Signed-off-by: Boyuan Zhang 
---
 configure.ac | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index 520948b051..5fd7d8510d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -74,7 +74,7 @@ AC_SUBST([OPENCL_VERSION])
 # in the first entry.
 LIBDRM_REQUIRED=2.4.75
 LIBDRM_RADEON_REQUIRED=2.4.71
-LIBDRM_AMDGPU_REQUIRED=2.4.93
+LIBDRM_AMDGPU_REQUIRED=2.4.95
 LIBDRM_INTEL_REQUIRED=2.4.75
 LIBDRM_NVVIEUX_REQUIRED=2.4.66
 LIBDRM_NOUVEAU_REQUIRED=2.4.66
-- 
2.17.1

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[Mesa-dev] [PATCH] st/va: use provided sizes and coords for vlVaGetImage

[boyuan.zhang]

From: Boyuan Zhang 

vlVaGetImage should respect the width, height, and coordinates x and y that
passed in. Therefore, pipe_box should be created with the passed in values
instead of surface width/height.

v2: add input size check, return error when size out of bounds
v3: fix the size check for vaimage
v4: add size adjustment for x and y coordinates

Signed-off-by: Boyuan Zhang 
Cc: "18.2" 
Reviewed-by: Leo Liu 
---
 src/gallium/state_trackers/va/image.c | 31 ---
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/src/gallium/state_trackers/va/image.c 
b/src/gallium/state_trackers/va/image.c
index 3f892c9..807fc83 100644
--- a/src/gallium/state_trackers/va/image.c
+++ b/src/gallium/state_trackers/va/image.c
@@ -353,6 +353,23 @@ vlVaGetImage(VADriverContextP ctx, VASurfaceID surface, 
int x, int y,
   return VA_STATUS_ERROR_INVALID_IMAGE;
}
 
+   if (x < 0 || y < 0) {
+  mtx_unlock(>mutex);
+  return VA_STATUS_ERROR_INVALID_PARAMETER;
+   }
+
+   if (x + width > surf->templat.width ||
+   y + height > surf->templat.height) {
+  mtx_unlock(>mutex);
+  return VA_STATUS_ERROR_INVALID_PARAMETER;
+   }
+
+   if (width > vaimage->width ||
+   height > vaimage->height) {
+  mtx_unlock(>mutex);
+  return VA_STATUS_ERROR_INVALID_PARAMETER;
+   }
+
img_buf = handle_table_get(drv->htab, vaimage->buf);
if (!img_buf) {
   mtx_unlock(>mutex);
@@ -400,11 +417,19 @@ vlVaGetImage(VADriverContextP ctx, VASurfaceID surface, 
int x, int y,
}
 
for (i = 0; i < vaimage->num_planes; i++) {
-  unsigned width, height;
+  unsigned box_w = align(width, 2);
+  unsigned box_h = align(height, 2);
+  unsigned box_x = x & ~1;
+  unsigned box_y = y & ~1;
   if (!views[i]) continue;
-  vlVaVideoSurfaceSize(surf, i, , );
+  vl_video_buffer_adjust_size(_w, _h, i,
+  surf->templat.chroma_format,
+  surf->templat.interlaced);
+  vl_video_buffer_adjust_size(_x, _y, i,
+  surf->templat.chroma_format,
+  surf->templat.interlaced);
   for (j = 0; j < views[i]->texture->array_size; ++j) {
- struct pipe_box box = {0, 0, j, width, height, 1};
+ struct pipe_box box = {box_x, box_y, j, box_w, box_h, 1};
  struct pipe_transfer *transfer;
  uint8_t *map;
  map = drv->pipe->transfer_map(drv->pipe, views[i]->texture, 0,
-- 
2.7.4

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[Mesa-dev] [PATCH] st/va: use provided sizes and coords for vlVaGetImage

[boyuan.zhang]

From: Boyuan Zhang 

vlVaGetImage should respect the width, height, and coordinates x and y that
passed in. Therefore, pipe_box should be created with the passed in values
instead of surface width/height.

v2: add input size check, return error when size out of bounds
v3: fix the size check for vaimage

Signed-off-by: Boyuan Zhang 
Cc: "18.2" 
Reviewed-by: Leo Liu 
---
 src/gallium/state_trackers/va/image.c | 26 +++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/src/gallium/state_trackers/va/image.c 
b/src/gallium/state_trackers/va/image.c
index 3f892c9..71d2f49 100644
--- a/src/gallium/state_trackers/va/image.c
+++ b/src/gallium/state_trackers/va/image.c
@@ -353,6 +353,23 @@ vlVaGetImage(VADriverContextP ctx, VASurfaceID surface, 
int x, int y,
   return VA_STATUS_ERROR_INVALID_IMAGE;
}
 
+   if (x < 0 || y < 0) {
+  mtx_unlock(>mutex);
+  return VA_STATUS_ERROR_INVALID_PARAMETER;
+   }
+
+   if (x + width > surf->templat.width ||
+   y + height > surf->templat.height) {
+  mtx_unlock(>mutex);
+  return VA_STATUS_ERROR_INVALID_PARAMETER;
+   }
+
+   if (width > vaimage->width ||
+   height > vaimage->height) {
+  mtx_unlock(>mutex);
+  return VA_STATUS_ERROR_INVALID_PARAMETER;
+   }
+
img_buf = handle_table_get(drv->htab, vaimage->buf);
if (!img_buf) {
   mtx_unlock(>mutex);
@@ -400,11 +417,14 @@ vlVaGetImage(VADriverContextP ctx, VASurfaceID surface, 
int x, int y,
}
 
for (i = 0; i < vaimage->num_planes; i++) {
-  unsigned width, height;
+  unsigned w = align(width, 2);
+  unsigned h = align(height, 2);
   if (!views[i]) continue;
-  vlVaVideoSurfaceSize(surf, i, , );
+  vl_video_buffer_adjust_size(, , i,
+  surf->templat.chroma_format,
+  surf->templat.interlaced);
   for (j = 0; j < views[i]->texture->array_size; ++j) {
- struct pipe_box box = {0, 0, j, width, height, 1};
+ struct pipe_box box = {x, y, j, w, h, 1};
  struct pipe_transfer *transfer;
  uint8_t *map;
  map = drv->pipe->transfer_map(drv->pipe, views[i]->texture, 0,
-- 
2.7.4

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[Mesa-dev] [PATCH] st/va: use provided sizes and coords for vlVaGetImage

[boyuan.zhang]

From: Boyuan Zhang 

vlVaGetImage should respect the width, height, and coordinates x and y that
passed in. Therefore, pipe_box should be created with the passed in values
instead of surface width/height.

v2: add input size check, return error when size out of bounds

Signed-off-by: Boyuan Zhang 
Cc: "18.2" 
Reviewed-by: Leo Liu 
---
 src/gallium/state_trackers/va/image.c | 26 +++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/src/gallium/state_trackers/va/image.c 
b/src/gallium/state_trackers/va/image.c
index 3f892c9..449ae86 100644
--- a/src/gallium/state_trackers/va/image.c
+++ b/src/gallium/state_trackers/va/image.c
@@ -353,6 +353,23 @@ vlVaGetImage(VADriverContextP ctx, VASurfaceID surface, 
int x, int y,
   return VA_STATUS_ERROR_INVALID_IMAGE;
}
 
+   if (x < 0 || y < 0) {
+  mtx_unlock(>mutex);
+  return VA_STATUS_ERROR_INVALID_PARAMETER;
+   }
+
+   if (x + width > surf->templat.width ||
+   y + height > surf->templat.height) {
+  mtx_unlock(>mutex);
+  return VA_STATUS_ERROR_INVALID_PARAMETER;
+   }
+
+   if (x + width > vaimage->width ||
+   y + height > vaimage->height) {
+  mtx_unlock(>mutex);
+  return VA_STATUS_ERROR_INVALID_PARAMETER;
+   }
+
img_buf = handle_table_get(drv->htab, vaimage->buf);
if (!img_buf) {
   mtx_unlock(>mutex);
@@ -400,11 +417,14 @@ vlVaGetImage(VADriverContextP ctx, VASurfaceID surface, 
int x, int y,
}
 
for (i = 0; i < vaimage->num_planes; i++) {
-  unsigned width, height;
+  unsigned w = align(width, 2);
+  unsigned h = align(height, 2);
   if (!views[i]) continue;
-  vlVaVideoSurfaceSize(surf, i, , );
+  vl_video_buffer_adjust_size(, , i,
+  surf->templat.chroma_format,
+  surf->templat.interlaced);
   for (j = 0; j < views[i]->texture->array_size; ++j) {
- struct pipe_box box = {0, 0, j, width, height, 1};
+ struct pipe_box box = {x, y, j, w, h, 1};
  struct pipe_transfer *transfer;
  uint8_t *map;
  map = drv->pipe->transfer_map(drv->pipe, views[i]->texture, 0,
-- 
2.7.4

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[Mesa-dev] [PATCH] st/va: use provided sizes and coords for getimage

[boyuan.zhang]

From: Boyuan Zhang 

vlVaGetImage should respect the width, height, and coordinates x and y that
passed in. Therefore, pipe_box should be created with the passed in values
instead of surface width/height. 

Signed-off-by: Boyuan Zhang 
---
 src/gallium/state_trackers/va/image.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/gallium/state_trackers/va/image.c 
b/src/gallium/state_trackers/va/image.c
index 3f892c9..c9f6f18 100644
--- a/src/gallium/state_trackers/va/image.c
+++ b/src/gallium/state_trackers/va/image.c
@@ -400,11 +400,14 @@ vlVaGetImage(VADriverContextP ctx, VASurfaceID surface, 
int x, int y,
}
 
for (i = 0; i < vaimage->num_planes; i++) {
-  unsigned width, height;
+  unsigned w = align(width, 2);
+  unsigned h = align(height, 2);
   if (!views[i]) continue;
-  vlVaVideoSurfaceSize(surf, i, , );
+  vl_video_buffer_adjust_size(, , i,
+  surf->templat.chroma_format,
+  surf->templat.interlaced);
   for (j = 0; j < views[i]->texture->array_size; ++j) {
- struct pipe_box box = {0, 0, j, width, height, 1};
+ struct pipe_box box = {x, y, j, w, h, 1};
  struct pipe_transfer *transfer;
  uint8_t *map;
  map = drv->pipe->transfer_map(drv->pipe, views[i]->texture, 0,
-- 
2.7.4

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[Mesa-dev] [PATCH] radeon/vce: use switch to convert profile idc

[boyuan.zhang]

From: Boyuan Zhang 

The previous array logic for converting pipe video profile to profile idc
relies on the order of pipe_video_profile enum defines. Adding new profile
to enum defines may break the logic. Therefore, it's better to use switch
helper function to acheive the same goal.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vce.c   | 24 +++
 src/gallium/drivers/radeon/radeon_vce.h   |  3 +++
 .../drivers/radeon/radeon_vce_40_2_2.c|  5 +---
 src/gallium/drivers/radeon/radeon_vce_52.c|  5 +---
 4 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vce.c 
b/src/gallium/drivers/radeon/radeon_vce.c
index 8972253c7c..6b9f2ab37b 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -572,3 +572,27 @@ void si_vce_add_buffer(struct rvce_encoder *enc, struct 
pb_buffer *buf,
RVCE_CS(offset);
}
 }
+
+unsigned si_vce_get_profile_idc(enum pipe_video_profile profile)
+{
+   switch (profile) {
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE:
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
+   return 66;
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
+   return 77;
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_EXTENDED:
+   return 88;
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
+   return 100;
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH10:
+   return 110;
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH422:
+   return 122;
+   case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH444:
+   return 244;
+   default:
+   RVID_ERR("Unsupported profile! Use baseline profile 
instead.\n");
+   return 66;
+   }
+}
diff --git a/src/gallium/drivers/radeon/radeon_vce.h 
b/src/gallium/drivers/radeon/radeon_vce.h
index cf625e6fed..255a3bf200 100644
--- a/src/gallium/drivers/radeon/radeon_vce.h
+++ b/src/gallium/drivers/radeon/radeon_vce.h
@@ -453,4 +453,7 @@ void si_vce_50_get_param(struct rvce_encoder *enc,
 void si_vce_52_get_param(struct rvce_encoder *enc,
 struct pipe_h264_enc_picture_desc *pic);
 
+/* convert pipe video profile to profile idc */
+unsigned si_vce_get_profile_idc(enum pipe_video_profile profile);
+
 #endif
diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c 
b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
index 66b54dab25..925480e4af 100644
--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
@@ -38,8 +38,6 @@
 #include "radeon_video.h"
 #include "radeon_vce.h"
 
-static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
-
 static void session(struct rvce_encoder *enc)
 {
RVCE_BEGIN(0x0001); // session cmd
@@ -82,8 +80,7 @@ static void create(struct rvce_encoder *enc)
 
RVCE_BEGIN(0x0101); // create cmd
RVCE_CS(0x); // encUseCircularBuffer
-   RVCE_CS(profiles[enc->base.profile -
-   PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]); // encProfile
+   RVCE_CS(si_vce_get_profile_idc(enc->base.profile)); // encProfile
RVCE_CS(enc->base.level); // encLevel
RVCE_CS(0x); // encPicStructRestriction
RVCE_CS(enc->base.width); // encImageWidth
diff --git a/src/gallium/drivers/radeon/radeon_vce_52.c 
b/src/gallium/drivers/radeon/radeon_vce_52.c
index 421539c4bd..bf7c5d6ff2 100644
--- a/src/gallium/drivers/radeon/radeon_vce_52.c
+++ b/src/gallium/drivers/radeon/radeon_vce_52.c
@@ -38,8 +38,6 @@
 #include "radeon_video.h"
 #include "radeon_vce.h"
 
-static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
-
 static void get_rate_control_param(struct rvce_encoder *enc, struct 
pipe_h264_enc_picture_desc *pic)
 {
enc->enc_pic.rc.rc_method = pic->rate_ctrl.rate_ctrl_method;
@@ -172,8 +170,7 @@ static void create(struct rvce_encoder *enc)
 
RVCE_BEGIN(0x0101); // create cmd
RVCE_CS(enc->enc_pic.ec.enc_use_circular_buffer);
-   RVCE_CS(profiles[enc->base.profile -
-   PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]); // encProfile
+   RVCE_CS(si_vce_get_profile_idc(enc->base.profile)); // encProfile
RVCE_CS(enc->base.level); // encLevel
RVCE_CS(enc->enc_pic.ec.enc_pic_struct_restriction);
RVCE_CS(enc->base.width); // encImageWidth
-- 
2.17.1

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[Mesa-dev] [PATCH] vl: reorder H264 profiles

[boyuan.zhang]

From: Boyuan Zhang 

Fix the wrong h264 profiles order. Previously, the constrained baseline was
added in between baseline and main profiles, which breaked the logic in
radeon/vce when converting from pipe_video_profile to profile_idc

Signed-off-by: Boyuan Zhang 
---
 src/gallium/include/pipe/p_video_enums.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/include/pipe/p_video_enums.h 
b/src/gallium/include/pipe/p_video_enums.h
index b5b8b06228..260f47ea8a 100644
--- a/src/gallium/include/pipe/p_video_enums.h
+++ b/src/gallium/include/pipe/p_video_enums.h
@@ -55,8 +55,8 @@ enum pipe_video_profile
PIPE_VIDEO_PROFILE_VC1_SIMPLE,
PIPE_VIDEO_PROFILE_VC1_MAIN,
PIPE_VIDEO_PROFILE_VC1_ADVANCED,
-   PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE,
PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE,
+   PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE,
PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN,
PIPE_VIDEO_PROFILE_MPEG4_AVC_EXTENDED,
PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH,
-- 
2.17.1

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[Mesa-dev] [PATCH 06/13] radeon/vcn: add jpeg decode implementation

[boyuan.zhang]

From: Boyuan Zhang 

Add a new file to handle VCN Jpeg decode specific functions. Use Jpeg
specific cmd sending function in end_frame call.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/Makefile.sources  |  1 +
 src/gallium/drivers/radeon/meson.build   |  1 +
 src/gallium/drivers/radeon/radeon_vcn_dec.c  | 21 +++--
 src/gallium/drivers/radeon/radeon_vcn_dec.h  |  4 +
 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c | 99 
 5 files changed, 119 insertions(+), 7 deletions(-)
 create mode 100644 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index f8ee860..e3ee82c 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -10,6 +10,7 @@ C_SOURCES := \
r600_texture.c \
radeon_uvd.c \
radeon_uvd.h \
+   radeon_vcn_dec_jpeg.c \
radeon_vcn_dec.c \
radeon_vcn_dec.h \
radeon_vcn_enc_1_2.c \
diff --git a/src/gallium/drivers/radeon/meson.build 
b/src/gallium/drivers/radeon/meson.build
index 582a5ff..c984a75 100644
--- a/src/gallium/drivers/radeon/meson.build
+++ b/src/gallium/drivers/radeon/meson.build
@@ -33,6 +33,7 @@ files_libradeon = files(
   'radeon_vcn_enc_1_2.c',
   'radeon_vcn_enc.c',
   'radeon_vcn_enc.h',
+  'radeon_vcn_dec_jpeg.c',
   'radeon_vcn_dec.c',
   'radeon_vcn_dec.h',
   'radeon_uvd_enc_1_1.c',
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 30a8952..264abea 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -991,6 +991,10 @@ static unsigned calc_dpb_size(struct radeon_decoder *dec)
dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
break;
 
+   case PIPE_VIDEO_FORMAT_JPEG:
+   dpb_size = 0;
+   break;
+
default:
// something is missing here
assert(0);
@@ -1270,14 +1274,14 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
}
 
dpb_size = calc_dpb_size(dec);
-
-   if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {
-   RVID_ERR("Can't allocated dpb.\n");
-   goto error;
+   if (dpb_size) {
+   if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {
+   RVID_ERR("Can't allocated dpb.\n");
+   goto error;
+   }
+   si_vid_clear_buffer(context, >dpb);
}
 
-   si_vid_clear_buffer(context, >dpb);
-
if (dec->stream_type == RDECODE_CODEC_H264_PERF) {
unsigned ctx_size = calc_ctx_size_h264_perf(dec);
if (!si_vid_create_buffer(dec->screen, >ctx, ctx_size, 
PIPE_USAGE_DEFAULT)) {
@@ -1304,7 +1308,10 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
 
next_buffer(dec);
 
-   dec->send_cmd = send_cmd_dec;
+   if (stream_type == RDECODE_CODEC_JPEG)
+   dec->send_cmd = send_cmd_jpeg;
+   else
+   dec->send_cmd = send_cmd_dec;
 
return >base;
 
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index 05e4847..782eb65 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -627,6 +627,10 @@ void send_cmd_dec(struct radeon_decoder *dec,
  struct pipe_video_buffer *target,
  struct pipe_picture_desc *picture);
 
+void send_cmd_jpeg(struct radeon_decoder *dec,
+ struct pipe_video_buffer *target,
+ struct pipe_picture_desc *picture);
+
 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templat);
 
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
new file mode 100644
index 000..c52ed36
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
@@ -0,0 +1,99 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all 

[Mesa-dev] [PATCH 08/13] radeon/uvd: remove get mjpeg slice header

[boyuan.zhang]

From: Boyuan Zhang 

Move the previous get_mjpeg_slice_heaeder function and eoi from
"radeon/vcn" to "st/va".

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_uvd.c | 147 
 1 file changed, 147 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd.c 
b/src/gallium/drivers/radeon/radeon_uvd.c
index 78ced17..bff48ad 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -965,139 +965,6 @@ static struct ruvd_mpeg4 get_mpeg4_msg(struct 
ruvd_decoder *dec,
return result;
 }
 
-static void get_mjpeg_slice_header(struct ruvd_decoder *dec, struct 
pipe_mjpeg_picture_desc *pic)
-{
-   int size = 0, saved_size, len_pos, i;
-   uint16_t *bs;
-   uint8_t *buf = dec->bs_ptr;
-
-   /* SOI */
-   buf[size++] = 0xff;
-   buf[size++] = 0xd8;
-
-   /* DQT */
-   buf[size++] = 0xff;
-   buf[size++] = 0xdb;
-
-   len_pos = size++;
-   size++;
-
-   for (i = 0; i < 4; ++i) {
-   if (pic->quantization_table.load_quantiser_table[i] == 0)
-   continue;
-
-   buf[size++] = i;
-   memcpy((buf + size), 
>quantization_table.quantiser_table[i], 64);
-   size += 64;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - 4);
-
-   saved_size = size;
-
-   /* DHT */
-   buf[size++] = 0xff;
-   buf[size++] = 0xc4;
-
-   len_pos = size++;
-   size++;
-
-   for (i = 0; i < 2; ++i) {
-   if (pic->huffman_table.load_huffman_table[i] == 0)
-   continue;
-
-   buf[size++] = 0x00 | i;
-   memcpy((buf + size), >huffman_table.table[i].num_dc_codes, 
16);
-   size += 16;
-   memcpy((buf + size), >huffman_table.table[i].dc_values, 
12);
-   size += 12;
-   }
-
-   for (i = 0; i < 2; ++i) {
-   if (pic->huffman_table.load_huffman_table[i] == 0)
-   continue;
-
-   buf[size++] = 0x10 | i;
-   memcpy((buf + size), >huffman_table.table[i].num_ac_codes, 
16);
-   size += 16;
-   memcpy((buf + size), >huffman_table.table[i].ac_values, 
162);
-   size += 162;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   saved_size = size;
-
-   /* DRI */
-   if (pic->slice_parameter.restart_interval) {
-   buf[size++] = 0xff;
-   buf[size++] = 0xdd;
-   buf[size++] = 0x00;
-   buf[size++] = 0x04;
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->slice_parameter.restart_interval);
-   saved_size = ++size;
-   }
-
-   /* SOF */
-   buf[size++] = 0xff;
-   buf[size++] = 0xc0;
-
-   len_pos = size++;
-   size++;
-
-   buf[size++] = 0x08;
-
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->picture_parameter.picture_height);
-   size++;
-
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->picture_parameter.picture_width);
-   size++;
-
-   buf[size++] = pic->picture_parameter.num_components;
-
-   for (i = 0; i < pic->picture_parameter.num_components; ++i) {
-   buf[size++] = pic->picture_parameter.components[i].component_id;
-   buf[size++] = 
pic->picture_parameter.components[i].h_sampling_factor << 4 |
-   pic->picture_parameter.components[i].v_sampling_factor;
-   buf[size++] = 
pic->picture_parameter.components[i].quantiser_table_selector;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   saved_size = size;
-
-   /* SOS */
-   buf[size++] = 0xff;
-   buf[size++] = 0xda;
-
-   len_pos = size++;
-   size++;
-
-   buf[size++] = pic->slice_parameter.num_components;
-
-   for (i = 0; i < pic->slice_parameter.num_components; ++i) {
-   buf[size++] = 
pic->slice_parameter.components[i].component_selector;
-   buf[size++] = 
pic->slice_parameter.components[i].dc_table_selector << 4 |
-   pic->slice_parameter.components[i].ac_table_selector;
-   }
-
-   buf[size++] = 0x00;
-   buf[size++] = 0x3f;
-   buf[size++] = 0x00;
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   dec->bs_ptr += size;
-   dec->bs_size += size;
-}
-
 /**
  * destroy this video decoder
  */
@@ -1176,7 +1043,6 @@ static void ruvd_decode_bitstream(struct pipe_video_codec 
*decoder,
  const unsigned *sizes)
 {
struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
-   enum pipe_video_format format = 
u_reduce_video_profile(picture->profile);
unsigned i;
 
assert(decoder);
@@ -1184,16 +1050,10 @@ 

[Mesa-dev] [PATCH 07/13] st/va: get mjpeg slice header

[boyuan.zhang]

From: Boyuan Zhang 

Move the previous get_mjpeg_slice_heaeder function and eoi from
"radeon/vcn" to "st/va".

Signed-off-by: Boyuan Zhang 
---
 src/gallium/state_trackers/va/picture.c   |  13 ++-
 src/gallium/state_trackers/va/picture_mjpeg.c | 132 ++
 src/gallium/state_trackers/va/va_private.h|  11 +++
 3 files changed, 154 insertions(+), 2 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index f2e9ba8..af136fb 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -251,11 +251,12 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
 {
enum pipe_video_format format;
unsigned num_buffers = 0;
-   void * const *buffers[2];
-   unsigned sizes[2];
+   void * const *buffers[3];
+   unsigned sizes[3];
static const uint8_t start_code_h264[] = { 0x00, 0x00, 0x01 };
static const uint8_t start_code_h265[] = { 0x00, 0x00, 0x01 };
static const uint8_t start_code_vc1[] = { 0x00, 0x00, 0x01, 0x0d };
+   static const uint8_t eoi_jpeg[] = { 0xff, 0xd9 };
 
format = u_reduce_video_profile(context->templat.profile);
switch (format) {
@@ -293,6 +294,9 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
   sizes[num_buffers++] = context->mpeg4.start_code_size;
   break;
case PIPE_VIDEO_FORMAT_JPEG:
+  vlVaGetJpegSliceHeader(context);
+  buffers[num_buffers] = (void *)context->mjpeg.slice_header;
+  sizes[num_buffers++] = context->mjpeg.slice_header_size;
   break;
default:
   break;
@@ -302,6 +306,11 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
sizes[num_buffers] = buf->size;
++num_buffers;
 
+   if (format == PIPE_VIDEO_FORMAT_JPEG) {
+  buffers[num_buffers] = (void *const)_jpeg;
+  sizes[num_buffers++] = sizeof(eoi_jpeg);
+   }
+
if (context->needs_begin_frame) {
   context->decoder->begin_frame(context->decoder, context->target,
  >desc.base);
diff --git a/src/gallium/state_trackers/va/picture_mjpeg.c 
b/src/gallium/state_trackers/va/picture_mjpeg.c
index 396b743..f1292ea 100644
--- a/src/gallium/state_trackers/va/picture_mjpeg.c
+++ b/src/gallium/state_trackers/va/picture_mjpeg.c
@@ -114,3 +114,135 @@ void vlVaHandleSliceParameterBufferMJPEG(vlVaContext 
*context, vlVaBuffer *buf)
context->desc.mjpeg.slice_parameter.restart_interval = 
mjpeg->restart_interval;
context->desc.mjpeg.slice_parameter.num_mcus = mjpeg->num_mcus;
 }
+
+void vlVaGetJpegSliceHeader(vlVaContext *context)
+{
+   int size = 0, saved_size, len_pos, i;
+   uint16_t *bs;
+   uint8_t *p = context->mjpeg.slice_header;
+
+   /* SOI */
+   p[size++] = 0xff;
+   p[size++] = 0xd8;
+
+   /* DQT */
+   p[size++] = 0xff;
+   p[size++] = 0xdb;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 4; ++i) {
+  if (context->desc.mjpeg.quantization_table.load_quantiser_table[i] == 0)
+ continue;
+
+  p[size++] = i;
+  memcpy((p + size), 
>desc.mjpeg.quantization_table.quantiser_table[i], 64);
+  size += 64;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - 4);
+
+   saved_size = size;
+
+   /* DHT */
+   p[size++] = 0xff;
+   p[size++] = 0xc4;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 2; ++i) {
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x00 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_dc_codes, 16);
+  size += 16;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].dc_values, 12);
+  size += 12;
+   }
+
+   for (i = 0; i < 2; ++i) {
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x10 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_ac_codes, 16);
+  size += 16;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].ac_values, 162);
+  size += 162;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - saved_size - 2);
+
+   saved_size = size;
+
+   /* DRI */
+   if (context->desc.mjpeg.slice_parameter.restart_interval) {
+  p[size++] = 0xff;
+  p[size++] = 0xdd;
+  p[size++] = 0x00;
+  p[size++] = 0x04;
+  bs = (uint16_t*)[size++];
+  *bs = util_bswap16(context->desc.mjpeg.slice_parameter.restart_interval);
+  saved_size = ++size;
+   }
+
+   /* SOF */
+   p[size++] = 0xff;
+   p[size++] = 0xc0;
+
+   len_pos = size++;
+   size++;
+
+   p[size++] = 0x08;
+
+   bs = (uint16_t*)[size++];
+   *bs = util_bswap16(context->desc.mjpeg.picture_parameter.picture_height);
+   size++;
+
+   bs = (uint16_t*)[size++];
+   *bs = util_bswap16(context->desc.mjpeg.picture_parameter.picture_width);
+   size++;
+
+   p[size++] = context->desc.mjpeg.picture_parameter.num_components;
+
+   for (i = 0; i < context->desc.mjpeg.picture_parameter.num_components; ++i) 

[Mesa-dev] [PATCH 08/13] radeon/uvd: remove get mjpeg slice header

[boyuan.zhang]

From: Boyuan Zhang 

Move the previous get_mjpeg_slice_header function from radeon/vcn to st/va.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_uvd.c | 136 
 1 file changed, 136 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd.c 
b/src/gallium/drivers/radeon/radeon_uvd.c
index 78ced17..78575e7 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -965,139 +965,6 @@ static struct ruvd_mpeg4 get_mpeg4_msg(struct 
ruvd_decoder *dec,
return result;
 }
 
-static void get_mjpeg_slice_header(struct ruvd_decoder *dec, struct 
pipe_mjpeg_picture_desc *pic)
-{
-   int size = 0, saved_size, len_pos, i;
-   uint16_t *bs;
-   uint8_t *buf = dec->bs_ptr;
-
-   /* SOI */
-   buf[size++] = 0xff;
-   buf[size++] = 0xd8;
-
-   /* DQT */
-   buf[size++] = 0xff;
-   buf[size++] = 0xdb;
-
-   len_pos = size++;
-   size++;
-
-   for (i = 0; i < 4; ++i) {
-   if (pic->quantization_table.load_quantiser_table[i] == 0)
-   continue;
-
-   buf[size++] = i;
-   memcpy((buf + size), 
>quantization_table.quantiser_table[i], 64);
-   size += 64;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - 4);
-
-   saved_size = size;
-
-   /* DHT */
-   buf[size++] = 0xff;
-   buf[size++] = 0xc4;
-
-   len_pos = size++;
-   size++;
-
-   for (i = 0; i < 2; ++i) {
-   if (pic->huffman_table.load_huffman_table[i] == 0)
-   continue;
-
-   buf[size++] = 0x00 | i;
-   memcpy((buf + size), >huffman_table.table[i].num_dc_codes, 
16);
-   size += 16;
-   memcpy((buf + size), >huffman_table.table[i].dc_values, 
12);
-   size += 12;
-   }
-
-   for (i = 0; i < 2; ++i) {
-   if (pic->huffman_table.load_huffman_table[i] == 0)
-   continue;
-
-   buf[size++] = 0x10 | i;
-   memcpy((buf + size), >huffman_table.table[i].num_ac_codes, 
16);
-   size += 16;
-   memcpy((buf + size), >huffman_table.table[i].ac_values, 
162);
-   size += 162;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   saved_size = size;
-
-   /* DRI */
-   if (pic->slice_parameter.restart_interval) {
-   buf[size++] = 0xff;
-   buf[size++] = 0xdd;
-   buf[size++] = 0x00;
-   buf[size++] = 0x04;
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->slice_parameter.restart_interval);
-   saved_size = ++size;
-   }
-
-   /* SOF */
-   buf[size++] = 0xff;
-   buf[size++] = 0xc0;
-
-   len_pos = size++;
-   size++;
-
-   buf[size++] = 0x08;
-
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->picture_parameter.picture_height);
-   size++;
-
-   bs = (uint16_t*)[size++];
-   *bs = util_bswap16(pic->picture_parameter.picture_width);
-   size++;
-
-   buf[size++] = pic->picture_parameter.num_components;
-
-   for (i = 0; i < pic->picture_parameter.num_components; ++i) {
-   buf[size++] = pic->picture_parameter.components[i].component_id;
-   buf[size++] = 
pic->picture_parameter.components[i].h_sampling_factor << 4 |
-   pic->picture_parameter.components[i].v_sampling_factor;
-   buf[size++] = 
pic->picture_parameter.components[i].quantiser_table_selector;
-   }
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   saved_size = size;
-
-   /* SOS */
-   buf[size++] = 0xff;
-   buf[size++] = 0xda;
-
-   len_pos = size++;
-   size++;
-
-   buf[size++] = pic->slice_parameter.num_components;
-
-   for (i = 0; i < pic->slice_parameter.num_components; ++i) {
-   buf[size++] = 
pic->slice_parameter.components[i].component_selector;
-   buf[size++] = 
pic->slice_parameter.components[i].dc_table_selector << 4 |
-   pic->slice_parameter.components[i].ac_table_selector;
-   }
-
-   buf[size++] = 0x00;
-   buf[size++] = 0x3f;
-   buf[size++] = 0x00;
-
-   bs = (uint16_t*)[len_pos];
-   *bs = util_bswap16(size - saved_size - 2);
-
-   dec->bs_ptr += size;
-   dec->bs_size += size;
-}
-
 /**
  * destroy this video decoder
  */
@@ -1184,9 +1051,6 @@ static void ruvd_decode_bitstream(struct pipe_video_codec 
*decoder,
if (!dec->bs_ptr)
return;
 
-   if (format == PIPE_VIDEO_FORMAT_JPEG)
-   get_mjpeg_slice_header(dec, (struct 
pipe_mjpeg_picture_desc*)picture);
-
for (i = 0; i < num_buffers; ++i) {
struct rvid_buffer *buf = 

[Mesa-dev] [PATCH 06/13] radeon/vcn: add jpeg decode implementation

[boyuan.zhang]

From: Boyuan Zhang 

Add a new file to handle VCN Jpeg decode specific functions. Use Jpeg
specific cmd sending function in end_frame call.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/Makefile.sources  |  1 +
 src/gallium/drivers/radeon/meson.build   |  1 +
 src/gallium/drivers/radeon/radeon_vcn_dec.c  | 32 ++--
 src/gallium/drivers/radeon/radeon_vcn_dec.h  |  4 +
 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c | 99 
 5 files changed, 130 insertions(+), 7 deletions(-)
 create mode 100644 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index f8ee860..e3ee82c 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -10,6 +10,7 @@ C_SOURCES := \
r600_texture.c \
radeon_uvd.c \
radeon_uvd.h \
+   radeon_vcn_dec_jpeg.c \
radeon_vcn_dec.c \
radeon_vcn_dec.h \
radeon_vcn_enc_1_2.c \
diff --git a/src/gallium/drivers/radeon/meson.build 
b/src/gallium/drivers/radeon/meson.build
index 582a5ff..c984a75 100644
--- a/src/gallium/drivers/radeon/meson.build
+++ b/src/gallium/drivers/radeon/meson.build
@@ -33,6 +33,7 @@ files_libradeon = files(
   'radeon_vcn_enc_1_2.c',
   'radeon_vcn_enc.c',
   'radeon_vcn_enc.h',
+  'radeon_vcn_dec_jpeg.c',
   'radeon_vcn_dec.c',
   'radeon_vcn_dec.h',
   'radeon_uvd_enc_1_1.c',
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 30a8952..861a40e 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -991,6 +991,10 @@ static unsigned calc_dpb_size(struct radeon_decoder *dec)
dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
break;
 
+   case PIPE_VIDEO_FORMAT_JPEG:
+   dpb_size = 0;
+   break;
+
default:
// something is missing here
assert(0);
@@ -1078,6 +1082,7 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,
  const unsigned *sizes)
 {
struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
+   enum pipe_video_format format = 
u_reduce_video_profile(picture->profile);
unsigned i;
 
assert(decoder);
@@ -1089,6 +1094,9 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,
struct rvid_buffer *buf = >bs_buffers[dec->cur_buffer];
unsigned new_size = dec->bs_size + sizes[i];
 
+   if (format == PIPE_VIDEO_FORMAT_JPEG)
+   new_size += 2; /* save for EOI */
+
if (new_size > buf->res->buf->size) {
dec->ws->buffer_unmap(buf->res->buf);
if (!si_vid_resize_buffer(dec->screen, dec->cs, buf, 
new_size)) {
@@ -1108,6 +1116,13 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,
dec->bs_size += sizes[i];
dec->bs_ptr += sizes[i];
}
+
+   if (format == PIPE_VIDEO_FORMAT_JPEG) {
+   ((uint8_t *)dec->bs_ptr)[0] = 0xff; /* EOI */
+   ((uint8_t *)dec->bs_ptr)[1] = 0xd9;
+   dec->bs_size += 2;
+   dec->bs_ptr += 2;
+   }
 }
 
 /**
@@ -1270,14 +1285,14 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
}
 
dpb_size = calc_dpb_size(dec);
-
-   if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {
-   RVID_ERR("Can't allocated dpb.\n");
-   goto error;
+   if (dpb_size) {
+   if (!si_vid_create_buffer(dec->screen, >dpb, dpb_size, 
PIPE_USAGE_DEFAULT)) {
+   RVID_ERR("Can't allocated dpb.\n");
+   goto error;
+   }
+   si_vid_clear_buffer(context, >dpb);
}
 
-   si_vid_clear_buffer(context, >dpb);
-
if (dec->stream_type == RDECODE_CODEC_H264_PERF) {
unsigned ctx_size = calc_ctx_size_h264_perf(dec);
if (!si_vid_create_buffer(dec->screen, >ctx, ctx_size, 
PIPE_USAGE_DEFAULT)) {
@@ -1304,7 +1319,10 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
 
next_buffer(dec);
 
-   dec->send_cmd = send_cmd_dec;
+   if (stream_type == RDECODE_CODEC_JPEG)
+   dec->send_cmd = send_cmd_jpeg;
+   else
+   dec->send_cmd = send_cmd_dec;
 
return >base;
 
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index 05e4847..782eb65 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -627,6 +627,10 @@ void send_cmd_dec(struct radeon_decoder *dec,
  struct 

[Mesa-dev] [PATCH 09/13] radeon/vcn: implement jpeg bitstream buffer cmd

[boyuan.zhang]

From: Boyuan Zhang 

Implement jpeg bitstream buffer cmd by programming registers directly,
since there is no firmware for VCN Jpeg decode.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c | 46 +++-
 1 file changed, 45 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
index c52ed36..d46581c 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
@@ -59,12 +59,56 @@ static struct pb_buffer 
*radeon_jpeg_get_decode_param(struct radeon_decoder *dec
return luma->resource.buf;
 }
 
+/* add a new set register command to the IB */
+static void set_reg_jpeg(struct radeon_decoder *dec, unsigned reg,
+unsigned cond, unsigned type, uint32_t val)
+{
+   radeon_emit(dec->cs, RDECODE_PKTJ(SOC15_REG_ADDR(reg), cond, type));
+   radeon_emit(dec->cs, val);
+}
+
 /* send a bitstream buffer command */
 static void send_cmd_bitstream(struct radeon_decoder *dec,
 struct pb_buffer* buf, uint32_t off,
 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
 {
-   /* TODO */
+   uint64_t addr;
+
+   // jpeg soft reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 1);
+
+   // ensuring the Reset is asserted in SCLK domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C2);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x01400200);
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // wait mem
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0);
+
+   // ensuring the Reset is de-asserted in SCLK domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (0 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, RADEON_PRIO_UVD);
+   addr = dec->ws->buffer_get_virtual_address(buf);
+   addr = addr + off;
+
+   // set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer 
address
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0, 
(addr >> 32));
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0, 
addr);
+
+   // set jpeg_rb_base
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_BASE, COND0, TYPE0, 0);
+
+   // set jpeg_rb_base
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFF0);
+
+   // set jpeg_rb_wptr
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_WPTR, COND0, TYPE0, (dec->jpg.bsd_size 
>> 2));
 }
 
 /* send a target buffer command */
-- 
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[Mesa-dev] [PATCH 13/13] radeonsi: enable vcn jpeg decode for raven

[boyuan.zhang]

From: Boyuan Zhang 

Enable vcn jpeg decode for raven.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeonsi/si_get.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index fc2be33..de587bb 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -640,6 +640,8 @@ static int si_get_video_param(struct pipe_screen *screen,
return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
return false;
case PIPE_VIDEO_FORMAT_JPEG:
+   if (sscreen->info.family == CHIP_RAVEN)
+   return true;
if (sscreen->info.family < CHIP_CARRIZO || 
sscreen->info.family >= CHIP_VEGA10)
return false;
if (!(sscreen->info.drm_major == 3 && 
sscreen->info.drm_minor >= 19)) {
-- 
2.7.4

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[Mesa-dev] [PATCH 10/13] radeon/vcn: implement jpeg target buffer cmd

[boyuan.zhang]

From: Boyuan Zhang 

Implement jpeg target buffer cmd by programming registers directly,
since there is no firmware for VCN Jpeg decode.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c | 73 +++-
 1 file changed, 72 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
index d46581c..7ab4e67 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
@@ -116,7 +116,78 @@ static void send_cmd_target(struct radeon_decoder *dec,
 struct pb_buffer* buf, uint32_t off,
 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
 {
-   /* TODO */
+   uint64_t addr;
+
+   set_reg_jpeg(dec, mmUVD_JPEG_PITCH, COND0, TYPE0, (dec->jpg.dt_pitch >> 
4));
+   set_reg_jpeg(dec, mmUVD_JPEG_UV_PITCH, COND0, TYPE0, 
((dec->jpg.dt_uv_pitch * 2) >> 4));
+
+   set_reg_jpeg(dec, mmUVD_JPEG_TILING_CTRL, COND0, TYPE0, 0);
+   set_reg_jpeg(dec, mmUVD_JPEG_UV_TILING_CTRL, COND0, TYPE0, 0);
+
+   dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, RADEON_PRIO_UVD);
+   addr = dec->ws->buffer_get_virtual_address(buf);
+   addr = addr + off;
+
+   // set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer 
address
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0, 
(addr >> 32));
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0, 
addr);
+
+   // set output buffer data address
+   set_reg_jpeg(dec, mmUVD_JPEG_INDEX, COND0, TYPE0, 0);
+   set_reg_jpeg(dec, mmUVD_JPEG_DATA, COND0, TYPE0, 
dec->jpg.dt_luma_top_offset);
+   set_reg_jpeg(dec, mmUVD_JPEG_INDEX, COND0, TYPE0, 1);
+   set_reg_jpeg(dec, mmUVD_JPEG_DATA, COND0, TYPE0, 
dec->jpg.dt_chroma_top_offset);
+   set_reg_jpeg(dec, mmUVD_JPEG_TIER_CNTL2, COND0, TYPE3, 0);
+
+   // set output buffer read pointer
+   set_reg_jpeg(dec, mmUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0);
+
+   // enable error interrupts
+   set_reg_jpeg(dec, mmUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFE);
+
+   // start engine command
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0x6);
+
+   // wait for job completion, wait for job JBSI fetch done
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (dec->jpg.bsd_size >> 
2));
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C2);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x01400200);
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_RPTR, COND0, TYPE3, 0x);
+
+   // wait for job jpeg outbuf idle
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x);
+   set_reg_jpeg(dec, mmUVD_JPEG_OUTBUF_WPTR, COND0, TYPE3, 0x0001);
+
+   // stop engine
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0x4);
+
+   // asserting jpeg lmi drop
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x0005);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 23 | 1 << 0));
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE1, 0);
+
+   // asserting jpeg reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 1);
+
+   // ensure reset is asserted in sclk domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // de-assert jpeg reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0);
+
+   // ensure reset is de-asserted in sclk domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (0 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // de-asserting jpeg lmi drop
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x0005);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0);
 }
 
 /**
-- 
2.7.4

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[Mesa-dev] [PATCH 12/13] winsys/amdgpu: add vcn jpeg cs support

[boyuan.zhang]

From: Boyuan Zhang 

Add vcn jpeg cs support, align cs by no-op.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index a3feeb9..5092f49 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -840,6 +840,10 @@ static bool amdgpu_init_cs_context(struct 
amdgpu_cs_context *cs,
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_ENC;
   break;
 
+   case RING_VCN_JPEG:
+  cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_JPEG;
+  break;
+
default:
case RING_GFX:
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_GFX;
@@ -1545,6 +1549,14 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
   while (rcs->current.cdw & 15)
  radeon_emit(rcs, 0x8000); /* type2 nop packet */
   break;
+   case RING_VCN_JPEG:
+  if (rcs->current.cdw % 2)
+ assert(0);
+  while (rcs->current.cdw & 15) {
+ radeon_emit(rcs, 0x6000); /* nop packet */
+ radeon_emit(rcs, 0x);
+  }
+  break;
case RING_VCN_DEC:
   while (rcs->current.cdw & 15)
  radeon_emit(rcs, 0x81ff); /* nop packet */
-- 
2.7.4

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[Mesa-dev] [PATCH 11/13] amd/common: add vcn jpeg ip info query

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/amd/common/ac_gpu_info.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 73fc362..a1db3b9 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -99,7 +99,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
struct amdgpu_buffer_size_alignments alignment_info = {};
struct amdgpu_heap_info vram, vram_vis, gtt;
struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
-   struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
+   struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, 
vcn_jpeg = {};
struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
struct amdgpu_gds_resource_info gds = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature 
= 0;
@@ -199,6 +199,14 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
}
 
+   if (info->drm_major == 3 && info->drm_minor >= 17) {
+   r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, 
_jpeg);
+   if (r) {
+   fprintf(stderr, "amdgpu: 
amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
+   return false;
+   }
+   }
+
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
>me_fw_version,
>me_fw_feature);
@@ -301,7 +309,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->max_se = amdinfo->num_shader_engines;
info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
info->has_hw_decode =
-   (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
+   (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
+   (vcn_jpeg.available_rings != 0);
info->uvd_fw_version =
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
@@ -368,6 +377,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
ib_align = MAX2(ib_align, vce.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
+   ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
assert(ib_align);
info->ib_start_alignment = ib_align;
 
-- 
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[Mesa-dev] [PATCH 07/13] st/va: get mjpeg slice header

[boyuan.zhang]

From: Boyuan Zhang 

Move the previous get_mjpeg_slice_header function from radeon/vcn to st/va.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/state_trackers/va/picture.c   |   3 +
 src/gallium/state_trackers/va/picture_mjpeg.c | 132 ++
 src/gallium/state_trackers/va/va_private.h|   3 +
 3 files changed, 138 insertions(+)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index f2e9ba8..d326ed4 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -293,6 +293,9 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
   sizes[num_buffers++] = context->mpeg4.start_code_size;
   break;
case PIPE_VIDEO_FORMAT_JPEG:
+  vlVaGetJpegSliceHeader(context);
+  buffers[num_buffers] = (void *)context->mjpeg.slice_header;
+  sizes[num_buffers++] = context->mjpeg.slice_header_size;
   break;
default:
   break;
diff --git a/src/gallium/state_trackers/va/picture_mjpeg.c 
b/src/gallium/state_trackers/va/picture_mjpeg.c
index 396b743..f1292ea 100644
--- a/src/gallium/state_trackers/va/picture_mjpeg.c
+++ b/src/gallium/state_trackers/va/picture_mjpeg.c
@@ -114,3 +114,135 @@ void vlVaHandleSliceParameterBufferMJPEG(vlVaContext 
*context, vlVaBuffer *buf)
context->desc.mjpeg.slice_parameter.restart_interval = 
mjpeg->restart_interval;
context->desc.mjpeg.slice_parameter.num_mcus = mjpeg->num_mcus;
 }
+
+void vlVaGetJpegSliceHeader(vlVaContext *context)
+{
+   int size = 0, saved_size, len_pos, i;
+   uint16_t *bs;
+   uint8_t *p = context->mjpeg.slice_header;
+
+   /* SOI */
+   p[size++] = 0xff;
+   p[size++] = 0xd8;
+
+   /* DQT */
+   p[size++] = 0xff;
+   p[size++] = 0xdb;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 4; ++i) {
+  if (context->desc.mjpeg.quantization_table.load_quantiser_table[i] == 0)
+ continue;
+
+  p[size++] = i;
+  memcpy((p + size), 
>desc.mjpeg.quantization_table.quantiser_table[i], 64);
+  size += 64;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - 4);
+
+   saved_size = size;
+
+   /* DHT */
+   p[size++] = 0xff;
+   p[size++] = 0xc4;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 2; ++i) {
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x00 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_dc_codes, 16);
+  size += 16;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].dc_values, 12);
+  size += 12;
+   }
+
+   for (i = 0; i < 2; ++i) {
+  if (context->desc.mjpeg.huffman_table.load_huffman_table[i] == 0)
+ continue;
+
+  p[size++] = 0x10 | i;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].num_ac_codes, 16);
+  size += 16;
+  memcpy((p + size), 
>desc.mjpeg.huffman_table.table[i].ac_values, 162);
+  size += 162;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - saved_size - 2);
+
+   saved_size = size;
+
+   /* DRI */
+   if (context->desc.mjpeg.slice_parameter.restart_interval) {
+  p[size++] = 0xff;
+  p[size++] = 0xdd;
+  p[size++] = 0x00;
+  p[size++] = 0x04;
+  bs = (uint16_t*)[size++];
+  *bs = util_bswap16(context->desc.mjpeg.slice_parameter.restart_interval);
+  saved_size = ++size;
+   }
+
+   /* SOF */
+   p[size++] = 0xff;
+   p[size++] = 0xc0;
+
+   len_pos = size++;
+   size++;
+
+   p[size++] = 0x08;
+
+   bs = (uint16_t*)[size++];
+   *bs = util_bswap16(context->desc.mjpeg.picture_parameter.picture_height);
+   size++;
+
+   bs = (uint16_t*)[size++];
+   *bs = util_bswap16(context->desc.mjpeg.picture_parameter.picture_width);
+   size++;
+
+   p[size++] = context->desc.mjpeg.picture_parameter.num_components;
+
+   for (i = 0; i < context->desc.mjpeg.picture_parameter.num_components; ++i) {
+  p[size++] = 
context->desc.mjpeg.picture_parameter.components[i].component_id;
+  p[size++] = 
context->desc.mjpeg.picture_parameter.components[i].h_sampling_factor << 4 |
+ 
context->desc.mjpeg.picture_parameter.components[i].v_sampling_factor;
+  p[size++] = 
context->desc.mjpeg.picture_parameter.components[i].quantiser_table_selector;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - saved_size - 2);
+
+   saved_size = size;
+
+   /* SOS */
+   p[size++] = 0xff;
+   p[size++] = 0xda;
+
+   len_pos = size++;
+   size++;
+
+   p[size++] = context->desc.mjpeg.slice_parameter.num_components;
+
+   for (i = 0; i < context->desc.mjpeg.slice_parameter.num_components; ++i) {
+  p[size++] = 
context->desc.mjpeg.slice_parameter.components[i].component_selector;
+  p[size++] = 
context->desc.mjpeg.slice_parameter.components[i].dc_table_selector << 4 |
+ 
context->desc.mjpeg.slice_parameter.components[i].ac_table_selector;
+   }
+
+   p[size++] = 0x00;
+   p[size++] = 0x3f;
+   p[size++] = 

[Mesa-dev] [PATCH 05/13] radeon/vcn: separate send cmd call from end frame

[boyuan.zhang]

From: Boyuan Zhang 

Use function pointer for sending cmd in end_frame call. By doing this, we can
assign different cmd sending logics for Jpeg decode later.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 30 -
 src/gallium/drivers/radeon/radeon_vcn_dec.h |  7 +++
 2 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index e6c1b67..30a8952 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -,24 +,17 @@ static void radeon_dec_decode_bitstream(struct 
pipe_video_codec *decoder,
 }
 
 /**
- * end decoding of the current frame
+ * send cmd for vcn dec
  */
-static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
+void send_cmd_dec(struct radeon_decoder *dec,
   struct pipe_video_buffer *target,
   struct pipe_picture_desc *picture)
 {
-   struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
struct pb_buffer *dt;
struct rvid_buffer *msg_fb_it_buf, *bs_buf;
 
-   assert(decoder);
-
-   if (!dec->bs_ptr)
-   return;
-
msg_fb_it_buf = >msg_fb_it_buffers[dec->cur_buffer];
bs_buf = >bs_buffers[dec->cur_buffer];
-
memset(dec->bs_ptr, 0, align(dec->bs_size, 128) - dec->bs_size);
dec->ws->buffer_unmap(bs_buf->res->buf);
 
@@ -1152,6 +1145,23 @@ static void radeon_dec_end_frame(struct pipe_video_codec 
*decoder,
send_cmd(dec, RDECODE_CMD_IT_SCALING_TABLE_BUFFER, 
msg_fb_it_buf->res->buf,
 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, 
RADEON_DOMAIN_GTT);
set_reg(dec, RDECODE_ENGINE_CNTL, 1);
+}
+
+/**
+ * end decoding of the current frame
+ */
+static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
+  struct pipe_video_buffer *target,
+  struct pipe_picture_desc *picture)
+{
+   struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
+
+   assert(decoder);
+
+   if (!dec->bs_ptr)
+   return;
+
+   dec->send_cmd(dec, target, picture);
 
flush(dec, PIPE_FLUSH_ASYNC);
next_buffer(dec);
@@ -1294,6 +1304,8 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
 
next_buffer(dec);
 
+   dec->send_cmd = send_cmd_dec;
+
return >base;
 
 error:
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index 399d75c..05e4847 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -618,8 +618,15 @@ struct radeon_decoder {
void*render_pic_list[16];
 
struct jpeg_params  jpg;
+   void (*send_cmd)(struct radeon_decoder *dec,
+struct pipe_video_buffer *target,
+struct pipe_picture_desc *picture);
 };
 
+void send_cmd_dec(struct radeon_decoder *dec,
+ struct pipe_video_buffer *target,
+ struct pipe_picture_desc *picture);
+
 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templat);
 
-- 
2.7.4

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[Mesa-dev] [PATCH 04/13] radeon/vcn: create cs based on ring type

[boyuan.zhang]

From: Boyuan Zhang 

Add RING_VCN_JPEG for VCN Jpeg decode, and keep RING_VCN_DEC for other codecs.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 8bea704..e6c1b67 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1173,7 +1173,7 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
struct radeon_winsys* ws = ((struct r600_common_context *)context)->ws;
struct r600_common_context *rctx = (struct r600_common_context*)context;
unsigned width = templ->width, height = templ->height;
-   unsigned dpb_size, bs_buf_size, stream_type = 0;
+   unsigned dpb_size, bs_buf_size, stream_type = 0, ring = RING_VCN_DEC;
struct radeon_decoder *dec;
int r, i;
 
@@ -1199,6 +1199,10 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
case PIPE_VIDEO_FORMAT_HEVC:
stream_type = RDECODE_CODEC_H265;
break;
+   case PIPE_VIDEO_FORMAT_JPEG:
+   stream_type = RDECODE_CODEC_JPEG;
+   ring = RING_VCN_JPEG;
+   break;
default:
assert(0);
break;
@@ -1225,7 +1229,7 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
dec->stream_handle = si_vid_alloc_stream_handle();
dec->screen = context->screen;
dec->ws = ws;
-   dec->cs = ws->cs_create(rctx->ctx, RING_VCN_DEC, NULL, NULL);
+   dec->cs = ws->cs_create(rctx->ctx, ring, NULL, NULL);
if (!dec->cs) {
RVID_ERR("Can't get command submission context.\n");
goto error;
-- 
2.7.4

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[Mesa-dev] [PATCH 02/13] radeon/vcn: add vcn jpeg decode interface

[boyuan.zhang]

From: Boyuan Zhang 

Add VCN Jpeg decode interfaces and register defines.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.h | 91 +
 1 file changed, 91 insertions(+)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index 4a90687..399d75c 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -43,6 +43,15 @@
 
 #define RDECODE_PKT2() (RDECODE_PKT_TYPE_S(2))
 
+#define RDECODE_PKT_REG_J(x)   ((unsigned)(x) & 0x3)
+#define RDECODE_PKT_RES_J(x)   (((unsigned)(x) & 0x3F) << 18)
+#define RDECODE_PKT_COND_J(x)  (((unsigned)(x) & 0xF) << 24)
+#define RDECODE_PKT_TYPE_J(x)  (((unsigned)(x) & 0xF) << 28)
+#define RDECODE_PKTJ(reg, cond, type)  (RDECODE_PKT_REG_J(reg) | \
+   RDECODE_PKT_RES_J(0) | \
+   RDECODE_PKT_COND_J(cond) | \
+   RDECODE_PKT_TYPE_J(type))
+
 #define RDECODE_CMD_MSG_BUFFER 0x
 #define RDECODE_CMD_DPB_BUFFER 0x0001
 #define RDECODE_CMD_DECODING_TARGET_BUFFER 0x0002
@@ -61,6 +70,7 @@
 #define RDECODE_CODEC_MPEG2_VLD0x0003
 #define RDECODE_CODEC_MPEG40x0004
 #define RDECODE_CODEC_H264_PERF0x0007
+#define RDECODE_CODEC_JPEG 0x0008
 #define RDECODE_CODEC_H265 0x0010
 
 #define RDECODE_ARRAY_MODE_LINEAR  0x
@@ -107,6 +117,77 @@
 
 #define NUM_BUFFERS4
 
+#define mmUVD_JPEG_CNTL0x0200
+#define mmUVD_JPEG_CNTL_BASE_IDX   1
+#define mmUVD_JPEG_RB_BASE 0x0201
+#define mmUVD_JPEG_RB_BASE_BASE_IDX1
+#define mmUVD_JPEG_RB_WPTR 0x0202
+#define mmUVD_JPEG_RB_WPTR_BASE_IDX1
+#define mmUVD_JPEG_RB_RPTR 0x0203
+#define mmUVD_JPEG_RB_RPTR_BASE_IDX1
+#define mmUVD_JPEG_RB_SIZE 0x0204
+#define mmUVD_JPEG_RB_SIZE_BASE_IDX1
+#define mmUVD_JPEG_TIER_CNTL2  0x021a
+#define mmUVD_JPEG_TIER_CNTL2_BASE_IDX 1
+#define mmUVD_JPEG_UV_TILING_CTRL  0x021c
+#define mmUVD_JPEG_UV_TILING_CTRL_BASE_IDX 1
+#define mmUVD_JPEG_TILING_CTRL 0x021e
+#define mmUVD_JPEG_TILING_CTRL_BASE_IDX1
+#define mmUVD_JPEG_OUTBUF_RPTR 0x0220
+#define mmUVD_JPEG_OUTBUF_RPTR_BASE_IDX1
+#define mmUVD_JPEG_OUTBUF_WPTR 0x0221
+#define mmUVD_JPEG_OUTBUF_WPTR_BASE_IDX1
+#define mmUVD_JPEG_PITCH   0x0222
+#define mmUVD_JPEG_PITCH_BASE_IDX  1
+#define mmUVD_JPEG_INT_EN  0x0229
+#define mmUVD_JPEG_INT_EN_BASE_IDX 1
+#define mmUVD_JPEG_UV_PITCH0x022b
+#define mmUVD_JPEG_UV_PITCH_BASE_IDX   1
+#define mmUVD_JPEG_INDEX   0x023e
+#define mmUVD_JPEG_INDEX_BASE_IDX  1
+#define mmUVD_JPEG_DATA0x023f
+#define mmUVD_JPEG_DATA_BASE_IDX   1
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH0x0438
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX   1
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0439
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX1
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x045a
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX1
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW  0x045b
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_CTX_INDEX0x0528
+#define mmUVD_CTX_INDEX_BASE_IDX   1
+#define mmUVD_CTX_DATA 0x0529
+#define mmUVD_CTX_DATA_BASE_IDX1
+#define mmUVD_SOFT_RESET   0x05a0
+#define mmUVD_SOFT_RESET_BASE_IDX  1
+
+#define UVD_BASE_INST0_SEG00x7800
+#define UVD_BASE_INST0_SEG10x7E00
+#define UVD_BASE_INST0_SEG20
+#define UVD_BASE_INST0_SEG30
+#define UVD_BASE_INST0_SEG40
+
+#define SOC15_REG_ADDR(reg)(UVD_BASE_INST0_SEG1 + reg)
+
+#define COND0  0
+#define COND1  1
+#define COND2  2
+#define COND3  3
+#define COND4  4

[Mesa-dev] [PATCH 03/13] radeon/winsys: add vcn jpeg ring type

[boyuan.zhang]

From: Boyuan Zhang 

Add a new ring type for vcn jpeg.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_winsys.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 0a56539..6290eef 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -78,6 +78,7 @@ enum ring_type {
 RING_UVD_ENC,
 RING_VCN_DEC,
 RING_VCN_ENC,
+RING_VCN_JPEG,
 RING_LAST,
 };
 
-- 
2.7.4

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[Mesa-dev] [PATCH 01/13] radeon/vcn: move radeon decoder define to header file

[boyuan.zhang]

From: Boyuan Zhang 

Move radeon_decoder definition from "radeon_vcn_dec.c" to "radeon_vcn_dec.h",
so that it can be included by other files later.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 28 
 src/gallium/drivers/radeon/radeon_vcn_dec.h | 29 +
 2 files changed, 29 insertions(+), 28 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 4bc922d..8bea704 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -49,38 +49,10 @@
 #define RDECODE_GPCOM_VCPU_DATA1   0x20714
 #define RDECODE_ENGINE_CNTL0x20718
 
-#define NUM_BUFFERS4
 #define NUM_MPEG2_REFS 6
 #define NUM_H264_REFS  17
 #define NUM_VC1_REFS   5
 
-struct radeon_decoder {
-   struct pipe_video_codec base;
-
-   unsignedstream_handle;
-   unsignedstream_type;
-   unsignedframe_number;
-
-   struct pipe_screen  *screen;
-   struct radeon_winsys*ws;
-   struct radeon_winsys_cs *cs;
-
-   void*msg;
-   uint32_t*fb;
-   uint8_t *it;
-   void*bs_ptr;
-
-   struct rvid_buffer  msg_fb_it_buffers[NUM_BUFFERS];
-   struct rvid_buffer  bs_buffers[NUM_BUFFERS];
-   struct rvid_buffer  dpb;
-   struct rvid_buffer  ctx;
-   struct rvid_buffer  sessionctx;
-
-   unsignedbs_size;
-   unsignedcur_buffer;
-   void*render_pic_list[16];
-};
-
 static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
struct pipe_h264_picture_desc *pic)
 {
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h 
b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index accffef..4a90687 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -105,6 +105,8 @@
 
 #define RDECODE_SPS_INFO_H264_EXTENSION_SUPPORT_FLAG_SHIFT 7
 
+#define NUM_BUFFERS4
+
 typedef struct rvcn_dec_message_index_s {
unsigned intmessage_id;
unsigned intoffset;
@@ -500,6 +502,33 @@ typedef struct rvcn_dec_feedback_profiling_s {
unsigned intdmaHwCrc32Value2;
 } rvcn_dec_feedback_profiling_t;
 
+struct radeon_decoder {
+   struct pipe_video_codec base;
+
+   unsignedstream_handle;
+   unsignedstream_type;
+   unsignedframe_number;
+
+   struct pipe_screen  *screen;
+   struct radeon_winsys*ws;
+   struct radeon_winsys_cs *cs;
+
+   void*msg;
+   uint32_t*fb;
+   uint8_t *it;
+   void*bs_ptr;
+
+   struct rvid_buffer  msg_fb_it_buffers[NUM_BUFFERS];
+   struct rvid_buffer  bs_buffers[NUM_BUFFERS];
+   struct rvid_buffer  dpb;
+   struct rvid_buffer  ctx;
+   struct rvid_buffer  sessionctx;
+
+   unsignedbs_size;
+   unsignedcur_buffer;
+   void*render_pic_list[16];
+};
+
 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templat);
 
-- 
2.7.4

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[Mesa-dev] [PATCH 09/10] radeonsi: add vcn jpeg decoder

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeonsi/si_uvd.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c
index b6cb4cb..f0abc36 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -30,6 +30,7 @@
 #include "radeon/radeon_uvd.h"
 #include "radeon/radeon_vce.h"
 #include "radeon/radeon_vcn_dec.h"
+#include "radeon/radeon_vcn_jpeg.h"
 #include "radeon/radeon_vcn_enc.h"
 #include "radeon/radeon_uvd_enc.h"
 #include "util/u_video.h"
@@ -159,6 +160,11 @@ struct pipe_video_codec *si_uvd_create_decoder(struct 
pipe_context *context,
}
}
 
-   return (vcn) ?  radeon_create_decoder(context, templ) :
+   if (vcn) {
+   if (u_reduce_video_profile(templ->profile) == 
PIPE_VIDEO_FORMAT_JPEG)
+   radeon_create_decoder_jpeg(context, templ);
+   else
+   radeon_create_decoder(context, templ);
+   } else
si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);
 }
-- 
2.7.4

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[Mesa-dev] [PATCH 07/10] amd/common: add vcn jpeg ip info query

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/amd/common/ac_gpu_info.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 73fc362..a1db3b9 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -99,7 +99,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
struct amdgpu_buffer_size_alignments alignment_info = {};
struct amdgpu_heap_info vram, vram_vis, gtt;
struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
-   struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
+   struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, 
vcn_jpeg = {};
struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
struct amdgpu_gds_resource_info gds = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature 
= 0;
@@ -199,6 +199,14 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
}
 
+   if (info->drm_major == 3 && info->drm_minor >= 17) {
+   r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, 
_jpeg);
+   if (r) {
+   fprintf(stderr, "amdgpu: 
amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
+   return false;
+   }
+   }
+
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
>me_fw_version,
>me_fw_feature);
@@ -301,7 +309,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->max_se = amdinfo->num_shader_engines;
info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
info->has_hw_decode =
-   (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
+   (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
+   (vcn_jpeg.available_rings != 0);
info->uvd_fw_version =
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
@@ -368,6 +377,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
ib_align = MAX2(ib_align, vce.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
+   ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
assert(ib_align);
info->ib_start_alignment = ib_align;
 
-- 
2.7.4

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[Mesa-dev] [PATCH 06/10] radeon/vcn: implement jpeg target buffer cmd

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_jpeg.c | 73 +++-
 1 file changed, 72 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_jpeg.c
index f7170fb..0e89d61 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_jpeg.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_jpeg.c
@@ -286,7 +286,78 @@ static void send_cmd_target(struct radeon_jpeg_decoder 
*dec,
 struct pb_buffer* buf, uint32_t off,
 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
 {
-   /* TODO */
+   uint64_t addr;
+
+   set_reg_jpeg(dec, mmUVD_JPEG_PITCH, COND0, TYPE0, (dec->dt_pitch >> 4));
+   set_reg_jpeg(dec, mmUVD_JPEG_UV_PITCH, COND0, TYPE0, ((dec->dt_uv_pitch 
* 2) >> 4));
+
+   set_reg_jpeg(dec, mmUVD_JPEG_TILING_CTRL, COND0, TYPE0, 0);
+   set_reg_jpeg(dec, mmUVD_JPEG_UV_TILING_CTRL, COND0, TYPE0, 0);
+
+   dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, RADEON_PRIO_UVD);
+   addr = dec->ws->buffer_get_virtual_address(buf);
+   addr = addr + off;
+
+   // set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer 
address
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0, 
(addr >> 32));
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0, 
addr);
+
+   // set output buffer data address
+   set_reg_jpeg(dec, mmUVD_JPEG_INDEX, COND0, TYPE0, 0);
+   set_reg_jpeg(dec, mmUVD_JPEG_DATA, COND0, TYPE0, 
dec->dt_luma_top_offset);
+   set_reg_jpeg(dec, mmUVD_JPEG_INDEX, COND0, TYPE0, 1);
+   set_reg_jpeg(dec, mmUVD_JPEG_DATA, COND0, TYPE0, 
dec->dt_chroma_top_offset);
+   set_reg_jpeg(dec, mmUVD_JPEG_TIER_CNTL2, COND0, TYPE3, 0);
+
+   // set output buffer read pointer
+   set_reg_jpeg(dec, mmUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0);
+
+   // enable error interrupts
+   set_reg_jpeg(dec, mmUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFE);
+
+   // start engine command
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0x6);
+
+   // wait for job completion, wait for job JBSI fetch done
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (dec->bsd_size >> 2));
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C2);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x01400200);
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_RPTR, COND0, TYPE3, 0x);
+
+   // wait for job jpeg outbuf idle
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x);
+   set_reg_jpeg(dec, mmUVD_JPEG_OUTBUF_WPTR, COND0, TYPE3, 0x0001);
+
+   // stop engine
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0x4);
+
+   // asserting jpeg lmi drop
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x0005);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 23 | 1 << 0));
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE1, 0);
+
+   // asserting jpeg reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 1);
+
+   // ensure reset is asserted in sclk domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // de-assert jpeg reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0);
+
+   // ensure reset is de-asserted in sclk domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (0 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // de-asserting jpeg lmi drop
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x0005);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0);
 }
 
 /* cycle to the next set of buffers */
-- 
2.7.4

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[Mesa-dev] [PATCH 10/10] radeonsi: enable vcn jpeg decode for raven

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeonsi/si_get.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index fc2be33..de587bb 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -640,6 +640,8 @@ static int si_get_video_param(struct pipe_screen *screen,
return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
return false;
case PIPE_VIDEO_FORMAT_JPEG:
+   if (sscreen->info.family == CHIP_RAVEN)
+   return true;
if (sscreen->info.family < CHIP_CARRIZO || 
sscreen->info.family >= CHIP_VEGA10)
return false;
if (!(sscreen->info.drm_major == 3 && 
sscreen->info.drm_minor >= 19)) {
-- 
2.7.4

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[Mesa-dev] [PATCH 04/10] radeon/vcn: implement jpeg decode functions

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_jpeg.c | 286 ++-
 1 file changed, 281 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_jpeg.c
index c078131..72dff57 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_jpeg.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_jpeg.c
@@ -63,12 +63,195 @@ struct radeon_jpeg_decoder {
unsigneddt_chroma_top_offset;
 };
 
+static void radeon_jpeg_destroy_associated_data(void *data)
+{
+   /* NOOP, since we only use an intptr */
+}
+
+static struct pb_buffer *radeon_jpeg_get_decode_param(struct 
radeon_jpeg_decoder *dec,
+   struct pipe_video_buffer *target,
+   struct pipe_picture_desc *picture)
+{
+   struct r600_texture *luma = (struct r600_texture *)
+   ((struct vl_video_buffer 
*)target)->resources[0];
+   struct r600_texture *chroma = (struct r600_texture *)
+   ((struct vl_video_buffer 
*)target)->resources[1];
+
+   dec->bsd_size = align(dec->bs_size, 128);
+   dec->dt_luma_top_offset = luma->surface.u.gfx9.surf_offset;
+   if (target->buffer_format == PIPE_FORMAT_NV12) {
+   dec->dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
+   dec->dt_pitch = luma->surface.u.gfx9.surf_pitch * 
luma->surface.blk_w;
+   }
+   else if (target->buffer_format == PIPE_FORMAT_YUYV)
+   dec->dt_pitch = luma->surface.u.gfx9.surf_pitch;
+   dec->dt_uv_pitch = dec->dt_pitch / 2;
+
+   return luma->resource.buf;
+}
+
+static void get_mjpeg_slice_header(struct radeon_jpeg_decoder *dec, struct 
pipe_mjpeg_picture_desc *pic)
+{
+   int size = 0, saved_size, len_pos, i;
+   uint16_t *bs;
+   uint8_t *buf = dec->bs_ptr;
+
+   /* SOI */
+   buf[size++] = 0xff;
+   buf[size++] = 0xd8;
+
+   /* DQT */
+   buf[size++] = 0xff;
+   buf[size++] = 0xdb;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 4; ++i) {
+   if (pic->quantization_table.load_quantiser_table[i] == 0)
+   continue;
+
+   buf[size++] = i;
+   memcpy((buf + size), 
>quantization_table.quantiser_table[i], 64);
+   size += 64;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - 4);
+
+   saved_size = size;
+
+   /* DHT */
+   buf[size++] = 0xff;
+   buf[size++] = 0xc4;
+
+   len_pos = size++;
+   size++;
+
+   for (i = 0; i < 2; ++i) {
+   if (pic->huffman_table.load_huffman_table[i] == 0)
+   continue;
+
+   buf[size++] = 0x00 | i;
+   memcpy((buf + size), >huffman_table.table[i].num_dc_codes, 
16);
+   size += 16;
+   memcpy((buf + size), >huffman_table.table[i].dc_values, 
12);
+   size += 12;
+   }
+
+   for (i = 0; i < 2; ++i) {
+   if (pic->huffman_table.load_huffman_table[i] == 0)
+   continue;
+
+   buf[size++] = 0x10 | i;
+   memcpy((buf + size), >huffman_table.table[i].num_ac_codes, 
16);
+   size += 16;
+   memcpy((buf + size), >huffman_table.table[i].ac_values, 
162);
+   size += 162;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - saved_size - 2);
+
+   saved_size = size;
+
+   /* DRI */
+   if (pic->slice_parameter.restart_interval) {
+   buf[size++] = 0xff;
+   buf[size++] = 0xdd;
+   buf[size++] = 0x00;
+   buf[size++] = 0x04;
+   bs = (uint16_t*)[size++];
+   *bs = util_bswap16(pic->slice_parameter.restart_interval);
+   saved_size = ++size;
+   }
+
+   /* SOF */
+   buf[size++] = 0xff;
+   buf[size++] = 0xc0;
+
+   len_pos = size++;
+   size++;
+
+   buf[size++] = 0x08;
+
+   bs = (uint16_t*)[size++];
+   *bs = util_bswap16(pic->picture_parameter.picture_height);
+   size++;
+
+   bs = (uint16_t*)[size++];
+   *bs = util_bswap16(pic->picture_parameter.picture_width);
+   size++;
+
+   buf[size++] = pic->picture_parameter.num_components;
+
+   for (i = 0; i < pic->picture_parameter.num_components; ++i) {
+   buf[size++] = pic->picture_parameter.components[i].component_id;
+   buf[size++] = 
pic->picture_parameter.components[i].h_sampling_factor << 4 |
+ 
pic->picture_parameter.components[i].v_sampling_factor;
+   buf[size++] = 
pic->picture_parameter.components[i].quantiser_table_selector;
+   }
+
+   bs = (uint16_t*)[len_pos];
+   *bs = util_bswap16(size - saved_size - 2);
+
+   

[Mesa-dev] [PATCH 02/10] radeon/winsys: add vcn jpeg ring type

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_winsys.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 0a56539..6290eef 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -78,6 +78,7 @@ enum ring_type {
 RING_UVD_ENC,
 RING_VCN_DEC,
 RING_VCN_ENC,
+RING_VCN_JPEG,
 RING_LAST,
 };
 
-- 
2.7.4

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[Mesa-dev] [PATCH 08/10] winsys/amdgpu: add vcn jpeg cs support

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index a3feeb9..5092f49 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -840,6 +840,10 @@ static bool amdgpu_init_cs_context(struct 
amdgpu_cs_context *cs,
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_ENC;
   break;
 
+   case RING_VCN_JPEG:
+  cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_JPEG;
+  break;
+
default:
case RING_GFX:
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_GFX;
@@ -1545,6 +1549,14 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
   while (rcs->current.cdw & 15)
  radeon_emit(rcs, 0x8000); /* type2 nop packet */
   break;
+   case RING_VCN_JPEG:
+  if (rcs->current.cdw % 2)
+ assert(0);
+  while (rcs->current.cdw & 15) {
+ radeon_emit(rcs, 0x6000); /* nop packet */
+ radeon_emit(rcs, 0x);
+  }
+  break;
case RING_VCN_DEC:
   while (rcs->current.cdw & 15)
  radeon_emit(rcs, 0x81ff); /* nop packet */
-- 
2.7.4

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[Mesa-dev] [PATCH 03/10] radeon/vcn: add jpeg decoder creation

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/Makefile.sources  |   1 +
 src/gallium/drivers/radeon/meson.build   |   1 +
 src/gallium/drivers/radeon/radeon_vcn_jpeg.c | 212 +++
 3 files changed, 214 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_vcn_jpeg.c

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index a11bffe..3424e2d 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -16,6 +16,7 @@ C_SOURCES := \
radeon_vcn_enc.c \
radeon_vcn_enc.h \
radeon_vcn_jpeg.h \
+   radeon_vcn_jpeg.c \
radeon_uvd_enc_1_1.c \
radeon_uvd_enc.c \
radeon_uvd_enc.h \
diff --git a/src/gallium/drivers/radeon/meson.build 
b/src/gallium/drivers/radeon/meson.build
index eb68b57..a12cd4e 100644
--- a/src/gallium/drivers/radeon/meson.build
+++ b/src/gallium/drivers/radeon/meson.build
@@ -36,6 +36,7 @@ files_libradeon = files(
   'radeon_vcn_dec.c',
   'radeon_vcn_dec.h',
   'radeon_vcn_jpeg.h',
+  'radeon_vcn_jpeg.c',
   'radeon_uvd_enc_1_1.c',
   'radeon_uvd_enc.c',
   'radeon_uvd_enc.h',
diff --git a/src/gallium/drivers/radeon/radeon_vcn_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_jpeg.c
new file mode 100644
index 000..c078131
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_vcn_jpeg.c
@@ -0,0 +1,212 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_memory.h"
+#include "util/u_video.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_vcn_jpeg.h"
+
+#define NUM_BUFFERS4
+
+struct radeon_jpeg_decoder {
+   struct pipe_video_codec base;
+
+   unsignedstream_handle;
+   unsignedstream_type;
+   unsignedframe_number;
+
+   struct pipe_screen  *screen;
+   struct radeon_winsys*ws;
+   struct radeon_winsys_cs *cs;
+
+   void*bs_ptr;
+
+   struct rvid_buffer  bs_buffers[NUM_BUFFERS];
+
+   unsignedbs_size;
+   unsignedcur_buffer;
+   unsignedbsd_size;
+   unsigneddt_pitch;
+   unsigneddt_uv_pitch;
+   unsigneddt_luma_top_offset;
+   unsigneddt_chroma_top_offset;
+};
+
+/* flush IB to the hardware */
+static int flush(struct radeon_jpeg_decoder *dec, unsigned flags)
+{
+   return dec->ws->cs_flush(dec->cs, flags, NULL);
+}
+
+/* cycle to the next set of buffers */
+static void next_buffer(struct radeon_jpeg_decoder *dec)
+{
+   ++dec->cur_buffer;
+   dec->cur_buffer %= NUM_BUFFERS;
+}
+
+/**
+ * destroy this video decoder
+ */
+static void radeon_jpeg_destroy(struct pipe_video_codec *decoder)
+{
+   /* TODO */
+}
+
+/**
+ * start decoding of a new frame
+ */
+static void radeon_jpeg_begin_frame(struct pipe_video_codec *decoder,
+struct pipe_video_buffer *target,
+struct pipe_picture_desc *picture)
+{
+   /* TODO */
+}
+
+/**
+ * decode a macroblock
+ */
+static void radeon_jpeg_decode_macroblock(struct pipe_video_codec *decoder,
+  struct pipe_video_buffer *target,
+  struct pipe_picture_desc *picture,
+  

[Mesa-dev] [PATCH 01/10] radeon/vcn: add vcn jpeg decode interface

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/Makefile.sources  |   1 +
 src/gallium/drivers/radeon/meson.build   |   1 +
 src/gallium/drivers/radeon/radeon_vcn_jpeg.h | 116 +++
 3 files changed, 118 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_vcn_jpeg.h

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index f8ee860..a11bffe 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -15,6 +15,7 @@ C_SOURCES := \
radeon_vcn_enc_1_2.c \
radeon_vcn_enc.c \
radeon_vcn_enc.h \
+   radeon_vcn_jpeg.h \
radeon_uvd_enc_1_1.c \
radeon_uvd_enc.c \
radeon_uvd_enc.h \
diff --git a/src/gallium/drivers/radeon/meson.build 
b/src/gallium/drivers/radeon/meson.build
index 582a5ff..eb68b57 100644
--- a/src/gallium/drivers/radeon/meson.build
+++ b/src/gallium/drivers/radeon/meson.build
@@ -35,6 +35,7 @@ files_libradeon = files(
   'radeon_vcn_enc.h',
   'radeon_vcn_dec.c',
   'radeon_vcn_dec.h',
+  'radeon_vcn_jpeg.h',
   'radeon_uvd_enc_1_1.c',
   'radeon_uvd_enc.c',
   'radeon_uvd_enc.h',
diff --git a/src/gallium/drivers/radeon/radeon_vcn_jpeg.h 
b/src/gallium/drivers/radeon/radeon_vcn_jpeg.h
new file mode 100644
index 000..7eda6f7
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_vcn_jpeg.h
@@ -0,0 +1,116 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#ifndef _RADEON_VCN_JPEG_H
+#define _RADEON_VCN_JPEG_H
+
+#define mmUVD_JPEG_CNTL
0x0200
+#define mmUVD_JPEG_CNTL_BASE_IDX   
1
+#define mmUVD_JPEG_RB_BASE 
0x0201
+#define mmUVD_JPEG_RB_BASE_BASE_IDX
1
+#define mmUVD_JPEG_RB_WPTR 
0x0202
+#define mmUVD_JPEG_RB_WPTR_BASE_IDX
1
+#define mmUVD_JPEG_RB_RPTR 
0x0203
+#define mmUVD_JPEG_RB_RPTR_BASE_IDX
1
+#define mmUVD_JPEG_RB_SIZE 
0x0204
+#define mmUVD_JPEG_RB_SIZE_BASE_IDX
1
+#define mmUVD_JPEG_TIER_CNTL2  
0x021a
+#define mmUVD_JPEG_TIER_CNTL2_BASE_IDX 
1
+#define mmUVD_JPEG_UV_TILING_CTRL  
0x021c
+#define mmUVD_JPEG_UV_TILING_CTRL_BASE_IDX 
1
+#define mmUVD_JPEG_TILING_CTRL 
0x021e
+#define mmUVD_JPEG_TILING_CTRL_BASE_IDX
1
+#define mmUVD_JPEG_OUTBUF_RPTR 
0x0220
+#define mmUVD_JPEG_OUTBUF_RPTR_BASE_IDX
1
+#define mmUVD_JPEG_OUTBUF_WPTR 
0x0221
+#define 

[Mesa-dev] [PATCH 05/10] radeon/vcn: implement jpeg bitstream buffer cmd

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_jpeg.c | 41 ++--
 1 file changed, 39 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_jpeg.c 
b/src/gallium/drivers/radeon/radeon_vcn_jpeg.c
index 72dff57..f7170fb 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_jpeg.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_jpeg.c
@@ -233,7 +233,8 @@ static int flush(struct radeon_jpeg_decoder *dec, unsigned 
flags)
 static void set_reg_jpeg(struct radeon_jpeg_decoder *dec, unsigned reg,
unsigned cond, unsigned type, uint32_t 
val)
 {
-   /* TODO */
+   radeon_emit(dec->cs, RDECODE_PKTJ(SOC15_REG_ADDR(reg), cond, type));
+   radeon_emit(dec->cs, val);
 }
 
 /* send a bitstream buffer command */
@@ -241,7 +242,43 @@ static void send_cmd_bitstream(struct radeon_jpeg_decoder 
*dec,
 struct pb_buffer* buf, uint32_t off,
 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
 {
-   /* TODO */
+   uint64_t addr;
+
+   // jpeg soft reset
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 1);
+
+   // ensuring the Reset is asserted in SCLK domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C2);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, 0x01400200);
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (1 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   // wait mem
+   set_reg_jpeg(dec, mmUVD_JPEG_CNTL, COND0, TYPE0, 0);
+
+   // ensuring the Reset is de-asserted in SCLK domain
+   set_reg_jpeg(dec, mmUVD_CTX_INDEX, COND0, TYPE0, 0x01C3);
+   set_reg_jpeg(dec, mmUVD_CTX_DATA, COND0, TYPE0, (0 << 9));
+   set_reg_jpeg(dec, mmUVD_SOFT_RESET, COND0, TYPE3, (1 << 9));
+
+   dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, RADEON_PRIO_UVD);
+   addr = dec->ws->buffer_get_virtual_address(buf);
+   addr = addr + off;
+
+   // set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer 
address
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0, 
(addr >> 32));
+   set_reg_jpeg(dec, mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0, 
addr);
+
+   // set jpeg_rb_base
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_BASE, COND0, TYPE0, 0);
+
+   // set jpeg_rb_base
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFF0);
+
+   // set jpeg_rb_wptr
+   set_reg_jpeg(dec, mmUVD_JPEG_RB_WPTR, COND0, TYPE0, (dec->bsd_size >> 
2));
 }
 
 /* send a target buffer command */
-- 
2.7.4

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[Mesa-dev] [PATCH] radeon/vce: add firmware support for ver 53 and up

[boyuan.zhang]

From: Boyuan Zhang 

All vce firmwares with major version greater than or equal to 53 are supported

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vce.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vce.c 
b/src/gallium/drivers/radeon/radeon_vce.c
index 427bf01e..17a1125 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -506,7 +506,7 @@ struct pipe_video_codec *si_vce_create_encoder(struct 
pipe_context *context,
break;
 
default:
-   if ((sscreen->info.vce_fw_version & (0xff << 24)) == FW_53) {
+   if ((sscreen->info.vce_fw_version & (0xff << 24)) >= FW_53) {
si_vce_52_init(enc);
si_get_pic_param = si_vce_52_get_param;
} else
@@ -542,7 +542,7 @@ bool si_vce_is_fw_version_supported(struct si_screen 
*sscreen)
case FW_52_8_3:
return true;
default:
-   if ((sscreen->info.vce_fw_version & (0xff << 24)) == FW_53)
+   if ((sscreen->info.vce_fw_version & (0xff << 24)) >= FW_53)
return true;
else
return false;
-- 
2.7.4

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[Mesa-dev] [PATCH] radeon/vcn: fix mpeg4 msg buffer settings

[boyuan.zhang]

From: Boyuan Zhang 

Previous bit-fields assignments are incorrect and will result certain mpeg4
decode failed due to wrong flag values. This patch fixes these assignments.

Cc: 18.0 18.1 

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index f83e9e5..4bc922d 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -554,15 +554,15 @@ static rvcn_dec_message_mpeg4_asp_vld_t 
get_mpeg4_msg(struct radeon_decoder *dec
 
result.vop_time_increment_resolution = 
pic->vop_time_increment_resolution;
 
-   result.short_video_header |= pic->short_video_header << 0;
-   result.interlaced |= pic->interlaced << 2;
-result.load_intra_quant_mat |= 1 << 3;
-   result.load_nonintra_quant_mat |= 1 << 4;
-   result.quarter_sample |= pic->quarter_sample << 5;
-   result.complexity_estimation_disable |= 1 << 6;
-   result.resync_marker_disable |= pic->resync_marker_disable << 7;
-   result.newpred_enable |= 0 << 10; //
-   result.reduced_resolution_vop_enable |= 0 << 11;
+   result.short_video_header = pic->short_video_header;
+   result.interlaced = pic->interlaced;
+   result.load_intra_quant_mat = 1;
+   result.load_nonintra_quant_mat = 1;
+   result.quarter_sample = pic->quarter_sample;
+   result.complexity_estimation_disable = 1;
+   result.resync_marker_disable = pic->resync_marker_disable;
+   result.newpred_enable = 0;
+   result.reduced_resolution_vop_enable = 0;
 
result.quant_type = pic->quant_type;
 
-- 
2.7.4

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[Mesa-dev] [PATCH] radeon/vcn: fix mpeg4 msg buffer settings

[boyuan.zhang]

From: Boyuan Zhang 

Previous bit-fields assignments are incorrect and will result certain mpeg4
decode failed due to wrong flag values. This patch fixes these assignments.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index f83e9e5..4bc922d 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -554,15 +554,15 @@ static rvcn_dec_message_mpeg4_asp_vld_t 
get_mpeg4_msg(struct radeon_decoder *dec
 
result.vop_time_increment_resolution = 
pic->vop_time_increment_resolution;
 
-   result.short_video_header |= pic->short_video_header << 0;
-   result.interlaced |= pic->interlaced << 2;
-result.load_intra_quant_mat |= 1 << 3;
-   result.load_nonintra_quant_mat |= 1 << 4;
-   result.quarter_sample |= pic->quarter_sample << 5;
-   result.complexity_estimation_disable |= 1 << 6;
-   result.resync_marker_disable |= pic->resync_marker_disable << 7;
-   result.newpred_enable |= 0 << 10; //
-   result.reduced_resolution_vop_enable |= 0 << 11;
+   result.short_video_header = pic->short_video_header;
+   result.interlaced = pic->interlaced;
+   result.load_intra_quant_mat = 1;
+   result.load_nonintra_quant_mat = 1;
+   result.quarter_sample = pic->quarter_sample;
+   result.complexity_estimation_disable = 1;
+   result.resync_marker_disable = pic->resync_marker_disable;
+   result.newpred_enable = 0;
+   result.reduced_resolution_vop_enable = 0;
 
result.quant_type = pic->quant_type;
 
-- 
2.7.4

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[Mesa-dev] [PATCH] radeon/vcn: fix mpeg4 msg buffer settings

[boyuan.zhang]

From: Boyuan Zhang 

Previous bit-fields assignments are incorrect and will result certain mpeg4
decode failed due to wrong flag values. This patch fixes these assignments.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index f83e9e5..4bc922d 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -554,15 +554,15 @@ static rvcn_dec_message_mpeg4_asp_vld_t 
get_mpeg4_msg(struct radeon_decoder *dec
 
result.vop_time_increment_resolution = 
pic->vop_time_increment_resolution;
 
-   result.short_video_header |= pic->short_video_header << 0;
-   result.interlaced |= pic->interlaced << 2;
-result.load_intra_quant_mat |= 1 << 3;
-   result.load_nonintra_quant_mat |= 1 << 4;
-   result.quarter_sample |= pic->quarter_sample << 5;
-   result.complexity_estimation_disable |= 1 << 6;
-   result.resync_marker_disable |= pic->resync_marker_disable << 7;
-   result.newpred_enable |= 0 << 10; //
-   result.reduced_resolution_vop_enable |= 0 << 11;
+   result.short_video_header = pic->short_video_header;
+   result.interlaced = pic->interlaced;
+   result.load_intra_quant_mat = 1;
+   result.load_nonintra_quant_mat = 1;
+   result.quarter_sample = pic->quarter_sample;
+   result.complexity_estimation_disable = 1;
+   result.resync_marker_disable = pic->resync_marker_disable;
+   result.newpred_enable = 0;
+   result.reduced_resolution_vop_enable = 0;
 
result.quant_type = pic->quant_type;
 
-- 
2.7.4

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[Mesa-dev] [PATCH] radeonsi: fix radeon create encoder return

[boyuan.zhang]

From: Boyuan Zhang 

Previous patch missed a "return" when trying to modify the create encoder
function, which made the whole logic fail. Therefore, add the return back.

Fixes: b38b208ff8886e799d6a2 "radeonsi:create uvd hevc enc entry"

Signed-off-by: Boyuan Zhang 
Reviewed-by: Alex Deucher 
Reviewed-by: Eric Engestrom 
---
 src/gallium/drivers/radeonsi/si_uvd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c
index 3906bbd..b6cb4cb 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -150,7 +150,7 @@ struct pipe_video_codec *si_uvd_create_decoder(struct 
pipe_context *context,
 
if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
if (vcn) {
-   radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
+   return radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
} else {
if (u_reduce_video_profile(templ->profile) == 
PIPE_VIDEO_FORMAT_HEVC)
return radeon_uvd_create_encoder(context, 
templ, ctx->b.ws, si_vce_get_buffer);
-- 
2.7.4

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[Mesa-dev] [PATCH] st/omx_bellagio: add picture profile and entry point

[boyuan.zhang]

From: Boyuan Zhang 

Profile and entry point were missing in the picture structure.
Therefore, add them back.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
---
 src/gallium/state_trackers/omx_bellagio/vid_enc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/state_trackers/omx_bellagio/vid_enc.c 
b/src/gallium/state_trackers/omx_bellagio/vid_enc.c
index 1a4fb62..162ec1f 100644
--- a/src/gallium/state_trackers/omx_bellagio/vid_enc.c
+++ b/src/gallium/state_trackers/omx_bellagio/vid_enc.c
@@ -1098,6 +1098,8 @@ static void enc_HandleTask(omx_base_PortType *port, 
struct encode_task *task,
 
picture.picture_type = picture_type;
picture.pic_order_cnt = task->pic_order_cnt;
+   picture.base.profile = 
enc_TranslateOMXProfileToPipe(priv->profile_level.eProfile);
+   picture.base.entry_point = PIPE_VIDEO_ENTRYPOINT_ENCODE;
if (priv->restricted_b_frames && picture_type == 
PIPE_H264_ENC_PICTURE_TYPE_B)
   picture.not_referenced = true;
enc_ControlPicture(port, );
-- 
2.7.4

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[Mesa-dev] [PATCH] radeon/vcn: use enc profile instead of pic profile

[boyuan.zhang]

From: Boyuan Zhang 

Picture profile might not be set in some cases. Therefore, better to use
the profile stored in encoder base.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc.c |  4 ++--
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 16 
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index 388a333..dcc25f2 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -40,7 +40,7 @@
 
 static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct 
pipe_picture_desc *picture)
 {
-   if (u_reduce_video_profile(picture->profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
+   if (u_reduce_video_profile(enc->base.profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
   struct pipe_h264_enc_picture_desc *pic = (struct 
pipe_h264_enc_picture_desc *)picture;
   enc->enc_pic.picture_type = pic->picture_type;
   enc->enc_pic.frame_num = pic->frame_num;
@@ -54,7 +54,7 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder 
*enc, struct pipe_pic
   enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) 
/ 2;
   enc->enc_pic.crop_top = 0;
   enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;
-   } else if (u_reduce_video_profile(picture->profile) == 
PIPE_VIDEO_FORMAT_HEVC) {
+   } else if (u_reduce_video_profile(enc->base.profile) == 
PIPE_VIDEO_FORMAT_HEVC) {
   struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;
   enc->enc_pic.picture_type = pic->picture_type;
   enc->enc_pic.frame_num = pic->frame_num;
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 07493d8..9adf40f 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -341,7 +341,7 @@ static void radeon_enc_spec_misc_hevc(struct radeon_encoder 
*enc, struct pipe_pi
 
 static void radeon_enc_rc_session_init(struct radeon_encoder *enc, struct 
pipe_picture_desc *picture)
 {
-   if (u_reduce_video_profile(picture->profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
+   if (u_reduce_video_profile(enc->base.profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
struct pipe_h264_enc_picture_desc *pic = (struct 
pipe_h264_enc_picture_desc *)picture;
enc->enc_pic.rc_session_init.vbv_buffer_level = 
pic->rate_ctrl.vbv_buf_lv;
switch(pic->rate_ctrl.rate_ctrl_method) {
@@ -359,7 +359,7 @@ static void radeon_enc_rc_session_init(struct 
radeon_encoder *enc, struct pipe_p
default:

enc->enc_pic.rc_session_init.rate_control_method = 
RENCODE_RATE_CONTROL_METHOD_NONE;
}
-   } else if (u_reduce_video_profile(picture->profile) == 
PIPE_VIDEO_FORMAT_HEVC) {
+   } else if (u_reduce_video_profile(enc->base.profile) == 
PIPE_VIDEO_FORMAT_HEVC) {
struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;
enc->enc_pic.rc_session_init.vbv_buffer_level = 
pic->rc.vbv_buf_lv;
switch(pic->rc.rate_ctrl_method) {
@@ -387,7 +387,7 @@ static void radeon_enc_rc_session_init(struct 
radeon_encoder *enc, struct pipe_p
 
 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc, struct 
pipe_picture_desc *picture)
 {
-   if (u_reduce_video_profile(picture->profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
+   if (u_reduce_video_profile(enc->base.profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
struct pipe_h264_enc_picture_desc *pic = (struct 
pipe_h264_enc_picture_desc *)picture;
enc->enc_pic.rc_layer_init.target_bit_rate = 
pic->rate_ctrl.target_bitrate;
enc->enc_pic.rc_layer_init.peak_bit_rate = 
pic->rate_ctrl.peak_bitrate;
@@ -397,7 +397,7 @@ static void radeon_enc_rc_layer_init(struct radeon_encoder 
*enc, struct pipe_pic
enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = 
pic->rate_ctrl.target_bits_picture;
enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = 
pic->rate_ctrl.peak_bits_picture_integer;
enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = 
pic->rate_ctrl.peak_bits_picture_fraction;
-   } else if (u_reduce_video_profile(picture->profile) == 
PIPE_VIDEO_FORMAT_HEVC) {
+   } else if (u_reduce_video_profile(enc->base.profile) == 
PIPE_VIDEO_FORMAT_HEVC) {
struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;
enc->enc_pic.rc_layer_init.target_bit_rate = 
pic->rc.target_bitrate;
enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rc.peak_bitrate;
@@ -1113,7 +1113,7 @@ static void 

[Mesa-dev] [PATCH] radeonsi: fix radeon create encoder return

[boyuan.zhang]

From: Boyuan Zhang 

Previous patch missed a "return" when trying to modify the create encoder
function, which made the whole logic fail. Therefore, add the return back.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeonsi/si_uvd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c
index 3906bbd..b6cb4cb 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -150,7 +150,7 @@ struct pipe_video_codec *si_uvd_create_decoder(struct 
pipe_context *context,
 
if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
if (vcn) {
-   radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
+   return radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
} else {
if (u_reduce_video_profile(templ->profile) == 
PIPE_VIDEO_FORMAT_HEVC)
return radeon_uvd_create_encoder(context, 
templ, ctx->b.ws, si_vce_get_buffer);
-- 
2.7.4

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[Mesa-dev] [PATCH 09/12] st/va: enable dual instances encode only for H264

[boyuan.zhang]

From: Boyuan Zhang 

Logics that related to dual instances encode should only be done for
H264, not other codecs.

Signed-off-by: Boyuan Zhang 
Acked-by: Christian König 
---
 src/gallium/state_trackers/va/picture.c |  3 ++-
 src/gallium/state_trackers/va/surface.c | 23 +--
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index d5fa947..57f53ac 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -610,7 +610,8 @@ vlVaEndPicture(VADriverContextP ctx, VAContextID context_id)
}
 
context->decoder->end_frame(context->decoder, context->target, 
>desc.base);
-   if (context->decoder->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+   if (context->decoder->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE &&
+  u_reduce_video_profile(context->templat.profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
   int idr_period = context->desc.h264enc.gop_size / context->gop_coeff;
   int p_remain_in_idr = idr_period - context->desc.h264enc.frame_num;
   surf->frame_num_cnt = context->desc.h264enc.frame_num_cnt;
diff --git a/src/gallium/state_trackers/va/surface.c 
b/src/gallium/state_trackers/va/surface.c
index 636505b..9823232 100644
--- a/src/gallium/state_trackers/va/surface.c
+++ b/src/gallium/state_trackers/va/surface.c
@@ -36,6 +36,7 @@
 #include "util/u_rect.h"
 #include "util/u_sampler.h"
 #include "util/u_surface.h"
+#include "util/u_video.h"
 
 #include "vl/vl_compositor.h"
 #include "vl/vl_video_buffer.h"
@@ -122,16 +123,18 @@ vlVaSyncSurface(VADriverContextP ctx, VASurfaceID 
render_target)
}
 
if (context->decoder->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
-  int frame_diff;
-  if (context->desc.h264enc.frame_num_cnt >= surf->frame_num_cnt)
- frame_diff = context->desc.h264enc.frame_num_cnt - 
surf->frame_num_cnt;
-  else
- frame_diff = 0x - surf->frame_num_cnt + 1 + 
context->desc.h264enc.frame_num_cnt;
-  if ((frame_diff == 0) &&
-  (surf->force_flushed == false) &&
-  (context->desc.h264enc.frame_num_cnt % 2 != 0)) {
- context->decoder->flush(context->decoder);
- context->first_single_submitted = true;
+  if (u_reduce_video_profile(context->templat.profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
+ int frame_diff;
+ if (context->desc.h264enc.frame_num_cnt >= surf->frame_num_cnt)
+frame_diff = context->desc.h264enc.frame_num_cnt - 
surf->frame_num_cnt;
+ else
+frame_diff = 0x - surf->frame_num_cnt + 1 + 
context->desc.h264enc.frame_num_cnt;
+ if ((frame_diff == 0) &&
+ (surf->force_flushed == false) &&
+ (context->desc.h264enc.frame_num_cnt % 2 != 0)) {
+context->decoder->flush(context->decoder);
+context->first_single_submitted = true;
+ }
   }
   context->decoder->get_feedback(context->decoder, surf->feedback, 
&(surf->coded_buf->coded_size));
   surf->feedback = NULL;
-- 
2.7.4

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[Mesa-dev] [PATCH 12/12] radeonsi: enable vcn encode for HEVC main

[boyuan.zhang]

From: Boyuan Zhang 

Enable vcn encode for HEVC main profile on Raven.

Signed-off-by: Boyuan Zhang 
Acked-by: Christian König 
---
 src/gallium/drivers/radeonsi/si_get.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index 1c84a25..8382721 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -588,8 +588,10 @@ static int si_get_video_param(struct pipe_screen *screen,
if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
switch (param) {
case PIPE_VIDEO_CAP_SUPPORTED:
-   return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
+   return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
(si_vce_is_fw_version_supported(sscreen) ||
+   sscreen->info.family == CHIP_RAVEN)) ||
+   (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
sscreen->info.family == CHIP_RAVEN);
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
-- 
2.7.4

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[Mesa-dev] [PATCH 08/12] st/va: add entrypoint check for HEVC

[boyuan.zhang]

From: Boyuan Zhang 

Add entrypoint check for HEVC to differentiate decode and encode jobs.

Signed-off-by: Boyuan Zhang 
Acked-by: Christian König 
---
 src/gallium/state_trackers/va/context.c | 22 --
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/src/gallium/state_trackers/va/context.c 
b/src/gallium/state_trackers/va/context.c
index f03b326..f567f54 100644
--- a/src/gallium/state_trackers/va/context.c
+++ b/src/gallium/state_trackers/va/context.c
@@ -263,16 +263,18 @@ vlVaCreateContext(VADriverContextP ctx, VAConfigID 
config_id, int picture_width,
 
  case PIPE_VIDEO_FORMAT_HEVC:
  context->templat.max_references = num_render_targets;
- context->desc.h265.pps = CALLOC_STRUCT(pipe_h265_pps);
- if (!context->desc.h265.pps) {
-FREE(context);
-return VA_STATUS_ERROR_ALLOCATION_FAILED;
- }
- context->desc.h265.pps->sps = CALLOC_STRUCT(pipe_h265_sps);
- if (!context->desc.h265.pps->sps) {
-FREE(context->desc.h265.pps);
-FREE(context);
-return VA_STATUS_ERROR_ALLOCATION_FAILED;
+ if (config->entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+context->desc.h265.pps = CALLOC_STRUCT(pipe_h265_pps);
+if (!context->desc.h265.pps) {
+   FREE(context);
+   return VA_STATUS_ERROR_ALLOCATION_FAILED;
+}
+context->desc.h265.pps->sps = CALLOC_STRUCT(pipe_h265_sps);
+if (!context->desc.h265.pps->sps) {
+   FREE(context->desc.h265.pps);
+   FREE(context);
+   return VA_STATUS_ERROR_ALLOCATION_FAILED;
+}
  }
  break;
 
-- 
2.7.4

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[Mesa-dev] [PATCH 10/12] st/va: add HEVC encode functions

[boyuan.zhang]

From: Boyuan Zhang 

Add a separate file for HEVC encode functions.

Signed-off-by: Boyuan Zhang 
Acked-by: Christian König 
---
 src/gallium/state_trackers/va/Makefile.sources   |  1 +
 src/gallium/state_trackers/va/meson.build|  2 +-
 src/gallium/state_trackers/va/picture.c  | 31 +-
 src/gallium/state_trackers/va/picture_hevc_enc.c | 75 
 src/gallium/state_trackers/va/va_private.h   |  6 ++
 5 files changed, 111 insertions(+), 4 deletions(-)
 create mode 100644 src/gallium/state_trackers/va/picture_hevc_enc.c

diff --git a/src/gallium/state_trackers/va/Makefile.sources 
b/src/gallium/state_trackers/va/Makefile.sources
index 8a69828..f3a13f2 100644
--- a/src/gallium/state_trackers/va/Makefile.sources
+++ b/src/gallium/state_trackers/va/Makefile.sources
@@ -10,6 +10,7 @@ C_SOURCES := \
picture_h264.c \
picture_h264_enc.c \
picture_hevc.c \
+   picture_hevc_enc.c \
picture_vc1.c \
picture_mjpeg.c \
postproc.c \
diff --git a/src/gallium/state_trackers/va/meson.build 
b/src/gallium/state_trackers/va/meson.build
index 0dec48c..bddd5ef 100644
--- a/src/gallium/state_trackers/va/meson.build
+++ b/src/gallium/state_trackers/va/meson.build
@@ -26,7 +26,7 @@ libva_st = static_library(
 'buffer.c', 'config.c', 'context.c', 'display.c', 'image.c', 'picture.c',
 'picture_mpeg12.c', 'picture_mpeg4.c', 'picture_h264.c', 'picture_hevc.c',
 'picture_vc1.c', 'picture_mjpeg.c', 'postproc.c', 'subpicture.c',
-'surface.c', 'picture_h264_enc.c',
+'surface.c', 'picture_h264_enc.c', 'picture_hevc_enc.c',
   ),
   c_args : [
 c_vis_args,
diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index 57f53ac..240f25a 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -316,6 +316,10 @@ handleVAEncMiscParameterTypeRateControl(vlVaContext 
*context, VAEncMiscParameter
   status = vlVaHandleVAEncMiscParameterTypeRateControlH264(context, misc);
   break;
 
+   case PIPE_VIDEO_FORMAT_HEVC:
+  status = vlVaHandleVAEncMiscParameterTypeRateControlHEVC(context, misc);
+  break;
+
default:
   break;
}
@@ -333,6 +337,10 @@ handleVAEncMiscParameterTypeFrameRate(vlVaContext 
*context, VAEncMiscParameterBu
   status = vlVaHandleVAEncMiscParameterTypeFrameRateH264(context, misc);
   break;
 
+   case PIPE_VIDEO_FORMAT_HEVC:
+  status = vlVaHandleVAEncMiscParameterTypeFrameRateHEVC(context, misc);
+  break;
+
default:
   break;
}
@@ -350,6 +358,10 @@ handleVAEncSequenceParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vl
   status = vlVaHandleVAEncSequenceParameterBufferTypeH264(drv, context, 
buf);
   break;
 
+   case PIPE_VIDEO_FORMAT_HEVC:
+  status = vlVaHandleVAEncSequenceParameterBufferTypeHEVC(drv, context, 
buf);
+  break;
+
default:
   break;
}
@@ -390,6 +402,10 @@ handleVAEncPictureParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlV
   status = vlVaHandleVAEncPictureParameterBufferTypeH264(drv, context, 
buf);
   break;
 
+   case PIPE_VIDEO_FORMAT_HEVC:
+  status = vlVaHandleVAEncPictureParameterBufferTypeHEVC(drv, context, 
buf);
+  break;
+
default:
   break;
}
@@ -407,6 +423,10 @@ handleVAEncSliceParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlVaB
   status = vlVaHandleVAEncSliceParameterBufferTypeH264(drv, context, buf);
   break;
 
+   case PIPE_VIDEO_FORMAT_HEVC:
+  status = vlVaHandleVAEncSliceParameterBufferTypeHEVC(drv, context, buf);
+  break;
+
default:
   break;
}
@@ -600,8 +620,11 @@ vlVaEndPicture(VADriverContextP ctx, VAContextID 
context_id)
 
if (context->decoder->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
   coded_buf = context->coded_buf;
-  getEncParamPresetH264(context);
-  context->desc.h264enc.frame_num_cnt++;
+  if (u_reduce_video_profile(context->templat.profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
+ getEncParamPresetH264(context);
+ context->desc.h264enc.frame_num_cnt++;
+  } else if (u_reduce_video_profile(context->templat.profile) == 
PIPE_VIDEO_FORMAT_HEVC)
+ getEncParamPresetH265(context);
   context->decoder->begin_frame(context->decoder, context->target, 
>desc.base);
   context->decoder->encode_bitstream(context->decoder, context->target,
  coded_buf->derived_surface.resource, 
);
@@ -630,7 +653,9 @@ vlVaEndPicture(VADriverContextP ctx, VAContextID context_id)
 context->first_single_submitted = false;
  surf->force_flushed = true;
   }
-   }
+   } else if (context->decoder->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE &&
+  u_reduce_video_profile(context->templat.profile) == 
PIPE_VIDEO_FORMAT_HEVC)
+  

[Mesa-dev] [PATCH 11/12] st/va: implement HEVC encode functions

[boyuan.zhang]

From: Boyuan Zhang 

Implement HEVC encode functions based on VAAPI HEVC encode interface.

Signed-off-by: Boyuan Zhang 
Acked-by: Christian König 
---
 src/gallium/state_trackers/va/picture_hevc_enc.c | 150 ++-
 1 file changed, 144 insertions(+), 6 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture_hevc_enc.c 
b/src/gallium/state_trackers/va/picture_hevc_enc.c
index 4b56207..8906901 100644
--- a/src/gallium/state_trackers/va/picture_hevc_enc.c
+++ b/src/gallium/state_trackers/va/picture_hevc_enc.c
@@ -32,7 +32,50 @@
 VAStatus
 vlVaHandleVAEncPictureParameterBufferTypeHEVC(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *buf)
 {
-   /* TODO */
+   VAEncPictureParameterBufferHEVC *h265;
+   vlVaBuffer *coded_buf;
+   int i;
+
+   h265 = buf->data;
+   context->desc.h265enc.decoded_curr_pic = h265->decoded_curr_pic.picture_id;
+
+   for (i = 0; i < 15; i++)
+  context->desc.h265enc.reference_frames[i] = 
h265->reference_frames[i].picture_id;
+
+   context->desc.h265enc.pic_order_cnt = h265->decoded_curr_pic.pic_order_cnt;
+   coded_buf = handle_table_get(drv->htab, h265->coded_buf);
+
+   if (!coded_buf->derived_surface.resource)
+  coded_buf->derived_surface.resource = 
pipe_buffer_create(drv->pipe->screen, PIPE_BIND_VERTEX_BUFFER,
+PIPE_USAGE_STREAM, 
coded_buf->size);
+
+   context->coded_buf = coded_buf;
+   context->desc.h265enc.pic.log2_parallel_merge_level_minus2 = 
h265->log2_parallel_merge_level_minus2;
+   context->desc.h265enc.pic.nal_unit_type = h265->nal_unit_type;
+   context->desc.h265enc.rc.quant_i_frames = h265->pic_init_qp;
+
+   switch(h265->pic_fields.bits.coding_type) {
+   case 1:
+  if (h265->pic_fields.bits.idr_pic_flag)
+ context->desc.h265enc.picture_type = PIPE_H265_ENC_PICTURE_TYPE_IDR;
+  else
+ context->desc.h265enc.picture_type = PIPE_H265_ENC_PICTURE_TYPE_I;
+  break;
+   case 2:
+  context->desc.h265enc.picture_type = PIPE_H265_ENC_PICTURE_TYPE_P;
+  break;
+   case 3:
+   case 4:
+   case 5:
+  return VA_STATUS_ERROR_UNIMPLEMENTED; //no b frame support
+  break;
+   }
+
+   context->desc.h265enc.pic.constrained_intra_pred_flag = 
h265->pic_fields.bits.constrained_intra_pred_flag;
+
+   util_hash_table_set(context->desc.h265enc.frame_idx,
+   UINT_TO_PTR(h265->decoded_curr_pic.picture_id),
+   UINT_TO_PTR(context->desc.h265enc.frame_num));
 
return VA_STATUS_SUCCESS;
 }
@@ -40,7 +83,33 @@ vlVaHandleVAEncPictureParameterBufferTypeHEVC(vlVaDriver 
*drv, vlVaContext *cont
 VAStatus
 vlVaHandleVAEncSliceParameterBufferTypeHEVC(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *buf)
 {
-   /* TODO */
+   VAEncSliceParameterBufferHEVC *h265;
+
+   h265 = buf->data;
+   context->desc.h265enc.ref_idx_l0 = VA_INVALID_ID;
+   context->desc.h265enc.ref_idx_l1 = VA_INVALID_ID;
+
+   for (int i = 0; i < 15; i++) {
+  if (h265->ref_pic_list0[i].picture_id != VA_INVALID_ID) {
+ if (context->desc.h265enc.ref_idx_l0 == VA_INVALID_ID)
+context->desc.h265enc.ref_idx_l0 = 
PTR_TO_UINT(util_hash_table_get(context->desc.h265enc.frame_idx,
+   
UINT_TO_PTR(h265->ref_pic_list0[i].picture_id)));
+  }
+  if (h265->ref_pic_list1[i].picture_id != VA_INVALID_ID && 
h265->slice_type == 1) {
+ if (context->desc.h265enc.ref_idx_l1 == VA_INVALID_ID)
+context->desc.h265enc.ref_idx_l1 = 
PTR_TO_UINT(util_hash_table_get(context->desc.h265enc.frame_idx,
+   
UINT_TO_PTR(h265->ref_pic_list1[i].picture_id)));
+  }
+   }
+
+   context->desc.h265enc.slice.max_num_merge_cand = h265->max_num_merge_cand;
+   context->desc.h265enc.slice.slice_cb_qp_offset = h265->slice_cb_qp_offset;
+   context->desc.h265enc.slice.slice_cr_qp_offset = h265->slice_cr_qp_offset;
+   context->desc.h265enc.slice.slice_beta_offset_div2 = 
h265->slice_beta_offset_div2;
+   context->desc.h265enc.slice.slice_tc_offset_div2 = 
h265->slice_tc_offset_div2;
+   context->desc.h265enc.slice.cabac_init_flag = 
h265->slice_fields.bits.cabac_init_flag;
+   context->desc.h265enc.slice.slice_deblocking_filter_disabled_flag = 
h265->slice_fields.bits.slice_deblocking_filter_disabled_flag;
+   context->desc.h265enc.slice.slice_loop_filter_across_slices_enabled_flag = 
h265->slice_fields.bits.slice_loop_filter_across_slices_enabled_flag;
 
return VA_STATUS_SUCCESS;
 }
@@ -48,7 +117,38 @@ vlVaHandleVAEncSliceParameterBufferTypeHEVC(vlVaDriver 
*drv, vlVaContext *contex
 VAStatus
 vlVaHandleVAEncSequenceParameterBufferTypeHEVC(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *buf)
 {
-   /* TODO */
+   VAEncSequenceParameterBufferHEVC *h265 = (VAEncSequenceParameterBufferHEVC 
*)buf->data;
+
+   if (!context->decoder) {
+  context->templat.level = 

[Mesa-dev] [PATCH 04/12] radeon/vcn: add ib implementations for HEVC

[boyuan.zhang]

From: Boyuan Zhang 

Implement required ibs for vcn HEVC encode.

Signed-off-by: Boyuan Zhang 
Acked-by: Christian König 
---
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 267 
 1 file changed, 222 insertions(+), 45 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 06b8092..a651f7e 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -231,6 +231,27 @@ static void radeon_enc_session_init(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
+{
+   enc->enc_pic.session_init.encode_standard = 
RENCODE_ENCODE_STANDARD_HEVC;
+   enc->enc_pic.session_init.aligned_picture_width = 
align(enc->base.width, 64);
+   enc->enc_pic.session_init.aligned_picture_height = 
align(enc->base.height, 16);
+   enc->enc_pic.session_init.padding_width = 
enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
+   enc->enc_pic.session_init.padding_height = 
enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
+   enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
+   enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
+
+   RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
+   RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
+   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
+   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
+   RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
+   RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
+   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
+   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_layer_control(struct radeon_encoder *enc)
 {
enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
@@ -262,6 +283,19 @@ static void radeon_enc_slice_control(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
+{
+   enc->enc_pic.hevc_slice_ctrl.slice_control_mode = 
RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
+   enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice = 
align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
+   
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment = 
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
+
+   RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SLICE_CONTROL);
+   RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
 {
enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
@@ -283,27 +317,68 @@ static void radeon_enc_spec_misc(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc, struct 
pipe_picture_desc *picture)
+{
+   struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;
+   enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 = 
pic->seq.log2_min_luma_coding_block_size_minus3;
+   enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
+   enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled = 
pic->seq.strong_intra_smoothing_enabled_flag;
+   enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = 
pic->pic.constrained_intra_pred_flag;
+   enc->enc_pic.hevc_spec_misc.cabac_init_flag = 
pic->slice.cabac_init_flag;
+   enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
+   enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
+
+   RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SPEC_MISC);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_rc_session_init(struct radeon_encoder *enc, struct 
pipe_picture_desc *picture)
 {
-   struct pipe_h264_enc_picture_desc *pic = (struct 
pipe_h264_enc_picture_desc *)picture;
-   

[Mesa-dev] [PATCH 05/12] radeon/vcn: add header implementations for HEVC

[boyuan.zhang]

From: Boyuan Zhang 

Implement encoding of sps, pps, vps, aud, and slice headers for HEVC
based on HEVC specs.

Signed-off-by: Boyuan Zhang 
Acked-by: Christian König 
---
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 348 +++-
 1 file changed, 347 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index a651f7e..c86c2f3 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -551,6 +551,86 @@ static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
+{
+   RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
+   RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
+   uint32_t *size_in_bytes = >cs->current.buf[enc->cs->current.cdw++];
+   int i;
+
+   radeon_enc_reset(enc);
+   radeon_enc_set_emulation_prevention(enc, false);
+   radeon_enc_code_fixed_bits(enc, 0x0001, 32);
+   radeon_enc_code_fixed_bits(enc, 0x4201, 16);
+   radeon_enc_byte_align(enc);
+   radeon_enc_set_emulation_prevention(enc, true);
+   radeon_enc_code_fixed_bits(enc, 0x0, 4);
+   radeon_enc_code_fixed_bits(enc, 
enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
+   radeon_enc_code_fixed_bits(enc, 0x1, 1);
+   radeon_enc_code_fixed_bits(enc, 0x0, 2);
+   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
+   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
+   radeon_enc_code_fixed_bits(enc, 0x6000, 32);
+   radeon_enc_code_fixed_bits(enc, 0xb000, 32);
+   radeon_enc_code_fixed_bits(enc, 0x0, 16);
+   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
+
+   for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; 
i++)
+   radeon_enc_code_fixed_bits(enc, 0x0, 2);
+
+   if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
+   for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); 
i < 8; i++)
+   radeon_enc_code_fixed_bits(enc, 0x0, 2);
+   }
+
+   radeon_enc_code_ue(enc, 0x0);
+   radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
+   radeon_enc_code_ue(enc, enc->enc_pic.pic_width_in_luma_samples);
+   radeon_enc_code_ue(enc, enc->enc_pic.pic_height_in_luma_samples);
+   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+   radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
+   radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
+   radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
+   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+   radeon_enc_code_ue(enc, 1);
+   radeon_enc_code_ue(enc, 0x0);
+   radeon_enc_code_ue(enc, 0x0);
+   radeon_enc_code_ue(enc, 
enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
+   //Only support CTBSize 64
+   radeon_enc_code_ue(enc, 6 - 
(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
+   radeon_enc_code_ue(enc, 
enc->enc_pic.log2_min_transform_block_size_minus2);
+   radeon_enc_code_ue(enc, 
enc->enc_pic.log2_diff_max_min_transform_block_size);
+   radeon_enc_code_ue(enc, 
enc->enc_pic.max_transform_hierarchy_depth_inter);
+   radeon_enc_code_ue(enc, 
enc->enc_pic.max_transform_hierarchy_depth_intra);
+
+   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+   radeon_enc_code_fixed_bits(enc, 
!enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
+   radeon_enc_code_fixed_bits(enc, 
enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
+   radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
+
+   radeon_enc_code_ue(enc, 1);
+   radeon_enc_code_ue(enc, 1);
+   radeon_enc_code_ue(enc, 0);
+   radeon_enc_code_ue(enc, 0);
+   radeon_enc_code_fixed_bits(enc, 0x1, 1);
+
+   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+
+   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_enc_code_fixed_bits(enc, 
enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
+
+   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+
+   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+
+   radeon_enc_code_fixed_bits(enc, 0x1, 1);
+
+   radeon_enc_byte_align(enc);
+   radeon_enc_flush_headers(enc);
+   *size_in_bytes = (enc->bits_output + 7) / 8;
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
 {
RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
@@ -586,6 +666,150 @@ static void radeon_enc_nalu_pps(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
+{
+   RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
+   

[Mesa-dev] [PATCH 06/12] st/va: move H264 enc functions into separate file

[boyuan.zhang]

From: Boyuan Zhang 

Move all H264 encode related functions into separate file. Similar to
VAAPI decode side, there will be separate file for each codec on encode
side as well.

Signed-off-by: Boyuan Zhang 
Acked-by: Christian König 
---
 src/gallium/state_trackers/va/Makefile.sources   |   1 +
 src/gallium/state_trackers/va/meson.build|   2 +-
 src/gallium/state_trackers/va/picture.c  | 188 ++---
 src/gallium/state_trackers/va/picture_h264_enc.c | 202 +++
 src/gallium/state_trackers/va/va_private.h   |   6 +
 5 files changed, 260 insertions(+), 139 deletions(-)
 create mode 100644 src/gallium/state_trackers/va/picture_h264_enc.c

diff --git a/src/gallium/state_trackers/va/Makefile.sources 
b/src/gallium/state_trackers/va/Makefile.sources
index 2d6546b..8a69828 100644
--- a/src/gallium/state_trackers/va/Makefile.sources
+++ b/src/gallium/state_trackers/va/Makefile.sources
@@ -8,6 +8,7 @@ C_SOURCES := \
picture_mpeg12.c \
picture_mpeg4.c \
picture_h264.c \
+   picture_h264_enc.c \
picture_hevc.c \
picture_vc1.c \
picture_mjpeg.c \
diff --git a/src/gallium/state_trackers/va/meson.build 
b/src/gallium/state_trackers/va/meson.build
index 56e68e9..0dec48c 100644
--- a/src/gallium/state_trackers/va/meson.build
+++ b/src/gallium/state_trackers/va/meson.build
@@ -26,7 +26,7 @@ libva_st = static_library(
 'buffer.c', 'config.c', 'context.c', 'display.c', 'image.c', 'picture.c',
 'picture_mpeg12.c', 'picture_mpeg4.c', 'picture_h264.c', 'picture_hevc.c',
 'picture_vc1.c', 'picture_mjpeg.c', 'postproc.c', 'subpicture.c',
-'surface.c',
+'surface.c', 'picture_h264_enc.c',
   ),
   c_args : [
 c_vis_args,
diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index 8951573..d5fa947 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -99,46 +99,6 @@ vlVaGetReferenceFrame(vlVaDriver *drv, VASurfaceID 
surface_id,
   *ref_frame = NULL;
 }
 
-static void
-getEncParamPreset(vlVaContext *context)
-{
-   //motion estimation preset
-   context->desc.h264enc.motion_est.motion_est_quarter_pixel = 0x0001;
-   context->desc.h264enc.motion_est.lsmvert = 0x0002;
-   context->desc.h264enc.motion_est.enc_disable_sub_mode = 0x0078;
-   context->desc.h264enc.motion_est.enc_en_ime_overw_dis_subm = 0x0001;
-   context->desc.h264enc.motion_est.enc_ime_overw_dis_subm_no = 0x0001;
-   context->desc.h264enc.motion_est.enc_ime2_search_range_x = 0x0004;
-   context->desc.h264enc.motion_est.enc_ime2_search_range_y = 0x0004;
-
-   //pic control preset
-   context->desc.h264enc.pic_ctrl.enc_cabac_enable = 0x0001;
-   context->desc.h264enc.pic_ctrl.enc_constraint_set_flags = 0x0040;
-
-   //rate control
-   context->desc.h264enc.rate_ctrl.vbv_buffer_size = 2000;
-   context->desc.h264enc.rate_ctrl.vbv_buf_lv = 48;
-   context->desc.h264enc.rate_ctrl.fill_data_enable = 1;
-   context->desc.h264enc.rate_ctrl.enforce_hrd = 1;
-   context->desc.h264enc.enable_vui = false;
-   if (context->desc.h264enc.rate_ctrl.frame_rate_num == 0 ||
-   context->desc.h264enc.rate_ctrl.frame_rate_den == 0) {
- context->desc.h264enc.rate_ctrl.frame_rate_num = 30;
- context->desc.h264enc.rate_ctrl.frame_rate_den = 1;
-   }
-   context->desc.h264enc.rate_ctrl.target_bits_picture =
-  context->desc.h264enc.rate_ctrl.target_bitrate *
-  ((float)context->desc.h264enc.rate_ctrl.frame_rate_den /
-  context->desc.h264enc.rate_ctrl.frame_rate_num);
-   context->desc.h264enc.rate_ctrl.peak_bits_picture_integer =
-  context->desc.h264enc.rate_ctrl.peak_bitrate *
-  ((float)context->desc.h264enc.rate_ctrl.frame_rate_den /
-  context->desc.h264enc.rate_ctrl.frame_rate_num);
-
-   context->desc.h264enc.rate_ctrl.peak_bits_picture_fraction = 0;
-   context->desc.h264enc.ref_pic_mode = 0x0201;
-}
-
 static VAStatus
 handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext *context, vlVaBuffer 
*buf)
 {
@@ -349,55 +309,52 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
 static VAStatus
 handleVAEncMiscParameterTypeRateControl(vlVaContext *context, 
VAEncMiscParameterBuffer *misc)
 {
-   VAEncMiscParameterRateControl *rc = (VAEncMiscParameterRateControl 
*)misc->data;
-   if (context->desc.h264enc.rate_ctrl.rate_ctrl_method ==
-   PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT)
-  context->desc.h264enc.rate_ctrl.target_bitrate = rc->bits_per_second;
-   else
-  context->desc.h264enc.rate_ctrl.target_bitrate = rc->bits_per_second * 
(rc->target_percentage / 100.0);
-   context->desc.h264enc.rate_ctrl.peak_bitrate = rc->bits_per_second;
-   if (context->desc.h264enc.rate_ctrl.target_bitrate < 200)
-  context->desc.h264enc.rate_ctrl.vbv_buffer_size = 

[Mesa-dev] [PATCH 02/12] radeon/vcn: add vcn encode interface for HEVC

[boyuan.zhang]

From: Boyuan Zhang 

Add vcn encode interface for HEVC, and rename radeon_enc_h264_enc_pic
to radeon_enc_pic since radeon_enc_pic is used by both H264 and HEVC.

Signed-off-by: Boyuan Zhang 
Acked-by: Christian König 
---
 src/gallium/drivers/radeon/radeon_vcn_enc.h | 81 -
 1 file changed, 79 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.h 
b/src/gallium/drivers/radeon/radeon_vcn_enc.h
index 0385860..86b4136 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.h
@@ -48,6 +48,10 @@
 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER   0x0010
 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU0x0020
 
+#define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL0x0011
+#define RENCODE_HEVC_IB_PARAM_SPEC_MISC0x0012
+#define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER0x0013
+
 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL0x0021
 #define RENCODE_H264_IB_PARAM_SPEC_MISC0x0022
 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS0x0023
@@ -67,6 +71,7 @@
 #define RENCODE_IF_MINOR_VERSION_MASK  0x
 #define RENCODE_IF_MINOR_VERSION_SHIFT 0
 
+#define RENCODE_ENCODE_STANDARD_HEVC   0
 #define RENCODE_ENCODE_STANDARD_H264   1
 
 #define RENCODE_PREENCODE_MODE_NONE0x
@@ -77,6 +82,9 @@
 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS  0x
 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_BITS 0x0001
 
+#define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS 0x
+#define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_BITS 0x0001
+
 #define RENCODE_RATE_CONTROL_METHOD_NONE   0x
 #define RENCODE_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR0x0001
 #define RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR   0x0002
@@ -95,6 +103,11 @@
 #define RENCODE_HEADER_INSTRUCTION_END 0x
 #define RENCODE_HEADER_INSTRUCTION_COPY0x0001
 
+#define RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END0x0001
+#define RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE0x00010001
+#define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT  0x00010002
+#define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00010003
+
 #define RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB   0x0002
 #define RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00020001
 
@@ -181,6 +194,25 @@ typedef struct rvcn_enc_h264_slice_control_s
 };
 } rvcn_enc_h264_slice_control_t;
 
+typedef struct rvcn_enc_hevc_slice_control_s
+{
+uint32_t   slice_control_mode;
+union
+{
+struct
+{
+uint32_t   num_ctbs_per_slice;
+uint32_t   num_ctbs_per_slice_segment;
+} fixed_ctbs_per_slice;
+
+struct
+{
+uint32_t   num_bits_per_slice;
+uint32_t   num_bits_per_slice_segment;
+} fixed_bits_per_slice;
+};
+} rvcn_enc_hevc_slice_control_t;
+
 typedef struct rvcn_enc_h264_spec_misc_s
 {
 uint32_t   constrained_intra_pred_flag;
@@ -192,6 +224,17 @@ typedef struct rvcn_enc_h264_spec_misc_s
 uint32_t   level_idc;
 } rvcn_enc_h264_spec_misc_t;
 
+typedef struct rvcn_enc_hevc_spec_misc_s
+{
+uint32_t   log2_min_luma_coding_block_size_minus3;
+uint32_t   amp_disabled;
+uint32_t   strong_intra_smoothing_enabled;
+uint32_t   constrained_intra_pred_flag;
+uint32_t   cabac_init_flag;
+uint32_t   half_pel_enabled;
+uint32_t   quarter_pel_enabled;
+} rvcn_enc_hevc_spec_misc_t;
+
 typedef struct rvcn_enc_rate_ctl_session_init_s
 {
 uint32_t   rate_control_method;
@@ -276,6 +319,16 @@ typedef struct rvcn_enc_h264_deblocking_filter_s
 int32_tcr_qp_offset;
 } rvcn_enc_h264_deblocking_filter_t;
 
+typedef struct rvcn_enc_hevc_deblocking_filter_s
+{
+uint32_t   loop_filter_across_slices_enabled;
+int32_tdeblocking_filter_disabled;
+int32_tbeta_offset_div2;
+int32_ttc_offset_div2;
+int32_tcb_qp_offset;
+int32_tcr_qp_offset;
+} rvcn_enc_hevc_deblocking_filter_t;
+
 typedef struct rvcn_enc_intra_refresh_s
 {
 uint32_t   intra_refresh_mode;
@@ -331,7 +384,7 @@ struct pipe_video_codec *radeon_create_encoder(struct 
pipe_context *context,
struct radeon_winsys* ws,
radeon_enc_get_buffer get_buffer);
 
-struct radeon_enc_h264_enc_pic {
+struct radeon_enc_pic {
enumpipe_h264_enc_picture_type picture_type;
 
unsignedframe_num;
@@ -343,21 +396,45 @@ struct radeon_enc_h264_enc_pic {

[Mesa-dev] [PATCH 07/12] st/va: add HEVC picture desc

[boyuan.zhang]

From: Boyuan Zhang 

Add HEVC picture desc, and add codec check when creating and destroying
context.

Signed-off-by: Boyuan Zhang 
Acked-by: Christian König 
---
 src/gallium/state_trackers/va/context.c| 26 ++
 src/gallium/state_trackers/va/va_private.h |  1 +
 2 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/src/gallium/state_trackers/va/context.c 
b/src/gallium/state_trackers/va/context.c
index 78e1f19..f03b326 100644
--- a/src/gallium/state_trackers/va/context.c
+++ b/src/gallium/state_trackers/va/context.c
@@ -284,8 +284,18 @@ vlVaCreateContext(VADriverContextP ctx, VAConfigID 
config_id, int picture_width,
context->desc.base.profile = config->profile;
context->desc.base.entry_point = config->entrypoint;
if (config->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
-  context->desc.h264enc.rate_ctrl.rate_ctrl_method = config->rc;
-  context->desc.h264enc.frame_idx = util_hash_table_create(handle_hash, 
handle_compare);
+  switch (u_reduce_video_profile(context->templat.profile)) {
+  case PIPE_VIDEO_FORMAT_MPEG4_AVC:
+ context->desc.h264enc.rate_ctrl.rate_ctrl_method = config->rc;
+ context->desc.h264enc.frame_idx = util_hash_table_create(handle_hash, 
handle_compare);
+ break;
+  case PIPE_VIDEO_FORMAT_HEVC:
+ context->desc.h265enc.rc.rate_ctrl_method = config->rc;
+ context->desc.h265enc.frame_idx = util_hash_table_create(handle_hash, 
handle_compare);
+ break;
+  default:
+ break;
+  }
}
 
mtx_lock(>mutex);
@@ -314,8 +324,16 @@ vlVaDestroyContext(VADriverContextP ctx, VAContextID 
context_id)
 
if (context->decoder) {
   if (context->desc.base.entry_point == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
- if (context->desc.h264enc.frame_idx)
-util_hash_table_destroy (context->desc.h264enc.frame_idx);
+ if (u_reduce_video_profile(context->decoder->profile) ==
+ PIPE_VIDEO_FORMAT_MPEG4_AVC) {
+if (context->desc.h264enc.frame_idx)
+   util_hash_table_destroy (context->desc.h264enc.frame_idx);
+ }
+ if (u_reduce_video_profile(context->decoder->profile) ==
+ PIPE_VIDEO_FORMAT_HEVC) {
+if (context->desc.h265enc.frame_idx)
+   util_hash_table_destroy (context->desc.h265enc.frame_idx);
+ }
   } else {
  if (u_reduce_video_profile(context->decoder->profile) ==
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
diff --git a/src/gallium/state_trackers/va/va_private.h 
b/src/gallium/state_trackers/va/va_private.h
index eef75c6..9b526ea 100644
--- a/src/gallium/state_trackers/va/va_private.h
+++ b/src/gallium/state_trackers/va/va_private.h
@@ -270,6 +270,7 @@ typedef struct {
   struct pipe_h265_picture_desc h265;
   struct pipe_mjpeg_picture_desc mjpeg;
   struct pipe_h264_enc_picture_desc h264enc;
+  struct pipe_h265_enc_picture_desc h265enc;
} desc;
 
struct {
-- 
2.7.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 03/12] radeon/vcn: support picture parameters for HEVC

[boyuan.zhang]

From: Boyuan Zhang 

Pass pipe_picture_desc instead of pipe_h264_enc_picture_desc so that
it can be used for different codecs. Add functions to handle picture
parameters that will be used for HEVC encode.

Signed-off-by: Boyuan Zhang 
Acked-by: Christian König 
---
 src/gallium/drivers/radeon/radeon_vcn_enc.c | 72 +++--
 src/gallium/drivers/radeon/radeon_vcn_enc.h |  2 +-
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 11 ++--
 3 files changed, 64 insertions(+), 21 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index 06579c8..388a333 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -38,20 +38,61 @@
 #include "radeon_video.h"
 #include "radeon_vcn_enc.h"
 
-static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct 
pipe_h264_enc_picture_desc *pic)
+static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct 
pipe_picture_desc *picture)
 {
-   enc->enc_pic.picture_type = pic->picture_type;
-   enc->enc_pic.frame_num = pic->frame_num;
-   enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
-   enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
-   enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
-   enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
-   enc->enc_pic.not_referenced = pic->not_referenced;
-   enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H264_ENC_PICTURE_TYPE_IDR);
-   enc->enc_pic.crop_left = 0;
-   enc->enc_pic.crop_right = (align(enc->base.width, 16) - 
enc->base.width) / 2;
-   enc->enc_pic.crop_top = 0;
-   enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;
+   if (u_reduce_video_profile(picture->profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
+  struct pipe_h264_enc_picture_desc *pic = (struct 
pipe_h264_enc_picture_desc *)picture;
+  enc->enc_pic.picture_type = pic->picture_type;
+  enc->enc_pic.frame_num = pic->frame_num;
+  enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+  enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+  enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+  enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+  enc->enc_pic.not_referenced = pic->not_referenced;
+  enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H264_ENC_PICTURE_TYPE_IDR);
+  enc->enc_pic.crop_left = 0;
+  enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) 
/ 2;
+  enc->enc_pic.crop_top = 0;
+  enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;
+   } else if (u_reduce_video_profile(picture->profile) == 
PIPE_VIDEO_FORMAT_HEVC) {
+  struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;
+  enc->enc_pic.picture_type = pic->picture_type;
+  enc->enc_pic.frame_num = pic->frame_num;
+  enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+  enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+  enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+  enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+  enc->enc_pic.not_referenced = pic->not_referenced;
+  enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
+(pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_I);
+  enc->enc_pic.crop_left = 0;
+  enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) 
/ 2;
+  enc->enc_pic.crop_top = 0;
+  enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;
+  enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+  enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+  enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.log2_max_poc = 0;
+  for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
+ i = (i >> 1);
+  enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+  enc->enc_pic.pic_width_in_luma_samples = 
pic->seq.pic_width_in_luma_samples;
+  enc->enc_pic.pic_height_in_luma_samples = 
pic->seq.pic_height_in_luma_samples;
+  enc->enc_pic.log2_diff_max_min_luma_coding_block_size = 
pic->seq.log2_diff_max_min_luma_coding_block_size;
+  enc->enc_pic.log2_min_transform_block_size_minus2 = 
pic->seq.log2_min_transform_block_size_minus2;
+  enc->enc_pic.log2_diff_max_min_transform_block_size = 
pic->seq.log2_diff_max_min_transform_block_size;
+  enc->enc_pic.max_transform_hierarchy_depth_inter = 
pic->seq.max_transform_hierarchy_depth_inter;
+  enc->enc_pic.max_transform_hierarchy_depth_intra = 
pic->seq.max_transform_hierarchy_depth_intra;
+  enc->enc_pic.log2_parallel_merge_level_minus2 = 
pic->pic.log2_parallel_merge_level_minus2;
+  

[Mesa-dev] [PATCH 01/12] vl: add parameters for HEVC encode

[boyuan.zhang]

From: Boyuan Zhang 

Add HEVC encode interface

Signed-off-by: Boyuan Zhang 
Acked-by: Christian König 
---
 src/gallium/include/pipe/p_video_state.h | 99 
 1 file changed, 99 insertions(+)

diff --git a/src/gallium/include/pipe/p_video_state.h 
b/src/gallium/include/pipe/p_video_state.h
index 5a88e6c..2533ba4 100644
--- a/src/gallium/include/pipe/p_video_state.h
+++ b/src/gallium/include/pipe/p_video_state.h
@@ -120,6 +120,15 @@ enum pipe_h264_enc_picture_type
PIPE_H264_ENC_PICTURE_TYPE_SKIP = 0x04
 };
 
+enum pipe_h265_enc_picture_type
+{
+   PIPE_H265_ENC_PICTURE_TYPE_P = 0x00,
+   PIPE_H265_ENC_PICTURE_TYPE_B = 0x01,
+   PIPE_H265_ENC_PICTURE_TYPE_I = 0x02,
+   PIPE_H265_ENC_PICTURE_TYPE_IDR = 0x03,
+   PIPE_H265_ENC_PICTURE_TYPE_SKIP = 0x04
+};
+
 enum pipe_h264_enc_rate_control_method
 {
PIPE_H264_ENC_RATE_CONTROL_METHOD_DISABLE = 0x00,
@@ -129,6 +138,15 @@ enum pipe_h264_enc_rate_control_method
PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE = 0x04
 };
 
+enum pipe_h265_enc_rate_control_method
+{
+   PIPE_H265_ENC_RATE_CONTROL_METHOD_DISABLE = 0x00,
+   PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP = 0x01,
+   PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP = 0x02,
+   PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT = 0x03,
+   PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE = 0x04
+};
+
 struct pipe_picture_desc
 {
enum pipe_video_profile profile;
@@ -412,6 +430,87 @@ struct pipe_h264_enc_picture_desc
 
 };
 
+struct pipe_h265_enc_seq_param
+{
+   uint8_t  general_profile_idc;
+   uint8_t  general_level_idc;
+   uint8_t  general_tier_flag;
+   uint32_t intra_period;
+   uint16_t pic_width_in_luma_samples;
+   uint16_t pic_height_in_luma_samples;
+   uint32_t chroma_format_idc;
+   uint32_t bit_depth_luma_minus8;
+   uint32_t bit_depth_chroma_minus8;
+   bool strong_intra_smoothing_enabled_flag;
+   bool amp_enabled_flag;
+   bool sample_adaptive_offset_enabled_flag;
+   bool pcm_enabled_flag;
+   bool sps_temporal_mvp_enabled_flag;
+   uint8_t  log2_min_luma_coding_block_size_minus3;
+   uint8_t  log2_diff_max_min_luma_coding_block_size;
+   uint8_t  log2_min_transform_block_size_minus2;
+   uint8_t  log2_diff_max_min_transform_block_size;
+   uint8_t  max_transform_hierarchy_depth_inter;
+   uint8_t  max_transform_hierarchy_depth_intra;
+};
+
+struct pipe_h265_enc_pic_param
+{
+   uint8_t log2_parallel_merge_level_minus2;
+   uint8_t nal_unit_type;
+   bool constrained_intra_pred_flag;
+};
+
+struct pipe_h265_enc_slice_param
+{
+   uint8_t max_num_merge_cand;
+   int8_t slice_cb_qp_offset;
+   int8_t slice_cr_qp_offset;
+   int8_t slice_beta_offset_div2;
+   int8_t slice_tc_offset_div2;
+   bool cabac_init_flag;
+   uint32_t slice_deblocking_filter_disabled_flag;
+   bool slice_loop_filter_across_slices_enabled_flag;
+};
+
+struct pipe_h265_enc_rate_control
+{
+   enum pipe_h265_enc_rate_control_method rate_ctrl_method;
+   unsigned target_bitrate;
+   unsigned peak_bitrate;
+   unsigned frame_rate_num;
+   unsigned frame_rate_den;
+   unsigned quant_i_frames;
+   unsigned vbv_buffer_size;
+   unsigned vbv_buf_lv;
+   unsigned target_bits_picture;
+   unsigned peak_bits_picture_integer;
+   unsigned peak_bits_picture_fraction;
+   unsigned fill_data_enable;
+   unsigned enforce_hrd;
+};
+
+struct pipe_h265_enc_picture_desc
+{
+   struct pipe_picture_desc base;
+
+   struct pipe_h265_enc_seq_param seq;
+   struct pipe_h265_enc_pic_param pic;
+   struct pipe_h265_enc_slice_param slice;
+   struct pipe_h265_enc_rate_control rc;
+
+   enum pipe_h265_enc_picture_type picture_type;
+   unsigned decoded_curr_pic;
+   unsigned reference_frames[16];
+   unsigned frame_num;
+   unsigned pic_order_cnt;
+   unsigned pic_order_cnt_type;
+   unsigned ref_idx_l0;
+   unsigned ref_idx_l1;
+   bool not_referenced;
+   struct util_hash_table *frame_idx;
+};
+
 struct pipe_h265_sps
 {
uint8_t chroma_format_idc;
-- 
2.7.4

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[Mesa-dev] [PATCH 2/2] radeon/uvd: add and manage render picture list

[boyuan.zhang]

From: Boyuan Zhang 

Create a list in decoder to store all render picture buffer pointers that
currently being used in reference picture lists.

During get message buffer call, check each pointer in render_pic_list[]
within given pic->ref[] list, remove pointer that no longer being used by
pic->ref[]. Then add current render surface pointer to the render_pic_list[]
and assign the associated index to result.curr_idx.

As a result, result.curr_idx will have the correct index to represent the
current render picture, instead of the previous increamenting values.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104745

Signed-off-by: Boyuan Zhang 
Reviewed-by: Christian König 
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 2ec48039b8aa1f6a5e16f3f12483b88981d0f5d3)
---
 src/gallium/drivers/radeon/radeon_uvd.c | 29 +
 1 file changed, 25 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd.c 
b/src/gallium/drivers/radeon/radeon_uvd.c
index 032ed7c..87e7858 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -97,6 +97,8 @@ struct ruvd_decoder {
unsignedcmd;
unsignedcntl;
} reg;
+
+   void*render_pic_list[16];
 };
 
 /* flush IB to the hardware */
@@ -596,7 +598,7 @@ static struct ruvd_h265 get_h265_msg(struct ruvd_decoder 
*dec, struct pipe_video
 struct pipe_h265_picture_desc *pic)
 {
struct ruvd_h265 result;
-   unsigned i;
+   unsigned i, j;
 
memset(, 0, sizeof(result));
 
@@ -676,11 +678,28 @@ static struct ruvd_h265 get_h265_msg(struct ruvd_decoder 
*dec, struct pipe_video
result.row_height_minus1[i] = pic->pps->row_height_minus1[i];
 
result.num_delta_pocs_ref_rps_idx = pic->NumDeltaPocsOfRefRpsIdx;
-   result.curr_idx = pic->CurrPicOrderCntVal;
result.curr_poc = pic->CurrPicOrderCntVal;
 
+   for (i = 0 ; i < 16 ; i++) {
+   for (j = 0; (pic->ref[j] != NULL) && (j < 16) ; j++) {
+   if (dec->render_pic_list[i] == pic->ref[j])
+   break;
+   if (j == 15)
+   dec->render_pic_list[i] = NULL;
+   else if (pic->ref[j+1] == NULL)
+   dec->render_pic_list[i] = NULL;
+   }
+   }
+   for (i = 0 ; i < 16 ; i++) {
+   if (dec->render_pic_list[i] == NULL) {
+   dec->render_pic_list[i] = target;
+   result.curr_idx = i;
+   break;
+   }
+   }
+
vl_video_buffer_set_associated_data(target, >base,
-   (void 
*)(uintptr_t)pic->CurrPicOrderCntVal,
+   (void *)(uintptr_t)result.curr_idx,
_destroy_associated_data);
 
for (i = 0; i < 16; ++i) {
@@ -723,7 +742,7 @@ static struct ruvd_h265 get_h265_msg(struct ruvd_decoder 
*dec, struct pipe_video
memcpy(dec->it + 864, pic->pps->sps->ScalingList32x32, 2 * 64);
 
for (i = 0 ; i < 2 ; i++) {
-   for (int j = 0 ; j < 15 ; j++)
+   for (j = 0 ; j < 15 ; j++)
result.direct_reflist[i][j] = pic->RefPicList[i][j];
}
 
@@ -1407,6 +1426,8 @@ struct pipe_video_codec 
*si_common_uvd_create_decoder(struct pipe_context *conte
goto error;
}
 
+   for (i = 0; i < 16; i++)
+dec->render_pic_list[i] = NULL;
dec->fb_size = (info.family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA :
FB_BUFFER_SIZE;
bs_buf_size = width * height * (512 / (16 * 16));
-- 
2.7.4

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[Mesa-dev] [PATCH 1/2] radeon/vcn: add and manage render picture list

[boyuan.zhang]

From: Boyuan Zhang 

Create a list in decoder to store all render picture buffer pointers that
currently being used in reference picture lists.

During get message buffer call, check each pointer in render_pic_list[]
within given pic->ref[] list, remove pointer that no longer being used by
pic->ref[]. Then add current render surface pointer to the render_pic_list[]
and assign the associated index to result.curr_idx.

As a result, result.curr_idx will have the correct index to represent the
current render picture, instead of the previous increamenting values.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104745

Signed-off-by: Boyuan Zhang 
Reviewed-by: Christian König 
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit f2bfd1cbb7e72945ca192845a1ad28426c7aea89)
---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 28 
 1 file changed, 24 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 2ece4a3..8010010 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -78,6 +78,7 @@ struct radeon_decoder {
 
unsignedbs_size;
unsignedcur_buffer;
+   void*render_pic_list[16];
 };
 
 static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
@@ -186,7 +187,7 @@ static rvcn_dec_message_hevc_t get_h265_msg(struct 
radeon_decoder *dec,
struct pipe_h265_picture_desc *pic)
 {
rvcn_dec_message_hevc_t result;
-   unsigned i;
+   unsigned i, j;
 
memset(, 0, sizeof(result));
result.sps_info_flags = 0;
@@ -273,11 +274,28 @@ static rvcn_dec_message_hevc_t get_h265_msg(struct 
radeon_decoder *dec,
result.row_height_minus1[i] = pic->pps->row_height_minus1[i];
 
result.num_delta_pocs_ref_rps_idx = pic->NumDeltaPocsOfRefRpsIdx;
-   result.curr_idx = pic->CurrPicOrderCntVal;
result.curr_poc = pic->CurrPicOrderCntVal;
 
+   for (i = 0 ; i < 16 ; i++) {
+   for (j = 0; (pic->ref[j] != NULL) && (j < 16) ; j++) {
+   if (dec->render_pic_list[i] == pic->ref[j])
+   break;
+   if (j == 15)
+   dec->render_pic_list[i] = NULL;
+   else if (pic->ref[j+1] == NULL)
+   dec->render_pic_list[i] = NULL;
+   }
+   }
+   for (i = 0 ; i < 16 ; i++) {
+   if (dec->render_pic_list[i] == NULL) {
+   dec->render_pic_list[i] = target;
+   result.curr_idx = i;
+   break;
+   }
+   }
+
vl_video_buffer_set_associated_data(target, >base,
-   (void 
*)(uintptr_t)pic->CurrPicOrderCntVal,
+   (void *)(uintptr_t)result.curr_idx,

_dec_destroy_associated_data);
 
for (i = 0; i < 16; ++i) {
@@ -320,7 +338,7 @@ static rvcn_dec_message_hevc_t get_h265_msg(struct 
radeon_decoder *dec,
memcpy(dec->it + 864, pic->pps->sps->ScalingList32x32, 2 * 64);
 
for (i = 0 ; i < 2 ; i++) {
-   for (int j = 0 ; j < 15 ; j++)
+   for (j = 0 ; j < 15 ; j++)
result.direct_reflist[i][j] = pic->RefPicList[i][j];
}
 
@@ -1236,6 +1254,8 @@ struct pipe_video_codec *radeon_create_decoder(struct 
pipe_context *context,
goto error;
}
 
+   for (i = 0; i < 16; i++)
+   dec->render_pic_list[i] = NULL;
bs_buf_size = width * height * (512 / (16 * 16));
for (i = 0; i < NUM_BUFFERS; ++i) {
unsigned msg_fb_it_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
-- 
2.7.4

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[Mesa-dev] [PATCH 09/12] st/va: enable dual instances encode only for H264

[boyuan.zhang]

From: Boyuan Zhang 

Logics that related to dual instances encode should only be done for
H264, not other codecs.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/state_trackers/va/picture.c |  3 ++-
 src/gallium/state_trackers/va/surface.c | 23 +--
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index 77d379b..537e931 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -650,7 +650,8 @@ vlVaEndPicture(VADriverContextP ctx, VAContextID context_id)
}
 
context->decoder->end_frame(context->decoder, context->target, 
>desc.base);
-   if (context->decoder->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+   if (context->decoder->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE &&
+  u_reduce_video_profile(context->templat.profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
   int idr_period = context->desc.h264enc.gop_size / context->gop_coeff;
   int p_remain_in_idr = idr_period - context->desc.h264enc.frame_num;
   surf->frame_num_cnt = context->desc.h264enc.frame_num_cnt;
diff --git a/src/gallium/state_trackers/va/surface.c 
b/src/gallium/state_trackers/va/surface.c
index 636505b..9823232 100644
--- a/src/gallium/state_trackers/va/surface.c
+++ b/src/gallium/state_trackers/va/surface.c
@@ -36,6 +36,7 @@
 #include "util/u_rect.h"
 #include "util/u_sampler.h"
 #include "util/u_surface.h"
+#include "util/u_video.h"
 
 #include "vl/vl_compositor.h"
 #include "vl/vl_video_buffer.h"
@@ -122,16 +123,18 @@ vlVaSyncSurface(VADriverContextP ctx, VASurfaceID 
render_target)
}
 
if (context->decoder->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
-  int frame_diff;
-  if (context->desc.h264enc.frame_num_cnt >= surf->frame_num_cnt)
- frame_diff = context->desc.h264enc.frame_num_cnt - 
surf->frame_num_cnt;
-  else
- frame_diff = 0x - surf->frame_num_cnt + 1 + 
context->desc.h264enc.frame_num_cnt;
-  if ((frame_diff == 0) &&
-  (surf->force_flushed == false) &&
-  (context->desc.h264enc.frame_num_cnt % 2 != 0)) {
- context->decoder->flush(context->decoder);
- context->first_single_submitted = true;
+  if (u_reduce_video_profile(context->templat.profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
+ int frame_diff;
+ if (context->desc.h264enc.frame_num_cnt >= surf->frame_num_cnt)
+frame_diff = context->desc.h264enc.frame_num_cnt - 
surf->frame_num_cnt;
+ else
+frame_diff = 0x - surf->frame_num_cnt + 1 + 
context->desc.h264enc.frame_num_cnt;
+ if ((frame_diff == 0) &&
+ (surf->force_flushed == false) &&
+ (context->desc.h264enc.frame_num_cnt % 2 != 0)) {
+context->decoder->flush(context->decoder);
+context->first_single_submitted = true;
+ }
   }
   context->decoder->get_feedback(context->decoder, surf->feedback, 
&(surf->coded_buf->coded_size));
   surf->feedback = NULL;
-- 
2.7.4

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[Mesa-dev] [PATCH 06/12] st/va: move H264 enc functions into separate file

[boyuan.zhang]

From: Boyuan Zhang 

Move all H264 encode related functions into separate file. Similar to
VAAPI decode side, there will be separate file for each codec on encode
side as well.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/state_trackers/va/Makefile.sources   |   1 +
 src/gallium/state_trackers/va/picture.c  | 146 +++-
 src/gallium/state_trackers/va/picture_h264_enc.c | 163 +++
 src/gallium/state_trackers/va/va_private.h   |   5 +
 4 files changed, 218 insertions(+), 97 deletions(-)
 create mode 100644 src/gallium/state_trackers/va/picture_h264_enc.c

diff --git a/src/gallium/state_trackers/va/Makefile.sources 
b/src/gallium/state_trackers/va/Makefile.sources
index 2d6546b..8a69828 100644
--- a/src/gallium/state_trackers/va/Makefile.sources
+++ b/src/gallium/state_trackers/va/Makefile.sources
@@ -8,6 +8,7 @@ C_SOURCES := \
picture_mpeg12.c \
picture_mpeg4.c \
picture_h264.c \
+   picture_h264_enc.c \
picture_hevc.c \
picture_vc1.c \
picture_mjpeg.c \
diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index 8951573..77d379b 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -349,55 +349,52 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
 static VAStatus
 handleVAEncMiscParameterTypeRateControl(vlVaContext *context, 
VAEncMiscParameterBuffer *misc)
 {
-   VAEncMiscParameterRateControl *rc = (VAEncMiscParameterRateControl 
*)misc->data;
-   if (context->desc.h264enc.rate_ctrl.rate_ctrl_method ==
-   PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT)
-  context->desc.h264enc.rate_ctrl.target_bitrate = rc->bits_per_second;
-   else
-  context->desc.h264enc.rate_ctrl.target_bitrate = rc->bits_per_second * 
(rc->target_percentage / 100.0);
-   context->desc.h264enc.rate_ctrl.peak_bitrate = rc->bits_per_second;
-   if (context->desc.h264enc.rate_ctrl.target_bitrate < 200)
-  context->desc.h264enc.rate_ctrl.vbv_buffer_size = 
MIN2((context->desc.h264enc.rate_ctrl.target_bitrate * 2.75), 200);
-   else
-  context->desc.h264enc.rate_ctrl.vbv_buffer_size = 
context->desc.h264enc.rate_ctrl.target_bitrate;
+   VAStatus status = VA_STATUS_SUCCESS;
 
-   return VA_STATUS_SUCCESS;
+   switch (u_reduce_video_profile(context->templat.profile)) {
+   case PIPE_VIDEO_FORMAT_MPEG4_AVC:
+  status = vlVaHandleVAEncMiscParameterTypeRateControlH264(context, misc);
+  break;
+
+   default:
+  break;
+   }
+
+   return status;
 }
 
 static VAStatus
 handleVAEncMiscParameterTypeFrameRate(vlVaContext *context, 
VAEncMiscParameterBuffer *misc)
 {
-   VAEncMiscParameterFrameRate *fr = (VAEncMiscParameterFrameRate *)misc->data;
-   if (fr->framerate & 0x) {
-  context->desc.h264enc.rate_ctrl.frame_rate_num = fr->framerate   & 
0x;
-  context->desc.h264enc.rate_ctrl.frame_rate_den = fr->framerate >> 16 & 
0x;
-   } else {
-  context->desc.h264enc.rate_ctrl.frame_rate_num = fr->framerate;
-  context->desc.h264enc.rate_ctrl.frame_rate_den = 1;
+   VAStatus status = VA_STATUS_SUCCESS;
+
+   switch (u_reduce_video_profile(context->templat.profile)) {
+   case PIPE_VIDEO_FORMAT_MPEG4_AVC:
+  status = vlVaHandleVAEncMiscParameterTypeFrameRateH264(context, misc);
+  break;
+
+   default:
+  break;
}
-   return VA_STATUS_SUCCESS;
+
+   return status;
 }
 
 static VAStatus
 handleVAEncSequenceParameterBufferType(vlVaDriver *drv, vlVaContext *context, 
vlVaBuffer *buf)
 {
-   VAEncSequenceParameterBufferH264 *h264 = (VAEncSequenceParameterBufferH264 
*)buf->data;
-   if (!context->decoder) {
-  context->templat.max_references = h264->max_num_ref_frames;
-  context->templat.level = h264->level_idc;
-  context->decoder = drv->pipe->create_video_codec(drv->pipe, 
>templat);
-  if (!context->decoder)
- return VA_STATUS_ERROR_ALLOCATION_FAILED;
+   VAStatus status = VA_STATUS_SUCCESS;
+
+   switch (u_reduce_video_profile(context->templat.profile)) {
+   case PIPE_VIDEO_FORMAT_MPEG4_AVC:
+  status = vlVaHandleVAEncSequenceParameterBufferTypeH264(drv, context, 
buf);
+  break;
+
+   default:
+  break;
}
 
-   context->gop_coeff = ((1024 + h264->intra_idr_period - 1) / 
h264->intra_idr_period + 1) / 2 * 2;
-   if (context->gop_coeff > VL_VA_ENC_GOP_COEFF)
-  context->gop_coeff = VL_VA_ENC_GOP_COEFF;
-   context->desc.h264enc.gop_size = h264->intra_idr_period * 
context->gop_coeff;
-   context->desc.h264enc.rate_ctrl.frame_rate_num = h264->time_scale / 2;
-   context->desc.h264enc.rate_ctrl.frame_rate_den = h264->num_units_in_tick;
-   context->desc.h264enc.pic_order_cnt_type = 
h264->seq_fields.bits.pic_order_cnt_type;
-   return VA_STATUS_SUCCESS;
+   return status;
 }
 
 static VAStatus
@@ -426,80 +423,35 @@ handleVAEncMiscParameterBufferType(vlVaContext *context, 

[Mesa-dev] [PATCH 10/12] st/va: add HEVC encode functions

[boyuan.zhang]

From: Boyuan Zhang 

Add a separate file for HEVC encode functions.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/state_trackers/va/Makefile.sources   |  1 +
 src/gallium/state_trackers/va/picture.c  | 56 +--
 src/gallium/state_trackers/va/picture_hevc_enc.c | 69 
 src/gallium/state_trackers/va/va_private.h   |  5 ++
 4 files changed, 128 insertions(+), 3 deletions(-)
 create mode 100644 src/gallium/state_trackers/va/picture_hevc_enc.c

diff --git a/src/gallium/state_trackers/va/Makefile.sources 
b/src/gallium/state_trackers/va/Makefile.sources
index 8a69828..f3a13f2 100644
--- a/src/gallium/state_trackers/va/Makefile.sources
+++ b/src/gallium/state_trackers/va/Makefile.sources
@@ -10,6 +10,7 @@ C_SOURCES := \
picture_h264.c \
picture_h264_enc.c \
picture_hevc.c \
+   picture_hevc_enc.c \
picture_vc1.c \
picture_mjpeg.c \
postproc.c \
diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index 537e931..e26996c 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -139,6 +139,31 @@ getEncParamPreset(vlVaContext *context)
context->desc.h264enc.ref_pic_mode = 0x0201;
 }
 
+static void
+getEncParamPresetH265(vlVaContext *context)
+{
+   //rate control
+   context->desc.h265enc.rc.vbv_buffer_size = 2000;
+   context->desc.h265enc.rc.vbv_buf_lv = 48;
+   context->desc.h265enc.rc.fill_data_enable = 1;
+   context->desc.h265enc.rc.enforce_hrd = 1;
+   if (context->desc.h265enc.rc.frame_rate_num == 0 ||
+ context->desc.h265enc.rc.frame_rate_den == 0) {
+  context->desc.h265enc.rc.frame_rate_num = 30;
+  context->desc.h265enc.rc.frame_rate_den = 1;
+   }
+   context->desc.h265enc.rc.target_bits_picture =
+  context->desc.h265enc.rc.target_bitrate *
+  ((float)context->desc.h265enc.rc.frame_rate_den /
+   context->desc.h265enc.rc.frame_rate_num);
+   context->desc.h265enc.rc.peak_bits_picture_integer =
+  context->desc.h265enc.rc.peak_bitrate *
+  ((float)context->desc.h265enc.rc.frame_rate_den /
+   context->desc.h265enc.rc.frame_rate_num);
+
+   context->desc.h265enc.rc.peak_bits_picture_fraction = 0;
+}
+
 static VAStatus
 handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext *context, vlVaBuffer 
*buf)
 {
@@ -356,6 +381,10 @@ handleVAEncMiscParameterTypeRateControl(vlVaContext 
*context, VAEncMiscParameter
   status = vlVaHandleVAEncMiscParameterTypeRateControlH264(context, misc);
   break;
 
+   case PIPE_VIDEO_FORMAT_HEVC:
+  status = vlVaHandleVAEncMiscParameterTypeRateControlHEVC(context, misc);
+  break;
+
default:
   break;
}
@@ -373,6 +402,10 @@ handleVAEncMiscParameterTypeFrameRate(vlVaContext 
*context, VAEncMiscParameterBu
   status = vlVaHandleVAEncMiscParameterTypeFrameRateH264(context, misc);
   break;
 
+   case PIPE_VIDEO_FORMAT_HEVC:
+  status = vlVaHandleVAEncMiscParameterTypeFrameRateHEVC(context, misc);
+  break;
+
default:
   break;
}
@@ -390,6 +423,10 @@ handleVAEncSequenceParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vl
   status = vlVaHandleVAEncSequenceParameterBufferTypeH264(drv, context, 
buf);
   break;
 
+   case PIPE_VIDEO_FORMAT_HEVC:
+  status = vlVaHandleVAEncSequenceParameterBufferTypeHEVC(drv, context, 
buf);
+  break;
+
default:
   break;
}
@@ -430,6 +467,10 @@ handleVAEncPictureParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlV
   status = vlVaHandleVAEncPictureParameterBufferTypeH264(drv, context, 
buf);
   break;
 
+   case PIPE_VIDEO_FORMAT_HEVC:
+  status = vlVaHandleVAEncPictureParameterBufferTypeHEVC(drv, context, 
buf);
+  break;
+
default:
   break;
}
@@ -447,6 +488,10 @@ handleVAEncSliceParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlVaB
   status = vlVaHandleVAEncSliceParameterBufferTypeH264(drv, context, buf);
   break;
 
+   case PIPE_VIDEO_FORMAT_HEVC:
+  status = vlVaHandleVAEncSliceParameterBufferTypeHEVC(drv, context, buf);
+  break;
+
default:
   break;
}
@@ -640,8 +685,11 @@ vlVaEndPicture(VADriverContextP ctx, VAContextID 
context_id)
 
if (context->decoder->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
   coded_buf = context->coded_buf;
-  getEncParamPreset(context);
-  context->desc.h264enc.frame_num_cnt++;
+  if (u_reduce_video_profile(context->templat.profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
+ getEncParamPreset(context);
+ context->desc.h264enc.frame_num_cnt++;
+  } else if (u_reduce_video_profile(context->templat.profile) == 
PIPE_VIDEO_FORMAT_HEVC)
+ getEncParamPresetH265(context);
   context->decoder->begin_frame(context->decoder, context->target, 
>desc.base);
   context->decoder->encode_bitstream(context->decoder, 

[Mesa-dev] [PATCH 12/12] radeonsi: enable vcn encode for HEVC main

[boyuan.zhang]

From: Boyuan Zhang 

Enable vcn encode for HEVC main profile on Raven.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeonsi/si_get.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index 1c84a25..8382721 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -588,8 +588,10 @@ static int si_get_video_param(struct pipe_screen *screen,
if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
switch (param) {
case PIPE_VIDEO_CAP_SUPPORTED:
-   return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
+   return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
(si_vce_is_fw_version_supported(sscreen) ||
+   sscreen->info.family == CHIP_RAVEN)) ||
+   (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
sscreen->info.family == CHIP_RAVEN);
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
-- 
2.7.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 11/12] st/va: implement HEVC encode functions

[boyuan.zhang]

From: Boyuan Zhang 

Implement HEVC encode functions based on VAAPI HEVC encode interface.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/state_trackers/va/picture_hevc_enc.c | 130 ++-
 1 file changed, 125 insertions(+), 5 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture_hevc_enc.c 
b/src/gallium/state_trackers/va/picture_hevc_enc.c
index 144bb8c..1f14098 100644
--- a/src/gallium/state_trackers/va/picture_hevc_enc.c
+++ b/src/gallium/state_trackers/va/picture_hevc_enc.c
@@ -32,7 +32,50 @@
 VAStatus
 vlVaHandleVAEncPictureParameterBufferTypeHEVC(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *buf)
 {
-   /* TODO */
+   VAEncPictureParameterBufferHEVC *h265;
+   vlVaBuffer *coded_buf;
+   int i;
+
+   h265 = buf->data;
+   context->desc.h265enc.decoded_curr_pic = h265->decoded_curr_pic.picture_id;
+
+   for (i = 0; i < 15; i++)
+  context->desc.h265enc.reference_frames[i] = 
h265->reference_frames[i].picture_id;
+
+   context->desc.h265enc.pic_order_cnt = h265->decoded_curr_pic.pic_order_cnt;
+   coded_buf = handle_table_get(drv->htab, h265->coded_buf);
+
+   if (!coded_buf->derived_surface.resource)
+  coded_buf->derived_surface.resource = 
pipe_buffer_create(drv->pipe->screen, PIPE_BIND_VERTEX_BUFFER,
+PIPE_USAGE_STREAM, 
coded_buf->size);
+
+   context->coded_buf = coded_buf;
+   context->desc.h265enc.pic.log2_parallel_merge_level_minus2 = 
h265->log2_parallel_merge_level_minus2;
+   context->desc.h265enc.pic.nal_unit_type = h265->nal_unit_type;
+
+   switch(h265->pic_fields.bits.coding_type) {
+   case 1:
+  if (h265->pic_fields.bits.idr_pic_flag)
+ context->desc.h265enc.picture_type = PIPE_H265_ENC_PICTURE_TYPE_IDR;
+  else
+ context->desc.h265enc.picture_type = PIPE_H265_ENC_PICTURE_TYPE_I;
+  break;
+   case 2:
+  context->desc.h265enc.picture_type = PIPE_H265_ENC_PICTURE_TYPE_P;
+  break;
+   case 3:
+   case 4:
+   case 5:
+  return VA_STATUS_ERROR_UNIMPLEMENTED; //no b frame support
+  break;
+   }
+
+   context->desc.h265enc.pic.constrained_intra_pred_flag = 
h265->pic_fields.bits.constrained_intra_pred_flag;
+   context->desc.h265enc.pic.loop_filter_across_tiles_enabled_flag = 
h265->pic_fields.bits.loop_filter_across_tiles_enabled_flag;
+
+   util_hash_table_set(context->desc.h265enc.frame_idx,
+   UINT_TO_PTR(h265->decoded_curr_pic.picture_id),
+   UINT_TO_PTR(context->desc.h265enc.frame_num));
 
return VA_STATUS_SUCCESS;
 }
@@ -40,7 +83,33 @@ vlVaHandleVAEncPictureParameterBufferTypeHEVC(vlVaDriver 
*drv, vlVaContext *cont
 VAStatus
 vlVaHandleVAEncSliceParameterBufferTypeHEVC(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *buf)
 {
-   /* TODO */
+   VAEncSliceParameterBufferHEVC *h265;
+
+   h265 = buf->data;
+   context->desc.h265enc.ref_idx_l0 = VA_INVALID_ID;
+   context->desc.h265enc.ref_idx_l1 = VA_INVALID_ID;
+
+   for (int i = 0; i < 15; i++) {
+  if (h265->ref_pic_list0[i].picture_id != VA_INVALID_ID) {
+ if (context->desc.h265enc.ref_idx_l0 == VA_INVALID_ID)
+context->desc.h265enc.ref_idx_l0 = 
PTR_TO_UINT(util_hash_table_get(context->desc.h265enc.frame_idx,
+   
UINT_TO_PTR(h265->ref_pic_list0[i].picture_id)));
+  }
+  if (h265->ref_pic_list1[i].picture_id != VA_INVALID_ID && 
h265->slice_type == 1) {
+ if (context->desc.h265enc.ref_idx_l1 == VA_INVALID_ID)
+context->desc.h265enc.ref_idx_l1 = 
PTR_TO_UINT(util_hash_table_get(context->desc.h265enc.frame_idx,
+   
UINT_TO_PTR(h265->ref_pic_list1[i].picture_id)));
+  }
+   }
+
+   context->desc.h265enc.slice.max_num_merge_cand = h265->max_num_merge_cand;
+   context->desc.h265enc.slice.slice_cb_qp_offset = h265->slice_cb_qp_offset;
+   context->desc.h265enc.slice.slice_cr_qp_offset = h265->slice_cr_qp_offset;
+   context->desc.h265enc.slice.slice_beta_offset_div2 = 
h265->slice_beta_offset_div2;
+   context->desc.h265enc.slice.slice_tc_offset_div2 = 
h265->slice_tc_offset_div2;
+   context->desc.h265enc.slice.cabac_init_flag = 
h265->slice_fields.bits.cabac_init_flag;
+   context->desc.h265enc.slice.slice_deblocking_filter_disabled_flag = 
h265->slice_fields.bits.slice_deblocking_filter_disabled_flag;
+   context->desc.h265enc.slice.slice_loop_filter_across_slices_enabled_flag = 
h265->slice_fields.bits.slice_loop_filter_across_slices_enabled_flag;
 
return VA_STATUS_SUCCESS;
 }
@@ -48,14 +117,57 @@ vlVaHandleVAEncSliceParameterBufferTypeHEVC(vlVaDriver 
*drv, vlVaContext *contex
 VAStatus
 vlVaHandleVAEncSequenceParameterBufferTypeHEVC(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *buf)
 {
-   /* TODO */
+   VAEncSequenceParameterBufferHEVC *h265 = (VAEncSequenceParameterBufferHEVC 
*)buf->data;
+
+   if (!context->decoder) {
+  context->templat.level = 

[Mesa-dev] [PATCH 02/12] radeon/vcn: add vcn encode interface for HEVC

[boyuan.zhang]

From: Boyuan Zhang 

Add vcn encode interface for HEVC, and rename radeon_enc_h264_enc_pic
to radeon_enc_pic since radeon_enc_pic is used by both H264 and HEVC.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc.h | 82 -
 1 file changed, 80 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.h 
b/src/gallium/drivers/radeon/radeon_vcn_enc.h
index 0385860..2ec42e4 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.h
@@ -48,6 +48,10 @@
 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER   0x0010
 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU0x0020
 
+#define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL0x0011
+#define RENCODE_HEVC_IB_PARAM_SPEC_MISC0x0012
+#define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER0x0013
+
 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL0x0021
 #define RENCODE_H264_IB_PARAM_SPEC_MISC0x0022
 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS0x0023
@@ -67,6 +71,7 @@
 #define RENCODE_IF_MINOR_VERSION_MASK  0x
 #define RENCODE_IF_MINOR_VERSION_SHIFT 0
 
+#define RENCODE_ENCODE_STANDARD_HEVC   0
 #define RENCODE_ENCODE_STANDARD_H264   1
 
 #define RENCODE_PREENCODE_MODE_NONE0x
@@ -77,6 +82,9 @@
 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS  0x
 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_BITS 0x0001
 
+#define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS 0x
+#define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_BITS 0x0001
+
 #define RENCODE_RATE_CONTROL_METHOD_NONE   0x
 #define RENCODE_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR0x0001
 #define RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR   0x0002
@@ -95,6 +103,11 @@
 #define RENCODE_HEADER_INSTRUCTION_END 0x
 #define RENCODE_HEADER_INSTRUCTION_COPY0x0001
 
+#define RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END0x0001
+#define RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE0x00010001
+#define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT  0x00010002
+#define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00010003
+
 #define RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB   0x0002
 #define RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00020001
 
@@ -181,6 +194,25 @@ typedef struct rvcn_enc_h264_slice_control_s
 };
 } rvcn_enc_h264_slice_control_t;
 
+typedef struct rvcn_enc_hevc_slice_control_s
+{
+uint32_t   slice_control_mode;
+union
+{
+struct
+{
+uint32_t   num_ctbs_per_slice;
+uint32_t   num_ctbs_per_slice_segment;
+} fixed_ctbs_per_slice;
+
+struct
+{
+uint32_t   num_bits_per_slice;
+uint32_t   num_bits_per_slice_segment;
+} fixed_bits_per_slice;
+};
+} rvcn_enc_hevc_slice_control_t;
+
 typedef struct rvcn_enc_h264_spec_misc_s
 {
 uint32_t   constrained_intra_pred_flag;
@@ -192,6 +224,17 @@ typedef struct rvcn_enc_h264_spec_misc_s
 uint32_t   level_idc;
 } rvcn_enc_h264_spec_misc_t;
 
+typedef struct rvcn_enc_hevc_spec_misc_s
+{
+uint32_t   log2_min_luma_coding_block_size_minus3;
+uint32_t   amp_disabled;
+uint32_t   strong_intra_smoothing_enabled;
+uint32_t   constrained_intra_pred_flag;
+uint32_t   cabac_init_flag;
+uint32_t   half_pel_enabled;
+uint32_t   quarter_pel_enabled;
+} rvcn_enc_hevc_spec_misc_t;
+
 typedef struct rvcn_enc_rate_ctl_session_init_s
 {
 uint32_t   rate_control_method;
@@ -276,6 +319,16 @@ typedef struct rvcn_enc_h264_deblocking_filter_s
 int32_tcr_qp_offset;
 } rvcn_enc_h264_deblocking_filter_t;
 
+typedef struct rvcn_enc_hevc_deblocking_filter_s
+{
+uint32_t   loop_filter_across_slices_enabled;
+int32_tdeblocking_filter_disabled;
+int32_tbeta_offset_div2;
+int32_ttc_offset_div2;
+int32_tcb_qp_offset;
+int32_tcr_qp_offset;
+} rvcn_enc_hevc_deblocking_filter_t;
+
 typedef struct rvcn_enc_intra_refresh_s
 {
 uint32_t   intra_refresh_mode;
@@ -331,7 +384,7 @@ struct pipe_video_codec *radeon_create_encoder(struct 
pipe_context *context,
struct radeon_winsys* ws,
radeon_enc_get_buffer get_buffer);
 
-struct radeon_enc_h264_enc_pic {
+struct radeon_enc_pic {
enumpipe_h264_enc_picture_type picture_type;
 
unsignedframe_num;
@@ -343,21 +396,46 @@ struct radeon_enc_h264_enc_pic {
unsignedcrop_right;
unsigned

[Mesa-dev] [PATCH 03/12] radeon/vcn: support picture parameters for HEVC

[boyuan.zhang]

From: Boyuan Zhang 

Pass pipe_picture_desc instead of pipe_h264_enc_picture_desc so that
it can be used for different codecs. Add functions to handle picture
parameters that will be used for HEVC encode.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc.c | 73 +++--
 src/gallium/drivers/radeon/radeon_vcn_enc.h |  2 +-
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 11 ++--
 3 files changed, 65 insertions(+), 21 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index 06579c8..20be5e6 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -38,20 +38,62 @@
 #include "radeon_video.h"
 #include "radeon_vcn_enc.h"
 
-static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct 
pipe_h264_enc_picture_desc *pic)
+static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct 
pipe_picture_desc *picture)
 {
-   enc->enc_pic.picture_type = pic->picture_type;
-   enc->enc_pic.frame_num = pic->frame_num;
-   enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
-   enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
-   enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
-   enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
-   enc->enc_pic.not_referenced = pic->not_referenced;
-   enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H264_ENC_PICTURE_TYPE_IDR);
-   enc->enc_pic.crop_left = 0;
-   enc->enc_pic.crop_right = (align(enc->base.width, 16) - 
enc->base.width) / 2;
-   enc->enc_pic.crop_top = 0;
-   enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;
+   if (u_reduce_video_profile(picture->profile) == 
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
+  struct pipe_h264_enc_picture_desc *pic = (struct 
pipe_h264_enc_picture_desc *)picture;
+  enc->enc_pic.picture_type = pic->picture_type;
+  enc->enc_pic.frame_num = pic->frame_num;
+  enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+  enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+  enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+  enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+  enc->enc_pic.not_referenced = pic->not_referenced;
+  enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H264_ENC_PICTURE_TYPE_IDR);
+  enc->enc_pic.crop_left = 0;
+  enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) 
/ 2;
+  enc->enc_pic.crop_top = 0;
+  enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;
+   } else if (u_reduce_video_profile(picture->profile) == 
PIPE_VIDEO_FORMAT_HEVC) {
+  struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;
+  enc->enc_pic.picture_type = pic->picture_type;
+  enc->enc_pic.frame_num = pic->frame_num;
+  enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+  enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+  enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+  enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+  enc->enc_pic.not_referenced = pic->not_referenced;
+  enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
+(pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_I);
+  enc->enc_pic.crop_left = 0;
+  enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) 
/ 2;
+  enc->enc_pic.crop_top = 0;
+  enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;
+  enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+  enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+  enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.log2_max_poc = 0;
+  for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
+ i = (i >> 1);
+  enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+  enc->enc_pic.pic_width_in_luma_samples = 
pic->seq.pic_width_in_luma_samples;
+  enc->enc_pic.pic_height_in_luma_samples = 
pic->seq.pic_height_in_luma_samples;
+  enc->enc_pic.log2_diff_max_min_luma_coding_block_size = 
pic->seq.log2_diff_max_min_luma_coding_block_size;
+  enc->enc_pic.log2_min_transform_block_size_minus2 = 
pic->seq.log2_min_transform_block_size_minus2;
+  enc->enc_pic.log2_diff_max_min_transform_block_size = 
pic->seq.log2_diff_max_min_transform_block_size;
+  enc->enc_pic.max_transform_hierarchy_depth_inter = 
pic->seq.max_transform_hierarchy_depth_inter;
+  enc->enc_pic.max_transform_hierarchy_depth_intra = 
pic->seq.max_transform_hierarchy_depth_intra;
+  enc->enc_pic.log2_parallel_merge_level_minus2 = 
pic->pic.log2_parallel_merge_level_minus2;
+  enc->enc_pic.bit_depth_luma_minus8 = 

[Mesa-dev] [PATCH 05/12] radeon/vcn: add header implementations for HEVC

[boyuan.zhang]

From: Boyuan Zhang 

Implement encoding of sps, pps, vps, aud, and slice headers for HEVC
based on HEVC specs.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 348 +++-
 1 file changed, 347 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index a651f7e..74c4a08 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -551,6 +551,86 @@ static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
+{
+   RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
+   RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
+   uint32_t *size_in_bytes = >cs->current.buf[enc->cs->current.cdw++];
+   int i;
+
+   radeon_enc_reset(enc);
+   radeon_enc_set_emulation_prevention(enc, false);
+   radeon_enc_code_fixed_bits(enc, 0x0001, 32);
+   radeon_enc_code_fixed_bits(enc, 0x4201, 16);
+   radeon_enc_byte_align(enc);
+   radeon_enc_set_emulation_prevention(enc, true);
+   radeon_enc_code_fixed_bits(enc, 0x0, 4);
+   radeon_enc_code_fixed_bits(enc, 
enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
+   radeon_enc_code_fixed_bits(enc, 0x1, 1);
+   radeon_enc_code_fixed_bits(enc, 0x0, 2);
+   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
+   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
+   radeon_enc_code_fixed_bits(enc, 0x6000, 32);
+   radeon_enc_code_fixed_bits(enc, 0xb000, 32);
+   radeon_enc_code_fixed_bits(enc, 0x0, 16);
+   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
+
+   for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; 
i++)
+   radeon_enc_code_fixed_bits(enc, 0x0, 2);
+
+   if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
+   for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); 
i < 8; i++)
+   radeon_enc_code_fixed_bits(enc, 0x0, 2);
+   }
+
+   radeon_enc_code_ue(enc, 0x0);
+   radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
+   radeon_enc_code_ue(enc, enc->enc_pic.pic_width_in_luma_samples);
+   radeon_enc_code_ue(enc, enc->enc_pic.pic_height_in_luma_samples);
+   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+   radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
+   radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
+   radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
+   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+   radeon_enc_code_ue(enc, 1);
+   radeon_enc_code_ue(enc, 0x0);
+   radeon_enc_code_ue(enc, 0x0);
+   radeon_enc_code_ue(enc, 
enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
+   //Only support CTBSize 64
+   radeon_enc_code_ue(enc, 6 - 
(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
+   radeon_enc_code_ue(enc, 
enc->enc_pic.log2_min_transform_block_size_minus2);
+   radeon_enc_code_ue(enc, 
enc->enc_pic.log2_diff_max_min_transform_block_size);
+   radeon_enc_code_ue(enc, 
enc->enc_pic.max_transform_hierarchy_depth_inter);
+   radeon_enc_code_ue(enc, 
enc->enc_pic.max_transform_hierarchy_depth_intra);
+
+   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+   radeon_enc_code_fixed_bits(enc, 
!enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
+   radeon_enc_code_fixed_bits(enc, 
enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
+   radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
+
+   radeon_enc_code_ue(enc, 1);
+   radeon_enc_code_ue(enc, 1);
+   radeon_enc_code_ue(enc, 0);
+   radeon_enc_code_ue(enc, 0);
+   radeon_enc_code_fixed_bits(enc, 0x1, 1);
+
+   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+
+   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_enc_code_fixed_bits(enc, 
enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
+
+   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+
+   radeon_enc_code_fixed_bits(enc, 0x0, 1);
+
+   radeon_enc_code_fixed_bits(enc, 0x1, 1);
+
+   radeon_enc_byte_align(enc);
+   radeon_enc_flush_headers(enc);
+   *size_in_bytes = (enc->bits_output + 7) / 8;
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
 {
RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
@@ -586,6 +666,150 @@ static void radeon_enc_nalu_pps(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
+{
+   RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
+   RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
+

[Mesa-dev] [PATCH 07/12] st/va: add HEVC picture desc

[boyuan.zhang]

From: Boyuan Zhang 

Add HEVC picture desc, and add codec check when creating and destroying
context.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/state_trackers/va/context.c| 26 ++
 src/gallium/state_trackers/va/va_private.h |  1 +
 2 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/src/gallium/state_trackers/va/context.c 
b/src/gallium/state_trackers/va/context.c
index 78e1f19..f03b326 100644
--- a/src/gallium/state_trackers/va/context.c
+++ b/src/gallium/state_trackers/va/context.c
@@ -284,8 +284,18 @@ vlVaCreateContext(VADriverContextP ctx, VAConfigID 
config_id, int picture_width,
context->desc.base.profile = config->profile;
context->desc.base.entry_point = config->entrypoint;
if (config->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
-  context->desc.h264enc.rate_ctrl.rate_ctrl_method = config->rc;
-  context->desc.h264enc.frame_idx = util_hash_table_create(handle_hash, 
handle_compare);
+  switch (u_reduce_video_profile(context->templat.profile)) {
+  case PIPE_VIDEO_FORMAT_MPEG4_AVC:
+ context->desc.h264enc.rate_ctrl.rate_ctrl_method = config->rc;
+ context->desc.h264enc.frame_idx = util_hash_table_create(handle_hash, 
handle_compare);
+ break;
+  case PIPE_VIDEO_FORMAT_HEVC:
+ context->desc.h265enc.rc.rate_ctrl_method = config->rc;
+ context->desc.h265enc.frame_idx = util_hash_table_create(handle_hash, 
handle_compare);
+ break;
+  default:
+ break;
+  }
}
 
mtx_lock(>mutex);
@@ -314,8 +324,16 @@ vlVaDestroyContext(VADriverContextP ctx, VAContextID 
context_id)
 
if (context->decoder) {
   if (context->desc.base.entry_point == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
- if (context->desc.h264enc.frame_idx)
-util_hash_table_destroy (context->desc.h264enc.frame_idx);
+ if (u_reduce_video_profile(context->decoder->profile) ==
+ PIPE_VIDEO_FORMAT_MPEG4_AVC) {
+if (context->desc.h264enc.frame_idx)
+   util_hash_table_destroy (context->desc.h264enc.frame_idx);
+ }
+ if (u_reduce_video_profile(context->decoder->profile) ==
+ PIPE_VIDEO_FORMAT_HEVC) {
+if (context->desc.h265enc.frame_idx)
+   util_hash_table_destroy (context->desc.h265enc.frame_idx);
+ }
   } else {
  if (u_reduce_video_profile(context->decoder->profile) ==
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
diff --git a/src/gallium/state_trackers/va/va_private.h 
b/src/gallium/state_trackers/va/va_private.h
index 520f970..c022feb 100644
--- a/src/gallium/state_trackers/va/va_private.h
+++ b/src/gallium/state_trackers/va/va_private.h
@@ -270,6 +270,7 @@ typedef struct {
   struct pipe_h265_picture_desc h265;
   struct pipe_mjpeg_picture_desc mjpeg;
   struct pipe_h264_enc_picture_desc h264enc;
+  struct pipe_h265_enc_picture_desc h265enc;
} desc;
 
struct {
-- 
2.7.4

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[Mesa-dev] [PATCH 08/12] st/va: add entrypoint check for HEVC

[boyuan.zhang]

From: Boyuan Zhang 

Add entrypoint check for HEVC to differentiate decode and encode jobs.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/state_trackers/va/context.c | 22 --
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/src/gallium/state_trackers/va/context.c 
b/src/gallium/state_trackers/va/context.c
index f03b326..f567f54 100644
--- a/src/gallium/state_trackers/va/context.c
+++ b/src/gallium/state_trackers/va/context.c
@@ -263,16 +263,18 @@ vlVaCreateContext(VADriverContextP ctx, VAConfigID 
config_id, int picture_width,
 
  case PIPE_VIDEO_FORMAT_HEVC:
  context->templat.max_references = num_render_targets;
- context->desc.h265.pps = CALLOC_STRUCT(pipe_h265_pps);
- if (!context->desc.h265.pps) {
-FREE(context);
-return VA_STATUS_ERROR_ALLOCATION_FAILED;
- }
- context->desc.h265.pps->sps = CALLOC_STRUCT(pipe_h265_sps);
- if (!context->desc.h265.pps->sps) {
-FREE(context->desc.h265.pps);
-FREE(context);
-return VA_STATUS_ERROR_ALLOCATION_FAILED;
+ if (config->entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+context->desc.h265.pps = CALLOC_STRUCT(pipe_h265_pps);
+if (!context->desc.h265.pps) {
+   FREE(context);
+   return VA_STATUS_ERROR_ALLOCATION_FAILED;
+}
+context->desc.h265.pps->sps = CALLOC_STRUCT(pipe_h265_sps);
+if (!context->desc.h265.pps->sps) {
+   FREE(context->desc.h265.pps);
+   FREE(context);
+   return VA_STATUS_ERROR_ALLOCATION_FAILED;
+}
  }
  break;
 
-- 
2.7.4

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[Mesa-dev] [PATCH 04/12] radeon/vcn: add ib implementations for HEVC

[boyuan.zhang]

From: Boyuan Zhang 

Implement required ibs for vcn HEVC encode.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 267 
 1 file changed, 222 insertions(+), 45 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 06b8092..a651f7e 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -231,6 +231,27 @@ static void radeon_enc_session_init(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
+{
+   enc->enc_pic.session_init.encode_standard = 
RENCODE_ENCODE_STANDARD_HEVC;
+   enc->enc_pic.session_init.aligned_picture_width = 
align(enc->base.width, 64);
+   enc->enc_pic.session_init.aligned_picture_height = 
align(enc->base.height, 16);
+   enc->enc_pic.session_init.padding_width = 
enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
+   enc->enc_pic.session_init.padding_height = 
enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
+   enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
+   enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
+
+   RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
+   RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
+   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
+   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
+   RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
+   RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
+   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
+   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_layer_control(struct radeon_encoder *enc)
 {
enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
@@ -262,6 +283,19 @@ static void radeon_enc_slice_control(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
+{
+   enc->enc_pic.hevc_slice_ctrl.slice_control_mode = 
RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
+   enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice = 
align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
+   
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment = 
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
+
+   RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SLICE_CONTROL);
+   RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
 {
enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
@@ -283,27 +317,68 @@ static void radeon_enc_spec_misc(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc, struct 
pipe_picture_desc *picture)
+{
+   struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;
+   enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 = 
pic->seq.log2_min_luma_coding_block_size_minus3;
+   enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
+   enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled = 
pic->seq.strong_intra_smoothing_enabled_flag;
+   enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = 
pic->pic.constrained_intra_pred_flag;
+   enc->enc_pic.hevc_spec_misc.cabac_init_flag = 
pic->slice.cabac_init_flag;
+   enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
+   enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
+
+   RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SPEC_MISC);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_rc_session_init(struct radeon_encoder *enc, struct 
pipe_picture_desc *picture)
 {
-   struct pipe_h264_enc_picture_desc *pic = (struct 
pipe_h264_enc_picture_desc *)picture;
-   switch(pic->rate_ctrl.rate_ctrl_method) {
-   

[Mesa-dev] [PATCH 01/12] vl: add parameters for HEVC encode

[boyuan.zhang]

From: Boyuan Zhang 

Add HEVC encode interface

Signed-off-by: Boyuan Zhang 
---
 src/gallium/include/pipe/p_video_state.h | 100 +++
 1 file changed, 100 insertions(+)

diff --git a/src/gallium/include/pipe/p_video_state.h 
b/src/gallium/include/pipe/p_video_state.h
index 5a88e6c..26e0acf 100644
--- a/src/gallium/include/pipe/p_video_state.h
+++ b/src/gallium/include/pipe/p_video_state.h
@@ -120,6 +120,15 @@ enum pipe_h264_enc_picture_type
PIPE_H264_ENC_PICTURE_TYPE_SKIP = 0x04
 };
 
+enum pipe_h265_enc_picture_type
+{
+   PIPE_H265_ENC_PICTURE_TYPE_P = 0x00,
+   PIPE_H265_ENC_PICTURE_TYPE_B = 0x01,
+   PIPE_H265_ENC_PICTURE_TYPE_I = 0x02,
+   PIPE_H265_ENC_PICTURE_TYPE_IDR = 0x03,
+   PIPE_H265_ENC_PICTURE_TYPE_SKIP = 0x04
+};
+
 enum pipe_h264_enc_rate_control_method
 {
PIPE_H264_ENC_RATE_CONTROL_METHOD_DISABLE = 0x00,
@@ -129,6 +138,15 @@ enum pipe_h264_enc_rate_control_method
PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE = 0x04
 };
 
+enum pipe_h265_enc_rate_control_method
+{
+   PIPE_H265_ENC_RATE_CONTROL_METHOD_DISABLE = 0x00,
+   PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP = 0x01,
+   PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP = 0x02,
+   PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT = 0x03,
+   PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE = 0x04
+};
+
 struct pipe_picture_desc
 {
enum pipe_video_profile profile;
@@ -412,6 +430,88 @@ struct pipe_h264_enc_picture_desc
 
 };
 
+struct pipe_h265_enc_seq_param
+{
+   uint8_t  general_profile_idc;
+   uint8_t  general_level_idc;
+   uint8_t  general_tier_flag;
+   uint32_t intra_period;
+   uint16_t pic_width_in_luma_samples;
+   uint16_t pic_height_in_luma_samples;
+   uint32_t chroma_format_idc;
+   uint32_t bit_depth_luma_minus8;
+   uint32_t bit_depth_chroma_minus8;
+   bool strong_intra_smoothing_enabled_flag;
+   bool amp_enabled_flag;
+   bool sample_adaptive_offset_enabled_flag;
+   bool pcm_enabled_flag;
+   bool sps_temporal_mvp_enabled_flag;
+   uint8_t  log2_min_luma_coding_block_size_minus3;
+   uint8_t  log2_diff_max_min_luma_coding_block_size;
+   uint8_t  log2_min_transform_block_size_minus2;
+   uint8_t  log2_diff_max_min_transform_block_size;
+   uint8_t  max_transform_hierarchy_depth_inter;
+   uint8_t  max_transform_hierarchy_depth_intra;
+};
+
+struct pipe_h265_enc_pic_param
+{
+   uint8_t log2_parallel_merge_level_minus2;
+   uint8_t nal_unit_type;
+   bool constrained_intra_pred_flag;
+   bool loop_filter_across_tiles_enabled_flag;
+};
+
+struct pipe_h265_enc_slice_param
+{
+   uint8_t max_num_merge_cand;
+   int8_t slice_cb_qp_offset;
+   int8_t slice_cr_qp_offset;
+   int8_t slice_beta_offset_div2;
+   int8_t slice_tc_offset_div2;
+   bool cabac_init_flag;
+   uint32_t slice_deblocking_filter_disabled_flag;
+   bool slice_loop_filter_across_slices_enabled_flag;
+};
+
+struct pipe_h265_enc_rate_control
+{
+   enum pipe_h265_enc_rate_control_method rate_ctrl_method;
+   unsigned target_bitrate;
+   unsigned peak_bitrate;
+   unsigned frame_rate_num;
+   unsigned frame_rate_den;
+   unsigned quant_i_frames;
+   unsigned vbv_buffer_size;
+   unsigned vbv_buf_lv;
+   unsigned target_bits_picture;
+   unsigned peak_bits_picture_integer;
+   unsigned peak_bits_picture_fraction;
+   unsigned fill_data_enable;
+   unsigned enforce_hrd;
+};
+
+struct pipe_h265_enc_picture_desc
+{
+   struct pipe_picture_desc base;
+
+   struct pipe_h265_enc_seq_param seq;
+   struct pipe_h265_enc_pic_param pic;
+   struct pipe_h265_enc_slice_param slice;
+   struct pipe_h265_enc_rate_control rc;
+
+   enum pipe_h265_enc_picture_type picture_type;
+   unsigned decoded_curr_pic;
+   unsigned reference_frames[16];
+   unsigned frame_num;
+   unsigned pic_order_cnt;
+   unsigned pic_order_cnt_type;
+   unsigned ref_idx_l0;
+   unsigned ref_idx_l1;
+   bool not_referenced;
+   struct util_hash_table *frame_idx;
+};
+
 struct pipe_h265_sps
 {
uint8_t chroma_format_idc;
-- 
2.7.4

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[Mesa-dev] [PATCH 3/4] st/va: directly use idr pic flag

[boyuan.zhang]

From: Boyuan Zhang 

Remove is_idr flag, and use idr_pic_flag provided by vaapi directly

Signed-off-by: Boyuan Zhang 
Reviewed-by: Christian König 
---
 src/gallium/state_trackers/va/picture.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index 55ca16e..8951573 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -432,7 +432,6 @@ handleVAEncPictureParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlV
h264 = buf->data;
context->desc.h264enc.frame_num = h264->frame_num;
context->desc.h264enc.not_referenced = false;
-   context->desc.h264enc.is_idr = (h264->pic_fields.bits.idr_pic_flag == 1);
context->desc.h264enc.pic_order_cnt = h264->CurrPic.TopFieldOrderCnt;
if (context->desc.h264enc.gop_cnt == 0)
   context->desc.h264enc.i_remain = context->gop_coeff;
@@ -451,7 +450,7 @@ handleVAEncPictureParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlV
   UINT_TO_PTR(h264->CurrPic.picture_id),
   UINT_TO_PTR(h264->frame_num));
 
-   if (context->desc.h264enc.is_idr)
+   if (h264->pic_fields.bits.idr_pic_flag == 1)
   context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_IDR;
else
   context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_P;
@@ -493,10 +492,9 @@ handleVAEncSliceParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlVaB
else if (h264->slice_type == 0)
   context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_P;
else if (h264->slice_type == 2) {
-  if (context->desc.h264enc.is_idr){
- context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_IDR;
+  if (context->desc.h264enc.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
  context->desc.h264enc.idr_pic_id++;
-  } else
+  else
  context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_I;
} else
   context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_SKIP;
-- 
2.7.4

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[Mesa-dev] [PATCH 4/4] vl: remove is idr flag

[boyuan.zhang]

From: Boyuan Zhang 

Remove is_idr flag since not being used anymore.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Christian König 
---
 src/gallium/include/pipe/p_video_state.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/gallium/include/pipe/p_video_state.h 
b/src/gallium/include/pipe/p_video_state.h
index 1d57165..5a88e6c 100644
--- a/src/gallium/include/pipe/p_video_state.h
+++ b/src/gallium/include/pipe/p_video_state.h
@@ -407,7 +407,6 @@ struct pipe_h264_enc_picture_desc
unsigned ref_pic_mode;
 
bool not_referenced;
-   bool is_idr;
bool enable_vui;
struct util_hash_table *frame_idx;
 
-- 
2.7.4

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