On Thursday, November 30, 2017 4:53:44 PM PST Rafael Antognolli wrote:
> I believe the workaround describes that the MI_LOAD_REGISTER_IMM should
> come right after the 3DSTATE_SAMPLE_PATTERN.
>
> Signed-off-by: Rafael Antognolli
> Cc: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/gen8_multisample_state.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/gen8_multisample_state.c
> b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
> index 9f849d64bbc..904e0fee2e5 100644
> --- a/src/mesa/drivers/dri/i965/gen8_multisample_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
> @@ -57,15 +57,15 @@ gen10_emit_wa_lri_to_cache_mode_zero(struct brw_context
> *brw)
> const struct gen_device_info *devinfo = >screen->devinfo;
> assert(devinfo->gen == 10);
>
> + /* Write to CACHE_MODE_0 (0x7000) */
> + brw_load_register_imm32(brw, GEN7_CACHE_MODE_0, 0);
> +
> /* Before changing the value of CACHE_MODE_0 register, GFX pipeline must
> * be idle; i.e., full flush is required.
> */
> brw_emit_pipe_control_flush(brw,
> PIPE_CONTROL_CACHE_FLUSH_BITS |
> PIPE_CONTROL_CACHE_INVALIDATE_BITS);
> -
> - /* Write to CACHE_MODE_0 (0x7000) */
> - brw_load_register_imm32(brw, GEN7_CACHE_MODE_0, 0);
> }
>
> /**
>
I would include in the commit message:
This fixes GPU hangs in the i965 initial state batchbuffer when running
some Piglit tests with always_flush_batch=true.
Reviewed-by: Kenneth Graunke
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