Re: [Mesa-dev] [PATCH] i965: Make Broadwell HiZ path arrange for TC flushes.
Chad Versace chad.vers...@linux.intel.com writes: On Mon, Apr 21, 2014 at 02:08:49PM -0700, Kenneth Graunke wrote: HiZ operations make the depth/render caches out of sync with the sampler caches. We need to arrange for a TC flush to happen before the target buffer is used by the sampler. Calling brw_render_cache_set_add_bo makes that happen. On previous generations, brw_blorp_exec took care of flushing the texture cache by calling intel_batchbuffer_emit_mi_flush after doing any rendering. If we were to use the normal drawing path, then brw_postdraw_set_buffers_need_resolve would handle this. On Broadwell, we don't use BLORP, and we don't emit a rectangle primitive via the normal drawing path. The 3DSTATE_WM_HZ_OP and PIPE_CONTROL implicitly make drawing happen. So, none of our existing code makes this flush happen - we need to do it directly. Fixes 11 Piglit copyteximage subtests. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77223 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77226 Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- src/mesa/drivers/dri/i965/gen8_depth_state.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c index 8f5718a..05c3723 100644 --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c @@ -307,6 +307,9 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, OUT_BATCH(0); ADVANCE_BATCH(); + /* Mark this buffer as needing a TC flush, as we've rendered to it. */ + brw_render_cache_set_add_bo(brw, mt-region-bo); + /* We've clobbered all of the depth packets, and the drawing rectangle, * so we need to ensure those packets are re-emitted before the next * primitive. Is this a general requirement for all surfaces? That is, after using a surface as a render target, a texture cache flush is required before sampling from it? Or is this requirement special to HiZ buffers, depth buffers, and/or WM_HZ_OP? The GPU L1/L2 caches are all incoherent with each other. Most of them are read only. If you've dirtied a thing with the render cache (color/Z/stencil render targets, BLT destinations, etc.) and you want to load from it through the sampler, data, or constant caches, you have to flush. pgp6WE_XSVNpW.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] i965: Make Broadwell HiZ path arrange for TC flushes.
HiZ operations make the depth/render caches out of sync with the sampler caches. We need to arrange for a TC flush to happen before the target buffer is used by the sampler. Calling brw_render_cache_set_add_bo makes that happen. On previous generations, brw_blorp_exec took care of flushing the texture cache by calling intel_batchbuffer_emit_mi_flush after doing any rendering. If we were to use the normal drawing path, then brw_postdraw_set_buffers_need_resolve would handle this. On Broadwell, we don't use BLORP, and we don't emit a rectangle primitive via the normal drawing path. The 3DSTATE_WM_HZ_OP and PIPE_CONTROL implicitly make drawing happen. So, none of our existing code makes this flush happen - we need to do it directly. Fixes 11 Piglit copyteximage subtests. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77223 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77226 Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- src/mesa/drivers/dri/i965/gen8_depth_state.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c index 8f5718a..05c3723 100644 --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c @@ -307,6 +307,9 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, OUT_BATCH(0); ADVANCE_BATCH(); + /* Mark this buffer as needing a TC flush, as we've rendered to it. */ + brw_render_cache_set_add_bo(brw, mt-region-bo); + /* We've clobbered all of the depth packets, and the drawing rectangle, * so we need to ensure those packets are re-emitted before the next * primitive. -- 1.9.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Make Broadwell HiZ path arrange for TC flushes.
Kenneth Graunke kenn...@whitecape.org writes: HiZ operations make the depth/render caches out of sync with the sampler caches. We need to arrange for a TC flush to happen before the target buffer is used by the sampler. Calling brw_render_cache_set_add_bo makes that happen. Reviewed-by: Eric Anholt e...@anholt.net pgp7iQyiX9VrC.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
