Re: [Mesa-dev] [PATCH 08/41] intel: Replace intel_renderbuffer::region with a miptree
On Thu, 17 Nov 2011 19:58:35 -0800, Chad Versace chad.vers...@linux.intel.com wrote: Essentially, this patch just globally substitutes `irb-region` with `irb-mt-region` and then does some minor cleanups to avoid segfaults and other problems. This is in preparation for 1. Fixing scatter/gather for mipmapped separate stencil textures. 2. Supporting HiZ for mipmapped depth textures. As a nice benefit, this lays down some preliminary groundwork for easily texturing from any renderbuffer, even those of the window system. A future commit will replace intel_mipmap_tree::hiz_region with a miptree. Signed-off-by: Chad Versace chad.vers...@linux.intel.com In case I get distracted before finishing, patches 1-7 are Reviewed-by: Eric Anholt e...@anholt.net --- @@ -1381,9 +1396,12 @@ intel_process_dri2_buffer_with_separate_stencil(struct intel_context *intel, buffer_name); if (buffer-attachment == __DRI_BUFFER_HIZ) { - intel_region_reference(rb-hiz_region, region); + intel_region_reference(rb-mt-hiz_region, region); } else { - intel_region_reference(rb-region, region); + rb-mt = intel_miptree_create_for_region(intel, + GL_TEXTURE_2D, + rb-Base.Format, + region);; } Leaked old rb-mt here? I don't see this function kicking off with an intel_miptree_release(rb-mt). Next quoted hunk has the same issue. if (buffer-attachment == __DRI_BUFFER_HIZ) { - intel_region_reference(rb-hiz_region, region); + intel_region_reference(rb-mt-hiz_region, region); } else { - intel_region_reference(rb-region, region); + rb-mt = intel_miptree_create_for_region(intel, + GL_TEXTURE_2D, + rb-Base.Format, + region);; extra ';' - intel_region_reference(intel_get_renderbuffer(fb, BUFFER_DEPTH)-region, - region); - intel_region_reference(intel_get_renderbuffer(fb, BUFFER_STENCIL)-region, - region); + struct intel_mipmap_tree *mt = +intel_miptree_create_for_region(intel, +GL_TEXTURE_2D, +depth_stencil_rb-Base.Format, +region); intel_region_release(region); + intel_miptree_reference(intel_get_renderbuffer(fb, BUFFER_DEPTH)-mt, mt); + intel_miptree_reference(intel_get_renderbuffer(fb, BUFFER_STENCIL)-mt, mt); Haven't you leaked a mt reference here? } irb = intel_renderbuffer(rb); - intel_region_reference(irb-region, image-region); + irb-mt = intel_miptree_create_for_region(intel, + GL_TEXTURE_2D, + image-format, + image-region); + if (!irb-mt) + return; Leak of existing irb-mt? pgpCCVaLQKkCc.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 08/41] intel: Replace intel_renderbuffer::region with a miptree
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 11/18/2011 12:04 PM, Eric Anholt wrote: On Thu, 17 Nov 2011 19:58:35 -0800, Chad Versace chad.vers...@linux.intel.com wrote: Essentially, this patch just globally substitutes `irb-region` with `irb-mt-region` and then does some minor cleanups to avoid segfaults and other problems. This is in preparation for 1. Fixing scatter/gather for mipmapped separate stencil textures. 2. Supporting HiZ for mipmapped depth textures. As a nice benefit, this lays down some preliminary groundwork for easily texturing from any renderbuffer, even those of the window system. A future commit will replace intel_mipmap_tree::hiz_region with a miptree. Signed-off-by: Chad Versace chad.vers...@linux.intel.com --- @@ -1381,9 +1396,12 @@ intel_process_dri2_buffer_with_separate_stencil(struct intel_context *intel, buffer_name); if (buffer-attachment == __DRI_BUFFER_HIZ) { - intel_region_reference(rb-hiz_region, region); + intel_region_reference(rb-mt-hiz_region, region); } else { - intel_region_reference(rb-region, region); + rb-mt = intel_miptree_create_for_region(intel, + GL_TEXTURE_2D, + rb-Base.Format, + region);; } Leaked old rb-mt here? I don't see this function kicking off with an intel_miptree_release(rb-mt). Next quoted hunk has the same issue. if (buffer-attachment == __DRI_BUFFER_HIZ) { - intel_region_reference(rb-hiz_region, region); + intel_region_reference(rb-mt-hiz_region, region); } else { - intel_region_reference(rb-region, region); + rb-mt = intel_miptree_create_for_region(intel, + GL_TEXTURE_2D, + rb-Base.Format, + region);; extra ';' - intel_region_reference(intel_get_renderbuffer(fb, BUFFER_DEPTH)-region, -region); - intel_region_reference(intel_get_renderbuffer(fb, BUFFER_STENCIL)-region, -region); + struct intel_mipmap_tree *mt = + intel_miptree_create_for_region(intel, + GL_TEXTURE_2D, + depth_stencil_rb-Base.Format, + region); intel_region_release(region); + intel_miptree_reference(intel_get_renderbuffer(fb, BUFFER_DEPTH)-mt, mt); + intel_miptree_reference(intel_get_renderbuffer(fb, BUFFER_STENCIL)-mt, mt); Haven't you leaked a mt reference here? } irb = intel_renderbuffer(rb); - intel_region_reference(irb-region, image-region); + irb-mt = intel_miptree_create_for_region(intel, + GL_TEXTURE_2D, + image-format, + image-region); + if (!irb-mt) + return; Leak of existing irb-mt? Right. My refcounting here is a mess. Expect v2 of this patch in a moment. - Chad Versace chad.vers...@linux.intel.com -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQIcBAEBAgAGBQJOxsS3AAoJEAIvNt057x8ijPEP/3QrgfEIwGvXlcE1z0m8qumn o3Iq9HhcWilUtCBQ/rm3kpg7htQvc9OjoDLGCpB97YCvtj0NMUh/8SrDipQZbdH4 o3+i1KtgHKNj+ZYbkajOlN1I6JPLds69QmYTW1XwYSyWe92oIp9mzC6RQHo8TDDs 1U+FvKnj3caoUAlLMCyjPoLQIQ/Z+R9bSd3+izuTRp4nd4cH7VU581WIYqitx88P Fp9kZH+cMp0D+upg/SARbjk8XeAPm2v6/HtLomLZ3pnMpBBAJ5BofmULxD7Cgd6w UMWTLg2OfiRbYfY03n/HEm9IAtTtoV80pNbDVeFEvGENk9Pa+Q4YTIm3ioYnxB1/ cks01ne2uCmteBOdUor6d6S+2LmuEOvuAkBSiE71O86c2ymyo96g/AR4tNslWANL Uab1RLPxXisBEqL8vVt0yN/u2+8ATbrICIM1c51bCq2wL35fX7dKBMPscCcARVmJ ZbWqpT1zNVU2AIagcqlYKCytxGqTbfTWTB0eSdFOnaRdMW2VapS2Y2xjXVWcingf ynoWPbwTAD16jB24WBlLDaUHZ+sPdfR95Mx7LPYlo+Andcu7+l7HwNXGKZvx7VcZ KJh600IRIBMG1qJzdfKC28D9zMgESRUxi6LJLCIEHj8y6UyThqUHkdU8Al3A3Qwu q6SgTCDK3wmEj0Fp6wPO =e7Px -END PGP SIGNATURE- ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 08/41] intel: Replace intel_renderbuffer::region with a miptree
Essentially, this patch just globally substitutes `irb-region` with `irb-mt-region` and then does some minor cleanups to avoid segfaults and other problems. This is in preparation for 1. Fixing scatter/gather for mipmapped separate stencil textures. 2. Supporting HiZ for mipmapped depth textures. As a nice benefit, this lays down some preliminary groundwork for easily texturing from any renderbuffer, even those of the window system. A future commit will replace intel_mipmap_tree::hiz_region with a miptree. Signed-off-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/drivers/dri/i965/brw_misc_state.c| 21 ++- src/mesa/drivers/dri/i965/brw_vtbl.c |2 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c |2 +- src/mesa/drivers/dri/i965/gen7_misc_state.c | 11 +- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |2 +- src/mesa/drivers/dri/intel/intel_blit.c | 21 ++- src/mesa/drivers/dri/intel/intel_buffer_objects.c |8 +- src/mesa/drivers/dri/intel/intel_buffers.c|9 +- src/mesa/drivers/dri/intel/intel_context.c| 55 +--- src/mesa/drivers/dri/intel/intel_fbo.c| 150 ++-- src/mesa/drivers/dri/intel/intel_fbo.h|7 +- src/mesa/drivers/dri/intel/intel_pixel_copy.c |5 +- src/mesa/drivers/dri/intel/intel_screen.c |3 +- src/mesa/drivers/dri/intel/intel_span.c |3 +- src/mesa/drivers/dri/intel/intel_tex_copy.c | 14 ++- src/mesa/drivers/dri/intel/intel_tex_image.c |6 +- 16 files changed, 181 insertions(+), 138 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 514c990..4119afa 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -33,6 +33,7 @@ #include intel_batchbuffer.h #include intel_fbo.h +#include intel_mipmap_tree.h #include intel_regions.h #include brw_context.h @@ -204,9 +205,14 @@ static void emit_depthbuffer(struct brw_context *brw) /* _NEW_BUFFERS */ struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH); struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL); - struct intel_region *hiz_region = depth_irb ? depth_irb-hiz_region : NULL; + struct intel_region *hiz_region = NULL; unsigned int len; + if (depth_irb + depth_irb-mt) { + hiz_region = depth_irb-mt-hiz_region; + } + /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both * non-pipelined state that will need the PIPE_CONTROL workaround. */ @@ -272,6 +278,8 @@ static void emit_depthbuffer(struct brw_context *brw) * [DevGT]: This field must be set to the same value (enabled or * disabled) as Hierarchical Depth Buffer Enable */ + struct intel_region *region = stencil_irb-mt-region; + assert(intel-has_separate_stencil); assert(stencil_irb-Base.Format == MESA_FORMAT_S8); @@ -283,8 +291,8 @@ static void emit_depthbuffer(struct brw_context *brw) (BRW_TILEWALK_YMAJOR 26) | (BRW_SURFACE_2D 29)); OUT_BATCH(0); - OUT_BATCH(((stencil_irb-region-width - 1) 6) | -(2 * stencil_irb-region-height - 1) 19); + OUT_BATCH(((region-width - 1) 6) | +(2 * region-height - 1) 19); OUT_BATCH(0); OUT_BATCH(0); @@ -294,7 +302,7 @@ static void emit_depthbuffer(struct brw_context *brw) ADVANCE_BATCH(); } else { - struct intel_region *region = depth_irb-region; + struct intel_region *region = depth_irb-mt-region; unsigned int format; uint32_t tile_x, tile_y, offset; @@ -379,10 +387,11 @@ static void emit_depthbuffer(struct brw_context *brw) /* Emit stencil buffer. */ if (stencil_irb) { +struct intel_region *region = stencil_irb-mt-region; BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_STENCIL_BUFFER 16) | (3 - 2)); -OUT_BATCH(stencil_irb-region-pitch * stencil_irb-region-cpp - 1); -OUT_RELOC(stencil_irb-region-bo, +OUT_BATCH(region-pitch * region-cpp - 1); +OUT_RELOC(region-bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); ADVANCE_BATCH(); diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index 7c23faa..9302b27 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -126,7 +126,7 @@ brw_update_draw_buffer(struct intel_context *intel) /* Check some stencil invariants. These should probably be in * emit_depthbuffer(). */ - if (irbStencil irbStencil-region) { + if (irbStencil irbStencil-mt) { if (!intel-has_separate_stencil) assert(irbStencil-Base.Format == MESA_FORMAT_S8_Z24); if (fb_has_hiz ||