From: Dave Airlie <airl...@redhat.com> This removes the other geometry specific user sgpr.
Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/common/ac_nir_to_llvm.c | 37 +++++++++++++++++++------------------ src/amd/common/ac_nir_to_llvm.h | 1 - src/amd/vulkan/radv_pipeline.c | 9 --------- 3 files changed, 19 insertions(+), 28 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 9e4069b535a..43e13ec91e4 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -88,7 +88,6 @@ struct radv_shader_context { LLVMValueRef tes_u; LLVMValueRef tes_v; - LLVMValueRef gsvs_ring_stride; LLVMValueRef gs2vs_offset; LLVMValueRef gs_wave_id; LLVMValueRef gs_vtx_offset[6]; @@ -122,6 +121,8 @@ struct radv_shader_context { uint32_t tcs_vertices_per_patch; uint32_t tcs_num_inputs; uint32_t tcs_num_patches; + uint32_t max_gsvs_emit_size; + uint32_t gsvs_vertex_size; }; static inline struct radv_shader_context * @@ -636,7 +637,6 @@ static void allocate_user_sgprs(struct radv_shader_context *ctx, user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx); } } - user_sgpr_info->sgpr_count += 1; break; default: break; @@ -966,8 +966,6 @@ static void create_function(struct radv_shader_context *ctx, &args); } - add_arg(&args, ARG_SGPR, ctx->ac.i32, - &ctx->gsvs_ring_stride); if (needs_view_index) add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.view_index); @@ -995,8 +993,6 @@ static void create_function(struct radv_shader_context *ctx, &user_sgpr_info, &args, &desc_sets); - add_arg(&args, ARG_SGPR, ctx->ac.i32, - &ctx->gsvs_ring_stride); if (needs_view_index) add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.view_index); @@ -1122,8 +1118,6 @@ static void create_function(struct radv_shader_context *ctx, previous_stage, &user_sgpr_idx); } - set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, - &user_sgpr_idx, 1); if (ctx->abi.view_index) set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1); break; @@ -6740,6 +6734,8 @@ ac_setup_rings(struct radv_shader_context *ctx) if (ctx->stage == MESA_SHADER_GEOMETRY) { LLVMValueRef tmp; uint32_t num_entries = 64; + LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size, false); + LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size << 16, false); ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false)); ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false)); @@ -6747,10 +6743,10 @@ ac_setup_rings(struct radv_shader_context *ctx) tmp = LLVMConstInt(ctx->ac.i32, num_entries, false); if (ctx->options->chip_class >= VI) - tmp = LLVMBuildMul(ctx->ac.builder, LLVMBuildLShr(ctx->ac.builder, ctx->gsvs_ring_stride, LLVMConstInt(ctx->ac.i32, 16, false), ""), tmp, ""); + tmp = LLVMBuildMul(ctx->ac.builder, gsvs_ring_stride, tmp, ""); ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), ""); tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, ""); - tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, ""); + tmp = LLVMBuildOr(ctx->ac.builder, tmp, gsvs_ring_desc, ""); ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, ""); } @@ -6968,6 +6964,17 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm, if (i) emit_barrier(&ctx.ac, ctx.stage); + nir_foreach_variable(variable, &shaders[i]->outputs) + scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage); + + if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) { + unsigned addclip = shaders[i]->info.clip_distance_array_size + + shaders[i]->info.cull_distance_array_size > 4; + ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16; + ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size * + shaders[i]->info.gs.vertices_out; + } + ac_setup_rings(&ctx); LLVMBasicBlockRef merge_block; @@ -6994,9 +7001,6 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm, else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY) prepare_gs_input_vgprs(&ctx); - nir_foreach_variable(variable, &shaders[i]->outputs) - scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage); - ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]); if (shader_count >= 2) { @@ -7005,11 +7009,8 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm, } if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) { - unsigned addclip = shaders[i]->info.clip_distance_array_size + - shaders[i]->info.cull_distance_array_size > 4; - shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16; - shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size * - shaders[i]->info.gs.vertices_out; + shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size; + shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size; } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) { shader_info->tcs.num_patches = ctx.tcs_num_patches; shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx); diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h index f4825ef4cd5..0ea6832acdc 100644 --- a/src/amd/common/ac_nir_to_llvm.h +++ b/src/amd/common/ac_nir_to_llvm.h @@ -112,7 +112,6 @@ enum ac_ud_index { AC_UD_PS_MAX_UD, AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START, AC_UD_CS_MAX_UD, - AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD, AC_UD_GS_MAX_UD, AC_UD_TCS_MAX_UD, AC_UD_TES_MAX_UD, diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 5d1b5f6e352..6c247589348 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2617,15 +2617,6 @@ radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs, } radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader); - - struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY, - AC_UD_GS_VS_RING_STRIDE_ENTRIES); - if (loc->sgpr_idx != -1) { - uint32_t stride = gs->info.gs.max_gsvs_emit_size; - stride = S_008F04_STRIDE(stride); - radeon_set_sh_reg_seq(cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 1); - radeon_emit(cs, stride); - } } static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade) -- 2.14.3 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev