Re: [Mesa-dev] [PATCH 8/8] clover/llvm: Make __OPENCL_VERSION__ dynamic

[Jan Vesely]

On Wed, 2017-08-09 at 22:36 -0500, Aaron Watry wrote:
> On Fri, Aug 4, 2017 at 1:43 PM, Jan Vesely  wrote:
> > On Sun, 2017-07-30 at 20:26 -0500, Aaron Watry wrote:
> > > Signed-off-by: Aaron Watry 
> > > CC: Jan Vesely 
> > > 
> > > v2: base it on the device version
> > > ---
> > >  src/gallium/state_trackers/clover/llvm/invocation.cpp | 3 ++-
> > >  1 file changed, 2 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp 
> > > b/src/gallium/state_trackers/clover/llvm/invocation.cpp
> > > index 63b2961752..443cd31e66 100644
> > > --- a/src/gallium/state_trackers/clover/llvm/invocation.cpp
> > > +++ b/src/gallium/state_trackers/clover/llvm/invocation.cpp
> > > @@ -224,7 +224,8 @@ namespace {
> > >c.getPreprocessorOpts().Includes.push_back("clc/clc.h");
> > > 
> > >// Add definition for the OpenCL version
> > > -  c.getPreprocessorOpts().addMacroDef("__OPENCL_VERSION__=110");
> > > +  c.getPreprocessorOpts().addMacroDef("__OPENCL_VERSION__=" +
> > > +  
> > > std::to_string(get_language_from_version_str(dev.device_version(;
> > 
> > I don't think you can use the same parsing function here.
> > __OPENCL_VERSION__ can go up to 2.2, while __OPENCL_C_VERSION__ is max
> > 2.0
> 
> Is that an issue here? I thought that the device's highest supported
> OpenCL version was what was required here?

The problem is that 'get_language_from_version_str' throws exception
when the version is >2.0. It's OK for clc version, but device CL
version can go above that.
I don't think it's a big problem, a simple "TODO: consider higher
versions" might be enough for now. it will take a while for clover to
actually run into this.

> 
> __OPENCL_VERSION__ is defined as "substitutes an integer reflecting
> the version number of the OpenCL
> supported by the OpenCL device", which in this case should map
> directly to dev.device_version().
> 
> __OPENCL_C_VERSION__ is already added by clang when the pre-processor
> is initialized using the selected language version
> (clang/FrontEnd/InitPreprocessor.cpp).

The more I think about this (default CLC version, and language version
restrictions), the more it looks like something that should be handled
by clang. The information is conceptually of the same kind as the set
of supported extensions.
My idea is to add default clc setting to clang/lib/Basic/Targets/, and
have a "Warning: CLC version incompatible with selected target" if the
invocation sets something that the target device does not support.
Clover can add "-Werror=clc-incompatible-version" to enforce build
failures.

I'm not sure if clang people will like the idea of having target
dependent default language version.

Jan

> 
> --Aaron
> 
> > 
> > Jan
> > 
> > > 
> > >// clc.h requires that this macro be defined:
> > >
> > > c.getPreprocessorOpts().addMacroDef("cl_clang_storage_class_specifiers");
> 
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Re: [Mesa-dev] [PATCH] isl: Validate row pitch of stencil surfaces.

[Jason Ekstrand]

On August 10, 2017 2:42:29 AM Kenneth Graunke  wrote:


On Wednesday, August 9, 2017 1:20:53 PM PDT Jason Ekstrand wrote:

On Wed, Aug 9, 2017 at 1:09 PM, Kenneth Graunke 
wrote:

> Also, silence an obnoxious finishme that started occurring for all
> GL applications which use stencil after the i965 ISL conversion.
> ---
>  src/intel/isl/isl.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> index 6b4203d79d2..c35116214c8 100644
> --- a/src/intel/isl/isl.c
> +++ b/src/intel/isl/isl.c
> @@ -1367,8 +1367,10 @@ isl_calc_row_pitch(const struct isl_device *dev,
> !pitch_in_range(row_pitch, _3DSTATE_HIER_DEPTH_BUFFER_
> SurfacePitch_bits(dev->info)))
>return false;
>
> -   if (surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT)
> -  isl_finishme("validate row pitch of stencil surfaces");
> +   if (dev->use_separate_stencil &&
> +   (surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) &&
> +   !pitch_in_range(row_pitch, _3DSTATE_STENCIL_BUFFER_
> SurfacePitch_bits(dev->info)))
>

Topi sent the same patch.  This doesn't work on gen4.


Did you see that I have dev->use_separate_stencil in the condition?

That essentially restricts this check to Gen6+, so Gen4-5 won't do
any checking at all.  Which is exactly how much checking it's doing
today. :)

Perhaps you'd instead prefer:

   uint32_t stencil_pitch_bits =
  dev->use_separate_stencil ?
  _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev->info) :
  _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info);

   if ((surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) &&
   !pitch_in_range(row_pitch, stencil_pitch_bits))
  return false;

so that we use the 3DSTATE_DEPTH_BUFFER pitch limits on Gen4 or whenever
we're doing combined depth/stencil, and 3DSTATE_STENCIL_BUFFER's limits
when doing separate stencil.


Works for me



> +  return false;
>
>   done:
> *out_row_pitch = row_pitch;
> --
> 2.14.0
>
>






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Re: [Mesa-dev] [PATCH v5 2/2] i965: Queue the buffer with a sync fence for Android OS

[Marathe, Yogesh]

Tomasz,

> -Original Message-
> From: Tomasz Figa [mailto:tf...@chromium.org]
> Sent: Thursday, August 10, 2017 5:29 PM
> To: Marathe, Yogesh 
> Hi Yogesh,
> 
> On Thu, Aug 10, 2017 at 5:25 PM, Marathe, Yogesh
>  wrote:
> > Hi Tomasz,
> >
> >> -Original Message-
> >> From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On
> >> Behalf Of Tomasz Figa
> >> Sent: Tuesday, August 8, 2017 7:45 AM
> >> To: Marathe, Yogesh 
> >> >> > >> Changing the topic, the patch doesn't seem to change the
> >> >> > >> implementation of swapBuffers to stop doing a flush on the
> >> >> > >> buffer, which defeats the purpose of the fence, as the it is
> >> >> > >> likely already signaled at the time it is passed to
> >> >> > >> queueBuffer. Shouldn't
> >> we fix this?
> >> >> > >>
> >> >> > >
> >> >> > > I have been wondering about it all the while, when I had
> >> >> > > prints in
> >> >> > > Fence::getSignalTime() to check finfo->status from consumer
> >> >> > > side during initial revisions, I always found it to be signaled!
> >> >> > >
> >> >> > > Can we really remove that flush in swapBuffers? In that case I
> >> >> > > believe the consumer _must_ wait on fence before really
> >> >> > > accessing it, so that would trigger a change in buffer consumer /
> application!
> >> >> >
> >> >> > The consumer must _always_ wait on the acquire fence if it's a
> >> >> > valid FD, as this is how the ANativeWindow interface is defined.
> >> >> > You can see Mesa already does it in droid_dequeue_buffer(). If
> >> >> > you find a consumer that is not doing so, it's a bug in the consumer.
> >> >> > There is no compatibility concern here, as it's strictly
> >> >> > regulated by Android
> >> specifications.
> >> >>
> >> >> I checked this, yes, BufferConsumer waits on fence provided its valid.
> >> >
> >> > Hi Tomasz,
> >> >
> >> > Is it ok to move that 'flush' removal change to separate commit? I
> >> > would opt for that. This gflush removal change is going to trigger
> >> > additional tests, while this one fixes the issue for now and has
> >> > list of review comments done. If this is fine, I'll push v6 for this.
> >>
> >> I'm okay with either.
> >>
> >
> > I found GLConsumer aosp has glFlush() is already, it means we had two
> > flush calls in the path, one in swapBuffers and other in libgui on consumer.
> >
> > I went ahead and removed  dri2_flush_drawable_for_swapbuffer.
> > Functionally, things seem to be ok. I assume this will be valid only
> > for android with valid fence changes and not for other platforms. Is this 
> > right
> expectation? Diff below.
> >
> > diff --git a/src/egl/drivers/dri2/platform_android.c
> > b/src/egl/drivers/dri2/platform_android.c
> > index 8bca753..80da021 100644
> > --- a/src/egl/drivers/dri2/platform_android.c
> > +++ b/src/egl/drivers/dri2/platform_android.c
> > @@ -706,7 +706,6 @@ droid_swap_buffers(_EGLDriver *drv, _EGLDisplay
> *disp, _EGLSurface *draw)
> > if (dri2_surf->back)
> >dri2_surf->back->age = 1;
> >
> > -   dri2_flush_drawable_for_swapbuffers(disp, draw);
> >
> > /* dri2_surf->buffer can be null even when no error has occured. For
> >  * example, if the user has called no GL rendering commands since
> > the
> >
> > If this is only change, I don’t think we need separate patch here. Please 
> > correct
> me if I'm wrong.
> 
> I think I have been mistaken in what
> dri2_flush_drawable_for_swabuffers() does. We need to keep it there as it
> makes the DRI2 driver issue operations finalizing the buffer, e.g.
> remaining drawing or a multisample resolve if necessary. However it doesn't do
> any synchronous wait on the queued operations, so there is no performance
> loss.
> 

I am OK either ways. Another thing, glFlush in libgui seems legitimate, it is
required in order to have eglDupNativeFenceFDANDROID() return a valid fd!

Now only pending thing is the 'old display surface' fence then, and we have 
decided
to wait for someone else from android to comment on it.

> Best regards,
> Tomasz
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Re: [Mesa-dev] [PATCH] st/va: change frame_idx from array to hash table

[Julien Isorce]

Boyuan, gentle ping ?

On 26 July 2017 at 19:36, Christian König  wrote:

> So that means Reviewed-and-tested-by: Zhang, Boyuan  >?
>
> Christian.
>
>
> Am 26.07.2017 um 20:29 schrieb Zhang, Boyuan:
>
>> The code looks good to me. I also did a few local vaapi-enc tests and
>> confirmed that patch works fine.
>>
>> Regards,
>> Boyuan
>>
>> -Original Message-
>> From: Liu, Leo
>> Sent: July-26-17 12:01 PM
>> To: Andy Furniss; Koenig, Christian; Julien Isorce;
>> mesa-dev@lists.freedesktop.org; Zhang, Boyuan
>> Subject: Re: [Mesa-dev] [PATCH] st/va: change frame_idx from array to
>> hash table
>>
>>
>>
>> On 07/25/2017 06:04 PM, Andy Furniss wrote:
>>
>>> Christian König wrote:
>>>
>>> Leo and Boyuan can you take a quick look as well? On first glance
 looks totally sane to me.

>>> This reminds me .
>>>
>>> I don't know what's special about my setup, but I haven't been able to
>>> use gst + vce properly since March.
>>>
>>> As I said at the time -
>>>
>>> https://lists.freedesktop.org/archives/mesa-dev/2017-March/148216.html
>>>
>>> I did ping as well, but never quite got round to doing a bug.
>>>
>>> I guess devs who tests vce with gstreamer don't see this?
>>>
>> Personally, haven't been working on encode too much recently. esp for
>> VA-API encode.
>>
>> Cheers,
>> Leo
>>
>>
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>>
>
>
>
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[Mesa-dev] [PATCH 1/2] i965: Clean up intel_batchbuffer_init().

[Kenneth Graunke]

Passing screen lets us get the kernel features, devinfo, and bufmgr,
without needing container_of.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102062
Cc: Mauro Rossi 
Cc: Tapani Pälli 
---
 src/mesa/drivers/dri/i965/brw_context.c   |  2 +-
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 16 
 src/mesa/drivers/dri/i965/intel_batchbuffer.h |  5 ++---
 3 files changed, 11 insertions(+), 12 deletions(-)

According to the bug report, something about container_of is causing
things to go haywire.  I'm not seeing the problem, but eliminating
that is easy enough and arguably a bit nicer anyway...

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 60b14571ed0..2d8f34f7efa 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -934,7 +934,7 @@ brwCreateContext(gl_api api,
 
intel_fbo_init(brw);
 
-   intel_batchbuffer_init(>batch, brw->bufmgr, brw->has_llc);
+   intel_batchbuffer_init(screen, >batch);
 
if (brw->gen >= 6) {
   /* Create a new hardware context.  Using a hardware context means that
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 66b9a28129e..59488a2f969 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -58,13 +58,13 @@ uint_key_hash(const void *key)
 }
 
 void
-intel_batchbuffer_init(struct intel_batchbuffer *batch,
-   struct brw_bufmgr *bufmgr,
-   bool has_llc)
+intel_batchbuffer_init(struct intel_screen *screen,
+   struct intel_batchbuffer *batch)
 {
-   struct brw_context *brw = container_of(batch, brw, batch);
+   struct brw_bufmgr *bufmgr = screen->bufmgr;
+   const struct gen_device_info *devinfo = >devinfo;
 
-   if (!has_llc) {
+   if (!devinfo->has_llc) {
   batch->cpu_map = malloc(BATCH_SZ);
   batch->map = batch->cpu_map;
   batch->map_next = batch->cpu_map;
@@ -87,14 +87,14 @@ intel_batchbuffer_init(struct intel_batchbuffer *batch,
}
 
batch->use_batch_first =
-  brw->screen->kernel_features & KERNEL_ALLOWS_EXEC_BATCH_FIRST;
+  screen->kernel_features & KERNEL_ALLOWS_EXEC_BATCH_FIRST;
 
/* PIPE_CONTROL needs a w/a but only on gen6 */
batch->valid_reloc_flags = EXEC_OBJECT_WRITE;
-   if (brw->gen == 6)
+   if (devinfo->gen == 6)
   batch->valid_reloc_flags |= EXEC_OBJECT_NEEDS_GTT;
 
-   intel_batchbuffer_reset(batch, bufmgr, has_llc);
+   intel_batchbuffer_reset(batch, bufmgr, devinfo->has_llc);
 }
 
 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index 4661a2a9f66..99d2747f282 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -38,9 +38,8 @@ extern "C" {
 
 struct intel_batchbuffer;
 
-void intel_batchbuffer_init(struct intel_batchbuffer *batch,
-struct brw_bufmgr *bufmgr,
-bool has_llc);
+void intel_batchbuffer_init(struct intel_screen *screen,
+struct intel_batchbuffer *batch);
 void intel_batchbuffer_free(struct intel_batchbuffer *batch);
 void intel_batchbuffer_save_state(struct brw_context *brw);
 void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
-- 
2.14.0

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[Mesa-dev] [PATCH 2/2] i965: Guard GetBufferSubData's streaming memcpy load with USE_SSE41

[Kenneth Graunke]

This should hopefully fix build issues on 32-bit Android-x86.

Cc: Mauro Rossi 
Cc: Tapani Pälli 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102050
---
 src/mesa/drivers/dri/i965/intel_buffer_objects.c | 2 ++
 1 file changed, 2 insertions(+)

Mauro, hopefully this helps?

diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c 
b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index ee591168283..9afd98edb87 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -342,6 +342,7 @@ brw_get_buffer_subdata(struct gl_context *ctx,
 
unsigned int map_flags = MAP_READ;
mem_copy_fn memcpy_fn = memcpy;
+#ifdef USE_SSE4_1
if (!intel_obj->buffer->cache_coherent && cpu_has_sse4_1) {
   /* Rather than acquire a new WB mmaping of the buffer object and pull
* it into the CPU cache, keep using the WC mmap that we have for writes,
@@ -350,6 +351,7 @@ brw_get_buffer_subdata(struct gl_context *ctx,
   map_flags |= MAP_COHERENT;
   memcpy_fn = (mem_copy_fn) _mesa_streaming_load_memcpy;
}
+#endif
 
void *map = brw_bo_map(brw, intel_obj->buffer, map_flags);
if (unlikely(!map)) {
-- 
2.14.0

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Re: [Mesa-dev] [PATCH 03/22] glformats: Add a mapping for MESA_FORMAT_S_UINT8

[Erik Faye-Lund]

On Sat, Aug 5, 2017 at 11:39 AM, Chris Wilson  wrote:
> Map the user format of GL_DEPTH_COMPONENT, GL_UNSIGNED_BYTE to the
> internal format of MESA_FORMAT_S_UINT8.
> ---
>  src/mesa/main/glformats.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
> index 06be3ec48d..8ae833ca65 100644
> --- a/src/mesa/main/glformats.c
> +++ b/src/mesa/main/glformats.c
> @@ -3472,6 +3472,10 @@ _mesa_format_from_format_and_type(GLenum format, 
> GLenum type)
>  * matching the OpenGL format and data type
>  */
> switch (type) {
> +   case GL_UNSIGNED_BYTE:
> +  if (format == GL_STENCIL_INDEX)
> + return MESA_FORMAT_S_UINT8;
> +  break;

The commit message says "GL_DEPTH_COMPONENT", but the code says
"GL_STENCIL_INDEX". I'm guessing the latter is the intended.
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Re: [Mesa-dev] [PATCH 3/3] intel/compiler: properly size attribute wa_flags array for Vulkan

[Iago Toral]

On Wed, 2017-08-09 at 16:18 +0100, Lionel Landwerlin wrote:
> Acked-by: Lionel Landwerlin 
> 
> I can see that it fixes the tests and it makes sense, but I'm failing
> to 
> see how gl_attrib_wa_flags ends up being set from anv :/

Sorry, I should've explained that. It is not really anv but the shared
compiler infrastructure that does this. From anv, the call chain is
this:

anv_pipeline_compile_vs -> brw_nir_lower_vs_inputs ->
brw_nir_apply_attribute_workarounds

brw_nir_lower_vs_inputs is the one that reads gl_attrib_wa_flags from
the brw_vs_prog_key state, which is eventually used used by
brw_nir_apply_attribute_workarounds (where the out-of-bounds accessed
happen without this patch).

Iago

> Thanks a lot!
> 
> On 21/07/17 09:26, Iago Toral Quiroga wrote:
> > Mesa will map user defined vertex input attributes to slots
> > starting at VERT_ATTRIB_GENERIC0 which gives us room for only 16
> > slots (up to GL_VERT_ATTRIB_MAX). This sufficient for GL, where
> > we expose exactly 16 vertex attributes for user defined inputs, but
> > in Vulkan we can expose up to 28 (which are also mapped from
> > VERT_ATTRIB_GENERIC0 onwards) so we need to account for this when
> > we scope the size of the array of attribute workaround flags
> > that is used during the brw_vertex_workarounds NIR pass. This
> > prevents out-of-bounds accesses in that array for NIR shaders
> > that use more than 16 vertex input attributes.
> > 
> > Fixes:
> > dEQP-VK.pipeline.vertex_input.max_attributes.*
> > ---
> > 
> > I considered other options for this too:
> > 
> > *  Increase the value of GL_VERT_ATTRIB_MAX, but that would affect
> > other drivers, including GL drivers that do not need to increase
> > this value. If we do this we should at least check that increasing
> > the value doesn't have unexpected consequences for drivers that
> > rely in GL_VERT_ATTRIB_MAX not being larger than what it currently
> > is.
> > 
> > * We could remap vulkan vertex attrib slots to start at 0 at some
> > point in the process... but I think that could be a source of
> > confusion, since from that point forward we shouldn't be using
> > shader enums to identify particular slots and there would also be
> > a mismatch between input bits in vs_prog_data->inputs_read
> > and actual slot positions which looks like an undesirable
> > situation.
> > 
> > * Since the brw_vertex_workarounds pass seems rather GL-specific at
> > the moment, we could let our compiler infrastructure know if we
> > are compiling a shader for Vulkan or GL APIs and use that info
> > to not run the pass for Vulkan shaders, however, there is a chance
> > that we need this pass in Vulkan in the future too (maybe with
> > Vulkan specific lowerings). There is actually a comment in
> > anv_pipipeline.c, function populate_vs_prog_key() suggesting this
> > possibility, so this solution would be invalid if that ever
> > happened.
> > 
> > Since all solutions have some kind of con I decided to go with the
> > less intrusive one for now.
> > 
> >   src/intel/compiler/brw_compiler.h | 18 +-
> >   1 file changed, 17 insertions(+), 1 deletion(-)
> > 
> > diff --git a/src/intel/compiler/brw_compiler.h
> > b/src/intel/compiler/brw_compiler.h
> > index bebd244736..41c0707003 100644
> > --- a/src/intel/compiler/brw_compiler.h
> > +++ b/src/intel/compiler/brw_compiler.h
> > @@ -188,6 +188,15 @@ struct brw_sampler_prog_key_data {
> >   #define BRW_ATTRIB_WA_SIGN  32  /* interpret as signed in
> > shader */
> >   #define BRW_ATTRIB_WA_SCALE 64  /* interpret as scaled in
> > shader */
> >   
> > +/**
> > + * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with
> > the range
> > + * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to
> > 16 user
> > + * input vertex attributes. In Vulkan, we expose up to 28 user
> > vertex input
> > + * attributes that are mapped to slots also starting at
> > VERT_ATTRIB_GENERIC0.
> > + */
> > +#define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
> > +#define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
> > +
> >   /** The program key for Vertex Shaders. */
> >   struct brw_vs_prog_key {
> >  unsigned program_string_id;
> > @@ -196,8 +205,15 @@ struct brw_vs_prog_key {
> >   * Per-attribute workaround flags
> >   *
> >   * For each attribute, a combination of BRW_ATTRIB_WA_*.
> > +*
> > +* For OpenGL, where we expose a maximum of 16 user input
> > atttributes
> > +* we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
> > +* slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
> > +* expose up to 28 user input vertex attributes that are mapped
> > to slots
> > +* starting at VERT_ATTRIB_GENERIC0, so this array need to be
> > large
> > +* enough to hold this many slots.
> >   */
> > -   uint8_t gl_attrib_wa_flags[VERT_ATTRIB_MAX];
> > +   uint8_t gl_attrib_wa_flags[MAX2(MAX_GL_VERT_ATTRIB,
> > MAX_VK_VERT_ATTRIB)];
> >   
> >  

Re: [Mesa-dev] [PATCH 2/2] dri3: Swapbuffer update

[Thomas Hellstrom]

On 08/10/2017 05:27 AM, Michel Dänzer wrote:

On 09/08/17 04:07 PM, Thomas Hellstrom wrote:

On 08/09/2017 08:36 AM, Michel Dänzer wrote:

On 08/08/17 03:48 PM, Thomas Hellstrom wrote:

Implement back-to-fake-front flips, Fix EGL_BUFFER_PRESERVED
path. Implement dri3 support for GLX_SWAP_EXCHANGE_OML and
GLX_SWAP_COPY_OML.

The back-to-fake-front flips will save a full buffer copy in the
case of a fake front being enabled and GLX_SWAP_UNDEFINED_OML.

Support for EGL_BUFFER_PRESERVED and GLX_SWAP_X_OML are mostly
useful for things like glretrace if traces are capured with
applications relying on a specific swapbuffer behavior.

The EGL_BUFFER_PRESERVED path previously made sure the present
was done as a copy, but there was nothing making sure that after
the present, the same back buffer was chosen. This has now been
changed so that if the previous back buffer is idle, we reuse it.
Otherwise we grab a new and copy the contents and buffer age from
the previous back buffer. Server side flips are allowed.

GLX_SWAP_COPY_OML will behave like EGL_BUFFER_PRESERVED.

GLX_SWAP_EXCHANGE_OML will behave similarly, except that we try
to reuse the previous fake front as the new back buffer if it's
idle. If not, we grab a new back buffer and copy the contents and
buffer age from the old fake front.

I'm not sure it's worth copying the contents of the desired next
back buffer to a different one and using that instead. There might
be cases where doing so results in lower performance than simply
using the desired back buffer anyway. Have you made any
measurements WRT this?

Agreed. I haven't done any measurements but my reasoning was that
probably any performance loss would be mostly associated with the
allocating itself, hence a short-lived problem once enough buffers
are allocated. The copying would, at least on modern tiling
hardware, probably not be a big loss since we don't flush.



With EGL_BUFFER_PRESERVED/GLX_SWAP_COPY_OML, always re-using the
same back buffer means that the client only needs to allocate one
back buffer, resulting in lower graphics memory consumption.



True. But there are some implications:

First, with GLX_SWAP_COPY_OML, reusing the back buffer means we need
to disable server-side page-flipping, otherwise the buffer would
never be idle. Second, if we have a fake front, there will be at
least one copy anyway. So in essence we need to disable server-side
page-flipping and might not gain anything in the end if using a fake
front.

With GLX_SWAP_EXCHANGE_OML, we'd be reusing the old fake front which
will, after a delay, always be idle. Also we don't need an extra copy
so the only loss will be a delay which might impact
latency-sensitive applications. I don't expect SWAP_EXCHANGE will be
used much anyway and even if we enable it in st/dri, it won't be
advertised until the server side AIGLX starts to use the image loader
extension or we rewrite the GLX fbconfig selection.

Okay, you've convinced me. Any chance this patch can be split up as well
though?



Yes, I'll try to split it up.

Thanks,
Thomas




What do you think of adding a driConf option to select "wait for
backbuffer idle in swapbuffers"

Seems like overkill. Let's wait for actual problem reports before
considering that.




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[Mesa-dev] [Bug 90264] [Regression, bisected] Tooltip corruption in Chrome

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=90264

John  changed:

   What|Removed |Added

 CC||john.etted...@gmail.com

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Re: [Mesa-dev] [PATCH 0/5] GL_OES_required_internalformat

[Tapani Pälli]

On 06/22/2017 02:08 AM, Eric Anholt wrote:

Tapani Pälli  writes:


On 06/14/2017 01:12 AM, Eric Anholt wrote:

Tapani Pälli  writes:


On 06/12/2017 09:52 AM, Tapani Pälli wrote:


On 05/18/2017 09:39 PM, Eric Anholt wrote:

Eric Anholt  writes:


This series came out of fixing dEQP failures on vc4's GLES2 context.
Mesa was allowing RGB565 textures, which is only valid with
GL_OES_required_internalformat.  Rather than disable RGB565, I decided
the extension was easy enough to support.

I've sent one piglit test for renderbuffer sizing, and dEQP has tests
for whether enums get accepted for TexImage.

There's a functional question in patch #2, see the comment there, and
there's a question of whether the extension should be dummy_true in
patch #5.

branch: https://github.com/anholt/mesa/commits/required-internalformat

I would still love review on this series.


Earlier I took a brief look at series and run through our CI, there were
many failing tests but t seems I forgot to reply/report .. I'll run it
again and let you know what's the result.


'36 failures' (many likely duplicates of some same issue), these ones ..

ES3-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.bdwm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pbo.bdwm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pixelstore.hswm64
ES3-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.sklm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pbo.sklm64
ES3-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.bdwm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pixelstore.bdwm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels.hswm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pixelstore.sklm64
ES3-CTS.functional.fbo.completeness.renderable.texture.color0.rgb10.hswm64
ES3-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.hswm64
ES3-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.hswm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pbo.hswm64
ES3-CTS.functional.fbo.completeness.renderable.texture.color0.rgb10.bdwm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels.bdwm64
ES3-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.sklm64
ES3-CTS.functional.fbo.completeness.renderable.texture.color0.rgb10.sklm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels.sklm64
ES2-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.bdwm64
ES2-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.sklm64
ES2-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.bdwm64
ES2-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.hswm64
ES2-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.hswm64
ES2-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.sklm64

piglit.spec.oes_texture_float.oes_texture_float half.g965m64
piglit.spec.oes_texture_float.oes_texture_float.g965m64
piglit.spec.oes_texture_float.oes_texture_float half linear.g965m64
piglit.spec.oes_texture_float.oes_texture_float linear.g965m64
piglit.spec.oes_texture_float.oes_texture_float half.g45m64
piglit.spec.oes_texture_float.oes_texture_float half linear.g45m64
piglit.spec.oes_texture_float.oes_texture_float linear.g45m64
piglit.spec.oes_texture_float.oes_texture_float.g45m64
piglit.spec.oes_texture_float.oes_texture_float.ilkm64
piglit.spec.oes_texture_float.oes_texture_float half linear.ilkm64
piglit.spec.oes_texture_float.oes_texture_float half.ilkm64
piglit.spec.oes_texture_float.oes_texture_float linear.ilkm64

Are you able to reproduce/run these tests on some machine?

I have a SKL desktop, so I reproduced the GLES2 rgb10 failure and fixed
it, and I think I've fixed the pre-snb failures in piglit.  New branch
up at https://github.com/anholt/mesa/commits/required-internalformat
which I'll piglit now.



OK, seems the packed_pixels ones are still failing. I'll try to debug
this a bit to see what's going on.


Have you had a chance to look at this at all?  Or could you give me a
command line for reproducing failure?  I've gone through my VK-GL-CTS
tree and DEQP trees trying various test runners with various manglings
of the names, with no luck.



Sorry I've forgotten this thread .. the 'CTS' ones are from Khronos 
'OpenGL & OpenGL ES CTS' (available in gitlab) which is run by Jenkins, 
are you able to access that suite?


// Tapani
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Re: [Mesa-dev] [PATCH 1/4] dri: Fix __DRIconfig reporting of __DRI_ATTRIB_SWAP_METHOD

[Michel Dänzer]

On 10/08/17 02:25 PM, Thomas Hellstrom wrote:
> On 08/10/2017 05:20 AM, Michel Dänzer wrote:
>> On 09/08/17 06:53 PM, Thomas Hellstrom wrote:
>>> The attribMap had two entries for this attribute, and
>>> driGetConfigAttribIndex didn't return a proper value for this attribute.
>>> Fix this, and also make sure we return SWAP_UNDEFINED for single-buffer
>>> configs as required by the GLX_OML_swap_method spec.
>>>
>>> Finally bump the dri core extension version to 2, indicating that we
>>> correctly report __DRI_ATTRIB_SWAP_METHOD.
>>>
>>> Signed-off-by: Thomas Hellstrom 
>> [...]
>>
>>> diff --git a/src/mesa/drivers/dri/common/utils.c
>>> b/src/mesa/drivers/dri/common/utils.c
>>> index c37d446..f3ea61e 100644
>>> --- a/src/mesa/drivers/dri/common/utils.c
>>> +++ b/src/mesa/drivers/dri/common/utils.c
>>> @@ -284,8 +284,9 @@ driCreateConfigs(mesa_format format,
>>>   modes->transparentIndex = GLX_DONT_CARE;
>>>   modes->rgbMode = GL_TRUE;
>>>   -if ( db_modes[i] == GLX_NONE ) {
>>> +if ( db_modes[i] == GLX_NONE) {
>>>   modes->doubleBufferMode = GL_FALSE;
>>> +modes->swapMethod = GLX_SWAP_UNDEFINED_OML;
>> The indentation of the added line doesn't match that of the previous
>> line. Patch 4 further changes this code (which is also what Brian's
>> comment was about AFAICT) to be even less consistently indented compared
>> to the surrounding code.
> 
> Hmm, Actually this looks awkward in the patches only due to me using
> spaces rather than tabs to indent in the new code (old code uses tabs). 
> Not sure what the preferred strategy is here, use mesa coding style
> (spaces) or old dri coding style (tabs).

I think first priority should be consistency with surrounding code
whenever possible, which it is in this case. If the formatting is to be
changed, it should be done in one go for the whole file or at least big
portions at a time, without making any functional changes at the same time.


> If the latter, we should probably at some point add subsystem editor
> setup files that override the mesa default ones.

I agree.


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Re: [Mesa-dev] [PATCH v5 2/2] i965: Queue the buffer with a sync fence for Android OS

[Marathe, Yogesh]

Hi Tomasz, 

> -Original Message-
> From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On Behalf
> Of Tomasz Figa
> Sent: Tuesday, August 8, 2017 7:45 AM
> To: Marathe, Yogesh 
> >> > >> Changing the topic, the patch doesn't seem to change the
> >> > >> implementation of swapBuffers to stop doing a flush on the
> >> > >> buffer, which defeats the purpose of the fence, as the it is
> >> > >> likely already signaled at the time it is passed to queueBuffer. 
> >> > >> Shouldn't
> we fix this?
> >> > >>
> >> > >
> >> > > I have been wondering about it all the while, when I had prints
> >> > > in
> >> > > Fence::getSignalTime() to check finfo->status from consumer side
> >> > > during initial revisions, I always found it to be signaled!
> >> > >
> >> > > Can we really remove that flush in swapBuffers? In that case I
> >> > > believe the consumer _must_ wait on fence before really accessing
> >> > > it, so that would trigger a change in buffer consumer / application!
> >> >
> >> > The consumer must _always_ wait on the acquire fence if it's a
> >> > valid FD, as this is how the ANativeWindow interface is defined.
> >> > You can see Mesa already does it in droid_dequeue_buffer(). If you
> >> > find a consumer that is not doing so, it's a bug in the consumer.
> >> > There is no compatibility concern here, as it's strictly regulated by 
> >> > Android
> specifications.
> >>
> >> I checked this, yes, BufferConsumer waits on fence provided its valid.
> >
> > Hi Tomasz,
> >
> > Is it ok to move that 'flush' removal change to separate commit? I
> > would opt for that. This gflush removal change is going to trigger
> > additional tests, while this one fixes the issue for now and has list
> > of review comments done. If this is fine, I'll push v6 for this.
> 
> I'm okay with either.
> 

I found GLConsumer aosp has glFlush() is already, it means we had two flush 
calls in
the path, one in swapBuffers and other in libgui on consumer.

I went ahead and removed  dri2_flush_drawable_for_swapbuffer. Functionally,
things seem to be ok. I assume this will be valid only for android with valid 
fence changes
and not for other platforms. Is this right expectation? Diff below.

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 8bca753..80da021 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -706,7 +706,6 @@ droid_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, 
_EGLSurface *draw)
if (dri2_surf->back)
   dri2_surf->back->age = 1;

-   dri2_flush_drawable_for_swapbuffers(disp, draw);

/* dri2_surf->buffer can be null even when no error has occured. For
 * example, if the user has called no GL rendering commands since the

If this is only change, I don’t think we need separate patch here. Please 
correct me if I'm wrong.

> Best regards,
> Tomasz
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Re: [Mesa-dev] [PATCH] isl: Validate row pitch of stencil surfaces.

[Kenneth Graunke]

On Wednesday, August 9, 2017 1:20:53 PM PDT Jason Ekstrand wrote:
> On Wed, Aug 9, 2017 at 1:09 PM, Kenneth Graunke 
> wrote:
> 
> > Also, silence an obnoxious finishme that started occurring for all
> > GL applications which use stencil after the i965 ISL conversion.
> > ---
> >  src/intel/isl/isl.c | 6 --
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> > index 6b4203d79d2..c35116214c8 100644
> > --- a/src/intel/isl/isl.c
> > +++ b/src/intel/isl/isl.c
> > @@ -1367,8 +1367,10 @@ isl_calc_row_pitch(const struct isl_device *dev,
> > !pitch_in_range(row_pitch, _3DSTATE_HIER_DEPTH_BUFFER_
> > SurfacePitch_bits(dev->info)))
> >return false;
> >
> > -   if (surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT)
> > -  isl_finishme("validate row pitch of stencil surfaces");
> > +   if (dev->use_separate_stencil &&
> > +   (surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) &&
> > +   !pitch_in_range(row_pitch, _3DSTATE_STENCIL_BUFFER_
> > SurfacePitch_bits(dev->info)))
> >
> 
> Topi sent the same patch.  This doesn't work on gen4.

Did you see that I have dev->use_separate_stencil in the condition?

That essentially restricts this check to Gen6+, so Gen4-5 won't do
any checking at all.  Which is exactly how much checking it's doing
today. :)

Perhaps you'd instead prefer:

   uint32_t stencil_pitch_bits =
  dev->use_separate_stencil ?
  _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev->info) :
  _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info);

   if ((surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) &&
   !pitch_in_range(row_pitch, stencil_pitch_bits))
  return false;

so that we use the 3DSTATE_DEPTH_BUFFER pitch limits on Gen4 or whenever
we're doing combined depth/stencil, and 3DSTATE_STENCIL_BUFFER's limits
when doing separate stencil.

> 
> > +  return false;
> >
> >   done:
> > *out_row_pitch = row_pitch;
> > --
> > 2.14.0
> >
> >
> 



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[Mesa-dev] [Bug 101334] AMD SI cards: Some vulkan apps freeze the system

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101334

John  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #49 from John  ---
I've rerun the madmax benchmark in case it was luck, but it was fine.

I've also played with Dolphin for hours and it was fine (well, I think it was
already fine before that patch).

I've tried a bit with RPCS3 as well, though that emulator has its own issue,
and got no freeze either.

So far I have not found anything that would cause problem, with Marko
confirming, and with the patch making it to git, I think that's good enough for
resolving this bug.

Thanks Grazvydas and Dave for the fixes!

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[Mesa-dev] [Bug 101071] compiling glsl fails with undefined reference to `pthread_create'

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101071

--- Comment #16 from John  ---
Hello,

I've been having the same issue for a while, even with Emil's patch on master:

libtool: link: ( cd "glsl/.libs" && rm -f "libstandalone.la" && ln -s
"../libstandalone.la" "libstandalone.la" )
/bin/sh ../../libtool  --tag=CXX   --mode=link g++ -fvisibility=hidden
-Werror=pointer-arith -Werror=vla -march=native -O2 -pipe
-fstack-protector-strong -fno-plt -fstack-check -flto=8 -g
-fvar-tracking-assignments -g -fvar-tracking-assignments -Wall -fno-math-errno
-fno-trapping-math   -Wl,-O1,--sort-common,--as-needed,-z,relro,-z,now
-Wl,-flto -o glsl_compiler glsl/main.o glsl/libstandalone.la  
libtool: link: g++ -fvisibility=hidden -Werror=pointer-arith -Werror=vla
-march=native -O2 -pipe -fstack-protector-strong -fno-plt -fstack-check -flto=8
-g -fvar-tracking-assignments -g -fvar-tracking-assignments -Wall
-fno-math-errno -fno-trapping-math -Wl,-O1 -Wl,--sort-common -Wl,--as-needed
-Wl,-z -Wl,relro -Wl,-z -Wl,now -Wl,-flto -o glsl_compiler glsl/main.o 
glsl/.libs/libstandalone.a -lz -lpthread -pthread
/usr/lib/gcc/x86_64-pc-linux-gnu/7.1.1/../../../../lib/libstdc++.so: undefined
reference to `pthread_create'
/usr/lib/gcc/x86_64-pc-linux-gnu/7.1.1/../../../../lib/libstdc++.so: undefined
reference to `pthread_once'
/usr/lib/gcc/x86_64-pc-linux-gnu/7.1.1/../../../../lib/libstdc++.so: undefined
reference to `pthread_join'
collect2: error: ld returned 1 exit status


If I remove "--as-needed" from my LDFLAGS it compiles with no problem.

I'm on GCC 7.1.1, glibc 2.25, not cross-compiling, but compiling for my system.

What am I doing wrong?

Thanks!

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Re: [Mesa-dev] [PATCH 1/4] dri: Fix __DRIconfig reporting of __DRI_ATTRIB_SWAP_METHOD

[Emil Velikov]

Hi Thomas,

Apologies for dropping in so late.

On 9 August 2017 at 10:53, Thomas Hellstrom  wrote:
> The attribMap had two entries for this attribute, and
> driGetConfigAttribIndex didn't return a proper value for this attribute.
> Fix this, and also make sure we return SWAP_UNDEFINED for single-buffer
> configs as required by the GLX_OML_swap_method spec.
>
> Finally bump the dri core extension version to 2, indicating that we
> correctly report __DRI_ATTRIB_SWAP_METHOD.
>
> Signed-off-by: Thomas Hellstrom 
> ---
>  include/GL/internal/dri_interface.h| 5 -
>  src/mesa/drivers/dri/common/dri_util.c | 2 +-
>  src/mesa/drivers/dri/common/utils.c| 8 ++--
>  3 files changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/include/GL/internal/dri_interface.h 
> b/include/GL/internal/dri_interface.h
> index f676ac5..5e8fce7 100644
> --- a/include/GL/internal/dri_interface.h
> +++ b/include/GL/internal/dri_interface.h
> @@ -726,9 +726,12 @@ struct __DRIuseInvalidateExtensionRec {
>
>  /**
>   * This extension defines the core DRI functionality.
> + *
> + * Version >= 2 indicates that getConfigAttrib with __DRI_ATTRIB_SWAP_METHOD
> + * returns a reliable value.
>   */
>  #define __DRI_CORE "DRI_Core"
> -#define __DRI_CORE_VERSION 1
> +#define __DRI_CORE_VERSION 2
>
The interface is bumped, yet nobody checks it.

If I understand your series correctly, when old drivers are present we
fallback to UNDEFINED and things should just work.
Hence the version bump isn't really needed.

Am I missing something?

Thanks
Emil
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Re: [Mesa-dev] [PATCH] configure: Trust LLVM >= 4.0 llvm-config --libs for shared libraries

[Emil Velikov]

On 9 August 2017 at 02:00, Michel Dänzer  wrote:
> On 09/08/17 03:24 AM, Emil Velikov wrote:
>> On 8 August 2017 at 08:23, Michel Dänzer  wrote:
>>> From: Michel Dänzer 
>>>
>>> No need to manually look for the library files anymore with current
>>> LLVM. This sidesteps the manual method failing when LLVM was built with
>>> -DLLVM_APPEND_VC_REV=ON.
>>>
>> IIRC you recently spotted that the Suse packaging was building LLVM
>> with separate shared libraries.
>
> Apparently that's getting fixed though.
>
>
>> This is something which gets flagged with this (admittedly) quirky test.
>
> What do you mean by that?
>
> I just double-checked that Mesa with this patch still builds fine
> against LLVM built with BUILD_SHARED_LIBS=ON, just like without it.
>
Right, I miss-remembered what the else block does.
Thanks for the correction.

Topic for another thread:
There's been a handful of issues reported with BUILD_SHARED_LIBS=ON.
Should we consider that unsupported setup and error out?

>
>> I think we'd want to keep the best of both - just not sure how to
>> exactly do that.
>> --libs/--libfiles was completely busted with LLVM 3.9 and is back to
>> normal with 4.0.
>>
>> Could we use that somehow?
>
> This patch relies on llvm-config --libs with LLVM >= 4.0. If you mean
> something else, please be more specific.
>
That's the thing - in some versions --libs is busted while for others
--libs/--libfiles.
There isn't a thing we could reliably check across the board, so I was
hoping you know of something.

That said, patch does exactly what it says on the
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH 2/3] specs: Add EGL_MESA_device_software

[Emil Velikov]

On 8 August 2017 at 19:42, Adam Jackson  wrote:
> On Tue, 2017-08-08 at 19:11 +0100, Emil Velikov wrote:
>> On 2 August 2017 at 21:24, Adam Jackson  wrote:
>> > The device extension string is expected to contain the name of the
>> > extension defining what kind of device it is, so the caller can know
>> > what kinds of operations it can perform with it. So that string had
>> > better be non-empty, hence this trivial extension.
>> >
>>
>> Is there something that forbids a EGL device to advertise an empty string?
>> I don't recall such text.
>
> Not strictly "forbids" I suppose, but it does seem to be implied.
> EGL_EXT_device_query says:
>
>> The EGL_EXTENSIONS string describes which device extensions are
>> supported by .  The string is of the same format specified
>> for display and client extension strings in section 3.4. Note that
>> device extensions are properties of the device, and are distinct
>> from other extension strings.
>
> It's not clear to me what a device that exposes zero device extensions
> would mean. If you had two such devices, how would you distinguish
> between them?
I take this as "will be defined in future extensions", but does not
forbid them by any means.
It will be quite bizarre of cours.

I'm asking all of this, since in my last respin of the EGL device
patches (some months ago in a local repo) I always advertised
EGL_EXT_device_enumeration.
it made things more robust and easier. I'll see if I can rebase that
and send it over, but I'm juggling a few other things atm.

> Probably the device_query spec should make this more
> explicit.
>
> NVIDIA's EGL returns EGL_EXT_device_drm and EGL_NV_device_cuda in this
> string; I haven't tested on any other implementations (in fact am not
> aware of other implementations of EXT_device_query). I imagine llvmpipe
> would say both MESA_device_software and EXT_device_drm if it was
> rendering to vgem.
>
I've been pondering on EXT_device_drm_render which will allow devices
to advertise the render node string.
Since in the DRI3 case one does not need the primary card node and the
associated platform specific auth magic.

Do you think it makes sense?

I have some WIP patches for that as well.

>> Drop "fallback"? Despite how crazy it sounds it's not impossible to
>> have a system with only software device(s).
>
> Good point, fixed. I think I also want to keep this one as a MESA
> extension, there could be other software devices with meaningfully
> different capabilities.
>
Agreed.

Thanks
Emil
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Re: [Mesa-dev] [PATCH 1/4] dri: Fix __DRIconfig reporting of __DRI_ATTRIB_SWAP_METHOD

[Thomas Hellstrom]

Hi, Emil,

On 08/10/2017 06:20 PM, Emil Velikov wrote:

Hi Thomas,

Apologies for dropping in so late.

On 9 August 2017 at 10:53, Thomas Hellstrom  wrote:

The attribMap had two entries for this attribute, and
driGetConfigAttribIndex didn't return a proper value for this attribute.
Fix this, and also make sure we return SWAP_UNDEFINED for single-buffer
configs as required by the GLX_OML_swap_method spec.

Finally bump the dri core extension version to 2, indicating that we
correctly report __DRI_ATTRIB_SWAP_METHOD.

Signed-off-by: Thomas Hellstrom 
---
  include/GL/internal/dri_interface.h| 5 -
  src/mesa/drivers/dri/common/dri_util.c | 2 +-
  src/mesa/drivers/dri/common/utils.c| 8 ++--
  3 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/include/GL/internal/dri_interface.h 
b/include/GL/internal/dri_interface.h
index f676ac5..5e8fce7 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -726,9 +726,12 @@ struct __DRIuseInvalidateExtensionRec {

  /**
   * This extension defines the core DRI functionality.
+ *
+ * Version >= 2 indicates that getConfigAttrib with __DRI_ATTRIB_SWAP_METHOD
+ * returns a reliable value.
   */
  #define __DRI_CORE "DRI_Core"
-#define __DRI_CORE_VERSION 1
+#define __DRI_CORE_VERSION 2


The interface is bumped, yet nobody checks it.

If I understand your series correctly, when old drivers are present we
fallback to UNDEFINED and things should just work.
Hence the version bump isn't really needed.

Am I missing something?

Thanks
Emil


It's checked in a later patch

https://lists.freedesktop.org/archives/mesa-dev/2017-August/165848.html

But I'm currently splitting it up into a series with some extra fixes in it.

/Thomas


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Re: [Mesa-dev] [PATCH 1/4] dri: Fix __DRIconfig reporting of __DRI_ATTRIB_SWAP_METHOD

[Emil Velikov]

On 10 August 2017 at 17:40, Thomas Hellstrom  wrote:
> It's checked in a later patch
>
> https://lists.freedesktop.org/archives/mesa-dev/2017-August/165848.html
>
> But I'm currently splitting it up into a series with some extra fixes in it.
>
Great, thanks.

-Emil
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Re: [Mesa-dev] [PATCH] egl/dri2: Implement swapInterval fallback in a conformant way

[Emil Velikov]

On 10 August 2017 at 13:51, Tomasz Figa  wrote:
> On Thu, Aug 10, 2017 at 9:40 PM, Eric Engestrom  wrote:
>> On 10 August 2017 06:43:45 BST, Tomasz Figa  wrote:
>>> dri2_fallback_swap_interval() currently used to stub out swap interval
>>> support in Android backend does nothing besides returning EGL_FALSE.
>>> This causes at least one known application (Android Snapchat) to fail
>>> due to an unexpected error and my loose interpretation of the EGL 1.5
>>> specification justifies it. Relevant quote below:
>>>
>>> The function
>>>
>>> EGLBoolean eglSwapInterval(EGLDisplay dpy, EGLint interval);
>>>
>>>specifies the minimum number of video frame periods per buffer swap
>>> for the draw surface of the current context, for the current rendering
>>> API. [...]
>>>
>>>The parameter interval specifies the minimum number of video frames
>>> that are displayed before a buffer swap will occur. The interval
>>> specified by the function applies to the draw surface bound to the
>>> context that is current on the calling thread. [...] interval is
>>> silently clamped to minimum and maximum implementation dependent
>>> values before being stored; these values are defined by EGLConfig
>>> attributes EGL_MIN_SWAP_INTERVAL and EGL_MAX_SWAP_INTERVAL
>>> respectively.
>>>
>>> The default swap interval is 1.
>>>
>>> Even though it does not specify the exact behavior if the platform
>>> does
>>> not support changing the swap interval, the default assumed state is
>>> the
>>> swap interval of 1, which I interpret as a value that
>>> eglSwapInterval()
>>> should succeed if called with, even if there is no ability to change
>>> the
>>> interval (but there is no change requested). Moreover, since the
>>> behavior is defined to clamp the requested value to minimum and
>>> maximum
>>> and at least the default value of 1 must be present in the range, the
>>> implementation might be expected to have a valid range, which in case
>>> of
>>> the feature being unsupported, would correspond to {1} and any request
>>> might be expected to be clamped to this value.
>>>
>>> This is further confirmed by the code in _eglSwapInterval() in
>>> src/egl/main/eglsurface.c, which is the default fallback
>>> implementation
>>> for EGL drivers not implementing its own. The problem with it is that
>>> the DRI2 EGL driver provides its own implementation that calls into
>>> platform backends, so we cannot just simply fall back to it.
>>>
>>> Signed-off-by: Tomasz Figa 
>>> ---
>>>  src/egl/drivers/dri2/egl_dri2.c   | 12 
>>>  src/egl/drivers/dri2/egl_dri2_fallbacks.h |  9 -
>>>  src/egl/drivers/dri2/platform_x11.c   |  1 +
>>>  3 files changed, 21 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/src/egl/drivers/dri2/egl_dri2.c
>>> b/src/egl/drivers/dri2/egl_dri2.c
>>> index f0d1ded408..686dd68d29 100644
>>> --- a/src/egl/drivers/dri2/egl_dri2.c
>>> +++ b/src/egl/drivers/dri2/egl_dri2.c
>>> @@ -630,6 +630,18 @@ dri2_setup_screen(_EGLDisplay *disp)
>>> struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
>>> unsigned int api_mask;
>>>
>>> +   /*
>>> +* EGL 1.5 specification defines the default value to 1. Moreover,
>>> +* eglSwapInterval() is required to clamp requested value to the
>>> supported
>>> +* range. Since the default value is implicitly assumed to be
>>> supported,
>>> +* use it as both minimum and maximum for the platforms that do
>>> not allow
>>> +* changing the interval. Platforms, which allow it (e.g. x11,
>>> wayland)
>>> +* override these values already.
>>> +*/
>>> +   dri2_dpy->min_swap_interval = 1;
>>> +   dri2_dpy->max_swap_interval = 1;
>>> +   dri2_dpy->default_swap_interval = 1;
>>> +
>>> if (dri2_dpy->image_driver) {
>>>   api_mask = dri2_dpy->image_driver->getAPIMask(dri2_dpy->dri_screen);
>>> } else if (dri2_dpy->dri2) {
>>> diff --git a/src/egl/drivers/dri2/egl_dri2_fallbacks.h
>>> b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
>>> index 604db881a8..c70c686f8d 100644
>>> --- a/src/egl/drivers/dri2/egl_dri2_fallbacks.h
>>> +++ b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
>>> @@ -59,7 +59,14 @@ static inline EGLBoolean
>>>  dri2_fallback_swap_interval(_EGLDriver *drv, _EGLDisplay *dpy,
>>>  _EGLSurface *surf, EGLint interval)
>>>  {
>>> -   return EGL_FALSE;
>>> +   if (interval > surf->Config->MaxSwapInterval)
>>> +  interval = surf->Config->MaxSwapInterval;
>>> +   else if (interval < surf->Config->MinSwapInterval)
>>> +  interval = surf->Config->MinSwapInterval;
>>> +
>>> +   surf->SwapInterval = interval;
>>> +
>>> +   return EGL_TRUE;
>>
>> Agreed with the interpretation, but if memory serves (on my phone on a plane 
>> right now) I already took care of clamping and setting the value one layer 
>> above, so the only change needed is s/EGL_FALSE/EGL_TRUE/ in this function.
>>

[Mesa-dev] [PATCH] dri: fix typo in comment

[Gwan-gyeong Mun]

Signed-off-by: Mun Gwan-gyeong 
---
 include/GL/internal/dri_interface.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/GL/internal/dri_interface.h 
b/include/GL/internal/dri_interface.h
index 2cbd738439..b90c9b2c66 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -1190,7 +1190,7 @@ struct __DRIdri2ExtensionRec {
  * by the driver (YUV planar formats) but serve as a base image for
  * creating sub-images for the different planes within the image.
  *
- * R8, GR88 and NONE should not be used with createImageFormName or
+ * R8, GR88 and NONE should not be used with createImageFromName or
  * createImage, and are returned by query from sub images created with
  * createImageFromNames (NONE, see above) and fromPlane (R8 & GR88).
  */
-- 
2.13.3

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Re: [Mesa-dev] [PATCH] configure: Trust LLVM >= 4.0 llvm-config --libs for shared libraries

[Jan Vesely]

On Thu, 2017-08-10 at 17:45 +0100, Emil Velikov wrote:
> On 9 August 2017 at 02:00, Michel Dänzer  wrote:
> > On 09/08/17 03:24 AM, Emil Velikov wrote:
> > > On 8 August 2017 at 08:23, Michel Dänzer  wrote:
> > > > From: Michel Dänzer 
> > > > 
> > > > No need to manually look for the library files anymore with current
> > > > LLVM. This sidesteps the manual method failing when LLVM was built with
> > > > -DLLVM_APPEND_VC_REV=ON.
> > > > 
> > > 
> > > IIRC you recently spotted that the Suse packaging was building LLVM
> > > with separate shared libraries.
> > 
> > Apparently that's getting fixed though.
> > 
> > 
> > > This is something which gets flagged with this (admittedly) quirky test.
> > 
> > What do you mean by that?
> > 
> > I just double-checked that Mesa with this patch still builds fine
> > against LLVM built with BUILD_SHARED_LIBS=ON, just like without it.
> > 
> 
> Right, I miss-remembered what the else block does.
> Thanks for the correction.
> 
> Topic for another thread:
> There's been a handful of issues reported with BUILD_SHARED_LIBS=ON.
> Should we consider that unsupported setup and error out?

please no.
BUILD_SHARED_LIBS=ON is a must for development setup
debug build of clang + llvm takes 1.4GB, each. Having a ~2.8GB library,
is a really bad idea for testing, not to mention linking time that goes
well into minutes for even a minor change in LLVM.

Jan

> 
> > 
> > > I think we'd want to keep the best of both - just not sure how to
> > > exactly do that.
> > > --libs/--libfiles was completely busted with LLVM 3.9 and is back to
> > > normal with 4.0.
> > > 
> > > Could we use that somehow?
> > 
> > This patch relies on llvm-config --libs with LLVM >= 4.0. If you mean
> > something else, please be more specific.
> > 
> 
> That's the thing - in some versions --libs is busted while for others
> --libs/--libfiles.
> There isn't a thing we could reliably check across the board, so I was
> hoping you know of something.
> 
> That said, patch does exactly what it says on the
> Reviewed-by: Emil Velikov 
> 
> -Emil
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[Mesa-dev] [PATCH 1/3] radeonsi/gfx9: fix the scissor bug workaround

[Marek Olšák]

From: Marek Olšák 

otherwise there is corruption in most apps.

Fixes: 0fe0320 radeonsi: use optimal packet order when doing a pipeline sync
---
 src/gallium/drivers/radeonsi/si_state_draw.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 23e9778..deb0691 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1361,25 +1361,29 @@ void si_draw_vbo(struct pipe_context *ctx, const struct 
pipe_draw_info *info)
 
si_need_cs_space(sctx);
 
/* Since we've called r600_context_add_resource_size for vertex buffers,
 * this must be called after si_need_cs_space, because we must let
 * need_cs_space flush before we add buffers to the buffer list.
 */
if (!si_upload_vertex_buffer_descriptors(sctx))
return;
 
-   /* GFX9 scissor bug workaround. There is also a more efficient but
-* more involved alternative workaround. */
+   /* GFX9 scissor bug workaround. This must be done before VPORT scissor
+* registers are changed. There is also a more efficient but more
+* involved alternative workaround.
+*/
if (sctx->b.chip_class == GFX9 &&
-   si_is_atom_dirty(sctx, >b.scissors.atom))
+   si_is_atom_dirty(sctx, >b.scissors.atom)) {
sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
+   si_emit_cache_flush(sctx);
+   }
 
/* Use optimal packet order based on whether we need to sync the 
pipeline. */
if (unlikely(sctx->b.flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
  SI_CONTEXT_FLUSH_AND_INV_DB |
  SI_CONTEXT_PS_PARTIAL_FLUSH |
  SI_CONTEXT_CS_PARTIAL_FLUSH))) {
/* If we have to wait for idle, set all states first, so that 
all
 * SET packets are processed in parallel with previous draw 
calls.
 * Then upload descriptors, set shader pointers, and draw, and
 * prefetch at the end. This ensures that the time the CUs
-- 
2.7.4

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[Mesa-dev] [PATCH 2/3] gallium/radeon: only pass shader-specific debug flags to the disk shader cache

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_pipe_common.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 2acef6a..95458d2e 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -870,24 +870,31 @@ static void r600_disk_cache_create(struct 
r600_common_screen *rscreen)
else {
uint32_t llvm_timestamp;
if 
(disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
  _timestamp)) 
{
res = asprintf(_str, "%u_%u",
   mesa_timestamp, llvm_timestamp);
}
}
 #endif
if (res != -1) {
+   /* These flags affect shader compilation. */
+   uint64_t shader_debug_flags =
+   rscreen->debug_flags &
+   (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
+DBG_SI_SCHED |
+DBG_UNSAFE_MATH);
+
rscreen->disk_shader_cache =
disk_cache_create(r600_get_family_name(rscreen),
  timestamp_str,
- rscreen->debug_flags);
+ shader_debug_flags);
free(timestamp_str);
}
}
 }
 
 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen 
*pscreen)
 {
struct r600_common_screen *rscreen = (struct 
r600_common_screen*)pscreen;
return rscreen->disk_shader_cache;
 }
-- 
2.7.4

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[Mesa-dev] [PATCH 3/3] gallium/radeon: pass LLVM processor to the disk shader cache

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_pipe_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 95458d2e..0038c9a 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -878,21 +878,21 @@ static void r600_disk_cache_create(struct 
r600_common_screen *rscreen)
 #endif
if (res != -1) {
/* These flags affect shader compilation. */
uint64_t shader_debug_flags =
rscreen->debug_flags &
(DBG_FS_CORRECT_DERIVS_AFTER_KILL |
 DBG_SI_SCHED |
 DBG_UNSAFE_MATH);
 
rscreen->disk_shader_cache =
-   disk_cache_create(r600_get_family_name(rscreen),
+   
disk_cache_create(r600_get_llvm_processor_name(rscreen->family),
  timestamp_str,
  shader_debug_flags);
free(timestamp_str);
}
}
 }
 
 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen 
*pscreen)
 {
struct r600_common_screen *rscreen = (struct 
r600_common_screen*)pscreen;
-- 
2.7.4

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[Mesa-dev] [PATCH] radeonsi/gfx9: use the VI codepath for clamping Z

[Marek Olšák]

From: Marek Olšák 

This fixes corrupted shadows in Unigine Valley.
The corruption disappeared when I stopped setting IMG_DATA_FORMAT_24_8
for depth.

Cc: 17.2 
---
 src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c |  2 +-
 src/gallium/drivers/radeonsi/si_state.c   | 12 +---
 2 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c 
b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index 42f977d..f8c99ff 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -1385,21 +1385,21 @@ static void tex_fetch_args(
z = coords[ref_pos];
}
 
/* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
 * so the depth comparison value isn't clamped for Z16 and
 * Z24 anymore. Do it manually here.
 *
 * It's unnecessary if the original texture format was
 * Z32_FLOAT, but we don't know that here.
 */
-   if (ctx->screen->b.chip_class == VI)
+   if (ctx->screen->b.chip_class >= VI)
z = ac_build_clamp(>ac, z);
 
address[count++] = z;
}
 
/* Pack user derivatives */
if (opcode == TGSI_OPCODE_TXD) {
int param, num_src_deriv_channels, num_dst_deriv_channels;
 
switch (target) {
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 11dee49..2c413a4 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3170,28 +3170,27 @@ si_make_texture_descriptor(struct si_screen *screen,
   enum pipe_texture_target target,
   enum pipe_format pipe_format,
   const unsigned char state_swizzle[4],
   unsigned first_level, unsigned last_level,
   unsigned first_layer, unsigned last_layer,
   unsigned width, unsigned height, unsigned depth,
   uint32_t *state,
   uint32_t *fmask_state)
 {
struct pipe_resource *res = >resource.b.b;
-   const struct util_format_description *base_desc, *desc;
+   const struct util_format_description *desc;
unsigned char swizzle[4];
int first_non_void;
unsigned num_format, data_format, type;
uint64_t va;
 
desc = util_format_description(pipe_format);
-   base_desc = util_format_description(res->format);
 
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
const unsigned char swizzle_[4] = {0, 0, 0, 0};
const unsigned char swizzle_[4] = {1, 1, 1, 1};
const unsigned char swizzle_[4] = {3, 3, 3, 3};
 
switch (pipe_format) {
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
case PIPE_FORMAT_X32_S8X24_UINT:
case PIPE_FORMAT_X8Z24_UNORM:
@@ -3278,29 +3277,20 @@ si_make_texture_descriptor(struct si_screen *screen,
num_format = 
V_008F14_IMG_NUM_FORMAT_USCALED;
}
}
}
 
data_format = si_translate_texformat(>b.b, pipe_format, desc, 
first_non_void);
if (data_format == ~0) {
data_format = 0;
}
 
-   /* Enable clamping for UNORM depth formats promoted to Z32F. */
-   if (screen->b.chip_class >= GFX9 &&
-   util_format_has_depth(desc) &&
-   num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
-   util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
-   /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to 
[0,1]". */
-   data_format = V_008F14_IMG_DATA_FORMAT_24_8;
-   }
-
/* S8 with Z32 HTILE needs a special format. */
if (screen->b.chip_class >= GFX9 &&
pipe_format == PIPE_FORMAT_S8_UINT &&
tex->tc_compatible_htile)
data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
 
if (!sampler &&
(res->target == PIPE_TEXTURE_CUBE ||
 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
 (screen->b.chip_class <= VI &&
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 14/25] i965: Use a common table to translate logical to hardware types

[Matt Turner]

On Mon, Aug 7, 2017 at 3:43 PM, Scott D Phillips
 wrote:
> Matt Turner  writes:
>> ---
>>  src/intel/compiler/brw_reg_type.c | 65 
>> +--
>>  1 file changed, 29 insertions(+), 36 deletions(-)
>>
>> diff --git a/src/intel/compiler/brw_reg_type.c 
>> b/src/intel/compiler/brw_reg_type.c
>> index 8aac0ca009..b0696570e5 100644
>> --- a/src/intel/compiler/brw_reg_type.c
>> +++ b/src/intel/compiler/brw_reg_type.c
>> @@ -25,6 +25,29 @@
>>  #include "brw_eu_defines.h"
>>  #include "common/gen_device_info.h"
>>
>> +#define INVALID (-1)
>
> The reg and imm enums have only non-negative values, so the compiler
> could choose an underlying type that is unsigned. The compiler could
> then elide the assert checks against INVALID as impossible because the
> type is unsigned. I guess the code is effectively the same as before,
> just noticed the warning from clang while looking at the patch.

Thanks. I definitely would not have thought about this.

We discussed this on IRC a bit, and ultimately concluded that casting
to the enum type in the assertion was the best approach:

   assert(gen4_hw_type[type].imm_type != (enum hw_imm_type)INVALID);

I tried defining INVALID as 0xff -- the thinking being that regardless
of the size of the underlying type it should be representable, but
clang gave the same warning as before. I also tried putting the cast
directly in the INVALID macro, but the two assertions compare it
against different enum values.
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Re: [Mesa-dev] [PATCH v3 1/6] radeonsi: declare new user SGPR indices for bindless samplers/images

[Marek Olšák]

On Tue, Aug 8, 2017 at 6:57 PM, Samuel Pitoiset
 wrote:
> A new pair of user SGPR is needed for loading the bindless
> descriptors from shaders. Because the descriptors are global for
> all stages, there is no need to add separate indices for GFX9.
>
> v3: - fix merged shaders on GFX9
> v2: - fix declaring new bindless parameter
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/gallium/drivers/radeonsi/si_shader.c  | 21 +
>  src/gallium/drivers/radeonsi/si_shader.h  |  4 +++-
>  src/gallium/drivers/radeonsi/si_shader_internal.h |  1 +
>  3 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
> b/src/gallium/drivers/radeonsi/si_shader.c
> index 09053c355e..035e36fbab 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -2900,6 +2900,9 @@ static void si_set_ls_return_value_for_tcs(struct 
> si_shader_context *ctx)
> ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
> ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
> ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 
> 5);
> +   ret = si_insert_input_ptr_as_2xi32(ctx, ret,
> +   ctx->param_bindless_samplers_and_images,
> +   8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
>
> ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
>   8 + SI_SGPR_VS_STATE_BITS);
> @@ -2938,6 +2941,9 @@ static void si_set_es_return_value_for_gs(struct 
> si_shader_context *ctx)
> ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
>
> ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 
> 5);
> +   ret = si_insert_input_ptr_as_2xi32(ctx, ret,
> +   ctx->param_bindless_samplers_and_images,
> +   8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
>
> unsigned desc_param = ctx->param_vs_state_bits + 1;
> ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
> @@ -4249,6 +4255,8 @@ static void declare_default_desc_pointers(struct 
> si_shader_context *ctx,
>  {
> ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
> si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
> +   ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
> +   si_const_array(ctx->v8i32, 0));
> declare_per_stage_desc_pointers(ctx, fninfo, true);
>  }
>
> @@ -4388,8 +4396,9 @@ static void create_function(struct si_shader_context 
> *ctx)
> add_arg(, ARG_SGPR, ctx->i32); /* unused */
> add_arg(, ARG_SGPR, ctx->i32); /* unused */
>
> -   add_arg(, ARG_SGPR, ctx->i32); /* unused */
> -   add_arg(, ARG_SGPR, ctx->i32); /* unused */

Don't remove these unused inputs.

> +   ctx->param_bindless_samplers_and_images =
> +   add_arg(, ARG_SGPR, si_const_array(ctx->v8i32, 
> 0));
> +
> declare_per_stage_desc_pointers(ctx, ,
> ctx->type == 
> PIPE_SHADER_VERTEX);
> declare_vs_specific_input_sgprs(ctx, );
> @@ -4442,8 +4451,9 @@ static void create_function(struct si_shader_context 
> *ctx)
> add_arg(, ARG_SGPR, ctx->i32); /* unused 
> (SPI_SHADER_PGM_LO/HI_GS << 8) */
> add_arg(, ARG_SGPR, ctx->i32); /* unused 
> (SPI_SHADER_PGM_LO/HI_GS >> 24) */
>
> -   add_arg(, ARG_SGPR, ctx->i32); /* unused */
> -   add_arg(, ARG_SGPR, ctx->i32); /* unused */

Don't remove these unused inputs.

With those fixed, the patch is:

Reviewed-by: Marek Olšák 

Marek
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[Mesa-dev] [PATCH 00/13] clang warning fixes

[Matt Turner]

Just a simple series cleaning up various bits of code that clang warns about.

The only real change is to "i965/vec4: Return float from spill_cost_for_type()" 
which fixes an obvious mistake. The rest just cleans things up like marking 
internal functions static.

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[Mesa-dev] [PATCH 03/13] mesa: Don't compare unsigned for < 0

[Matt Turner]

The INTEL_performance_query spec says

   "Performance counter id 0 is reserved as an invalid counter."

GLuint counterid_to_index(GLuint counterid) just returns counterid - 1,
so with unsigned overflow rules, it will generate 0x given an
input of 0. 0x will trigger the counterIndex >= queryNumCounters
check, so the code worked as is. It just contained a useless comparison.
---
 src/mesa/main/performance_query.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/performance_query.c 
b/src/mesa/main/performance_query.c
index 56f6a7da8b..b9e7cf9961 100644
--- a/src/mesa/main/performance_query.c
+++ b/src/mesa/main/performance_query.c
@@ -349,7 +349,7 @@ _mesa_GetPerfCounterInfoINTEL(GLuint queryId, GLuint 
counterId,
 
counterIndex = counterid_to_index(counterId);
 
-   if (counterIndex < 0 || counterIndex >= queryNumCounters) {
+   if (counterIndex >= queryNumCounters) {
   _mesa_error(ctx, GL_INVALID_VALUE,
   "glGetPerfCounterInfoINTEL(invalid counterId)");
   return;
-- 
2.13.0

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[Mesa-dev] [PATCH 01/13] egl: Fix inclusion of egl.h+mesa_glinterop.h

[Matt Turner]

Previously clang would warn about redefinition of typedef EGLDisplay. Avoid
this by adding preprocessor guards to mesa_glinterop.h and including it
after EGL.h is indirectly included.
---
 include/GL/mesa_glinterop.h | 4 
 src/egl/drivers/dri2/egl_dri2.c | 2 +-
 src/egl/main/eglapi.c   | 2 +-
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/include/GL/mesa_glinterop.h b/include/GL/mesa_glinterop.h
index 173476a988..45fda93ca2 100644
--- a/include/GL/mesa_glinterop.h
+++ b/include/GL/mesa_glinterop.h
@@ -58,12 +58,16 @@ extern "C" {
 #endif
 
 /* Forward declarations to avoid inclusion of GL/glx.h */
+#ifndef GLX_H
 struct _XDisplay;
 struct __GLXcontextRec;
+#endif
 
 /* Forward declarations to avoid inclusion of EGL/egl.h */
+#ifndef __egl_h_
 typedef void *EGLDisplay;
 typedef void *EGLContext;
+#endif
 
 /** Returned error codes. */
 enum {
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index f0d1ded408..07a2c4dede 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -46,7 +46,6 @@
 #endif
 #include 
 #include 
-#include "GL/mesa_glinterop.h"
 #include 
 #include 
 
@@ -61,6 +60,7 @@
 #endif
 
 #include "egl_dri2.h"
+#include "GL/mesa_glinterop.h"
 #include "loader/loader.h"
 #include "util/u_atomic.h"
 #include "util/u_vector.h"
diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index 7f04218104..060705a5ec 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -88,7 +88,6 @@
 #include 
 #include "c99_compat.h"
 #include "c11/threads.h"
-#include "GL/mesa_glinterop.h"
 #include "util/macros.h"
 
 #include "eglglobals.h"
@@ -102,6 +101,7 @@
 #include "eglimage.h"
 #include "eglsync.h"
 
+#include "GL/mesa_glinterop.h"
 
 /**
  * Macros to help return an API entrypoint.
-- 
2.13.0

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[Mesa-dev] [PATCH 07/13] intel/isl: Remove 'inline' keywords

[Matt Turner]

Unless you have data, the compiler knows better than you whether a
function should be inlined.
---
 src/intel/isl/isl_emit_depth_stencil.c | 2 +-
 src/intel/isl/isl_format.c | 2 +-
 src/intel/isl/isl_surface_state.c  | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/isl/isl_emit_depth_stencil.c 
b/src/intel/isl/isl_emit_depth_stencil.c
index 0d541fd1ce..36d75f03b9 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -26,7 +26,7 @@
 #define __gen_address_type uint64_t
 #define __gen_user_data void
 
-static inline uint64_t
+static uint64_t
 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
 {
return addr + delta;
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index 435b0d003a..fba3ac5e1a 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -608,7 +608,7 @@ isl_formats_are_ccs_e_compatible(const struct 
gen_device_info *devinfo,
   fmtl1->channels.a.bits == fmtl2->channels.a.bits;
 }
 
-static inline bool
+static bool
 isl_format_has_channel_type(enum isl_format fmt, enum isl_base_type type)
 {
const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
diff --git a/src/intel/isl/isl_surface_state.c 
b/src/intel/isl/isl_surface_state.c
index e8bdb65962..f88af389cb 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -26,7 +26,7 @@
 #define __gen_address_type uint64_t
 #define __gen_user_data void
 
-static inline uint64_t
+static uint64_t
 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
 {
return addr + delta;
@@ -134,7 +134,7 @@ get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t 
usage)
  * hardware.  Note that this does NOT give you the actual hardware enum values
  * but an index into the isl_to_gen_[hv]align arrays above.
  */
-static inline struct isl_extent3d
+static struct isl_extent3d
 get_image_alignment(const struct isl_surf *surf)
 {
if (GEN_GEN >= 9) {
-- 
2.13.0

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[Mesa-dev] [PATCH 02/13] nir/spirv: Use unreachable("...") rather than assert(!"...")

[Matt Turner]

Quiets a number of uninitialized variable warnings in clang.
---
 src/compiler/spirv/spirv_to_nir.c  | 24 
 src/compiler/spirv/vtn_variables.c | 10 +-
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 7b34dad30c..870dda0314 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -262,7 +262,7 @@ vtn_handle_extension(struct vtn_builder *b, SpvOp opcode,
   if (strcmp((const char *)[2], "GLSL.std.450") == 0) {
  val->ext_handler = vtn_handle_glsl450_instruction;
   } else {
- assert(!"Unsupported extension");
+ unreachable("Unsupported extension");
   }
   break;
}
@@ -724,7 +724,7 @@ translate_image_format(SpvImageFormat format)
case SpvImageFormatR16ui:return 0x8234; /* GL_R16UI */
case SpvImageFormatR8ui: return 0x8232; /* GL_R8UI */
default:
-  assert(!"Invalid image format");
+  unreachable("Invalid image format");
   return 0;
}
 }
@@ -785,7 +785,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
   val->type->type = glsl_matrix_type(glsl_get_base_type(base->type),
  glsl_get_vector_elements(base->type),
  columns);
-  assert(!glsl_type_is_error(val->type->type));
+  unreachable(glsl_type_is_error(val->type->type));
   val->type->length = columns;
   val->type->array_element = base;
   val->type->row_major = false;
@@ -919,7 +919,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
  else if (dim == GLSL_SAMPLER_DIM_SUBPASS)
 dim = GLSL_SAMPLER_DIM_SUBPASS_MS;
  else
-assert(!"Unsupported multisampled image type");
+unreachable("Unsupported multisampled image type");
   }
 
   val->type->image_format = translate_image_format(format);
@@ -929,12 +929,12 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
  val->type->type = glsl_sampler_type(dim, is_shadow, is_array,
  glsl_get_base_type(sampled_type));
   } else if (sampled == 2) {
- assert(!is_shadow);
+ unreachable(is_shadow);
  val->type->sampled = false;
  val->type->type = glsl_image_type(dim, is_array,
glsl_get_base_type(sampled_type));
   } else {
- assert(!"We need to know if the image will be sampled");
+ unreachable("We need to know if the image will be sampled");
   }
   break;
}
@@ -1378,7 +1378,7 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
   break;
 
case SpvOpConstantSampler:
-  assert(!"OpConstantSampler requires Kernel Capability");
+  unreachable("OpConstantSampler requires Kernel Capability");
   break;
 
default:
@@ -2626,7 +2626,7 @@ gl_primitive_from_spv_execution_mode(SpvExecutionMode 
mode)
case SpvExecutionModeOutputTriangleStrip:
   return 5; /* GL_TRIANGLE_STRIP */
default:
-  assert(!"Invalid primitive type");
+  unreachable("Invalid primitive type");
   return 4;
}
 }
@@ -2646,7 +2646,7 @@ vertices_in_from_spv_execution_mode(SpvExecutionMode mode)
case SpvExecutionModeInputTrianglesAdjacency:
   return 6;
default:
-  assert(!"Invalid GS input mode");
+  unreachable("Invalid GS input mode");
   return 0;
}
 }
@@ -2974,7 +2974,7 @@ vtn_handle_execution_mode(struct vtn_builder *b, struct 
vtn_value *entry_point,
   break;
 
case SpvExecutionModeXfb:
-  assert(!"Unhandled execution mode");
+  unreachable("Unhandled execution mode");
   break;
 
case SpvExecutionModeVecTypeHint:
@@ -3008,7 +3008,7 @@ vtn_handle_variable_or_type_instruction(struct 
vtn_builder *b, SpvOp opcode,
case SpvOpMemberDecorate:
case SpvOpGroupDecorate:
case SpvOpGroupMemberDecorate:
-  assert(!"Invalid opcode types and variables section");
+  unreachable("Invalid opcode types and variables section");
   break;
 
case SpvOpTypeVoid:
@@ -3348,7 +3348,7 @@ spirv_to_nir(const uint32_t *words, size_t word_count,
vtn_handle_preamble_instruction);
 
if (b->entry_point == NULL) {
-  assert(!"Entry point not found");
+  unreachable("Entry point not found");
   ralloc_free(b);
   return NULL;
}
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 4432e72e54..077ad7bb1c 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -172,7 +172,7 @@ vtn_ssa_offset_pointer_dereference(struct vtn_builder *b,
   }
 
   /* This is the first access chain so we also need an offset */
-  assert(!offset);
+  unreachable(offset);
   offset = nir_imm_int(>nb, 0);
}
assert(offset);
@@ -599,7 +599,7 

[Mesa-dev] [PATCH 06/13] anv: Remove 'inline' keywords

[Matt Turner]

Unless you have data, the compiler knows better than you whether a
function should be inlined.
---
 src/intel/vulkan/anv_batch_chain.c |  4 ++--
 src/intel/vulkan/anv_blorp.c   |  2 +-
 src/intel/vulkan/gen7_cmd_buffer.c |  2 +-
 src/intel/vulkan/gen8_cmd_buffer.c |  4 ++--
 src/intel/vulkan/genX_gpu_memcpy.c |  2 +-
 src/intel/vulkan/genX_pipeline.c   | 18 +-
 src/intel/vulkan/genX_query.c  |  2 +-
 src/intel/vulkan/genX_state.c  |  4 ++--
 8 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/src/intel/vulkan/anv_batch_chain.c 
b/src/intel/vulkan/anv_batch_chain.c
index ad76dc1fc0..3726ad5dfd 100644
--- a/src/intel/vulkan/anv_batch_chain.c
+++ b/src/intel/vulkan/anv_batch_chain.c
@@ -441,7 +441,7 @@ anv_batch_bo_list_clone(const struct list_head *list,
  * Functions related to anv_batch_bo
  *---*/
 
-static inline struct anv_batch_bo *
+static struct anv_batch_bo *
 anv_cmd_buffer_current_batch_bo(struct anv_cmd_buffer *cmd_buffer)
 {
return LIST_ENTRY(struct anv_batch_bo, cmd_buffer->batch_bos.prev, link);
@@ -846,7 +846,7 @@ anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer 
*cmd_buffer)
}
 }
 
-static inline VkResult
+static VkResult
 anv_cmd_buffer_add_seen_bbos(struct anv_cmd_buffer *cmd_buffer,
  struct list_head *list)
 {
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 860e50ac48..09d360e987 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -594,7 +594,7 @@ do_buffer_copy(struct blorp_batch *batch,
 /**
  * Returns the greatest common divisor of a and b that is a power of two.
  */
-static inline uint64_t
+static uint64_t
 gcd_pow2_u64(uint64_t a, uint64_t b)
 {
assert(a > 0 || b > 0);
diff --git a/src/intel/vulkan/gen7_cmd_buffer.c 
b/src/intel/vulkan/gen7_cmd_buffer.c
index 5f7b5a07e4..b05a0fd913 100644
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -34,7 +34,7 @@
 #include "genxml/genX_pack.h"
 
 #if GEN_GEN == 7 && !GEN_IS_HASWELL
-static inline int64_t
+static int64_t
 clamp_int64(int64_t x, int64_t min, int64_t max)
 {
if (x < min)
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c 
b/src/intel/vulkan/gen8_cmd_buffer.c
index a209d70161..f253b23ee2 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -167,7 +167,7 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer 
*cmd_buffer, bool enable)
}
 }
 
-static inline bool
+static bool
 want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer)
 {
assert(GEN_GEN == 8);
@@ -256,7 +256,7 @@ want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer)
   wm_prog_data->computed_depth_mode != PSCDEPTH_OFF;
 }
 
-static inline bool
+static bool
 want_stencil_pma_fix(struct anv_cmd_buffer *cmd_buffer)
 {
assert(GEN_GEN == 9);
diff --git a/src/intel/vulkan/genX_gpu_memcpy.c 
b/src/intel/vulkan/genX_gpu_memcpy.c
index db723d4a52..6ed9ac7366 100644
--- a/src/intel/vulkan/genX_gpu_memcpy.c
+++ b/src/intel/vulkan/genX_gpu_memcpy.c
@@ -36,7 +36,7 @@
 /**
  * Returns the greatest common divisor of a and b that is a power of two.
  */
-static inline uint64_t
+static uint64_t
 gcd_pow2_u64(uint64_t a, uint64_t b)
 {
assert(a > 0 || b > 0);
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 55db5339d6..6390bd4f6a 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -281,7 +281,7 @@ genX(emit_urb_setup)(struct anv_device *device, struct 
anv_batch *batch,
}
 }
 
-static inline void
+static void
 emit_urb_setup(struct anv_pipeline *pipeline)
 {
unsigned entry_size[4];
@@ -1077,19 +1077,19 @@ emit_3dstate_streamout(struct anv_pipeline *pipeline,
}
 }
 
-static inline uint32_t
+static uint32_t
 get_sampler_count(const struct anv_shader_bin *bin)
 {
return DIV_ROUND_UP(bin->bind_map.sampler_count, 4);
 }
 
-static inline uint32_t
+static uint32_t
 get_binding_table_entry_count(const struct anv_shader_bin *bin)
 {
return DIV_ROUND_UP(bin->bind_map.surface_count, 32);
 }
 
-static inline struct anv_address
+static struct anv_address
 get_scratch_address(struct anv_pipeline *pipeline,
 gl_shader_stage stage,
 const struct anv_shader_bin *bin)
@@ -1102,20 +1102,20 @@ get_scratch_address(struct anv_pipeline *pipeline,
};
 }
 
-static inline uint32_t
+static uint32_t
 get_scratch_space(const struct anv_shader_bin *bin)
 {
return ffs(bin->prog_data->total_scratch / 2048);
 }
 
-static inline uint32_t
+static uint32_t
 get_urb_output_offset()
 {
/* Skip the VUE header and position slots */
return 1;
 }
 
-static inline uint32_t
+static uint32_t
 get_urb_output_length(const struct anv_shader_bin *bin)
 {
const struct brw_vue_prog_data *prog_data =
@@ -1333,7 +1333,7 @@ emit_3dstate_gs(struct anv_pipeline *pipeline)
}
 }
 

[Mesa-dev] [PATCH 04/13] glsl: Remove unused private fields

[Matt Turner]

---
 src/compiler/glsl/lower_int64.cpp | 4 +---
 src/mesa/program/ir_to_mesa.cpp   | 3 +--
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/src/compiler/glsl/lower_int64.cpp 
b/src/compiler/glsl/lower_int64.cpp
index 9770d314af..aa2e1e063d 100644
--- a/src/compiler/glsl/lower_int64.cpp
+++ b/src/compiler/glsl/lower_int64.cpp
@@ -69,7 +69,7 @@ namespace {
 class lower_64bit_visitor : public ir_rvalue_visitor {
 public:
lower_64bit_visitor(void *mem_ctx, exec_list *instructions, unsigned lower)
-  : progress(false), lower(lower), instructions(instructions),
+  : progress(false), lower(lower),
 function_list(), added_functions(_list, mem_ctx)
{
   functions = _mesa_hash_table_create(mem_ctx,
@@ -111,8 +111,6 @@ public:
 private:
unsigned lower; /** Bitfield of which operations to lower */
 
-   exec_list *instructions;
-
/** Hashtable containing all of the known functions in the IR */
struct hash_table *functions;
 
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index ac12b59d07..67a4ad4a7c 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -2410,7 +2410,7 @@ class add_uniform_to_shader : public 
program_resource_visitor {
 public:
add_uniform_to_shader(struct gl_shader_program *shader_program,
 struct gl_program_parameter_list *params)
-  : shader_program(shader_program), params(params), idx(-1)
+  : params(params), idx(-1)
{
   /* empty */
}
@@ -2429,7 +2429,6 @@ private:
 const enum glsl_interface_packing packing,
 bool last_field);
 
-   struct gl_shader_program *shader_program;
struct gl_program_parameter_list *params;
int idx;
ir_variable *var;
-- 
2.13.0

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[Mesa-dev] [PATCH 05/13] anv: Move clamp_int64() inside the IVB check

[Matt Turner]

It's only used in the gen7_cmd_buffer_emit_scissor() function.
---
 src/intel/vulkan/gen7_cmd_buffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/gen7_cmd_buffer.c 
b/src/intel/vulkan/gen7_cmd_buffer.c
index b1721c78ba..5f7b5a07e4 100644
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -33,6 +33,7 @@
 #include "genxml/gen_macros.h"
 #include "genxml/genX_pack.h"
 
+#if GEN_GEN == 7 && !GEN_IS_HASWELL
 static inline int64_t
 clamp_int64(int64_t x, int64_t min, int64_t max)
 {
@@ -44,7 +45,6 @@ clamp_int64(int64_t x, int64_t min, int64_t max)
   return max;
 }
 
-#if GEN_GEN == 7 && !GEN_IS_HASWELL
 void
 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
 {
-- 
2.13.0

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[Mesa-dev] [PATCH 08/13] i965: Remove some 'inline' keywords

[Matt Turner]

brw_texture_view_sane() is only used by an assert()...
---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 17fa1ce8fe..04ad4ce895 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -100,7 +100,7 @@ __gen_combine_address(struct brw_context *brw, void 
*location,
}
 }
 
-static inline struct brw_address
+static struct brw_address
 rw_bo(struct brw_bo *bo, uint32_t offset)
 {
return (struct brw_address) {
@@ -110,7 +110,7 @@ rw_bo(struct brw_bo *bo, uint32_t offset)
};
 }
 
-static inline struct brw_address
+static struct brw_address
 ro_bo(struct brw_bo *bo, uint32_t offset)
 {
return (struct brw_address) {
@@ -119,7 +119,7 @@ ro_bo(struct brw_bo *bo, uint32_t offset)
};
 }
 
-static inline struct brw_address
+static struct brw_address
 ggtt_bo(struct brw_bo *bo, uint32_t offset)
 {
return (struct brw_address) {
@@ -130,13 +130,13 @@ ggtt_bo(struct brw_bo *bo, uint32_t offset)
 }
 
 #if GEN_GEN == 4
-static inline struct brw_address
+static struct brw_address
 KSP(struct brw_context *brw, uint32_t offset)
 {
return ro_bo(brw->cache.bo, offset);
 }
 #else
-static inline uint32_t
+static uint32_t
 KSP(struct brw_context *brw, uint32_t offset)
 {
return offset;
@@ -2201,7 +2201,7 @@ const struct brw_tracked_state genX(cc_vp) = {
 
 /* -- */
 
-static inline void
+static void
 set_scissor_bits(const struct gl_context *ctx, int i,
  bool render_to_fbo, unsigned fb_width, unsigned fb_height,
  struct GENX(SCISSOR_RECT) *sc)
@@ -3656,7 +3656,7 @@ genX(upload_3dstate_so_buffers)(struct brw_context *brw)
 #endif
 }
 
-static inline bool
+static bool
 query_active(struct gl_query_object *q)
 {
return q && q->Active;
-- 
2.13.0

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[Mesa-dev] [PATCH 10/13] i965/vec4: Use 'class' src_reg, rather than 'struct' src_reg

[Matt Turner]

---
 src/intel/compiler/brw_vec4.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 410922c62b..45e918127d 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -1950,7 +1950,7 @@ vec4_visitor::convert_to_hw_regs()
 {
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
   for (int i = 0; i < 3; i++) {
- struct src_reg  = inst->src[i];
+ class src_reg  = inst->src[i];
  struct brw_reg reg;
  switch (src.file) {
  case VGRF: {
-- 
2.13.0

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[Mesa-dev] [PATCH 13/13] glsl: Add prototype for udivmod64()

[Matt Turner]

---
 src/compiler/glsl/builtin_functions.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/compiler/glsl/builtin_functions.h 
b/src/compiler/glsl/builtin_functions.h
index 2053c82b74..89ec9b7d5d 100644
--- a/src/compiler/glsl/builtin_functions.h
+++ b/src/compiler/glsl/builtin_functions.h
@@ -64,6 +64,9 @@ umul64(void *mem_ctx, builtin_available_predicate avail);
 ir_function_signature *
 sign64(void *mem_ctx, builtin_available_predicate avail);
 
+ir_function_signature *
+udivmod64(void *mem_ctx, builtin_available_predicate avail);
+
 }
 
 #endif /* BULITIN_FUNCTIONS_H */
-- 
2.13.0

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[Mesa-dev] [PATCH 09/13] i965/vec4: Return float from spill_cost_for_type()

[Matt Turner]

---
 src/intel/compiler/brw_vec4_reg_allocate.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_vec4_reg_allocate.cpp 
b/src/intel/compiler/brw_vec4_reg_allocate.cpp
index a0ba77b867..bbad46ee6c 100644
--- a/src/intel/compiler/brw_vec4_reg_allocate.cpp
+++ b/src/intel/compiler/brw_vec4_reg_allocate.cpp
@@ -369,7 +369,7 @@ can_use_scratch_for_source(const vec4_instruction *inst, 
unsigned i,
return prev_inst_read_scratch_reg;
 }
 
-static inline unsigned
+static inline float
 spill_cost_for_type(enum brw_reg_type type)
 {
/* Spilling of a 64-bit register involves emitting 2 32-bit scratch
-- 
2.13.0

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[Mesa-dev] [PATCH 11/13] i965: Mark functions static

[Matt Turner]

Cuts 300 bytes of .text
---
 src/intel/compiler/brw_fs_surface_builder.cpp   | 30 -
 src/intel/compiler/brw_vec4_nir.cpp |  5 +++--
 src/intel/compiler/brw_vec4_surface_builder.cpp |  6 ++---
 3 files changed, 21 insertions(+), 20 deletions(-)

diff --git a/src/intel/compiler/brw_fs_surface_builder.cpp 
b/src/intel/compiler/brw_fs_surface_builder.cpp
index 8990a5ca71..d00d8920b2 100644
--- a/src/intel/compiler/brw_fs_surface_builder.cpp
+++ b/src/intel/compiler/brw_fs_surface_builder.cpp
@@ -169,7 +169,7 @@ namespace {
* they come in from SPIR-V or Vulkan.  We need to turn them into an ISL
* enum before we can use them.
*/
-  enum isl_format
+  static enum isl_format
   isl_format_for_gl_format(uint32_t gl_format)
   {
  switch (gl_format) {
@@ -358,7 +358,7 @@ namespace {
   /**
* Check whether the bound image is suitable for untyped access.
*/
-  brw_predicate
+  static brw_predicate
   emit_untyped_image_check(const fs_builder , const fs_reg ,
brw_predicate pred)
   {
@@ -390,7 +390,7 @@ namespace {
* the comparison result to f0.0.  Returns an appropriate predication
* mode to use on subsequent image operations.
*/
-  brw_predicate
+  static brw_predicate
   emit_typed_atomic_check(const fs_builder , const fs_reg )
   {
  const gen_device_info *devinfo = bld.shader->devinfo;
@@ -420,7 +420,7 @@ namespace {
* and write the comparison result to f0.0.  Returns an appropriate
* predication mode to use on subsequent image operations.
*/
-  brw_predicate
+  static brw_predicate
   emit_bounds_check(const fs_builder , const fs_reg ,
 const fs_reg , unsigned dims)
   {
@@ -443,7 +443,7 @@ namespace {
* the surface, which may be more than the sum of \p surf_dims and \p
* arr_dims if padding is required.
*/
-  unsigned
+  static unsigned
   num_image_coordinates(const fs_builder ,
 unsigned surf_dims, unsigned arr_dims,
 isl_format format)
@@ -465,7 +465,7 @@ namespace {
* Transform image coordinates into the form expected by the
* implementation.
*/
-  fs_reg
+  static fs_reg
   emit_image_coordinates(const fs_builder , const fs_reg ,
  unsigned surf_dims, unsigned arr_dims,
  isl_format format)
@@ -505,7 +505,7 @@ namespace {
* Section 4.5 "Address Tiling Function" of the IVB PRM for an in-depth
* explanation of the hardware tiling format.
*/
-  fs_reg
+  static fs_reg
   emit_address_calculation(const fs_builder , const fs_reg ,
const fs_reg , unsigned dims)
   {
@@ -679,7 +679,7 @@ namespace {
* shifts and widths.  Note that bitfield components are not allowed to
* cross 32-bit boundaries.
*/
-  fs_reg
+  static fs_reg
   emit_pack(const fs_builder , const fs_reg ,
 const color_u , const color_u )
   {
@@ -712,7 +712,7 @@ namespace {
* shifts and widths.  Note that bitfield components are not allowed to
* cross 32-bit boundaries.
*/
-  fs_reg
+  static fs_reg
   emit_unpack(const fs_builder , const fs_reg ,
   const color_u , const color_u )
   {
@@ -740,7 +740,7 @@ namespace {
* Convert an integer vector into another integer vector of the
* specified bit widths, properly handling overflow.
*/
-  fs_reg
+  static fs_reg
   emit_convert_to_integer(const fs_builder , const fs_reg ,
   const color_u , bool is_signed)
   {
@@ -780,7 +780,7 @@ namespace {
* Convert a normalized fixed-point vector of the specified signedness
* and bit widths into a floating point vector.
*/
-  fs_reg
+  static fs_reg
   emit_convert_from_scaled(const fs_builder , const fs_reg ,
const color_u , bool is_signed)
   {
@@ -810,7 +810,7 @@ namespace {
* Convert a floating-point vector into a normalized fixed-point vector
* of the specified signedness and bit widths.
*/
-  fs_reg
+  static fs_reg
   emit_convert_to_scaled(const fs_builder , const fs_reg ,
  const color_u , bool is_signed)
   {
@@ -859,7 +859,7 @@ namespace {
* Convert a floating point vector of the specified bit widths into a
* 32-bit floating point vector.
*/
-  fs_reg
+  static fs_reg
   emit_convert_from_float(const fs_builder , const fs_reg ,
   const color_u )
   {
@@ -890,7 +890,7 @@ namespace {
* Convert a vector into a floating point vector of the specified bit

[Mesa-dev] [PATCH 12/13] glsl: Mark functions static

[Matt Turner]

Cuts 3224 bytes of .text
---
 src/compiler/glsl/ast_function.cpp  | 10 +-
 src/compiler/glsl/ast_to_hir.cpp|  6 +++---
 src/compiler/glsl/glsl_parser_extras.cpp|  2 +-
 src/compiler/glsl/ir_validate.cpp   |  2 +-
 src/compiler/glsl/link_uniform_initializers.cpp | 10 +-
 src/compiler/glsl/link_varyings.cpp |  8 
 src/compiler/glsl/linker.cpp| 20 ++--
 src/compiler/glsl/lower_if_to_cond_assign.cpp   |  4 ++--
 src/compiler/glsl/lower_vector.cpp  |  2 +-
 src/compiler/glsl/main.cpp  |  2 +-
 src/compiler/glsl/standalone.cpp|  6 +++---
 11 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/src/compiler/glsl/ast_function.cpp 
b/src/compiler/glsl/ast_function.cpp
index f7e90fba5b..51f188486c 100644
--- a/src/compiler/glsl/ast_function.cpp
+++ b/src/compiler/glsl/ast_function.cpp
@@ -1272,7 +1272,7 @@ process_array_constructor(exec_list *instructions,
 /**
  * Determine if a list consists of a single scalar r-value
  */
-bool
+static bool
 single_scalar_parameter(exec_list *parameters)
 {
const ir_rvalue *const p = (ir_rvalue *) parameters->get_head_raw();
@@ -1293,7 +1293,7 @@ single_scalar_parameter(exec_list *parameters)
  * An \c ir_dereference_variable of the temprorary generated in the constructor
  * body.
  */
-ir_rvalue *
+static ir_rvalue *
 emit_inline_vector_constructor(const glsl_type *type,
exec_list *instructions,
exec_list *parameters,
@@ -1457,7 +1457,7 @@ emit_inline_vector_constructor(const glsl_type *type,
  * \c src_base + \c count must be less than or equal to the number of
  * components in the source vector.
  */
-ir_instruction *
+static ir_instruction *
 assign_to_matrix_column(ir_variable *var, unsigned column, unsigned row_base,
 ir_rvalue *src, unsigned src_base, unsigned count,
 void *mem_ctx)
@@ -1497,7 +1497,7 @@ assign_to_matrix_column(ir_variable *var, unsigned 
column, unsigned row_base,
  * An \c ir_dereference_variable of the temprorary generated in the constructor
  * body.
  */
-ir_rvalue *
+static ir_rvalue *
 emit_inline_matrix_constructor(const glsl_type *type,
exec_list *instructions,
exec_list *parameters,
@@ -1766,7 +1766,7 @@ emit_inline_matrix_constructor(const glsl_type *type,
 }
 
 
-ir_rvalue *
+static ir_rvalue *
 emit_inline_record_constructor(const glsl_type *type,
exec_list *instructions,
exec_list *parameters,
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index ee80605232..ef1b3002d8 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -1182,7 +1182,7 @@ do_comparison(void *mem_ctx, int operation, ir_rvalue 
*op0, ir_rvalue *op1)
  * scalar booleans.  If it isn't, emit an error and return a constant
  * boolean to avoid triggering cascading error messages.
  */
-ir_rvalue *
+static ir_rvalue *
 get_scalar_boolean_operand(exec_list *instructions,
struct _mesa_glsl_parse_state *state,
ast_expression *parent_expr,
@@ -4320,7 +4320,7 @@ get_variable_being_redeclared(ir_variable *var, YYLTYPE 
loc,
 /**
  * Generate the IR for an initializer in a variable declaration
  */
-ir_rvalue *
+static ir_rvalue *
 process_initializer(ir_variable *var, ast_declaration *decl,
 ast_fully_specified_type *type,
 exec_list *initializer_instructions,
@@ -4714,7 +4714,7 @@ handle_geometry_shader_input_decl(struct 
_mesa_glsl_parse_state *state,
   "geometry shader input");
 }
 
-void
+static void
 validate_identifier(const char *identifier, YYLTYPE loc,
 struct _mesa_glsl_parse_state *state)
 {
diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index 8f1651d494..cfb214e440 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -1079,7 +1079,7 @@ _mesa_ast_process_interface_block(YYLTYPE *locp,
}
 }
 
-void
+static void
 _mesa_ast_type_qualifier_print(const struct ast_type_qualifier *q)
 {
if (q->is_subroutine_decl())
diff --git a/src/compiler/glsl/ir_validate.cpp 
b/src/compiler/glsl/ir_validate.cpp
index 6e2f3e5b50..f6503fb4e8 100644
--- a/src/compiler/glsl/ir_validate.cpp
+++ b/src/compiler/glsl/ir_validate.cpp
@@ -1035,7 +1035,7 @@ ir_validate::validate_ir(ir_instruction *ir, void *data)
_mesa_set_add(ir_set, ir);
 }
 
-void
+static void
 check_node_type(ir_instruction *ir, void *data)
 {
(void) data;
diff --git a/src/compiler/glsl/link_uniform_initializers.cpp 
b/src/compiler/glsl/link_uniform_initializers.cpp
index 

[Mesa-dev] [PATCH 4/7 v2] configure.ac: Introduce HAVE_ARM_ASM/HAVE_AARCH64_ASM and the -D flags.

[Eric Anholt]

I've been trying to get away without these conditionals in vc4's NEON
code, but it meant compiling extra unused code on x86, and build failing
on ARMv6.

v2: Use the _arm/_arm64 flags to simplify detection (suggested by Rob),
but hide the _arm version under ARCH_ARM_HAVE_NEON to keep from trying
to build this stuff for armv5te.
---
 Android.common.mk |  4 
 configure.ac  | 24 
 2 files changed, 28 insertions(+)

diff --git a/Android.common.mk b/Android.common.mk
index 6bd30816bc41..e5416c4e3839 100644
--- a/Android.common.mk
+++ b/Android.common.mk
@@ -88,6 +88,10 @@ LOCAL_CFLAGS += \
 
 endif
 endif
+ifeq ($(ARCH_ARM_HAVE_NEON),true)
+LOCAL_CFLAGS_arm += -DUSE_ARM_ASM
+endif
+LOCAL_CFLAGS_arm64 += -DUSE_AARCH64_ASM
 
 ifneq ($(LOCAL_IS_HOST_MODULE),true)
 LOCAL_CFLAGS += -DHAVE_LIBDRM
diff --git a/configure.ac b/configure.ac
index 5b12dd8506a5..d4f36898ba5b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -773,6 +773,20 @@ if test "x$enable_asm" = xyes; then
 ;;
 esac
 ;;
+aarch64)
+case "$host_os" in
+linux*)
+asm_arch=aarch64
+;;
+esac
+;;
+arm)
+case "$host_os" in
+linux*)
+asm_arch=arm
+;;
+esac
+;;
 esac
 
 case "$asm_arch" in
@@ -792,6 +806,14 @@ if test "x$enable_asm" = xyes; then
 DEFINES="$DEFINES -DUSE_PPC64LE_ASM"
 AC_MSG_RESULT([yes, ppc64le])
 ;;
+aarch64)
+DEFINES="$DEFINES -DUSE_AARCH64_ASM"
+AC_MSG_RESULT([yes, aarch64])
+;;
+arm)
+DEFINES="$DEFINES -DUSE_ARM_ASM"
+AC_MSG_RESULT([yes, arm])
+;;
 *)
 AC_MSG_RESULT([no, platform not supported])
 ;;
@@ -2729,6 +2751,8 @@ AM_CONDITIONAL(HAVE_X86_ASM, test "x$asm_arch" = xx86 -o 
"x$asm_arch" = xx86_64)
 AM_CONDITIONAL(HAVE_X86_64_ASM, test "x$asm_arch" = xx86_64)
 AM_CONDITIONAL(HAVE_SPARC_ASM, test "x$asm_arch" = xsparc)
 AM_CONDITIONAL(HAVE_PPC64LE_ASM, test "x$asm_arch" = xppc64le)
+AM_CONDITIONAL(HAVE_AARCH64_ASM, test "x$asm_arch" = xaarch64)
+AM_CONDITIONAL(HAVE_ARM_ASM, test "x$asm_arch" = xarm)
 
 AC_SUBST([NINE_MAJOR], 1)
 AC_SUBST([NINE_MINOR], 0)
-- 
2.13.3

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[Mesa-dev] [PATCH 5/7 v2] broadcom/vc4: Build the vc4_tiling_lt_neon.c with -mfpu=neon on ARM.

[Eric Anholt]

If you don't pass this, the compiler refuses to compile the assembly for
pre-v7 CPUs.  This also keeps us from building identical, non-NEON code on
aarch64 and x86.

Fixes: a373f77662c5 ("vc4: Use a wrapper file to set VC4_BUILD_NEON instead of 
CFLAGS.")

v2: Fix Android build by just appending NEON_C_SOURCES when
ARCH_ARM_HAVE_NEON.
---
 src/gallium/drivers/vc4/Android.mk   |  4 
 src/gallium/drivers/vc4/Makefile.am  |  7 +++
 src/gallium/drivers/vc4/Makefile.sources |  3 ++-
 src/gallium/drivers/vc4/vc4_tiling.h | 17 +++--
 4 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/vc4/Android.mk 
b/src/gallium/drivers/vc4/Android.mk
index 84bfaa839f9e..fc141de3ca8e 100644
--- a/src/gallium/drivers/vc4/Android.mk
+++ b/src/gallium/drivers/vc4/Android.mk
@@ -28,6 +28,10 @@ include $(CLEAR_VARS)
 LOCAL_SRC_FILES := \
$(C_SOURCES)
 
+ifeq ($(ARCH_ARM_HAVE_NEON),true)
+LOCAL_SRC_FILES += $(NEON_C_SOURCES)
+endif
+
 LOCAL_GENERATED_SOURCES := $(MESA_GEN_NIR_H)
 LOCAL_C_INCLUDES := \
$(MESA_TOP)/include/drm-uapi
diff --git a/src/gallium/drivers/vc4/Makefile.am 
b/src/gallium/drivers/vc4/Makefile.am
index 9b0ef6ef790e..4c2b7486c522 100644
--- a/src/gallium/drivers/vc4/Makefile.am
+++ b/src/gallium/drivers/vc4/Makefile.am
@@ -44,6 +44,13 @@ libvc4_la_LIBADD = \
$(top_builddir)/src/broadcom/cle/libbroadcom_cle.la \
$()
 
+if HAVE_ARM_ASM
+noinst_LTLIBRARIES += libvc4_neon.la
+libvc4_la_LIBADD += libvc4_neon.la
+libvc4_neon_la_SOURCES = $(NEON_C_SOURCES)
+libvc4_neon_la_CFLAGS = $(AM_CFLAGS) -mfpu=neon
+endif
+
 libvc4_la_LDFLAGS = $(SIM_LDFLAGS)
 
 EXTRA_DIST = kernel/README
diff --git a/src/gallium/drivers/vc4/Makefile.sources 
b/src/gallium/drivers/vc4/Makefile.sources
index f67dffe00636..76dea7041b72 100644
--- a/src/gallium/drivers/vc4/Makefile.sources
+++ b/src/gallium/drivers/vc4/Makefile.sources
@@ -57,7 +57,8 @@ C_SOURCES := \
vc4_state.c \
vc4_tiling.c \
vc4_tiling_lt.c \
-   vc4_tiling_lt_neon.c \
vc4_tiling.h \
vc4_uniforms.c \
$()
+
+NEON_C_SOURCES := vc4_tiling_lt_neon.c
diff --git a/src/gallium/drivers/vc4/vc4_tiling.h 
b/src/gallium/drivers/vc4/vc4_tiling.h
index 3168ec20a606..66767e7f1f83 100644
--- a/src/gallium/drivers/vc4/vc4_tiling.h
+++ b/src/gallium/drivers/vc4/vc4_tiling.h
@@ -89,13 +89,15 @@ vc4_load_lt_image(void *dst, uint32_t dst_stride,
   void *src, uint32_t src_stride,
   int cpp, const struct pipe_box *box)
 {
+#ifdef USE_ARM_ASM
 if (util_cpu_caps.has_neon) {
 vc4_load_lt_image_neon(dst, dst_stride, src, src_stride,
cpp, box);
-} else {
-vc4_load_lt_image_base(dst, dst_stride, src, src_stride,
-   cpp, box);
+return;
 }
+#endif
+vc4_load_lt_image_base(dst, dst_stride, src, src_stride,
+   cpp, box);
 }
 
 static inline void
@@ -103,13 +105,16 @@ vc4_store_lt_image(void *dst, uint32_t dst_stride,
void *src, uint32_t src_stride,
int cpp, const struct pipe_box *box)
 {
+#ifdef USE_ARM_ASM
 if (util_cpu_caps.has_neon) {
 vc4_store_lt_image_neon(dst, dst_stride, src, src_stride,
 cpp, box);
-} else {
-vc4_store_lt_image_base(dst, dst_stride, src, src_stride,
-cpp, box);
+return;
 }
+#endif
+
+vc4_store_lt_image_base(dst, dst_stride, src, src_stride,
+cpp, box);
 }
 
 #endif /* VC4_TILING_H */
-- 
2.13.3

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[Mesa-dev] [PATCH 6/7 v3] broadcom/vc4: Port NEON-code to ARM64

[Eric Anholt]

From: Jonas Pfeil 

Changed all register and instruction names, works the same.

v2: Rebase on build system changes (by anholt)
v3: Fix build on clang (by anholt, reported by Rob)

Signed-off-by: Jonas Pfeil 
---
 src/gallium/drivers/vc4/vc4_tiling_lt.c | 84 +
 1 file changed, 84 insertions(+)

diff --git a/src/gallium/drivers/vc4/vc4_tiling_lt.c 
b/src/gallium/drivers/vc4/vc4_tiling_lt.c
index f37a92e9390e..4a76c0ff7218 100644
--- a/src/gallium/drivers/vc4/vc4_tiling_lt.c
+++ b/src/gallium/drivers/vc4/vc4_tiling_lt.c
@@ -105,6 +105,50 @@ vc4_load_utile(void *cpu, void *gpu, uint32_t cpu_stride, 
uint32_t cpp)
 : "r"(gpu), "r"(cpu), "r"(cpu + 8), "r"(cpu_stride)
 : "q0", "q1", "q2", "q3");
 }
+#elif defined (PIPE_ARCH_AARCH64)
+   if (gpu_stride == 8) {
+__asm__ volatile (
+/* Load from the GPU in one shot, no interleave, to
+ * d0-d7.
+ */
+"ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [%0]\n"
+/* Store each 8-byte line to cpu-side destination,
+ * incrementing it by the stride each time.
+ */
+"st1 {v0.D}[0], [%1], %2\n"
+"st1 {v0.D}[1], [%1], %2\n"
+"st1 {v1.D}[0], [%1], %2\n"
+"st1 {v1.D}[1], [%1], %2\n"
+"st1 {v2.D}[0], [%1], %2\n"
+"st1 {v2.D}[1], [%1], %2\n"
+"st1 {v3.D}[0], [%1], %2\n"
+"st1 {v3.D}[1], [%1]\n"
+   :
+: "r"(gpu), "r"(cpu), "r"(cpu_stride)
+: "v0", "v1", "v2", "v3");
+} else {
+assert(gpu_stride == 16);
+__asm__ volatile (
+/* Load from the GPU in one shot, no interleave, to
+ * d0-d7.
+ */
+"ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [%0]\n"
+/* Store each 16-byte line in 2 parts to the cpu-side
+ * destination.  (vld1 can only store one d-register
+ * at a time).
+ */
+"st1 {v0.D}[0], [%1], %3\n"
+"st1 {v0.D}[1], [%2], %3\n"
+"st1 {v1.D}[0], [%1], %3\n"
+"st1 {v1.D}[1], [%2], %3\n"
+"st1 {v2.D}[0], [%1], %3\n"
+"st1 {v2.D}[1], [%2], %3\n"
+"st1 {v3.D}[0], [%1]\n"
+"st1 {v3.D}[1], [%2]\n"
+:
+: "r"(gpu), "r"(cpu), "r"(cpu + 8), "r"(cpu_stride)
+: "v0", "v1", "v2", "v3");
+}
 #else
 for (uint32_t gpu_offset = 0; gpu_offset < 64; gpu_offset += 
gpu_stride) {
 memcpy(cpu, gpu + gpu_offset, gpu_stride);
@@ -160,6 +204,46 @@ vc4_store_utile(void *gpu, void *cpu, uint32_t cpu_stride, 
uint32_t cpp)
 : "r"(gpu), "r"(cpu), "r"(cpu + 8), "r"(cpu_stride)
 : "q0", "q1", "q2", "q3");
 }
+#elif defined (PIPE_ARCH_AARCH64)
+   if (gpu_stride == 8) {
+__asm__ volatile (
+/* Load each 8-byte line from cpu-side source,
+ * incrementing it by the stride each time.
+ */
+"ld1 {v0.D}[0], [%1], %2\n"
+"ld1 {v0.D}[1], [%1], %2\n"
+"ld1 {v1.D}[0], [%1], %2\n"
+"ld1 {v1.D}[1], [%1], %2\n"
+"ld1 {v2.D}[0], [%1], %2\n"
+"ld1 {v2.D}[1], [%1], %2\n"
+"ld1 {v3.D}[0], [%1], %2\n"
+"ld1 {v3.D}[1], [%1]\n"
+/* Store to the GPU in one shot, no interleave. */
+"st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [%0]\n"
+:
+: "r"(gpu), "r"(cpu), "r"(cpu_stride)
+: "v0", "v1", "v2", "v3");
+} else {
+assert(gpu_stride == 16);
+__asm__ volatile (
+/* Load each 16-byte line in 2 parts from the cpu-side
+ * destination.  (vld1 can only store one d-register
+ * at a time).
+ */
+"ld1 {v0.D}[0], [%1], %3\n"
+"ld1 {v0.D}[1], [%2], %3\n"
+"ld1 {v1.D}[0], [%1], %3\n"
+"ld1 {v1.D}[1], [%2], %3\n"
+"ld1 {v2.D}[0], [%1], %3\n"
+"ld1 {v2.D}[1], [%2], %3\n"
+  

Re: [Mesa-dev] [PATCH 02/13] nir/spirv: Use unreachable("...") rather than assert(!"...")

[Jordan Justen]

On 2017-08-10 15:02:33, Matt Turner wrote:
> Quiets a number of uninitialized variable warnings in clang.
> ---
>  src/compiler/spirv/spirv_to_nir.c  | 24 
>  src/compiler/spirv/vtn_variables.c | 10 +-
>  2 files changed, 17 insertions(+), 17 deletions(-)
> 
> diff --git a/src/compiler/spirv/spirv_to_nir.c 
> b/src/compiler/spirv/spirv_to_nir.c
> index 7b34dad30c..870dda0314 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -262,7 +262,7 @@ vtn_handle_extension(struct vtn_builder *b, SpvOp opcode,
>if (strcmp((const char *)[2], "GLSL.std.450") == 0) {
>   val->ext_handler = vtn_handle_glsl450_instruction;
>} else {
> - assert(!"Unsupported extension");
> + unreachable("Unsupported extension");
>}
>break;
> }
> @@ -724,7 +724,7 @@ translate_image_format(SpvImageFormat format)
> case SpvImageFormatR16ui:return 0x8234; /* GL_R16UI */
> case SpvImageFormatR8ui: return 0x8232; /* GL_R8UI */
> default:
> -  assert(!"Invalid image format");
> +  unreachable("Invalid image format");
>return 0;
> }
>  }
> @@ -785,7 +785,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
>val->type->type = glsl_matrix_type(glsl_get_base_type(base->type),
>   
> glsl_get_vector_elements(base->type),
>   columns);
> -  assert(!glsl_type_is_error(val->type->type));
> +  unreachable(glsl_type_is_error(val->type->type));

I think we want assert here, right?

>val->type->length = columns;
>val->type->array_element = base;
>val->type->row_major = false;
> @@ -919,7 +919,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
>   else if (dim == GLSL_SAMPLER_DIM_SUBPASS)
>  dim = GLSL_SAMPLER_DIM_SUBPASS_MS;
>   else
> -assert(!"Unsupported multisampled image type");
> +unreachable("Unsupported multisampled image type");
>}
>  
>val->type->image_format = translate_image_format(format);
> @@ -929,12 +929,12 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
>   val->type->type = glsl_sampler_type(dim, is_shadow, is_array,
>   
> glsl_get_base_type(sampled_type));
>} else if (sampled == 2) {
> - assert(!is_shadow);
> + unreachable(is_shadow);

and here ...

>   val->type->sampled = false;
>   val->type->type = glsl_image_type(dim, is_array,
> glsl_get_base_type(sampled_type));
>} else {
> - assert(!"We need to know if the image will be sampled");
> + unreachable("We need to know if the image will be sampled");
>}
>break;
> }
> @@ -1378,7 +1378,7 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
>break;
>  
> case SpvOpConstantSampler:
> -  assert(!"OpConstantSampler requires Kernel Capability");
> +  unreachable("OpConstantSampler requires Kernel Capability");
>break;
>  
> default:
> @@ -2626,7 +2626,7 @@ gl_primitive_from_spv_execution_mode(SpvExecutionMode 
> mode)
> case SpvExecutionModeOutputTriangleStrip:
>return 5; /* GL_TRIANGLE_STRIP */
> default:
> -  assert(!"Invalid primitive type");
> +  unreachable("Invalid primitive type");
>return 4;
> }
>  }
> @@ -2646,7 +2646,7 @@ vertices_in_from_spv_execution_mode(SpvExecutionMode 
> mode)
> case SpvExecutionModeInputTrianglesAdjacency:
>return 6;
> default:
> -  assert(!"Invalid GS input mode");
> +  unreachable("Invalid GS input mode");
>return 0;
> }
>  }
> @@ -2974,7 +2974,7 @@ vtn_handle_execution_mode(struct vtn_builder *b, struct 
> vtn_value *entry_point,
>break;
>  
> case SpvExecutionModeXfb:
> -  assert(!"Unhandled execution mode");
> +  unreachable("Unhandled execution mode");
>break;
>  
> case SpvExecutionModeVecTypeHint:
> @@ -3008,7 +3008,7 @@ vtn_handle_variable_or_type_instruction(struct 
> vtn_builder *b, SpvOp opcode,
> case SpvOpMemberDecorate:
> case SpvOpGroupDecorate:
> case SpvOpGroupMemberDecorate:
> -  assert(!"Invalid opcode types and variables section");
> +  unreachable("Invalid opcode types and variables section");
>break;
>  
> case SpvOpTypeVoid:
> @@ -3348,7 +3348,7 @@ spirv_to_nir(const uint32_t *words, size_t word_count,
> vtn_handle_preamble_instruction);
>  
> if (b->entry_point == NULL) {
> -  assert(!"Entry point not found");
> +  unreachable("Entry point not found");
>ralloc_free(b);
>return NULL;
> }
> diff --git a/src/compiler/spirv/vtn_variables.c 
> b/src/compiler/spirv/vtn_variables.c
> index 4432e72e54..077ad7bb1c 100644
> --- 

Re: [Mesa-dev] [PATCH 00/13] clang warning fixes

[Jordan Justen]

Where's the patchlist on your cover letter? :)

1: Reviewed-by: Jordan Justen 

2: If only changing the string calls:
   Reviewed-by: Jordan Justen 

3-5: Reviewed-by: Jordan Justen 

6-8: Do you have data that removing the inlines doesn't hurt things?
 ;) I actually don't have an opinion on these, so I'll hold off
 to see if anyone else chimes in.

9: Reviewed-by: Jordan Justen 
   (Noting that you are changing an inline function. ;)

10-13: Reviewed-by: Jordan Justen 

On 2017-08-10 15:02:31, Matt Turner wrote:
> Just a simple series cleaning up various bits of code that clang warns about.
> 
> The only real change is to "i965/vec4: Return float from 
> spill_cost_for_type()" which fixes an obvious mistake. The rest just cleans 
> things up like marking internal functions static.
> 
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Re: [Mesa-dev] [PATCH] i965/blorp: Correct type of src_format in call to intel_miptree_texture_aux_usage

[Jordan Justen]

Reviewed-by: Jordan Justen 

On 2017-08-09 15:52:30, Scott D Phillips wrote:
> intel_miptree_texture_aux_usage() takes an isl_format, but we are
> passing a mesa_format. clang warns:
> 
>  brw_blorp.c:305:52: warning: implicit conversion from enumeration
> type 'mesa_format' to different enumeration type
> 'enum isl_format' [-Wenum-conversion]
>intel_miptree_texture_aux_usage(brw, src_mt, src_format);
>~~~  ^~
> 
> Fixes: fc1639e46d ("i965/blorp: Use texture/render_aux_usage for blits")
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 446f507619..d8e48064e3 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -301,8 +301,9 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
>src_format = dst_format = MESA_FORMAT_R_FLOAT32;
> }
>  
> +   enum isl_format src_isl_format = 
> brw_isl_format_for_mesa_format(src_format);
> enum isl_aux_usage src_aux_usage =
> -  intel_miptree_texture_aux_usage(brw, src_mt, src_format);
> +  intel_miptree_texture_aux_usage(brw, src_mt, src_isl_format);
> /* We do format workarounds for some depth formats so we can't reliably
>  * sample with HiZ.  One of these days, we should fix that.
>  */
> -- 
> 2.13.3
> 
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Re: [Mesa-dev] [PATCH] build: Fix up spirv_info.Plo

[Emil Velikov]

Thanks Matt. Patch is:

Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH] st/va: change frame_idx from array to hash table

[Zhang, Boyuan]

Oops, I thought I did it in previous email. Sorry about that. Patches are
Reviewed-and-tested-by: Boyuan Zhang 

Regards,
Boyuan

From: Julien Isorce [mailto:julien.iso...@gmail.com]
Sent: August-10-17 11:37 AM
To: Christian König
Cc: Zhang, Boyuan; Liu, Leo; Andy Furniss; Koenig, Christian; 
mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH] st/va: change frame_idx from array to hash table

Boyuan, gentle ping ?



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[Mesa-dev] [PATCH] egl/dri2: Implement swapInterval fallback in a conformant way (v2)

[Tomasz Figa]

dri2_fallback_swap_interval() currently used to stub out swap interval
support in Android backend does nothing besides returning EGL_FALSE.
This causes at least one known application (Android Snapchat) to fail
due to an unexpected error and my loose interpretation of the EGL 1.5
specification justifies it. Relevant quote below:

The function

EGLBoolean eglSwapInterval(EGLDisplay dpy, EGLint interval);

specifies the minimum number of video frame periods per buffer swap
for the draw surface of the current context, for the current rendering
API. [...]

The parameter interval specifies the minimum number of video frames
that are displayed before a buffer swap will occur. The interval
specified by the function applies to the draw surface bound to the
context that is current on the calling thread. [...] interval is
silently clamped to minimum and maximum implementation dependent
values before being stored; these values are defined by EGLConfig
attributes EGL_MIN_SWAP_INTERVAL and EGL_MAX_SWAP_INTERVAL
respectively.

The default swap interval is 1.

Even though it does not specify the exact behavior if the platform does
not support changing the swap interval, the default assumed state is the
swap interval of 1, which I interpret as a value that eglSwapInterval()
should succeed if called with, even if there is no ability to change the
interval (but there is no change requested). Moreover, since the
behavior is defined to clamp the requested value to minimum and maximum
and at least the default value of 1 must be present in the range, the
implementation might be expected to have a valid range, which in case of
the feature being unsupported, would correspond to {1} and any request
might be expected to be clamped to this value.

Fix this by defaulting dri2_dpy's min_swap_interval, max_swap_interval
and default_swap_interval to 1 in dri2_setup_screen() and let platforms,
which support this functionality set their own values after this
function returns. Thanks to patches merged earlier, we can also remove
the dri2_fallback_swap_interval() completely, as with a singular range
it would not be called anyway.

v2: Remove dri2_fallback_swap_interval() completely thanks to higher
layer already clamping the requested interval and not calling the
driver layer if the clamped value is the same as current.

Signed-off-by: Tomasz Figa 
---
 src/egl/drivers/dri2/egl_dri2.c | 12 
 src/egl/drivers/dri2/egl_dri2_fallbacks.h   |  7 ---
 src/egl/drivers/dri2/platform_android.c |  1 -
 src/egl/drivers/dri2/platform_drm.c |  1 -
 src/egl/drivers/dri2/platform_surfaceless.c |  1 -
 src/egl/drivers/dri2/platform_x11.c |  2 +-
 6 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index f0d1ded408..686dd68d29 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -630,6 +630,18 @@ dri2_setup_screen(_EGLDisplay *disp)
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
unsigned int api_mask;
 
+   /*
+* EGL 1.5 specification defines the default value to 1. Moreover,
+* eglSwapInterval() is required to clamp requested value to the supported
+* range. Since the default value is implicitly assumed to be supported,
+* use it as both minimum and maximum for the platforms that do not allow
+* changing the interval. Platforms, which allow it (e.g. x11, wayland)
+* override these values already.
+*/
+   dri2_dpy->min_swap_interval = 1;
+   dri2_dpy->max_swap_interval = 1;
+   dri2_dpy->default_swap_interval = 1;
+
if (dri2_dpy->image_driver) {
   api_mask = dri2_dpy->image_driver->getAPIMask(dri2_dpy->dri_screen);
} else if (dri2_dpy->dri2) {
diff --git a/src/egl/drivers/dri2/egl_dri2_fallbacks.h 
b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
index 604db881a8..a664677572 100644
--- a/src/egl/drivers/dri2/egl_dri2_fallbacks.h
+++ b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
@@ -55,13 +55,6 @@ dri2_fallback_create_image_khr(_EGLDriver *drv, _EGLDisplay 
*disp,
return NULL;
 }
 
-static inline EGLBoolean
-dri2_fallback_swap_interval(_EGLDriver *drv, _EGLDisplay *dpy,
-_EGLSurface *surf, EGLint interval)
-{
-   return EGL_FALSE;
-}
-
 static inline EGLBoolean
 dri2_fallback_swap_buffers_with_damage(_EGLDriver *drv, _EGLDisplay *dpy,
   _EGLSurface *surf,
diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 50a8248695..c1bae34f2d 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -1118,7 +1118,6 @@ static const struct dri2_egl_display_vtbl 
droid_display_vtbl = {
.create_pbuffer_surface = droid_create_pbuffer_surface,
.destroy_surface = droid_destroy_surface,
.create_image = 

[Mesa-dev] [PATCH libdrm] tests/amdgpu: add uvd encode unit tests

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 tests/amdgpu/Makefile.am |   1 +
 tests/amdgpu/amdgpu_test.c   |   6 +
 tests/amdgpu/amdgpu_test.h   |  15 ++
 tests/amdgpu/frame.h |   2 +-
 tests/amdgpu/uvd_enc_tests.c | 500 
 tests/amdgpu/uve_ib.h| 527 +++
 6 files changed, 1050 insertions(+), 1 deletion(-)
 create mode 100644 tests/amdgpu/uvd_enc_tests.c
 create mode 100644 tests/amdgpu/uve_ib.h

diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index 9e08578..13b3dc8 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -27,4 +27,5 @@ amdgpu_test_SOURCES = \
vce_tests.c \
vce_ib.h \
frame.h \
+   uvd_enc_tests.c \
vcn_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 1d44b09..cd6b826 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -91,6 +91,12 @@ static CU_SuiteInfo suites[] = {
.pCleanupFunc = suite_vcn_tests_clean,
.pTests = vcn_tests,
},
+   {
+   .pName = "UVD ENC Tests",
+   .pInitFunc = suite_uvd_enc_tests_init,
+   .pCleanupFunc = suite_uvd_enc_tests_clean,
+   .pTests = uvd_enc_tests,
+   },
CU_SUITE_INFO_NULL,
 };
 
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index c75a07a..d0b61ba 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -120,6 +120,21 @@ int suite_vcn_tests_clean();
 extern CU_TestInfo vcn_tests[];
 
 /**
+ * Initialize uvd enc test suite
+ */
+int suite_uvd_enc_tests_init();
+
+/**
+ * Deinitialize uvd enc test suite
+ */
+int suite_uvd_enc_tests_clean();
+
+/**
+ * Tests in uvd enc test suite
+ */
+extern CU_TestInfo uvd_enc_tests[];
+
+/**
  * Helper functions
  */
 static inline amdgpu_bo_handle gpu_mem_alloc(
diff --git a/tests/amdgpu/frame.h b/tests/amdgpu/frame.h
index 4c946c2..335401c 100644
--- a/tests/amdgpu/frame.h
+++ b/tests/amdgpu/frame.h
@@ -24,7 +24,7 @@
 #ifndef _frame_h_
 #define _frame_h_
 
-const uint8_t frame[] = {
+static const uint8_t frame[] = {
0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 
0xeb, 0xeb, 0xeb, 0xeb,
0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 
0xd2, 0xd2, 0xd2, 0xd2,
0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 
0xd2, 0xaa, 0xaa, 0xaa,
diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c
new file mode 100644
index 000..6c19f7b
--- /dev/null
+++ b/tests/amdgpu/uvd_enc_tests.c
@@ -0,0 +1,500 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+#include 
+
+#include "CUnit/Basic.h"
+
+#include "util_math.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+#include "frame.h"
+#include "uve_ib.h"
+
+#define IB_SIZE4096
+#define MAX_RESOURCES  16
+
+struct amdgpu_uvd_enc_bo {
+   amdgpu_bo_handle handle;
+   amdgpu_va_handle va_handle;
+   uint64_t addr;
+   uint64_t size;
+   uint8_t *ptr;
+};
+
+struct amdgpu_uvd_enc {
+   unsigned width;
+   unsigned height;
+   struct amdgpu_uvd_enc_bo session;
+   struct amdgpu_uvd_enc_bo vbuf;
+   struct amdgpu_uvd_enc_bo bs;
+   struct amdgpu_uvd_enc_bo fb;
+   struct amdgpu_uvd_enc_bo cpb;
+};
+
+static amdgpu_device_handle device_handle;
+static uint32_t major_version;
+static uint32_t minor_version;
+static uint32_t family_id;
+
+static amdgpu_context_handle context_handle;
+static amdgpu_bo_handle ib_handle;
+static amdgpu_va_handle ib_va_handle;
+static uint64_t ib_mc_address;
+static uint32_t 

[Mesa-dev] [PATCH] configure: remove trailing "-a" in swr architecture test

[Tim Rowley]

Fixes "configure: line 27326: test: argument expected"

CC: mesa-sta...@lists.freedesktop.org
---
 configure.ac | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index 5b12dd8..316e6a8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2545,7 +2545,7 @@ if test -n "$with_gallium_drivers"; then
 if test "x$HAVE_SWR_AVX" != xyes -a \
 "x$HAVE_SWR_AVX2" != xyes -a \
 "x$HAVE_SWR_KNL" != xyes -a \
-"x$HAVE_SWR_SKX" != xyes -a; then
+"x$HAVE_SWR_SKX" != xyes; then
AC_MSG_ERROR([swr enabled but no swr architectures selected])
 fi
 
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] configure: remove trailing "-a" in swr architecture test

[Matt Turner]

Reviewed-by: Matt Turner 
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Re: [Mesa-dev] [PATCH 09/25] i965: Reorder brw_reg_type enum values

[Matt Turner]

On Tue, Aug 8, 2017 at 4:21 PM, Scott D Phillips
 wrote:
> Matt Turner  writes:
>> These vaguely corresponded to the hardware encodings, but that is purely
>> historical at this point. Reorder them so we stop making things "almost
>> work" when mixing enums.
>>
>> The ordering has been closen so that no enum value is the same as a
>> compatible hardware encoding.
>> ---
>>  src/intel/compiler/brw_eu.c  |  1 -
>>  src/intel/compiler/brw_eu_emit.c |  6 --
>>  src/intel/compiler/brw_fs.cpp|  1 +
>>  src/intel/compiler/brw_reg.h | 32 ++--
>>  src/intel/compiler/brw_vec4.cpp  |  3 ++-
>>  5 files changed, 17 insertions(+), 26 deletions(-)
>>
>> diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
>> index 0ef52e219c..700a1badd4 100644
>> --- a/src/intel/compiler/brw_eu.c
>> +++ b/src/intel/compiler/brw_eu.c
>> @@ -62,7 +62,6 @@ brw_reg_type_letters(unsigned type)
>>[BRW_REGISTER_TYPE_UQ] = "UQ",
>>[BRW_REGISTER_TYPE_Q]  = "Q",
>> };
>> -   assert(type <= BRW_REGISTER_TYPE_Q);
>> return names[type];
>>  }
>>
>> diff --git a/src/intel/compiler/brw_eu_emit.c 
>> b/src/intel/compiler/brw_eu_emit.c
>> index 6673e0741a..b59fc33a54 100644
>> --- a/src/intel/compiler/brw_eu_emit.c
>> +++ b/src/intel/compiler/brw_eu_emit.c
>> @@ -112,7 +112,6 @@ brw_reg_type_to_hw_type(const struct gen_device_info 
>> *devinfo,
>>};
>>assert(type < ARRAY_SIZE(imm_hw_types));
>>assert(imm_hw_types[type] != -1);
>> -  assert(devinfo->gen >= 8 || type < BRW_REGISTER_TYPE_DF);
>>return imm_hw_types[type];
>> } else {
>>/* Non-immediate registers */
>> @@ -134,8 +133,6 @@ brw_reg_type_to_hw_type(const struct gen_device_info 
>> *devinfo,
>>};
>>assert(type < ARRAY_SIZE(hw_types));
>>assert(hw_types[type] != -1);
>> -  assert(devinfo->gen >= 7 || type < BRW_REGISTER_TYPE_DF);
>> -  assert(devinfo->gen >= 8 || type < BRW_REGISTER_TYPE_Q);
>
> It might be good to keep these asserts around, but phrased as something
> like assert(gen_has_reg_type(gen, file, type)) or something.

I thought about this some. I think the removal is more a feature than a bug.

brw_reg_type_letters is called by dump_instructions().
brw_hw_reg_type_to_size() is called by the disassembler and the
validator. In both of these cases, we really don't want to hit an
assert when we're just trying to generate some textual representation
of the instruction. If it has some bogus type, we want to see it (and
the rest of the instructions) rather than failing an assertion.

brw_reg_type_to_hw_type() is called by functions writing the
instruction word, so it's a different case. My goal has been to move
the unorganized assertions (see brw_MUL for example) into the
structure of brw_eu_validate.c. So I think I'm okay with removing this
ad hoc validation.

>>return hw_types[type];
>> }
>>  }
>> @@ -184,9 +181,6 @@ brw_hw_reg_type_to_size(const struct gen_device_info 
>> *devinfo,
>>   [GEN8_HW_REG_NON_IMM_TYPE_HF] = 2,
>>};
>>assert(type < ARRAY_SIZE(hw_sizes));
>> -  assert(devinfo->gen >= 7 ||
>> - (type < GEN7_HW_REG_NON_IMM_TYPE_DF || type == 
>> BRW_HW_REG_TYPE_F));
>> -  assert(devinfo->gen >= 8 || type <= BRW_HW_REG_TYPE_F);
>>return hw_sizes[type];
>> }
>>  }
>> diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
>> index fdc30d450c..0ea4c4f1cc 100644
>> --- a/src/intel/compiler/brw_fs.cpp
>> +++ b/src/intel/compiler/brw_fs.cpp
>> @@ -403,6 +403,7 @@ void
>>  fs_reg::init()
>>  {
>> memset(this, 0, sizeof(*this));
>> +   type = BRW_REGISTER_TYPE_UD;
>> stride = 1;
>>  }
>>
>> diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
>> index 17a51fbd65..48e6fd7b7d 100644
>> --- a/src/intel/compiler/brw_reg.h
>> +++ b/src/intel/compiler/brw_reg.h
>> @@ -203,29 +203,25 @@ brw_mask_for_swizzle(unsigned swz)
>>  }
>>
>>  enum PACKED brw_reg_type {
>
> And maybe add a comment here like this part of the commit message:
>
>  * The ordering has been chosen so that no enum value is the same as a
>  * compatible hardware encoding.
>
> So it's clear that matching some hardware encoding is an anti-goal.

Sure, that's a good idea. Thanks!
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Re: [Mesa-dev] [PATCH 0/5] GL_OES_required_internalformat

[Eric Anholt]

Tapani Pälli  writes:

> On 06/22/2017 02:08 AM, Eric Anholt wrote:
>> Tapani Pälli  writes:
>> 
>>> On 06/14/2017 01:12 AM, Eric Anholt wrote:
 Tapani Pälli  writes:

> On 06/12/2017 09:52 AM, Tapani Pälli wrote:
>>
>> On 05/18/2017 09:39 PM, Eric Anholt wrote:
>>> Eric Anholt  writes:
>>>
 This series came out of fixing dEQP failures on vc4's GLES2 context.
 Mesa was allowing RGB565 textures, which is only valid with
 GL_OES_required_internalformat.  Rather than disable RGB565, I decided
 the extension was easy enough to support.

 I've sent one piglit test for renderbuffer sizing, and dEQP has tests
 for whether enums get accepted for TexImage.

 There's a functional question in patch #2, see the comment there, and
 there's a question of whether the extension should be dummy_true in
 patch #5.

 branch: https://github.com/anholt/mesa/commits/required-internalformat
>>> I would still love review on this series.
>>>
>> Earlier I took a brief look at series and run through our CI, there were
>> many failing tests but t seems I forgot to reply/report .. I'll run it
>> again and let you know what's the result.
>>
> '36 failures' (many likely duplicates of some same issue), these ones ..
>
> ES3-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.bdwm64
> ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pbo.bdwm64
> ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pixelstore.hswm64
> ES3-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.sklm64
> ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pbo.sklm64
> ES3-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.bdwm64
> ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pixelstore.bdwm64
> ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels.hswm64
> ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pixelstore.sklm64
> ES3-CTS.functional.fbo.completeness.renderable.texture.color0.rgb10.hswm64
> ES3-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.hswm64
> ES3-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.hswm64
> ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pbo.hswm64
> ES3-CTS.functional.fbo.completeness.renderable.texture.color0.rgb10.bdwm64
> ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels.bdwm64
> ES3-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.sklm64
> ES3-CTS.functional.fbo.completeness.renderable.texture.color0.rgb10.sklm64
> ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels.sklm64
> ES2-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.bdwm64
> ES2-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.sklm64
> ES2-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.bdwm64
> ES2-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.hswm64
> ES2-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.hswm64
> ES2-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.sklm64
>
> piglit.spec.oes_texture_float.oes_texture_float half.g965m64
> piglit.spec.oes_texture_float.oes_texture_float.g965m64
> piglit.spec.oes_texture_float.oes_texture_float half linear.g965m64
> piglit.spec.oes_texture_float.oes_texture_float linear.g965m64
> piglit.spec.oes_texture_float.oes_texture_float half.g45m64
> piglit.spec.oes_texture_float.oes_texture_float half linear.g45m64
> piglit.spec.oes_texture_float.oes_texture_float linear.g45m64
> piglit.spec.oes_texture_float.oes_texture_float.g45m64
> piglit.spec.oes_texture_float.oes_texture_float.ilkm64
> piglit.spec.oes_texture_float.oes_texture_float half linear.ilkm64
> piglit.spec.oes_texture_float.oes_texture_float half.ilkm64
> piglit.spec.oes_texture_float.oes_texture_float linear.ilkm64
>
> Are you able to reproduce/run these tests on some machine?
 I have a SKL desktop, so I reproduced the GLES2 rgb10 failure and fixed
 it, and I think I've fixed the pre-snb failures in piglit.  New branch
 up at https://github.com/anholt/mesa/commits/required-internalformat
 which I'll piglit now.
>>>
>>>
>>> OK, seems the packed_pixels ones are still failing. I'll try to debug
>>> this a bit to see what's going on.
>> 
>> Have you had a chance to look at this at all?  Or could you give me a
>> command line for reproducing failure?  I've gone through my VK-GL-CTS
>> tree and DEQP trees trying various test runners with various manglings
>> of the names, with no luck.
>> 
>
> Sorry I've forgotten this thread .. the 'CTS' ones are from Khronos 
> 'OpenGL & OpenGL ES CTS' (available in gitlab) which is run by Jenkins, 
> are you able to access that suite?

If you mean the 

Re: [Mesa-dev] [PATCH] egl/dri2: Implement swapInterval fallback in a conformant way (v2)

[Chad Versace]

On Thu 10 Aug 2017, Tomasz Figa wrote:
> dri2_fallback_swap_interval() currently used to stub out swap interval
> support in Android backend does nothing besides returning EGL_FALSE.
> This causes at least one known application (Android Snapchat) to fail
> due to an unexpected error and my loose interpretation of the EGL 1.5
> specification justifies it. Relevant quote below:

...

> Signed-off-by: Tomasz Figa 
> ---
>  src/egl/drivers/dri2/egl_dri2.c | 12 
>  src/egl/drivers/dri2/egl_dri2_fallbacks.h   |  7 ---
>  src/egl/drivers/dri2/platform_android.c |  1 -
>  src/egl/drivers/dri2/platform_drm.c |  1 -
>  src/egl/drivers/dri2/platform_surfaceless.c |  1 -
>  src/egl/drivers/dri2/platform_x11.c |  2 +-
>  6 files changed, 13 insertions(+), 11 deletions(-)

Reviewed-by: Chad Versace 

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Re: [Mesa-dev] [Mesa-stable] [PATCH] configure: remove trailing "-a" in swr architecture test

[Chuck Atkins]

I hit this a few weeks ago when I was adding the cray flags to swr and
patched it manually but forgot to push it upstream.  Thanks for the fix.

Tested-by: Chuck Atkins 

- Chuck

On Thu, Aug 10, 2017 at 2:04 PM, Matt Turner  wrote:

> Reviewed-by: Matt Turner 
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>
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Re: [Mesa-dev] [PATCH] egl/dri2: Implement swapInterval fallback in a conformant way

[Tapani Pälli]

I agree to the interpretation, it is stated that EGL_FALSE happens 'on 
failure' and there are 2 error cases specified for eglSwapInterval. It 
seems right to assume those are the only cases where it can fail (no 
current context or surface bound).


Reviewed-by: Tapani Pälli 

On 08/10/2017 08:43 AM, Tomasz Figa wrote:

dri2_fallback_swap_interval() currently used to stub out swap interval
support in Android backend does nothing besides returning EGL_FALSE.
This causes at least one known application (Android Snapchat) to fail
due to an unexpected error and my loose interpretation of the EGL 1.5
specification justifies it. Relevant quote below:

 The function

 EGLBoolean eglSwapInterval(EGLDisplay dpy, EGLint interval);

 specifies the minimum number of video frame periods per buffer swap
 for the draw surface of the current context, for the current rendering
 API. [...]

 The parameter interval specifies the minimum number of video frames
 that are displayed before a buffer swap will occur. The interval
 specified by the function applies to the draw surface bound to the
 context that is current on the calling thread. [...] interval is
 silently clamped to minimum and maximum implementation dependent
 values before being stored; these values are defined by EGLConfig
 attributes EGL_MIN_SWAP_INTERVAL and EGL_MAX_SWAP_INTERVAL
 respectively.

 The default swap interval is 1.

Even though it does not specify the exact behavior if the platform does
not support changing the swap interval, the default assumed state is the
swap interval of 1, which I interpret as a value that eglSwapInterval()
should succeed if called with, even if there is no ability to change the
interval (but there is no change requested). Moreover, since the
behavior is defined to clamp the requested value to minimum and maximum
and at least the default value of 1 must be present in the range, the
implementation might be expected to have a valid range, which in case of
the feature being unsupported, would correspond to {1} and any request
might be expected to be clamped to this value.

This is further confirmed by the code in _eglSwapInterval() in
src/egl/main/eglsurface.c, which is the default fallback implementation
for EGL drivers not implementing its own. The problem with it is that
the DRI2 EGL driver provides its own implementation that calls into
platform backends, so we cannot just simply fall back to it.

Signed-off-by: Tomasz Figa 
---
  src/egl/drivers/dri2/egl_dri2.c   | 12 
  src/egl/drivers/dri2/egl_dri2_fallbacks.h |  9 -
  src/egl/drivers/dri2/platform_x11.c   |  1 +
  3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index f0d1ded408..686dd68d29 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -630,6 +630,18 @@ dri2_setup_screen(_EGLDisplay *disp)
 struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
 unsigned int api_mask;
  
+   /*

+* EGL 1.5 specification defines the default value to 1. Moreover,
+* eglSwapInterval() is required to clamp requested value to the supported
+* range. Since the default value is implicitly assumed to be supported,
+* use it as both minimum and maximum for the platforms that do not allow
+* changing the interval. Platforms, which allow it (e.g. x11, wayland)
+* override these values already.
+*/
+   dri2_dpy->min_swap_interval = 1;
+   dri2_dpy->max_swap_interval = 1;
+   dri2_dpy->default_swap_interval = 1;
+
 if (dri2_dpy->image_driver) {
api_mask = dri2_dpy->image_driver->getAPIMask(dri2_dpy->dri_screen);
 } else if (dri2_dpy->dri2) {
diff --git a/src/egl/drivers/dri2/egl_dri2_fallbacks.h 
b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
index 604db881a8..c70c686f8d 100644
--- a/src/egl/drivers/dri2/egl_dri2_fallbacks.h
+++ b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
@@ -59,7 +59,14 @@ static inline EGLBoolean
  dri2_fallback_swap_interval(_EGLDriver *drv, _EGLDisplay *dpy,
  _EGLSurface *surf, EGLint interval)
  {
-   return EGL_FALSE;
+   if (interval > surf->Config->MaxSwapInterval)
+  interval = surf->Config->MaxSwapInterval;
+   else if (interval < surf->Config->MinSwapInterval)
+  interval = surf->Config->MinSwapInterval;
+
+   surf->SwapInterval = interval;
+
+   return EGL_TRUE;
  }
  
  static inline EGLBoolean

diff --git a/src/egl/drivers/dri2/platform_x11.c 
b/src/egl/drivers/dri2/platform_x11.c
index 4610ec579f..97cdd09078 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -1283,6 +1283,7 @@ dri2_x11_setup_swap_interval(struct dri2_egl_display 
*dri2_dpy)
  */
 dri2_dpy->min_swap_interval = 0;
 dri2_dpy->max_swap_interval = 0;
+   dri2_dpy->default_swap_interval = 0;
  
 if 

Re: [Mesa-dev] [PATCH v5 2/2] i965: Queue the buffer with a sync fence for Android OS

[Tomasz Figa]

Hi Yogesh,

On Thu, Aug 10, 2017 at 5:25 PM, Marathe, Yogesh
 wrote:
> Hi Tomasz,
>
>> -Original Message-
>> From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On Behalf
>> Of Tomasz Figa
>> Sent: Tuesday, August 8, 2017 7:45 AM
>> To: Marathe, Yogesh 
>> >> > >> Changing the topic, the patch doesn't seem to change the
>> >> > >> implementation of swapBuffers to stop doing a flush on the
>> >> > >> buffer, which defeats the purpose of the fence, as the it is
>> >> > >> likely already signaled at the time it is passed to queueBuffer. 
>> >> > >> Shouldn't
>> we fix this?
>> >> > >>
>> >> > >
>> >> > > I have been wondering about it all the while, when I had prints
>> >> > > in
>> >> > > Fence::getSignalTime() to check finfo->status from consumer side
>> >> > > during initial revisions, I always found it to be signaled!
>> >> > >
>> >> > > Can we really remove that flush in swapBuffers? In that case I
>> >> > > believe the consumer _must_ wait on fence before really accessing
>> >> > > it, so that would trigger a change in buffer consumer / application!
>> >> >
>> >> > The consumer must _always_ wait on the acquire fence if it's a
>> >> > valid FD, as this is how the ANativeWindow interface is defined.
>> >> > You can see Mesa already does it in droid_dequeue_buffer(). If you
>> >> > find a consumer that is not doing so, it's a bug in the consumer.
>> >> > There is no compatibility concern here, as it's strictly regulated by 
>> >> > Android
>> specifications.
>> >>
>> >> I checked this, yes, BufferConsumer waits on fence provided its valid.
>> >
>> > Hi Tomasz,
>> >
>> > Is it ok to move that 'flush' removal change to separate commit? I
>> > would opt for that. This gflush removal change is going to trigger
>> > additional tests, while this one fixes the issue for now and has list
>> > of review comments done. If this is fine, I'll push v6 for this.
>>
>> I'm okay with either.
>>
>
> I found GLConsumer aosp has glFlush() is already, it means we had two flush 
> calls in
> the path, one in swapBuffers and other in libgui on consumer.
>
> I went ahead and removed  dri2_flush_drawable_for_swapbuffer. Functionally,
> things seem to be ok. I assume this will be valid only for android with valid 
> fence changes
> and not for other platforms. Is this right expectation? Diff below.
>
> diff --git a/src/egl/drivers/dri2/platform_android.c 
> b/src/egl/drivers/dri2/platform_android.c
> index 8bca753..80da021 100644
> --- a/src/egl/drivers/dri2/platform_android.c
> +++ b/src/egl/drivers/dri2/platform_android.c
> @@ -706,7 +706,6 @@ droid_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, 
> _EGLSurface *draw)
> if (dri2_surf->back)
>dri2_surf->back->age = 1;
>
> -   dri2_flush_drawable_for_swapbuffers(disp, draw);
>
> /* dri2_surf->buffer can be null even when no error has occured. For
>  * example, if the user has called no GL rendering commands since the
>
> If this is only change, I don’t think we need separate patch here. Please 
> correct me if I'm wrong.

I think I have been mistaken in what
dri2_flush_drawable_for_swabuffers() does. We need to keep it there as
it makes the DRI2 driver issue operations finalizing the buffer, e.g.
remaining drawing or a multisample resolve if necessary. However it
doesn't do any synchronous wait on the queued operations, so there is
no performance loss.

Best regards,
Tomasz
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Re: [Mesa-dev] [PATCH] egl/dri2: Implement swapInterval fallback in a conformant way (v2)

[Emil Velikov]

On 10 August 2017 at 14:59, Tomasz Figa  wrote:
> dri2_fallback_swap_interval() currently used to stub out swap interval
> support in Android backend does nothing besides returning EGL_FALSE.
> This causes at least one known application (Android Snapchat) to fail
> due to an unexpected error and my loose interpretation of the EGL 1.5
> specification justifies it. Relevant quote below:
>
> The function
>
> EGLBoolean eglSwapInterval(EGLDisplay dpy, EGLint interval);
>
> specifies the minimum number of video frame periods per buffer swap
> for the draw surface of the current context, for the current rendering
> API. [...]
>
> The parameter interval specifies the minimum number of video frames
> that are displayed before a buffer swap will occur. The interval
> specified by the function applies to the draw surface bound to the
> context that is current on the calling thread. [...] interval is
> silently clamped to minimum and maximum implementation dependent
> values before being stored; these values are defined by EGLConfig
> attributes EGL_MIN_SWAP_INTERVAL and EGL_MAX_SWAP_INTERVAL
> respectively.
>
> The default swap interval is 1.
>
> Even though it does not specify the exact behavior if the platform does
> not support changing the swap interval, the default assumed state is the
> swap interval of 1, which I interpret as a value that eglSwapInterval()
> should succeed if called with, even if there is no ability to change the
> interval (but there is no change requested). Moreover, since the
> behavior is defined to clamp the requested value to minimum and maximum
> and at least the default value of 1 must be present in the range, the
> implementation might be expected to have a valid range, which in case of
> the feature being unsupported, would correspond to {1} and any request
> might be expected to be clamped to this value.
>
> Fix this by defaulting dri2_dpy's min_swap_interval, max_swap_interval
> and default_swap_interval to 1 in dri2_setup_screen() and let platforms,
> which support this functionality set their own values after this
> function returns. Thanks to patches merged earlier, we can also remove
> the dri2_fallback_swap_interval() completely, as with a singular range
> it would not be called anyway.
>
> v2: Remove dri2_fallback_swap_interval() completely thanks to higher
> layer already clamping the requested interval and not calling the
> driver layer if the clamped value is the same as current.
>
Not every driver is EGL 1.5, although the 1.4 spec has exact same text.

Reviewed-by: Emil Velikov 

We could have this in stable, but will need a clamp like v1 since
Eric's rework did not land there.
Gents, how do you feel on the topic?

-Emil
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Re: [Mesa-dev] [PATCH 3/7] util: Fix build on old glibc.

[Matt Turner]

On 08/08, Eric Anholt wrote:

We need to link librt for u_thread.h's clock_gettime() call.

Fixes: b822d9dd67b5 ("gallium/util: move u_queue.{c,h} to src/util")
---


Reviewed-by: Matt Turner 


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Re: [Mesa-dev] [PATCH v2 5/8] glsl: pass mem_ctx to constant_expression_value(...) and friends

[Kenneth Graunke]

On Thursday, August 10, 2017 3:42:29 AM PDT Timothy Arceri wrote:
> The main motivation for this is that threaded compilation can fall
> over if we were to allocate IR inside constant_expression_value()
> when calling it on a builtin. This is because builtins are shared
> across the whole OpenGL context.
> 
> f81ede469910d worked around the problem by cloning the entire
> builtin before constant_expression_value() could be called on
> it. However cloning the whole function each time we referenced
> it lead to a significant reduction in the GLSL IR compiler
> performance. This change along with the following patch
> helps fix that performance regression.
> 
> Other advantages are that we reduce the number of calls to
> ralloc_parent(), and for loop unrolling we free constants after
> they are used rather than leaving them hanging around.
> 
> Cc: Kenneth Graunke 
> Cc: Lionel Landwerlin 

Looks good to me!  Thanks Tim!

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 6/8] glsl: stop cloning builtin fuctions _mesa_glsl_find_builtin_function()

[Kenneth Graunke]

On Tuesday, August 8, 2017 8:34:07 PM PDT Timothy Arceri wrote:
> The cloning was introduced in f81ede469910d to fixed a problem with
> shaders including IR that was owned by builtins.
> 
> However the approach of cloning the whole function each time we
> reference a builtin lead to a significant reduction in the GLSL
> IR compilers performance.
> 
> The previous patch fixes the ownership problem in a more precise
> way. So we can now remove this cloning.
> 
> Testing on a Ryzan 7 1800X shows a ~15% decreases in compiling the
> Deus Ex: Mankind Divided shaders on radeonsi (which take 5min+ on
> some machines). Looking just at the GLSL IR compiler the speed up
> is ~40%.
> 
> Cc: Kenneth Graunke 
> Cc: Lionel Landwerlin 
> 
> Tested-by: Dieter Nützel 

With 5v2, this is:

Reviewed-by: Kenneth Graunke 

Thanks!


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Re: [Mesa-dev] [PATCH] isl: Validate row pitch of stencil surfaces.

[Ilia Mirkin]

On Wed, Aug 9, 2017 at 4:09 PM, Kenneth Graunke  wrote:
> Also, silence an obnoxious finishme that started occurring for all
> GL applications which use stencil after the i965 ISL conversion.

Without commenting on the correctness of the patch, either this or
something like it should really end up in 17.2.

Cheers,

  -ilia
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Re: [Mesa-dev] [PATCH] isl: Validate row pitch of stencil surfaces.

[Jason Ekstrand]

On August 10, 2017 12:45:43 PM Ilia Mirkin  wrote:


On Wed, Aug 9, 2017 at 4:09 PM, Kenneth Graunke  wrote:

Also, silence an obnoxious finishme that started occurring for all
GL applications which use stencil after the i965 ISL conversion.


Without commenting on the correctness of the patch, either this or
something like it should really end up in 17.2.

Cheers,


Agreed


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Re: [Mesa-dev] [PATCH 4/7 v2] configure.ac: Introduce HAVE_ARM_ASM/HAVE_AARCH64_ASM and the -D flags.

[Rob Herring]

On Thu, Aug 10, 2017 at 5:43 PM, Eric Anholt  wrote:
> I've been trying to get away without these conditionals in vc4's NEON
> code, but it meant compiling extra unused code on x86, and build failing
> on ARMv6.
>
> v2: Use the _arm/_arm64 flags to simplify detection (suggested by Rob),
> but hide the _arm version under ARCH_ARM_HAVE_NEON to keep from trying
> to build this stuff for armv5te.
> ---
>  Android.common.mk |  4 
>  configure.ac  | 24 
>  2 files changed, 28 insertions(+)

For Android:

Tested-by: Rob Herring 
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Re: [Mesa-dev] [PATCH 6/7 v3] broadcom/vc4: Port NEON-code to ARM64

[Rob Herring]

On Thu, Aug 10, 2017 at 5:43 PM, Eric Anholt  wrote:
> From: Jonas Pfeil 
>
> Changed all register and instruction names, works the same.
>
> v2: Rebase on build system changes (by anholt)
> v3: Fix build on clang (by anholt, reported by Rob)
>
> Signed-off-by: Jonas Pfeil 
> ---
>  src/gallium/drivers/vc4/vc4_tiling_lt.c | 84 
> +
>  1 file changed, 84 insertions(+)

For Android:

Tested-by: Rob Herring 
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Re: [Mesa-dev] [PATCH 5/7 v2] broadcom/vc4: Build the vc4_tiling_lt_neon.c with -mfpu=neon on ARM.

[Rob Herring]

On Thu, Aug 10, 2017 at 5:43 PM, Eric Anholt  wrote:
> If you don't pass this, the compiler refuses to compile the assembly for
> pre-v7 CPUs.  This also keeps us from building identical, non-NEON code on
> aarch64 and x86.
>
> Fixes: a373f77662c5 ("vc4: Use a wrapper file to set VC4_BUILD_NEON instead 
> of CFLAGS.")
>
> v2: Fix Android build by just appending NEON_C_SOURCES when
> ARCH_ARM_HAVE_NEON.
> ---
>  src/gallium/drivers/vc4/Android.mk   |  4 
>  src/gallium/drivers/vc4/Makefile.am  |  7 +++
>  src/gallium/drivers/vc4/Makefile.sources |  3 ++-
>  src/gallium/drivers/vc4/vc4_tiling.h | 17 +++--
>  4 files changed, 24 insertions(+), 7 deletions(-)

For Android:

Tested-by: Rob Herring 
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Re: [Mesa-dev] [PATCH] build: Fix up spirv_info.Plo

[Rhys Kidd]

On 10 August 2017 at 12:46, Emil Velikov  wrote:

> Thanks Matt. Patch is:
>
> Reviewed-by: Emil Velikov 
>

It's a little late, but gets my:

Tested-by: Rhys Kidd 

Thanks Matt for fixing the out-of-tree builds.


>
> -Emil
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Re: [Mesa-dev] [PATCH 2/3] gallium/radeon: only pass shader-specific debug flags to the disk shader cache

[Timothy Arceri]

Reviewed-by: Timothy Arceri 
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Re: [Mesa-dev] [PATCH 3/3] gallium/radeon: pass LLVM processor to the disk shader cache

[Timothy Arceri]

On 11/08/17 05:57, Marek Olšák wrote:

From: Marek Olšák 

---
  src/gallium/drivers/radeon/r600_pipe_common.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 95458d2e..0038c9a 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -878,21 +878,21 @@ static void r600_disk_cache_create(struct 
r600_common_screen *rscreen)
  #endif
if (res != -1) {
/* These flags affect shader compilation. */
uint64_t shader_debug_flags =
rscreen->debug_flags &
(DBG_FS_CORRECT_DERIVS_AFTER_KILL |
 DBG_SI_SCHED |
 DBG_UNSAFE_MATH);
  
  			rscreen->disk_shader_cache =

-   disk_cache_create(r600_get_family_name(rscreen),
+   
disk_cache_create(r600_get_llvm_processor_name(rscreen->family),


I take it this will always by more fine grained than any compilation 
options for the GLSL/TGSI stages?


Otherwise maybe we should store both like we do for the Mesa/LLVM build 
timestamps.




  timestamp_str,
  shader_debug_flags);
free(timestamp_str);
}
}
  }
  
  static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)

  {
struct r600_common_screen *rscreen = (struct 
r600_common_screen*)pscreen;


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Re: [Mesa-dev] [PATCH] ac: fail shader compilation if libelf is replaced by an incompatible version

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 08/09/2017 10:34 PM, Marek Olšák wrote:

From: Marek Olšák 

UE4Editor has this issue.

This commit prevents hangs (release build) or assertion failures (debug
build).

Cc: 17.2 
---
  src/amd/common/ac_binary.c  | 12 ++--
  src/amd/common/ac_binary.h  |  2 +-
  src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c |  5 -
  3 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/src/amd/common/ac_binary.c b/src/amd/common/ac_binary.c
index 618b5cf..1bf52c7 100644
--- a/src/amd/common/ac_binary.c
+++ b/src/amd/common/ac_binary.c
@@ -102,59 +102,66 @@ static void parse_relocs(Elf *elf, Elf_Data *relocs, 
Elf_Data *symbols,
gelf_getrel(relocs, i, );
gelf_getsym(symbols, GELF_R_SYM(rel.r_info), );
symbol_name = elf_strptr(elf, symbol_sh_link, symbol.st_name);
  
  		reloc->offset = rel.r_offset;

strncpy(reloc->name, symbol_name, sizeof(reloc->name)-1);
reloc->name[sizeof(reloc->name)-1] = 0;
}
  }
  
-void ac_elf_read(const char *elf_data, unsigned elf_size,

+bool ac_elf_read(const char *elf_data, unsigned elf_size,
 struct ac_shader_binary *binary)
  {
char *elf_buffer;
Elf *elf;
Elf_Scn *section = NULL;
Elf_Data *symbols = NULL, *relocs = NULL;
size_t section_str_index;
unsigned symbol_sh_link = 0;
+   bool success = true;
  
  	/* One of the libelf implementations

 * (http://www.mr511.de/software/english.htm) requires calling
 * elf_version() before elf_memory().
 */
elf_version(EV_CURRENT);
elf_buffer = MALLOC(elf_size);
memcpy(elf_buffer, elf_data, elf_size);
  
  	elf = elf_memory(elf_buffer, elf_size);
  
  	elf_getshdrstrndx(elf, _str_index);
  
  	while ((section = elf_nextscn(elf, section))) {

const char *name;
Elf_Data *section_data = NULL;
GElf_Shdr section_header;
if (gelf_getshdr(section, _header) != _header) {
fprintf(stderr, "Failed to read ELF section header\n");
-   return;
+   success = false;
+   break;
}
name = elf_strptr(elf, section_str_index, 
section_header.sh_name);
if (!strcmp(name, ".text")) {
section_data = elf_getdata(section, section_data);
binary->code_size = section_data->d_size;
binary->code = MALLOC(binary->code_size * 
sizeof(unsigned char));
memcpy(binary->code, section_data->d_buf, 
binary->code_size);
} else if (!strcmp(name, ".AMDGPU.config")) {
section_data = elf_getdata(section, section_data);
binary->config_size = section_data->d_size;
+   if (!binary->config_size) {
+   fprintf(stderr, ".AMDGPU.config is empty!\n");
+   success = false;
+   break;
+   }
binary->config = MALLOC(binary->config_size * 
sizeof(unsigned char));
memcpy(binary->config, section_data->d_buf, 
binary->config_size);
} else if (!strcmp(name, ".AMDGPU.disasm")) {
/* Always read disassembly if it's available. */
section_data = elf_getdata(section, section_data);
binary->disasm_string = strndup(section_data->d_buf,
section_data->d_size);
} else if (!strncmp(name, ".rodata", 7)) {
section_data = elf_getdata(section, section_data);
binary->rodata_size = section_data->d_size;
@@ -179,20 +186,21 @@ void ac_elf_read(const char *elf_data, unsigned elf_size,
FREE(elf_buffer);
  
  	/* Cache the config size per symbol */

if (binary->global_symbol_count) {
binary->config_size_per_symbol =
binary->config_size / binary->global_symbol_count;
} else {
binary->global_symbol_count = 1;
binary->config_size_per_symbol = binary->config_size;
}
+   return success;
  }
  
  const unsigned char *ac_shader_binary_config_start(

const struct ac_shader_binary *binary,
uint64_t symbol_offset)
  {
unsigned i;
for (i = 0; i < binary->global_symbol_count; ++i) {
if (binary->global_symbol_offsets[i] == symbol_offset) {
unsigned offset = i * binary->config_size_per_symbol;
diff --git a/src/amd/common/ac_binary.h b/src/amd/common/ac_binary.h

[Mesa-dev] [Bug 101334] AMD SI cards: Some vulkan apps freeze the system

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101334

--- Comment #50 from Marko  ---
Hi everyone,

I've tested DOOM yesterday for maybe half an hour and you can color me
impressed.
The FPS is in the 50's range for High/ultra, no glitches, stuttering or
artifacts/texture corruption. No freezes either. The performance is on par with
Windows, give or take. 

Dota2 also works like a charm with comparable, solid framerates (50+ on best
quality).

Thanks for fixing this guys!

Marko

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[Mesa-dev] [PATCH v2 5/8] glsl: pass mem_ctx to constant_expression_value(...) and friends

[Timothy Arceri]

The main motivation for this is that threaded compilation can fall
over if we were to allocate IR inside constant_expression_value()
when calling it on a builtin. This is because builtins are shared
across the whole OpenGL context.

f81ede469910d worked around the problem by cloning the entire
builtin before constant_expression_value() could be called on
it. However cloning the whole function each time we referenced
it lead to a significant reduction in the GLSL IR compiler
performance. This change along with the following patch
helps fix that performance regression.

Other advantages are that we reduce the number of calls to
ralloc_parent(), and for loop unrolling we free constants after
they are used rather than leaving them hanging around.

Cc: Kenneth Graunke 
Cc: Lionel Landwerlin 
---
 src/compiler/glsl/ast_array_index.cpp|   2 +-
 src/compiler/glsl/ast_function.cpp   |  17 ++--
 src/compiler/glsl/ast_to_hir.cpp |  15 ++-
 src/compiler/glsl/ast_type.cpp   |   7 +-
 src/compiler/glsl/ir.h   |  37 +---
 src/compiler/glsl/ir_constant_expression.cpp | 114 +++
 src/compiler/glsl/linker.cpp |   2 +-
 src/compiler/glsl/loop_controls.cpp  |   6 +-
 src/compiler/glsl/loop_unroll.cpp|   2 +-
 src/compiler/glsl/lower_buffer_access.cpp|   2 +-
 src/compiler/glsl/lower_distance.cpp |   3 +-
 src/compiler/glsl/lower_tess_level.cpp   |   3 +-
 src/compiler/glsl/lower_vec_index_to_swizzle.cpp |   7 +-
 src/compiler/glsl/lower_vector_derefs.cpp|   3 +-
 src/compiler/glsl/lower_vector_insert.cpp|   3 +-
 src/compiler/glsl/opt_algebraic.cpp  |   9 +-
 src/compiler/glsl/opt_constant_folding.cpp   |   5 +-
 src/compiler/glsl/opt_constant_propagation.cpp   |   3 +-
 src/compiler/glsl/opt_constant_variable.cpp  |   2 +-
 src/compiler/glsl/opt_if_simplification.cpp  |   3 +-
 src/mesa/program/ir_to_mesa.cpp  |   6 +-
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp   |   7 +-
 22 files changed, 168 insertions(+), 90 deletions(-)

diff --git a/src/compiler/glsl/ast_array_index.cpp 
b/src/compiler/glsl/ast_array_index.cpp
index efddbed6ea..3b30f6858e 100644
--- a/src/compiler/glsl/ast_array_index.cpp
+++ b/src/compiler/glsl/ast_array_index.cpp
@@ -160,21 +160,21 @@ _mesa_ast_array_index_to_hir(void *mem_ctx,
   } else if (!idx->type->is_scalar()) {
  _mesa_glsl_error(& idx_loc, state, "array index must be scalar");
   }
}
 
/* If the array index is a constant expression and the array has a
 * declared size, ensure that the access is in-bounds.  If the array
 * index is not a constant expression, ensure that the array has a
 * declared size.
 */
-   ir_constant *const const_index = idx->constant_expression_value();
+   ir_constant *const const_index = idx->constant_expression_value(mem_ctx);
if (const_index != NULL && idx->type->is_integer()) {
   const int idx = const_index->value.i[0];
   const char *type_name = "error";
   unsigned bound = 0;
 
   /* From page 24 (page 30 of the PDF) of the GLSL 1.50 spec:
*
*"It is illegal to declare an array with a size, and then
*later (in the same shader) index the same array with an
*integral constant expression greater than or equal to the
diff --git a/src/compiler/glsl/ast_function.cpp 
b/src/compiler/glsl/ast_function.cpp
index f7e90fba5b..b121ab9210 100644
--- a/src/compiler/glsl/ast_function.cpp
+++ b/src/compiler/glsl/ast_function.cpp
@@ -30,32 +30,35 @@
 #include "builtin_functions.h"
 
 static ir_rvalue *
 convert_component(ir_rvalue *src, const glsl_type *desired_type);
 
 static unsigned
 process_parameters(exec_list *instructions, exec_list *actual_parameters,
exec_list *parameters,
struct _mesa_glsl_parse_state *state)
 {
+   void *mem_ctx = state;
unsigned count = 0;
 
foreach_list_typed(ast_node, ast, link, parameters) {
   /* We need to process the parameters first in order to know if we can
* raise or not a unitialized warning. Calling set_is_lhs silence the
* warning for now. Raising the warning or not will be checked at
* verify_parameter_modes.
*/
   ast->set_is_lhs(true);
   ir_rvalue *result = ast->hir(instructions, state);
 
-  ir_constant *const constant = result->constant_expression_value();
+  ir_constant *const constant =
+ result->constant_expression_value(mem_ctx);
+
   if (constant != NULL)
  result = constant;
 
   actual_parameters->push_tail(result);
   count++;
}
 
return count;
 }
 
@@ -511,21 +514,22 @@ generate_call(exec_list *instructions, 
ir_function_signature *sig,
 * - a built-in function call whose arguments 

Re: [Mesa-dev] [PATCH] egl/dri2: Implement swapInterval fallback in a conformant way

[Eric Engestrom]

On 10 August 2017 06:43:45 BST, Tomasz Figa  wrote:
> dri2_fallback_swap_interval() currently used to stub out swap interval
> support in Android backend does nothing besides returning EGL_FALSE.
> This causes at least one known application (Android Snapchat) to fail
> due to an unexpected error and my loose interpretation of the EGL 1.5
> specification justifies it. Relevant quote below:
> 
> The function
> 
> EGLBoolean eglSwapInterval(EGLDisplay dpy, EGLint interval);
> 
>specifies the minimum number of video frame periods per buffer swap
> for the draw surface of the current context, for the current rendering
> API. [...]
> 
>The parameter interval specifies the minimum number of video frames
> that are displayed before a buffer swap will occur. The interval
> specified by the function applies to the draw surface bound to the
> context that is current on the calling thread. [...] interval is
> silently clamped to minimum and maximum implementation dependent
> values before being stored; these values are defined by EGLConfig
> attributes EGL_MIN_SWAP_INTERVAL and EGL_MAX_SWAP_INTERVAL
> respectively.
> 
> The default swap interval is 1.
> 
> Even though it does not specify the exact behavior if the platform
> does
> not support changing the swap interval, the default assumed state is
> the
> swap interval of 1, which I interpret as a value that
> eglSwapInterval()
> should succeed if called with, even if there is no ability to change
> the
> interval (but there is no change requested). Moreover, since the
> behavior is defined to clamp the requested value to minimum and
> maximum
> and at least the default value of 1 must be present in the range, the
> implementation might be expected to have a valid range, which in case
> of
> the feature being unsupported, would correspond to {1} and any request
> might be expected to be clamped to this value.
> 
> This is further confirmed by the code in _eglSwapInterval() in
> src/egl/main/eglsurface.c, which is the default fallback
> implementation
> for EGL drivers not implementing its own. The problem with it is that
> the DRI2 EGL driver provides its own implementation that calls into
> platform backends, so we cannot just simply fall back to it.
> 
> Signed-off-by: Tomasz Figa 
> ---
>  src/egl/drivers/dri2/egl_dri2.c   | 12 
>  src/egl/drivers/dri2/egl_dri2_fallbacks.h |  9 -
>  src/egl/drivers/dri2/platform_x11.c   |  1 +
>  3 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/src/egl/drivers/dri2/egl_dri2.c
> b/src/egl/drivers/dri2/egl_dri2.c
> index f0d1ded408..686dd68d29 100644
> --- a/src/egl/drivers/dri2/egl_dri2.c
> +++ b/src/egl/drivers/dri2/egl_dri2.c
> @@ -630,6 +630,18 @@ dri2_setup_screen(_EGLDisplay *disp)
> struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
> unsigned int api_mask;
>  
> +   /*
> +* EGL 1.5 specification defines the default value to 1. Moreover,
> +* eglSwapInterval() is required to clamp requested value to the
> supported
> +* range. Since the default value is implicitly assumed to be
> supported,
> +* use it as both minimum and maximum for the platforms that do
> not allow
> +* changing the interval. Platforms, which allow it (e.g. x11,
> wayland)
> +* override these values already.
> +*/
> +   dri2_dpy->min_swap_interval = 1;
> +   dri2_dpy->max_swap_interval = 1;
> +   dri2_dpy->default_swap_interval = 1;
> +
> if (dri2_dpy->image_driver) {
>   api_mask = dri2_dpy->image_driver->getAPIMask(dri2_dpy->dri_screen);
> } else if (dri2_dpy->dri2) {
> diff --git a/src/egl/drivers/dri2/egl_dri2_fallbacks.h
> b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
> index 604db881a8..c70c686f8d 100644
> --- a/src/egl/drivers/dri2/egl_dri2_fallbacks.h
> +++ b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
> @@ -59,7 +59,14 @@ static inline EGLBoolean
>  dri2_fallback_swap_interval(_EGLDriver *drv, _EGLDisplay *dpy,
>  _EGLSurface *surf, EGLint interval)
>  {
> -   return EGL_FALSE;
> +   if (interval > surf->Config->MaxSwapInterval)
> +  interval = surf->Config->MaxSwapInterval;
> +   else if (interval < surf->Config->MinSwapInterval)
> +  interval = surf->Config->MinSwapInterval;
> +
> +   surf->SwapInterval = interval;
> +
> +   return EGL_TRUE;

Agreed with the interpretation, but if memory serves (on my phone on a plane 
right now) I already took care of clamping and setting the value one layer 
above, so the only change needed is s/EGL_FALSE/EGL_TRUE/ in this function.

Look for a commit of mine (`git log --author=engestrom -- src/egl/`) about 3 
weeks ago.

Cheers,
  Eric

>  }
>  
>  static inline EGLBoolean
> diff --git a/src/egl/drivers/dri2/platform_x11.c
> b/src/egl/drivers/dri2/platform_x11.c
> index 4610ec579f..97cdd09078 100644
> --- a/src/egl/drivers/dri2/platform_x11.c
> +++ 

Re: [Mesa-dev] [PATCH] egl/dri2: Implement swapInterval fallback in a conformant way

[Tomasz Figa]

On Thu, Aug 10, 2017 at 9:40 PM, Eric Engestrom  wrote:
> On 10 August 2017 06:43:45 BST, Tomasz Figa  wrote:
>> dri2_fallback_swap_interval() currently used to stub out swap interval
>> support in Android backend does nothing besides returning EGL_FALSE.
>> This causes at least one known application (Android Snapchat) to fail
>> due to an unexpected error and my loose interpretation of the EGL 1.5
>> specification justifies it. Relevant quote below:
>>
>> The function
>>
>> EGLBoolean eglSwapInterval(EGLDisplay dpy, EGLint interval);
>>
>>specifies the minimum number of video frame periods per buffer swap
>> for the draw surface of the current context, for the current rendering
>> API. [...]
>>
>>The parameter interval specifies the minimum number of video frames
>> that are displayed before a buffer swap will occur. The interval
>> specified by the function applies to the draw surface bound to the
>> context that is current on the calling thread. [...] interval is
>> silently clamped to minimum and maximum implementation dependent
>> values before being stored; these values are defined by EGLConfig
>> attributes EGL_MIN_SWAP_INTERVAL and EGL_MAX_SWAP_INTERVAL
>> respectively.
>>
>> The default swap interval is 1.
>>
>> Even though it does not specify the exact behavior if the platform
>> does
>> not support changing the swap interval, the default assumed state is
>> the
>> swap interval of 1, which I interpret as a value that
>> eglSwapInterval()
>> should succeed if called with, even if there is no ability to change
>> the
>> interval (but there is no change requested). Moreover, since the
>> behavior is defined to clamp the requested value to minimum and
>> maximum
>> and at least the default value of 1 must be present in the range, the
>> implementation might be expected to have a valid range, which in case
>> of
>> the feature being unsupported, would correspond to {1} and any request
>> might be expected to be clamped to this value.
>>
>> This is further confirmed by the code in _eglSwapInterval() in
>> src/egl/main/eglsurface.c, which is the default fallback
>> implementation
>> for EGL drivers not implementing its own. The problem with it is that
>> the DRI2 EGL driver provides its own implementation that calls into
>> platform backends, so we cannot just simply fall back to it.
>>
>> Signed-off-by: Tomasz Figa 
>> ---
>>  src/egl/drivers/dri2/egl_dri2.c   | 12 
>>  src/egl/drivers/dri2/egl_dri2_fallbacks.h |  9 -
>>  src/egl/drivers/dri2/platform_x11.c   |  1 +
>>  3 files changed, 21 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/egl/drivers/dri2/egl_dri2.c
>> b/src/egl/drivers/dri2/egl_dri2.c
>> index f0d1ded408..686dd68d29 100644
>> --- a/src/egl/drivers/dri2/egl_dri2.c
>> +++ b/src/egl/drivers/dri2/egl_dri2.c
>> @@ -630,6 +630,18 @@ dri2_setup_screen(_EGLDisplay *disp)
>> struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
>> unsigned int api_mask;
>>
>> +   /*
>> +* EGL 1.5 specification defines the default value to 1. Moreover,
>> +* eglSwapInterval() is required to clamp requested value to the
>> supported
>> +* range. Since the default value is implicitly assumed to be
>> supported,
>> +* use it as both minimum and maximum for the platforms that do
>> not allow
>> +* changing the interval. Platforms, which allow it (e.g. x11,
>> wayland)
>> +* override these values already.
>> +*/
>> +   dri2_dpy->min_swap_interval = 1;
>> +   dri2_dpy->max_swap_interval = 1;
>> +   dri2_dpy->default_swap_interval = 1;
>> +
>> if (dri2_dpy->image_driver) {
>>   api_mask = dri2_dpy->image_driver->getAPIMask(dri2_dpy->dri_screen);
>> } else if (dri2_dpy->dri2) {
>> diff --git a/src/egl/drivers/dri2/egl_dri2_fallbacks.h
>> b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
>> index 604db881a8..c70c686f8d 100644
>> --- a/src/egl/drivers/dri2/egl_dri2_fallbacks.h
>> +++ b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
>> @@ -59,7 +59,14 @@ static inline EGLBoolean
>>  dri2_fallback_swap_interval(_EGLDriver *drv, _EGLDisplay *dpy,
>>  _EGLSurface *surf, EGLint interval)
>>  {
>> -   return EGL_FALSE;
>> +   if (interval > surf->Config->MaxSwapInterval)
>> +  interval = surf->Config->MaxSwapInterval;
>> +   else if (interval < surf->Config->MinSwapInterval)
>> +  interval = surf->Config->MinSwapInterval;
>> +
>> +   surf->SwapInterval = interval;
>> +
>> +   return EGL_TRUE;
>
> Agreed with the interpretation, but if memory serves (on my phone on a plane 
> right now) I already took care of clamping and setting the value one layer 
> above, so the only change needed is s/EGL_FALSE/EGL_TRUE/ in this function.
>
> Look for a commit of mine (`git log --author=engestrom -- src/egl/`) about 3 
> weeks ago.

Good catch, thanks for pointing out. I should have checked upstream
first. Looks like 

Re: [Mesa-dev] [PATCH] egl/dri2: Implement swapInterval fallback in a conformant way (v2)

[Tapani Pälli]

Reviewed-by: Tapani Pälli 

On 08/10/2017 04:59 PM, Tomasz Figa wrote:

dri2_fallback_swap_interval() currently used to stub out swap interval
support in Android backend does nothing besides returning EGL_FALSE.
This causes at least one known application (Android Snapchat) to fail
due to an unexpected error and my loose interpretation of the EGL 1.5
specification justifies it. Relevant quote below:

 The function

 EGLBoolean eglSwapInterval(EGLDisplay dpy, EGLint interval);

 specifies the minimum number of video frame periods per buffer swap
 for the draw surface of the current context, for the current rendering
 API. [...]

 The parameter interval specifies the minimum number of video frames
 that are displayed before a buffer swap will occur. The interval
 specified by the function applies to the draw surface bound to the
 context that is current on the calling thread. [...] interval is
 silently clamped to minimum and maximum implementation dependent
 values before being stored; these values are defined by EGLConfig
 attributes EGL_MIN_SWAP_INTERVAL and EGL_MAX_SWAP_INTERVAL
 respectively.

 The default swap interval is 1.

Even though it does not specify the exact behavior if the platform does
not support changing the swap interval, the default assumed state is the
swap interval of 1, which I interpret as a value that eglSwapInterval()
should succeed if called with, even if there is no ability to change the
interval (but there is no change requested). Moreover, since the
behavior is defined to clamp the requested value to minimum and maximum
and at least the default value of 1 must be present in the range, the
implementation might be expected to have a valid range, which in case of
the feature being unsupported, would correspond to {1} and any request
might be expected to be clamped to this value.

Fix this by defaulting dri2_dpy's min_swap_interval, max_swap_interval
and default_swap_interval to 1 in dri2_setup_screen() and let platforms,
which support this functionality set their own values after this
function returns. Thanks to patches merged earlier, we can also remove
the dri2_fallback_swap_interval() completely, as with a singular range
it would not be called anyway.

v2: Remove dri2_fallback_swap_interval() completely thanks to higher
 layer already clamping the requested interval and not calling the
 driver layer if the clamped value is the same as current.

Signed-off-by: Tomasz Figa 
---
  src/egl/drivers/dri2/egl_dri2.c | 12 
  src/egl/drivers/dri2/egl_dri2_fallbacks.h   |  7 ---
  src/egl/drivers/dri2/platform_android.c |  1 -
  src/egl/drivers/dri2/platform_drm.c |  1 -
  src/egl/drivers/dri2/platform_surfaceless.c |  1 -
  src/egl/drivers/dri2/platform_x11.c |  2 +-
  6 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index f0d1ded408..686dd68d29 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -630,6 +630,18 @@ dri2_setup_screen(_EGLDisplay *disp)
 struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
 unsigned int api_mask;
  
+   /*

+* EGL 1.5 specification defines the default value to 1. Moreover,
+* eglSwapInterval() is required to clamp requested value to the supported
+* range. Since the default value is implicitly assumed to be supported,
+* use it as both minimum and maximum for the platforms that do not allow
+* changing the interval. Platforms, which allow it (e.g. x11, wayland)
+* override these values already.
+*/
+   dri2_dpy->min_swap_interval = 1;
+   dri2_dpy->max_swap_interval = 1;
+   dri2_dpy->default_swap_interval = 1;
+
 if (dri2_dpy->image_driver) {
api_mask = dri2_dpy->image_driver->getAPIMask(dri2_dpy->dri_screen);
 } else if (dri2_dpy->dri2) {
diff --git a/src/egl/drivers/dri2/egl_dri2_fallbacks.h 
b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
index 604db881a8..a664677572 100644
--- a/src/egl/drivers/dri2/egl_dri2_fallbacks.h
+++ b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
@@ -55,13 +55,6 @@ dri2_fallback_create_image_khr(_EGLDriver *drv, _EGLDisplay 
*disp,
 return NULL;
  }
  
-static inline EGLBoolean

-dri2_fallback_swap_interval(_EGLDriver *drv, _EGLDisplay *dpy,
-_EGLSurface *surf, EGLint interval)
-{
-   return EGL_FALSE;
-}
-
  static inline EGLBoolean
  dri2_fallback_swap_buffers_with_damage(_EGLDriver *drv, _EGLDisplay *dpy,
_EGLSurface *surf,
diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 50a8248695..c1bae34f2d 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -1118,7 +1118,6 @@ static const struct dri2_egl_display_vtbl 
droid_display_vtbl = {
  

Re: [Mesa-dev] [PATCH] egl/dri2: Implement swapInterval fallback in a conformant way (v2)

[Tomasz Figa]

On Fri, Aug 11, 2017 at 2:29 AM, Emil Velikov  wrote:
> On 10 August 2017 at 14:59, Tomasz Figa  wrote:
>> dri2_fallback_swap_interval() currently used to stub out swap interval
>> support in Android backend does nothing besides returning EGL_FALSE.
>> This causes at least one known application (Android Snapchat) to fail
>> due to an unexpected error and my loose interpretation of the EGL 1.5
>> specification justifies it. Relevant quote below:
>>
>> The function
>>
>> EGLBoolean eglSwapInterval(EGLDisplay dpy, EGLint interval);
>>
>> specifies the minimum number of video frame periods per buffer swap
>> for the draw surface of the current context, for the current rendering
>> API. [...]
>>
>> The parameter interval specifies the minimum number of video frames
>> that are displayed before a buffer swap will occur. The interval
>> specified by the function applies to the draw surface bound to the
>> context that is current on the calling thread. [...] interval is
>> silently clamped to minimum and maximum implementation dependent
>> values before being stored; these values are defined by EGLConfig
>> attributes EGL_MIN_SWAP_INTERVAL and EGL_MAX_SWAP_INTERVAL
>> respectively.
>>
>> The default swap interval is 1.
>>
>> Even though it does not specify the exact behavior if the platform does
>> not support changing the swap interval, the default assumed state is the
>> swap interval of 1, which I interpret as a value that eglSwapInterval()
>> should succeed if called with, even if there is no ability to change the
>> interval (but there is no change requested). Moreover, since the
>> behavior is defined to clamp the requested value to minimum and maximum
>> and at least the default value of 1 must be present in the range, the
>> implementation might be expected to have a valid range, which in case of
>> the feature being unsupported, would correspond to {1} and any request
>> might be expected to be clamped to this value.
>>
>> Fix this by defaulting dri2_dpy's min_swap_interval, max_swap_interval
>> and default_swap_interval to 1 in dri2_setup_screen() and let platforms,
>> which support this functionality set their own values after this
>> function returns. Thanks to patches merged earlier, we can also remove
>> the dri2_fallback_swap_interval() completely, as with a singular range
>> it would not be called anyway.
>>
>> v2: Remove dri2_fallback_swap_interval() completely thanks to higher
>> layer already clamping the requested interval and not calling the
>> driver layer if the clamped value is the same as current.
>>
> Not every driver is EGL 1.5, although the 1.4 spec has exact same text.
>
> Reviewed-by: Emil Velikov 
>
> We could have this in stable, but will need a clamp like v1 since
> Eric's rework did not land there.
> Gents, how do you feel on the topic?

FWIW, Eric's patches applied cleanly onto our chromium branch, which
was based on something not very far away from what 17.2 branched at.
If for some reasons we prefer to avoid further cherry picks, we can go
with my v1 for stable, which doesn't depend on them.

Best regards,
Tomasz
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/2] st/omx_tizonia: add --enable-omx-tizonia flag and build files

[Gurkirpal Singh]

Coexist with --enable-omx so they can be built independently
Detect tizonia package config file
Generate libomxtiz_mesa.so and install it to libtizcore.pc::pluginsdir
Only compile empty source (target.c) for now.

GSoC Project link: 
https://summerofcode.withgoogle.com/projects/#4737166321123328

Signed-off-by: Gurkirpal Singh 
---
 configure.ac| 30 +++
 src/gallium/Makefile.am |  4 ++
 src/gallium/targets/omx-tizonia/Makefile.am | 77 +
 src/gallium/targets/omx-tizonia/omx.sym | 11 +
 src/gallium/targets/omx-tizonia/target.c|  2 +
 5 files changed, 124 insertions(+)
 create mode 100644 src/gallium/targets/omx-tizonia/Makefile.am
 create mode 100644 src/gallium/targets/omx-tizonia/omx.sym
 create mode 100644 src/gallium/targets/omx-tizonia/target.c

diff --git a/configure.ac b/configure.ac
index f131788..1bd6635 100644
--- a/configure.ac
+++ b/configure.ac
@@ -85,6 +85,7 @@ dnl Versions for external dependencies
 DRI2PROTO_REQUIRED=2.8
 GLPROTO_REQUIRED=1.4.14
 LIBOMXIL_BELLAGIO_REQUIRED=0.0
+LIBOMXIL_TIZONIA_REQUIRED=0.8.0
 LIBVA_REQUIRED=0.38.0
 VDPAU_REQUIRED=1.1
 WAYLAND_REQUIRED=1.11
@@ -1219,6 +1220,11 @@ AC_ARG_ENABLE([omx],
  [enable OpenMAX library @<:@default=disabled@:>@])],
[enable_omx="$enableval"],
[enable_omx=no])
+AC_ARG_ENABLE([omx-tizonia],
+   [AS_HELP_STRING([--enable-omx-tizonia],
+ [enable OpenMAX Tizonia library @<:@default=disabled@:>@])],
+   [enable_omx_tizonia="$enableval"],
+   [enable_omx_tizonia=no])
 AC_ARG_ENABLE([va],
[AS_HELP_STRING([--enable-va],
  [enable va library @<:@default=auto@:>@])],
@@ -1270,6 +1276,7 @@ if test "x$enable_opengl" = xno -a \
 "x$enable_xvmc" = xno -a \
 "x$enable_vdpau" = xno -a \
 "x$enable_omx" = xno -a \
+"x$enable_omx_tizonia" = xno -a \
 "x$enable_va" = xno -a \
 "x$enable_opencl" = xno; then
 AC_MSG_ERROR([at least one API should be enabled])
@@ -2116,6 +2123,10 @@ if test -n "$with_gallium_drivers" -a 
"x$with_gallium_drivers" != xswrast; then
 PKG_CHECK_EXISTS([libomxil-bellagio >= $LIBOMXIL_BELLAGIO_REQUIRED], 
[enable_omx=yes], [enable_omx=no])
 fi
 
+if test "x$enable_omx_tizonia -a "x$have_omx_platform" = xyes" = xauto; 
then
+   PKG_CHECK_EXISTS([libtizonia >= $LIBOMXIL_TIZONIA_REQUIRED], 
[enable_omx_tizonia=yes], [enable_omx_tizonia=no])
+fi
+
 if test "x$enable_va" = xauto -a "x$have_va_platform" = xyes; then
 PKG_CHECK_EXISTS([libva >= $LIBVA_REQUIRED], [enable_va=yes], 
[enable_va=no])
 fi
@@ -2167,6 +2178,14 @@ if test "x$enable_omx" = xyes; then
 fi
 AM_CONDITIONAL(HAVE_ST_OMX, test "x$enable_omx" = xyes)
 
+if test "x$enable_omx_tizonia" = xyes; then
+PKG_CHECK_MODULES([OMX_TIZONIA], [libtizonia >= 
$LIBOMXIL_TIZONIA_REQUIRED])
+PKG_CHECK_MODULES([OMX_TIZILHEADERS], [tizilheaders >= 
$LIBOMXIL_TIZONIA_REQUIRED])
+PKG_CHECK_MODULES([OMX_TIZPLATFORM], [libtizplatform >= 
$LIBOMXIL_TIZONIA_REQUIRED])
+gallium_st="$gallium_st omx_tizonia"
+fi
+AM_CONDITIONAL(HAVE_ST_OMX_TIZONIA, test "x$enable_omx_tizonia" = xyes)
+
 if test "x$enable_va" = xyes; then
 if test "x$have_va_platform" != xyes; then
 AC_MSG_ERROR([VA requires at least one of the x11 drm or wayland 
platforms])
@@ -2337,6 +2356,15 @@ AC_ARG_WITH([omx-libdir],
   $PKG_CONFIG --define-variable=libdir=\$libdir 
--variable=pluginsdir libomxil-bellagio`])
 AC_SUBST([OMX_LIB_INSTALL_DIR])
 
+dnl Directory for OMX_TIZONIA libs
+
+AC_ARG_WITH([omx-tizonia-libdir],
+[AS_HELP_STRING([--with-omx-tizonia-libdir=DIR],
+[directory for the OMX_TIZONIA libraries])],
+[OMX_TIZONIA_LIB_INSTALL_DIR="$withval"],
+[OMX_TIZONIA_LIB_INSTALL_DIR=`$PKG_CONFIG 
--define-variable=libdir=\$libdir --variable=pluginsdir libtizcore`])
+AC_SUBST([OMX_TIZONIA_LIB_INSTALL_DIR])
+
 dnl Directory for VA libs
 
 AC_ARG_WITH([va-libdir],
@@ -2835,6 +2863,7 @@ AC_CONFIG_FILES([Makefile
  src/gallium/state_trackers/glx/xlib/Makefile
  src/gallium/state_trackers/nine/Makefile
  src/gallium/state_trackers/omx/Makefile
+ src/gallium/state_trackers/omx_tizonia/Makefile
  src/gallium/state_trackers/osmesa/Makefile
  src/gallium/state_trackers/va/Makefile
  src/gallium/state_trackers/vdpau/Makefile
@@ -2845,6 +2874,7 @@ AC_CONFIG_FILES([Makefile
  src/gallium/targets/dri/Makefile
  src/gallium/targets/libgl-xlib/Makefile
  src/gallium/targets/omx/Makefile
+ src/gallium/targets/omx-tizonia/Makefile
  src/gallium/targets/opencl/Makefile
  src/gallium/targets/opencl/mesa.icd
  src/gallium/targets/osmesa/Makefile
diff --git a/src/gallium/Makefile.am b/src/gallium/Makefile.am
index 

[Mesa-dev] [PATCH 2/2] st/omx_tizonia: Add AVC decoder

[Gurkirpal Singh]

Signed-off-by: Gurkirpal Singh 
---
 src/gallium/state_trackers/omx_tizonia/Makefile.am |   35 +
 .../state_trackers/omx_tizonia/Makefile.sources|9 +
 .../state_trackers/omx_tizonia/entrypoint.c|  152 ++
 .../state_trackers/omx_tizonia/entrypoint.h|   35 +
 src/gallium/state_trackers/omx_tizonia/h264d.c |  173 ++
 src/gallium/state_trackers/omx_tizonia/h264d.h |   54 +
 src/gallium/state_trackers/omx_tizonia/h264dprc.c  | 1713 
 src/gallium/state_trackers/omx_tizonia/h264dprc.h  |   31 +
 .../state_trackers/omx_tizonia/h264dprc_decls.h|  108 ++
 src/gallium/state_trackers/omx_tizonia/names.h |   30 +
 10 files changed, 2340 insertions(+)
 create mode 100644 src/gallium/state_trackers/omx_tizonia/Makefile.am
 create mode 100644 src/gallium/state_trackers/omx_tizonia/Makefile.sources
 create mode 100644 src/gallium/state_trackers/omx_tizonia/entrypoint.c
 create mode 100644 src/gallium/state_trackers/omx_tizonia/entrypoint.h
 create mode 100644 src/gallium/state_trackers/omx_tizonia/h264d.c
 create mode 100644 src/gallium/state_trackers/omx_tizonia/h264d.h
 create mode 100644 src/gallium/state_trackers/omx_tizonia/h264dprc.c
 create mode 100644 src/gallium/state_trackers/omx_tizonia/h264dprc.h
 create mode 100644 src/gallium/state_trackers/omx_tizonia/h264dprc_decls.h
 create mode 100644 src/gallium/state_trackers/omx_tizonia/names.h

diff --git a/src/gallium/state_trackers/omx_tizonia/Makefile.am 
b/src/gallium/state_trackers/omx_tizonia/Makefile.am
new file mode 100644
index 000..932929b
--- /dev/null
+++ b/src/gallium/state_trackers/omx_tizonia/Makefile.am
@@ -0,0 +1,35 @@
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT.  IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+# HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+include Makefile.sources
+include $(top_srcdir)/src/gallium/Automake.inc
+
+AM_CFLAGS = \
+   $(GALLIUM_CFLAGS) \
+   $(VISIBILITY_CFLAGS) \
+   $(VL_CFLAGS) \
+   $(XCB_DRI3_CFLAGS) \
+   $(OMX_TIZONIA_CFLAGS) \
+   $(OMX_TIZILHEADERS_CFLAGS) \
+   $(OMX_TIZPLATFORM_CFLAGS)
+
+noinst_LTLIBRARIES = libomxtiztracker.la
+
+libomxtiztracker_la_SOURCES = $(C_SOURCES)
diff --git a/src/gallium/state_trackers/omx_tizonia/Makefile.sources 
b/src/gallium/state_trackers/omx_tizonia/Makefile.sources
new file mode 100644
index 000..7bb08b9
--- /dev/null
+++ b/src/gallium/state_trackers/omx_tizonia/Makefile.sources
@@ -0,0 +1,9 @@
+C_SOURCES := \
+   entrypoint.c \
+   entrypoint.h \
+   h264d.c \
+   h264d.h \
+   h264dprc.c \
+   h264dprc.h \
+   names.h \
+   h264prc_decls.h
diff --git a/src/gallium/state_trackers/omx_tizonia/entrypoint.c 
b/src/gallium/state_trackers/omx_tizonia/entrypoint.c
new file mode 100644
index 000..95094cf
--- /dev/null
+++ b/src/gallium/state_trackers/omx_tizonia/entrypoint.c
@@ -0,0 +1,152 @@
+/**
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR 

[Mesa-dev] [PATCH] radeonsi: don't enable surf index on shareable images.

[Dave Airlie]

From: Dave Airlie 

This fixes the SteamVR menus, which were broken by this feature.

Signed-off-by: Dave Airlie 
---
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 99e4d77..2cbff58 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -97,12 +97,15 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
 * always use consecutive surface indices when FMASK is allocated between
 * them.
 */
-   if (flags & RADEON_SURF_FMASK)
-  config.info.surf_index = >surf_index_fmask;
-   else if (!(flags & RADEON_SURF_Z_OR_SBUFFER))
-  config.info.surf_index = >surf_index_color;
-   else
-  config.info.surf_index = NULL;
+   if (!(flags & RADEON_SURF_SHAREABLE)) {
+ if (flags & RADEON_SURF_FMASK)
+   config.info.surf_index = >surf_index_fmask;
+ else if (!(flags & RADEON_SURF_Z_OR_SBUFFER))
+   config.info.surf_index = >surf_index_color;
+ else
+   config.info.surf_index = NULL;
+   } else
+ config.info.surf_index = NULL;
 
return ac_compute_surface(ws->addrlib, >info, , mode, surf);
 }
-- 
2.9.4

___
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Re: [Mesa-dev] [PATCH 0/5] GL_OES_required_internalformat

[Tapani Pälli]

On 08/10/2017 10:04 PM, Eric Anholt wrote:

Tapani Pälli  writes:


On 06/22/2017 02:08 AM, Eric Anholt wrote:

Tapani Pälli  writes:


On 06/14/2017 01:12 AM, Eric Anholt wrote:

Tapani Pälli  writes:


On 06/12/2017 09:52 AM, Tapani Pälli wrote:


On 05/18/2017 09:39 PM, Eric Anholt wrote:

Eric Anholt  writes:


This series came out of fixing dEQP failures on vc4's GLES2 context.
Mesa was allowing RGB565 textures, which is only valid with
GL_OES_required_internalformat.  Rather than disable RGB565, I decided
the extension was easy enough to support.

I've sent one piglit test for renderbuffer sizing, and dEQP has tests
for whether enums get accepted for TexImage.

There's a functional question in patch #2, see the comment there, and
there's a question of whether the extension should be dummy_true in
patch #5.

branch: https://github.com/anholt/mesa/commits/required-internalformat

I would still love review on this series.


Earlier I took a brief look at series and run through our CI, there were
many failing tests but t seems I forgot to reply/report .. I'll run it
again and let you know what's the result.


'36 failures' (many likely duplicates of some same issue), these ones ..

ES3-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.bdwm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pbo.bdwm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pixelstore.hswm64
ES3-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.sklm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pbo.sklm64
ES3-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.bdwm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pixelstore.bdwm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels.hswm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pixelstore.sklm64
ES3-CTS.functional.fbo.completeness.renderable.texture.color0.rgb10.hswm64
ES3-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.hswm64
ES3-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.hswm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels_pbo.hswm64
ES3-CTS.functional.fbo.completeness.renderable.texture.color0.rgb10.bdwm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels.bdwm64
ES3-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.sklm64
ES3-CTS.functional.fbo.completeness.renderable.texture.color0.rgb10.sklm64
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels.sklm64
ES2-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.bdwm64
ES2-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.sklm64
ES2-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.bdwm64
ES2-CTS.functional.fbo.completeness.renderable.texture.depth.rgb10.hswm64
ES2-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.hswm64
ES2-CTS.functional.fbo.completeness.renderable.texture.stencil.rgb10.sklm64

piglit.spec.oes_texture_float.oes_texture_float half.g965m64
piglit.spec.oes_texture_float.oes_texture_float.g965m64
piglit.spec.oes_texture_float.oes_texture_float half linear.g965m64
piglit.spec.oes_texture_float.oes_texture_float linear.g965m64
piglit.spec.oes_texture_float.oes_texture_float half.g45m64
piglit.spec.oes_texture_float.oes_texture_float half linear.g45m64
piglit.spec.oes_texture_float.oes_texture_float linear.g45m64
piglit.spec.oes_texture_float.oes_texture_float.g45m64
piglit.spec.oes_texture_float.oes_texture_float.ilkm64
piglit.spec.oes_texture_float.oes_texture_float half linear.ilkm64
piglit.spec.oes_texture_float.oes_texture_float half.ilkm64
piglit.spec.oes_texture_float.oes_texture_float linear.ilkm64

Are you able to reproduce/run these tests on some machine?

I have a SKL desktop, so I reproduced the GLES2 rgb10 failure and fixed
it, and I think I've fixed the pre-snb failures in piglit.  New branch
up at https://github.com/anholt/mesa/commits/required-internalformat
which I'll piglit now.



OK, seems the packed_pixels ones are still failing. I'll try to debug
this a bit to see what's going on.


Have you had a chance to look at this at all?  Or could you give me a
command line for reproducing failure?  I've gone through my VK-GL-CTS
tree and DEQP trees trying various test runners with various manglings
of the names, with no luck.



Sorry I've forgotten this thread .. the 'CTS' ones are from Khronos
'OpenGL & OpenGL ES CTS' (available in gitlab) which is run by Jenkins,
are you able to access that suite?


If you mean the "OpenGL & OpenGL ES Conformance Test Suite" in gitlab
(g...@gitlab.khronos.org:opengl/cts.git), that repository says:

"This project is moved to maintenance mode.

Use VK-GL-CTS for development, bug fixes"

Are you sure that's the repository you're using?



Yes, I believe that is still the repository being used with some 
patches/fixes applied on top and that repository is a mixture of dEQP 
and old CTS. I can see that 'vk-gl-cts' does not have