Re: [PATCH v2] target/sh4: Fix TB_FLAG_UNALIGN

2022-10-03 Thread Yoshinori Sato
On Mon, 03 Oct 2022 02:23:51 +0900,
Richard Henderson wrote:
> 
> Ping, or should I create a PR myself?
> 
> r~

Sorry.
I can't work this week, so please submit a PR.

> 
> On 9/1/22 07:15, Yoshinori Sato wrote:
> > On Thu, 01 Sep 2022 19:15:09 +0900,
> > Richard Henderson wrote:
> >> 
> >> The value previously chosen overlaps GUSA_MASK.
> >> 
> >> Rename all DELAY_SLOT_* and GUSA_* defines to emphasize
> >> that they are included in TB_FLAGs.  Add aliases for the
> >> FPSCR and SR bits that are included in TB_FLAGS, so that
> >> we don't accidentally reassign those bits.
> >> 
> >> Fixes: 4da06fb3062 ("target/sh4: Implement prctl_unalign_sigbus")
> >> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/856
> >> Signed-off-by: Richard Henderson 
> >> ---
> >>   target/sh4/cpu.h| 56 +
> >>   linux-user/sh4/signal.c |  6 +--
> >>   target/sh4/cpu.c|  6 +--
> >>   target/sh4/helper.c |  6 +--
> >>   target/sh4/translate.c  | 90 ++---
> >>   5 files changed, 88 insertions(+), 76 deletions(-)
> >> 
> >> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
> >> index 9f15ef913c..727b829598 100644
> >> --- a/target/sh4/cpu.h
> >> +++ b/target/sh4/cpu.h
> >> @@ -78,26 +78,33 @@
> >>   #define FPSCR_RM_NEAREST   (0 << 0)
> >>   #define FPSCR_RM_ZERO  (1 << 0)
> >>   -#define DELAY_SLOT_MASK0x7
> >> -#define DELAY_SLOT (1 << 0)
> >> -#define DELAY_SLOT_CONDITIONAL (1 << 1)
> >> -#define DELAY_SLOT_RTE (1 << 2)
> >> +#define TB_FLAG_DELAY_SLOT   (1 << 0)
> >> +#define TB_FLAG_DELAY_SLOT_COND  (1 << 1)
> >> +#define TB_FLAG_DELAY_SLOT_RTE   (1 << 2)
> >> +#define TB_FLAG_PENDING_MOVCA(1 << 3)
> >> +#define TB_FLAG_GUSA_SHIFT   4  /* [11:4] */
> >> +#define TB_FLAG_GUSA_EXCLUSIVE   (1 << 12)
> >> +#define TB_FLAG_UNALIGN  (1 << 13)
> >> +#define TB_FLAG_SR_FD(1 << SR_FD)   /* 15 */
> >> +#define TB_FLAG_FPSCR_PR FPSCR_PR   /* 19 */
> >> +#define TB_FLAG_FPSCR_SZ FPSCR_SZ   /* 20 */
> >> +#define TB_FLAG_FPSCR_FR FPSCR_FR   /* 21 */
> >> +#define TB_FLAG_SR_RB(1 << SR_RB)   /* 29 */
> >> +#define TB_FLAG_SR_MD(1 << SR_MD)   /* 30 */
> >>   -#define TB_FLAG_PENDING_MOVCA  (1 << 3)
> >> -#define TB_FLAG_UNALIGN(1 << 4)
> >> -
> >> -#define GUSA_SHIFT 4
> >> -#ifdef CONFIG_USER_ONLY
> >> -#define GUSA_EXCLUSIVE (1 << 12)
> >> -#define GUSA_MASK  ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE)
> >> -#else
> >> -/* Provide dummy versions of the above to allow tests against tbflags
> >> -   to be elided while avoiding ifdefs.  */
> >> -#define GUSA_EXCLUSIVE 0
> >> -#define GUSA_MASK  0
> >> -#endif
> >> -
> >> -#define TB_FLAG_ENVFLAGS_MASK  (DELAY_SLOT_MASK | GUSA_MASK)
> >> +#define TB_FLAG_DELAY_SLOT_MASK  (TB_FLAG_DELAY_SLOT |   \
> >> +  TB_FLAG_DELAY_SLOT_COND |  \
> >> +  TB_FLAG_DELAY_SLOT_RTE)
> >> +#define TB_FLAG_GUSA_MASK((0xff << TB_FLAG_GUSA_SHIFT) | \
> >> +  TB_FLAG_GUSA_EXCLUSIVE)
> >> +#define TB_FLAG_FPSCR_MASK   (TB_FLAG_FPSCR_PR | \
> >> +  TB_FLAG_FPSCR_SZ | \
> >> +  TB_FLAG_FPSCR_FR)
> >> +#define TB_FLAG_SR_MASK  (TB_FLAG_SR_FD | \
> >> +  TB_FLAG_SR_RB | \
> >> +  TB_FLAG_SR_MD)
> >> +#define TB_FLAG_ENVFLAGS_MASK(TB_FLAG_DELAY_SLOT_MASK | \
> >> +  TB_FLAG_GUSA_MASK)
> >> typedef struct tlb_t {
> >>   uint32_t vpn;/* virtual page number */
> >> @@ -258,7 +265,7 @@ static inline int cpu_mmu_index (CPUSH4State *env, 
> >> bool ifetch)
> >>   {
> >>   /* The instruction in a RTE delay slot is fetched in privileged
> >>  mode, but executed in user mode.  */
> >> -if (ifetch && (env->flags & DELAY_SLOT_RTE)) {
> >> +if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
> >>   return 0;
> >>   } else {
> >>   return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
> >> @@ -366,11 +373,10 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State 
> >> *env, target_ulong *pc,
> >>   {
> >>   *pc = env->pc;
> >>   /* For a gUSA region, notice the end of the region.  */
> >> -*cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0;
> >> -*flags = env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */
> >> -| (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))  /* Bits 
> >> 19-21 */
> >> -| (env->sr & ((1u << SR_MD) | (1u << SR_RB)))  /* Bits 
> >> 29-30 */
> >> -| (env->sr & (1u << SR_FD))/* Bit 15 
> >> */
> >> +*cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 

Re: [PATCH 1/1] qxl: add subsystem_vendor_id property

2022-10-03 Thread Denis V. Lunev

On 9/29/22 09:37, Gerd Hoffmann wrote:

On Wed, Sep 28, 2022 at 05:52:44PM +0200, Denis V. Lunev wrote:

This property is needed for WHQL/inboxing of Windows drivers. We do need
to get drivers to be separated by the hypervisor vendors and that should
be done as PCI subvendor ID.

This patch adds PCI subsystem vendor ID to QXL device to match that
convention.

We have pci_default_sub_vendor_id + pci_default_sub_device_id in
hw/pci/pci.c.  If you want another subsystem id for another vendor
there is a single place to change it for all devices.

Right now there is no runtime switch for them, so updating it requires
a two-liner patch for your vendor build.  We can discuss changing that,
but that should best be coordinated with libvirt folks to make sure
the management stack actually allows setting the subsystem id without
needing hacks.

Yes. There is no runtime switch for it. I have also checked this.

The story here seems more complex. We are using in our
downstream the following patch from Ben Warren

https://lists.gnu.org/archive/html/qemu-devel/2017-12/msg02128.html

and I have mistakenly thought that it was accepted in
the mainstream. OK, unfortunately that was not happen.
As this has been pointed out in the above thread
the discussion was moved into

https://patchwork.kernel.org/project/qemu-devel/patch/20171102133115.19195-1-lpro...@redhat.com/

Anyway, we need to support different PCI sub-vendor IDs
in order to be compliant with Microsoft WHQL rules. Though,
actually, at my opinion this requirement has nothing in
common with libvirt people. The most convenient way
here would be to specify these properties within vendor
machine types and this place is a perfect match as any
respectable has its own machine type.

I would also think that PCI level is not a good place for that
as we would not be able to apply this change blindly as at
PCI level this change would be too global and the same
was initially noted by Michael Tsirkin here

https://lists.gnu.org/archive/html/qemu-devel/2017-12/msg04384.html

Any thoughts?
What should we do with the original patch from Ben? We
still need an ability to expose vendor identity in QXL/virtio...

Den



[PATCH] docs/nuvoton: Update URL for images

2022-10-03 Thread Joel Stanley
openpower.xyz was retired some time ago. The OpenBMC Jenkins is where
images can be found these days.

Signed-off-by: Joel Stanley 
---
 docs/system/arm/nuvoton.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index ef2792076aa8..c38df32bde07 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -82,9 +82,9 @@ Boot options
 
 The Nuvoton machines can boot from an OpenBMC firmware image, or directly into
 a kernel using the ``-kernel`` option. OpenBMC images for ``quanta-gsj`` and
-possibly others can be downloaded from the OpenPOWER jenkins :
+possibly others can be downloaded from the OpenBMC jenkins :
 
-   https://openpower.xyz/
+   https://jenkins.openbmc.org/
 
 The firmware image should be attached as an MTD drive. Example :
 
-- 
2.35.1




Re: [PATCH v2 2/3] target/arm: Use ARMGranuleSize in ARMVAParameters

2022-10-03 Thread Richard Henderson

On 10/3/22 09:23, Peter Maydell wrote:

Now we have an enum for the granule size, use it in the
ARMVAParameters struct instead of the using16k/using64k bools.

Signed-off-by: Peter Maydell
---
  target/arm/internals.h | 23 +--
  target/arm/helper.c| 39 ---
  target/arm/ptw.c   |  8 +---
  3 files changed, 50 insertions(+), 20 deletions(-)


Reviewed-by: Richard Henderson 

r~



Re: x86, pflash, unassigned memory access

2022-10-03 Thread Alexey Kardashevskiy

Anyone, ping?

On 27/09/2022 12:35, Alexey Kardashevskiy wrote:

Hi!

I am trying qemu-system-x86_64 with OVMF with the q35 machine, the 
complete command line is below.


It works fine (including SEV on AMD EPYC), but these 2 parameters make 
me wonder if I miss something:


-drive 
if=pflash,format=raw,unit=0,file=/home/aik/OVMF_CODE.fd,readonly=on,id=MYPF \

-d guest_errors

With this, I see a bunch of
===
Invalid access at addr 0xFFC0, size 1, region '(null)', reason: 
rejected
Invalid access at addr 0xFFC1, size 1, region '(null)', reason: 
rejected
Invalid access at addr 0xFFC2, size 1, region '(null)', reason: 
rejected

...
Invalid access at addr 0xFFC00FFF, size 1, region '(null)', reason: 
rejected

QEMU Flash: Failed to find probe location
QEMU flash was not detected. Writable FVB is not being installed.
===

These are the indication of unassigned memory access which always meant 
a bug in my past experience (which is POWERPC so not so relevant here 
but nevertheless).


OVMF is probing the flash at 0xFFC0 (hardcoded in OVMF) in
https://github.com/tianocore/edk2/blob/master/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c#L65
but cannot succeed - "info mtree -f" says that at no point there is 
anything at 0xFFC0:


===
...
fed1c000-fed1 (prio 1, i/o): lpc-rcrb-mmio
fee0-feef (prio 4096, i/o): kvm-apic-msi
ffc84000- (prio 0, romd): system.flash0 KVM
0008-00080fff (prio 0, i/o): 
virtio-pci-common-virtio-net

...
===

hw/block/pflash_cfi01.c suggests QEMU implements this protocol via 
pflash_cfi01_ops but it is never called as:

- it is the same memory region as the OVMF code and
- it is mapped at 0xffc84000 (which is 4G - 
size("./Build/OvmfX64/DEBUG_GCC5/FV/OVMF_CODE.fd"), not where OVMF 
expects it) and
- it has romd==true, it is a KVM memory slot and IO is never emulated in 
QEMU.


Adding another IO memory region with pflash_cfi01_ops and mapping it at 
0xFFC0 makes it loop in OVMF somewhere.


OVMF code is linked to hardcoded 0xffc84000 (FD_SIZE_IN_KB==4096).


So I wonder - are these illegal accesses a bug of some sort in QEMU or 
OVMF or command line? Thanks,





The complete command line is:

/home/aik/pbuild/qemu-snp-localhost-x86_64/qemu-system-x86_64 \
-enable-kvm \
-m 2G \
-smp 2 \
-netdev user,id=USER0,hostfwd=tcp::2223-:22 \
-device 
virtio-net-pci,id=vnet0,iommu_platform=on,disable-legacy=on,romfile=,netdev=USER0 \

-machine q35 \
-device 
virtio-scsi-pci,id=vscsi0,iommu_platform=on,disable-modern=off,disable-legacy=on \
-drive 
id=DRIVE0,if=none,file=img/u2204_128G_aikbook_sev.qcow2,format=qcow2 \

-device scsi-hd,id=scsi-hd0,drive=DRIVE0 \
-drive 
if=pflash,format=raw,unit=0,file=/home/aik/OVMF_CODE.fd,readonly=on,id=MYPF \

-nographic \
-chardev stdio,id=STDIO0,signal=off,mux=on \
-device isa-serial,id=isa-serial0,chardev=STDIO0 \
-mon id=MON0,chardev=STDIO0,mode=readline \
-kernel /boot/vmlinuz \
-append console=ttyS0,115200n1 earlyprintk root=/dev/sda3 \
-d guest_errors




--
Alexey



A few QEMU questiosn

2022-10-03 Thread a b
Hello, there,

I have a few newbie QEMU questions.  I found that mmu_idx in aarch64-softmmu  
falls in 8, 10 and 12.

I need some help to understand what they are for.

I cannot find which macros are for mmu-idx 8, 10 and 12 at 
target/arm/cpu.h.
 It looks like all the values from 
ARMMMUIdx
 are greater than 0x10 (ARM_MMU_IDX_A). Am I looking at the wrong place or 
missing something for the different MMU modes in aarch64?

I'd appreciate your help.

Regards



[PATCH v4 5/6] hw/arm/virt: Improve high memory region address

2022-10-03 Thread Gavin Shan
There are three high memory regions, which are VIRT_HIGH_REDIST2,
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
are floating on highest RAM address. However, they can be disabled
in several cases.

(1) One specific high memory region is disabled by developer by
toggling vms->highmem_{redists, ecam, mmio}.

(2) VIRT_HIGH_PCIE_ECAM region is disabled on machine, which is
'virt-2.12' or ealier than it.

(3) VIRT_HIGH_PCIE_ECAM region is disabled when firmware is loaded
on 32-bits system.

(4) One specific high memory region is disabled when it breaks the
PA space limit.

The current implementation of virt_set_memmap() isn't comprehensive
because the space for one specific high memory region is always
reserved from the PA space for case (1), (2) and (3). In the code,
'base' and 'vms->highest_gpa' are always increased for those three
cases. It's unnecessary since the assigned space of the disabled
high memory region won't be used afterwards.

This improves the address assignment for those three high memory
region by skipping the address assignment for one specific high
memory region if it has been disabled in case (1), (2) and (3).
'vms->high_compact' is false for now, meaning that we don't have
any behavior changes until it becomes configurable through property
'compact-highmem' in next patch.

Signed-off-by: Gavin Shan 
---
 hw/arm/virt.c | 19 ---
 include/hw/arm/virt.h |  1 +
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 59de7b78b5..4164da49e9 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1715,9 +1715,6 @@ static void virt_set_high_memmap(VirtMachineState *vms,
 region_base = ROUND_UP(base, extended_memmap[i].size);
 region_size = extended_memmap[i].size;
 
-vms->memmap[i].base = region_base;
-vms->memmap[i].size = region_size;
-
 /*
  * Check each device to see if they fit in the PA space,
  * moving highest_gpa as we go.
@@ -1725,12 +1722,20 @@ static void virt_set_high_memmap(VirtMachineState *vms,
  * For each device that doesn't fit, disable it.
  */
 fits = (region_base + region_size) <= BIT_ULL(pa_bits);
-if (fits) {
+if (*region_enabled && fits) {
+vms->memmap[i].base = region_base;
+vms->memmap[i].size = region_size;
 vms->highest_gpa = region_base + region_size - 1;
+base = region_base + region_size;
+} else {
+*region_enabled = false;
+if (!vms->highmem_compact) {
+base = region_base + region_size;
+if (fits) {
+vms->highest_gpa = region_base + region_size - 1;
+}
+}
 }
-
-*region_enabled &= fits;
-base = region_base + region_size;
 }
 }
 
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 6ec479ca2b..709f623741 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -144,6 +144,7 @@ struct VirtMachineState {
 PFlashCFI01 *flash[2];
 bool secure;
 bool highmem;
+bool highmem_compact;
 bool highmem_ecam;
 bool highmem_mmio;
 bool highmem_redists;
-- 
2.23.0




[PATCH v4 6/6] hw/arm/virt: Add 'compact-highmem' property

2022-10-03 Thread Gavin Shan
After the improvement to high memory region address assignment is
applied, the memory layout can be changed, introducing possible
migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region
is disabled or enabled when the optimization is applied or not, with
the following configuration.

  pa_bits  = 40;
  vms->highmem_redists = false;
  vms->highmem_ecam= false;
  vms->highmem_mmio= true;

  # qemu-system-aarch64 -accel kvm -cpu host\
-machine virt-7.2,compact-highmem={on, off} \
-m 4G,maxmem=511G -monitor stdio

  Regioncompact-highmem=off compact-highmem=on
  
  RAM   [1GB 512GB][1GB 512GB]
  HIGH_GIC_REDISTS  [512GB   512GB+64MB]   [disabled]
  HIGH_PCIE_ECAM[512GB+256MB 512GB+512MB]  [disabled]
  HIGH_PCIE_MMIO[disabled] [512GB   1TB]

In order to keep backwords compatibility, we need to disable the
optimization on machines, which is virt-7.1 or ealier than it. It
means the optimization is enabled by default from virt-7.2. Besides,
'compact-highmem' property is added so that the optimization can be
explicitly enabled or disabled on all machine types by users.

Signed-off-by: Gavin Shan 
---
 docs/system/arm/virt.rst |  4 
 hw/arm/virt.c| 47 
 include/hw/arm/virt.h|  1 +
 3 files changed, 52 insertions(+)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index 20442ea2c1..75bf5a4994 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -94,6 +94,10 @@ highmem
   address space above 32 bits. The default is ``on`` for machine types
   later than ``virt-2.12``.
 
+compact-highmem
+  Set ``on``/``off`` to enable/disable compact space for high memory regions.
+  The default is ``on`` for machine types later than ``virt-7.2``
+
 gic-version
   Specify the version of the Generic Interrupt Controller (GIC) to provide.
   Valid values are:
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4164da49e9..9fe65a2ae1 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -174,6 +174,27 @@ static const MemMapEntry base_memmap[] = {
  * Note the extended_memmap is sized so that it eventually also includes the
  * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
  * index of base_memmap).
+ *
+ * The addresses assigned to these regions are affected by 'compact-highmem'
+ * property, which is to enable or disable the compact space in the Highmem
+ * IO regions. For example, VIRT_HIGH_PCIE_MMIO can be disabled or enabled
+ * depending on the property in the following scenario.
+ *
+ * pa_bits  = 40;
+ * vms->highmem_redists = false;
+ * vms->highmem_ecam= false;
+ * vms->highmem_mmio= true;
+ *
+ * # qemu-system-aarch64 -accel kvm -cpu host\
+ *   -machine virt-7.2,compact-highmem={on, off} \
+ *   -m 4G,maxmem=511G -monitor stdio
+ *
+ * Regioncompact-highmem=offcompact-highmem=on
+ * 
+ * RAM   [1GB 512GB][1GB 512GB]
+ * HIGH_GIC_REDISTS  [512GB   512GB+64MB]   [disabled]
+ * HIGH_PCIE_ECAM[512GB+256GB 512GB+512MB]  [disabled]
+ * HIGH_PCIE_MMIO[disabled] [512GB   1TB]
  */
 static MemMapEntry extended_memmap[] = {
 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
@@ -2349,6 +2370,20 @@ static void virt_set_highmem(Object *obj, bool value, 
Error **errp)
 vms->highmem = value;
 }
 
+static bool virt_get_compact_highmem(Object *obj, Error **errp)
+{
+VirtMachineState *vms = VIRT_MACHINE(obj);
+
+return vms->highmem_compact;
+}
+
+static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
+{
+VirtMachineState *vms = VIRT_MACHINE(obj);
+
+vms->highmem_compact = value;
+}
+
 static bool virt_get_its(Object *obj, Error **errp)
 {
 VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -2967,6 +3002,13 @@ static void virt_machine_class_init(ObjectClass *oc, 
void *data)
   "Set on/off to enable/disable using "
   "physical address space above 32 
bits");
 
+object_class_property_add_bool(oc, "compact-highmem",
+   virt_get_compact_highmem,
+   virt_set_compact_highmem);
+object_class_property_set_description(oc, "compact-highmem",
+  "Set on/off to enable/disable 
compact "
+  "space for high memory regions");
+
 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
   virt_set_gic_version);
 object_class_property_set_description(oc, "gic-version",
@@ -3051,6 +3093,7 @@ static void virt_instance_init(Object 

[PATCH v4 4/6] hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper

2022-10-03 Thread Gavin Shan
This introduces virt_get_high_memmap_enabled() helper, which returns
the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will
be used in the subsequent patches.

No functional change intended.

Signed-off-by: Gavin Shan 
---
 hw/arm/virt.c | 30 +-
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index b0b679d1f4..59de7b78b5 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1689,14 +1689,29 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState 
*vms, int idx)
 return arm_cpu_mp_affinity(idx, clustersz);
 }
 
+static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
+ int index)
+{
+bool *enabled_array[] = {
+>highmem_redists,
+>highmem_ecam,
+>highmem_mmio,
+};
+
+assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
+
+return enabled_array[index - VIRT_LOWMEMMAP_LAST];
+}
+
 static void virt_set_high_memmap(VirtMachineState *vms,
  hwaddr base, int pa_bits)
 {
 hwaddr region_base, region_size;
-bool fits;
+bool *region_enabled, fits;
 int i;
 
 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
+region_enabled = virt_get_high_memmap_enabled(vms, i);
 region_base = ROUND_UP(base, extended_memmap[i].size);
 region_size = extended_memmap[i].size;
 
@@ -1714,18 +1729,7 @@ static void virt_set_high_memmap(VirtMachineState *vms,
 vms->highest_gpa = region_base + region_size - 1;
 }
 
-switch (i) {
-case VIRT_HIGH_GIC_REDIST2:
-vms->highmem_redists &= fits;
-break;
-case VIRT_HIGH_PCIE_ECAM:
-vms->highmem_ecam &= fits;
-break;
-case VIRT_HIGH_PCIE_MMIO:
-vms->highmem_mmio &= fits;
-break;
-}
-
+*region_enabled &= fits;
 base = region_base + region_size;
 }
 }
-- 
2.23.0




[PATCH v4 0/6] hw/arm/virt: Improve address assignment for high memory regions

2022-10-03 Thread Gavin Shan
There are three high memory regions, which are VIRT_HIGH_REDIST2,
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
are floating on highest RAM address. However, they can be disabled
in several cases.

(1) One specific high memory region is disabled by developer by
toggling vms->highmem_{redists, ecam, mmio}.

(2) VIRT_HIGH_PCIE_ECAM region is disabled on machine, which is
'virt-2.12' or ealier than it.

(3) VIRT_HIGH_PCIE_ECAM region is disabled when firmware is loaded
on 32-bits system.

(4) One specific high memory region is disabled when it breaks the
PA space limit.

The current implementation of virt_set_memmap() isn't comprehensive
because the space for one specific high memory region is always
reserved from the PA space for case (1), (2) and (3). In the code,
'base' and 'vms->highest_gpa' are always increased for those three
cases. It's unnecessary since the assigned space of the disabled
high memory region won't be used afterwards.

The series intends to improve the address assignment for these
high memory regions.

PATCH[1-4] preparatory work for the improvment
PATCH[5]   improve high memory region address assignment
PATCH[6]   adds 'compact-highmem' to enable or disable the optimization

History
===
v3: https://lists.nongnu.org/archive/html/qemu-arm/2022-09/msg00258.html
v2: https://lore.kernel.org/all/20220815062958.100366-1-gs...@redhat.com/T/
v1: https://lists.nongnu.org/archive/html/qemu-arm/2022-08/msg00013.html

Changelog
==
v4:
  * Add virt_get_high_memmap_enabled() helper  (Eric)
  * Move 'vms->highmem_compact' and related logic from
PATCH[v4 6/6] to PATCH[v4 5/6] to avoid git-bisect
breakage   (Eric)
  * Document the legacy and optimized high memory region
layout in commit log and source code   (Eric)
v3:
  * Reorder the patches(Gavin)
  * Add 'highmem-compact' property for backwards compatibility (Eric)
v2:
  * Split the patches for easier review(Gavin)
  * Improved changelog (Marc)
  * Use 'bool fits' in virt_set_high_memmap()  (Eric)

Gavin Shan (6):
  hw/arm/virt: Introduce virt_set_high_memmap() helper
  hw/arm/virt: Rename variable size to region_size in
virt_set_high_memmap()
  hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()
  hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper
  hw/arm/virt: Improve high memory region address
  hw/arm/virt: Add 'compact-highmem' property

 docs/system/arm/virt.rst |   4 ++
 hw/arm/virt.c| 131 +--
 include/hw/arm/virt.h|   2 +
 3 files changed, 104 insertions(+), 33 deletions(-)

-- 
2.23.0




[PATCH v4 2/6] hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap()

2022-10-03 Thread Gavin Shan
This renames variable 'size' to 'region_size' in virt_set_high_memmap().
Its counterpart ('region_base') will be introduced in next patch.

No functional change intended.

Signed-off-by: Gavin Shan 
Reviewed-by: Eric Auger 
---
 hw/arm/virt.c | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4dab528b82..187b3ee0e2 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1692,15 +1692,16 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState 
*vms, int idx)
 static void virt_set_high_memmap(VirtMachineState *vms,
  hwaddr base, int pa_bits)
 {
+hwaddr region_size;
+bool fits;
 int i;
 
 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
-hwaddr size = extended_memmap[i].size;
-bool fits;
+region_size = extended_memmap[i].size;
 
-base = ROUND_UP(base, size);
+base = ROUND_UP(base, region_size);
 vms->memmap[i].base = base;
-vms->memmap[i].size = size;
+vms->memmap[i].size = region_size;
 
 /*
  * Check each device to see if they fit in the PA space,
@@ -1708,9 +1709,9 @@ static void virt_set_high_memmap(VirtMachineState *vms,
  *
  * For each device that doesn't fit, disable it.
  */
-fits = (base + size) <= BIT_ULL(pa_bits);
+fits = (base + region_size) <= BIT_ULL(pa_bits);
 if (fits) {
-vms->highest_gpa = base + size - 1;
+vms->highest_gpa = base + region_size - 1;
 }
 
 switch (i) {
@@ -1725,7 +1726,7 @@ static void virt_set_high_memmap(VirtMachineState *vms,
 break;
 }
 
-base += size;
+base += region_size;
 }
 }
 
-- 
2.23.0




[PATCH v4 1/6] hw/arm/virt: Introduce virt_set_high_memmap() helper

2022-10-03 Thread Gavin Shan
This introduces virt_set_high_memmap() helper. The logic of high
memory region address assignment is moved to the helper. The intention
is to make the subsequent optimization for high memory region address
assignment easier.

No functional change intended.

Signed-off-by: Gavin Shan 
Reviewed-by: Eric Auger 
Reviewed-by: Cornelia Huck 
---
 hw/arm/virt.c | 74 ---
 1 file changed, 41 insertions(+), 33 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 0961e053e5..4dab528b82 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1689,6 +1689,46 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState 
*vms, int idx)
 return arm_cpu_mp_affinity(idx, clustersz);
 }
 
+static void virt_set_high_memmap(VirtMachineState *vms,
+ hwaddr base, int pa_bits)
+{
+int i;
+
+for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
+hwaddr size = extended_memmap[i].size;
+bool fits;
+
+base = ROUND_UP(base, size);
+vms->memmap[i].base = base;
+vms->memmap[i].size = size;
+
+/*
+ * Check each device to see if they fit in the PA space,
+ * moving highest_gpa as we go.
+ *
+ * For each device that doesn't fit, disable it.
+ */
+fits = (base + size) <= BIT_ULL(pa_bits);
+if (fits) {
+vms->highest_gpa = base + size - 1;
+}
+
+switch (i) {
+case VIRT_HIGH_GIC_REDIST2:
+vms->highmem_redists &= fits;
+break;
+case VIRT_HIGH_PCIE_ECAM:
+vms->highmem_ecam &= fits;
+break;
+case VIRT_HIGH_PCIE_MMIO:
+vms->highmem_mmio &= fits;
+break;
+}
+
+base += size;
+}
+}
+
 static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
 {
 MachineState *ms = MACHINE(vms);
@@ -1744,39 +1784,7 @@ static void virt_set_memmap(VirtMachineState *vms, int 
pa_bits)
 /* We know for sure that at least the memory fits in the PA space */
 vms->highest_gpa = memtop - 1;
 
-for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
-hwaddr size = extended_memmap[i].size;
-bool fits;
-
-base = ROUND_UP(base, size);
-vms->memmap[i].base = base;
-vms->memmap[i].size = size;
-
-/*
- * Check each device to see if they fit in the PA space,
- * moving highest_gpa as we go.
- *
- * For each device that doesn't fit, disable it.
- */
-fits = (base + size) <= BIT_ULL(pa_bits);
-if (fits) {
-vms->highest_gpa = base + size - 1;
-}
-
-switch (i) {
-case VIRT_HIGH_GIC_REDIST2:
-vms->highmem_redists &= fits;
-break;
-case VIRT_HIGH_PCIE_ECAM:
-vms->highmem_ecam &= fits;
-break;
-case VIRT_HIGH_PCIE_MMIO:
-vms->highmem_mmio &= fits;
-break;
-}
-
-base += size;
-}
+virt_set_high_memmap(vms, base, pa_bits);
 
 if (device_memory_size > 0) {
 ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
-- 
2.23.0




[PATCH v4 3/6] hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()

2022-10-03 Thread Gavin Shan
This introduces variable 'region_base' for the base address of the
specific high memory region. It's the preparatory work to optimize
high memory region address assignment.

No functional change intended.

Signed-off-by: Gavin Shan 
Reviewed-by: Eric Auger 
---
 hw/arm/virt.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 187b3ee0e2..b0b679d1f4 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1692,15 +1692,15 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState 
*vms, int idx)
 static void virt_set_high_memmap(VirtMachineState *vms,
  hwaddr base, int pa_bits)
 {
-hwaddr region_size;
+hwaddr region_base, region_size;
 bool fits;
 int i;
 
 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
+region_base = ROUND_UP(base, extended_memmap[i].size);
 region_size = extended_memmap[i].size;
 
-base = ROUND_UP(base, region_size);
-vms->memmap[i].base = base;
+vms->memmap[i].base = region_base;
 vms->memmap[i].size = region_size;
 
 /*
@@ -1709,9 +1709,9 @@ static void virt_set_high_memmap(VirtMachineState *vms,
  *
  * For each device that doesn't fit, disable it.
  */
-fits = (base + region_size) <= BIT_ULL(pa_bits);
+fits = (region_base + region_size) <= BIT_ULL(pa_bits);
 if (fits) {
-vms->highest_gpa = base + region_size - 1;
+vms->highest_gpa = region_base + region_size - 1;
 }
 
 switch (i) {
@@ -1726,7 +1726,7 @@ static void virt_set_high_memmap(VirtMachineState *vms,
 break;
 }
 
-base += region_size;
+base = region_base + region_size;
 }
 }
 
-- 
2.23.0




Re: ublk-qcow2: ublk-qcow2 is available

2022-10-03 Thread Denis V. Lunev

On 10/3/22 21:53, Stefan Hajnoczi wrote:

On Fri, Sep 30, 2022 at 05:24:11PM +0800, Ming Lei wrote:

ublk-qcow2 is available now.

Cool, thanks for sharing!

yep


So far it provides basic read/write function, and compression and snapshot
aren't supported yet. The target/backend implementation is completely
based on io_uring, and share the same io_uring with ublk IO command
handler, just like what ublk-loop does.

Follows the main motivations of ublk-qcow2:

- building one complicated target from scratch helps libublksrv APIs/functions
   become mature/stable more quickly, since qcow2 is complicated and needs more
   requirement from libublksrv compared with other simple ones(loop, null)

- there are several attempts of implementing qcow2 driver in kernel, such as
   ``qloop`` [2], ``dm-qcow2`` [3] and ``in kernel qcow2(ro)`` [4], so 
ublk-qcow2
   might useful be for covering requirement in this field

There is one important thing to keep in mind about all partly-userspace
implementations though:
* any single allocation happened in the context of the
   userspace daemon through try_to_free_pages() in
   kernel has a possibility to trigger the operation,
   which will require userspace daemon action, which
   is inside the kernel now.
* the probability of this is higher in the overcommitted
   environment

This was the main motivation of us in favor for the in-kernel
implementation.


- performance comparison with qemu-nbd, and it was my 1st thought to evaluate
   performance of ublk/io_uring backend by writing one ublk-qcow2 since ublksrv
   is started

- help to abstract common building block or design pattern for writing new ublk
   target/backend

So far it basically passes xfstest(XFS) test by using ublk-qcow2 block
device as TEST_DEV, and kernel building workload is verified too. Also
soft update approach is applied in meta flushing, and meta data
integrity is guaranteed, 'make test T=qcow2/040' covers this kind of
test, and only cluster leak is reported during this test.

The performance data looks much better compared with qemu-nbd, see
details in commit log[1], README[5] and STATUS[6]. And the test covers both
empty image and pre-allocated image, for example of pre-allocated qcow2
image(8GB):

- qemu-nbd (make test T=qcow2/002)

Single queue?


randwrite(4k): jobs 1, iops 24605
randread(4k): jobs 1, iops 30938
randrw(4k): jobs 1, iops read 13981 write 14001
rw(512k): jobs 1, iops read 724 write 728

Please try qemu-storage-daemon's VDUSE export type as well. The
command-line should be similar to this:

   # modprobe virtio_vdpa # attaches vDPA devices to host kernel
   # modprobe vduse
   # qemu-storage-daemon \
   --blockdev 
file,filename=test.qcow2,cache.direct=of|off,aio=native,node-name=file \
   --blockdev qcow2,file=file,node-name=qcow2 \
   --object iothread,id=iothread0 \
   --export 
vduse-blk,id=vduse0,name=vduse0,num-queues=$(nproc),node-name=qcow2,writable=on,iothread=iothread0
   # vdpa dev add name vduse0 mgmtdev vduse

A virtio-blk device should appear and xfstests can be run on it
(typically /dev/vda unless you already have other virtio-blk devices).

Afterwards you can destroy the device using:

   # vdpa dev del vduse0

but this would be anyway limited by a single thread doing AIO in
qemu-storage-daemon, I believe.



- ublk-qcow2 (make test T=qcow2/022)

There are a lot of other factors not directly related to NBD vs ublk. In
order to get an apples-to-apples comparison with qemu-* a ublk export
type is needed in qemu-storage-daemon. That way only the difference is
the ublk interface and the rest of the code path is identical, making it
possible to compare NBD, VDUSE, ublk, etc more precisely.

I think that comparison is interesting before comparing different qcow2
implementations because qcow2 sits on top of too much other code. It's
hard to know what should be accounted to configuration differences,
implementation differences, or fundamental differences that cannot be
overcome (this is the interesting part!).


randwrite(4k): jobs 1, iops 104481
randread(4k): jobs 1, iops 114937
randrw(4k): jobs 1, iops read 53630 write 53577
rw(512k): jobs 1, iops read 1412 write 1423

Also ublk-qcow2 aligns queue's chunk_sectors limit with qcow2's cluster size,
which is 64KB at default, this way simplifies backend io handling, but
it could be increased to 512K or more proper size for improving sequential
IO perf, just need one coroutine to handle more than one IOs.


[1] 
https://github.com/ming1/ubdsrv/commit/9faabbec3a92ca83ddae92335c66eabbeff654e7
[2] 
https://upcommons.upc.edu/bitstream/handle/2099.1/9619/65757.pdf?sequence=1=y
[3] https://lwn.net/Articles/889429/
[4] https://lab.ks.uni-freiburg.de/projects/kernel-qcow2/repository
[5] https://github.com/ming1/ubdsrv/blob/master/qcow2/README.rst
[6] https://github.com/ming1/ubdsrv/blob/master/qcow2/STATUS.rst


interesting...

Den



Re: [PATCH v3 5/5] hw/arm/virt: Add 'highmem-compact' property

2022-10-03 Thread Gavin Shan

Hi Eric,

On 10/3/22 4:49 PM, Eric Auger wrote:

On 9/29/22 01:49, Gavin Shan wrote:

On 9/28/22 10:22 PM, Eric Auger wrote:

On 9/22/22 01:13, Gavin Shan wrote:

After the improvement to high memory region address assignment is
applied, the memory layout is changed. For example, VIRT_HIGH_PCIE_MMIO

s/the memory layout is changed./the memory layout is changed,
introducing possible migration breakage.


Ok, much clearer.


memory region is enabled when the improvement is applied, but it's
disabled if the improvement isn't applied.

  pa_bits  = 40;
  vms->highmem_redists = false;
  vms->highmem_ecam    = false;
  vms->highmem_mmio    = true;

  # qemu-system-aarch64 -accel kvm -cpu host \
    -machine virt-7.2 -m 4G,maxmem=511G  \
    -monitor stdio

In order to keep backwords compatibility, we need to disable the
optimization on machines, which is virt-7.1 or ealier than it. It
means the optimization is enabled by default from virt-7.2. Besides,
'highmem-compact' property is added so that the optimization can be

I would rather rename the property into compact-highmem even if the vms
field is name highmem_compact to align with other highmem fields


Ok, but I would love to know why. Note that we already have
'highmem=on|off'. 'highmem_compact=on|off' seems consistent
to me.

To me the property name should rather sound 'english' with the adjective
before the name 'high memory"' but I am not a native english speaker
either.


Ok. I agree 'compact-highmem' is better. The backup variable name will
be still 'highmem_compact', which is consistent with the existing ones.




explicitly enabled or disabled on all machine types by users.

Signed-off-by: Gavin Shan 
---
   docs/system/arm/virt.rst |  4 
   hw/arm/virt.c    | 33 +
   include/hw/arm/virt.h    |  2 ++
   3 files changed, 39 insertions(+)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index 20442ea2c1..f05ec2253b 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -94,6 +94,10 @@ highmem
     address space above 32 bits. The default is ``on`` for machine
types
     later than ``virt-2.12``.
   +highmem-compact
+  Set ``on``/``off`` to enable/disable compact space for high
memory regions.
+  The default is ``on`` for machine types later than ``virt-7.2``

I think you should document what is compact layout versus legacy one,
both in the commit msg and maybe as a comment in a code along with the
comment in hw/arm/virt.c starting with 'Highmem IO Regions: '


Ok, I will add this into the commit log in v4. I don't think it's
necessary
to add duplicate comment in the code. People can check the commit log for
details if needed.


+
   gic-version
     Specify the version of the Generic Interrupt Controller (GIC) to
provide.
     Valid values are:
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index b702f8f2b5..a4fbdaef91 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1734,6 +1734,13 @@ static void
virt_set_high_memmap(VirtMachineState *vms,
   base = region_base + region_size;
   } else {
   *region_enabled = false;
+
+    if (!vms->highmem_compact) {

this snippet should be already present in previous patch otherwise this
will break bisectability.



Hmm, nice catch! I think I need to swap PATCH[4] and PATCH[5] in next
revision. In that order, 'compact-highmem' is introduced in PATCH[4],
but not used yet. PATCH[5] has the optimization and 'compact-highmem'
is used.

No in general you introduce the property at the very end with the code
guarded with an unset vms->highmem_compact in the previous patch.



Yeah, what I need is define 'vms->highmem_compact' in PATCH[v3 4/5],
whose value is false. I also need to update @base and @vms->highest_gpa
on !vms->highmem_compact' in PATCH[v3 4/5].




+    base = region_base + region_size;
+    if (fits) {
+    vms->highest_gpa = region_base + region_size - 1;
+    }
+    }
   }
   }
   }
@@ -2348,6 +2355,20 @@ static void virt_set_highmem(Object *obj,
bool value, Error **errp)
   vms->highmem = value;
   }
   +static bool virt_get_highmem_compact(Object *obj, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    return vms->highmem_compact;
+}
+
+static void virt_set_highmem_compact(Object *obj, bool value, Error
**errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    vms->highmem_compact = value;
+}
+
   static bool virt_get_its(Object *obj, Error **errp)
   {
   VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -2966,6 +2987,13 @@ static void
virt_machine_class_init(ObjectClass *oc, void *data)
     "Set on/off to
enable/disable using "
     "physical address space
above 32 bits");
   +    object_class_property_add_bool(oc, "highmem-compact",
+ 

Re: [PATCH v3] virtio-scsi: Send "REPORTED LUNS CHANGED" sense data upon disk hotplug events.

2022-10-03 Thread Venu Busireddy
On 2022-10-03 18:13:06 -0500, Venu Busireddy wrote:
> On 2022-09-30 18:25:48 +0200, Paolo Bonzini wrote:
> > On Fri, Sep 30, 2022 at 4:42 PM Venu Busireddy
> >  wrote:
> > > > > Immediately after a hotunplug event, qemu (without any action from
> > > > > the guest) processes a REPORT_LUNS command on the lun 0 of the device
> > > > > (haven't figured out what causes this).
> > > >
> > > > There is only one call to virtio_scsi_handle_cmd_req_prepare and it
> > > > takes the command from the guest, are you sure it is without any
> > > > action from the guest?
> > >
> > > I am sure, based on what I am observing. I am running the scsitrace
> > > (scsitrace -n vtioscsi -v) command on the Solaris guest, and I see no
> > > output there.
> > 
> > Do you have the sources to the driver and/or to the scsitrace dtrace
> 
> I do not have access to the source code. I am working on gaining access.
> 
> > script? Something must be putting the SCSI command in the queue.
> > Perhaps the driver is doing so when it sees an event? And if it is
> > bypassing the normal submission mechanism, the REPORT LUNS commands is
> > hidden in scsitrac; that in turn retruns a unit attention and steals
> 
> While SAM does say "if a REPORT LUNS command enters the enabled command
> state, the device server shall process the REPORT LUNS command and shall
> not report any unit attention condition;," it also says that the unit
> attention condition will not be cleared if the UA_INTLCK_CTRL is set to
> 10b or 11b in the "Control mode page."
> 
> It doesn't appear to me that virtio-scsi supports "Control mode pages."

Just to clarify, I am referring the mode pages with page code 0x0a (and
any subpage codes).

> Does it? If it doesn't, is the expected handling of REPORT LUNS command
> be same as the case of UA_INTLCK_CTRL being set to 00b?
> 
> And while trying to understand this, and reading the code regarding
> the handling of UA_INTLCK_CTRL, I ran across the following comment in
> scsi_req_get_sense():
> 
> /*
>  * FIXME: clearing unit attention conditions upon autosense should be done
>  * only if the UA_INTLCK_CTRL field in the Control mode page is set to 00b
>  * (SAM-5, 5.14).
>  *
>  * We assume UA_INTLCK_CTRL to be 00b for HBAs that support autosense, and
>  * 10b for HBAs that do not support it (do not call scsi_req_get_sense).
>  * Here we handle unit attention clearing for UA_INTLCK_CTRL == 00b.
>  */
> 
> If virtio-scsi doesn't support "Control mode pages," why does the above
> comment even say "assume UA_INTLCK_CTRL to be 00b" or address the case
> of 10b? Also, other than the reference to it in the above comment,
> UA_INTLCK_CTRL is not used anywhere else in the code. This comment
> confused me. Is the comment just wrong, or am I missing something? I am
> just trying to understand this better so that I am better prepared when
> the client driver folks start asking me questions about the qemu support.
> 
> Venu
> 
> > it from the other commands such as TEST UNIT READY, but that's a guest
> > driver bug.
> > 
> > But QEMU cannot just return the unit attention twice. I would start
> > with the patch to use the bus unit attention mechanism. It would be
> > even better to have two unit tests that check the behavior prescribed
> > by the standard: 1) UNIT ATTENTION from TEST UNIT READY immediately
> > after a hotunplug notification; 2) no UNIT ATTENTION from REPORT LUNS
> > and also no UNIT ATTENTION from a subsequent TEST UNIT READY command.
> > Debugging the guest is a separate step.



Re: [PATCH v10 3/7] block: add block layer APIs resembling Linux ZonedBlockDevice ioctls

2022-10-03 Thread Damien Le Moal
On 2022/10/04 2:47, Stefan Hajnoczi wrote:
> On Thu, Sep 29, 2022 at 04:36:27PM +0800, Sam Li wrote:
>> Add a new zoned_host_device BlockDriver. The zoned_host_device option
>> accepts only zoned host block devices. By adding zone management
>> operations in this new BlockDriver, users can use the new block
>> layer APIs including Report Zone and four zone management operations
>> (open, close, finish, reset).
>>
>> Qemu-io uses the new APIs to perform zoned storage commands of the device:
>> zone_report(zrp), zone_open(zo), zone_close(zc), zone_reset(zrs),
>> zone_finish(zf).
>>
>> For example, to test zone_report, use following command:
>> $ ./build/qemu-io --image-opts -n driver=zoned_host_device, 
>> filename=/dev/nullb0
>> -c "zrp offset nr_zones"
>>
>> Signed-off-by: Sam Li 
>> Reviewed-by: Hannes Reinecke 
>> ---
>>  block/block-backend.c | 146 +
>>  block/file-posix.c| 340 +-
>>  block/io.c|  41 
>>  include/block/block-common.h  |   4 +
>>  include/block/block-io.h  |   7 +
>>  include/block/block_int-common.h  |  24 +++
>>  include/block/raw-aio.h   |   6 +-
>>  include/sysemu/block-backend-io.h |  17 ++
>>  meson.build   |   4 +
>>  qapi/block-core.json  |   8 +-
>>  qemu-io-cmds.c| 148 +
>>  11 files changed, 741 insertions(+), 4 deletions(-)
>>
>> diff --git a/block/block-backend.c b/block/block-backend.c
>> index d4a5df2ac2..f7f7acd6f4 100644
>> --- a/block/block-backend.c
>> +++ b/block/block-backend.c
>> @@ -1431,6 +1431,15 @@ typedef struct BlkRwCo {
>>  void *iobuf;
>>  int ret;
>>  BdrvRequestFlags flags;
>> +union {
>> +struct {
>> +unsigned int *nr_zones;
>> +BlockZoneDescriptor *zones;
>> +} zone_report;
>> +struct {
>> +BlockZoneOp op;
>> +} zone_mgmt;
>> +};
>>  } BlkRwCo;
>>  
>>  int blk_make_zero(BlockBackend *blk, BdrvRequestFlags flags)
>> @@ -1775,6 +1784,143 @@ int coroutine_fn blk_co_flush(BlockBackend *blk)
>>  return ret;
>>  }
>>  
>> +static void blk_aio_zone_report_entry(void *opaque) {
> 
> 
> The coroutine_fn annotation is missing:
> 
>   static void coroutine_fn blk_aio_zone_report_entry(void *opaque) {
> 
>> +BlkAioEmAIOCB *acb = opaque;
>> +BlkRwCo *rwco = >rwco;
>> +
>> +rwco->ret = blk_co_zone_report(rwco->blk, rwco->offset,
>> +   rwco->zone_report.nr_zones,
>> +   rwco->zone_report.zones);
>> +blk_aio_complete(acb);
>> +}
>> +
>> +BlockAIOCB *blk_aio_zone_report(BlockBackend *blk, int64_t offset,
>> +unsigned int *nr_zones,
>> +BlockZoneDescriptor  *zones,
>> +BlockCompletionFunc *cb, void *opaque)
>> +{
>> +BlkAioEmAIOCB *acb;
>> +Coroutine *co;
>> +IO_CODE();
>> +
>> +blk_inc_in_flight(blk);
>> +acb = blk_aio_get(_aio_em_aiocb_info, blk, cb, opaque);
>> +acb->rwco = (BlkRwCo) {
>> +.blk= blk,
>> +.offset = offset,
>> +.ret= NOT_DONE,
>> +.zone_report = {
>> +.zones = zones,
>> +.nr_zones = nr_zones,
>> +},
>> +};
>> +acb->has_returned = false;
>> +
>> +co = qemu_coroutine_create(blk_aio_zone_report_entry, acb);
>> +bdrv_coroutine_enter(blk_bs(blk), co);
>> +
>> +acb->has_returned = true;
>> +if (acb->rwco.ret != NOT_DONE) {
>> +replay_bh_schedule_oneshot_event(blk_get_aio_context(blk),
>> + blk_aio_complete_bh, acb);
>> +}
>> +
>> +return >common;
>> +}
>> +
>> +static void blk_aio_zone_mgmt_entry(void *opaque) {
> 
> coroutine_fn is missing here.
> 
>> +BlkAioEmAIOCB *acb = opaque;
>> +BlkRwCo *rwco = >rwco;
>> +
>> +rwco->ret = blk_co_zone_mgmt(rwco->blk, rwco->zone_mgmt.op,
>> + rwco->offset, acb->bytes);
>> +blk_aio_complete(acb);
>> +}
>> +
>> +BlockAIOCB *blk_aio_zone_mgmt(BlockBackend *blk, BlockZoneOp op,
>> +  int64_t offset, int64_t len,
>> +  BlockCompletionFunc *cb, void *opaque) {
>> +BlkAioEmAIOCB *acb;
>> +Coroutine *co;
>> +IO_CODE();
>> +
>> +blk_inc_in_flight(blk);
>> +acb = blk_aio_get(_aio_em_aiocb_info, blk, cb, opaque);
>> +acb->rwco = (BlkRwCo) {
>> +.blk= blk,
>> +.offset = offset,
>> +.ret= NOT_DONE,
>> +.zone_mgmt = {
>> +.op = op,
>> +},
>> +};
>> +acb->bytes = len;
>> +acb->has_returned = false;
>> +
>> +co = qemu_coroutine_create(blk_aio_zone_mgmt_entry, acb);
>> +bdrv_coroutine_enter(blk_bs(blk), co);
>> +
>> +acb->has_returned = true;
>> +if (acb->rwco.ret != NOT_DONE) {
>> +

Re: [PATCH v2] mips/malta: pass RNG seed to to kernel via env var

2022-10-03 Thread Jason A. Donenfeld
Hi Philippe,

On Tue, Oct 4, 2022 at 12:36 AM Philippe Mathieu-Daudé  wrote:
> Send each new revision as a new top-level thread, rather than burying it
> in-reply-to an earlier revision, as many reviewers are not looking
> inside deep threads for new patches.

Will do.

> You seem to justify this commit by the kernel commit, which justifies
> itself mentioning hypervisor use... So the egg comes first before the
> chicken.

Oh, that's not really the intention. My goal is to provide sane
interfaces for preboot environments -- whether those are in a
hypervisor like QEMU or in firmware like CFE -- to pass a random seed
along to the kernel. To that end, I've been making sure there's both a
kernel side and a QEMU side, and submitting both to see what folks
think. The fact that you have some questions (below) is a good thing;
I'm glad to have your input on it.

> > +
> > +qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
> > +for (size_t i = 0; i < sizeof(rng_seed); ++i) {
> > +sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]);
> > +}
> > +prom_set(prom_buf, prom_index++, "rngseed");
> > +prom_set(prom_buf, prom_index++, "%s", rng_seed_hex);
>
> You use the firmware interface to pass rng data to an hypervisor...
>
> Look to me you are forcing one API to ease another one. From the
> FW PoV it is a lie, because the FW will only change this value if
> an operator is involved. Here PROM stands for "programmable read-only
> memory", rarely modified. Having the 'rngseed' updated on each
> reset is surprising.
>
> Do you have an example of firmware doing that? (So I can understand
> whether this is the best way to mimic this behavior here).
>
> Aren't they better APIs to have hypervisors pass data to a kernel?

So a firmware interface *is* the intended situation here. To answer
your last question first: the "standard" firmware interface for
passing these seeds is via device tree's "rng-seed" field. There's
also a EFI protocol for this. And on x86 it can be passed through the
setup_data field. And on m68k the bootinfo bootloader/firmware struct
has a BI_RNG_SEED type. There's plenty of ARM and x86 hardware that
uses device tree and EFI for this, where the firmware is involved in
generating the seeds, and in the device tree case, in mangling the
device tree to have the right values. So, to answer your first
question, yes I think this is indeed a firmware-style interface.

Right now this is obviously intended for QEMU (and other hypervisors)
to implement. Later I'm hoping that firmware environments like CFE
might gain support for setting this. (You could do so interactively
now with "setenv".) So it seems like the environment block here really
is the right way to pass this. If you have a MIPS/malta platform
alternative, I'd be happy to consider it with you, but in my look at
things so far, the fw env block seems like by far the best way of
doing this, especially so considering it's part of both real firmware
environments and QEMU, and is relatively straightforward to implement.

Jason



Re: [PATCH v3] virtio-scsi: Send "REPORTED LUNS CHANGED" sense data upon disk hotplug events.

2022-10-03 Thread Venu Busireddy
On 2022-09-30 18:25:48 +0200, Paolo Bonzini wrote:
> On Fri, Sep 30, 2022 at 4:42 PM Venu Busireddy
>  wrote:
> > > > Immediately after a hotunplug event, qemu (without any action from
> > > > the guest) processes a REPORT_LUNS command on the lun 0 of the device
> > > > (haven't figured out what causes this).
> > >
> > > There is only one call to virtio_scsi_handle_cmd_req_prepare and it
> > > takes the command from the guest, are you sure it is without any
> > > action from the guest?
> >
> > I am sure, based on what I am observing. I am running the scsitrace
> > (scsitrace -n vtioscsi -v) command on the Solaris guest, and I see no
> > output there.
> 
> Do you have the sources to the driver and/or to the scsitrace dtrace

I do not have access to the source code. I am working on gaining access.

> script? Something must be putting the SCSI command in the queue.
> Perhaps the driver is doing so when it sees an event? And if it is
> bypassing the normal submission mechanism, the REPORT LUNS commands is
> hidden in scsitrac; that in turn retruns a unit attention and steals

While SAM does say "if a REPORT LUNS command enters the enabled command
state, the device server shall process the REPORT LUNS command and shall
not report any unit attention condition;," it also says that the unit
attention condition will not be cleared if the UA_INTLCK_CTRL is set to
10b or 11b in the "Control mode page."

It doesn't appear to me that virtio-scsi supports "Control mode pages."
Does it? If it doesn't, is the expected handling of REPORT LUNS command
be same as the case of UA_INTLCK_CTRL being set to 00b?

And while trying to understand this, and reading the code regarding
the handling of UA_INTLCK_CTRL, I ran across the following comment in
scsi_req_get_sense():

/*
 * FIXME: clearing unit attention conditions upon autosense should be done
 * only if the UA_INTLCK_CTRL field in the Control mode page is set to 00b
 * (SAM-5, 5.14).
 *
 * We assume UA_INTLCK_CTRL to be 00b for HBAs that support autosense, and
 * 10b for HBAs that do not support it (do not call scsi_req_get_sense).
 * Here we handle unit attention clearing for UA_INTLCK_CTRL == 00b.
 */

If virtio-scsi doesn't support "Control mode pages," why does the above
comment even say "assume UA_INTLCK_CTRL to be 00b" or address the case
of 10b? Also, other than the reference to it in the above comment,
UA_INTLCK_CTRL is not used anywhere else in the code. This comment
confused me. Is the comment just wrong, or am I missing something? I am
just trying to understand this better so that I am better prepared when
the client driver folks start asking me questions about the qemu support.

Venu

> it from the other commands such as TEST UNIT READY, but that's a guest
> driver bug.
> 
> But QEMU cannot just return the unit attention twice. I would start
> with the patch to use the bus unit attention mechanism. It would be
> even better to have two unit tests that check the behavior prescribed
> by the standard: 1) UNIT ATTENTION from TEST UNIT READY immediately
> after a hotunplug notification; 2) no UNIT ATTENTION from REPORT LUNS
> and also no UNIT ATTENTION from a subsequent TEST UNIT READY command.
> Debugging the guest is a separate step.



Re: [PULL 00/18] Block layer patches

2022-10-03 Thread Stefan Hajnoczi
Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any 
user-visible changes.


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Re: [PULL 00/10] target-arm queue

2022-10-03 Thread Stefan Hajnoczi
Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any 
user-visible changes.


signature.asc
Description: PGP signature


Re: [PULL 0/8] chardev patches

2022-10-03 Thread Stefan Hajnoczi
Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any 
user-visible changes.


signature.asc
Description: PGP signature


Re: [Virtio-fs] virtiofsd: Any reason why there's not an "openat2" sandbox mode?

2022-10-03 Thread Colin Walters



On Thu, Sep 29, 2022, at 1:03 PM, Vivek Goyal wrote:
> 
> So rust version of virtiofsd, already supports running unprivileged
> (inside a user namespace).

I know, but as I already said, the use case here is running inside an OpenShift 
unprivileged pod where *we are already in a container*.

> host$ podman unshare -- virtiofsd --socket-path=/tmp/vfsd.sock 
> --shared-dir /mnt \
> --announce-submounts --sandbox chroot &

Yes, but in current OCP 4.11 our seccomp policy denies CLONE_NEWUSER:

```
$ unshare -m
unshare: unshare failed: Function not implemented
```

https://docs.openshift.com/container-platform/4.11/security/seccomp-profiles.html

> I think only privileged operation it needs is assigning a range of
> subuid/subgid to the uid you are using on host.

We also turn on NO_NEW_PRIVILEGES by default in OCP pods.  

Now, I *could* in general get elevated permissions where I need to today.  But 
it's also really important to me to have a long term goal of having operating 
system builds and tests work well as "just another workload" in our production 
container platform (now, one *does* want to bind in /dev/kvm, but that's 
generally safe, and even that strictly speaking is optional if one can stomach 
the ~10x perf hit).

> Can you give rust virtiofsd (unprivileged) a try.

I admit to not actually trying it in a pod, but I think we all agree it can't 
work, and the only thing that can today is openat2.



Re: [PATCH v2] mips/malta: pass RNG seed to to kernel via env var

2022-10-03 Thread Philippe Mathieu-Daudé via

Hi Jason,

Per 
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#when-resending-patches-add-a-version-tag:


Send each new revision as a new top-level thread, rather than burying it 
in-reply-to an earlier revision, as many reviewers are not looking 
inside deep threads for new patches.


On 3/10/22 12:36, Jason A. Donenfeld wrote:

As of the kernel commit linked below, Linux ingests an RNG seed
passed from the hypervisor. So, pass this for the Malta platform, and
reinitialize it on reboot too, so that it's always fresh.

>

Cc: Philippe Mathieu-Daudé 
Cc: Jiaxun Yang 
Cc: Aurelien Jarno 
Link: https://git.kernel.org/mips/c/056a68cea01


You seem to justify this commit by the kernel commit, which justifies
itself mentioning hypervisor use... So the egg comes first before the
chicken.


Signed-off-by: Jason A. Donenfeld 
---
Changes v1->v2:
- Update commit message.
- No code changes.

  hw/mips/malta.c | 25 +
  1 file changed, 25 insertions(+)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 0e932988e0..9d793b3c17 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -26,6 +26,7 @@
  #include "qemu/units.h"
  #include "qemu/bitops.h"
  #include "qemu/datadir.h"
+#include "qemu/guest-random.h"
  #include "hw/clock.h"
  #include "hw/southbridge/piix.h"
  #include "hw/isa/superio.h"
@@ -1017,6 +1018,17 @@ static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t 
*prom_buf, int index,
  va_end(ap);
  }
  
+static void reinitialize_rng_seed(void *opaque)

+{
+char *rng_seed_hex = opaque;
+uint8_t rng_seed[32];
+
+qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
+for (size_t i = 0; i < sizeof(rng_seed); ++i) {
+sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]);
+}
+}
+
  /* Kernel */
  static uint64_t load_kernel(void)
  {
@@ -1028,6 +1040,8 @@ static uint64_t load_kernel(void)
  long prom_size;
  int prom_index = 0;
  uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr);
+uint8_t rng_seed[32];
+char rng_seed_hex[sizeof(rng_seed) * 2 + 1];
  
  #if TARGET_BIG_ENDIAN

  big_endian = 1;
@@ -1115,9 +1129,20 @@ static uint64_t load_kernel(void)
  
  prom_set(prom_buf, prom_index++, "modetty0");

  prom_set(prom_buf, prom_index++, "38400n8r");
+
+qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
+for (size_t i = 0; i < sizeof(rng_seed); ++i) {
+sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]);
+}
+prom_set(prom_buf, prom_index++, "rngseed");
+prom_set(prom_buf, prom_index++, "%s", rng_seed_hex);


You use the firmware interface to pass rng data to an hypervisor...

Look to me you are forcing one API to ease another one. From the
FW PoV it is a lie, because the FW will only change this value if
an operator is involved. Here PROM stands for "programmable read-only
memory", rarely modified. Having the 'rngseed' updated on each
reset is surprising.

Do you have an example of firmware doing that? (So I can understand
whether this is the best way to mimic this behavior here).

Aren't they better APIs to have hypervisors pass data to a kernel?

Regards,

Phil.


  prom_set(prom_buf, prom_index++, NULL);
  
  rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR);

+qemu_register_reset(reinitialize_rng_seed,
+memmem(rom_ptr(ENVP_PADDR, prom_size), prom_size,
+   rng_seed_hex, sizeof(rng_seed_hex)));
  
  g_free(prom_buf);

  return kernel_entry;





[PULL 1/8] hw/virtio/vhost-shadow-virtqueue: Silence GCC error "maybe-uninitialized"

2022-10-03 Thread Laurent Vivier
From: Bernhard Beschow 

GCC issues a false positive warning, resulting in build failure with -Werror:

  In file included from /usr/include/glib-2.0/glib.h:114,
   from src/include/glib-compat.h:32,
   from src/include/qemu/osdep.h:144,
   from ../src/hw/virtio/vhost-shadow-virtqueue.c:10:
  In function ‘g_autoptr_cleanup_generic_gfree’,
  inlined from ‘vhost_handle_guest_kick’ at 
../src/hw/virtio/vhost-shadow-virtqueue.c:292:42:
  /usr/include/glib-2.0/glib/glib-autocleanups.h:28:3: error: ‘elem’ may be 
used uninitialized [-Werror=maybe-uninitialized]
 28 |   g_free (*pp);
|   ^~~~
  ../src/hw/virtio/vhost-shadow-virtqueue.c: In function 
‘vhost_handle_guest_kick’:
  ../src/hw/virtio/vhost-shadow-virtqueue.c:292:42: note: ‘elem’ was declared 
here
292 | g_autofree VirtQueueElement *elem;
|  ^~~~
  cc1: all warnings being treated as errors

There is actually no problem since "elem" is initialized in both branches.
Silence the warning by initializig it with "NULL".

$ gcc --version
gcc (GCC) 12.2.0

Fixes: 9c2ab2f1ec333be8614cc12272d4b91960704dbe ("vhost: stop transfer elem 
ownership in vhost_handle_guest_kick")
Signed-off-by: Bernhard Beschow 
Reviewed-by: Richard Henderson 
Reviewed-by: Philippe Mathieu-Daudé 
Message-Id: <20220910151117.6665-1-shen...@gmail.com>
Signed-off-by: Laurent Vivier 
---
 hw/virtio/vhost-shadow-virtqueue.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/virtio/vhost-shadow-virtqueue.c 
b/hw/virtio/vhost-shadow-virtqueue.c
index e8e5bbc368dd..596d4434d289 100644
--- a/hw/virtio/vhost-shadow-virtqueue.c
+++ b/hw/virtio/vhost-shadow-virtqueue.c
@@ -289,7 +289,7 @@ static void vhost_handle_guest_kick(VhostShadowVirtqueue 
*svq)
 virtio_queue_set_notification(svq->vq, false);
 
 while (true) {
-g_autofree VirtQueueElement *elem;
+g_autofree VirtQueueElement *elem = NULL;
 int r;
 
 if (svq->next_guest_avail_elem) {
-- 
2.37.3




Re: [PULL 0/8] Trivial branch for 7.2 patches

2022-10-03 Thread Laurent Vivier

Le 03/10/2022 à 21:04, Stefan Hajnoczi a écrit :

On Fri, 30 Sept 2022 at 16:22, Laurent Vivier  wrote:

Philippe Mathieu-Daudé via (1):
   block/qcow2-bitmap: Add missing cast to silent GCC error


Hi Laurent,
This commit uses a mailing list email, probably due to DKIM/SPF issues:
Author: Philippe Mathieu-Daudé via 

I think the policy is to reject such pull requests and fix the
authorship. Could you update your pull request and resend?



Thank you Stefan.

Normally I have a pre-publish-send-email to check that, but it didn't fail in 
the expected way...

I re-send the PR.

Laurent



Re: [PATCH v3 4/5] hw/arm/virt: Improve high memory region address assignment

2022-10-03 Thread Gavin Shan

Hi Eric,

On 10/3/22 4:44 PM, Eric Auger wrote:

On 9/29/22 01:37, Gavin Shan wrote:

On 9/28/22 10:51 PM, Eric Auger wrote:

On 9/22/22 01:13, Gavin Shan wrote:

There are three high memory regions, which are VIRT_HIGH_REDIST2,
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
are floating on highest RAM address. However, they can be disabled
in several cases.

(1) One specific high memory region is disabled by developer by
  toggling vms->highmem_{redists, ecam, mmio}.

(2) VIRT_HIGH_PCIE_ECAM region is disabled on machine, which is
  'virt-2.12' or ealier than it.

(3) VIRT_HIGH_PCIE_ECAM region is disabled when firmware is loaded
  on 32-bits system.

(4) One specific high memory region is disabled when it breaks the
  PA space limit.

The current implementation of virt_set_memmap() isn't comprehensive
because the space for one specific high memory region is always
reserved from the PA space for case (1), (2) and (3). In the code,
'base' and 'vms->highest_gpa' are always increased for those three
cases. It's unnecessary since the assigned space of the disabled
high memory region won't be used afterwards.

This improves the address assignment for those three high memory
region by skipping the address assignment for one specific high
memory region if it has been disabled in case (1), (2) and (3).

Signed-off-by: Gavin Shan 
---
   hw/arm/virt.c | 44 ++--
   1 file changed, 26 insertions(+), 18 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index b0b679d1f4..b702f8f2b5 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1693,15 +1693,31 @@ static void
virt_set_high_memmap(VirtMachineState *vms,
    hwaddr base, int pa_bits)
   {
   hwaddr region_base, region_size;
-    bool fits;
+    bool *region_enabled, fits;

IDo you really need a pointer? If the region is unknown this is a bug in
virt code.


The pointer is needed so that we can disable the region by setting
'false'
to it at later point. Yeah, I think you're correct that 'unknown region'
is a bug and we need to do assert(region_enabled), or something like
below.

Yeah I don't think using a pointer here is useful.


When the high memory region can't fit into the PA space, it is disabled
by toggling the corresponding flag (vms->highmem_{redists, ecam, mmio})
to false. It's part of the original implementation, as below. We either
need a 'switch ... case' or a pointer. A pointer is more convenient since
we need check and possibly update to the value.

   switch (i) {
case VIRT_HIGH_GIC_REDIST2:
vms->highmem_redists &= fits;
break;
case VIRT_HIGH_PCIE_ECAM:
vms->highmem_ecam &= fits;
break;
case VIRT_HIGH_PCIE_MMIO:
vms->highmem_mmio &= fits;
break;
}




   int i;
     for (i = VIRT_LOWMEMMAP_LAST; i <
ARRAY_SIZE(extended_memmap); i++) {
   region_base = ROUND_UP(base, extended_memmap[i].size);
   region_size = extended_memmap[i].size;
   -    vms->memmap[i].base = region_base;
-    vms->memmap[i].size = region_size;
+    switch (i) {
+    case VIRT_HIGH_GIC_REDIST2:
+    region_enabled = >highmem_redists;
+    break;
+    case VIRT_HIGH_PCIE_ECAM:
+    region_enabled = >highmem_ecam;
+    break;
+    case VIRT_HIGH_PCIE_MMIO:
+    region_enabled = >highmem_mmio;
+    break;

While we are at it I would change the vms fields dealing with those
highmem regions and turn those fields into an array of bool indexed
using i - VIRT_LOWMEMMAP_LAST (using a macro or something alike). We
would not be obliged to have this switch, now duplicated.


It makes sense to me. How about to have something like below in v4?

static inline bool *virt_get_high_memmap_enabled(VirtMachineState
*vms, int index)
{
     bool *enabled_array[] = {
   >highmem_redists,
   >highmem_ecam,
   >highmem_mmio,
     };

     assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));

     return enabled_array[index - VIRT_LOWMEMMAP_LAST];
}

I was rather thinking as directly using a vms->highmem_flags[] but your
proposal may work as well.


Ok. I will use my proposed change in next revision.




+    default:
+    region_enabled = NULL;
+    }
+
+    /* Skip unknown region */
+    if (!region_enabled) {
+    continue;
+    }
     /*
    * Check each device to see if they fit in the PA space,
@@ -1710,23 +1726,15 @@ static void
virt_set_high_memmap(VirtMachineState *vms,
    * For each device that doesn't fit, disable it.
    */
   fits = (region_base + region_size) <= BIT_ULL(pa_bits);
-    if (fits) {
-    vms->highest_gpa = region_base + region_size - 1;
-    }
+    if (*region_enabled && fits) {
+    vms->memmap[i].base = region_base;
+  

Re: [PATCH 03/10] mac_{old|new}world: Set default values for some local variables

2022-10-03 Thread BALATON Zoltan

On Thu, 29 Sep 2022, Mark Cave-Ayland wrote:

On 25/09/2022 10:16, BALATON Zoltan wrote:

On Sun, 25 Sep 2022, Mark Cave-Ayland wrote:

On 17/09/2022 00:07, BALATON Zoltan wrote:

Some lines can be dropped making the code flow simpler and easier to
follow by setting default values at variable declaration for some
variables in both mac_oldworld.c and mac_newworld.c.

Signed-off-by: BALATON Zoltan 
---
  hw/ppc/mac_newworld.c | 28 +---
  hw/ppc/mac_oldworld.c | 27 +--
  2 files changed, 10 insertions(+), 45 deletions(-)

diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 27e4e8d136..6bc3bd19be 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -111,11 +111,11 @@ static void ppc_core99_init(MachineState *machine)
  CPUPPCState *env = NULL;
  char *filename;
  IrqLines *openpic_irqs;
-    int i, j, k, ppc_boot_device, machine_arch, bios_size;
+    int i, j, k, ppc_boot_device, machine_arch, bios_size = -1;
  const char *bios_name = machine->firmware ?: PROM_FILENAME;
  MemoryRegion *bios = g_new(MemoryRegion, 1);
-    hwaddr kernel_base, initrd_base, cmdline_base = 0;
-    long kernel_size, initrd_size;
+    hwaddr kernel_base = 0, initrd_base = 0, cmdline_base = 0;
+    long kernel_size = 0, initrd_size = 0;
  UNINHostState *uninorth_pci;
  PCIBus *pci_bus;
  PCIDevice *macio;
@@ -130,7 +130,7 @@ static void ppc_core99_init(MachineState *machine)
  DeviceState *dev, *pic_dev;
  DeviceState *uninorth_internal_dev = NULL, *uninorth_agp_dev = 
NULL;

  hwaddr nvram_addr = 0xFFF04000;
-    uint64_t tbfreq;
+    uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ;
    /* init CPUs */
  for (i = 0; i < machine->smp.cpus; i++) {
@@ -165,8 +165,6 @@ static void ppc_core99_init(MachineState *machine)
  bios_size = load_image_targphys(filename, PROM_BASE, 
PROM_SIZE);

  }
  g_free(filename);
-    } else {
-    bios_size = -1;
  }
  if (bios_size < 0 || bios_size > PROM_SIZE) {
  error_report("could not load PowerPC bios '%s'", bios_name);
@@ -174,15 +172,12 @@ static void ppc_core99_init(MachineState *machine)
  }
    if (machine->kernel_filename) {
-    int bswap_needed;
+    int bswap_needed = 0;
    #ifdef BSWAP_NEEDED
  bswap_needed = 1;
-#else
-    bswap_needed = 0;
  #endif
  kernel_base = KERNEL_LOAD_ADDR;
-
  kernel_size = load_elf(machine->kernel_filename, NULL,
 translate_kernel_address, NULL, NULL, 
NULL,

 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
@@ -212,16 +207,10 @@ static void ppc_core99_init(MachineState *machine)
  }
  cmdline_base = TARGET_PAGE_ALIGN(initrd_base + 
initrd_size);

  } else {
-    initrd_base = 0;
-    initrd_size = 0;


This bit seems a bit odd...

  cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size 
+ KERNEL_GAP);

  }
  ppc_boot_device = 'm';
  } else {
-    kernel_base = 0;
-    kernel_size = 0;
-    initrd_base = 0;
-    initrd_size = 0;


and also here. The only reason I can think that someone would explicitly 
set these variables back to 0 would be if there are cases in the load_*() 
functions where non-zero values could be returned for failure. It's worth 
having a look to confirm this and see if this also needs some additional 
tweaks to the logic flow here.


They aren't set back to 0 but set here the first time. Nothing touches 
these variables before this if-else do this patch just moves the zero init 
to the variable declaration and only leaves the cases which set a value 
different than zero here which I think is easier to follow.


Okay - in that case if you can test with a non-kernel ELF to verify this, and 
add a note confirming that everything still works for the error paths then 
that will be fine.


I've originally added non-elf loading to be able to use -bios macrom.bin 
which I've now verified that it still works so this should be OK. I've 
also split this patch up to more parts for easier review in the later 
versions of the series but what it does is basically instead of


int x;
if (cond) {
  x = a;
} else {
  x = 0;
}

we do

int x = 0;
if (cond) {
  x = a;
}

which I thought would be simple to review.

Regards,
BALATON Zoltan

[PULL 0/8] Trivial branch for 7.2 patches

2022-10-03 Thread Laurent Vivier
The following changes since commit c8de6ec63d766ca1998c5af468483ce912fdc0c2:

  Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into 
staging (2022-09-28 17:04:11 -0400)

are available in the Git repository at:

  https://gitlab.com/laurent_vivier/qemu.git 
tags/trivial-branch-for-7.2-pull-request

for you to fetch changes up to 4a4a74bf439910e957db42405a3abefdf867516a:

  docs: Update TPM documentation for usage of a TPM 2 (2022-10-04 00:10:11 
+0200)


Pull request trivial patches branch 20220930-v2



Bernhard Beschow (1):
  hw/virtio/vhost-shadow-virtqueue: Silence GCC error
"maybe-uninitialized"

Markus Armbruster (2):
  Drop superfluous conditionals around g_free()
  Use g_new() & friends where that makes obvious sense

Matheus Tavares Bernardino (1):
  checkpatch: ignore target/hexagon/imported/* files

Philippe Mathieu-Daudé (1):
  block/qcow2-bitmap: Add missing cast to silent GCC error

Stefan Berger (1):
  docs: Update TPM documentation for usage of a TPM 2

Tong Zhang (1):
  mem/cxl_type3: fix GPF DVSEC

Wang, Lei (1):
  .gitignore: add .cache/ to .gitignore

 .gitignore |  1 +
 block/qcow2-bitmap.c   |  2 +-
 docs/specs/tpm.rst | 44 --
 hw/mem/cxl_type3.c |  2 +-
 hw/remote/iommu.c  |  2 +-
 hw/virtio/vhost-shadow-virtqueue.c |  2 +-
 hw/virtio/virtio-crypto.c  |  2 +-
 migration/dirtyrate.c  |  4 +--
 replay/replay.c|  6 ++--
 scripts/checkpatch.pl  |  1 +
 softmmu/dirtylimit.c   |  4 +--
 target/i386/kvm/kvm.c  | 12 +++-
 target/i386/whpx/whpx-all.c| 14 --
 13 files changed, 47 insertions(+), 49 deletions(-)

-- 
2.37.3




Re: [PATCH v2 07/13] hw/ppc/e500: Remove if statement which is now always true

2022-10-03 Thread Philippe Mathieu-Daudé via

On 3/10/22 22:31, Bernhard Beschow wrote:

Now that the MPC8544DS board also has a platform bus, the if statement
is always true.

Signed-off-by: Bernhard Beschow 
Reviewed-by: Bin Meng 
Reviewed-by: Philippe Mathieu-Daudé 
---
  hw/ppc/e500.c  | 30 ++
  hw/ppc/e500.h  |  1 -
  hw/ppc/e500plat.c  |  1 -
  hw/ppc/mpc8544ds.c |  1 -
  4 files changed, 14 insertions(+), 19 deletions(-)



  /* Platform Bus Device */
-if (pmc->has_platform_bus) {
-dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
-dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
-qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
-qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
-sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
-pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
-
-s = SYS_BUS_DEVICE(pms->pbus_dev);
-for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
-int irqn = pmc->platform_bus_first_irq + i;
-sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
-}
+dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
+dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
+qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
+qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);


Should we abort(pmc->platform_bus_size > 0) now?


+pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
  
-memory_region_add_subregion(address_space_mem,

-pmc->platform_bus_base,
->pbus_dev->mmio);
+s = SYS_BUS_DEVICE(pms->pbus_dev);
+for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
+int irqn = pmc->platform_bus_first_irq + i;
+sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
  }
  
+memory_region_add_subregion(address_space_mem,

+pmc->platform_bus_base,
+>pbus_dev->mmio);




Re: ublk-qcow2: ublk-qcow2 is available

2022-10-03 Thread Stefan Hajnoczi
On Fri, Sep 30, 2022 at 05:24:11PM +0800, Ming Lei wrote:
> ublk-qcow2 is available now.

Cool, thanks for sharing!

> 
> So far it provides basic read/write function, and compression and snapshot
> aren't supported yet. The target/backend implementation is completely
> based on io_uring, and share the same io_uring with ublk IO command
> handler, just like what ublk-loop does.
> 
> Follows the main motivations of ublk-qcow2:
> 
> - building one complicated target from scratch helps libublksrv APIs/functions
>   become mature/stable more quickly, since qcow2 is complicated and needs more
>   requirement from libublksrv compared with other simple ones(loop, null)
> 
> - there are several attempts of implementing qcow2 driver in kernel, such as
>   ``qloop`` [2], ``dm-qcow2`` [3] and ``in kernel qcow2(ro)`` [4], so 
> ublk-qcow2
>   might useful be for covering requirement in this field
> 
> - performance comparison with qemu-nbd, and it was my 1st thought to evaluate
>   performance of ublk/io_uring backend by writing one ublk-qcow2 since ublksrv
>   is started
> 
> - help to abstract common building block or design pattern for writing new 
> ublk
>   target/backend
> 
> So far it basically passes xfstest(XFS) test by using ublk-qcow2 block
> device as TEST_DEV, and kernel building workload is verified too. Also
> soft update approach is applied in meta flushing, and meta data
> integrity is guaranteed, 'make test T=qcow2/040' covers this kind of
> test, and only cluster leak is reported during this test.
> 
> The performance data looks much better compared with qemu-nbd, see
> details in commit log[1], README[5] and STATUS[6]. And the test covers both
> empty image and pre-allocated image, for example of pre-allocated qcow2
> image(8GB):
> 
> - qemu-nbd (make test T=qcow2/002)

Single queue?

>   randwrite(4k): jobs 1, iops 24605
>   randread(4k): jobs 1, iops 30938
>   randrw(4k): jobs 1, iops read 13981 write 14001
>   rw(512k): jobs 1, iops read 724 write 728

Please try qemu-storage-daemon's VDUSE export type as well. The
command-line should be similar to this:

  # modprobe virtio_vdpa # attaches vDPA devices to host kernel
  # modprobe vduse
  # qemu-storage-daemon \
  --blockdev 
file,filename=test.qcow2,cache.direct=of|off,aio=native,node-name=file \
  --blockdev qcow2,file=file,node-name=qcow2 \
  --object iothread,id=iothread0 \
  --export 
vduse-blk,id=vduse0,name=vduse0,num-queues=$(nproc),node-name=qcow2,writable=on,iothread=iothread0
  # vdpa dev add name vduse0 mgmtdev vduse

A virtio-blk device should appear and xfstests can be run on it
(typically /dev/vda unless you already have other virtio-blk devices).

Afterwards you can destroy the device using:

  # vdpa dev del vduse0

> 
> - ublk-qcow2 (make test T=qcow2/022)

There are a lot of other factors not directly related to NBD vs ublk. In
order to get an apples-to-apples comparison with qemu-* a ublk export
type is needed in qemu-storage-daemon. That way only the difference is
the ublk interface and the rest of the code path is identical, making it
possible to compare NBD, VDUSE, ublk, etc more precisely.

I think that comparison is interesting before comparing different qcow2
implementations because qcow2 sits on top of too much other code. It's
hard to know what should be accounted to configuration differences,
implementation differences, or fundamental differences that cannot be
overcome (this is the interesting part!).

>   randwrite(4k): jobs 1, iops 104481
>   randread(4k): jobs 1, iops 114937
>   randrw(4k): jobs 1, iops read 53630 write 53577
>   rw(512k): jobs 1, iops read 1412 write 1423
> 
> Also ublk-qcow2 aligns queue's chunk_sectors limit with qcow2's cluster size,
> which is 64KB at default, this way simplifies backend io handling, but
> it could be increased to 512K or more proper size for improving sequential
> IO perf, just need one coroutine to handle more than one IOs.
> 
> 
> [1] 
> https://github.com/ming1/ubdsrv/commit/9faabbec3a92ca83ddae92335c66eabbeff654e7
> [2] 
> https://upcommons.upc.edu/bitstream/handle/2099.1/9619/65757.pdf?sequence=1=y
> [3] https://lwn.net/Articles/889429/
> [4] https://lab.ks.uni-freiburg.de/projects/kernel-qcow2/repository
> [5] https://github.com/ming1/ubdsrv/blob/master/qcow2/README.rst
> [6] https://github.com/ming1/ubdsrv/blob/master/qcow2/STATUS.rst
> 
> Thanks,
> Ming
> 


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Re: [PATCH v2 12/13] hw/sd/sdhci: Implement Freescale eSDHC device model

2022-10-03 Thread Philippe Mathieu-Daudé via

On 3/10/22 22:31, Bernhard Beschow wrote:

Will allow e500 boards to access SD cards using just their own devices.

Signed-off-by: Bernhard Beschow 
---
  hw/sd/sdhci.c | 147 +-
  include/hw/sd/sdhci.h |   3 +
  2 files changed, 149 insertions(+), 1 deletion(-)



+/* --- qdev Freescale eSDHC --- */
+
+/* Watermark Level Register */
+#define ESDHC_WML0x44
+
+/* Host Controller Capabilities Register 2 */
+#define ESDHC_CAPABILITIES_10x114


Not used?


+
+/* Control Register for DMA transfer */
+#define ESDHC_DMA_SYSCTL0x40c
+
+#define ESDHC_REGISTERS_MAP_SIZE0x410
+
+static uint64_t esdhci_read(void *opaque, hwaddr offset, unsigned size)
+{
+uint64_t ret;
+
+if (size != 4) {
+qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
+  " wrong size\n", size, offset);
+return 0;
+}
+
+if (offset & 0x3) {
+qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
+  " unaligned\n", size, offset);
+return 0;


Isn't it already enforced by esdhc_mmio_ops.valid.unaligned = false?


+}
+
+switch (offset) {
+case SDHC_SYSAD:
+case SDHC_BLKSIZE:
+case SDHC_ARGUMENT:
+case SDHC_TRNMOD:
+case SDHC_RSPREG0:
+case SDHC_RSPREG1:
+case SDHC_RSPREG2:
+case SDHC_RSPREG3:
+case SDHC_BDATA:
+case SDHC_PRNSTS:
+case SDHC_HOSTCTL:
+case SDHC_CLKCON:
+case SDHC_NORINTSTS:
+case SDHC_NORINTSTSEN:
+case SDHC_NORINTSIGEN:
+case SDHC_ACMD12ERRSTS:
+case SDHC_CAPAB:
+case SDHC_SLOT_INT_STATUS:
+ret = sdhci_read(opaque, offset, size);
+break;
+
+case ESDHC_WML:
+case ESDHC_DMA_SYSCTL:
+ret = 0;
+qemu_log_mask(LOG_UNIMP, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
+  " not implemented\n", size, offset);
+break;
+
+default:
+ret = 0;
+qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
+  " unknown offset\n", size, offset);
+break;
+}
+
+return ret;
+}
+
+static void esdhci_write(void *opaque, hwaddr offset, uint64_t val,
+ unsigned size)
+{
+if (size != 4) {
+qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx
+  " <- 0x%08lx wrong size\n", size, offset, val);
+return;
+}
+
+if (offset & 0x3) {
+qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx
+  " <- 0x%08lx unaligned\n", size, offset, val);
+return;
+}
+
+switch (offset) {
+case SDHC_SYSAD:
+case SDHC_BLKSIZE:
+case SDHC_ARGUMENT:
+case SDHC_TRNMOD:
+case SDHC_BDATA:
+case SDHC_HOSTCTL:
+case SDHC_CLKCON:
+case SDHC_NORINTSTS:
+case SDHC_NORINTSTSEN:
+case SDHC_NORINTSIGEN:
+case SDHC_FEAER:
+sdhci_write(opaque, offset, val, size);
+break;
+
+case ESDHC_WML:
+case ESDHC_DMA_SYSCTL:
+qemu_log_mask(LOG_UNIMP, "ESDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08lx 
"
+  "not implemented\n", size, offset, val);
+break;
+
+default:
+qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx
+  " <- 0x%08lx unknown offset\n", size, offset, val);
+break;
+}
+}
+
+static const MemoryRegionOps esdhc_mmio_ops = {
+.read = esdhci_read,
+.write = esdhci_write,
+.valid = {
+.min_access_size = 1,
+.max_access_size = 4,
+.unaligned = false
+},
+.endianness = DEVICE_BIG_ENDIAN,
+};




Re: [RFC 3/7] migration: Block migration comment or code is wrong

2022-10-03 Thread Stefan Hajnoczi
On Mon, Oct 03, 2022 at 05:15:56AM +0200, Juan Quintela wrote:
> And it appears that what is wrong is the code. During bulk stage we
> need to make sure that some block is dirty, but no games with
> max_size at all.
> 
> Signed-off-by: Juan Quintela 
> ---
>  migration/block.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Stefan Hajnoczi 


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Re: [PATCH v2 13/13] hw/ppc/e500: Add Freescale eSDHC to e500 boards

2022-10-03 Thread Philippe Mathieu-Daudé via

On 3/10/22 22:31, Bernhard Beschow wrote:

Adds missing functionality to emulated e500 SOCs which increases the
chance of given "real" firmware images to access SD cards.

Signed-off-by: Bernhard Beschow 
---
  docs/system/ppc/ppce500.rst | 13 +
  hw/ppc/Kconfig  |  1 +
  hw/ppc/e500.c   | 31 ++-
  3 files changed, 44 insertions(+), 1 deletion(-)



+static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic)
+{
+hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET;
+hwaddr size = MPC85XX_ESDHC_REGS_SIZE;
+int irq = MPC85XX_ESDHC_IRQ;


Why not pass these 3 variable as argument?


+g_autofree char *name = NULL;
+
+name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio);
+qemu_fdt_add_subnode(fdt, name);
+qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0);
+qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic);
+qemu_fdt_setprop_cells(fdt, name, "bus-width", 4);
+qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2);
+qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size);
+qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc");
+}
  
  typedef struct PlatformDevtreeData {

  void *fdt;
@@ -553,6 +573,8 @@ static int ppce500_load_device_tree(PPCE500MachineState 
*pms,
  
  dt_rtc_create(fdt, "i2c", "rtc");
  
+/* sdhc */

+dt_sdhc_create(fdt, soc, mpic);
  




Re: [RFC PATCH v2 00/29] PowerPC interrupt rework

2022-10-03 Thread Cédric Le Goater

(qemu) info pic
info pic
CPU[]:   QW   NSR CPPR IPB LSMFB ACK# INC AGE PIPR  W2
CPU[]: USER    00   00  00    00   00  00  00   00  
CPU[]:   OS    00   00  00    ff   ff  00  ff   ff  
CPU[]: POOL    00   00  00    ff   00  00  00   00  
CPU[]: PHYS    00   ff  00    00   00  00  00   ff  8000
CPU[0001]:   QW   NSR CPPR IPB LSMFB ACK# INC AGE PIPR  W2
CPU[0001]: USER    00   00  00    00   00  00  00   00  
CPU[0001]:   OS    00   00  00    ff   ff  00  ff   ff  
CPU[0001]: POOL    00   00  00    ff   00  00  00   00  0001
CPU[0001]: PHYS    00   ff  00    00   00  00  00   ff  8000
CPU[0002]:   QW   NSR CPPR IPB LSMFB ACK# INC AGE PIPR  W2
CPU[0002]: USER    00   00  00    00   00  00  00   00  
CPU[0002]:   OS    00   00  00    ff   ff  00  ff   ff  
CPU[0002]: POOL    00   00  00    ff   00  00  00   00  0002
CPU[0002]: PHYS    00   ff  00    00   00  00  00   ff  8000
CPU[0003]:   QW   NSR CPPR IPB LSMFB ACK# INC AGE PIPR  W2
CPU[0003]: USER    00   00  00    00   00  00  00   00  
CPU[0003]:   OS    00   ff  00    00   ff  00  ff   ff  0004


vCPU 4 was scheduled to run on this CPU at some point, but it is not
anymore : no VALID bit.


CPU[0003]: POOL    00   00  00    ff   00  00  00   00  0003
CPU[0003]: PHYS    00   ff  00    00   00  00  00   ff  8000
XIVE[0] #0 Source  .. 000f
   0014 MSI --
   0015 MSI --
   0016 MSI --
   0017 MSI --
   0018 MSI --
   0019 MSI --
   001a MSI --
   001b MSI --
   001e MSI P-


The 0x1E HW interrupt (virtual device) is pending. And not queued.


   0023 MSI --
   0024 MSI --
   0025 MSI --
   0026 MSI --
XIVE[0] #0 EAT  .. 000f
   0014   end:00/000f data:0010
   0015   end:00/0017 data:0010
   0016   end:00/001f data:0010
   0017   end:00/0027 data:0010 -> 0x10 == CPU IPI 
   0018   end:00/004e data:0010 -> This is the vCPU IPI 
   0019   end:00/004e data:0012

   001a   end:00/004e data:001b
   001b   end:00/004e data:0013
   001e   end:00/004e data:0016


notificationd of 0x1E HW interrupts will be pushed on vCPU 0 queue 0x4e,
with (Linux) effective interrupt number 0x16, the console may be.


   0023   end:00/004e data:0017
   0024   end:00/004e data:0018
   0025   end:00/004e data:0019
   0026   end:00/004e data:001a


Follow the PHB interrupts, MSI and LSIs.


   000fb000   end:00/001f data:0030
   000fb001   end:00/0027 data:0031
   000fb002   end:00/000f data:0032
   000fb003   end:00/000f data:0033
   000fb004   end:00/0017 data:0034
   000fb005   end:00/001f data:0035
   000fb006   end:00/0027 data:0036
   000fb7fe   end:00/000f data:0029
   000fb7ff   end:00/0017 data:002a
   000fbffe   end:00/001f data:0027
   000fbfff   end:00/0027 data:0028
   000fcffe   end:00/000f data:0025
   000fcfff   end:00/0017 data:0026
   000fd000   end:00/001f data:0037
   000fd001   end:00/000f data:0038
   000fd002   end:00/0017 data:0039
   000fd003   end:00/001f data:003a
   000fd004   end:00/0027 data:003b
   000fd7fe   end:00/001f data:0023
   000fd7ff   end:00/0027 data:0024
   000fdffe   end:00/000f data:0021
   000fdfff   end:00/0017 data:0022
   000feffe   end:00/001f data:001f
   000fefff   end:00/0027 data:0020


opal events are after

   0000   end:00/000f data:0011 
   0001   end:00/0017 data:0012
   0002   end:00/001f data:0013 
   0003   end:00/0027 data:0014 # opal-psi#0:lpchc

   0004   end:00/000f data:0015
   0005   end:00/0017 data:0016
   0006   end:00/001f data:0017
   0007   end:00/0027 data:0018
   0008   end:00/000f data:0019
   0009   end:00/0017 data:001a
   000a   end:00/001f data:001b
   000b   end:00/0027 data:001c
   000c   end:00/000f data:001d
   000d   end:00/0017 data:001e # opal-psi#0:psu ? 
XIVE[0] #0 ENDT

   000f -Q vqnb---f prio:7 nvt:00/0080 eq:@0340   825/16384 ^1 [ 
804f 804f 804f 804f 804f ^ ]


event queue of host CPU 0 is filling up with escalation interrupt
numbers, 0x4f.

host CPU 0 (queue 0xf) is serving its own IPI, some MSIs, some EEH PCI
interrupts, and some OPAL events.


   0017 -Q vqnb---f prio:7 nvt:00/0084 eq:@0375  1048/16384 ^1 [ 
801e 801e 801e 801e 801e ^ ]


hmm, host CPU 1 is serving 0xd = opal-psi#0:psu. May be too much.


   001f -Q vqnb---f prio:7 nvt:00/0088 eq:@037f   154/16384 ^1 [ 
803a 803a 803a 803a 803a ^ ]


0x3a is an MSI.


   0027 -Q vqnb---f prio:7 nvt:00/008c eq:@038a   340/16384 ^1 [ 
8014 8014 8014 8014 803b ^ ]


This is the console 0x14 and 0x3b is 

Re: [PATCH v2 09/13] hw/ppc/e500: Implement pflash handling

2022-10-03 Thread Philippe Mathieu-Daudé via

On 3/10/22 22:31, Bernhard Beschow wrote:

Allows e500 boards to have their root file system reside on flash using
only builtin devices located in the eLBC memory region.

Note that the flash memory area is only created when a -pflash argument is
given, and that the size is determined by the given file. The idea is to
put users into control.

Signed-off-by: Bernhard Beschow 
---
  docs/system/ppc/ppce500.rst | 12 ++
  hw/ppc/Kconfig  |  1 +
  hw/ppc/e500.c   | 76 +
  3 files changed, 89 insertions(+)



@@ -856,6 +892,7 @@ void ppce500_init(MachineState *machine)
  unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
  IrqLines *irqs;
  DeviceState *dev, *mpicdev;
+DriveInfo *dinfo;
  CPUPPCState *firstenv = NULL;
  MemoryRegion *ccsr_addr_space;
  SysBusDevice *s;
@@ -1024,6 +1061,45 @@ void ppce500_init(MachineState *machine)
  pmc->platform_bus_base,
  >pbus_dev->mmio);
  
+dinfo = drive_get(IF_PFLASH, 0, 0);

+if (dinfo) {
+BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
+BlockDriverState *bs = blk_bs(blk);
+uint64_t size = bdrv_getlength(bs);
+uint64_t mmio_size = pms->pbus_dev->mmio.size;
+uint32_t sector_len = 64 * KiB;
+
+if (ctpop64(size) != 1) {
+error_report("Size of pflash file must be a power of two.");


This is a PFLASH restriction (which you already fixed in the previous
patch), not a board one.


+exit(1);
+}
+
+if (size > mmio_size) {
+error_report("Size of pflash file must not be bigger than %" PRIu64
+ " bytes.", mmio_size);


There is no hardware limitation here, you can wire flash bigger than the
memory aperture. What is above the aperture will simply be ignored.

Should we display a warning here instead of a fatal error?


+exit(1);
+}
+
+assert(QEMU_IS_ALIGNED(size, sector_len));


Similarly, this doesn't seem a problem the board code should worry
about: better to defer it to PFLASH realize().


+dev = qdev_new(TYPE_PFLASH_CFI01);
+qdev_prop_set_drive(dev, "drive", blk);
+qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
+qdev_prop_set_uint64(dev, "sector-length", sector_len);
+qdev_prop_set_uint8(dev, "width", 2);
+qdev_prop_set_bit(dev, "big-endian", true);
+qdev_prop_set_uint16(dev, "id0", 0x89);
+qdev_prop_set_uint16(dev, "id1", 0x18);
+qdev_prop_set_uint16(dev, "id2", 0x);
+qdev_prop_set_uint16(dev, "id3", 0x0);
+qdev_prop_set_string(dev, "name", "e500.flash");
+s = SYS_BUS_DEVICE(dev);
+sysbus_realize_and_unref(s, _fatal);
+
+memory_region_add_subregion(>pbus_dev->mmio, 0,
+sysbus_mmio_get_region(s, 0));
+}
+
  /*
   * Smart firmware defaults ahead!
   *





Re: [PATCH v2 00/13] ppc/e500: Add support for two types of flash, cleanup

2022-10-03 Thread Philippe Mathieu-Daudé via

Hi Daniel,

On 3/10/22 22:31, Bernhard Beschow wrote:

Cover letter:
~

This series adds support for -pflash and direct SD card access to the
PPC e500 boards. The idea is to increase compatibility with "real" firmware
images where only the bare minimum of drivers is compiled in.



Bernhard Beschow (13):
   hw/ppc/meson: Allow e500 boards to be enabled separately
   hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxx
   docs/system/ppc/ppce500: Add heading for networking chapter
   hw/ppc/e500: Reduce usage of sysbus API
   hw/ppc/mpc8544ds: Rename wrongly named method
   hw/ppc/mpc8544ds: Add platform bus
   hw/ppc/e500: Remove if statement which is now always true


This first part is mostly reviewed and can already go via your
ppc-next queue.


   hw/block/pflash_cfi01: Error out if device length isn't a power of two
   hw/ppc/e500: Implement pflash handling
   hw/sd/sdhci-internal: Unexport ESDHC defines
   hw/sd/sdhci: Rename ESDHC_* defines to USDHC_*
   hw/sd/sdhci: Implement Freescale eSDHC device model
   hw/ppc/e500: Add Freescale eSDHC to e500 boards


This second part still need work. I can take it via the sdmmc-next
queue.

Regards,

Phil.



Re: [PATCH v2 08/13] hw/block/pflash_cfi01: Error out if device length isn't a power of two

2022-10-03 Thread Philippe Mathieu-Daudé via

On 3/10/22 22:31, Bernhard Beschow wrote:

According to the JEDEC standard the device length is communicated to an
OS as an exponent (power of two).

Signed-off-by: Bernhard Beschow 
Reviewed-by: Bin Meng 
---
  hw/block/pflash_cfi01.c | 8 ++--
  1 file changed, 6 insertions(+), 2 deletions(-)


With CFI02 similarly fixed:
Reviewed-by: Philippe Mathieu-Daudé 



[PATCH v2 13/13] hw/ppc/e500: Add Freescale eSDHC to e500 boards

2022-10-03 Thread Bernhard Beschow
Adds missing functionality to emulated e500 SOCs which increases the
chance of given "real" firmware images to access SD cards.

Signed-off-by: Bernhard Beschow 
---
 docs/system/ppc/ppce500.rst | 13 +
 hw/ppc/Kconfig  |  1 +
 hw/ppc/e500.c   | 31 ++-
 3 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
index 1ed6c36599..c758aa51eb 100644
--- a/docs/system/ppc/ppce500.rst
+++ b/docs/system/ppc/ppce500.rst
@@ -19,6 +19,7 @@ The ``ppce500`` machine supports the following devices:
 * Power-off functionality via one GPIO pin
 * 1 Freescale MPC8xxx PCI host controller
 * VirtIO devices via PCI bus
+* 1 Freescale Enhanced Secure Digital Host controller (eSDHC)
 * 1 Freescale Enhanced Triple Speed Ethernet controller (eTSEC)
 
 Hardware configuration information
@@ -131,6 +132,18 @@ be used as follows:
   -drive if=pflash,file=/path/to/rootfs.ext2,format=raw \
   -append "rootwait root=/dev/mtdblock0"
 
+Alternatively, the root file system can also reside on an emulated SD card
+whose size must again be a power of two:
+
+.. code-block:: bash
+
+  $ qemu-system-ppc{64|32} -M ppce500 -cpu e500mc -smp 4 -m 2G \
+  -display none -serial stdio \
+  -kernel vmlinux \
+  -device sd-card,drive=mydrive \
+  -drive id=mydrive,if=none,file=/path/to/rootfs.ext2,format=raw \
+  -append "rootwait root=/dev/mmcblk0"
+
 Running U-Boot
 --
 
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 769a1ead1c..6e31f568ba 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -129,6 +129,7 @@ config E500
 select PFLASH_CFI01
 select PLATFORM_BUS
 select PPCE500_PCI
+select SDHCI
 select SERIAL
 select MPC_I2C
 select FDT_PPC
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 2b1430fca4..379d89bf2d 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -48,6 +48,7 @@
 #include "hw/net/fsl_etsec/etsec.h"
 #include "hw/i2c/i2c.h"
 #include "hw/irq.h"
+#include "hw/sd/sdhci.h"
 
 #define EPAPR_MAGIC(0x45504150)
 #define DTC_LOAD_PAD   0x180
@@ -66,11 +67,14 @@
 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
 #define MPC8544_PCI_REGS_OFFSET0x8000ULL
 #define MPC8544_PCI_REGS_SIZE  0x1000ULL
+#define MPC85XX_ESDHC_REGS_OFFSET  0x2e000ULL
+#define MPC85XX_ESDHC_REGS_SIZE0x1000ULL
 #define MPC8544_UTIL_OFFSET0xeULL
 #define MPC8XXX_GPIO_OFFSET0x000FF000ULL
 #define MPC8544_I2C_REGS_OFFSET0x3000ULL
 #define MPC8XXX_GPIO_IRQ   47
 #define MPC8544_I2C_IRQ43
+#define MPC85XX_ESDHC_IRQ  72
 #define RTC_REGS_OFFSET0x68
 
 #define PLATFORM_CLK_FREQ_HZ   (400 * 1000 * 1000)
@@ -203,6 +207,22 @@ static void dt_i2c_create(void *fdt, const char *soc, 
const char *mpic,
 g_free(i2c);
 }
 
+static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic)
+{
+hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET;
+hwaddr size = MPC85XX_ESDHC_REGS_SIZE;
+int irq = MPC85XX_ESDHC_IRQ;
+g_autofree char *name = NULL;
+
+name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio);
+qemu_fdt_add_subnode(fdt, name);
+qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0);
+qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic);
+qemu_fdt_setprop_cells(fdt, name, "bus-width", 4);
+qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2);
+qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size);
+qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc");
+}
 
 typedef struct PlatformDevtreeData {
 void *fdt;
@@ -553,6 +573,8 @@ static int ppce500_load_device_tree(PPCE500MachineState 
*pms,
 
 dt_rtc_create(fdt, "i2c", "rtc");
 
+/* sdhc */
+dt_sdhc_create(fdt, soc, mpic);
 
 gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
 MPC8544_UTIL_OFFSET);
@@ -982,7 +1004,8 @@ void ppce500_init(MachineState *machine)
0, qdev_get_gpio_in(mpicdev, 42), 399193,
serial_hd(1), DEVICE_BIG_ENDIAN);
 }
-/* I2C */
+
+/* I2C */
 dev = qdev_new("mpc-i2c");
 s = SYS_BUS_DEVICE(dev);
 sysbus_realize_and_unref(s, _fatal);
@@ -992,6 +1015,12 @@ void ppce500_init(MachineState *machine)
 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
 
+/* eSDHC */
+dev = qdev_new(TYPE_FSL_ESDHC);
+s = SYS_BUS_DEVICE(dev);
+sysbus_realize_and_unref(s, _fatal);
+sysbus_mmio_map(s, 0, pmc->ccsrbar_base + MPC85XX_ESDHC_REGS_OFFSET);
+sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ));
 
 /* General Utility device */
 dev = qdev_new("mpc8544-guts");
-- 
2.37.3




[PATCH v2 11/13] hw/sd/sdhci: Rename ESDHC_* defines to USDHC_*

2022-10-03 Thread Bernhard Beschow
The device model's functions start with "usdhc_", so rename the defines
accordingly for consistency.

Signed-off-by: Bernhard Beschow 
Reviewed-by: Bin Meng 
---
 hw/sd/sdhci.c | 66 +--
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 6da5e2c781..306070c872 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1577,24 +1577,24 @@ static const TypeInfo sdhci_bus_info = {
 
 /* --- qdev i.MX eSDHC --- */
 
-#define ESDHC_MIX_CTRL  0x48
+#define USDHC_MIX_CTRL  0x48
 
-#define ESDHC_VENDOR_SPEC   0xc0
-#define ESDHC_IMX_FRC_SDCLK_ON  (1 << 8)
+#define USDHC_VENDOR_SPEC   0xc0
+#define USDHC_IMX_FRC_SDCLK_ON  (1 << 8)
 
-#define ESDHC_DLL_CTRL  0x60
+#define USDHC_DLL_CTRL  0x60
 
-#define ESDHC_TUNING_CTRL   0xcc
-#define ESDHC_TUNE_CTRL_STATUS  0x68
-#define ESDHC_WTMK_LVL  0x44
+#define USDHC_TUNING_CTRL   0xcc
+#define USDHC_TUNE_CTRL_STATUS  0x68
+#define USDHC_WTMK_LVL  0x44
 
 /* Undocumented register used by guests working around erratum ERR004536 */
-#define ESDHC_UNDOCUMENTED_REG270x6c
+#define USDHC_UNDOCUMENTED_REG270x6c
 
-#define ESDHC_CTRL_4BITBUS  (0x1 << 1)
-#define ESDHC_CTRL_8BITBUS  (0x2 << 1)
+#define USDHC_CTRL_4BITBUS  (0x1 << 1)
+#define USDHC_CTRL_8BITBUS  (0x2 << 1)
 
-#define ESDHC_PRNSTS_SDSTB  (1 << 3)
+#define USDHC_PRNSTS_SDSTB  (1 << 3)
 
 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
 {
@@ -1615,11 +1615,11 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, 
unsigned size)
 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
 
 if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
-hostctl1 |= ESDHC_CTRL_8BITBUS;
+hostctl1 |= USDHC_CTRL_8BITBUS;
 }
 
 if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
-hostctl1 |= ESDHC_CTRL_4BITBUS;
+hostctl1 |= USDHC_CTRL_4BITBUS;
 }
 
 ret  = hostctl1;
@@ -1630,21 +1630,21 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, 
unsigned size)
 
 case SDHC_PRNSTS:
 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
-ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
+ret = sdhci_read(opaque, offset, size) & ~USDHC_PRNSTS_SDSTB;
 if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
-ret |= ESDHC_PRNSTS_SDSTB;
+ret |= USDHC_PRNSTS_SDSTB;
 }
 break;
 
-case ESDHC_VENDOR_SPEC:
+case USDHC_VENDOR_SPEC:
 ret = s->vendor_spec;
 break;
-case ESDHC_DLL_CTRL:
-case ESDHC_TUNE_CTRL_STATUS:
-case ESDHC_UNDOCUMENTED_REG27:
-case ESDHC_TUNING_CTRL:
-case ESDHC_MIX_CTRL:
-case ESDHC_WTMK_LVL:
+case USDHC_DLL_CTRL:
+case USDHC_TUNE_CTRL_STATUS:
+case USDHC_UNDOCUMENTED_REG27:
+case USDHC_TUNING_CTRL:
+case USDHC_MIX_CTRL:
+case USDHC_WTMK_LVL:
 ret = 0;
 break;
 }
@@ -1660,18 +1660,18 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, 
unsigned size)
 uint32_t value = (uint32_t)val;
 
 switch (offset) {
-case ESDHC_DLL_CTRL:
-case ESDHC_TUNE_CTRL_STATUS:
-case ESDHC_UNDOCUMENTED_REG27:
-case ESDHC_TUNING_CTRL:
-case ESDHC_WTMK_LVL:
+case USDHC_DLL_CTRL:
+case USDHC_TUNE_CTRL_STATUS:
+case USDHC_UNDOCUMENTED_REG27:
+case USDHC_TUNING_CTRL:
+case USDHC_WTMK_LVL:
 break;
 
-case ESDHC_VENDOR_SPEC:
+case USDHC_VENDOR_SPEC:
 s->vendor_spec = value;
 switch (s->vendor) {
 case SDHCI_VENDOR_IMX:
-if (value & ESDHC_IMX_FRC_SDCLK_ON) {
+if (value & USDHC_IMX_FRC_SDCLK_ON) {
 s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
 } else {
 s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
@@ -1740,12 +1740,12 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, 
unsigned size)
  * Second, split "Data Transfer Width" from bits 2 and 1 in to
  * bits 5 and 1
  */
-if (value & ESDHC_CTRL_8BITBUS) {
+if (value & USDHC_CTRL_8BITBUS) {
 hostctl1 |= SDHC_CTRL_8BITBUS;
 }
 
-if (value & ESDHC_CTRL_4BITBUS) {
-hostctl1 |= ESDHC_CTRL_4BITBUS;
+if (value & USDHC_CTRL_4BITBUS) {
+hostctl1 |= USDHC_CTRL_4BITBUS;
 }
 
 /*
@@ -1768,7 +1768,7 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, 
unsigned size)
 sdhci_write(opaque, offset, value, size);
 break;
 
-case ESDHC_MIX_CTRL:
+case USDHC_MIX_CTRL:
 /*
  * So, when SD/MMC stack in Linux tries to write to "Transfer
  * Mode Register", ESDHC i.MX quirk code will translate it
-- 
2.37.3




[PATCH v2 12/13] hw/sd/sdhci: Implement Freescale eSDHC device model

2022-10-03 Thread Bernhard Beschow
Will allow e500 boards to access SD cards using just their own devices.

Signed-off-by: Bernhard Beschow 
---
 hw/sd/sdhci.c | 147 +-
 include/hw/sd/sdhci.h |   3 +
 2 files changed, 149 insertions(+), 1 deletion(-)

diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 306070c872..ff92c6c4e5 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1369,6 +1369,7 @@ void sdhci_initfn(SDHCIState *s)
 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, 
s);
 
 s->io_ops = _mmio_ops;
+s->io_registers_map_size = SDHC_REGISTERS_MAP_SIZE;
 }
 
 void sdhci_uninitfn(SDHCIState *s)
@@ -1392,7 +1393,7 @@ void sdhci_common_realize(SDHCIState *s, Error **errp)
 s->fifo_buffer = g_malloc0(s->buf_maxsz);
 
 memory_region_init_io(>iomem, OBJECT(s), s->io_ops, s, "sdhci",
-  SDHC_REGISTERS_MAP_SIZE);
+  s->io_registers_map_size);
 }
 
 void sdhci_common_unrealize(SDHCIState *s)
@@ -1575,6 +1576,149 @@ static const TypeInfo sdhci_bus_info = {
 .class_init = sdhci_bus_class_init,
 };
 
+/* --- qdev Freescale eSDHC --- */
+
+/* Watermark Level Register */
+#define ESDHC_WML0x44
+
+/* Host Controller Capabilities Register 2 */
+#define ESDHC_CAPABILITIES_10x114
+
+/* Control Register for DMA transfer */
+#define ESDHC_DMA_SYSCTL0x40c
+
+#define ESDHC_REGISTERS_MAP_SIZE0x410
+
+static uint64_t esdhci_read(void *opaque, hwaddr offset, unsigned size)
+{
+uint64_t ret;
+
+if (size != 4) {
+qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
+  " wrong size\n", size, offset);
+return 0;
+}
+
+if (offset & 0x3) {
+qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
+  " unaligned\n", size, offset);
+return 0;
+}
+
+switch (offset) {
+case SDHC_SYSAD:
+case SDHC_BLKSIZE:
+case SDHC_ARGUMENT:
+case SDHC_TRNMOD:
+case SDHC_RSPREG0:
+case SDHC_RSPREG1:
+case SDHC_RSPREG2:
+case SDHC_RSPREG3:
+case SDHC_BDATA:
+case SDHC_PRNSTS:
+case SDHC_HOSTCTL:
+case SDHC_CLKCON:
+case SDHC_NORINTSTS:
+case SDHC_NORINTSTSEN:
+case SDHC_NORINTSIGEN:
+case SDHC_ACMD12ERRSTS:
+case SDHC_CAPAB:
+case SDHC_SLOT_INT_STATUS:
+ret = sdhci_read(opaque, offset, size);
+break;
+
+case ESDHC_WML:
+case ESDHC_DMA_SYSCTL:
+ret = 0;
+qemu_log_mask(LOG_UNIMP, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
+  " not implemented\n", size, offset);
+break;
+
+default:
+ret = 0;
+qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
+  " unknown offset\n", size, offset);
+break;
+}
+
+return ret;
+}
+
+static void esdhci_write(void *opaque, hwaddr offset, uint64_t val,
+ unsigned size)
+{
+if (size != 4) {
+qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx
+  " <- 0x%08lx wrong size\n", size, offset, val);
+return;
+}
+
+if (offset & 0x3) {
+qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx
+  " <- 0x%08lx unaligned\n", size, offset, val);
+return;
+}
+
+switch (offset) {
+case SDHC_SYSAD:
+case SDHC_BLKSIZE:
+case SDHC_ARGUMENT:
+case SDHC_TRNMOD:
+case SDHC_BDATA:
+case SDHC_HOSTCTL:
+case SDHC_CLKCON:
+case SDHC_NORINTSTS:
+case SDHC_NORINTSTSEN:
+case SDHC_NORINTSIGEN:
+case SDHC_FEAER:
+sdhci_write(opaque, offset, val, size);
+break;
+
+case ESDHC_WML:
+case ESDHC_DMA_SYSCTL:
+qemu_log_mask(LOG_UNIMP, "ESDHC wr_%ub @0x%02" HWADDR_PRIx " <- 
0x%08lx "
+  "not implemented\n", size, offset, val);
+break;
+
+default:
+qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx
+  " <- 0x%08lx unknown offset\n", size, offset, val);
+break;
+}
+}
+
+static const MemoryRegionOps esdhc_mmio_ops = {
+.read = esdhci_read,
+.write = esdhci_write,
+.valid = {
+.min_access_size = 1,
+.max_access_size = 4,
+.unaligned = false
+},
+.endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void esdhci_init(Object *obj)
+{
+DeviceState *dev = DEVICE(obj);
+SDHCIState *s = SYSBUS_SDHCI(obj);
+
+s->io_ops = _mmio_ops;
+s->io_registers_map_size = ESDHC_REGISTERS_MAP_SIZE;
+
+/*
+ * Compatible with:
+ * - SD Host Controller Specification Version 2.0 Part A2
+ */
+qdev_prop_set_uint8(dev, "sd-spec-version", 2);
+}
+
+static const TypeInfo esdhc_info = {
+.name = TYPE_FSL_ESDHC,
+.parent = TYPE_SYSBUS_SDHCI,
+.instance_init = esdhci_init,
+};
+
 /* --- qdev i.MX eSDHC --- */
 
 #define USDHC_MIX_CTRL  0x48
@@ -1907,6 

[PATCH v2 07/13] hw/ppc/e500: Remove if statement which is now always true

2022-10-03 Thread Bernhard Beschow
Now that the MPC8544DS board also has a platform bus, the if statement
is always true.

Signed-off-by: Bernhard Beschow 
Reviewed-by: Bin Meng 
Reviewed-by: Philippe Mathieu-Daudé 
---
 hw/ppc/e500.c  | 30 ++
 hw/ppc/e500.h  |  1 -
 hw/ppc/e500plat.c  |  1 -
 hw/ppc/mpc8544ds.c |  1 -
 4 files changed, 14 insertions(+), 19 deletions(-)

diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 496c61b612..3e950ea3ba 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -1007,25 +1007,23 @@ void ppce500_init(MachineState *machine)
 }
 
 /* Platform Bus Device */
-if (pmc->has_platform_bus) {
-dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
-dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
-qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
-qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
-sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
-pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
-
-s = SYS_BUS_DEVICE(pms->pbus_dev);
-for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
-int irqn = pmc->platform_bus_first_irq + i;
-sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
-}
+dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
+dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
+qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
+qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
+pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
 
-memory_region_add_subregion(address_space_mem,
-pmc->platform_bus_base,
->pbus_dev->mmio);
+s = SYS_BUS_DEVICE(pms->pbus_dev);
+for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
+int irqn = pmc->platform_bus_first_irq + i;
+sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
 }
 
+memory_region_add_subregion(address_space_mem,
+pmc->platform_bus_base,
+>pbus_dev->mmio);
+
 /*
  * Smart firmware defaults ahead!
  *
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index 1e5853b032..68f754ce50 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -27,7 +27,6 @@ struct PPCE500MachineClass {
 
 int mpic_version;
 bool has_mpc8xxx_gpio;
-bool has_platform_bus;
 hwaddr platform_bus_base;
 hwaddr platform_bus_size;
 int platform_bus_first_irq;
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index fc911bbb7b..5bb1c603da 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -86,7 +86,6 @@ static void e500plat_machine_class_init(ObjectClass *oc, void 
*data)
 pmc->fixup_devtree = e500plat_fixup_devtree;
 pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_42;
 pmc->has_mpc8xxx_gpio = true;
-pmc->has_platform_bus = true;
 pmc->platform_bus_base = 0xfULL;
 pmc->platform_bus_size = 128 * MiB;
 pmc->platform_bus_first_irq = 5;
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index 9c81477698..7dd5219736 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -46,7 +46,6 @@ static void mpc8544ds_machine_class_init(ObjectClass *oc, 
void *data)
 pmc->pci_nr_slots = 2;
 pmc->fixup_devtree = mpc8544ds_fixup_devtree;
 pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20;
-pmc->has_platform_bus = true;
 pmc->platform_bus_base = 0xFF80ULL;
 pmc->platform_bus_size = 8 * MiB;
 pmc->platform_bus_first_irq = 5;
-- 
2.37.3




[PATCH v2 10/13] hw/sd/sdhci-internal: Unexport ESDHC defines

2022-10-03 Thread Bernhard Beschow
These defines aren't used outside of sdhci.c, so can be defined there.

Signed-off-by: Bernhard Beschow 
Reviewed-by: Bin Meng 
Reviewed-by: Philippe Mathieu-Daudé 
---
 hw/sd/sdhci-internal.h | 20 
 hw/sd/sdhci.c  | 19 +++
 2 files changed, 19 insertions(+), 20 deletions(-)

diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index e8c753d6d1..964570f8e8 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -288,26 +288,6 @@ enum {
 
 extern const VMStateDescription sdhci_vmstate;
 
-
-#define ESDHC_MIX_CTRL  0x48
-
-#define ESDHC_VENDOR_SPEC   0xc0
-#define ESDHC_IMX_FRC_SDCLK_ON  (1 << 8)
-
-#define ESDHC_DLL_CTRL  0x60
-
-#define ESDHC_TUNING_CTRL   0xcc
-#define ESDHC_TUNE_CTRL_STATUS  0x68
-#define ESDHC_WTMK_LVL  0x44
-
-/* Undocumented register used by guests working around erratum ERR004536 */
-#define ESDHC_UNDOCUMENTED_REG270x6c
-
-#define ESDHC_CTRL_4BITBUS  (0x1 << 1)
-#define ESDHC_CTRL_8BITBUS  (0x2 << 1)
-
-#define ESDHC_PRNSTS_SDSTB  (1 << 3)
-
 /*
  * Default SD/MMC host controller features information, which will be
  * presented in CAPABILITIES register of generic SD host controller at reset.
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 0e5e988927..6da5e2c781 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1577,6 +1577,25 @@ static const TypeInfo sdhci_bus_info = {
 
 /* --- qdev i.MX eSDHC --- */
 
+#define ESDHC_MIX_CTRL  0x48
+
+#define ESDHC_VENDOR_SPEC   0xc0
+#define ESDHC_IMX_FRC_SDCLK_ON  (1 << 8)
+
+#define ESDHC_DLL_CTRL  0x60
+
+#define ESDHC_TUNING_CTRL   0xcc
+#define ESDHC_TUNE_CTRL_STATUS  0x68
+#define ESDHC_WTMK_LVL  0x44
+
+/* Undocumented register used by guests working around erratum ERR004536 */
+#define ESDHC_UNDOCUMENTED_REG270x6c
+
+#define ESDHC_CTRL_4BITBUS  (0x1 << 1)
+#define ESDHC_CTRL_8BITBUS  (0x2 << 1)
+
+#define ESDHC_PRNSTS_SDSTB  (1 << 3)
+
 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
 {
 SDHCIState *s = SYSBUS_SDHCI(opaque);
-- 
2.37.3




Re: [PATCH v2 05/13] mac_oldworld: Do not open code sysbus_mmio_map()

2022-10-03 Thread BALATON Zoltan

On Mon, 3 Oct 2022, Mark Cave-Ayland wrote:

On 29/09/2022 12:32, BALATON Zoltan wrote:


On Thu, 29 Sep 2022, Mark Cave-Ayland wrote:

On 25/09/2022 13:38, BALATON Zoltan wrote:


Signed-off-by: BALATON Zoltan 
---
  hw/ppc/mac_oldworld.c | 8 ++--
  1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index cb67e44081..75fbd2a7df 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -218,16 +218,12 @@ static void ppc_heathrow_init(MachineState 
*machine)

  qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x8000);
  s = SYS_BUS_DEVICE(grackle_dev);
  sysbus_realize_and_unref(s, _fatal);
-
  sysbus_mmio_map(s, 0, GRACKLE_BASE);
  sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x20);
  /* PCI hole */
-    memory_region_add_subregion(get_system_memory(), 0x8000ULL,
-    sysbus_mmio_get_region(s, 2));
+    sysbus_mmio_map(s, 2, 0x8000);
  /* Register 2 MB of ISA IO space */
-    memory_region_add_subregion(get_system_memory(), 0xfe00,
-    sysbus_mmio_get_region(s, 3));
-
+    sysbus_mmio_map(s, 3, 0xfe00);
  pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus;
    /* MacIO */


Please drop this patch for now. The code was written on assumption that 
both sysbus and sysbus devices would be going away soon, and there are 
certainly discussions under way about coming up with a migration strategy 
to allow them to be completely removed.


This patch actually simplifies transition from sysbus to whatever else will 
be decided because then you'll surely have a way to replace 
sysbus_mmio_map() that's used everywhere else with something. This file now 
has both sysbus_mmio_map and sysbus mmio_get_region so using only one will 
make it easier to convert it and until then it's easier to read so I don't 
agree with this suggestion and want to stick to these patches (same with 
uninorth). Please reconsider your decision.


When sysbus eventually goes then mapping devices will most likely be handled 
by the memory API as above rather than using an explicit _map() API, so let's 
keep that rather than converting everything to use sysbus_mmio_map().


Hopefully not as that would make code very unreadable and hard to get for 
people unfamiliar with QOM so to not scare off potential contributors 
please invent an easier way, at least define a macro or a function for 
such common operation when sysus goes away. But it may be a long time 
until sysbus will be gone and until then we leave this code inconsistent 
now using two ways to map areaswhich I don't agree with but since you 
cannot be convinced I've dropped these changes for now.


Regards,
BALATON Zoltan

Re: [PATCH v2 04/13] hw/ppc/e500: Reduce usage of sysbus API

2022-10-03 Thread Philippe Mathieu-Daudé via

On 3/10/22 22:31, Bernhard Beschow wrote:

PlatformBusDevice has an mmio attribute which gets aliased to
SysBusDevice::mmio[0]. So PlatformbusDevice::mmio can be used directly,
avoiding the sysbus API.

Signed-off-by: Bernhard Beschow 
---
  hw/ppc/e500.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)


Reviewed-by: Philippe Mathieu-Daudé 




[PATCH v2 03/13] docs/system/ppc/ppce500: Add heading for networking chapter

2022-10-03 Thread Bernhard Beschow
The sudden change of topics is slightly confusing and makes the
networking information less visible. So separate the networking chapter
to improve comprehensibility.

Signed-off-by: Bernhard Beschow 
Reviewed-by: Bin Meng 
Reviewed-by: Philippe Mathieu-Daudé 
---
 docs/system/ppc/ppce500.rst | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
index 9beef39171..ba6bcb7314 100644
--- a/docs/system/ppc/ppce500.rst
+++ b/docs/system/ppc/ppce500.rst
@@ -146,6 +146,9 @@ You can specify a real world SoC device that QEMU has 
built-in support but all
 these SoCs are e500v2 based MPC85xx series, hence you cannot test anything
 built for P4080 (e500mc), P5020 (e5500) and T2080 (e6500).
 
+Networking
+--
+
 By default a VirtIO standard PCI networking device is connected as an ethernet
 interface at PCI address 0.1.0, but we can switch that to an e1000 NIC by:
 
-- 
2.37.3




[PATCH v2 09/13] hw/ppc/e500: Implement pflash handling

2022-10-03 Thread Bernhard Beschow
Allows e500 boards to have their root file system reside on flash using
only builtin devices located in the eLBC memory region.

Note that the flash memory area is only created when a -pflash argument is
given, and that the size is determined by the given file. The idea is to
put users into control.

Signed-off-by: Bernhard Beschow 
---
 docs/system/ppc/ppce500.rst | 12 ++
 hw/ppc/Kconfig  |  1 +
 hw/ppc/e500.c   | 76 +
 3 files changed, 89 insertions(+)

diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
index ba6bcb7314..1ed6c36599 100644
--- a/docs/system/ppc/ppce500.rst
+++ b/docs/system/ppc/ppce500.rst
@@ -119,6 +119,18 @@ To boot the 32-bit Linux kernel:
   -initrd /path/to/rootfs.cpio \
   -append "root=/dev/ram"
 
+Rather than using a root file system on ram disk, it is possible to have it on
+emulated flash. Given an ext2 image whose size must be a power of two, it can
+be used as follows:
+
+.. code-block:: bash
+
+  $ qemu-system-ppc{64|32} -M ppce500 -cpu e500mc -smp 4 -m 2G \
+  -display none -serial stdio \
+  -kernel vmlinux \
+  -drive if=pflash,file=/path/to/rootfs.ext2,format=raw \
+  -append "rootwait root=/dev/mtdblock0"
+
 Running U-Boot
 --
 
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 791fe78a50..769a1ead1c 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -126,6 +126,7 @@ config E500
 select ETSEC
 select GPIO_MPC8XXX
 select OPENPIC
+select PFLASH_CFI01
 select PLATFORM_BUS
 select PPCE500_PCI
 select SERIAL
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 3e950ea3ba..2b1430fca4 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -23,8 +23,10 @@
 #include "e500-ccsr.h"
 #include "net/net.h"
 #include "qemu/config-file.h"
+#include "hw/block/flash.h"
 #include "hw/char/serial.h"
 #include "hw/pci/pci.h"
+#include "sysemu/block-backend-io.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
 #include "sysemu/reset.h"
@@ -267,6 +269,31 @@ static void sysbus_device_create_devtree(SysBusDevice 
*sbdev, void *opaque)
 }
 }
 
+static void create_devtree_flash(SysBusDevice *sbdev,
+ PlatformDevtreeData *data)
+{
+g_autofree char *name = NULL;
+uint64_t num_blocks = object_property_get_uint(OBJECT(sbdev),
+   "num-blocks",
+   _fatal);
+uint64_t sector_length = object_property_get_uint(OBJECT(sbdev),
+  "sector-length",
+  _fatal);
+uint64_t bank_width = object_property_get_uint(OBJECT(sbdev),
+   "width",
+   _fatal);
+hwaddr flashbase = 0;
+hwaddr flashsize = num_blocks * sector_length;
+void *fdt = data->fdt;
+
+name = g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase);
+qemu_fdt_add_subnode(fdt, name);
+qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash");
+qemu_fdt_setprop_sized_cells(fdt, name, "reg",
+ 1, flashbase, 1, flashsize);
+qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width);
+}
+
 static void platform_bus_create_devtree(PPCE500MachineState *pms,
 void *fdt, const char *mpic)
 {
@@ -276,6 +303,8 @@ static void platform_bus_create_devtree(PPCE500MachineState 
*pms,
 uint64_t addr = pmc->platform_bus_base;
 uint64_t size = pmc->platform_bus_size;
 int irq_start = pmc->platform_bus_first_irq;
+SysBusDevice *sbdev;
+bool ambiguous;
 
 /* Create a /platform node that we can put all devices into */
 
@@ -302,6 +331,13 @@ static void 
platform_bus_create_devtree(PPCE500MachineState *pms,
 /* Loop through all dynamic sysbus devices and create nodes for them */
 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, );
 
+sbdev = SYS_BUS_DEVICE(object_resolve_path_type("", TYPE_PFLASH_CFI01,
+));
+if (sbdev) {
+assert(!ambiguous);
+create_devtree_flash(sbdev, );
+}
+
 g_free(node);
 }
 
@@ -856,6 +892,7 @@ void ppce500_init(MachineState *machine)
 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
 IrqLines *irqs;
 DeviceState *dev, *mpicdev;
+DriveInfo *dinfo;
 CPUPPCState *firstenv = NULL;
 MemoryRegion *ccsr_addr_space;
 SysBusDevice *s;
@@ -1024,6 +1061,45 @@ void ppce500_init(MachineState *machine)
 pmc->platform_bus_base,
 >pbus_dev->mmio);
 
+dinfo = drive_get(IF_PFLASH, 0, 0);
+if (dinfo) {
+BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
+BlockDriverState *bs = blk_bs(blk);
+uint64_t size = bdrv_getlength(bs);

[PATCH v3 08/13] hw/ppc/mac.h: Move newworld specific parts out from shared header

2022-10-03 Thread BALATON Zoltan
Move the parts specific to and only used by mac99 out from the shared
mac.h into mac_newworld.c where they better belong.

Signed-off-by: BALATON Zoltan 
Reviewed-by: Mark Cave-Ayland 
---
 hw/ppc/mac.h  | 24 
 hw/ppc/mac_newworld.c | 19 +++
 hw/ppc/mac_oldworld.c |  1 +
 3 files changed, 20 insertions(+), 24 deletions(-)

diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index a1fa8f8e41..e97087c7e7 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -26,15 +26,8 @@
 #ifndef PPC_MAC_H
 #define PPC_MAC_H
 
-#include "qemu/units.h"
 #include "exec/memory.h"
-#include "hw/boards.h"
 #include "hw/sysbus.h"
-#include "hw/input/adb.h"
-#include "hw/misc/mos6522.h"
-#include "hw/pci/pci_host.h"
-#include "hw/pci-host/uninorth.h"
-#include "qom/object.h"
 
 #define NVRAM_SIZE0x2000
 #define PROM_FILENAME"openbios-ppc"
@@ -65,23 +58,6 @@
 #define NEWWORLD_EXTING_GPIO1  0x2f
 #define NEWWORLD_EXTING_GPIO9  0x37
 
-/* Core99 machine */
-#define TYPE_CORE99_MACHINE MACHINE_TYPE_NAME("mac99")
-typedef struct Core99MachineState Core99MachineState;
-DECLARE_INSTANCE_CHECKER(Core99MachineState, CORE99_MACHINE,
- TYPE_CORE99_MACHINE)
-
-#define CORE99_VIA_CONFIG_CUDA 0x0
-#define CORE99_VIA_CONFIG_PMU  0x1
-#define CORE99_VIA_CONFIG_PMU_ADB  0x2
-
-struct Core99MachineState {
-/*< private >*/
-MachineState parent;
-
-uint8_t via_config;
-};
-
 /* Grackle PCI */
 #define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
 
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 1abdc581fa..33caecd236 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -48,10 +48,13 @@
 
 #include "qemu/osdep.h"
 #include "qemu/datadir.h"
+#include "qemu/units.h"
 #include "qapi/error.h"
 #include "hw/ppc/ppc.h"
 #include "hw/qdev-properties.h"
 #include "hw/ppc/mac.h"
+#include "hw/boards.h"
+#include "hw/pci-host/uninorth.h"
 #include "hw/input/adb.h"
 #include "hw/ppc/mac_dbdma.h"
 #include "hw/pci/pci.h"
@@ -83,6 +86,22 @@
 #define PROM_BASE 0xfff0
 #define PROM_SIZE (1 * MiB)
 
+#define TYPE_CORE99_MACHINE MACHINE_TYPE_NAME("mac99")
+typedef struct Core99MachineState Core99MachineState;
+DECLARE_INSTANCE_CHECKER(Core99MachineState, CORE99_MACHINE,
+ TYPE_CORE99_MACHINE)
+
+#define CORE99_VIA_CONFIG_CUDA 0x0
+#define CORE99_VIA_CONFIG_PMU  0x1
+#define CORE99_VIA_CONFIG_PMU_ADB  0x2
+
+struct Core99MachineState {
+/*< private >*/
+MachineState parent;
+
+uint8_t via_config;
+};
+
 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
 Error **errp)
 {
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index be06ea04ff..a10c884503 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -31,6 +31,7 @@
 #include "hw/ppc/ppc.h"
 #include "hw/qdev-properties.h"
 #include "mac.h"
+#include "hw/boards.h"
 #include "hw/input/adb.h"
 #include "sysemu/sysemu.h"
 #include "net/net.h"
-- 
2.30.4




Re: [PATCH v2 05/13] hw/ppc/mpc8544ds: Rename wrongly named method

2022-10-03 Thread Philippe Mathieu-Daudé via

On 3/10/22 22:31, Bernhard Beschow wrote:

Signed-off-by: Bernhard Beschow 
---
  hw/ppc/mpc8544ds.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé 




[PATCH v2 08/13] hw/block/pflash_cfi01: Error out if device length isn't a power of two

2022-10-03 Thread Bernhard Beschow
According to the JEDEC standard the device length is communicated to an
OS as an exponent (power of two).

Signed-off-by: Bernhard Beschow 
Reviewed-by: Bin Meng 
---
 hw/block/pflash_cfi01.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index 0cbc2fb4cb..8c9b3f518a 100644
--- a/hw/block/pflash_cfi01.c
+++ b/hw/block/pflash_cfi01.c
@@ -690,7 +690,7 @@ static const MemoryRegionOps pflash_cfi01_ops = {
 .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-static void pflash_cfi01_fill_cfi_table(PFlashCFI01 *pfl)
+static void pflash_cfi01_fill_cfi_table(PFlashCFI01 *pfl, Error **errp)
 {
 uint64_t blocks_per_device, sector_len_per_device, device_len;
 int num_devices;
@@ -708,6 +708,10 @@ static void pflash_cfi01_fill_cfi_table(PFlashCFI01 *pfl)
 sector_len_per_device = pfl->sector_len / num_devices;
 }
 device_len = sector_len_per_device * blocks_per_device;
+if (ctpop64(device_len) != 1) {
+error_setg(errp, "Device size must be a power of two.");
+return;
+}
 
 /* Hardcoded CFI table */
 /* Standard "QRY" string */
@@ -865,7 +869,7 @@ static void pflash_cfi01_realize(DeviceState *dev, Error 
**errp)
  */
 pfl->cmd = 0x00;
 pfl->status = 0x80; /* WSM ready */
-pflash_cfi01_fill_cfi_table(pfl);
+pflash_cfi01_fill_cfi_table(pfl, errp);
 }
 
 static void pflash_cfi01_system_reset(DeviceState *dev)
-- 
2.37.3




[PATCH v3 11/13] hw/ppc/mac.h: Move PROM and KERNEL defines to board code

2022-10-03 Thread BALATON Zoltan
The PROM_FILENAME and KERNEL_* defines are used by mac_oldworld and
mac_newworld but they don't have to be identical so these could be
moved to the individual boards.

Signed-off-by: BALATON Zoltan 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Mark Cave-Ayland 
---
 hw/ppc/mac.h  | 4 
 hw/ppc/mac_newworld.c | 4 
 hw/ppc/mac_oldworld.c | 7 ++-
 3 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index fe77a6c6db..3e2df262ee 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -30,10 +30,6 @@
 #include "hw/sysbus.h"
 
 #define NVRAM_SIZE0x2000
-#define PROM_FILENAME"openbios-ppc"
-
-#define KERNEL_LOAD_ADDR 0x0100
-#define KERNEL_GAP   0x0010
 
 /* Mac NVRAM */
 #define TYPE_MACIO_NVRAM "macio-nvram"
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 33caecd236..34531c64a7 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -83,9 +83,13 @@
 
 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
 
+#define PROM_FILENAME "openbios-ppc"
 #define PROM_BASE 0xfff0
 #define PROM_SIZE (1 * MiB)
 
+#define KERNEL_LOAD_ADDR 0x0100
+#define KERNEL_GAP   0x0010
+
 #define TYPE_CORE99_MACHINE MACHINE_TYPE_NAME("mac99")
 typedef struct Core99MachineState Core99MachineState;
 DECLARE_INSTANCE_CHECKER(Core99MachineState, CORE99_MACHINE,
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index e1a22f8eba..5213cbcc04 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -58,10 +58,15 @@
 
 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
 
-#define GRACKLE_BASE 0xfec0
+#define PROM_FILENAME "openbios-ppc"
 #define PROM_BASE 0xffc0
 #define PROM_SIZE (4 * MiB)
 
+#define KERNEL_LOAD_ADDR 0x0100
+#define KERNEL_GAP   0x0010
+
+#define GRACKLE_BASE 0xfec0
+
 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
 Error **errp)
 {
-- 
2.30.4




[PATCH v2 04/13] hw/ppc/e500: Reduce usage of sysbus API

2022-10-03 Thread Bernhard Beschow
PlatformBusDevice has an mmio attribute which gets aliased to
SysBusDevice::mmio[0]. So PlatformbusDevice::mmio can be used directly,
avoiding the sysbus API.

Signed-off-by: Bernhard Beschow 
---
 hw/ppc/e500.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 32495d0123..496c61b612 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -1023,7 +1023,7 @@ void ppce500_init(MachineState *machine)
 
 memory_region_add_subregion(address_space_mem,
 pmc->platform_bus_base,
-sysbus_mmio_get_region(s, 0));
+>pbus_dev->mmio);
 }
 
 /*
-- 
2.37.3




[PATCH v3 12/13] hw/ppc/mac.h: Rename to include/hw/nvram/mac_nvram.h

2022-10-03 Thread BALATON Zoltan
All that is left in mac.h now belongs to the nvram emulation so rename
it accordingly and only include it where it is really used.

Signed-off-by: BALATON Zoltan 
Reviewed-by: Mark Cave-Ayland 
---
 MAINTAINERS  |  1 +
 hw/ide/macio.c   |  1 -
 hw/intc/heathrow_pic.c   |  1 -
 hw/intc/openpic.c|  1 -
 hw/misc/macio/cuda.c |  1 -
 hw/misc/macio/gpio.c |  1 -
 hw/misc/macio/macio.c|  1 -
 hw/misc/macio/pmu.c  |  1 -
 hw/nvram/mac_nvram.c |  2 +-
 hw/pci-host/grackle.c|  1 -
 hw/pci-host/uninorth.c   |  1 -
 hw/ppc/mac_newworld.c|  2 +-
 hw/ppc/mac_oldworld.c|  1 -
 include/hw/misc/macio/macio.h|  2 +-
 hw/ppc/mac.h => include/hw/nvram/mac_nvram.h | 11 ++-
 15 files changed, 10 insertions(+), 18 deletions(-)
 rename hw/ppc/mac.h => include/hw/nvram/mac_nvram.h (89%)

diff --git a/MAINTAINERS b/MAINTAINERS
index 6e6819afcd..69bf07e92b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1328,6 +1328,7 @@ F: hw/nvram/mac_nvram.c
 F: hw/input/adb*
 F: include/hw/misc/macio/
 F: include/hw/misc/mos6522.h
+F: include/hw/nvram/mac_nvram.h
 F: include/hw/ppc/mac_dbdma.h
 F: include/hw/pci-host/uninorth.h
 F: include/hw/input/adb*
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index 1c15c37ec5..e604466acb 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -24,7 +24,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "hw/ppc/mac.h"
 #include "hw/ppc/mac_dbdma.h"
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
diff --git a/hw/intc/heathrow_pic.c b/hw/intc/heathrow_pic.c
index cb97c315da..13048a2735 100644
--- a/hw/intc/heathrow_pic.c
+++ b/hw/intc/heathrow_pic.c
@@ -24,7 +24,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "hw/ppc/mac.h"
 #include "migration/vmstate.h"
 #include "qemu/module.h"
 #include "hw/intc/heathrow_pic.h"
diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c
index b0787e8ee7..c757adbe53 100644
--- a/hw/intc/openpic.c
+++ b/hw/intc/openpic.c
@@ -32,7 +32,6 @@
 
 #include "qemu/osdep.h"
 #include "hw/irq.h"
-#include "hw/ppc/mac.h"
 #include "hw/pci/pci.h"
 #include "hw/ppc/openpic.h"
 #include "hw/ppc/ppc_e500.h"
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
index 1498113cfc..0d4c13319a 100644
--- a/hw/misc/macio/cuda.c
+++ b/hw/misc/macio/cuda.c
@@ -25,7 +25,6 @@
 
 #include "qemu/osdep.h"
 #include "hw/irq.h"
-#include "hw/ppc/mac.h"
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 #include "hw/input/adb.h"
diff --git a/hw/misc/macio/gpio.c b/hw/misc/macio/gpio.c
index b1bcf830c3..c8ac5633b2 100644
--- a/hw/misc/macio/gpio.c
+++ b/hw/misc/macio/gpio.c
@@ -24,7 +24,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "hw/ppc/mac.h"
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 #include "hw/misc/macio/macio.h"
diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
index f9f0758b03..93a7c7bbc8 100644
--- a/hw/misc/macio/macio.c
+++ b/hw/misc/macio/macio.c
@@ -26,7 +26,6 @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/module.h"
-#include "hw/ppc/mac.h"
 #include "hw/misc/macio/cuda.h"
 #include "hw/pci/pci.h"
 #include "hw/ppc/mac_dbdma.h"
diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c
index 336502a84b..70562ed8d0 100644
--- a/hw/misc/macio/pmu.c
+++ b/hw/misc/macio/pmu.c
@@ -29,7 +29,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "hw/ppc/mac.h"
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 #include "hw/input/adb.h"
diff --git a/hw/nvram/mac_nvram.c b/hw/nvram/mac_nvram.c
index 11f2d31cdb..3d9ddda217 100644
--- a/hw/nvram/mac_nvram.c
+++ b/hw/nvram/mac_nvram.c
@@ -25,7 +25,7 @@
 
 #include "qemu/osdep.h"
 #include "hw/nvram/chrp_nvram.h"
-#include "hw/ppc/mac.h"
+#include "hw/nvram/mac_nvram.h"
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 #include "qemu/cutils.h"
diff --git a/hw/pci-host/grackle.c b/hw/pci-host/grackle.c
index e4c7303859..95945ac0f4 100644
--- a/hw/pci-host/grackle.c
+++ b/hw/pci-host/grackle.c
@@ -24,7 +24,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "hw/ppc/mac.h"
 #include "hw/qdev-properties.h"
 #include "hw/pci/pci.h"
 #include "hw/irq.h"
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index d25b62d6a5..aebd44d265 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -24,7 +24,6 @@
 
 #include "qemu/osdep.h"
 #include "hw/irq.h"
-#include "hw/ppc/mac.h"
 #include "hw/qdev-properties.h"
 #include "qemu/module.h"
 #include "hw/pci/pci.h"
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 34531c64a7..7a12949fc1 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -52,7 +52,7 @@
 #include "qapi/error.h"
 #include "hw/ppc/ppc.h"
 #include "hw/qdev-properties.h"
-#include 

[PATCH v2 06/13] hw/ppc/mpc8544ds: Add platform bus

2022-10-03 Thread Bernhard Beschow
Models the real device more closely.

Address and size values are taken from mpc8544.dts from the linux-5.17.7
tree. The IRQ range is taken from e500plat.c.

Signed-off-by: Bernhard Beschow 
---
 hw/ppc/mpc8544ds.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index 8e674ad195..9c81477698 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -14,6 +14,7 @@
 #include "sysemu/device_tree.h"
 #include "hw/ppc/openpic.h"
 #include "qemu/error-report.h"
+#include "qemu/units.h"
 #include "cpu.h"
 
 static void mpc8544ds_fixup_devtree(void *fdt)
@@ -45,6 +46,11 @@ static void mpc8544ds_machine_class_init(ObjectClass *oc, 
void *data)
 pmc->pci_nr_slots = 2;
 pmc->fixup_devtree = mpc8544ds_fixup_devtree;
 pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20;
+pmc->has_platform_bus = true;
+pmc->platform_bus_base = 0xFF80ULL;
+pmc->platform_bus_size = 8 * MiB;
+pmc->platform_bus_first_irq = 5;
+pmc->platform_bus_num_irqs = 10;
 pmc->ccsrbar_base = 0xE000ULL;
 pmc->pci_mmio_base = 0xC000ULL;
 pmc->pci_mmio_bus_base = 0xC000ULL;
-- 
2.37.3




[PATCH v3 00/13] Misc ppc/mac machines clean up

2022-10-03 Thread BALATON Zoltan
This series includes some clean ups to mac_newworld and mac_oldworld
to make them a bit simpler and more readable, It also removes the
shared mac.h file that turns out was more of a random collection of
unrelated things. Getting rid of this mac.h improves the locality of
device models and reduces unnecessary interdependency.

v3: Some more patch spliting and changes I've noticed and address more
review comments
v2: Split some patches and add a few more I've noticed now and address
review comments

BALATON Zoltan (13):
  mac_newworld: Drop some variables
  mac_oldworld: Drop some more variables
  mac_{old|new}world: Set tbfreq at declaration
  mac_{old|new}world: Avoid else branch by setting default value
  mac_{old|new}world: Simplify cmdline_base calculation
  mac_newworld: Clean up creation of Uninorth devices
  mac_{old|new}world: Reduce number of QOM casts
  hw/ppc/mac.h: Move newworld specific parts out from shared header
  hw/ppc/mac.h: Move macio specific parts out from shared header
  hw/ppc/mac.h: Move grackle-pcihost type declaration out to a header
  hw/ppc/mac.h: Move PROM and KERNEL defines to board code
  hw/ppc/mac.h: Rename to include/hw/nvram/mac_nvram.h
  mac_nvram: Use NVRAM_SIZE constant

 MAINTAINERS   |   2 +
 hw/ide/macio.c|   1 -
 hw/intc/heathrow_pic.c|   1 -
 hw/intc/openpic.c |   1 -
 hw/misc/macio/cuda.c  |   1 -
 hw/misc/macio/gpio.c  |   1 -
 hw/misc/macio/macio.c |   8 +-
 hw/misc/macio/pmu.c   |   1 -
 hw/nvram/mac_nvram.c  |   2 +-
 hw/pci-host/grackle.c |  15 +--
 hw/pci-host/uninorth.c|   1 -
 hw/ppc/mac.h  | 105 
 hw/ppc/mac_newworld.c | 225 --
 hw/ppc/mac_oldworld.c | 111 +++--
 include/hw/misc/macio/macio.h |  23 +++-
 include/hw/nvram/mac_nvram.h  |  51 
 include/hw/pci-host/grackle.h |  44 +++
 17 files changed, 280 insertions(+), 313 deletions(-)
 delete mode 100644 hw/ppc/mac.h
 create mode 100644 include/hw/nvram/mac_nvram.h
 create mode 100644 include/hw/pci-host/grackle.h

-- 
2.30.4




[PATCH v2 02/13] hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxx

2022-10-03 Thread Bernhard Beschow
Having a dedicated config switch makes dependency handling cleaner.

Signed-off-by: Bernhard Beschow 
Reviewed-by: Bin Meng 
Reviewed-by: Philippe Mathieu-Daudé 
---
 hw/gpio/Kconfig | 3 +++
 hw/gpio/meson.build | 2 +-
 hw/ppc/Kconfig  | 1 +
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
index f0e7405f6e..d2cf3accc8 100644
--- a/hw/gpio/Kconfig
+++ b/hw/gpio/Kconfig
@@ -8,6 +8,9 @@ config PL061
 config GPIO_KEY
 bool
 
+config GPIO_MPC8XXX
+bool
+
 config GPIO_PWR
 bool
 
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
index 7bd6a57264..b726e6d27a 100644
--- a/hw/gpio/meson.build
+++ b/hw/gpio/meson.build
@@ -1,5 +1,5 @@
-softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c'))
 softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c'))
+softmmu_ss.add(when: 'CONFIG_GPIO_MPC8XXX', if_true: files('mpc8xxx.c'))
 softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c'))
 softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c'))
 softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c'))
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 22a64745d4..791fe78a50 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -124,6 +124,7 @@ config E500
 imply AT24C
 imply VIRTIO_PCI
 select ETSEC
+select GPIO_MPC8XXX
 select OPENPIC
 select PLATFORM_BUS
 select PPCE500_PCI
-- 
2.37.3




[PATCH v3 04/13] mac_{old|new}world: Avoid else branch by setting default value

2022-10-03 Thread BALATON Zoltan
Several variables are set in if-else branches where the else branch
can be removed by setting a default value at the variable declaration
which leads to simlpler code that is easier to follow.

Signed-off-by: BALATON Zoltan 
---
 hw/ppc/mac_newworld.c | 19 ---
 hw/ppc/mac_oldworld.c | 18 --
 2 files changed, 8 insertions(+), 29 deletions(-)

diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 6327694f85..6bc3bd19be 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -111,11 +111,11 @@ static void ppc_core99_init(MachineState *machine)
 CPUPPCState *env = NULL;
 char *filename;
 IrqLines *openpic_irqs;
-int i, j, k, ppc_boot_device, machine_arch, bios_size;
+int i, j, k, ppc_boot_device, machine_arch, bios_size = -1;
 const char *bios_name = machine->firmware ?: PROM_FILENAME;
 MemoryRegion *bios = g_new(MemoryRegion, 1);
-hwaddr kernel_base, initrd_base, cmdline_base = 0;
-long kernel_size, initrd_size;
+hwaddr kernel_base = 0, initrd_base = 0, cmdline_base = 0;
+long kernel_size = 0, initrd_size = 0;
 UNINHostState *uninorth_pci;
 PCIBus *pci_bus;
 PCIDevice *macio;
@@ -165,8 +165,6 @@ static void ppc_core99_init(MachineState *machine)
 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE);
 }
 g_free(filename);
-} else {
-bios_size = -1;
 }
 if (bios_size < 0 || bios_size > PROM_SIZE) {
 error_report("could not load PowerPC bios '%s'", bios_name);
@@ -174,15 +172,12 @@ static void ppc_core99_init(MachineState *machine)
 }
 
 if (machine->kernel_filename) {
-int bswap_needed;
+int bswap_needed = 0;
 
 #ifdef BSWAP_NEEDED
 bswap_needed = 1;
-#else
-bswap_needed = 0;
 #endif
 kernel_base = KERNEL_LOAD_ADDR;
-
 kernel_size = load_elf(machine->kernel_filename, NULL,
translate_kernel_address, NULL, NULL, NULL,
NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
@@ -212,16 +207,10 @@ static void ppc_core99_init(MachineState *machine)
 }
 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
 } else {
-initrd_base = 0;
-initrd_size = 0;
 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + 
KERNEL_GAP);
 }
 ppc_boot_device = 'm';
 } else {
-kernel_base = 0;
-kernel_size = 0;
-initrd_base = 0;
-initrd_size = 0;
 ppc_boot_device = '\0';
 /* We consider that NewWorld PowerMac never have any floppy drive
  * For now, OHW cannot boot from the network.
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index 5cabc410e7..cb67e44081 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -84,11 +84,11 @@ static void ppc_heathrow_init(MachineState *machine)
 PowerPCCPU *cpu = NULL;
 CPUPPCState *env = NULL;
 char *filename;
-int i, bios_size;
+int i, bios_size = -1;
 MemoryRegion *bios = g_new(MemoryRegion, 1);
 uint64_t bios_addr;
-uint32_t kernel_base, initrd_base, cmdline_base = 0;
-int32_t kernel_size, initrd_size;
+uint32_t kernel_base = 0, initrd_base = 0, cmdline_base = 0;
+int32_t kernel_size = 0, initrd_size = 0;
 PCIBus *pci_bus;
 PCIDevice *macio;
 MACIOIDEState *macio_ide;
@@ -139,8 +139,6 @@ static void ppc_heathrow_init(MachineState *machine)
 bios_addr = PROM_BASE;
 }
 g_free(filename);
-} else {
-bios_size = -1;
 }
 if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) {
 error_report("could not load PowerPC bios '%s'", bios_name);
@@ -148,12 +146,10 @@ static void ppc_heathrow_init(MachineState *machine)
 }
 
 if (machine->kernel_filename) {
-int bswap_needed;
+int bswap_needed = 0;
 
 #ifdef BSWAP_NEEDED
 bswap_needed = 1;
-#else
-bswap_needed = 0;
 #endif
 kernel_base = KERNEL_LOAD_ADDR;
 kernel_size = load_elf(machine->kernel_filename, NULL,
@@ -186,16 +182,10 @@ static void ppc_heathrow_init(MachineState *machine)
 }
 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
 } else {
-initrd_base = 0;
-initrd_size = 0;
 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + 
KERNEL_GAP);
 }
 ppc_boot_device = 'm';
 } else {
-kernel_base = 0;
-kernel_size = 0;
-initrd_base = 0;
-initrd_size = 0;
 ppc_boot_device = '\0';
 for (i = 0; machine->boot_config.order[i] != '\0'; i++) {
 /*
-- 
2.30.4




[PATCH v3 09/13] hw/ppc/mac.h: Move macio specific parts out from shared header

2022-10-03 Thread BALATON Zoltan
Move the parts specific to and only used by macio out from the shared
mac.h into macio.c where they better belong.

Signed-off-by: BALATON Zoltan 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Mark Cave-Ayland 
---
 hw/misc/macio/macio.c |  5 +++--
 hw/ppc/mac.h  | 23 ---
 include/hw/misc/macio/macio.h | 21 +
 3 files changed, 24 insertions(+), 25 deletions(-)

diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
index c1fad43f6c..f9f0758b03 100644
--- a/hw/misc/macio/macio.c
+++ b/hw/misc/macio/macio.c
@@ -37,8 +37,9 @@
 #include "hw/intc/heathrow_pic.h"
 #include "trace.h"
 
-/* Note: this code is strongly inspirated from the corresponding code
- * in PearPC */
+#define ESCC_CLOCK 3686400
+
+/* Note: this code is strongly inspired by the corresponding code in PearPC */
 
 /*
  * The mac-io has two interfaces to the ESCC. One is called "escc-legacy",
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index e97087c7e7..55cb02c990 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -35,29 +35,6 @@
 #define KERNEL_LOAD_ADDR 0x0100
 #define KERNEL_GAP   0x0010
 
-#define ESCC_CLOCK 3686400
-
-/* Old World IRQs */
-#define OLDWORLD_CUDA_IRQ  0x12
-#define OLDWORLD_ESCCB_IRQ 0x10
-#define OLDWORLD_ESCCA_IRQ 0xf
-#define OLDWORLD_IDE0_IRQ  0xd
-#define OLDWORLD_IDE0_DMA_IRQ  0x2
-#define OLDWORLD_IDE1_IRQ  0xe
-#define OLDWORLD_IDE1_DMA_IRQ  0x3
-
-/* New World IRQs */
-#define NEWWORLD_CUDA_IRQ  0x19
-#define NEWWORLD_PMU_IRQ   0x19
-#define NEWWORLD_ESCCB_IRQ 0x24
-#define NEWWORLD_ESCCA_IRQ 0x25
-#define NEWWORLD_IDE0_IRQ  0xd
-#define NEWWORLD_IDE0_DMA_IRQ  0x2
-#define NEWWORLD_IDE1_IRQ  0xe
-#define NEWWORLD_IDE1_DMA_IRQ  0x3
-#define NEWWORLD_EXTING_GPIO1  0x2f
-#define NEWWORLD_EXTING_GPIO9  0x37
-
 /* Grackle PCI */
 #define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
 
diff --git a/include/hw/misc/macio/macio.h b/include/hw/misc/macio/macio.h
index 6c05f3bfd2..26cf15b1ce 100644
--- a/include/hw/misc/macio/macio.h
+++ b/include/hw/misc/macio/macio.h
@@ -38,6 +38,27 @@
 #include "hw/ppc/openpic.h"
 #include "qom/object.h"
 
+/* Old World IRQs */
+#define OLDWORLD_CUDA_IRQ  0x12
+#define OLDWORLD_ESCCB_IRQ 0x10
+#define OLDWORLD_ESCCA_IRQ 0xf
+#define OLDWORLD_IDE0_IRQ  0xd
+#define OLDWORLD_IDE0_DMA_IRQ  0x2
+#define OLDWORLD_IDE1_IRQ  0xe
+#define OLDWORLD_IDE1_DMA_IRQ  0x3
+
+/* New World IRQs */
+#define NEWWORLD_CUDA_IRQ  0x19
+#define NEWWORLD_PMU_IRQ   0x19
+#define NEWWORLD_ESCCB_IRQ 0x24
+#define NEWWORLD_ESCCA_IRQ 0x25
+#define NEWWORLD_IDE0_IRQ  0xd
+#define NEWWORLD_IDE0_DMA_IRQ  0x2
+#define NEWWORLD_IDE1_IRQ  0xe
+#define NEWWORLD_IDE1_DMA_IRQ  0x3
+#define NEWWORLD_EXTING_GPIO1  0x2f
+#define NEWWORLD_EXTING_GPIO9  0x37
+
 /* MacIO virtual bus */
 #define TYPE_MACIO_BUS "macio-bus"
 OBJECT_DECLARE_SIMPLE_TYPE(MacIOBusState, MACIO_BUS)
-- 
2.30.4




[PATCH v3 03/13] mac_{old|new}world: Set tbfreq at declaration

2022-10-03 Thread BALATON Zoltan
The tbfreq variable is only set once in an if-else which can be done
at the variable declaration saving some lines of code and making it
simpler.

Signed-off-by: BALATON Zoltan 
Reviewed-by: Mark Cave-Ayland 
---
 hw/ppc/mac_newworld.c | 9 +
 hw/ppc/mac_oldworld.c | 9 +
 2 files changed, 2 insertions(+), 16 deletions(-)

diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 27e4e8d136..6327694f85 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -130,7 +130,7 @@ static void ppc_core99_init(MachineState *machine)
 DeviceState *dev, *pic_dev;
 DeviceState *uninorth_internal_dev = NULL, *uninorth_agp_dev = NULL;
 hwaddr nvram_addr = 0xFFF04000;
-uint64_t tbfreq;
+uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ;
 
 /* init CPUs */
 for (i = 0; i < machine->smp.cpus; i++) {
@@ -343,13 +343,6 @@ static void ppc_core99_init(MachineState *machine)
 has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA ||
core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB);
 
-/* Timebase Frequency */
-if (kvm_enabled()) {
-tbfreq = kvmppc_get_tbfreq();
-} else {
-tbfreq = TBFREQ;
-}
-
 /* init basic PC hardware */
 pci_bus = PCI_HOST_BRIDGE(uninorth_pci)->bus;
 
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index 86512d31ad..5cabc410e7 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -99,7 +99,7 @@ static void ppc_heathrow_init(MachineState *machine)
 uint16_t ppc_boot_device;
 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 void *fw_cfg;
-uint64_t tbfreq;
+uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ;
 
 /* init CPUs */
 for (i = 0; i < machine->smp.cpus; i++) {
@@ -223,13 +223,6 @@ static void ppc_heathrow_init(MachineState *machine)
 }
 }
 
-/* Timebase Frequency */
-if (kvm_enabled()) {
-tbfreq = kvmppc_get_tbfreq();
-} else {
-tbfreq = TBFREQ;
-}
-
 /* Grackle PCI host bridge */
 grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
 qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x8000);
-- 
2.30.4




[PATCH v2 05/13] hw/ppc/mpc8544ds: Rename wrongly named method

2022-10-03 Thread Bernhard Beschow
Signed-off-by: Bernhard Beschow 
---
 hw/ppc/mpc8544ds.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index 81177505f0..8e674ad195 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -36,7 +36,7 @@ static void mpc8544ds_init(MachineState *machine)
 ppce500_init(machine);
 }
 
-static void e500plat_machine_class_init(ObjectClass *oc, void *data)
+static void mpc8544ds_machine_class_init(ObjectClass *oc, void *data)
 {
 MachineClass *mc = MACHINE_CLASS(oc);
 PPCE500MachineClass *pmc = PPCE500_MACHINE_CLASS(oc);
@@ -63,7 +63,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void 
*data)
 static const TypeInfo mpc8544ds_info = {
 .name  = TYPE_MPC8544DS_MACHINE,
 .parent= TYPE_PPCE500_MACHINE,
-.class_init= e500plat_machine_class_init,
+.class_init= mpc8544ds_machine_class_init,
 };
 
 static void mpc8544ds_register_types(void)
-- 
2.37.3




[PATCH v2 01/13] hw/ppc/meson: Allow e500 boards to be enabled separately

2022-10-03 Thread Bernhard Beschow
Gives users more fine-grained control over what should be compiled into
QEMU.

Signed-off-by: Bernhard Beschow 
Reviewed-by: Bin Meng 
Reviewed-by: Philippe Mathieu-Daudé 
---
 configs/devices/ppc-softmmu/default.mak | 3 ++-
 hw/ppc/Kconfig  | 8 
 hw/ppc/meson.build  | 6 ++
 3 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/configs/devices/ppc-softmmu/default.mak 
b/configs/devices/ppc-softmmu/default.mak
index 658a454426..a887f5438b 100644
--- a/configs/devices/ppc-softmmu/default.mak
+++ b/configs/devices/ppc-softmmu/default.mak
@@ -1,7 +1,8 @@
 # Default configuration for ppc-softmmu
 
 # For embedded PPCs:
-CONFIG_E500=y
+CONFIG_E500PLAT=y
+CONFIG_MPC8544DS=y
 CONFIG_PPC405=y
 CONFIG_PPC440=y
 CONFIG_VIRTEX=y
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 3a4418a69e..22a64745d4 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -132,6 +132,14 @@ config E500
 select FDT_PPC
 select DS1338
 
+config E500PLAT
+bool
+select E500
+
+config MPC8544DS
+bool
+select E500
+
 config VIRTEX
 bool
 select PPC4XX
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index 62801923f3..32babc9b48 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -71,12 +71,10 @@ ppc_ss.add(when: 'CONFIG_MAC_OLDWORLD', if_true: 
files('mac_oldworld.c'))
 # NewWorld PowerMac
 ppc_ss.add(when: 'CONFIG_MAC_NEWWORLD', if_true: files('mac_newworld.c'))
 # e500
+ppc_ss.add(when: 'CONFIG_E500PLAT', if_true: files('e500plat.c'))
+ppc_ss.add(when: 'CONFIG_MPC8544DS', if_true: files('mpc8544ds.c'))
 ppc_ss.add(when: 'CONFIG_E500', if_true: files(
   'e500.c',
-  'mpc8544ds.c',
-  'e500plat.c'
-))
-ppc_ss.add(when: 'CONFIG_E500', if_true: files(
   'mpc8544_guts.c',
   'ppce500_spin.c'
 ))
-- 
2.37.3




[PATCH v3 02/13] mac_oldworld: Drop some more variables

2022-10-03 Thread BALATON Zoltan
Drop some more local variables additionally to commit b8df32555ce5 to
match clean ups done to mac_newwold in previous patch.

Signed-off-by: BALATON Zoltan 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Mark Cave-Ayland 
---
 hw/ppc/mac_oldworld.c | 43 +--
 1 file changed, 21 insertions(+), 22 deletions(-)

diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index 03732ca7ed..86512d31ad 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -80,14 +80,13 @@ static void ppc_heathrow_reset(void *opaque)
 
 static void ppc_heathrow_init(MachineState *machine)
 {
-ram_addr_t ram_size = machine->ram_size;
 const char *bios_name = machine->firmware ?: PROM_FILENAME;
-const char *boot_device = machine->boot_config.order;
 PowerPCCPU *cpu = NULL;
 CPUPPCState *env = NULL;
 char *filename;
-int i;
+int i, bios_size;
 MemoryRegion *bios = g_new(MemoryRegion, 1);
+uint64_t bios_addr;
 uint32_t kernel_base, initrd_base, cmdline_base = 0;
 int32_t kernel_size, initrd_size;
 PCIBus *pci_bus;
@@ -97,16 +96,13 @@ static void ppc_heathrow_init(MachineState *machine)
 SysBusDevice *s;
 DeviceState *dev, *pic_dev, *grackle_dev;
 BusState *adb_bus;
-uint64_t bios_addr;
-int bios_size;
-unsigned int smp_cpus = machine->smp.cpus;
 uint16_t ppc_boot_device;
 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 void *fw_cfg;
 uint64_t tbfreq;
 
 /* init CPUs */
-for (i = 0; i < smp_cpus; i++) {
+for (i = 0; i < machine->smp.cpus; i++) {
 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 env = >env;
 
@@ -116,9 +112,9 @@ static void ppc_heathrow_init(MachineState *machine)
 }
 
 /* allocate RAM */
-if (ram_size > 2047 * MiB) {
+if (machine->ram_size > 2047 * MiB) {
 error_report("Too much memory for this machine: %" PRId64 " MB, "
- "maximum 2047 MB", ram_size / MiB);
+ "maximum 2047 MB", machine->ram_size / MiB);
 exit(1);
 }
 
@@ -165,12 +161,12 @@ static void ppc_heathrow_init(MachineState *machine)
NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
 if (kernel_size < 0)
 kernel_size = load_aout(machine->kernel_filename, kernel_base,
-ram_size - kernel_base, bswap_needed,
-TARGET_PAGE_SIZE);
+machine->ram_size - kernel_base,
+bswap_needed, TARGET_PAGE_SIZE);
 if (kernel_size < 0)
 kernel_size = load_image_targphys(machine->kernel_filename,
   kernel_base,
-  ram_size - kernel_base);
+  machine->ram_size - kernel_base);
 if (kernel_size < 0) {
 error_report("could not load kernel '%s'",
  machine->kernel_filename);
@@ -182,7 +178,7 @@ static void ppc_heathrow_init(MachineState *machine)
 KERNEL_GAP);
 initrd_size = load_image_targphys(machine->initrd_filename,
   initrd_base,
-  ram_size - initrd_base);
+  machine->ram_size - initrd_base);
 if (initrd_size < 0) {
 error_report("could not load initial ram disk '%s'",
  machine->initrd_filename);
@@ -201,19 +197,22 @@ static void ppc_heathrow_init(MachineState *machine)
 initrd_base = 0;
 initrd_size = 0;
 ppc_boot_device = '\0';
-for (i = 0; boot_device[i] != '\0'; i++) {
-/* TOFIX: for now, the second IDE channel is not properly
+for (i = 0; machine->boot_config.order[i] != '\0'; i++) {
+/*
+ * TOFIX: for now, the second IDE channel is not properly
  *used by OHW. The Mac floppy disk are not emulated.
  *For now, OHW cannot boot from the network.
  */
 #if 0
-if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
-ppc_boot_device = boot_device[i];
+if (machine->boot_config.order[i] >= 'a' &&
+machine->boot_config.order[i] <= 'f') {
+ppc_boot_device = machine->boot_config.order[i];
 break;
 }
 #else
-if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
-ppc_boot_device = boot_device[i];
+if (machine->boot_config.order[i] >= 'c' &&
+machine->boot_config.order[i] <= 'd') {
+ppc_boot_device = machine->boot_config.order[i];
 break;
 }
 #endif
@@ -266,7 +265,7 @@ static void 

[PATCH v3 01/13] mac_newworld: Drop some variables

2022-10-03 Thread BALATON Zoltan
Values not used frequently enough may not worth putting in a local
variable, especially with names almost as long as the original value
because that does not improve readability, to the contrary it makes it
harder to see what value is used. Drop a few such variables. This is
the same clean up that was done for mac_oldworld in commit b8df32555ce5.

Signed-off-by: BALATON Zoltan 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Mark Cave-Ayland 
---
 hw/ppc/mac_newworld.c | 65 +++
 1 file changed, 29 insertions(+), 36 deletions(-)

diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index cf7eb72391..27e4e8d136 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -106,18 +106,13 @@ static void ppc_core99_reset(void *opaque)
 /* PowerPC Mac99 hardware initialisation */
 static void ppc_core99_init(MachineState *machine)
 {
-ram_addr_t ram_size = machine->ram_size;
-const char *bios_name = machine->firmware ?: PROM_FILENAME;
-const char *kernel_filename = machine->kernel_filename;
-const char *kernel_cmdline = machine->kernel_cmdline;
-const char *initrd_filename = machine->initrd_filename;
-const char *boot_device = machine->boot_config.order;
 Core99MachineState *core99_machine = CORE99_MACHINE(machine);
 PowerPCCPU *cpu = NULL;
 CPUPPCState *env = NULL;
 char *filename;
 IrqLines *openpic_irqs;
-int linux_boot, i, j, k;
+int i, j, k, ppc_boot_device, machine_arch, bios_size;
+const char *bios_name = machine->firmware ?: PROM_FILENAME;
 MemoryRegion *bios = g_new(MemoryRegion, 1);
 hwaddr kernel_base, initrd_base, cmdline_base = 0;
 long kernel_size, initrd_size;
@@ -129,22 +124,16 @@ static void ppc_core99_init(MachineState *machine)
 MACIOIDEState *macio_ide;
 BusState *adb_bus;
 MacIONVRAMState *nvr;
-int bios_size;
-int ppc_boot_device;
 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 void *fw_cfg;
-int machine_arch;
 SysBusDevice *s;
 DeviceState *dev, *pic_dev;
 DeviceState *uninorth_internal_dev = NULL, *uninorth_agp_dev = NULL;
 hwaddr nvram_addr = 0xFFF04000;
 uint64_t tbfreq;
-unsigned int smp_cpus = machine->smp.cpus;
-
-linux_boot = (kernel_filename != NULL);
 
 /* init CPUs */
-for (i = 0; i < smp_cpus; i++) {
+for (i = 0; i < machine->smp.cpus; i++) {
 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 env = >env;
 
@@ -184,7 +173,7 @@ static void ppc_core99_init(MachineState *machine)
 exit(1);
 }
 
-if (linux_boot) {
+if (machine->kernel_filename) {
 int bswap_needed;
 
 #ifdef BSWAP_NEEDED
@@ -194,29 +183,31 @@ static void ppc_core99_init(MachineState *machine)
 #endif
 kernel_base = KERNEL_LOAD_ADDR;
 
-kernel_size = load_elf(kernel_filename, NULL,
+kernel_size = load_elf(machine->kernel_filename, NULL,
translate_kernel_address, NULL, NULL, NULL,
NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
 if (kernel_size < 0)
-kernel_size = load_aout(kernel_filename, kernel_base,
-ram_size - kernel_base, bswap_needed,
-TARGET_PAGE_SIZE);
+kernel_size = load_aout(machine->kernel_filename, kernel_base,
+machine->ram_size - kernel_base,
+bswap_needed, TARGET_PAGE_SIZE);
 if (kernel_size < 0)
-kernel_size = load_image_targphys(kernel_filename,
+kernel_size = load_image_targphys(machine->kernel_filename,
   kernel_base,
-  ram_size - kernel_base);
+  machine->ram_size - kernel_base);
 if (kernel_size < 0) {
-error_report("could not load kernel '%s'", kernel_filename);
+error_report("could not load kernel '%s'",
+ machine->kernel_filename);
 exit(1);
 }
 /* load initrd */
-if (initrd_filename) {
+if (machine->initrd_filename) {
 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + 
KERNEL_GAP);
-initrd_size = load_image_targphys(initrd_filename, initrd_base,
-  ram_size - initrd_base);
+initrd_size = load_image_targphys(machine->initrd_filename,
+  initrd_base,
+  machine->ram_size - initrd_base);
 if (initrd_size < 0) {
 error_report("could not load initial ram disk '%s'",
- initrd_filename);
+ machine->initrd_filename);
 exit(1);
 }
 cmdline_base = 

[PATCH v2 00/13] ppc/e500: Add support for two types of flash, cleanup

2022-10-03 Thread Bernhard Beschow
Cover letter:
~

This series adds support for -pflash and direct SD card access to the
PPC e500 boards. The idea is to increase compatibility with "real" firmware
images where only the bare minimum of drivers is compiled in.

The series is structured as follows:

Patches 1-5 perform some general cleanup which paves the way for the rest of
the series.

Patches 6-9 add -pflash handling where memory-mapped flash can be added on
user's behalf. That is, the flash memory region in the eLBC is only added if
the -pflash argument is supplied. Note that the cfi01 device model becomes
stricter in checking the size of the emulated flash space.

Patches 10-13 add a new device model - the Freescale eSDHC - to the e500
boards which was missing so far.

User documentation is also added as the new features become available.

Tesing done:
* `qemu-system-ppc -M ppce500 -cpu e500mc -m 256 -kernel uImage -append
"console=ttyS0 rootwait root=/dev/mtdblock0 nokaslr" -drive
if=pflash,file=rootfs.ext2,format=raw`
* `qemu-system-ppc -M ppce500 -cpu e500mc -m 256 -kernel uImage -append
"console=ttyS0 rootwait root=/dev/mmcblk0" -device sd-card,drive=mydrive -drive
id=mydrive,if=none,file=rootfs.ext2,format=raw`

The load was created using latest Buildroot with `make
qemu_ppc_e500mc_defconfig` where the rootfs was configured to be of ext2 type.
In both cases it was possible to log in and explore the root file system.

v2:
~~~
Bin:
- Add source for MPC8544DS platform bus' memory map in commit message.
- Keep "ESDHC" in comment referring to Linux driver.
- Use "qemu-system-ppc{64|32} in documentation.
- Use g_autofree in device tree code.
- Remove unneeded device tree properties.
- Error out if pflash size doesn't fit into eLBC memory window.
- Remove unused ESDHC defines.
- Define macro ESDHC_WML for register offset with magic constant.
- Fix some whitespace issues when adding eSDHC device to e500.

Phil:
- Fix tense in commit message.

Bernhard Beschow (13):
  hw/ppc/meson: Allow e500 boards to be enabled separately
  hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxx
  docs/system/ppc/ppce500: Add heading for networking chapter
  hw/ppc/e500: Reduce usage of sysbus API
  hw/ppc/mpc8544ds: Rename wrongly named method
  hw/ppc/mpc8544ds: Add platform bus
  hw/ppc/e500: Remove if statement which is now always true
  hw/block/pflash_cfi01: Error out if device length isn't a power of two
  hw/ppc/e500: Implement pflash handling
  hw/sd/sdhci-internal: Unexport ESDHC defines
  hw/sd/sdhci: Rename ESDHC_* defines to USDHC_*
  hw/sd/sdhci: Implement Freescale eSDHC device model
  hw/ppc/e500: Add Freescale eSDHC to e500 boards

 configs/devices/ppc-softmmu/default.mak |   3 +-
 docs/system/ppc/ppce500.rst |  28 
 hw/block/pflash_cfi01.c |   8 +-
 hw/gpio/Kconfig |   3 +
 hw/gpio/meson.build |   2 +-
 hw/ppc/Kconfig  |  11 ++
 hw/ppc/e500.c   | 133 +--
 hw/ppc/e500.h   |   1 -
 hw/ppc/e500plat.c   |   1 -
 hw/ppc/meson.build  |   6 +-
 hw/ppc/mpc8544ds.c  |   9 +-
 hw/sd/sdhci-internal.h  |  20 ---
 hw/sd/sdhci.c   | 210 +---
 include/hw/sd/sdhci.h   |   3 +
 14 files changed, 368 insertions(+), 70 deletions(-)

-- 
2.37.3




[PATCH v3 06/13] mac_newworld: Clean up creation of Uninorth devices

2022-10-03 Thread BALATON Zoltan
Map regions in ascending order and reorganise code a bit to avoid some
casts and move Uninorth parts together.

Signed-off-by: BALATON Zoltan 
---
 hw/ppc/mac_newworld.c | 38 ++
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 73b01e8c6d..be2cb5f057 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -228,13 +228,6 @@ static void ppc_core99_init(MachineState *machine)
 }
 }
 
-/* UniN init */
-dev = qdev_new(TYPE_UNI_NORTH);
-s = SYS_BUS_DEVICE(dev);
-sysbus_realize_and_unref(s, _fatal);
-memory_region_add_subregion(get_system_memory(), 0xf800,
-sysbus_mmio_get_region(s, 0));
-
 openpic_irqs = g_new0(IrqLines, machine->smp.cpus);
 for (i = 0; i < machine->smp.cpus; i++) {
 /* Mac99 IRQ connection between OpenPIC outputs pins
@@ -275,24 +268,31 @@ static void ppc_core99_init(MachineState *machine)
 }
 }
 
+/* UniN init */
+s = SYS_BUS_DEVICE(qdev_new(TYPE_UNI_NORTH));
+sysbus_realize_and_unref(s, _fatal);
+memory_region_add_subregion(get_system_memory(), 0xf800,
+sysbus_mmio_get_region(s, 0));
+
+
 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
+machine_arch = ARCH_MAC99_U3;
 /* 970 gets a U3 bus */
 /* Uninorth AGP bus */
 dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE);
-sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
 uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
 s = SYS_BUS_DEVICE(dev);
+sysbus_realize_and_unref(s, _fatal);
+sysbus_mmio_map(s, 0, 0xf080);
+sysbus_mmio_map(s, 1, 0xf0c0);
 /* PCI hole */
-memory_region_add_subregion(get_system_memory(), 0x8000ULL,
+memory_region_add_subregion(get_system_memory(), 0x8000,
 sysbus_mmio_get_region(s, 2));
 /* Register 8 MB of ISA IO space */
 memory_region_add_subregion(get_system_memory(), 0xf200,
 sysbus_mmio_get_region(s, 3));
-sysbus_mmio_map(s, 0, 0xf080);
-sysbus_mmio_map(s, 1, 0xf0c0);
-
-machine_arch = ARCH_MAC99_U3;
 } else {
+machine_arch = ARCH_MAC99;
 /* Use values found on a real PowerMac */
 /* Uninorth AGP bus */
 uninorth_agp_dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
@@ -309,22 +309,20 @@ static void ppc_core99_init(MachineState *machine)
 sysbus_mmio_map(s, 0, 0xf480);
 sysbus_mmio_map(s, 1, 0xf4c0);
 
-/* Uninorth main bus */
+/* Uninorth main bus - this must be last to make it the default */
 dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
 qdev_prop_set_uint32(dev, "ofw-addr", 0xf200);
-sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
 uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev);
 s = SYS_BUS_DEVICE(dev);
+sysbus_realize_and_unref(s, _fatal);
+sysbus_mmio_map(s, 0, 0xf280);
+sysbus_mmio_map(s, 1, 0xf2c0);
 /* PCI hole */
-memory_region_add_subregion(get_system_memory(), 0x8000ULL,
+memory_region_add_subregion(get_system_memory(), 0x8000,
 sysbus_mmio_get_region(s, 2));
 /* Register 8 MB of ISA IO space */
 memory_region_add_subregion(get_system_memory(), 0xf200,
 sysbus_mmio_get_region(s, 3));
-sysbus_mmio_map(s, 0, 0xf280);
-sysbus_mmio_map(s, 1, 0xf2c0);
-
-machine_arch = ARCH_MAC99;
 }
 
 machine->usb |= defaults_enabled() && !machine->usb_disabled;
-- 
2.30.4




[PATCH v3 05/13] mac_{old|new}world: Simplify cmdline_base calculation

2022-10-03 Thread BALATON Zoltan
By slight reorganisation we can avoid an else branch and some code
duplication which makes it easier to follow the code.

Signed-off-by: BALATON Zoltan 
---
 hw/ppc/mac_newworld.c | 6 +++---
 hw/ppc/mac_oldworld.c | 7 +++
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 6bc3bd19be..73b01e8c6d 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -194,9 +194,11 @@ static void ppc_core99_init(MachineState *machine)
  machine->kernel_filename);
 exit(1);
 }
+cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size +
+ KERNEL_GAP);
 /* load initrd */
 if (machine->initrd_filename) {
-initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + 
KERNEL_GAP);
+initrd_base = cmdline_base;
 initrd_size = load_image_targphys(machine->initrd_filename,
   initrd_base,
   machine->ram_size - initrd_base);
@@ -206,8 +208,6 @@ static void ppc_core99_init(MachineState *machine)
 exit(1);
 }
 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
-} else {
-cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + 
KERNEL_GAP);
 }
 ppc_boot_device = 'm';
 } else {
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index cb67e44081..b424729a39 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -168,10 +168,11 @@ static void ppc_heathrow_init(MachineState *machine)
  machine->kernel_filename);
 exit(1);
 }
+cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size +
+ KERNEL_GAP);
 /* load initrd */
 if (machine->initrd_filename) {
-initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size +
-KERNEL_GAP);
+initrd_base = cmdline_base;
 initrd_size = load_image_targphys(machine->initrd_filename,
   initrd_base,
   machine->ram_size - initrd_base);
@@ -181,8 +182,6 @@ static void ppc_heathrow_init(MachineState *machine)
 exit(1);
 }
 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
-} else {
-cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + 
KERNEL_GAP);
 }
 ppc_boot_device = 'm';
 } else {
-- 
2.30.4




[PATCH v3 07/13] mac_{old|new}world: Reduce number of QOM casts

2022-10-03 Thread BALATON Zoltan
By storing the device pointers in a variable with the right type the
number of QOM casts can be reduced which also makes the code more
readable.

Signed-off-by: BALATON Zoltan 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Mark Cave-Ayland 
---
 hw/ppc/mac_newworld.c | 61 ---
 hw/ppc/mac_oldworld.c | 26 --
 2 files changed, 39 insertions(+), 48 deletions(-)

diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index be2cb5f057..1abdc581fa 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -116,18 +116,16 @@ static void ppc_core99_init(MachineState *machine)
 MemoryRegion *bios = g_new(MemoryRegion, 1);
 hwaddr kernel_base = 0, initrd_base = 0, cmdline_base = 0;
 long kernel_size = 0, initrd_size = 0;
-UNINHostState *uninorth_pci;
 PCIBus *pci_bus;
-PCIDevice *macio;
-ESCCState *escc;
 bool has_pmu, has_adb;
+Object *macio;
 MACIOIDEState *macio_ide;
 BusState *adb_bus;
 MacIONVRAMState *nvr;
 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 void *fw_cfg;
 SysBusDevice *s;
-DeviceState *dev, *pic_dev;
+DeviceState *dev, *pic_dev, *uninorth_pci_dev;
 DeviceState *uninorth_internal_dev = NULL, *uninorth_agp_dev = NULL;
 hwaddr nvram_addr = 0xFFF04000;
 uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ;
@@ -229,6 +227,7 @@ static void ppc_core99_init(MachineState *machine)
 }
 
 openpic_irqs = g_new0(IrqLines, machine->smp.cpus);
+dev = DEVICE(cpu);
 for (i = 0; i < machine->smp.cpus; i++) {
 /* Mac99 IRQ connection between OpenPIC outputs pins
  * and PowerPC input pins
@@ -236,30 +235,30 @@ static void ppc_core99_init(MachineState *machine)
 switch (PPC_INPUT(env)) {
 case PPC_FLAGS_INPUT_6xx:
 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
-qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT);
+qdev_get_gpio_in(dev, PPC6xx_INPUT_INT);
 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
- qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT);
+ qdev_get_gpio_in(dev, PPC6xx_INPUT_INT);
 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
-qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_MCP);
+qdev_get_gpio_in(dev, PPC6xx_INPUT_MCP);
 /* Not connected ? */
 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
 /* Check this */
 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
-qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_HRESET);
+qdev_get_gpio_in(dev, PPC6xx_INPUT_HRESET);
 break;
 #if defined(TARGET_PPC64)
 case PPC_FLAGS_INPUT_970:
 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
-qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_INT);
+qdev_get_gpio_in(dev, PPC970_INPUT_INT);
 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
-qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_INT);
+qdev_get_gpio_in(dev, PPC970_INPUT_INT);
 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
-qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_MCP);
+qdev_get_gpio_in(dev, PPC970_INPUT_MCP);
 /* Not connected ? */
 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
 /* Check this */
 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
-qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_HRESET);
+qdev_get_gpio_in(dev, PPC970_INPUT_HRESET);
 break;
 #endif /* defined(TARGET_PPC64) */
 default:
@@ -279,9 +278,8 @@ static void ppc_core99_init(MachineState *machine)
 machine_arch = ARCH_MAC99_U3;
 /* 970 gets a U3 bus */
 /* Uninorth AGP bus */
-dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE);
-uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
-s = SYS_BUS_DEVICE(dev);
+uninorth_pci_dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE);
+s = SYS_BUS_DEVICE(uninorth_pci_dev);
 sysbus_realize_and_unref(s, _fatal);
 sysbus_mmio_map(s, 0, 0xf080);
 sysbus_mmio_map(s, 1, 0xf0c0);
@@ -310,10 +308,9 @@ static void ppc_core99_init(MachineState *machine)
 sysbus_mmio_map(s, 1, 0xf4c0);
 
 /* Uninorth main bus - this must be last to make it the default */
-dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
-qdev_prop_set_uint32(dev, "ofw-addr", 0xf200);
-uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev);
-s = SYS_BUS_DEVICE(dev);
+uninorth_pci_dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
+qdev_prop_set_uint32(uninorth_pci_dev, "ofw-addr", 0xf200);
+s = SYS_BUS_DEVICE(uninorth_pci_dev);
 sysbus_realize_and_unref(s, _fatal);
 sysbus_mmio_map(s, 0, 0xf280);
 sysbus_mmio_map(s, 1, 0xf2c0);
@@ -331,24 +328,24 

[PATCH v3 10/13] hw/ppc/mac.h: Move grackle-pcihost type declaration out to a header

2022-10-03 Thread BALATON Zoltan
Signed-off-by: BALATON Zoltan 
---
 MAINTAINERS   |  1 +
 hw/pci-host/grackle.c | 14 +--
 hw/ppc/mac.h  |  3 ---
 hw/ppc/mac_oldworld.c |  1 +
 include/hw/pci-host/grackle.h | 44 +++
 5 files changed, 47 insertions(+), 16 deletions(-)
 create mode 100644 include/hw/pci-host/grackle.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 789172b2a8..6e6819afcd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1345,6 +1345,7 @@ F: hw/intc/heathrow_pic.c
 F: hw/input/adb*
 F: include/hw/intc/heathrow_pic.h
 F: include/hw/input/adb*
+F: include/hw/pci-host/grackle.h
 F: pc-bios/qemu_vga.ndrv
 
 PReP
diff --git a/hw/pci-host/grackle.c b/hw/pci-host/grackle.c
index b05facf463..e4c7303859 100644
--- a/hw/pci-host/grackle.c
+++ b/hw/pci-host/grackle.c
@@ -24,7 +24,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "hw/pci/pci_host.h"
 #include "hw/ppc/mac.h"
 #include "hw/qdev-properties.h"
 #include "hw/pci/pci.h"
@@ -33,18 +32,7 @@
 #include "qemu/module.h"
 #include "trace.h"
 #include "qom/object.h"
-
-OBJECT_DECLARE_SIMPLE_TYPE(GrackleState, GRACKLE_PCI_HOST_BRIDGE)
-
-struct GrackleState {
-PCIHostState parent_obj;
-
-uint32_t ofw_addr;
-qemu_irq irqs[4];
-MemoryRegion pci_mmio;
-MemoryRegion pci_hole;
-MemoryRegion pci_io;
-};
+#include "hw/pci-host/grackle.h"
 
 /* Don't know if this matches real hardware, but it agrees with OHW.  */
 static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index 55cb02c990..fe77a6c6db 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -35,9 +35,6 @@
 #define KERNEL_LOAD_ADDR 0x0100
 #define KERNEL_GAP   0x0010
 
-/* Grackle PCI */
-#define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
-
 /* Mac NVRAM */
 #define TYPE_MACIO_NVRAM "macio-nvram"
 OBJECT_DECLARE_SIMPLE_TYPE(MacIONVRAMState, MACIO_NVRAM)
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index a10c884503..e1a22f8eba 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -38,6 +38,7 @@
 #include "hw/isa/isa.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
+#include "hw/pci-host/grackle.h"
 #include "hw/nvram/fw_cfg.h"
 #include "hw/char/escc.h"
 #include "hw/misc/macio/macio.h"
diff --git a/include/hw/pci-host/grackle.h b/include/hw/pci-host/grackle.h
new file mode 100644
index 00..7ad3a779f0
--- /dev/null
+++ b/include/hw/pci-host/grackle.h
@@ -0,0 +1,44 @@
+/*
+ * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
+ *
+ * Copyright (c) 2006-2007 Fabrice Bellard
+ * Copyright (c) 2007 Jocelyn Mayer
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef GRACKLE_H
+#define GRACKLE_H
+
+#include "hw/pci/pci_host.h"
+
+#define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
+OBJECT_DECLARE_SIMPLE_TYPE(GrackleState, GRACKLE_PCI_HOST_BRIDGE)
+
+struct GrackleState {
+PCIHostState parent_obj;
+
+uint32_t ofw_addr;
+qemu_irq irqs[4];
+MemoryRegion pci_mmio;
+MemoryRegion pci_hole;
+MemoryRegion pci_io;
+};
+
+#endif
-- 
2.30.4




Re: [PATCH 07/11] hw/ppc/e500: Implement pflash handling

2022-10-03 Thread B



Am 16. September 2022 17:05:13 UTC schrieb Bernhard Beschow :
>Am 16. September 2022 15:00:06 UTC schrieb Bin Meng :
>>On Thu, Sep 15, 2022 at 11:36 PM Bernhard Beschow  wrote:
>>>
>>> Allows e500 boards to have their root file system reside on flash using
>>> only builtin devices.
>>>
>>> Note that the flash memory area is only created when a -pflash argument is
>>> given, and that the size is determined by the given file. The idea is to
>>> put users into control.
>>>
>>> Signed-off-by: Bernhard Beschow 
>>> ---
>>>  docs/system/ppc/ppce500.rst | 12 +
>>>  hw/ppc/Kconfig  |  1 +
>>>  hw/ppc/e500.c   | 54 +
>>>  3 files changed, 67 insertions(+)
>>>
>>> diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
>>> index ba6bcb7314..c3f55c6f3d 100644
>>> --- a/docs/system/ppc/ppce500.rst
>>> +++ b/docs/system/ppc/ppce500.rst
>>> @@ -119,6 +119,18 @@ To boot the 32-bit Linux kernel:
>>>-initrd /path/to/rootfs.cpio \
>>>-append "root=/dev/ram"
>>>
>>> +Rather than using a root file system on ram disk, it is possible to have 
>>> it on
>>> +emulated flash. Given an ext2 image whose size must be a power of two, it 
>>> can
>>> +be used as follows:
>>> +
>>> +.. code-block:: bash
>>> +
>>> +  $ qemu-system-ppc64 -M ppce500 -cpu e500mc -smp 4 -m 2G \
>>
>>qemu-system-ppc{64|32}
>
>Will fix.
>
>>> +  -display none -serial stdio \
>>> +  -kernel vmlinux \
>>> +  -drive if=pflash,file=/path/to/rootfs.ext2,format=raw \
>>> +  -append "rootwait root=/dev/mtdblock0"
>>> +
>>>  Running U-Boot
>>>  --
>>>
>>> diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
>>> index 791fe78a50..769a1ead1c 100644
>>> --- a/hw/ppc/Kconfig
>>> +++ b/hw/ppc/Kconfig
>>> @@ -126,6 +126,7 @@ config E500
>>>  select ETSEC
>>>  select GPIO_MPC8XXX
>>>  select OPENPIC
>>> +select PFLASH_CFI01
>>>  select PLATFORM_BUS
>>>  select PPCE500_PCI
>>>  select SERIAL
>>> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
>>> index 864b6f3d92..7843a4e04b 100644
>>> --- a/hw/ppc/e500.c
>>> +++ b/hw/ppc/e500.c
>>> @@ -23,8 +23,10 @@
>>>  #include "e500-ccsr.h"
>>>  #include "net/net.h"
>>>  #include "qemu/config-file.h"
>>> +#include "hw/block/flash.h"
>>>  #include "hw/char/serial.h"
>>>  #include "hw/pci/pci.h"
>>> +#include "sysemu/block-backend-io.h"
>>>  #include "sysemu/sysemu.h"
>>>  #include "sysemu/kvm.h"
>>>  #include "sysemu/reset.h"
>>> @@ -267,6 +269,34 @@ static void sysbus_device_create_devtree(SysBusDevice 
>>> *sbdev, void *opaque)
>>>  }
>>>  }
>>>
>>> +static void create_devtree_flash(SysBusDevice *sbdev,
>>> + PlatformDevtreeData *data)
>>> +{
>>> +char *name;
>>
>>Use g_autofree
>
>Yes, good idea.
>
>>> +uint64_t num_blocks = object_property_get_uint(OBJECT(sbdev),
>>> +   "num-blocks",
>>> +   _fatal);
>>> +uint64_t sector_length = object_property_get_uint(OBJECT(sbdev),
>>> +  "sector-length",
>>> +  _fatal);
>>> +uint64_t bank_width = object_property_get_uint(OBJECT(sbdev),
>>> +   "width",
>>> +   _fatal);
>>> +hwaddr flashbase = 0;
>>> +hwaddr flashsize = num_blocks * sector_length;
>>> +void *fdt = data->fdt;
>>> +
>>> +name = g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase);
>>> +qemu_fdt_add_subnode(fdt, name);
>>> +qemu_fdt_setprop_cell(fdt, name, "#address-cells", 1);
>>> +qemu_fdt_setprop_cell(fdt, name, "#size-cells", 1);
>>
>>#address-cells and #size-cells are not needed.
>
>Will remove.
>
>>> +qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash");
>>> +qemu_fdt_setprop_sized_cells(fdt, name, "reg",
>>> + 1, flashbase, 1, flashsize);
>>> +qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width);
>>> +g_free(name);
>>> +}
>>> +
>>>  static void platform_bus_create_devtree(PPCE500MachineState *pms,
>>>  void *fdt, const char *mpic)
>>>  {
>>> @@ -276,6 +306,8 @@ static void 
>>> platform_bus_create_devtree(PPCE500MachineState *pms,
>>>  uint64_t addr = pmc->platform_bus_base;
>>>  uint64_t size = pmc->platform_bus_size;
>>>  int irq_start = pmc->platform_bus_first_irq;
>>> +SysBusDevice *sbdev;
>>> +bool ambiguous;
>>>
>>>  /* Create a /platform node that we can put all devices into */
>>>
>>> @@ -302,6 +334,13 @@ static void 
>>> platform_bus_create_devtree(PPCE500MachineState *pms,
>>>  /* Loop through all dynamic sysbus devices and create nodes for them */
>>>  foreach_dynamic_sysbus_device(sysbus_device_create_devtree, );
>>>
>>> +sbdev = 

[PATCH v3 13/13] mac_nvram: Use NVRAM_SIZE constant

2022-10-03 Thread BALATON Zoltan
The NVRAM_SIZE constant was defined but not used. Rename it to
MACIO_NVRAM_SIZE to match the device model and use it where appropriate.

Signed-off-by: BALATON Zoltan 
Reviewed-by: Mark Cave-Ayland 
---
 hw/misc/macio/macio.c| 2 +-
 hw/ppc/mac_newworld.c| 4 ++--
 include/hw/nvram/mac_nvram.h | 3 +--
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
index 93a7c7bbc8..08dbdd7fc0 100644
--- a/hw/misc/macio/macio.c
+++ b/hw/misc/macio/macio.c
@@ -226,7 +226,7 @@ static void macio_oldworld_init(Object *obj)
 
 object_initialize_child(OBJECT(s), "nvram", >nvram, TYPE_MACIO_NVRAM);
 dev = DEVICE(>nvram);
-qdev_prop_set_uint32(dev, "size", 0x2000);
+qdev_prop_set_uint32(dev, "size", MACIO_NVRAM_SIZE);
 qdev_prop_set_uint32(dev, "it_shift", 4);
 
 for (i = 0; i < 2; i++) {
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 7a12949fc1..50bbd86099 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -451,12 +451,12 @@ static void ppc_core99_init(MachineState *machine)
 nvram_addr = 0xFFE0;
 }
 dev = qdev_new(TYPE_MACIO_NVRAM);
-qdev_prop_set_uint32(dev, "size", 0x2000);
+qdev_prop_set_uint32(dev, "size", MACIO_NVRAM_SIZE);
 qdev_prop_set_uint32(dev, "it_shift", 1);
 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
 nvr = MACIO_NVRAM(dev);
-pmac_format_nvram_partition(nvr, 0x2000);
+pmac_format_nvram_partition(nvr, MACIO_NVRAM_SIZE);
 /* No PCI init: the BIOS will do it */
 
 dev = qdev_new(TYPE_FW_CFG_MEM);
diff --git a/include/hw/nvram/mac_nvram.h b/include/hw/nvram/mac_nvram.h
index baa9f6a5a6..b780aca470 100644
--- a/include/hw/nvram/mac_nvram.h
+++ b/include/hw/nvram/mac_nvram.h
@@ -29,9 +29,8 @@
 #include "exec/memory.h"
 #include "hw/sysbus.h"
 
-#define NVRAM_SIZE0x2000
+#define MACIO_NVRAM_SIZE 0x2000
 
-/* Mac NVRAM */
 #define TYPE_MACIO_NVRAM "macio-nvram"
 OBJECT_DECLARE_SIMPLE_TYPE(MacIONVRAMState, MACIO_NVRAM)
 
-- 
2.30.4




[PULL v3 00/15] x86 + misc changes for 2022-09-29

2022-10-03 Thread Paolo Bonzini
The following changes since commit 99d6b11b5b44d7dd64f4cb1973184e40a4a174f8:

  Merge tag 'pull-target-arm-20220922' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-09-26 
13:38:26 -0400)

are available in the Git repository at:

  https://gitlab.com/bonzini/qemu.git tags/for-upstream

for you to fetch changes up to cc63374a5a7c240b7d3be734ef589dabbefc7527:

  x86: re-initialize RNG seed when selecting kernel (2022-10-01 21:16:36 +0200)


* x86: re-enable rng seeding via SetupData
* x86: reinitialize RNG seed on system reboot and after kernel load
* qboot: rebuild based on latest commit
* watchdog: remove -watchdog option
* update Meson to 0.61.5, move more configure tests


Jason A. Donenfeld (5):
  x86: return modified setup_data only if read as memory, not as file
  x86: use typedef for SetupData struct
  x86: reinitialize RNG seed on system reboot
  x86: re-enable rng seeding via SetupData
  x86: re-initialize RNG seed when selecting kernel

Paolo Bonzini (9):
  qboot: rebuild based on latest commit
  configure: do not invoke as/ld directly for pc-bios/optionrom
  watchdog: remove -watchdog option
  ui: fix path to dbus-display1.h
  meson: -display dbus and CFI are incompatible
  meson: require 0.61.3
  meson: multiple names can be passed to dependency()
  configure, meson: move C++ compiler detection to meson.build
  configure, meson: move linker flag detection to meson

Ray Zhang (1):
  target/i386/kvm: fix kvmclock_current_nsec: Assertion `time.tsc_timestamp 
<= migration_tsc' failed

 configure   |  97 +++-
 docs/about/deprecated.rst   |   5 ---
 docs/about/removed-features.rst |   5 +++
 hw/i386/microvm.c   |   2 +-
 hw/i386/pc_piix.c   |   3 +-
 hw/i386/pc_q35.c|   3 +-
 hw/i386/x86.c   |  70 ++---
 hw/nvram/fw_cfg.c   |  12 ++---
 hw/watchdog/sbsa_gwdt.c |   6 ---
 hw/watchdog/watchdog.c  |  43 --
 hw/watchdog/wdt_aspeed.c|   6 ---
 hw/watchdog/wdt_diag288.c   |   6 ---
 hw/watchdog/wdt_i6300esb.c  |   6 ---
 hw/watchdog/wdt_ib700.c |   6 ---
 hw/watchdog/wdt_imx2.c  |   6 ---
 include/hw/nvram/fw_cfg.h   |  22 +
 include/sysemu/watchdog.h   |  12 -
 meson   |   2 +-
 meson.build |  74 --
 pc-bios/optionrom/Makefile  |  12 ++---
 pc-bios/qboot.rom   | Bin 65536 -> 65536 bytes
 qemu-options.hx |  33 +-
 qga/meson.build |   2 +-
 scripts/main.c  |   1 +
 softmmu/vl.c|  16 ---
 target/i386/kvm/kvm.c   |   2 +-
 tests/qtest/dbus-display-test.c |   2 +-
 ui/dbus.h   |   2 +-
 28 files changed, 159 insertions(+), 297 deletions(-)
 mode change 100644 => 100755 pc-bios/qboot.rom
 create mode 100644 scripts/main.c
-- 
2.37.3




[PULL 09/15] meson: -display dbus and CFI are incompatible

2022-10-03 Thread Paolo Bonzini
The generated skeletons for DBus call the finalize method of the parent
type using code like

G_OBJECT_CLASS (qemu_dbus_display1_chardev_skeleton_parent_class)->finalize 
(object);

However, the finalize method is defined in a shared library that is not
compiled with CFI.  Do not enable anything that uses gdbus-codegen if
--enable-cfi was specified.

Signed-off-by: Paolo Bonzini 
---
 meson.build | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index 3885fc1076..ca47ecbffe 100644
--- a/meson.build
+++ b/meson.build
@@ -487,6 +487,7 @@ meson.override_dependency('glib-2.0', glib)
 
 gio = not_found
 gdbus_codegen = not_found
+gdbus_codegen_error = '@0@ requires gdbus-codegen, please install libgio'
 if not get_option('gio').auto() or have_system
   gio = dependency('gio-2.0', required: get_option('gio'),
method: 'pkg-config', kwargs: static_kwargs)
@@ -511,6 +512,10 @@ if not get_option('gio').auto() or have_system
  version: gio.version())
   endif
 endif
+if gdbus_codegen.found() and get_option('cfi')
+  gdbus_codegen = not_found
+  gdbus_codegen_error = '@0@ uses gdbus-codegen, which does not support 
control flow integrity'
+endif
 
 lttng = not_found
 if 'ust' in get_option('trace_backends')
@@ -1676,7 +1681,7 @@ dbus_display = get_option('dbus_display') \
   .require(enable_modules,
error_message: '-display dbus requires --enable-modules') \
   .require(gdbus_codegen.found(),
-   error_message: '-display dbus requires gdbus-codegen') \
+   error_message: gdbus_codegen_error.format('-display dbus')) \
   .require(opengl.found() and gbm.found(),
error_message: '-display dbus requires epoxy/egl and gbm') \
   .allowed()
-- 
2.37.3




Re: [PULL 0/8] Trivial branch for 7.2 patches

2022-10-03 Thread Stefan Hajnoczi
On Fri, 30 Sept 2022 at 16:22, Laurent Vivier  wrote:
> Philippe Mathieu-Daudé via (1):
>   block/qcow2-bitmap: Add missing cast to silent GCC error

Hi Laurent,
This commit uses a mailing list email, probably due to DKIM/SPF issues:
Author: Philippe Mathieu-Daudé via 

I think the policy is to reject such pull requests and fix the
authorship. Could you update your pull request and resend?

Thanks!

Stefan



Re: [PATCH v3] tcg/ppc: Optimize 26-bit jumps

2022-10-03 Thread Leandro Lupori

On 9/19/22 14:56, Leandro Lupori wrote:

PowerPC64 processors handle direct branches better than indirect
ones, resulting in less stalled cycles and branch misses.

However, PPC's tb_target_set_jmp_target() was only using direct
branches for 16-bit jumps, while PowerPC64's unconditional branch
instructions are able to handle displacements of up to 26 bits.
To take advantage of this, now jumps whose displacements fit in
between 17 and 26 bits are also converted to direct branches.

Signed-off-by: Leandro Lupori 
---
v3:
   - make goto tb code 16-byte aligned
   - code cleanup



Ping?

Does v3 look good now?

Regards,
Leandro


v2: use stq to replace all instructions atomically

  tcg/ppc/tcg-target.c.inc | 105 +++
  1 file changed, 74 insertions(+), 31 deletions(-)

diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 1cbd047ab3..0cde11c3de 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -1847,44 +1847,87 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
  tcg_out32(s, insn);
  }
  
-void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,

-  uintptr_t jmp_rw, uintptr_t addr)
+static inline uint64_t make_pair(tcg_insn_unit i1, tcg_insn_unit i2)
  {
-if (TCG_TARGET_REG_BITS == 64) {
-tcg_insn_unit i1, i2;
-intptr_t tb_diff = addr - tc_ptr;
-intptr_t br_diff = addr - (jmp_rx + 4);
-uint64_t pair;
-
-/* This does not exercise the range of the branch, but we do
-   still need to be able to load the new value of TCG_REG_TB.
-   But this does still happen quite often.  */
-if (tb_diff == (int16_t)tb_diff) {
-i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
-i2 = B | (br_diff & 0x3fc);
-} else {
-intptr_t lo = (int16_t)tb_diff;
-intptr_t hi = (int32_t)(tb_diff - lo);
-assert(tb_diff == hi + lo);
-i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
-i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
-}
-#if HOST_BIG_ENDIAN
-pair = (uint64_t)i1 << 32 | i2;
+if (HOST_BIG_ENDIAN) {
+return (uint64_t)i1 << 32 | i2;
+}
+return (uint64_t)i2 << 32 | i1;
+}
+
+static inline void ppc64_replace2(uintptr_t rx, uintptr_t rw,
+tcg_insn_unit i0, tcg_insn_unit i1)
+{
+#if TCG_TARGET_REG_BITS == 64
+qatomic_set((uint64_t *)rw, make_pair(i0, i1));
+flush_idcache_range(rx, rw, 8);
  #else
-pair = (uint64_t)i2 << 32 | i1;
+qemu_build_not_reached();
  #endif
+}
  
-/* As per the enclosing if, this is ppc64.  Avoid the _Static_assert

-   within qatomic_set that would fail to build a ppc32 host.  */
-qatomic_set__nocheck((uint64_t *)jmp_rw, pair);
-flush_idcache_range(jmp_rx, jmp_rw, 8);
-} else {
+static inline void ppc64_replace4(uintptr_t rx, uintptr_t rw,
+tcg_insn_unit i0, tcg_insn_unit i1, tcg_insn_unit i2, tcg_insn_unit i3)
+{
+uint64_t p[2];
+
+p[!HOST_BIG_ENDIAN] = make_pair(i0, i1);
+p[HOST_BIG_ENDIAN] = make_pair(i2, i3);
+
+asm("mr  %%r6, %1\n\t"
+"mr  %%r7, %2\n\t"
+"stq %%r6, %0"
+: "=Q"(*(__int128 *)rw) : "r"(p[0]), "r"(p[1]) : "r6", "r7");
+flush_idcache_range(rx, rw, 16);
+}
+
+void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
+  uintptr_t jmp_rw, uintptr_t addr)
+{
+tcg_insn_unit i0, i1, i2, i3;
+intptr_t tb_diff = addr - tc_ptr;
+intptr_t br_diff = addr - (jmp_rx + 4);
+intptr_t lo, hi;
+
+if (TCG_TARGET_REG_BITS == 32) {
  intptr_t diff = addr - jmp_rx;
  tcg_debug_assert(in_range_b(diff));
  qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fc));
  flush_idcache_range(jmp_rx, jmp_rw, 4);
+return;
+}
+
+/*
+ * This does not exercise the range of the branch, but we do
+ * still need to be able to load the new value of TCG_REG_TB.
+ * But this does still happen quite often.
+ */
+if (tb_diff == (int16_t)tb_diff) {
+i0 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
+i1 = B | (br_diff & 0x3fc);
+ppc64_replace2(jmp_rx, jmp_rw, i0, i1);
+return;
+}
+
+lo = (int16_t)tb_diff;
+hi = (int32_t)(tb_diff - lo);
+assert(tb_diff == hi + lo);
+i0 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
+i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
+if (!have_isa_2_07) {
+ppc64_replace2(jmp_rx, jmp_rw, i0, i1);
+return;
+}
+
+br_diff -= 4;
+if (in_range_b(br_diff)) {
+i2 = B | (br_diff & 0x3fc);
+i3 = NOP;
+} else {
+i2 = MTSPR | RS(TCG_REG_TB) | CTR;
+i3 = BCCTR | BO_ALWAYS;
  }
+ppc64_replace4(jmp_rx, jmp_rw, i0, i1, i2, i3);
  }
  
  static void tcg_out_call_int(TCGContext *s, int lk,

@@ -2574,8 +2617,8 @@ static void tcg_out_op(TCGContext *s, 

Re: [PATCH v10 3/7] block: add block layer APIs resembling Linux ZonedBlockDevice ioctls

2022-10-03 Thread Stefan Hajnoczi
On Thu, Sep 29, 2022 at 04:36:27PM +0800, Sam Li wrote:
> Add a new zoned_host_device BlockDriver. The zoned_host_device option
> accepts only zoned host block devices. By adding zone management
> operations in this new BlockDriver, users can use the new block
> layer APIs including Report Zone and four zone management operations
> (open, close, finish, reset).
> 
> Qemu-io uses the new APIs to perform zoned storage commands of the device:
> zone_report(zrp), zone_open(zo), zone_close(zc), zone_reset(zrs),
> zone_finish(zf).
> 
> For example, to test zone_report, use following command:
> $ ./build/qemu-io --image-opts -n driver=zoned_host_device, 
> filename=/dev/nullb0
> -c "zrp offset nr_zones"
> 
> Signed-off-by: Sam Li 
> Reviewed-by: Hannes Reinecke 
> ---
>  block/block-backend.c | 146 +
>  block/file-posix.c| 340 +-
>  block/io.c|  41 
>  include/block/block-common.h  |   4 +
>  include/block/block-io.h  |   7 +
>  include/block/block_int-common.h  |  24 +++
>  include/block/raw-aio.h   |   6 +-
>  include/sysemu/block-backend-io.h |  17 ++
>  meson.build   |   4 +
>  qapi/block-core.json  |   8 +-
>  qemu-io-cmds.c| 148 +
>  11 files changed, 741 insertions(+), 4 deletions(-)
> 
> diff --git a/block/block-backend.c b/block/block-backend.c
> index d4a5df2ac2..f7f7acd6f4 100644
> --- a/block/block-backend.c
> +++ b/block/block-backend.c
> @@ -1431,6 +1431,15 @@ typedef struct BlkRwCo {
>  void *iobuf;
>  int ret;
>  BdrvRequestFlags flags;
> +union {
> +struct {
> +unsigned int *nr_zones;
> +BlockZoneDescriptor *zones;
> +} zone_report;
> +struct {
> +BlockZoneOp op;
> +} zone_mgmt;
> +};
>  } BlkRwCo;
>  
>  int blk_make_zero(BlockBackend *blk, BdrvRequestFlags flags)
> @@ -1775,6 +1784,143 @@ int coroutine_fn blk_co_flush(BlockBackend *blk)
>  return ret;
>  }
>  
> +static void blk_aio_zone_report_entry(void *opaque) {


The coroutine_fn annotation is missing:

  static void coroutine_fn blk_aio_zone_report_entry(void *opaque) {

> +BlkAioEmAIOCB *acb = opaque;
> +BlkRwCo *rwco = >rwco;
> +
> +rwco->ret = blk_co_zone_report(rwco->blk, rwco->offset,
> +   rwco->zone_report.nr_zones,
> +   rwco->zone_report.zones);
> +blk_aio_complete(acb);
> +}
> +
> +BlockAIOCB *blk_aio_zone_report(BlockBackend *blk, int64_t offset,
> +unsigned int *nr_zones,
> +BlockZoneDescriptor  *zones,
> +BlockCompletionFunc *cb, void *opaque)
> +{
> +BlkAioEmAIOCB *acb;
> +Coroutine *co;
> +IO_CODE();
> +
> +blk_inc_in_flight(blk);
> +acb = blk_aio_get(_aio_em_aiocb_info, blk, cb, opaque);
> +acb->rwco = (BlkRwCo) {
> +.blk= blk,
> +.offset = offset,
> +.ret= NOT_DONE,
> +.zone_report = {
> +.zones = zones,
> +.nr_zones = nr_zones,
> +},
> +};
> +acb->has_returned = false;
> +
> +co = qemu_coroutine_create(blk_aio_zone_report_entry, acb);
> +bdrv_coroutine_enter(blk_bs(blk), co);
> +
> +acb->has_returned = true;
> +if (acb->rwco.ret != NOT_DONE) {
> +replay_bh_schedule_oneshot_event(blk_get_aio_context(blk),
> + blk_aio_complete_bh, acb);
> +}
> +
> +return >common;
> +}
> +
> +static void blk_aio_zone_mgmt_entry(void *opaque) {

coroutine_fn is missing here.

> +BlkAioEmAIOCB *acb = opaque;
> +BlkRwCo *rwco = >rwco;
> +
> +rwco->ret = blk_co_zone_mgmt(rwco->blk, rwco->zone_mgmt.op,
> + rwco->offset, acb->bytes);
> +blk_aio_complete(acb);
> +}
> +
> +BlockAIOCB *blk_aio_zone_mgmt(BlockBackend *blk, BlockZoneOp op,
> +  int64_t offset, int64_t len,
> +  BlockCompletionFunc *cb, void *opaque) {
> +BlkAioEmAIOCB *acb;
> +Coroutine *co;
> +IO_CODE();
> +
> +blk_inc_in_flight(blk);
> +acb = blk_aio_get(_aio_em_aiocb_info, blk, cb, opaque);
> +acb->rwco = (BlkRwCo) {
> +.blk= blk,
> +.offset = offset,
> +.ret= NOT_DONE,
> +.zone_mgmt = {
> +.op = op,
> +},
> +};
> +acb->bytes = len;
> +acb->has_returned = false;
> +
> +co = qemu_coroutine_create(blk_aio_zone_mgmt_entry, acb);
> +bdrv_coroutine_enter(blk_bs(blk), co);
> +
> +acb->has_returned = true;
> +if (acb->rwco.ret != NOT_DONE) {
> +replay_bh_schedule_oneshot_event(blk_get_aio_context(blk),
> + blk_aio_complete_bh, acb);
> +}
> +
> +return >common;
> +}
> +
> +/*
> + * Send a zone_report command.

[PULL v3 0/4] Hexagon (target/hexagon) improve store handling and gen_tcg_funcs.py

2022-10-03 Thread Taylor Simpson
The following changes since commit c8de6ec63d766ca1998c5af468483ce912fdc0c2:

  Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into 
staging (2022-09-28 17:04:11 -0400)

are available in the Git repository at:

  https://github.com/quic/qemu tags/pull-hex-20221003

for you to fetch changes up to 772b3eb4b4fe15f0595bd95923778a5a0f3558cc:

  Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on A_CVI_NEW 
(2022-10-03 11:07:44 -0700)


 Changes in v3 
Add patch from Matheus Tavares Bernardino
 Changes in v2 
Reorder patches so intermediate patch builds/tests properly

Make store handling faster and more robust
Bug fix in gen_tcg_funcs.py


Matheus Tavares Bernardino (1):
  Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on A_CVI_NEW

Taylor Simpson (3):
  Hexagon (target/hexagon) add instruction attributes from archlib
  Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01]
  Hexagon (target/hexagon) move store size tracking to translation

 target/hexagon/macros.h   |   8 +--
 target/hexagon/attribs_def.h.inc  |  38 ++-
 target/hexagon/decode.c   |  13 ++--
 target/hexagon/genptr.c   |  36 --
 target/hexagon/translate.c|  35 --
 target/hexagon/gen_tcg_funcs.py   |   2 +-
 target/hexagon/hex_common.py  |   3 +-
 target/hexagon/imported/ldst.idef | 122 +-
 target/hexagon/imported/subinsns.idef |  72 ++--
 9 files changed, 192 insertions(+), 137 deletions(-)


Re: [PATCH v2] mips/malta: pass RNG seed to to kernel via env var

2022-10-03 Thread Jason A. Donenfeld
On Mon, Oct 03, 2022 at 12:36:27PM +0200, Jason A. Donenfeld wrote:
> As of the kernel commit linked below, Linux ingests an RNG seed
> passed from the hypervisor. So, pass this for the Malta platform, and
> reinitialize it on reboot too, so that it's always fresh.
> 
> Cc: Philippe Mathieu-Daudé 
> Cc: Jiaxun Yang 
> Cc: Aurelien Jarno 
> Link: https://git.kernel.org/mips/c/056a68cea01

FYI, the kernel side of things has now been merged to Linus' tree and
will be in 6.1-rc1: https://git.kernel.org/torvalds/c/056a68cea01 (Still
waiting on this QEMU patch obviously).

Jason



[PULL v3 2/4] Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01]

2022-10-03 Thread Taylor Simpson
We have found cases where pkt_has_store_s[01] is set incorrectly.
This leads to generating an unnecessary store that is left over
from a previous packet.

Add an attribute to determine if an instruction is a scalar store
The attribute is attached to the fSTORE macro (hex_common.py)
Update the logic in decode.c that sets pkt_has_store_s[01]

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <20220920080746.26791-4-tsimp...@quicinc.com>
---
 target/hexagon/attribs_def.h.inc |  1 +
 target/hexagon/decode.c  | 13 -
 target/hexagon/translate.c   | 10 ++
 target/hexagon/hex_common.py |  3 ++-
 4 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index 222ad95fb0..5d2a102c18 100644
--- a/target/hexagon/attribs_def.h.inc
+++ b/target/hexagon/attribs_def.h.inc
@@ -44,6 +44,7 @@ DEF_ATTRIB(MEMSIZE_1B, "Memory width is 1 byte", "", "")
 DEF_ATTRIB(MEMSIZE_2B, "Memory width is 2 bytes", "", "")
 DEF_ATTRIB(MEMSIZE_4B, "Memory width is 4 bytes", "", "")
 DEF_ATTRIB(MEMSIZE_8B, "Memory width is 8 bytes", "", "")
+DEF_ATTRIB(SCALAR_STORE, "Store is scalar", "", "")
 DEF_ATTRIB(REGWRSIZE_1B, "Memory width is 1 byte", "", "")
 DEF_ATTRIB(REGWRSIZE_2B, "Memory width is 2 bytes", "", "")
 DEF_ATTRIB(REGWRSIZE_4B, "Memory width is 4 bytes", "", "")
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index 6f0f27b4ba..6b73b5c60c 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights 
Reserved.
+ *  Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights 
Reserved.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -402,10 +402,13 @@ static void decode_set_insn_attr_fields(Packet *pkt)
 }
 
 if (GET_ATTRIB(opcode, A_STORE)) {
-if (pkt->insn[i].slot == 0) {
-pkt->pkt_has_store_s0 = true;
-} else {
-pkt->pkt_has_store_s1 = true;
+if (GET_ATTRIB(opcode, A_SCALAR_STORE) &&
+!GET_ATTRIB(opcode, A_MEMSIZE_0B)) {
+if (pkt->insn[i].slot == 0) {
+pkt->pkt_has_store_s0 = true;
+} else {
+pkt->pkt_has_store_s1 = true;
+}
 }
 }
 
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 0e8a0772f7..b6b834b4ee 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights 
Reserved.
+ *  Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights 
Reserved.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -499,10 +499,12 @@ static void process_store_log(DisasContext *ctx, Packet 
*pkt)
  *  slot 1 and then slot 0.  This will be important when
  *  the memory accesses overlap.
  */
-if (pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa) {
+if (pkt->pkt_has_store_s1) {
+g_assert(!pkt->pkt_has_dczeroa);
 process_store(ctx, pkt, 1);
 }
-if (pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa) {
+if (pkt->pkt_has_store_s0) {
+g_assert(!pkt->pkt_has_dczeroa);
 process_store(ctx, pkt, 0);
 }
 }
@@ -665,7 +667,7 @@ static void gen_commit_packet(CPUHexagonState *env, 
DisasContext *ctx,
  * The dczeroa will be the store in slot 0, check that we don't have
  * a store in slot 1 or an HVX store.
  */
-g_assert(has_store_s0 && !has_store_s1 && !has_hvx_store);
+g_assert(!has_store_s1 && !has_hvx_store);
 process_dczeroa(ctx, pkt);
 } else if (has_hvx_store) {
 TCGv mem_idx = tcg_constant_tl(ctx->mem_idx);
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index c81aca8d2a..d9ba7df786 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 ##
-##  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights 
Reserved.
+##  Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights 
Reserved.
 ##
 ##  This program is free software; you can redistribute it and/or modify
 ##  it under the terms of the GNU General Public License as published by
@@ -75,6 +75,7 @@ def calculate_attribs():
 add_qemu_macro_attrib('fWRITE_P3', 'A_WRITES_PRED_REG')
 add_qemu_macro_attrib('fSET_OVERFLOW', 'A_IMPLICIT_WRITES_USR')
 add_qemu_macro_attrib('fSET_LPCFG', 'A_IMPLICIT_WRITES_USR')
+add_qemu_macro_attrib('fSTORE', 'A_SCALAR_STORE')
 
 # Recurse down macros, find attributes from sub-macros
 macroValues = list(macros.values())
-- 
2.17.1


[PULL v3 3/4] Hexagon (target/hexagon) move store size tracking to translation

2022-10-03 Thread Taylor Simpson
The store width is needed for packet commit, so it is stored in
ctx->store_width.  Currently, it is set when a store has a TCG
override instead of a QEMU helper.  In the QEMU helper case, the
ctx->store_width is not set, we invoke a helper during packet commit
that uses the runtime store width.

This patch ensures ctx->store_width is set for all store instructions,
so performance is improved because packet commit can generate the proper
TCG store rather than the generic helper.

We do this by
- Use the attributes from the instructions during translation to
  set ctx->store_width
- Remove setting of ctx->store_width from genptr.c

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <20220920080746.26791-3-tsimp...@quicinc.com>
---
 target/hexagon/macros.h|  8 
 target/hexagon/genptr.c| 36 
 target/hexagon/translate.c | 25 +
 3 files changed, 41 insertions(+), 28 deletions(-)

diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 92eb8bbf05..c8805bdaeb 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -156,7 +156,7 @@
 __builtin_choose_expr(TYPE_TCGV(X), \
 gen_store1, (void)0))
 #define MEM_STORE1(VA, DATA, SLOT) \
-MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT)
+MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 
 #define MEM_STORE2_FUNC(X) \
 __builtin_choose_expr(TYPE_INT(X), \
@@ -164,7 +164,7 @@
 __builtin_choose_expr(TYPE_TCGV(X), \
 gen_store2, (void)0))
 #define MEM_STORE2(VA, DATA, SLOT) \
-MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT)
+MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 
 #define MEM_STORE4_FUNC(X) \
 __builtin_choose_expr(TYPE_INT(X), \
@@ -172,7 +172,7 @@
 __builtin_choose_expr(TYPE_TCGV(X), \
 gen_store4, (void)0))
 #define MEM_STORE4(VA, DATA, SLOT) \
-MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT)
+MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 
 #define MEM_STORE8_FUNC(X) \
 __builtin_choose_expr(TYPE_INT(X), \
@@ -180,7 +180,7 @@
 __builtin_choose_expr(TYPE_TCGV_I64(X), \
 gen_store8, (void)0))
 #define MEM_STORE8(VA, DATA, SLOT) \
-MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT)
+MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 #else
 #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA))
 #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA))
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 8a334ba07b..806d0974ff 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -401,62 +401,50 @@ static inline void gen_store32(TCGv vaddr, TCGv src, int 
width, int slot)
 tcg_gen_mov_tl(hex_store_val32[slot], src);
 }
 
-static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src,
-  DisasContext *ctx, int slot)
+static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, int slot)
 {
 gen_store32(vaddr, src, 1, slot);
-ctx->store_width[slot] = 1;
 }
 
-static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
-   DisasContext *ctx, int slot)
+static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, int 
slot)
 {
 TCGv tmp = tcg_constant_tl(src);
-gen_store1(cpu_env, vaddr, tmp, ctx, slot);
+gen_store1(cpu_env, vaddr, tmp, slot);
 }
 
-static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src,
-  DisasContext *ctx, int slot)
+static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, int slot)
 {
 gen_store32(vaddr, src, 2, slot);
-ctx->store_width[slot] = 2;
 }
 
-static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
-   DisasContext *ctx, int slot)
+static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, int 
slot)
 {
 TCGv tmp = tcg_constant_tl(src);
-gen_store2(cpu_env, vaddr, tmp, ctx, slot);
+gen_store2(cpu_env, vaddr, tmp, slot);
 }
 
-static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src,
-  DisasContext *ctx, int slot)
+static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, int slot)
 {
 gen_store32(vaddr, src, 4, slot);
-ctx->store_width[slot] = 4;
 }
 
-static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
-   DisasContext *ctx, int slot)
+static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, int 
slot)
 {
 TCGv tmp = tcg_constant_tl(src);
-gen_store4(cpu_env, vaddr, tmp, ctx, slot);
+gen_store4(cpu_env, vaddr, tmp, slot);
 }
 
-static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
-  DisasContext *ctx, int slot)
+static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, int 
slot)
 {
 

[PULL v3 4/4] Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on A_CVI_NEW

2022-10-03 Thread Taylor Simpson
From: Matheus Tavares Bernardino 

Hexagon instructions with the A_CVI_NEW attribute produce a vector value
that can be used in the same packet. The python function responsible for
generating code for such instructions has a typo ("if" instead of
"elif"), which makes genptr_dst_write_ext() be executed twice, thus also
generating the same tcg code twice. Fortunately, this doesn't cause any
problems for correctness, but it is less efficient than it could be. Fix
it by using an "elif" and avoiding the unnecessary extra code gen.

Signed-off-by: Matheus Tavares Bernardino 
Signed-off-by: Taylor Simpson 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Reviewed-by: Taylor Simpson 
Message-Id: 

---
 target/hexagon/gen_tcg_funcs.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index d72c689ad7..6dea02b0b9 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -548,7 +548,7 @@ def genptr_dst_write_opn(f,regtype, regid, tag):
 if (hex_common.is_hvx_reg(regtype)):
 if (hex_common.is_new_result(tag)):
 genptr_dst_write_ext(f, tag, regtype, regid, "EXT_NEW")
-if (hex_common.is_tmp_result(tag)):
+elif (hex_common.is_tmp_result(tag)):
 genptr_dst_write_ext(f, tag, regtype, regid, "EXT_TMP")
 else:
 genptr_dst_write_ext(f, tag, regtype, regid, "EXT_DFL")
-- 
2.17.1



[PULL v3 1/4] Hexagon (target/hexagon) add instruction attributes from archlib

2022-10-03 Thread Taylor Simpson
The imported files from the architecture library have added some
instruction attributes.  Some of these will be used in a subsequent
patch for determing the size of a store.

Signed-off-by: Taylor Simpson 
Acked-by: Richard Henderson 
Message-Id: <20220920080746.26791-2-tsimp...@quicinc.com>
---
 target/hexagon/attribs_def.h.inc  |  37 +++-
 target/hexagon/imported/ldst.idef | 122 +-
 target/hexagon/imported/subinsns.idef |  72 +++
 3 files changed, 133 insertions(+), 98 deletions(-)

diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index dc890a557f..222ad95fb0 100644
--- a/target/hexagon/attribs_def.h.inc
+++ b/target/hexagon/attribs_def.h.inc
@@ -1,5 +1,5 @@
 /*
- *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights 
Reserved.
+ *  Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights 
Reserved.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -38,6 +38,16 @@ DEF_ATTRIB(SUBINSN, "sub-instruction", "", "")
 /* Load and Store attributes */
 DEF_ATTRIB(LOAD, "Loads from memory", "", "")
 DEF_ATTRIB(STORE, "Stores to memory", "", "")
+DEF_ATTRIB(STOREIMMED, "Stores immed to memory", "", "")
+DEF_ATTRIB(MEMSIZE_0B, "Memory width is 0 byte", "", "")
+DEF_ATTRIB(MEMSIZE_1B, "Memory width is 1 byte", "", "")
+DEF_ATTRIB(MEMSIZE_2B, "Memory width is 2 bytes", "", "")
+DEF_ATTRIB(MEMSIZE_4B, "Memory width is 4 bytes", "", "")
+DEF_ATTRIB(MEMSIZE_8B, "Memory width is 8 bytes", "", "")
+DEF_ATTRIB(REGWRSIZE_1B, "Memory width is 1 byte", "", "")
+DEF_ATTRIB(REGWRSIZE_2B, "Memory width is 2 bytes", "", "")
+DEF_ATTRIB(REGWRSIZE_4B, "Memory width is 4 bytes", "", "")
+DEF_ATTRIB(REGWRSIZE_8B, "Memory width is 8 bytes", "", "")
 DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "")
 DEF_ATTRIB(MEMLIKE_PACKET_RULES, "follows Memory-like packet rules", "", "")
 
@@ -71,6 +81,11 @@ DEF_ATTRIB(COF, "Change-of-flow instruction", "", "")
 DEF_ATTRIB(CONDEXEC, "May be cancelled by a predicate", "", "")
 DEF_ATTRIB(DOTNEWVALUE, "Uses a register value generated in this pkt", "", "")
 DEF_ATTRIB(NEWCMPJUMP, "Compound compare and jump", "", "")
+DEF_ATTRIB(NVSTORE, "New-value store", "", "")
+DEF_ATTRIB(MEMOP, "memop", "", "")
+
+DEF_ATTRIB(ROPS_2, "Compound instruction worth 2 RISC-ops", "", "")
+DEF_ATTRIB(ROPS_3, "Compound instruction worth 3 RISC-ops", "", "")
 
 /* access to implicit registers */
 DEF_ATTRIB(IMPLICIT_WRITES_LR, "Writes the link register", "", "UREG.LR")
@@ -87,6 +102,9 @@ DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", 
"UREG.P3")
 DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "")
 DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
 DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "")
+DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "")
+DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "")
+DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "")
 
 DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "")
 DEF_ATTRIB(IT_NOP, "nop instruction", "", "")
@@ -94,17 +112,21 @@ DEF_ATTRIB(IT_EXTENDER, "constant extender instruction", 
"", "")
 
 
 /* Restrictions to make note of */
+DEF_ATTRIB(RESTRICT_COF_MAX1, "One change-of-flow per packet", "", "")
+DEF_ATTRIB(RESTRICT_NOPACKET, "Not allowed in a packet", "", "")
 DEF_ATTRIB(RESTRICT_SLOT0ONLY, "Must execute on slot0", "", "")
 DEF_ATTRIB(RESTRICT_SLOT1ONLY, "Must execute on slot1", "", "")
 DEF_ATTRIB(RESTRICT_SLOT2ONLY, "Must execute on slot2", "", "")
 DEF_ATTRIB(RESTRICT_SLOT3ONLY, "Must execute on slot3", "", "")
 DEF_ATTRIB(RESTRICT_NOSLOT1, "No slot 1 instruction in parallel", "", "")
 DEF_ATTRIB(RESTRICT_PREFERSLOT0, "Try to encode into slot 0", "", "")
+DEF_ATTRIB(RESTRICT_PACKET_AXOK, "May exist with A-type or X-type", "", "")
 
 DEF_ATTRIB(ICOP, "Instruction cache op", "", "")
 
 DEF_ATTRIB(HWLOOP0_END, "Ends HW loop0", "", "")
 DEF_ATTRIB(HWLOOP1_END, "Ends HW loop1", "", "")
+DEF_ATTRIB(RET_TYPE, "return type", "", "")
 DEF_ATTRIB(DCZEROA, "dczeroa type", "", "")
 DEF_ATTRIB(ICFLUSHOP, "icflush op type", "", "")
 DEF_ATTRIB(DCFLUSHOP, "dcflush op type", "", "")
@@ -116,5 +138,18 @@ DEF_ATTRIB(L2FETCH, "Instruction is l2fetch type", "", "")
 DEF_ATTRIB(ICINVA, "icinva", "", "")
 DEF_ATTRIB(DCCLEANINVA, "dccleaninva", "", "")
 
+/* Documentation Notes */
+DEF_ATTRIB(NOTE_CONDITIONAL, "can be conditionally executed", "", "")
+DEF_ATTRIB(NOTE_NEWVAL_SLOT0, "New-value oprnd must execute on slot 0", "", "")
+DEF_ATTRIB(NOTE_PRIV, "Monitor-level feature", "", "")
+DEF_ATTRIB(NOTE_NOPACKET, "solo instruction", "", "")
+DEF_ATTRIB(NOTE_AXOK, "May only be grouped with ALU32 or non-FP XTYPE.", "", 
"")
+DEF_ATTRIB(NOTE_LATEPRED, "The predicate can not be used as a .new", "", "")
+DEF_ATTRIB(NOTE_NVSLOT0, "Can execute only in slot 0 (ST)", "", "")
+
+/* Restrictions to make note of */

[PATCH v2] hw/net: npcm7xx_emc: set MAC in register space

2022-10-03 Thread Patrick Venture
The MAC address set from Qemu wasn't being saved into the register space.

Reviewed-by: Hao Wu 
Signed-off-by: Patrick Venture 
---
v2: only set the registers from qemu on reset
once registers set, only read and write to them
---
 hw/net/npcm7xx_emc.c | 30 +++---
 1 file changed, 23 insertions(+), 7 deletions(-)

diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c
index 7c86bb52e5..a33f8c7b23 100644
--- a/hw/net/npcm7xx_emc.c
+++ b/hw/net/npcm7xx_emc.c
@@ -112,6 +112,16 @@ static void emc_reset(NPCM7xxEMCState *emc)
 
 emc->tx_active = false;
 emc->rx_active = false;
+
+/* Set the MAC address in the register space. */
+uint32_t value = (emc->conf.macaddr.a[0] << 24) |
+(emc->conf.macaddr.a[1] << 16) |
+(emc->conf.macaddr.a[2] << 8) |
+emc->conf.macaddr.a[3];
+emc->regs[REG_CAMM_BASE] = value;
+
+value = (emc->conf.macaddr.a[4] << 24) | (emc->conf.macaddr.a[5] << 16);
+emc->regs[REG_CAML_BASE] = value;
 }
 
 static void npcm7xx_emc_reset(DeviceState *dev)
@@ -432,13 +442,25 @@ static bool emc_receive_filter1(NPCM7xxEMCState *emc, 
const uint8_t *buf,
 }
 case ETH_PKT_UCAST: {
 bool matches;
+uint32_t value;
+struct MACAddr mac;
 if (emc->regs[REG_CAMCMR] & REG_CAMCMR_AUP) {
 return true;
 }
+
+value = emc->regs[REG_CAMM_BASE];
+mac.a[0] = value >> 24;
+mac.a[1] = value >> 16;
+mac.a[2] = value >> 8;
+mac.a[3] = value >> 0;
+value = emc->regs[REG_CAML_BASE];
+mac.a[4] = value >> 24;
+mac.a[5] = value >> 16;
+
 matches = ((emc->regs[REG_CAMCMR] & REG_CAMCMR_ECMP) &&
/* We only support one CAM register, CAM0. */
(emc->regs[REG_CAMEN] & (1 << 0)) &&
-   memcmp(buf, emc->conf.macaddr.a, ETH_ALEN) == 0);
+   memcmp(buf, mac.a, ETH_ALEN) == 0);
 if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) {
 *fail_reason = "MACADDR matched, comparison complemented";
 return !matches;
@@ -661,15 +683,9 @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset,
 break;
 case REG_CAMM_BASE + 0:
 emc->regs[reg] = value;
-emc->conf.macaddr.a[0] = value >> 24;
-emc->conf.macaddr.a[1] = value >> 16;
-emc->conf.macaddr.a[2] = value >> 8;
-emc->conf.macaddr.a[3] = value >> 0;
 break;
 case REG_CAML_BASE + 0:
 emc->regs[reg] = value;
-emc->conf.macaddr.a[4] = value >> 24;
-emc->conf.macaddr.a[5] = value >> 16;
 break;
 case REG_MCMDR: {
 uint32_t prev;
-- 
2.38.0.rc1.362.ged0d419d3c-goog




Conserving GitLab CI minutes - check your repo is a true fork

2022-10-03 Thread Daniel P . Berrangé
Last week the /qemu-project namespace got added to the GitLab Open Source
Program. This gives repos under that namespace extra CI minutes (50,000)
and a cost factor of 0.5, meaning in effect 100,000 minutes per month.
Primarily this applies to CI pipelines jobs the merge coordinator runs
for pull requests via the upstream staging branch.


Joining the OSS program also, however, has a benefit for people who have
forks of the /qemu-project/qemu repository.

Each user with the free plan normally gets 400 minutes of CI quota per
month [1], though some people with older gitlab.com user accounts may still
get 2,000 CI minutes / month. Note this quota is across all repos under
your /$USERNAME path in gitlab, NOT per repo.

You can check your allowance and usage at:

   https://gitlab.com/-/profile/usage_quotas#pipelines-quota-tab

Where things get complicated is the CI cost factor, which varies depending
on repo context[2].

Provided your QEMU repo is a fork of /qemu-project/qemu, its CI cost factor
should be 0.008.  IOW, if you have 400 minutes quota and only run pipelines
for QEMU, you should be able to use 50,000 minutes of wall-clock time on
shared runners.

If your QEMU repo is NOT a fork of /qemu-project/qemu, your CI cost factor
will likely be 1.  IOW, if you have 400 minutes quota you'll only get 400
minutes of wall-clock time. A QEMU CI pipeline will devour those 400 minutes
almost instantly.

IOW, it is absolutely critical that your repository is considered a fork
of /qemu-project/qemu if you intend to use CI, as it will mean you consume
CI quota x125 more slowly.

For the majority of contributors this won't be a problem, but a few may
have created their QEMU repo before /qemu-project existed on GitLab, and
thus not be considerd a fork.

To check this, go to the Gitlab web UI for your repo and check that the
header says:

" Forked from QEMU / QEMU "

just underneath the repo description.

If it does not say that, then you'll need to rename your existing repo to
a different path, and fork from /qemu-project/qemu again.

NB, if you exhaust your CI quota, it resets on the 1st of each month.


Even with the reduced 0.008 cost factor, QEMU pipelines can consume CI time
pretty quickly, so be prudent with what jobs you run.

Ensure ***ALL*** your branches are rebased to post v7.1.0 release, before
pushing to gitlab, such that they include this commit:

  commit 28357dc525b4798cdef1101cbb459afcd7233280
  Author: Daniel P. Berrangé 
  Date:   Fri May 27 16:36:02 2022 +0100

gitlab: don't run CI jobs in forks by default

This prevents CI pipelines being created merely by pushing the branch.

Also avoiding setting 'QEMU_CI=2' when running pipelines, as that triggers
every job which will burn alot of CI quota. Best is to use 'QEMU_CI=1'
which creates the pipeline but marks all jobs as manual, so you can choose
exactly which subset to run.

BTW, this largely all applies to other projects on gitlab that use CI
too. In libvirt we're switching off CI on push events too, and have also
joined the OSS Program to get forks to benefit from reduced cost factor
for CI.

With regards,
Daniel

[1] https://about.gitlab.com/pricing/

[2] https://docs.gitlab.com/ee/ci/pipelines/cicd_minutes.html#cost-factor
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|




Re: [RFC PATCH v2 11/29] target/ppc: add power-saving interrupt masking logic to p9_next_unmasked_interrupt

2022-10-03 Thread Fabiano Rosas
"Matheus K. Ferst"  writes:

> On 30/09/2022 15:38, Fabiano Rosas wrote:
>> Matheus Ferst  writes:
>> 
>>> Export p9_interrupt_powersave and use it in p9_next_unmasked_interrupt.
>>>
>>> Signed-off-by: Matheus Ferst 
>>> ---
>>> Temporarily putting the prototype in internal.h for lack of a better place,
>>> we will un-export p9_interrupt_powersave in future patches.
>>> ---
>>>   target/ppc/cpu_init.c|  2 +-
>>>   target/ppc/excp_helper.c | 46 
>>>   target/ppc/internal.h|  4 
>>>   3 files changed, 38 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
>>> index 1f8f6c6ef2..7889158c52 100644
>>> --- a/target/ppc/cpu_init.c
>>> +++ b/target/ppc/cpu_init.c
>>> @@ -6351,7 +6351,7 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass 
>>> *pcc, uint32_t pvr, bool best)
>>>   return false;
>>>   }
>>>
>>> -static int p9_interrupt_powersave(CPUPPCState *env)
>>> +int p9_interrupt_powersave(CPUPPCState *env)
>>>   {
>>>   /* External Exception */
>>>   if ((env->pending_interrupts & PPC_INTERRUPT_EXT) &&
>>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>>> index 67e73f30ab..5a0d2c11a2 100644
>>> --- a/target/ppc/excp_helper.c
>>> +++ b/target/ppc/excp_helper.c
>>> @@ -1686,28 +1686,39 @@ void ppc_cpu_do_interrupt(CPUState *cs)
>>>
>>>   static int p9_next_unmasked_interrupt(CPUPPCState *env)
>>>   {
>>> -bool async_deliver;
>>> +PowerPCCPU *cpu = env_archcpu(env);
>>> +CPUState *cs = CPU(cpu);
>>> +/* Ignore MSR[EE] when coming out of some power management states */
>>> +bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
>>>
>>>   assert((env->pending_interrupts & P9_UNUSED_INTERRUPTS) == 0);
>>>
>>> +if (cs->halted) {
>>> +if (env->spr[SPR_PSSCR] & PSSCR_EC) {
>>> +/*
>>> + * When PSSCR[EC] is set, LPCR[PECE] controls which interrupts 
>>> can
>>> + * wakeup the processor
>>> + */
>>> +return p9_interrupt_powersave(env);
>>> +} else {
>>> +/*
>>> + * When it's clear, any system-caused exception exits 
>>> power-saving
>>> + * mode, even the ones that gate on MSR[EE].
>>> + */
>>> +msr_ee = true;
>>> +}
>>> +}
>>> +
>>>   /* Machine check exception */
>>>   if (env->pending_interrupts & PPC_INTERRUPT_MCK) {
>>>   return PPC_INTERRUPT_MCK;
>>>   }
>>>
>>> -/*
>>> - * For interrupts that gate on MSR:EE, we need to do something a
>>> - * bit more subtle, as we need to let them through even when EE is
>>> - * clear when coming out of some power management states (in order
>>> - * for them to become a 0x100).
>>> - */
>>> -async_deliver = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
>>> -
>> 
>> You could simplify the code below if you bail early here when !msr_ee.
>> 
>
> The next interrupts have checks in the form
>
> if (MSR[EE] && some_condition) || (!MSR[HV] && some_other_condition)
>
> so we cannot return yet. We could check twice for these interrupts, e.g.

Ah, ok. Let's leave like it is then.

>
> if ((env->pending_interrupts & PPC_INTERRUPT_EXT) &&
>  (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) {
>  return PPC_INTERRUPT_EXT;
> }
>
> /* ... */
>
> if (!msr_ee) {
>  return 0;
> }
>
> /* ... */
>
> if ((env->pending_interrupts & PPC_INTERRUPT_EXT) &&
>  !(heic && FIELD_EX64_HV(env->msr) && !FIELD_EX64(env->msr, MSR, PR))) {
>  return PPC_INTERRUPT_EXT;
> }
>
> But I'm not sure if it'd be better.
>
>>>   /* Hypervisor decrementer exception */
>>>   if (env->pending_interrupts & PPC_INTERRUPT_HDECR) {
>>>   /* LPCR will be clear when not supported so this will work */
>>>   bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
>>> -if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) {
>>> +if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) {
>>>   /* HDEC clears on delivery */
>>>   return PPC_INTERRUPT_HDECR;
>>>   }
>>> @@ -1717,7 +1728,7 @@ static int p9_next_unmasked_interrupt(CPUPPCState 
>>> *env)
>>>   if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) {
>>>   /* LPCR will be clear when not supported so this will work */
>>>   bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
>>> -if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) {
>>> +if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hvice) {
>>>   return PPC_INTERRUPT_HVIRT;
>>>   }
>>>   }
>>> @@ -1727,13 +1738,13 @@ static int p9_next_unmasked_interrupt(CPUPPCState 
>>> *env)
>>>   bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
>>>   bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
>>>   /* HEIC blocks delivery to the hypervisor */
>>> -if ((async_deliver && !(heic && 

Re: [RFC PATCH v2 09/29] target/ppc: remove generic architecture checks from p9_deliver_interrupt

2022-10-03 Thread Fabiano Rosas
"Matheus K. Ferst"  writes:

> On 30/09/2022 15:13, Fabiano Rosas wrote:
>> Matheus Ferst  writes:
>> 
>>> No functional change intended.
>>>
>>> Signed-off-by: Matheus Ferst 
>>> ---
>>>   target/ppc/excp_helper.c | 9 +
>>>   1 file changed, 1 insertion(+), 8 deletions(-)
>>>
>>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>>> index 603c956588..67e73f30ab 100644
>>> --- a/target/ppc/excp_helper.c
>>> +++ b/target/ppc/excp_helper.c
>>> @@ -1919,18 +1919,11 @@ static void p9_deliver_interrupt(CPUPPCState *env, 
>>> int interrupt)
>>>   break;
>>>
>>>   case PPC_INTERRUPT_DECR: /* Decrementer exception */
>>> -if (ppc_decr_clear_on_delivery(env)) {
>>> -env->pending_interrupts &= ~PPC_INTERRUPT_DECR;
>>> -}
>> 
>> Maybe I'm missing something, but this should continue to clear the bit,
>> no? Same comment for P8.
>> 
>
> ppc_decr_clear_on_delivery returns true if (env->tb_env->flags & 
> (PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL)) ==
> PPC_DECR_UNDERFLOW_TRIGGERED, i.e., PPC_DECR_UNDERFLOW_TRIGGERED is set 
> and PPC_DECR_UNDERFLOW_LEVEL is clear. All Book3S CPU have a level 
> triggered interrupt, so the method return false.

You're right, I misread the code.

>
> Thanks,
> Matheus K. Ferst
> Instituto de Pesquisas ELDORADO 
> Analista de Software
> Aviso Legal - Disclaimer 









[PATCH v2 3/3] docs/system/arm/emulation.rst: Report FEAT_GTG support

2022-10-03 Thread Peter Maydell
FEAT_GTG is a change tho the ID register ID_AA64MMFR0_EL1 so that it
can report a different set of supported granule (page) sizes for
stage 1 and stage 2 translation tables.  As of commit c20281b2a5048
we already report the granule sizes that way for '-cpu max', and now
we also correctly make attempts to use unimplemented granule sizes
fail, so we can report the support of the feature in the
documentation.

Reviewed-by: Richard Henderson 
Signed-off-by: Peter Maydell 
---
 docs/system/arm/emulation.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index be7bbffe595..cfb4b0768b0 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -31,6 +31,7 @@ the following architecture extensions:
 - FEAT_FRINTTS (Floating-point to integer instructions)
 - FEAT_FlagM (Flag manipulation instructions v2)
 - FEAT_FlagM2 (Enhancements to flag manipulation instructions)
+- FEAT_GTG (Guest translation granule size)
 - FEAT_HCX (Support for the HCRX_EL2 register)
 - FEAT_HPDS (Hierarchical permission disables)
 - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
-- 
2.25.1




[PATCH v2 1/3] target/arm: Don't allow guest to use unimplemented granule sizes

2022-10-03 Thread Peter Maydell
Arm CPUs support some subset of the granule (page) sizes 4K, 16K and
64K.  The guest selects the one it wants using bits in the TCR_ELx
registers.  If it tries to program these registers with a value that
is either reserved or which requests a size that the CPU does not
implement, the architecture requires that the CPU behaves as if the
field was programmed to some size that has been implemented.
Currently we don't implement this, and instead let the guest use any
granule size, even if the CPU ID register fields say it isn't
present.

Make aa64_va_parameters() check against the supported granule size
and force use of a different one if it is not implemented.

(A subsequent commit will make ARMVAParameters use the new enum
rather than the current pair of using16k/using64k bools.)

Reviewed-by: Richard Henderson 
Signed-off-by: Peter Maydell 
---
v1->v2: rename enum to ARMGranuleSize, put it in internals.h
---
 target/arm/cpu.h   |  33 +
 target/arm/internals.h |   9 
 target/arm/helper.c| 102 +
 3 files changed, 136 insertions(+), 8 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 33cdbc0143e..6d39d27378d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4103,6 +4103,39 @@ static inline bool 
isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
 }
 
+static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
+{
+return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
+}
+
+static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
+{
+return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
+}
+
+static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
+{
+return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
+}
+
+static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
+{
+unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
+return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
+}
+
+static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
+{
+unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
+return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
+}
+
+static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
+{
+unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
+return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
+}
+
 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
 {
 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 307a5965053..0727c7e4559 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1065,6 +1065,15 @@ static inline uint32_t aarch64_pstate_valid_mask(const 
ARMISARegisters *id)
 return valid;
 }
 
+/* Granule size (i.e. page size) */
+typedef enum ARMGranuleSize {
+/* Same order as TG0 encoding */
+Gran4K,
+Gran64K,
+Gran16K,
+GranInvalid,
+} ARMGranuleSize;
+
 /*
  * Parameters of a given virtual address, as extracted from the
  * translation control register (TCR) for a given regime.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b5dac651e75..41b8435deac 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10289,20 +10289,105 @@ static int aa64_va_parameter_tcma(uint64_t tcr, 
ARMMMUIdx mmu_idx)
 }
 }
 
+static ARMGranuleSize tg0_to_gran_size(int tg)
+{
+switch (tg) {
+case 0:
+return Gran4K;
+case 1:
+return Gran64K;
+case 2:
+return Gran16K;
+default:
+return GranInvalid;
+}
+}
+
+static ARMGranuleSize tg1_to_gran_size(int tg)
+{
+switch (tg) {
+case 1:
+return Gran16K;
+case 2:
+return Gran4K;
+case 3:
+return Gran64K;
+default:
+return GranInvalid;
+}
+}
+
+static inline bool have4k(ARMCPU *cpu, bool stage2)
+{
+return stage2 ? cpu_isar_feature(aa64_tgran4_2, cpu)
+: cpu_isar_feature(aa64_tgran4, cpu);
+}
+
+static inline bool have16k(ARMCPU *cpu, bool stage2)
+{
+return stage2 ? cpu_isar_feature(aa64_tgran16_2, cpu)
+: cpu_isar_feature(aa64_tgran16, cpu);
+}
+
+static inline bool have64k(ARMCPU *cpu, bool stage2)
+{
+return stage2 ? cpu_isar_feature(aa64_tgran64_2, cpu)
+: cpu_isar_feature(aa64_tgran64, cpu);
+}
+
+static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran,
+ bool stage2)
+{
+switch (gran) {
+case Gran4K:
+if (have4k(cpu, stage2)) {
+return gran;
+}
+break;
+case Gran16K:
+if (have16k(cpu, stage2)) {
+return gran;
+}
+break;
+case Gran64K:
+if (have64k(cpu, stage2)) {
+return gran;
+}
+break;

Re: [PATCH v6 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL

2022-10-03 Thread Alex Bennée


Richard Henderson  writes:

> Changes for v6:
>   * CPUTLBEntryFull is now completely reviewed.

You should try a --disable-tcg build because I saw that failing in CI.

-- 
Alex Bennée



[PATCH v2 0/3] target/arm: Enforce implemented granule size limits

2022-10-03 Thread Peter Maydell
Arm CPUs support some subset of the granule (page) sizes 4K, 16K and
64K.  The guest selects the one it wants using bits in the TCR_ELx
registers.  If it tries to program these registers with a value that
is either reserved or which requests a size that the CPU does not
implement, the architecture requires that the CPU behaves as if the
field was programmed to some size that has been implemented.
Currently we don't implement this, and instead let the guest use any
granule size, even if the CPU ID register fields say it isn't
present.

Patch 1 in this series makes us enforce this architectural
requirement (the main effect will be that we stop incorrectly
implementing 16K granules on most of the non-cpu-max CPUs).

Patch 2 is new in v2, and extends the use of the new ARMGranuleSize
enum to the ARMVAParameters struct.

Patch 3 adds FEAT_GTG to the list of supported features, because
all this feature really is is the definition of the separate
fields for stage1 and stage2 granule support in ID_AA64MMFR0_EL1,
and we already updated -cpu max to report its granule support
that way when we were adding the LPA2 support.

v1->v2 changes:
 * renamed the enum to ARMGranuleSize, moved it to internals.h
 * new patch 2

Patch 2 is the only unreviewed one.

thanks
-- PMM

Peter Maydell (3):
  target/arm: Don't allow guest to use unimplemented granule sizes
  target/arm: Use ARMGranuleSize in ARMVAParameters
  docs/system/arm/emulation.rst: Report FEAT_GTG support

 docs/system/arm/emulation.rst |   1 +
 target/arm/cpu.h  |  33 
 target/arm/internals.h|  32 +++-
 target/arm/helper.c   | 137 +-
 target/arm/ptw.c  |   8 +-
 5 files changed, 185 insertions(+), 26 deletions(-)

-- 
2.25.1




[PATCH v2 2/3] target/arm: Use ARMGranuleSize in ARMVAParameters

2022-10-03 Thread Peter Maydell
Now we have an enum for the granule size, use it in the
ARMVAParameters struct instead of the using16k/using64k bools.

Signed-off-by: Peter Maydell 
---
 target/arm/internals.h | 23 +--
 target/arm/helper.c| 39 ---
 target/arm/ptw.c   |  8 +---
 3 files changed, 50 insertions(+), 20 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 0727c7e4559..95f654db3bc 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1074,6 +1074,26 @@ typedef enum ARMGranuleSize {
 GranInvalid,
 } ARMGranuleSize;
 
+/**
+ * arm_granule_bits: Return address size of the granule in bits
+ *
+ * Return the address size of the granule in bits. This corresponds
+ * to the pseudocode TGxGranuleBits().
+ */
+static inline int arm_granule_bits(ARMGranuleSize gran)
+{
+switch (gran) {
+case Gran64K:
+return 16;
+case Gran16K:
+return 14;
+case Gran4K:
+return 12;
+default:
+g_assert_not_reached();
+}
+}
+
 /*
  * Parameters of a given virtual address, as extracted from the
  * translation control register (TCR) for a given regime.
@@ -1086,10 +1106,9 @@ typedef struct ARMVAParameters {
 bool tbi: 1;
 bool epd: 1;
 bool hpd: 1;
-bool using16k   : 1;
-bool using64k   : 1;
 bool tsz_oob: 1;  /* tsz has been clamped to legal range */
 bool ds : 1;
+ARMGranuleSize gran : 2;
 } ARMVAParameters;
 
 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 41b8435deac..484a2d54ab8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4487,6 +4487,24 @@ typedef struct {
 uint64_t length;
 } TLBIRange;
 
+static ARMGranuleSize tlbi_range_tg_to_gran_size(int tg)
+{
+/*
+ * Note that the TLBI range TG field encoding differs from both
+ * TG0 and TG1 encodings.
+ */
+switch (tg) {
+case 1:
+return Gran4K;
+case 2:
+return Gran16K;
+case 3:
+return Gran64K;
+default:
+return GranInvalid;
+}
+}
+
 static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
  uint64_t value)
 {
@@ -4495,17 +4513,19 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, 
ARMMMUIdx mmuidx,
 uint64_t select = sextract64(value, 36, 1);
 ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true);
 TLBIRange ret = { };
+ARMGranuleSize gran;
 
 page_size_granule = extract64(value, 46, 2);
+gran = tlbi_range_tg_to_gran_size(page_size_granule);
 
 /* The granule encoded in value must match the granule in use. */
-if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) {
+if (gran != param.gran) {
 qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n",
   page_size_granule);
 return ret;
 }
 
-page_shift = (page_size_granule - 1) * 2 + 12;
+page_shift = arm_granule_bits(gran);
 num = extract64(value, 39, 5);
 scale = extract64(value, 44, 2);
 exponent = (5 * scale) + 1;
@@ -10377,7 +10397,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, 
uint64_t va,
ARMMMUIdx mmu_idx, bool data)
 {
 uint64_t tcr = regime_tcr(env, mmu_idx);
-bool epd, hpd, using16k, using64k, tsz_oob, ds;
+bool epd, hpd, tsz_oob, ds;
 int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
 ARMGranuleSize gran;
 ARMCPU *cpu = env_archcpu(env);
@@ -10421,11 +10441,9 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, 
uint64_t va,
 }
 
 gran = sanitize_gran_size(cpu, gran, stage2);
-using64k = gran == Gran64K;
-using16k = gran == Gran16K;
 
 if (cpu_isar_feature(aa64_st, cpu)) {
-max_tsz = 48 - using64k;
+max_tsz = 48 - (gran == Gran64K);
 } else {
 max_tsz = 39;
 }
@@ -10435,7 +10453,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, 
uint64_t va,
  * adjust the effective value of DS, as documented.
  */
 min_tsz = 16;
-if (using64k) {
+if (gran == Gran64K) {
 if (cpu_isar_feature(aa64_lva, cpu)) {
 min_tsz = 12;
 }
@@ -10444,14 +10462,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, 
uint64_t va,
 switch (mmu_idx) {
 case ARMMMUIdx_Stage2:
 case ARMMMUIdx_Stage2_S:
-if (using16k) {
+if (gran == Gran16K) {
 ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu);
 } else {
 ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu);
 }
 break;
 default:
-if (using16k) {
+if (gran == Gran16K) {
 ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu);
 } else {
 ds = cpu_isar_feature(aa64_tgran4_lpa2, 

Re: [RFC PATCH v2 09/29] target/ppc: remove generic architecture checks from p9_deliver_interrupt

2022-10-03 Thread Matheus K. Ferst

On 30/09/2022 15:13, Fabiano Rosas wrote:

Matheus Ferst  writes:


No functional change intended.

Signed-off-by: Matheus Ferst 
---
  target/ppc/excp_helper.c | 9 +
  1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 603c956588..67e73f30ab 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1919,18 +1919,11 @@ static void p9_deliver_interrupt(CPUPPCState *env, int 
interrupt)
  break;

  case PPC_INTERRUPT_DECR: /* Decrementer exception */
-if (ppc_decr_clear_on_delivery(env)) {
-env->pending_interrupts &= ~PPC_INTERRUPT_DECR;
-}


Maybe I'm missing something, but this should continue to clear the bit,
no? Same comment for P8.



ppc_decr_clear_on_delivery returns true if (env->tb_env->flags & 
(PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL)) ==
PPC_DECR_UNDERFLOW_TRIGGERED, i.e., PPC_DECR_UNDERFLOW_TRIGGERED is set 
and PPC_DECR_UNDERFLOW_LEVEL is clear. All Book3S CPU have a level 
triggered interrupt, so the method return false.


Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO 
Analista de Software
Aviso Legal - Disclaimer 



Re: [RFC PATCH v2 00/29] PowerPC interrupt rework

2022-10-03 Thread Matheus K. Ferst

On 28/09/2022 14:31, Cédric Le Goater wrote:

Hello Matheus,

On 9/27/22 22:15, Matheus Ferst wrote:
Link to v1: 
https://lists.gnu.org/archive/html/qemu-ppc/2022-08/msg00370.html
This series is also available as a git branch: 
https://github.com/PPC64/qemu/tree/ferst-interrupt-fix-v2


This is impressive work on QEMU PPC.


This version addresses Fabiano's feedback and fixes some issues found
with the tests suggested by Cédric. While working on it, I found two
intermittent problems on master:

  i) ~10% of boots with pSeries and 970/970mp/POWER5+ hard lockup after


These CPUs never got real attention with KVM. The FW was even broken
before 7.0.


 either SCSI or network initialization when using -smp 4. With
 -smp 2, the problem is harder to reproduce but still happens, and I
 couldn't reproduce with thread=single.
ii) ~52% of KVM guest initializations on PowerNV hang in different parts
 of the boot process when using more than one CPU.


Do you mean when the guest is SMP or the host ?


I should've added more details, this percentage was testing powernv9 
with "-smp 4" and a pSeries-POWER9 guest with "-smp 4", but I can also 
reproduce with a multithread L0 and single thread L1. The firmware is 
printing messages like:


Could not set special wakeup on 0:1: timeout waiting for SPECIAL_WKUP_DONE.

when it hangs, but I also have this message on some successful boots.




With the complete series applied, I couldn't reproduce (i) anymore,


Super ! Models are getting better. This is nice for the 970.


and (ii) became a little more frequent (~58%).


Have you checked 'info pic' ? XIVE is in charge of vCPU scheduling.


I don't have much knowledge in this area yet, so I don't know what to 
look for, but if it's useful, here is the output of the command when the 
problem occurs with a 4 core L0 and a single core L1:


(qemu) info pic
info pic
CPU[]:   QW   NSR CPPR IPB LSMFB ACK# INC AGE PIPR  W2
CPU[]: USER00   00  0000   00  00  00   00  
CPU[]:   OS00   00  00ff   ff  00  ff   ff  
CPU[]: POOL00   00  00ff   00  00  00   00  
CPU[]: PHYS00   ff  0000   00  00  00   ff  8000
CPU[0001]:   QW   NSR CPPR IPB LSMFB ACK# INC AGE PIPR  W2
CPU[0001]: USER00   00  0000   00  00  00   00  
CPU[0001]:   OS00   00  00ff   ff  00  ff   ff  
CPU[0001]: POOL00   00  00ff   00  00  00   00  0001
CPU[0001]: PHYS00   ff  0000   00  00  00   ff  8000
CPU[0002]:   QW   NSR CPPR IPB LSMFB ACK# INC AGE PIPR  W2
CPU[0002]: USER00   00  0000   00  00  00   00  
CPU[0002]:   OS00   00  00ff   ff  00  ff   ff  
CPU[0002]: POOL00   00  00ff   00  00  00   00  0002
CPU[0002]: PHYS00   ff  0000   00  00  00   ff  8000
CPU[0003]:   QW   NSR CPPR IPB LSMFB ACK# INC AGE PIPR  W2
CPU[0003]: USER00   00  0000   00  00  00   00  
CPU[0003]:   OS00   ff  0000   ff  00  ff   ff  0004
CPU[0003]: POOL00   00  00ff   00  00  00   00  0003
CPU[0003]: PHYS00   ff  0000   00  00  00   ff  8000
XIVE[0] #0 Source  .. 000f
  0014 MSI --
  0015 MSI --
  0016 MSI --
  0017 MSI --
  0018 MSI --
  0019 MSI --
  001a MSI --
  001b MSI --
  001e MSI P-
  0023 MSI --
  0024 MSI --
  0025 MSI --
  0026 MSI --
XIVE[0] #0 EAT  .. 000f
  0014   end:00/000f data:0010
  0015   end:00/0017 data:0010
  0016   end:00/001f data:0010
  0017   end:00/0027 data:0010
  0018   end:00/004e data:0010
  0019   end:00/004e data:0012
  001a   end:00/004e data:001b
  001b   end:00/004e data:0013
  001e   end:00/004e data:0016
  0023   end:00/004e data:0017
  0024   end:00/004e data:0018
  0025   end:00/004e data:0019
  0026   end:00/004e data:001a
  000fb000   end:00/001f data:0030
  000fb001   end:00/0027 data:0031
  000fb002   end:00/000f data:0032
  000fb003   end:00/000f data:0033
  000fb004   end:00/0017 data:0034
  000fb005   end:00/001f data:0035
  000fb006   end:00/0027 data:0036
  000fb7fe   end:00/000f data:0029
  000fb7ff   end:00/0017 data:002a
  000fbffe   end:00/001f data:0027
  000fbfff   end:00/0027 data:0028
  000fcffe   end:00/000f data:0025
  000fcfff   end:00/0017 data:0026
  000fd000   end:00/001f data:0037
  000fd001   end:00/000f data:0038
  000fd002   end:00/0017 data:0039
  000fd003   end:00/001f data:003a
  000fd004   end:00/0027 data:003b
  000fd7fe   end:00/001f data:0023
  000fd7ff   end:00/0027 data:0024
  000fdffe   end:00/000f data:0021
  000fdfff   end:00/0017 data:0022
  000feffe   end:00/001f data:001f
  000fefff   end:00/0027 data:0020
  0000   end:00/000f data:0011
  0001   end:00/0017 data:0012
  

Re: [RFC PATCH v2 11/29] target/ppc: add power-saving interrupt masking logic to p9_next_unmasked_interrupt

2022-10-03 Thread Matheus K. Ferst

On 30/09/2022 15:38, Fabiano Rosas wrote:

Matheus Ferst  writes:


Export p9_interrupt_powersave and use it in p9_next_unmasked_interrupt.

Signed-off-by: Matheus Ferst 
---
Temporarily putting the prototype in internal.h for lack of a better place,
we will un-export p9_interrupt_powersave in future patches.
---
  target/ppc/cpu_init.c|  2 +-
  target/ppc/excp_helper.c | 46 
  target/ppc/internal.h|  4 
  3 files changed, 38 insertions(+), 14 deletions(-)

diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 1f8f6c6ef2..7889158c52 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6351,7 +6351,7 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, 
uint32_t pvr, bool best)
  return false;
  }

-static int p9_interrupt_powersave(CPUPPCState *env)
+int p9_interrupt_powersave(CPUPPCState *env)
  {
  /* External Exception */
  if ((env->pending_interrupts & PPC_INTERRUPT_EXT) &&
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 67e73f30ab..5a0d2c11a2 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1686,28 +1686,39 @@ void ppc_cpu_do_interrupt(CPUState *cs)

  static int p9_next_unmasked_interrupt(CPUPPCState *env)
  {
-bool async_deliver;
+PowerPCCPU *cpu = env_archcpu(env);
+CPUState *cs = CPU(cpu);
+/* Ignore MSR[EE] when coming out of some power management states */
+bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;

  assert((env->pending_interrupts & P9_UNUSED_INTERRUPTS) == 0);

+if (cs->halted) {
+if (env->spr[SPR_PSSCR] & PSSCR_EC) {
+/*
+ * When PSSCR[EC] is set, LPCR[PECE] controls which interrupts can
+ * wakeup the processor
+ */
+return p9_interrupt_powersave(env);
+} else {
+/*
+ * When it's clear, any system-caused exception exits power-saving
+ * mode, even the ones that gate on MSR[EE].
+ */
+msr_ee = true;
+}
+}
+
  /* Machine check exception */
  if (env->pending_interrupts & PPC_INTERRUPT_MCK) {
  return PPC_INTERRUPT_MCK;
  }

-/*
- * For interrupts that gate on MSR:EE, we need to do something a
- * bit more subtle, as we need to let them through even when EE is
- * clear when coming out of some power management states (in order
- * for them to become a 0x100).
- */
-async_deliver = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
-


You could simplify the code below if you bail early here when !msr_ee.



The next interrupts have checks in the form

if (MSR[EE] && some_condition) || (!MSR[HV] && some_other_condition)

so we cannot return yet. We could check twice for these interrupts, e.g.

if ((env->pending_interrupts & PPC_INTERRUPT_EXT) &&
(env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) {
return PPC_INTERRUPT_EXT;
}

/* ... */

if (!msr_ee) {
return 0;
}

/* ... */

if ((env->pending_interrupts & PPC_INTERRUPT_EXT) &&
!(heic && FIELD_EX64_HV(env->msr) && !FIELD_EX64(env->msr, MSR, PR))) {
return PPC_INTERRUPT_EXT;
}

But I'm not sure if it'd be better.


  /* Hypervisor decrementer exception */
  if (env->pending_interrupts & PPC_INTERRUPT_HDECR) {
  /* LPCR will be clear when not supported so this will work */
  bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
-if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) {
+if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) {
  /* HDEC clears on delivery */
  return PPC_INTERRUPT_HDECR;
  }
@@ -1717,7 +1728,7 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
  if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) {
  /* LPCR will be clear when not supported so this will work */
  bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
-if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) {
+if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hvice) {
  return PPC_INTERRUPT_HVIRT;
  }
  }
@@ -1727,13 +1738,13 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
  bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
  bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
  /* HEIC blocks delivery to the hypervisor */
-if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) &&
+if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) &&
  !FIELD_EX64(env->msr, MSR, PR))) ||
  (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) {
  return PPC_INTERRUPT_EXT;
  }
  }
-if (async_deliver != 0) {
+if (msr_ee != 0) {
  /* Decrementer exception */
  if (env->pending_interrupts & PPC_INTERRUPT_DECR) {
  return PPC_INTERRUPT_DECR;
@@ -1895,6 +1906,15 @@ static void 

Re: [RFC PATCH v2 13/29] target/ppc: remove unused interrupts from p8_pending_interrupt

2022-10-03 Thread Matheus K. Ferst

On 27/09/2022 19:14, Fabiano Rosas wrote:

Matheus Ferst  writes:


Remove the following unused interrupts from the POWER8 interrupt masking
method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970, and POWER5p;
- Debug Interrupt: removed in Power ISA v2.07;
- Hypervisor Virtualization: introduced in Power ISA v3.0;
- Critical Input, Watchdog Timer, and Fixed Interval Timer: only defined
   for embedded CPUs;
- Hypervisor Doorbell, Doorbell, and Critical Doorbell: processor does


We still need the first two.
0xe80 - Directed hypervisor doorbell
0xa00 - Directed privileged doorbell



It seems that on PowerISA v2.07, the category for msgsnd and msgclr 
became "Embedded Processor Control" or "Book S." That's certainly not 
what we are doing in code, both instructions are behind the PPC2_PRCNTL 
flag, so they are not available for -cpu POWER8. Also, we're not 
checking for ISA 3.00 on msgsync... I'll keep these interrupts in v3 and 
send a separate patch fixing the instruction flags.


Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO 
Analista de Software
Aviso Legal - Disclaimer 



Re: [PATCH] tests/avocado: Add missing require_netdev('user') checks

2022-10-03 Thread Alex Bennée


Peter Maydell  writes:

> Some avocado tests fail if QEMU was built without libslirp. Add
> require_netdev('user') checks where necessary:
>
> These tests try to ping 10.0.2.2 and expect it to succeed:
>   boot_linux_console.py:BootLinuxConsole.test_arm_emcraft_sf2
>   boot_linux_console.py:BootLinuxConsole.test_arm_orangepi_sd
>   ppc_bamboo.py:BambooMachine.test_ppc_bamboo
>
> These tests run a commandline that includes '-net user':
>   machine_aspeed.py:AST2x00Machine.test_arm_ast2500_evb_builroot
>   (and others that use the do_test_arm_aspeed_buidroot_start()
>   or do_test_arm_aspeed_sdk_start() helper functions)
>
> These changes seem to be sufficient for 'make check-avocado'
> to not fail on a --disable-slirp build.
>
> Signed-off-by: Peter Maydell 

I was just about to write such a patch myself ;-)

Reviewed-by: Alex Bennée 

-- 
Alex Bennée



Re: [PATCH v6 13/18] accel/tcg: Do not align tb->page_addr[0]

2022-10-03 Thread Alex Bennée


Richard Henderson  writes:

> On 10/3/22 05:47, Alex Bennée wrote:
>> Richard Henderson  writes:
>> 
>>> Let tb->page_addr[0] contain the offset within the page of the
>>> start of the translation block.  We need to recover this value
>>> anyway at various points, and it is easier to discard the page
>>> offset when it's not needed, which happens naturally via the
>>> existing find_page shift.
>>>
>>> Signed-off-by: Richard Henderson 
>>> ---
>>>   accel/tcg/cpu-exec.c  | 16 
>>>   accel/tcg/cputlb.c|  3 ++-
>>>   accel/tcg/translate-all.c |  9 +
>>>   3 files changed, 15 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
>>> index 5f43b9769a..dd58a144a8 100644
>>> --- a/accel/tcg/cpu-exec.c
>>> +++ b/accel/tcg/cpu-exec.c
>>> @@ -174,7 +174,7 @@ struct tb_desc {
>>>   target_ulong pc;
>>>   target_ulong cs_base;
>>>   CPUArchState *env;
>>> -tb_page_addr_t phys_page1;
>>> +tb_page_addr_t page_addr0;
>> We don't actually document that this is an offset here (or indeed in
>> TranslationBlock) and the definition of tb_page_addr_t:
>>/* Page tracking code uses ram addresses in system mode, and
>> virtual
>>   addresses in userspace mode.  Define tb_page_addr_t to be an 
>> appropriate
>>   type.  */
>>#if defined(CONFIG_USER_ONLY)
>>typedef abi_ulong tb_page_addr_t;
>>#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx
>>#else
>>typedef ram_addr_t tb_page_addr_t;
>>#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
>>#endif
>> implies these are full size pointers into the guests address space.
>
> And that's what I've got.  What we we were storing in phys_page1
> before was a full size pointer that was page aligned.  I'm now
> dropping the page alignment and having a full size pointer to the
> exact first byte of the translated code.

OK then I'm confused by the commit message which says:

  Let tb->page_addr[0] contain the offset within the page of the
  start of the translation block

> Is that clearer?  How would you improve the wording?
>
>
> r~
>
>> Either we need a new type (tb_page_offset_t) or to properly comment the
>> structures with what they mean.
>> Otherwise:
>> Reviewed-by: Alex Bennée 
>> 


-- 
Alex Bennée



Re: [PATCH] net: improve error message for missing netdev backend

2022-10-03 Thread Christian Schoenebeck
On Montag, 3. Oktober 2022 14:50:04 CEST Daniel P. Berrangé wrote:
> On Mon, Oct 03, 2022 at 02:46:04PM +0200, Christian Schoenebeck wrote:
> > On Montag, 3. Oktober 2022 12:06:12 CEST Daniel P. Berrangé wrote:
> > > The current message when using '-net user...' with SLIRP disabled at
> > > 
> > > compile time is:
> > >   qemu-system-x86_64: -net user: Parameter 'type' expects a net backend
> > >   type
> > > 
> > > (maybe it is not compiled into this binary)
> > 
> > Is this intended as alternative to Marc-André's previous patch?
> 
> This is a patch that should be applied regardless of any other change,
> because the error message we report here today is awful and needs
> improving.
> 
> >  If yes,
> >  then
> > 
> > same applies here: what about people not passing any networking arg to
> > QEMU? They would not get any error message at all, right?
> 
> Yes, I mentioned that in the text that you've quoted below

Yeah, missed that one, sorry.

> > > An observation is that we're using the 'netdev->type' field here which
> > > is an enum value, produced after QAPI has converted from its string
> > > form.
> > > 
> > > IOW, at this point in the code, we know that the user's specified
> > > type name was a valid network backend. The only possible scenario that
> > > can make the backend init function be NULL, is if support for that
> > > backend was disabled at build time. Given this, we don't need to caveat
> > > our error message with a 'maybe' hint, we can be totally explicit.
> > > 
> > > The use of QERR_INVALID_PARAMETER_VALUE doesn't really lend itself to
> > > user friendly error message text. Since this is not used to set a
> > > specific QAPI error class, we can simply stop using this pre-formatted
> > > error text and provide something better.
> > > 
> > > Thus the new message is:
> > >   qemu-system-x86_64: -net user: network backend 'user' is not compiled
> > >   into
> > > 
> > > this binary
> > 
> > And why not naming the child, i.e. that QEMU was built without slirp?
> 
> There are several network backends that can be conditionally disabled
> at build time, and IMHO its overkill to give a different message for
> each one. This message is sufficient to show users where to go next.

Yes, but that is not a user friendly error message, especially for people who 
never dealt with QEMU's networking options before. That message does not make 
it obvious how to find the solution IMO.

What about a web link to the QEMU networking docs where this issue could then 
be clarified in a more user friendly manner? #anchors_are_cheap

> > > The case of passing 'hubport' for -net is also given a message reminding
> > > people they should have used -netdev/-nic instead, as this backend type
> > > is only valid for the modern syntax.
> > > 
> > > Signed-off-by: Daniel P. Berrangé 
> > > ---
> > > 
> > > NB, this does not make any difference to people who were relying on the
> > > QEMU built-in default hub that was created if you don't list any -net /
> > > -netdev / -nic argument, only those using explicit args.
> 
>  here.
> 
> 
> 
> With regards,
> Daniel





[PATCH] hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3

2022-10-03 Thread Jerome Forissier
According to the Linux kernel booting.rst [1], CPTR_EL3.ESM and
SCR_EL3.EnTP2 must be initialized to 1 when EL3 is present and FEAT_SME
is advertised. This has to be taken care of when QEMU boots directly
into the kernel (i.e., "-M virt,secure=on -cpu max -kernel Image").

Cc: qemu-sta...@nongnu.org
Fixes: 78cb9776662a ("target/arm: Enable SME for -cpu max")
Link: [1] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm64/booting.rst?h=v6.0#n321
Signed-off-by: Jerome Forissier 
---
 hw/arm/boot.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index ada2717f76..ee3858b673 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -763,6 +763,10 @@ static void do_cpu_reset(void *opaque)
 if (cpu_isar_feature(aa64_sve, cpu)) {
 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
 }
+if (cpu_isar_feature(aa64_sme, cpu)) {
+env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
+env->cp15.scr_el3 |= SCR_ENTP2;
+}
 /* AArch64 kernels never boot in secure mode */
 assert(!info->secure_boot);
 /* This hook is only supported for AArch32 currently:
-- 
2.34.1




Re: [PATCH] Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on A_CVI_NEW

2022-10-03 Thread Philippe Mathieu-Daudé via

On 30/9/22 22:08, Matheus Tavares Bernardino wrote:

Hexagon instructions with the A_CVI_NEW attribute produce a vector value
that can be used in the same packet. The python function responsible for
generating code for such instructions has a typo ("if" instead of
"elif"), which makes genptr_dst_write_ext() be executed twice, thus also
generating the same tcg code twice. Fortunately, this doesn't cause any
problems for correctness, but it is less efficient than it could be. Fix
it by using an "elif" and avoiding the unnecessary extra code gen.

Signed-off-by: Matheus Tavares Bernardino 
---
  target/hexagon/gen_tcg_funcs.py | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)


Reviewed-by: Philippe Mathieu-Daudé 




Re: [PATCH v5 4/9] target/arm: Change gen_exception_insn* to work on displacements

2022-10-03 Thread Philippe Mathieu-Daudé via

On 1/10/22 00:03, Richard Henderson wrote:

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.

Signed-off-by: Richard Henderson 
---
  target/arm/translate.h|  5 +++--
  target/arm/translate-a64.c| 28 ++-
  target/arm/translate-m-nocp.c |  6 ++---
  target/arm/translate-mve.c|  2 +-
  target/arm/translate-vfp.c|  6 ++---
  target/arm/translate.c| 42 +--
  6 files changed, 43 insertions(+), 46 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé 



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