Re: [PATCH v2 1/3] target/mips: Restrict semihosting to TCG

[Anton Johansson via]

On 30/05/24, Philippe Mathieu-Daudé wrote:
> Semihosting currently uses the TCG probe_access API. To prepare for
> encoding the TCG dependency in Kconfig, do not enable it unless TCG
> is available.
> 
> Suggested-by: Paolo Bonzini 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/mips/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

xtensa and m68k also `select SEMIHOSTING`, were these missed?

Otherwise for patch 1 & 2:
Reviewed-by: Anton Johansson 

Re: [PATCH v2 0/3] semihosting: Restrict to TCG

[Anton Johansson via]

On 06/06/24, Philippe Mathieu-Daudé wrote:
> Kind ping :)

I'm off today, I'll take a look tomorrow morning!:)
//Anton

Re: [PATCH 0/4] hw/s390x: Alias @dump-skeys -> @dump-s390-skey and deprecate

[Anton Johansson via]

On 30/05/24, Philippe Mathieu-Daudé wrote:
> We are trying to unify all qemu-system-FOO to a single binary.
> In order to do that we need to remove QAPI target specific code.
> 
> @dump-skeys is only available on qemu-system-s390x. This series
> rename it as @dump-s390-skey, making it available on other
> binaries. We take care of backward compatibility via deprecation.
> 
> Philippe Mathieu-Daudé (4):
>   hw/s390x: Introduce the @dump-s390-skeys QMP command
>   hw/s390x: Introduce the 'dump_s390_skeys' HMP command
>   hw/s390x: Deprecate the HMP 'dump_skeys' command
>   hw/s390x: Deprecate the QMP @dump-skeys command

Series:
Reviewed-by: Anton Johansson 

[PATCH v4 0/4] target/hexagon: Minor idef-parser cleanup

[Anton Johansson via]

Was running idef-parser with ASAN and noticed we were leaking the
init_list GArray, which is used to hold instruction arguments that may
need initialization.  This patchset fixes the leak, removes unused
macros and undefined functions, and simplifies gen_inst_init_args() to
only handle predicate values.

Changes in v2:
  * Update comment in 3rd patch
  * Follow style guide in 4th patch

Changes in v3/v4:
  * Added reviewed-bys

Anton Johansson (4):
  target/hexagon: idef-parser remove unused defines
  target/hexagon: idef-parser remove undefined functions
  target/hexagon: idef-parser fix leak of init_list
  target/hexagon: idef-parser simplify predicate init

 target/hexagon/idef-parser/idef-parser.h| 10 --
 target/hexagon/idef-parser/idef-parser.y|  2 --
 target/hexagon/idef-parser/parser-helpers.c | 35 +
 target/hexagon/idef-parser/parser-helpers.h | 13 
 4 files changed, 22 insertions(+), 38 deletions(-)

-- 
2.45.0

[PATCH v4 1/4] target/hexagon: idef-parser remove unused defines

[Anton Johansson via]

Before switching to GArray/g_string_printf we used fixed size arrays for
output buffers and instructions arguments among other things.

Macros defining the sizes of these buffers were left behind, remove
them.

Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
Reviewed-by: Brian Cain 
---
 target/hexagon/idef-parser/idef-parser.h | 10 --
 1 file changed, 10 deletions(-)

diff --git a/target/hexagon/idef-parser/idef-parser.h 
b/target/hexagon/idef-parser/idef-parser.h
index 3faa1deecd..8594cbe3a2 100644
--- a/target/hexagon/idef-parser/idef-parser.h
+++ b/target/hexagon/idef-parser/idef-parser.h
@@ -23,16 +23,6 @@
 #include 
 #include 
 
-#define TCGV_NAME_SIZE 7
-#define MAX_WRITTEN_REGS 32
-#define OFFSET_STR_LEN 32
-#define ALLOC_LIST_LEN 32
-#define ALLOC_NAME_SIZE 32
-#define INIT_LIST_LEN 32
-#define OUT_BUF_LEN (1024 * 1024)
-#define SIGNATURE_BUF_LEN (128 * 1024)
-#define HEADER_BUF_LEN (128 * 1024)
-
 /* Variadic macros to wrap the buffer printing functions */
 #define EMIT(c, ...)   
\
 do {   
\
-- 
2.45.0

[PATCH v4 2/4] target/hexagon: idef-parser remove undefined functions

[Anton Johansson via]

Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
Reviewed-by: Brian Cain 
---
 target/hexagon/idef-parser/parser-helpers.h | 13 -
 1 file changed, 13 deletions(-)

diff --git a/target/hexagon/idef-parser/parser-helpers.h 
b/target/hexagon/idef-parser/parser-helpers.h
index 7c58087169..2087d534a9 100644
--- a/target/hexagon/idef-parser/parser-helpers.h
+++ b/target/hexagon/idef-parser/parser-helpers.h
@@ -143,8 +143,6 @@ void commit(Context *c);
 
 #define OUT(c, locp, ...) FOR_EACH((c), (locp), OUT_IMPL, __VA_ARGS__)
 
-const char *cmp_swap(Context *c, YYLTYPE *locp, const char *type);
-
 /**
  * Temporary values creation
  */
@@ -236,8 +234,6 @@ HexValue gen_extract_op(Context *c,
 HexValue *index,
 HexExtract *extract);
 
-HexValue gen_read_reg(Context *c, YYLTYPE *locp, HexValue *reg);
-
 void gen_write_reg(Context *c, YYLTYPE *locp, HexValue *reg, HexValue *value);
 
 void gen_assign(Context *c,
@@ -274,13 +270,6 @@ HexValue gen_ctpop_op(Context *c, YYLTYPE *locp, HexValue 
*src);
 
 HexValue gen_rotl(Context *c, YYLTYPE *locp, HexValue *src, HexValue *n);
 
-HexValue gen_deinterleave(Context *c, YYLTYPE *locp, HexValue *mixed);
-
-HexValue gen_interleave(Context *c,
-YYLTYPE *locp,
-HexValue *odd,
-HexValue *even);
-
 HexValue gen_carry_from_add(Context *c,
 YYLTYPE *locp,
 HexValue *op1,
@@ -349,8 +338,6 @@ HexValue gen_rvalue_ternary(Context *c, YYLTYPE *locp, 
HexValue *cond,
 
 const char *cond_to_str(TCGCond cond);
 
-void emit_header(Context *c);
-
 void emit_arg(Context *c, YYLTYPE *locp, HexValue *arg);
 
 void emit_footer(Context *c);
-- 
2.45.0

[PATCH v4 3/4] target/hexagon: idef-parser fix leak of init_list

[Anton Johansson via]

gen_inst_init_args() is called for instructions using a predicate as an
rvalue. Upon first call, the list of arguments which might need
initialization init_list is freed to indicate that they have been
processed. For instructions without an rvalue predicate,
gen_inst_init_args() isn't called and init_list will never be freed.

Free init_list from free_instruction() if it hasn't already been freed.
A comment in free_instruction is also updated.

Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
Reviewed-by: Brian Cain 
---
 target/hexagon/idef-parser/parser-helpers.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/hexagon/idef-parser/parser-helpers.c 
b/target/hexagon/idef-parser/parser-helpers.c
index 95f2b43076..c150c308be 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -2121,9 +2121,16 @@ void free_instruction(Context *c)
 g_string_free(g_array_index(c->inst.strings, GString*, i), TRUE);
 }
 g_array_free(c->inst.strings, TRUE);
+/*
+ * Free list of arguments that might need initialization, if they haven't
+ * already been freed.
+ */
+if (c->inst.init_list) {
+g_array_free(c->inst.init_list, TRUE);
+}
 /* Free INAME token value */
 g_string_free(c->inst.name, TRUE);
-/* Free variables and registers */
+/* Free declared TCGv variables */
 g_array_free(c->inst.allocated, TRUE);
 /* Initialize instruction-specific portion of the context */
 memset(&(c->inst), 0, sizeof(Inst));
-- 
2.45.0

[PATCH v4 4/4] target/hexagon: idef-parser simplify predicate init

[Anton Johansson via]

Only predicate instruction arguments need to be initialized by
idef-parser. This commit removes registers from the init_list and
simplifies gen_inst_init_args() slightly.

Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
Reviewed-by: Brian Cain 
---
 target/hexagon/idef-parser/idef-parser.y|  2 --
 target/hexagon/idef-parser/parser-helpers.c | 26 +++--
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/target/hexagon/idef-parser/idef-parser.y 
b/target/hexagon/idef-parser/idef-parser.y
index cd2612eb8c..9ffb9f9699 100644
--- a/target/hexagon/idef-parser/idef-parser.y
+++ b/target/hexagon/idef-parser/idef-parser.y
@@ -233,8 +233,6 @@ code : '{' statements '}'
 argument_decl : REG
 {
 emit_arg(c, &@1, &$1);
-/* Enqueue register into initialization list */
-g_array_append_val(c->inst.init_list, $1);
 }
   | PRED
 {
diff --git a/target/hexagon/idef-parser/parser-helpers.c 
b/target/hexagon/idef-parser/parser-helpers.c
index c150c308be..a7dcd85fe4 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1652,26 +1652,28 @@ void gen_inst(Context *c, GString *iname)
 
 
 /*
- * Initialize declared but uninitialized registers, but only for
- * non-conditional instructions
+ * Initialize declared but uninitialized instruction arguments. Only needed for
+ * predicate arguments, initialization of registers is handled by the Hexagon
+ * frontend.
  */
 void gen_inst_init_args(Context *c, YYLTYPE *locp)
 {
+HexValue *val = NULL;
+char suffix;
+
+/* If init_list is NULL arguments have already been initialized */
 if (!c->inst.init_list) {
 return;
 }
 
 for (unsigned i = 0; i < c->inst.init_list->len; i++) {
-HexValue *val = _array_index(c->inst.init_list, HexValue, i);
-if (val->type == REGISTER_ARG) {
-/* Nothing to do here */
-} else if (val->type == PREDICATE) {
-char suffix = val->is_dotnew ? 'N' : 'V';
-EMIT_HEAD(c, "tcg_gen_movi_i%u(P%c%c, 0);\n", val->bit_width,
-  val->pred.id, suffix);
-} else {
-yyassert(c, locp, false, "Invalid arg type!");
-}
+val = _array_index(c->inst.init_list, HexValue, i);
+suffix = val->is_dotnew ? 'N' : 'V';
+yyassert(c, locp, val->type == PREDICATE,
+ "Only predicates need to be initialized!");
+yyassert(c, locp, val->bit_width == 32,
+ "Predicates should always be 32 bits");
+EMIT_HEAD(c, "tcg_gen_movi_i32(P%c%c, 0);\n", val->pred.id, suffix);
 }
 
 /* Free argument init list once we have initialized everything */
-- 
2.45.0

[PATCH v3 4/4] target/hexagon: idef-parser simplify predicate init

[Anton Johansson via]

Only predicate instruction arguments need to be initialized by
idef-parser. This commit removes registers from the init_list and
simplifies gen_inst_init_args() slightly.

Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/idef-parser/idef-parser.y|  2 --
 target/hexagon/idef-parser/parser-helpers.c | 26 +++--
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/target/hexagon/idef-parser/idef-parser.y 
b/target/hexagon/idef-parser/idef-parser.y
index cd2612eb8c..9ffb9f9699 100644
--- a/target/hexagon/idef-parser/idef-parser.y
+++ b/target/hexagon/idef-parser/idef-parser.y
@@ -233,8 +233,6 @@ code : '{' statements '}'
 argument_decl : REG
 {
 emit_arg(c, &@1, &$1);
-/* Enqueue register into initialization list */
-g_array_append_val(c->inst.init_list, $1);
 }
   | PRED
 {
diff --git a/target/hexagon/idef-parser/parser-helpers.c 
b/target/hexagon/idef-parser/parser-helpers.c
index c150c308be..a7dcd85fe4 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1652,26 +1652,28 @@ void gen_inst(Context *c, GString *iname)
 
 
 /*
- * Initialize declared but uninitialized registers, but only for
- * non-conditional instructions
+ * Initialize declared but uninitialized instruction arguments. Only needed for
+ * predicate arguments, initialization of registers is handled by the Hexagon
+ * frontend.
  */
 void gen_inst_init_args(Context *c, YYLTYPE *locp)
 {
+HexValue *val = NULL;
+char suffix;
+
+/* If init_list is NULL arguments have already been initialized */
 if (!c->inst.init_list) {
 return;
 }
 
 for (unsigned i = 0; i < c->inst.init_list->len; i++) {
-HexValue *val = _array_index(c->inst.init_list, HexValue, i);
-if (val->type == REGISTER_ARG) {
-/* Nothing to do here */
-} else if (val->type == PREDICATE) {
-char suffix = val->is_dotnew ? 'N' : 'V';
-EMIT_HEAD(c, "tcg_gen_movi_i%u(P%c%c, 0);\n", val->bit_width,
-  val->pred.id, suffix);
-} else {
-yyassert(c, locp, false, "Invalid arg type!");
-}
+val = _array_index(c->inst.init_list, HexValue, i);
+suffix = val->is_dotnew ? 'N' : 'V';
+yyassert(c, locp, val->type == PREDICATE,
+ "Only predicates need to be initialized!");
+yyassert(c, locp, val->bit_width == 32,
+ "Predicates should always be 32 bits");
+EMIT_HEAD(c, "tcg_gen_movi_i32(P%c%c, 0);\n", val->pred.id, suffix);
 }
 
 /* Free argument init list once we have initialized everything */
-- 
2.45.0

[PATCH v3 1/4] target/hexagon: idef-parser remove unused defines

[Anton Johansson via]

Before switching to GArray/g_string_printf we used fixed size arrays for
output buffers and instructions arguments among other things.

Macros defining the sizes of these buffers were left behind, remove
them.

Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/idef-parser/idef-parser.h | 10 --
 1 file changed, 10 deletions(-)

diff --git a/target/hexagon/idef-parser/idef-parser.h 
b/target/hexagon/idef-parser/idef-parser.h
index 3faa1deecd..8594cbe3a2 100644
--- a/target/hexagon/idef-parser/idef-parser.h
+++ b/target/hexagon/idef-parser/idef-parser.h
@@ -23,16 +23,6 @@
 #include 
 #include 
 
-#define TCGV_NAME_SIZE 7
-#define MAX_WRITTEN_REGS 32
-#define OFFSET_STR_LEN 32
-#define ALLOC_LIST_LEN 32
-#define ALLOC_NAME_SIZE 32
-#define INIT_LIST_LEN 32
-#define OUT_BUF_LEN (1024 * 1024)
-#define SIGNATURE_BUF_LEN (128 * 1024)
-#define HEADER_BUF_LEN (128 * 1024)
-
 /* Variadic macros to wrap the buffer printing functions */
 #define EMIT(c, ...)   
\
 do {   
\
-- 
2.45.0

[PATCH v3 3/4] target/hexagon: idef-parser fix leak of init_list

[Anton Johansson via]

gen_inst_init_args() is called for instructions using a predicate as an
rvalue. Upon first call, the list of arguments which might need
initialization init_list is freed to indicate that they have been
processed. For instructions without an rvalue predicate,
gen_inst_init_args() isn't called and init_list will never be freed.

Free init_list from free_instruction() if it hasn't already been freed.
A comment in free_instruction is also updated.

Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/idef-parser/parser-helpers.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/hexagon/idef-parser/parser-helpers.c 
b/target/hexagon/idef-parser/parser-helpers.c
index 95f2b43076..c150c308be 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -2121,9 +2121,16 @@ void free_instruction(Context *c)
 g_string_free(g_array_index(c->inst.strings, GString*, i), TRUE);
 }
 g_array_free(c->inst.strings, TRUE);
+/*
+ * Free list of arguments that might need initialization, if they haven't
+ * already been freed.
+ */
+if (c->inst.init_list) {
+g_array_free(c->inst.init_list, TRUE);
+}
 /* Free INAME token value */
 g_string_free(c->inst.name, TRUE);
-/* Free variables and registers */
+/* Free declared TCGv variables */
 g_array_free(c->inst.allocated, TRUE);
 /* Initialize instruction-specific portion of the context */
 memset(&(c->inst), 0, sizeof(Inst));
-- 
2.45.0

[PATCH v3 0/4] target/hexagon: Minor idef-parser cleanup

[Anton Johansson via]

Was running idef-parser with valgrind and noticed we were leaking the
init_list GArray, which is used to hold instruction arguments that may
need initialization.  This patchset fixes the leak, removes unused
macros and undefined functions, and simplifies gen_inst_init_args() to
only handle predicate values.

Changes in v2:
  * Update comment in 3rd patch
  * Follow style guide in 4th patch

Changes in v3:
  * Add reviewed-bys

Anton Johansson (4):
  target/hexagon: idef-parser remove unused defines
  target/hexagon: idef-parser remove undefined functions
  target/hexagon: idef-parser fix leak of init_list
  target/hexagon: idef-parser simplify predicate init

 target/hexagon/idef-parser/idef-parser.h| 10 --
 target/hexagon/idef-parser/idef-parser.y|  2 --
 target/hexagon/idef-parser/parser-helpers.c | 35 +
 target/hexagon/idef-parser/parser-helpers.h | 13 
 4 files changed, 22 insertions(+), 38 deletions(-)

-- 
2.45.0

[PATCH v3 2/4] target/hexagon: idef-parser remove undefined functions

[Anton Johansson via]

Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/idef-parser/parser-helpers.h | 13 -
 1 file changed, 13 deletions(-)

diff --git a/target/hexagon/idef-parser/parser-helpers.h 
b/target/hexagon/idef-parser/parser-helpers.h
index 7c58087169..2087d534a9 100644
--- a/target/hexagon/idef-parser/parser-helpers.h
+++ b/target/hexagon/idef-parser/parser-helpers.h
@@ -143,8 +143,6 @@ void commit(Context *c);
 
 #define OUT(c, locp, ...) FOR_EACH((c), (locp), OUT_IMPL, __VA_ARGS__)
 
-const char *cmp_swap(Context *c, YYLTYPE *locp, const char *type);
-
 /**
  * Temporary values creation
  */
@@ -236,8 +234,6 @@ HexValue gen_extract_op(Context *c,
 HexValue *index,
 HexExtract *extract);
 
-HexValue gen_read_reg(Context *c, YYLTYPE *locp, HexValue *reg);
-
 void gen_write_reg(Context *c, YYLTYPE *locp, HexValue *reg, HexValue *value);
 
 void gen_assign(Context *c,
@@ -274,13 +270,6 @@ HexValue gen_ctpop_op(Context *c, YYLTYPE *locp, HexValue 
*src);
 
 HexValue gen_rotl(Context *c, YYLTYPE *locp, HexValue *src, HexValue *n);
 
-HexValue gen_deinterleave(Context *c, YYLTYPE *locp, HexValue *mixed);
-
-HexValue gen_interleave(Context *c,
-YYLTYPE *locp,
-HexValue *odd,
-HexValue *even);
-
 HexValue gen_carry_from_add(Context *c,
 YYLTYPE *locp,
 HexValue *op1,
@@ -349,8 +338,6 @@ HexValue gen_rvalue_ternary(Context *c, YYLTYPE *locp, 
HexValue *cond,
 
 const char *cond_to_str(TCGCond cond);
 
-void emit_header(Context *c);
-
 void emit_arg(Context *c, YYLTYPE *locp, HexValue *arg);
 
 void emit_footer(Context *c);
-- 
2.45.0

[PATCH v2 1/4] target/hexagon: idef-parser remove unused defines

[Anton Johansson via]

Before switching to GArray/g_string_printf we used fixed size arrays for
output buffers and instructions arguments among other things.

Macros defining the sizes of these buffers were left behind, remove
them.

Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/idef-parser/idef-parser.h | 10 --
 1 file changed, 10 deletions(-)

diff --git a/target/hexagon/idef-parser/idef-parser.h 
b/target/hexagon/idef-parser/idef-parser.h
index 3faa1deecd..8594cbe3a2 100644
--- a/target/hexagon/idef-parser/idef-parser.h
+++ b/target/hexagon/idef-parser/idef-parser.h
@@ -23,16 +23,6 @@
 #include 
 #include 
 
-#define TCGV_NAME_SIZE 7
-#define MAX_WRITTEN_REGS 32
-#define OFFSET_STR_LEN 32
-#define ALLOC_LIST_LEN 32
-#define ALLOC_NAME_SIZE 32
-#define INIT_LIST_LEN 32
-#define OUT_BUF_LEN (1024 * 1024)
-#define SIGNATURE_BUF_LEN (128 * 1024)
-#define HEADER_BUF_LEN (128 * 1024)
-
 /* Variadic macros to wrap the buffer printing functions */
 #define EMIT(c, ...)   
\
 do {   
\
-- 
2.45.0

[PATCH v2 0/4] target/hexagon: Minor idef-parser cleanup

[Anton Johansson via]

Was running idef-parser with valgrind and noticed we were leaking the
init_list GArray, which is used to hold instruction arguments that may
need initialization.  This patchset fixes the leak, removes unused
macros and undefined functions, and simplifies gen_inst_init_args() to
only handle predicate values.

Changes in v2:
  * Update comment in 3rd patch
  * Follow style guide in 4th patch

Anton Johansson (4):
  target/hexagon: idef-parser remove unused defines
  target/hexagon: idef-parser remove undefined functions
  target/hexagon: idef-parser fix leak of init_list
  target/hexagon: idef-parser simplify predicate init

 target/hexagon/idef-parser/idef-parser.h| 10 --
 target/hexagon/idef-parser/idef-parser.y|  2 --
 target/hexagon/idef-parser/parser-helpers.c | 35 +
 target/hexagon/idef-parser/parser-helpers.h | 13 
 4 files changed, 22 insertions(+), 38 deletions(-)

-- 
2.45.0

[PATCH v2 4/4] target/hexagon: idef-parser simplify predicate init

[Anton Johansson via]

Only predicate instruction arguments need to be initialized by
idef-parser. This commit removes registers from the init_list and
simplifies gen_inst_init_args() slightly.

Signed-off-by: Anton Johansson 
---
 target/hexagon/idef-parser/idef-parser.y|  2 --
 target/hexagon/idef-parser/parser-helpers.c | 26 +++--
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/target/hexagon/idef-parser/idef-parser.y 
b/target/hexagon/idef-parser/idef-parser.y
index cd2612eb8c..9ffb9f9699 100644
--- a/target/hexagon/idef-parser/idef-parser.y
+++ b/target/hexagon/idef-parser/idef-parser.y
@@ -233,8 +233,6 @@ code : '{' statements '}'
 argument_decl : REG
 {
 emit_arg(c, &@1, &$1);
-/* Enqueue register into initialization list */
-g_array_append_val(c->inst.init_list, $1);
 }
   | PRED
 {
diff --git a/target/hexagon/idef-parser/parser-helpers.c 
b/target/hexagon/idef-parser/parser-helpers.c
index c150c308be..a7dcd85fe4 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1652,26 +1652,28 @@ void gen_inst(Context *c, GString *iname)
 
 
 /*
- * Initialize declared but uninitialized registers, but only for
- * non-conditional instructions
+ * Initialize declared but uninitialized instruction arguments. Only needed for
+ * predicate arguments, initialization of registers is handled by the Hexagon
+ * frontend.
  */
 void gen_inst_init_args(Context *c, YYLTYPE *locp)
 {
+HexValue *val = NULL;
+char suffix;
+
+/* If init_list is NULL arguments have already been initialized */
 if (!c->inst.init_list) {
 return;
 }
 
 for (unsigned i = 0; i < c->inst.init_list->len; i++) {
-HexValue *val = _array_index(c->inst.init_list, HexValue, i);
-if (val->type == REGISTER_ARG) {
-/* Nothing to do here */
-} else if (val->type == PREDICATE) {
-char suffix = val->is_dotnew ? 'N' : 'V';
-EMIT_HEAD(c, "tcg_gen_movi_i%u(P%c%c, 0);\n", val->bit_width,
-  val->pred.id, suffix);
-} else {
-yyassert(c, locp, false, "Invalid arg type!");
-}
+val = _array_index(c->inst.init_list, HexValue, i);
+suffix = val->is_dotnew ? 'N' : 'V';
+yyassert(c, locp, val->type == PREDICATE,
+ "Only predicates need to be initialized!");
+yyassert(c, locp, val->bit_width == 32,
+ "Predicates should always be 32 bits");
+EMIT_HEAD(c, "tcg_gen_movi_i32(P%c%c, 0);\n", val->pred.id, suffix);
 }
 
 /* Free argument init list once we have initialized everything */
-- 
2.45.0

[PATCH v2 2/4] target/hexagon: idef-parser remove undefined functions

[Anton Johansson via]

Signed-off-by: Anton Johansson 
Reviewed-by: Taylor Simpson 
---
 target/hexagon/idef-parser/parser-helpers.h | 13 -
 1 file changed, 13 deletions(-)

diff --git a/target/hexagon/idef-parser/parser-helpers.h 
b/target/hexagon/idef-parser/parser-helpers.h
index 7c58087169..2087d534a9 100644
--- a/target/hexagon/idef-parser/parser-helpers.h
+++ b/target/hexagon/idef-parser/parser-helpers.h
@@ -143,8 +143,6 @@ void commit(Context *c);
 
 #define OUT(c, locp, ...) FOR_EACH((c), (locp), OUT_IMPL, __VA_ARGS__)
 
-const char *cmp_swap(Context *c, YYLTYPE *locp, const char *type);
-
 /**
  * Temporary values creation
  */
@@ -236,8 +234,6 @@ HexValue gen_extract_op(Context *c,
 HexValue *index,
 HexExtract *extract);
 
-HexValue gen_read_reg(Context *c, YYLTYPE *locp, HexValue *reg);
-
 void gen_write_reg(Context *c, YYLTYPE *locp, HexValue *reg, HexValue *value);
 
 void gen_assign(Context *c,
@@ -274,13 +270,6 @@ HexValue gen_ctpop_op(Context *c, YYLTYPE *locp, HexValue 
*src);
 
 HexValue gen_rotl(Context *c, YYLTYPE *locp, HexValue *src, HexValue *n);
 
-HexValue gen_deinterleave(Context *c, YYLTYPE *locp, HexValue *mixed);
-
-HexValue gen_interleave(Context *c,
-YYLTYPE *locp,
-HexValue *odd,
-HexValue *even);
-
 HexValue gen_carry_from_add(Context *c,
 YYLTYPE *locp,
 HexValue *op1,
@@ -349,8 +338,6 @@ HexValue gen_rvalue_ternary(Context *c, YYLTYPE *locp, 
HexValue *cond,
 
 const char *cond_to_str(TCGCond cond);
 
-void emit_header(Context *c);
-
 void emit_arg(Context *c, YYLTYPE *locp, HexValue *arg);
 
 void emit_footer(Context *c);
-- 
2.45.0

[PATCH v2 3/4] target/hexagon: idef-parser fix leak of init_list

[Anton Johansson via]

gen_inst_init_args() is called for instructions using a predicate as an
rvalue. Upon first call, the list of arguments which might need
initialization init_list is freed to indicate that they have been
processed. For instructions without an rvalue predicate,
gen_inst_init_args() isn't called and init_list will never be freed.

Free init_list from free_instruction() if it hasn't already been freed.
A comment in free_instruction is also updated.

Signed-off-by: Anton Johansson 
---
 target/hexagon/idef-parser/parser-helpers.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/hexagon/idef-parser/parser-helpers.c 
b/target/hexagon/idef-parser/parser-helpers.c
index 95f2b43076..c150c308be 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -2121,9 +2121,16 @@ void free_instruction(Context *c)
 g_string_free(g_array_index(c->inst.strings, GString*, i), TRUE);
 }
 g_array_free(c->inst.strings, TRUE);
+/*
+ * Free list of arguments that might need initialization, if they haven't
+ * already been freed.
+ */
+if (c->inst.init_list) {
+g_array_free(c->inst.init_list, TRUE);
+}
 /* Free INAME token value */
 g_string_free(c->inst.name, TRUE);
-/* Free variables and registers */
+/* Free declared TCGv variables */
 g_array_free(c->inst.allocated, TRUE);
 /* Initialize instruction-specific portion of the context */
 memset(&(c->inst), 0, sizeof(Inst));
-- 
2.45.0

Re: [PATCH 3/4] target/hexagon: idef-parser fix leak of init_list

['Anton Johansson' via]

On 07/05/24, ltaylorsimp...@gmail.com wrote:
> 
> 
> > -Original Message-
> > From: 'Anton Johansson' 
> > Sent: Tuesday, May 7, 2024 4:47 AM
> > To: ltaylorsimp...@gmail.com
> > Cc: qemu-devel@nongnu.org; a...@rev.ng; bc...@quicinc.com
> > Subject: Re: [PATCH 3/4] target/hexagon: idef-parser fix leak of init_list
> > 
> > On 06/05/24, ltaylorsimp...@gmail.com wrote:
> > >
> > >
> > > > -Original Message-
> > > > From: Anton Johansson 
> > > > Sent: Monday, May 6, 2024 1:31 PM
> > > > To: qemu-devel@nongnu.org
> > > > Cc: a...@rev.ng; ltaylorsimp...@gmail.com; bc...@quicinc.com
> > > > Subject: [PATCH 3/4] target/hexagon: idef-parser fix leak of
> > > > init_list
> > > >
> > > > gen_inst_init_args() is called for instructions using a predicate as
> > > > an
> > > rvalue.
> > > > Upon first call, the list of arguments which might need
> > > > initialization
> > > init_list is
> > > > freed to indicate that they have been processed. For instructions
> > > > without
> > > an
> > > > rvalue predicate,
> > > > gen_inst_init_args() isn't called and init_list will never be freed.
> > > >
> > > > Free init_list from free_instruction() if it hasn't already been freed.
> > > >
> > > > Signed-off-by: Anton Johansson 
> > > > ---
> > > >  target/hexagon/idef-parser/parser-helpers.c | 7 +++
> > > >  1 file changed, 7 insertions(+)
> > > >
> > > > diff --git a/target/hexagon/idef-parser/parser-helpers.c
> > > > b/target/hexagon/idef-parser/parser-helpers.c
> > > > index 95f2b43076..bae01c2bb8 100644
> > > > --- a/target/hexagon/idef-parser/parser-helpers.c
> > > > +++ b/target/hexagon/idef-parser/parser-helpers.c
> > > > @@ -2121,6 +2121,13 @@ void free_instruction(Context *c)
> > > >  g_string_free(g_array_index(c->inst.strings, GString*, i), 
> > > > TRUE);
> > > >  }
> > > >  g_array_free(c->inst.strings, TRUE);
> > > > +/*
> > > > + * Free list of arguments that might need initialization, if
> > > > + they
> > > haven't
> > > > + * already been free'd.
> > > > + */
> > > > +if (c->inst.init_list) {
> > > > +g_array_free(c->inst.init_list, TRUE);
> > > > +}
> > > >  /* Free INAME token value */
> > > >  g_string_free(c->inst.name, TRUE);
> > > >  /* Free variables and registers */
> > >
> > > Why not do this in gen_inst_init_args just before this?
> > >/* Free argument init list once we have initialized everything */
> > > g_array_free(c->inst.init_list, TRUE);
> > > c->inst.init_list = NULL;
> > 
> > Thanks for the reviews Taylor! I'm not sure I understand what you mean
> > here, we already free init_list in gen_inst_init_args, since 
> > gen_inst_init_args
> > won't be called for all instructions we need to also free from a common
> > place.
> > 
> > //Anton
> 
> It just seems more natural to free the elements of the array at the same 
> place you free the array itself.  If there are valid reasons for doing it 
> elsewhere, I'm OK with that.
> 
> Taylor
> 
> 

Ah I see what you mean. The array and its elements are either freed in
gen_inst_init_args or free_instruction so they do occur together. The
"freeing of variables and registers" comment only refers to declared
TCGvs and has nothing to do with the arguments.

Comment is a bit outdated so I've updated it.

//Anton

Re: [PATCH 4/4] target/hexagon: idef-parser simplify predicate init

['Anton Johansson' via]

On 06/05/24, ltaylorsimp...@gmail.com wrote:
> 
> 
> > -Original Message-
> > From: Anton Johansson 
> > Sent: Monday, May 6, 2024 1:31 PM
> > To: qemu-devel@nongnu.org
> > Cc: a...@rev.ng; ltaylorsimp...@gmail.com; bc...@quicinc.com
> > Subject: [PATCH 4/4] target/hexagon: idef-parser simplify predicate init
> > 
> > Only predicate instruction arguments need to be initialized by
> idef-parser.
> > This commit removes registers from the init_list and simplifies
> > gen_inst_init_args() slightly.
> > 
> > Signed-off-by: Anton Johansson 
> > ---
> >  target/hexagon/idef-parser/idef-parser.y|  2 --
> >  target/hexagon/idef-parser/parser-helpers.c | 20 +---
> >  2 files changed, 9 insertions(+), 13 deletions(-)
> 
> > diff --git a/target/hexagon/idef-parser/parser-helpers.c
> > b/target/hexagon/idef-parser/parser-helpers.c
> > index bae01c2bb8..33e8f82007 100644
> > --- a/target/hexagon/idef-parser/parser-helpers.c
> > +++ b/target/hexagon/idef-parser/parser-helpers.c
> > @@ -1652,26 +1652,24 @@ void gen_inst(Context *c, GString *iname)
> > 
> >  void gen_inst_init_args(Context *c, YYLTYPE *locp)  {
> > +/* If init_list is NULL arguments have already been initialized */
> >  if (!c->inst.init_list) {
> >  return;
> >  }
> > 
> >  for (unsigned i = 0; i < c->inst.init_list->len; i++) {
> >  HexValue *val = _array_index(c->inst.init_list, HexValue, i);
> > -if (val->type == REGISTER_ARG) {
> > -/* Nothing to do here */
> > -} else if (val->type == PREDICATE) {
> > -char suffix = val->is_dotnew ? 'N' : 'V';
> > -EMIT_HEAD(c, "tcg_gen_movi_i%u(P%c%c, 0);\n", val->bit_width,
> > -  val->pred.id, suffix);
> > -} else {
> > -yyassert(c, locp, false, "Invalid arg type!");
> > -}
> > +yyassert(c, locp, val->type == PREDICATE,
> > + "Only predicates need to be initialized!");
> > +char suffix = val->is_dotnew ? 'N' : 'V';
> 
> Declarations should be at the beginning of the function per QEMU coding
> standards.

Agh right!

>
> > +EMIT_HEAD(c, "tcg_gen_movi_i%u(P%c%c, 0);\n", val->bit_width,
> 
> Since you know this is a predicate, the bit_width will always be 32.  You
> can hard-code that instead of using %u.

Good point, I'll add a paranoia assertion as well.

//Anton

Re: [PATCH 3/4] target/hexagon: idef-parser fix leak of init_list

['Anton Johansson' via]

On 06/05/24, ltaylorsimp...@gmail.com wrote:
> 
> 
> > -Original Message-
> > From: Anton Johansson 
> > Sent: Monday, May 6, 2024 1:31 PM
> > To: qemu-devel@nongnu.org
> > Cc: a...@rev.ng; ltaylorsimp...@gmail.com; bc...@quicinc.com
> > Subject: [PATCH 3/4] target/hexagon: idef-parser fix leak of init_list
> > 
> > gen_inst_init_args() is called for instructions using a predicate as an
> rvalue.
> > Upon first call, the list of arguments which might need initialization
> init_list is
> > freed to indicate that they have been processed. For instructions without
> an
> > rvalue predicate,
> > gen_inst_init_args() isn't called and init_list will never be freed.
> > 
> > Free init_list from free_instruction() if it hasn't already been freed.
> > 
> > Signed-off-by: Anton Johansson 
> > ---
> >  target/hexagon/idef-parser/parser-helpers.c | 7 +++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/target/hexagon/idef-parser/parser-helpers.c
> > b/target/hexagon/idef-parser/parser-helpers.c
> > index 95f2b43076..bae01c2bb8 100644
> > --- a/target/hexagon/idef-parser/parser-helpers.c
> > +++ b/target/hexagon/idef-parser/parser-helpers.c
> > @@ -2121,6 +2121,13 @@ void free_instruction(Context *c)
> >  g_string_free(g_array_index(c->inst.strings, GString*, i), TRUE);
> >  }
> >  g_array_free(c->inst.strings, TRUE);
> > +/*
> > + * Free list of arguments that might need initialization, if they
> haven't
> > + * already been free'd.
> > + */
> > +if (c->inst.init_list) {
> > +g_array_free(c->inst.init_list, TRUE);
> > +}
> >  /* Free INAME token value */
> >  g_string_free(c->inst.name, TRUE);
> >  /* Free variables and registers */
> 
> Why not do this in gen_inst_init_args just before this?
>/* Free argument init list once we have initialized everything */
> g_array_free(c->inst.init_list, TRUE);
> c->inst.init_list = NULL;

Thanks for the reviews Taylor! I'm not sure I understand what you mean
here, we already free init_list in gen_inst_init_args, since
gen_inst_init_args won't be called for all instructions we need to also
free from a common place.

//Anton

[PATCH 2/4] target/hexagon: idef-parser remove undefined functions

[Anton Johansson via]

Signed-off-by: Anton Johansson 
---
 target/hexagon/idef-parser/parser-helpers.h | 13 -
 1 file changed, 13 deletions(-)

diff --git a/target/hexagon/idef-parser/parser-helpers.h 
b/target/hexagon/idef-parser/parser-helpers.h
index 7c58087169..2087d534a9 100644
--- a/target/hexagon/idef-parser/parser-helpers.h
+++ b/target/hexagon/idef-parser/parser-helpers.h
@@ -143,8 +143,6 @@ void commit(Context *c);
 
 #define OUT(c, locp, ...) FOR_EACH((c), (locp), OUT_IMPL, __VA_ARGS__)
 
-const char *cmp_swap(Context *c, YYLTYPE *locp, const char *type);
-
 /**
  * Temporary values creation
  */
@@ -236,8 +234,6 @@ HexValue gen_extract_op(Context *c,
 HexValue *index,
 HexExtract *extract);
 
-HexValue gen_read_reg(Context *c, YYLTYPE *locp, HexValue *reg);
-
 void gen_write_reg(Context *c, YYLTYPE *locp, HexValue *reg, HexValue *value);
 
 void gen_assign(Context *c,
@@ -274,13 +270,6 @@ HexValue gen_ctpop_op(Context *c, YYLTYPE *locp, HexValue 
*src);
 
 HexValue gen_rotl(Context *c, YYLTYPE *locp, HexValue *src, HexValue *n);
 
-HexValue gen_deinterleave(Context *c, YYLTYPE *locp, HexValue *mixed);
-
-HexValue gen_interleave(Context *c,
-YYLTYPE *locp,
-HexValue *odd,
-HexValue *even);
-
 HexValue gen_carry_from_add(Context *c,
 YYLTYPE *locp,
 HexValue *op1,
@@ -349,8 +338,6 @@ HexValue gen_rvalue_ternary(Context *c, YYLTYPE *locp, 
HexValue *cond,
 
 const char *cond_to_str(TCGCond cond);
 
-void emit_header(Context *c);
-
 void emit_arg(Context *c, YYLTYPE *locp, HexValue *arg);
 
 void emit_footer(Context *c);
-- 
2.44.0

[PATCH 4/4] target/hexagon: idef-parser simplify predicate init

[Anton Johansson via]

Only predicate instruction arguments need to be initialized by
idef-parser. This commit removes registers from the init_list and
simplifies gen_inst_init_args() slightly.

Signed-off-by: Anton Johansson 
---
 target/hexagon/idef-parser/idef-parser.y|  2 --
 target/hexagon/idef-parser/parser-helpers.c | 20 +---
 2 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/target/hexagon/idef-parser/idef-parser.y 
b/target/hexagon/idef-parser/idef-parser.y
index cd2612eb8c..9ffb9f9699 100644
--- a/target/hexagon/idef-parser/idef-parser.y
+++ b/target/hexagon/idef-parser/idef-parser.y
@@ -233,8 +233,6 @@ code : '{' statements '}'
 argument_decl : REG
 {
 emit_arg(c, &@1, &$1);
-/* Enqueue register into initialization list */
-g_array_append_val(c->inst.init_list, $1);
 }
   | PRED
 {
diff --git a/target/hexagon/idef-parser/parser-helpers.c 
b/target/hexagon/idef-parser/parser-helpers.c
index bae01c2bb8..33e8f82007 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1652,26 +1652,24 @@ void gen_inst(Context *c, GString *iname)
 
 
 /*
- * Initialize declared but uninitialized registers, but only for
- * non-conditional instructions
+ * Initialize declared but uninitialized instruction arguments. Only needed for
+ * predicate arguments, initialization of registers is handled by the Hexagon
+ * frontend.
  */
 void gen_inst_init_args(Context *c, YYLTYPE *locp)
 {
+/* If init_list is NULL arguments have already been initialized */
 if (!c->inst.init_list) {
 return;
 }
 
 for (unsigned i = 0; i < c->inst.init_list->len; i++) {
 HexValue *val = _array_index(c->inst.init_list, HexValue, i);
-if (val->type == REGISTER_ARG) {
-/* Nothing to do here */
-} else if (val->type == PREDICATE) {
-char suffix = val->is_dotnew ? 'N' : 'V';
-EMIT_HEAD(c, "tcg_gen_movi_i%u(P%c%c, 0);\n", val->bit_width,
-  val->pred.id, suffix);
-} else {
-yyassert(c, locp, false, "Invalid arg type!");
-}
+yyassert(c, locp, val->type == PREDICATE,
+ "Only predicates need to be initialized!");
+char suffix = val->is_dotnew ? 'N' : 'V';
+EMIT_HEAD(c, "tcg_gen_movi_i%u(P%c%c, 0);\n", val->bit_width,
+  val->pred.id, suffix);
 }
 
 /* Free argument init list once we have initialized everything */
-- 
2.44.0

[PATCH 3/4] target/hexagon: idef-parser fix leak of init_list

[Anton Johansson via]

gen_inst_init_args() is called for instructions using a predicate as an
rvalue. Upon first call, the list of arguments which might need
initialization init_list is freed to indicate that they have been
processed. For instructions without an rvalue predicate,
gen_inst_init_args() isn't called and init_list will never be freed.

Free init_list from free_instruction() if it hasn't already been freed.

Signed-off-by: Anton Johansson 
---
 target/hexagon/idef-parser/parser-helpers.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/target/hexagon/idef-parser/parser-helpers.c 
b/target/hexagon/idef-parser/parser-helpers.c
index 95f2b43076..bae01c2bb8 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -2121,6 +2121,13 @@ void free_instruction(Context *c)
 g_string_free(g_array_index(c->inst.strings, GString*, i), TRUE);
 }
 g_array_free(c->inst.strings, TRUE);
+/*
+ * Free list of arguments that might need initialization, if they haven't
+ * already been free'd.
+ */
+if (c->inst.init_list) {
+g_array_free(c->inst.init_list, TRUE);
+}
 /* Free INAME token value */
 g_string_free(c->inst.name, TRUE);
 /* Free variables and registers */
-- 
2.44.0

[PATCH 0/4] target/hexagon: Minor idef-parser cleanup

[Anton Johansson via]

Was running idef-parser with valgrind and noticed we were leaking the
init_list GArray, which is used to hold instruction arguments that may
need initialization.  This patchset fixes the leak, removes unused
macros and undefined functions, and simplifies gen_inst_init_args() to
only handle predicate values.

Anton Johansson (4):
  target/hexagon: idef-parser remove unused defines
  target/hexagon: idef-parser remove undefined functions
  target/hexagon: idef-parser fix leak of init_list
  target/hexagon: idef-parser simplify predicate init

 target/hexagon/idef-parser/idef-parser.h| 10 
 target/hexagon/idef-parser/idef-parser.y|  2 --
 target/hexagon/idef-parser/parser-helpers.c | 27 -
 target/hexagon/idef-parser/parser-helpers.h | 13 --
 4 files changed, 16 insertions(+), 36 deletions(-)

-- 
2.44.0

[PATCH 1/4] target/hexagon: idef-parser remove unused defines

[Anton Johansson via]

Before switching to GArray/g_string_printf we used fixed size arrays for
output buffers and instructions arguments among other things.

Macros defining the sizes of these buffers were left behind, remove
them.

Signed-off-by: Anton Johansson 
---
 target/hexagon/idef-parser/idef-parser.h | 10 --
 1 file changed, 10 deletions(-)

diff --git a/target/hexagon/idef-parser/idef-parser.h 
b/target/hexagon/idef-parser/idef-parser.h
index 3faa1deecd..8594cbe3a2 100644
--- a/target/hexagon/idef-parser/idef-parser.h
+++ b/target/hexagon/idef-parser/idef-parser.h
@@ -23,16 +23,6 @@
 #include 
 #include 
 
-#define TCGV_NAME_SIZE 7
-#define MAX_WRITTEN_REGS 32
-#define OFFSET_STR_LEN 32
-#define ALLOC_LIST_LEN 32
-#define ALLOC_NAME_SIZE 32
-#define INIT_LIST_LEN 32
-#define OUT_BUF_LEN (1024 * 1024)
-#define SIGNATURE_BUF_LEN (128 * 1024)
-#define HEADER_BUF_LEN (128 * 1024)
-
 /* Variadic macros to wrap the buffer printing functions */
 #define EMIT(c, ...)   
\
 do {   
\
-- 
2.44.0

Re: [PATCH 07/24] exec: Un-inline tlb_vaddr_to_host() and declare it in 'exec/cputlb.h'

[Anton Johansson via]

On 25/04/24, Anton Johansson via wrote:
> On 18/04/24, Philippe Mathieu-Daudé wrote:
> > Declare tlb_vaddr_to_host() in "exec/cputlb.h" with the CPU TLB
> > API. Un-inline the user emulation definition to avoid including
> > "exec/cpu_ldst.h" (which declares g2h) in "exec/cputlb.h".
> > 
> > Signed-off-by: Philippe Mathieu-Daudé 
> > ---
> >  include/exec/cpu_ldst.h  | 24 
> >  include/exec/cputlb.h| 18 ++
> >  accel/tcg/user-exec.c|  7 +++
> >  target/arm/tcg/helper-a64.c  |  1 +
> >  target/riscv/vector_helper.c |  1 +
> >  target/sparc/mmu_helper.c|  1 +
> >  6 files changed, 28 insertions(+), 24 deletions(-)
> 
> Reviewed-by: Anton Johansson 
> 

Missed existing review, my bad!

Re: [PATCH 20/24] hw/xtensa: Include missing 'exec/cpu-common.h' in 'bootparam.h'

[Anton Johansson via]

On 18/04/24, Philippe Mathieu-Daudé wrote:
> cpu_physical_memory_write() is declared in "exec/cpu-common.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  hw/xtensa/bootparam.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/hw/xtensa/bootparam.h b/hw/xtensa/bootparam.h
> index ade7891ec5..f57ff850bc 100644
> --- a/hw/xtensa/bootparam.h
> +++ b/hw/xtensa/bootparam.h
> @@ -1,6 +1,8 @@
>  #ifndef HW_XTENSA_BOOTPARAM_H
>  #define HW_XTENSA_BOOTPARAM_H
>  
> +#include "exec/cpu-common.h"
> +
>  #define BP_TAG_COMMAND_LINE 0x1001  /* command line (0-terminated 
> string)*/
>  #define BP_TAG_INITRD   0x1002  /* ramdisk addr and size 
> (bp_meminfo) */
>  #define BP_TAG_MEMORY   0x1003  /* memory addr and size (bp_meminfo) 
> */
> -- 
> 2.41.0
> 

Reviewed-by: Anton Johansson 

Re: [PATCH 16/24] exec: Move GUEST_ADDR_MAX definition to 'cpu_ldst.h'

[Anton Johansson via]

On 18/04/24, Philippe Mathieu-Daudé wrote:
> GUEST_ADDR_MAX is only used in accel/tcg/user-exec.c
> and "exec/cpu_ldst.h". Move it from "exec/cpu-all.h"
> to "exec/cpu_ldst.h" so we can avoid including
> "exec/cpu-all.h" in accel/tcg/user-exec.c.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  include/exec/cpu-all.h  | 34 +-
>  include/exec/cpu_ldst.h | 30 ++
>  accel/tcg/cpu-exec.c|  1 -
>  3 files changed, 31 insertions(+), 34 deletions(-)

Reviewed-by: Anton Johansson 

Re: [PATCH 15/24] exec: Restrict inclusion of 'user/guest-base.h'

[Anton Johansson via]

On 18/04/24, Philippe Mathieu-Daudé wrote:
> Declare 'have_guest_base' in "user/guest-base.h".
> 
> Very few files require this header, so explicitly include
> it there instead of "exec/cpu-all.h" which is used in many
> source files.
> 
> Assert this user-specific header is only included from user
> emulation.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> Reviewed-by: Richard Henderson 
> Message-Id: <20231211212003.21686-23-phi...@linaro.org>
> ---
>  include/exec/cpu-all.h| 3 ---
>  include/exec/cpu_ldst.h   | 2 ++
>  include/user/guest-base.h | 6 ++
>  bsd-user/main.c   | 1 +
>  linux-user/elfload.c  | 1 +
>  linux-user/main.c | 1 +
>  6 files changed, 11 insertions(+), 3 deletions(-)

Reviewed-by: Anton Johansson 

Re: [PATCH 14/24] exec: Rename 'exec/user/guest-base.h' as 'user/guest-base.h'

[Anton Johansson via]

On 18/04/24, Philippe Mathieu-Daudé wrote:
> The include/user/ directory contains the user-emulation
> specific headers. Move guest-base.h there too.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  include/exec/cpu-all.h   | 2 +-
>  include/{exec => }/user/guest-base.h | 4 ++--
>  tcg/tcg.c| 2 +-
>  3 files changed, 4 insertions(+), 4 deletions(-)
>  rename include/{exec => }/user/guest-base.h (72%)

Patch looks good, but the difference between user/ and exec/user is not
entirely clear to me :)

Reviewed-by: Anton Johansson 

Re: [PATCH 09/24] physmem: Restrict TCG CPU IOTLB code to TCG accel

[Anton Johansson via]

On 18/04/24, Philippe Mathieu-Daudé wrote:
> Restrict iotlb_to_section(), address_space_translate_for_iotlb()
> and memory_region_section_get_iotlb() to TCG. Declare them in
> "exec/cputlb.h". Declare iotlb_to_section() using the
> MemoryRegionSection typedef.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  include/exec/cputlb.h   | 25 +++--
>  include/exec/exec-all.h | 21 -
>  system/physmem.c|  6 ++
>  3 files changed, 29 insertions(+), 23 deletions(-)
> 
> diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
> index 173eb98b9a..3594f904b4 100644
> --- a/include/exec/cputlb.h
> +++ b/include/exec/cputlb.h
> @@ -21,6 +21,8 @@
>  #define CPUTLB_H
>  
>  #include "exec/abi_ptr.h"
> +#include "exec/hwaddr.h"
> +#include "exec/memattrs.h"
>  #include "exec/cpu-common.h"
>  #include "exec/mmu-access-type.h"
>  
> @@ -43,10 +45,29 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
>  MMUAccessType access_type, int mmu_idx);
>  
>  #if !defined(CONFIG_USER_ONLY)
> -/* cputlb.c */
> +
>  void tlb_protect_code(ram_addr_t ram_addr);
>  void tlb_unprotect_code(ram_addr_t ram_addr);
> -#endif
> +
> +/**
> + * iotlb_to_section:
> + * @cpu: CPU performing the access
> + * @index: TCG CPU IOTLB entry
> + *
> + * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that
> + * it refers to. @index will have been initially created and returned
> + * by memory_region_section_get_iotlb().
> + */
> +MemoryRegionSection *iotlb_to_section(CPUState *cpu,
> +  hwaddr index, MemTxAttrs attrs);
> +MemoryRegionSection *
> +address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
> +  hwaddr *xlat, hwaddr *plen,
> +  MemTxAttrs attrs, int *prot);
> +hwaddr memory_region_section_get_iotlb(CPUState *cpu,
> +   MemoryRegionSection *section);
> +
> +#endif /* CONFIG_USER_ONLY */

!CONFIG_USER_ONLY

>  
>  #endif /* CONFIG_TCG */
>  
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 5cddfea01b..e4cff08db4 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -536,21 +536,6 @@ extern __thread uintptr_t tci_tb_ptr;
> smaller than 4 bytes, so we don't worry about special-casing this.  */
>  #define GETPC_ADJ   2
>  
> -#if !defined(CONFIG_USER_ONLY)
> -
> -/**
> - * iotlb_to_section:
> - * @cpu: CPU performing the access
> - * @index: TCG CPU IOTLB entry
> - *
> - * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that
> - * it refers to. @index will have been initially created and returned
> - * by memory_region_section_get_iotlb().
> - */
> -struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
> - hwaddr index, MemTxAttrs attrs);
> -#endif
> -
>  /**
>   * get_page_addr_code_hostp()
>   * @env: CPUArchState
> @@ -659,12 +644,6 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, 
> ram_addr_t length);
>  void tlb_set_dirty(CPUState *cpu, vaddr addr);
>  void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
>  
> -MemoryRegionSection *
> -address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
> -  hwaddr *xlat, hwaddr *plen,
> -  MemTxAttrs attrs, int *prot);
> -hwaddr memory_region_section_get_iotlb(CPUState *cpu,
> -   MemoryRegionSection *section);
>  #endif
>  
>  #endif
> diff --git a/system/physmem.c b/system/physmem.c
> index cf6334f3a3..38d3ede9f9 100644
> --- a/system/physmem.c
> +++ b/system/physmem.c
> @@ -31,6 +31,7 @@
>  #endif /* CONFIG_TCG */
>  
>  #include "exec/exec-all.h"
> +#include "exec/cputlb.h"
>  #include "exec/target_page.h"
>  #include "hw/qdev-core.h"
>  #include "hw/qdev-properties.h"
> @@ -585,6 +586,7 @@ typedef struct TCGIOMMUNotifier {
>  bool active;
>  } TCGIOMMUNotifier;
>  
> +#ifdef CONFIG_TCG
>  static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb)
>  {
>  TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n);
> @@ -648,6 +650,7 @@ static void tcg_register_iommu_notifier(CPUState *cpu,
>  notifier->active = true;
>  }
>  }
> +#endif
>  
>  void tcg_iommu_free_notifier_list(CPUState *cpu)
>  {
> @@ -668,6 +671,7 @@ void tcg_iommu_init_notifier_list(CPUState *cpu)
>  cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier 
> *));
>  }
>  
> +#ifdef CONFIG_TCG
>  /* Called from RCU critical section */
>  MemoryRegionSection *
>  address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr,
> @@ -761,6 +765,8 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu,
>  return section - d->map.sections;
>  }
>  
> +#endif /* CONFIG_TCG */

I might be missing some context here but are the other iotlb functions
#ifdef 

Re: [PATCH 11/24] exec: Move tlb_reset_dirty*() declarations to 'exec/cputlb.h'

[Anton Johansson via]

On 18/04/24, Philippe Mathieu-Daudé wrote:
> Declare tlb_reset_dirty() and tlb_reset_dirty_range_all()
> in "exec/cputlb.h". Restrict tlb_reset_dirty_range_all()
> to TCG accel.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  include/exec/cputlb.h   | 12 +++-
>  include/exec/exec-all.h |  3 ---
>  include/exec/ram_addr.h |  1 +
>  system/physmem.c|  2 ++
>  4 files changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
> index 3594f904b4..dc92befb93 100644
> --- a/include/exec/cputlb.h
> +++ b/include/exec/cputlb.h
> @@ -49,6 +49,9 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
>  void tlb_protect_code(ram_addr_t ram_addr);
>  void tlb_unprotect_code(ram_addr_t ram_addr);
>  
> +void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
> +void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
> +
>  /**
>   * iotlb_to_section:
>   * @cpu: CPU performing the access
> @@ -69,6 +72,13 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu,
>  
>  #endif /* CONFIG_USER_ONLY */
>  
> -#endif /* CONFIG_TCG */
> +#else /* !CONFIG_TCG */
> +
> +static inline void tlb_reset_dirty_range_all(ram_addr_t start,
> + ram_addr_t length)
> +{
> +}
> +
> +#endif /* !CONFIG_TCG */

The only use of tlb_reset_dirty_range_all() is in
cpu_physical_memory_dirty_bits_cleared() surrounded by an
if (tcg_enabled()).  Would stubbing the latter function be better?

>  
>  #endif
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 778c82ba8e..6f46015ab4 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -640,9 +640,6 @@ static inline void mmap_lock(void) {}
>  static inline void mmap_unlock(void) {}
>  #define WITH_MMAP_LOCK_GUARD()
>  
> -void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
> -void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
> -
>  #endif
>  
>  #endif
> diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
> index 3fc83587c0..f06ae9b516 100644
> --- a/include/exec/ram_addr.h
> +++ b/include/exec/ram_addr.h
> @@ -26,6 +26,7 @@
>  #include "exec/ramlist.h"
>  #include "exec/ramblock.h"
>  #include "exec/exec-all.h"
> +#include "cputlb.h"
>  #include "qemu/rcu.h"
>  
>  extern uint64_t total_dirty_pages;
> diff --git a/system/physmem.c b/system/physmem.c
> index 38d3ede9f9..7a7876a375 100644
> --- a/system/physmem.c
> +++ b/system/physmem.c
> @@ -850,6 +850,7 @@ found:
>  return block;
>  }
>  
> +#ifdef CONFIG_TCG
>  void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
>  {
>  CPUState *cpu;
> @@ -869,6 +870,7 @@ void tlb_reset_dirty_range_all(ram_addr_t start, 
> ram_addr_t length)
>  tlb_reset_dirty(cpu, start1, length);
>  }
>  }
> +#endif

This function only depends on qemu_get_ramblock which is statically
defined in physmem.c although it doesnt depend on anything in physmem.c
as far as I can tell. Thoughts on moving qemu_get_ramblock to a common
.c or .h and moving the tlb_reset_dirty_range_all definition to
cputlb.c?

Re: [PATCH 07/24] exec: Un-inline tlb_vaddr_to_host() and declare it in 'exec/cputlb.h'

[Anton Johansson via]

On 18/04/24, Philippe Mathieu-Daudé wrote:
> Declare tlb_vaddr_to_host() in "exec/cputlb.h" with the CPU TLB
> API. Un-inline the user emulation definition to avoid including
> "exec/cpu_ldst.h" (which declares g2h) in "exec/cputlb.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  include/exec/cpu_ldst.h  | 24 
>  include/exec/cputlb.h| 18 ++
>  accel/tcg/user-exec.c|  7 +++
>  target/arm/tcg/helper-a64.c  |  1 +
>  target/riscv/vector_helper.c |  1 +
>  target/sparc/mmu_helper.c|  1 +
>  6 files changed, 28 insertions(+), 24 deletions(-)

Reviewed-by: Anton Johansson 

Re: [PATCH 02/24] exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header

[Anton Johansson via]

On 18/04/24, Philippe Mathieu-Daudé wrote:
> On 18/4/24 21:25, Philippe Mathieu-Daudé wrote:
> > The CPUBreakpoint and CPUWatchpoint structures are declared
> > in "hw/core/cpu.h", which contains declarations related to
> > CPUState and CPUClass. Some source files only require the
> > BP/WP definitions and don't need to pull in all CPU* API.
> > In order to simplify, create a new "exec/breakpoint.h" header.
> > 
> > Signed-off-by: Philippe Mathieu-Daudé 
> > ---
> >   include/exec/breakpoint.h | 23 +++
> >   include/hw/core/cpu.h | 16 +---
> >   target/arm/internals.h|  1 +
> >   target/ppc/internal.h |  1 +
> >   target/riscv/debug.h  |  2 ++
> >   5 files changed, 28 insertions(+), 15 deletions(-)
> >   create mode 100644 include/exec/breakpoint.h

Reviewed-by: Anton Johansson 

Ideas on dealing with mttcg_enabled/use_icount globals

[Anton Johansson via]

Hi Phil,

I've been staring myself blind trying to deal with
qemu_tcg_mttcg_enabled()/icount_enabled() and I'm wondering if you have
an ideas.

I'm leaning towards moving these globals to some TCG accelerator
specific state (TCGState?) that's initialized once we know how many/what
cpus are in the system. The problem is then making sure all uses have 
access to this state.

For qemu_tcg_mttcg_enabled() there is one trickier use in
tcg_region_init(). We probably need to delay the initialization of the
tcg region until we know the cpus in the system, this is getting close 
to the configuration/initialization order issues we've discussed 
previously so I'm not sure how easy this would be.

As for icount_enabled(), I'm not entirely sure yet, its uses are a lot 
more scattered throughout the codebase and I'm still going through them.

Cheers,
-- 
Anton Johansson
rev.ng Labs Srl.

Re: [RFC PATCH-for-9.1 8/8] target/microblaze: Widen $ear to 64-bit

[Anton Johansson via]

On 19/03/24, Philippe Mathieu-Daudé wrote:
> The Exception Address Register is 64-bit wide.
> User emulation only access the 32 lower bits.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/microblaze/cpu.h   | 2 +-
>  linux-user/elfload.c  | 2 +-
>  target/microblaze/gdbstub.c   | 2 +-
>  target/microblaze/translate.c | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index c3e2aba0ec..a9f93b37b7 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -251,7 +251,7 @@ struct CPUArchState {
>  uint32_t pc;
>  uint32_t msr;/* All bits of MSR except MSR[C] and MSR[CC] */
>  uint32_t msr_c;  /* MSR[C], in low bit; other bits must be 0 */
> -target_ulong ear;
> +uint64_t ear;
>  uint32_t esr;
>  uint32_t fsr;
>  uint32_t btr;
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 60cf55b36c..4612aef95a 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -1498,7 +1498,7 @@ static void elf_core_copy_regs(target_elf_gregset_t 
> *regs, const CPUMBState *env
>  (*regs)[pos++] = tswapreg(env->pc);
>  (*regs)[pos++] = tswapreg(mb_cpu_read_msr(env));
>  (*regs)[pos++] = 0;
> -(*regs)[pos++] = tswapreg(env->ear);
> +(*regs)[pos++] = tswapreg((uint32_t)env->ear);
As far as I can tell env->ear is never written to from TCG so we 
shouldn't have any problems w. endian mismatch between guest/host,
right?

Anyway,

Reviewed-by: Anton Johansson 

Re: [PATCH-for-9.1 5/8] target/microblaze: Restrict 64-bit 'res_addr' to system emulation

[Anton Johansson via]

On 19/03/24, Philippe Mathieu-Daudé wrote:
> 'res_addr' is only used in system emulation, where we have
> TARGET_LONG_BITS = 64, so we can directly use the native
> uint64_t type instead of target_ulong.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/microblaze/cpu.h   | 10 +-
>  target/microblaze/cpu.c   |  2 ++
>  target/microblaze/machine.c   |  2 +-
>  target/microblaze/translate.c |  9 +++--
>  4 files changed, 15 insertions(+), 8 deletions(-)
> 
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index c0c7574dbd..c3e2aba0ec 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -260,11 +260,6 @@ struct CPUArchState {
>  /* Stack protectors. Yes, it's a hw feature.  */
>  uint32_t slr, shr;
>  
> -/* lwx/swx reserved address */
> -#define RES_ADDR_NONE 0x /* Use 0x to indicate no 
> reservation */
> -target_ulong res_addr;
> -uint32_t res_val;
> -
>  /* Internal flags.  */
>  #define IMM_FLAG(1 << 0)
>  #define BIMM_FLAG   (1 << 1)
> @@ -286,6 +281,11 @@ struct CPUArchState {
>  uint32_t iflags;
>  
>  #if !defined(CONFIG_USER_ONLY)
> +/* lwx/swx reserved address */
> +#define RES_ADDR_NONE 0x /* Use 0x to indicate no 
> reservation */
> +uint64_t res_addr;
> +uint32_t res_val;
> +
>  /* Unified MMU.  */
>  MicroBlazeMMU mmu;
>  #endif
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 96c2b71f7f..9e393cf217 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -193,7 +193,9 @@ static void mb_cpu_reset_hold(Object *obj)
>  }
>  
>  memset(env, 0, offsetof(CPUMBState, end_reset_fields));
> +#ifndef CONFIG_USER_ONLY
>  env->res_addr = RES_ADDR_NONE;
> +#endif
>  
>  /* Disable stack protector.  */
>  env->shr = ~0;
> diff --git a/target/microblaze/machine.c b/target/microblaze/machine.c
> index 51705e4f5c..4daf8a2471 100644
> --- a/target/microblaze/machine.c
> +++ b/target/microblaze/machine.c
> @@ -78,7 +78,7 @@ static const VMStateField vmstate_env_fields[] = {
>  VMSTATE_UINT32(iflags, CPUMBState),
>  
>  VMSTATE_UINT32(res_val, CPUMBState),
> -VMSTATE_UINTTL(res_addr, CPUMBState),
> +VMSTATE_UINT64(res_addr, CPUMBState),
>  
>  VMSTATE_STRUCT(mmu, CPUMBState, 0, vmstate_mmu, MicroBlazeMMU),
>  
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index d6a42381bb..493850c544 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1872,7 +1872,9 @@ void mb_tcg_init(void)
>  SP(iflags),
>  SP(bvalue),
>  SP(btarget),
> +#if !defined(CONFIG_USER_ONLY)
>  SP(res_val),
> +#endif
>  };
>  
>  #undef R
> @@ -1883,6 +1885,9 @@ void mb_tcg_init(void)
>tcg_global_mem_new_i32(tcg_env, i32s[i].ofs, i32s[i].name);
>  }
>  
> -cpu_res_addr =
> -tcg_global_mem_new(tcg_env, offsetof(CPUMBState, res_addr), 
> "res_addr");
> +#if !defined(CONFIG_USER_ONLY)
> +cpu_res_addr = tcg_global_mem_new_i64(tcg_env,
> +  offsetof(CPUMBState, res_addr),
> +  "res_addr");
> +#endif
>  }
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH-for-9.1 7/8] target/microblaze: Move MMU helpers to sys_helper.c

[Anton Johansson via]

On 19/03/24, Philippe Mathieu-Daudé wrote:
> MMU helpers are only used during system emulation,
> move them to sys_helper.c.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/microblaze/op_helper.c  | 48 --
>  target/microblaze/sys_helper.c | 47 +
>  2 files changed, 47 insertions(+), 48 deletions(-)
> 
> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
> index f6378030b7..45dbed4aaa 100644
> --- a/target/microblaze/op_helper.c
> +++ b/target/microblaze/op_helper.c
> @@ -381,51 +381,3 @@ void helper_stackprot(CPUMBState *env, target_ulong addr)
>  cpu_loop_exit_restore(cs, GETPC());
>  }
>  }
> -
> -#if !defined(CONFIG_USER_ONLY)
> -/* Writes/reads to the MMU's special regs end up here.  */
> -uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
> -{
> -return mmu_read(env, ext, rn);
> -}
> -
> -void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
> -{
> -mmu_write(env, ext, rn, v);
> -}
> -
> -void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
> -   unsigned size, MMUAccessType access_type,
> -   int mmu_idx, MemTxAttrs attrs,
> -   MemTxResult response, uintptr_t retaddr)
> -{
> -MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> -CPUMBState *env = >env;
> -
> -qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
> -  " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n",
> -  addr, physaddr, size,
> -  access_type == MMU_INST_FETCH ? "INST_FETCH" :
> -  (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : 
> "DATA_STORE"));
> -
> -if (!(env->msr & MSR_EE)) {
> -return;
> -}
> -
> -if (access_type == MMU_INST_FETCH) {
> -if (!cpu->cfg.iopb_bus_exception) {
> -return;
> -}
> -env->esr = ESR_EC_INSN_BUS;
> -} else {
> -if (!cpu->cfg.dopb_bus_exception) {
> -return;
> -}
> -env->esr = ESR_EC_DATA_BUS;
> -}
> -
> -env->ear = addr;
> -cs->exception_index = EXCP_HW_EXCP;
> -cpu_loop_exit_restore(cs, retaddr);
> -}
> -#endif
> diff --git a/target/microblaze/sys_helper.c b/target/microblaze/sys_helper.c
> index 5180500354..7531f95ca7 100644
> --- a/target/microblaze/sys_helper.c
> +++ b/target/microblaze/sys_helper.c
> @@ -21,6 +21,7 @@
>  #include "qemu/osdep.h"
>  #include "cpu.h"
>  #include "exec/exec-all.h"
> +#include "exec/helper-proto.h"
>  #include "qemu/host-utils.h"
>  #include "exec/log.h"
>  
> @@ -292,3 +293,49 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>  cs->exception_index = EXCP_HW_EXCP;
>  cpu_loop_exit(cs);
>  }
> +
> +/* Writes/reads to the MMU's special regs end up here.  */
> +uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
> +{
> +return mmu_read(env, ext, rn);
> +}
> +
> +void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
> +{
> +mmu_write(env, ext, rn, v);
> +}
> +
> +void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
> +   unsigned size, MMUAccessType access_type,
> +   int mmu_idx, MemTxAttrs attrs,
> +   MemTxResult response, uintptr_t retaddr)
> +{
> +MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> +CPUMBState *env = >env;
> +
> +qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
> +  " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n",
> +  addr, physaddr, size,
> +  access_type == MMU_INST_FETCH ? "INST_FETCH" :
> +  (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : 
> "DATA_STORE"));
> +
> +if (!(env->msr & MSR_EE)) {
> +return;
> +}
> +
> +if (access_type == MMU_INST_FETCH) {
> +if (!cpu->cfg.iopb_bus_exception) {
> +return;
> +}
> +env->esr = ESR_EC_INSN_BUS;
> +} else {
> +if (!cpu->cfg.dopb_bus_exception) {
> +return;
> +}
> +env->esr = ESR_EC_DATA_BUS;
> +}
> +
> +env->ear = addr;
> +cs->exception_index = EXCP_HW_EXCP;
> +cpu_loop_exit_restore(cs, retaddr);
> +}
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH-for-9.1 6/8] target/microblaze: Rename helper.c -> sys_helper.c

[Anton Johansson via]

On 19/03/24, Philippe Mathieu-Daudé wrote:
> helper.c only contains system emulation helpers,
> rename it as sys_helper.c.
> Adapt meson and remove pointless #ifdef'ry.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/microblaze/{helper.c => sys_helper.c} | 5 +
>  target/microblaze/meson.build| 2 +-
>  2 files changed, 2 insertions(+), 5 deletions(-)
>  rename target/microblaze/{helper.c => sys_helper.c} (99%)
> 
> diff --git a/target/microblaze/helper.c b/target/microblaze/sys_helper.c
> similarity index 99%
> rename from target/microblaze/helper.c
> rename to target/microblaze/sys_helper.c
> index 3f410fc7b5..5180500354 100644
> --- a/target/microblaze/helper.c
> +++ b/target/microblaze/sys_helper.c
> @@ -1,5 +1,5 @@
>  /*
> - *  MicroBlaze helper routines.
> + *  MicroBlaze system helper routines.
>   *
>   *  Copyright (c) 2009 Edgar E. Iglesias 
>   *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
> @@ -24,7 +24,6 @@
>  #include "qemu/host-utils.h"
>  #include "exec/log.h"
>  
> -#ifndef CONFIG_USER_ONLY
>  static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu,
>  MMUAccessType access_type)
>  {
> @@ -266,8 +265,6 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int 
> interrupt_request)
>  return false;
>  }
>  
> -#endif /* !CONFIG_USER_ONLY */
> -
>  void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>  MMUAccessType access_type,
>  int mmu_idx, uintptr_t retaddr)
> diff --git a/target/microblaze/meson.build b/target/microblaze/meson.build
> index 3ed4fbb67a..013ea542be 100644
> --- a/target/microblaze/meson.build
> +++ b/target/microblaze/meson.build
> @@ -5,7 +5,6 @@ microblaze_ss.add(gen)
>  microblaze_ss.add(files(
>'cpu.c',
>'gdbstub.c',
> -  'helper.c',
>'op_helper.c',
>'translate.c',
>  ))
> @@ -14,6 +13,7 @@ microblaze_system_ss = ss.source_set()
>  microblaze_system_ss.add(files(
>'mmu.c',
>'machine.c',
> +  'sys_helper.c',
>  ))
>  
>  target_arch += {'microblaze': microblaze_ss}
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH-for-9.1 4/8] target/microblaze: Use 32-bit destination in gen_goto_tb()

[Anton Johansson via]

On 19/03/24, Philippe Mathieu-Daudé wrote:
> cpu_pc and jmp_dest are 32-bit.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/microblaze/translate.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 4e52ef32db..d6a42381bb 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -121,7 +121,7 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t 
> esr_ec)
>  gen_raise_exception_sync(dc, EXCP_HW_EXCP);
>  }
>  
> -static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
> +static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest)
>  {
>  if (translator_use_goto_tb(>base, dest)) {
>  tcg_gen_goto_tb(n);
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH-for-9.1 3/8] target/microblaze: Widen vaddr in mmu_translate()

[Anton Johansson via]

On 19/03/24, Philippe Mathieu-Daudé wrote:
> Use 'vaddr' type for virtual addresses.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/microblaze/mmu.h | 2 +-
>  target/microblaze/mmu.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
> index 1068bd2d52..2aca39c923 100644
> --- a/target/microblaze/mmu.h
> +++ b/target/microblaze/mmu.h
> @@ -86,7 +86,7 @@ typedef struct {
>  } MicroBlazeMMULookup;
>  
>  unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
> -   target_ulong vaddr, MMUAccessType rw, int 
> mmu_idx);
> +   vaddr vaddr, MMUAccessType rw, int mmu_idx);
>  uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
>  void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
>  void mmu_init(MicroBlazeMMU *mmu);
> diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
> index 234006634e..eb7c683020 100644
> --- a/target/microblaze/mmu.c
> +++ b/target/microblaze/mmu.c
> @@ -75,7 +75,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int 
> newpid)
>  
>  /* rw - 0 = read, 1 = write, 2 = fetch.  */
>  unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
> -   target_ulong vaddr, MMUAccessType rw, int mmu_idx)
> +   vaddr vaddr, MMUAccessType rw, int mmu_idx)
>  {
>  MicroBlazeMMU *mmu = >env.mmu;
>  unsigned int i, hit = 0;
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH-for-9.1 2/8] target/microblaze: Use hwaddr/vaddr in cpu_get_phys_page_attrs_debug()

[Anton Johansson via]

On 19/03/24, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/microblaze/helper.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
> index 0a12c4ea94..3f410fc7b5 100644
> --- a/target/microblaze/helper.c
> +++ b/target/microblaze/helper.c
> @@ -228,7 +228,8 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, 
> vaddr addr,
>  MemTxAttrs *attrs)
>  {
>  MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> -target_ulong vaddr, paddr = 0;
> +vaddr vaddr;
> +hwaddr paddr = 0;
>  MicroBlazeMMULookup lu;
>  int mmu_idx = cpu_mmu_index(cs, false);
>  unsigned int hit;
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH-for-9.1 1/8] target/microblaze: Use correct string format in do_unaligned_access()

[Anton Johansson via]

On 19/03/24, Philippe Mathieu-Daudé wrote:
> 'addr' is of type 'vaddr'; no need to cast, use the
> corresponding format string.
> 
> Fixes: ab0c8d0f5b ("target/microblaze: Use cc->do_unaligned_access")
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/microblaze/helper.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
> index d25c9eb4d3..0a12c4ea94 100644
> --- a/target/microblaze/helper.c
> +++ b/target/microblaze/helper.c
> @@ -279,8 +279,8 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>  iflags = cpu->env.iflags;
>  
>  qemu_log_mask(CPU_LOG_INT,
> -  "Unaligned access addr=" TARGET_FMT_lx " pc=%x 
> iflags=%x\n",
> -  (target_ulong)addr, cpu->env.pc, iflags);
> +  "Unaligned access addr=0x%"VADDR_PRIx" pc=0x%x 
> iflags=0x%x\n",
> +  addr, cpu->env.pc, iflags);
>  
>  esr = ESR_EC_UNALIGNED_DATA;
>  if (likely(iflags & ESR_ESS_FLAG)) {
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH v1 18/21] hexagon: correct typos

[Anton Johansson via]

On 20/02/24, Philippe Mathieu-Daudé wrote:
> On 20/2/24 09:52, Manos Pitsidianakis wrote:
> > Correct typos automatically found with the `typos` tool
> > 
> > 
> > Signed-off-by: Manos Pitsidianakis 
> > ---
> >   target/hexagon/idef-parser/macros.inc | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> Reviewed-by: Philippe Mathieu-Daudé 
> 
> 
Ah nice, havent seen the typos tool before!

Reviewed-by: Anton Johansson 

Re: [PATCH v2 0/3] Hexagon (target/hexagon) Only pass env to generated helper when needed

[Anton Johansson via]

On 06/02/24, Taylor Simpson wrote:
> Currently, we pass env to every generated helper.  When the semantics of
> the instruction only depend on the arguments, this is unnecessary and
> adds extra overhead to the helper call.
> 
>  Changes in v2 
> - Separate patches to pass P0 and SP explicitly to helpers that need it
> - Add the TCG_CALL_NO_RWG_SE flag to any non-HVX helpers that
>   don't get ptr to env
> 
> Taylor Simpson (3):
>   Hexagon (target/hexagon) Pass P0 explicitly to helpers that need it
>   Hexagon (target/hexagon) Pass SP explicitly to helpers that need it
>   Hexagon (target/hexagon) Only pass env to generated helper when needed
> 
>  target/hexagon/gen_tcg.h|  3 ++
>  target/hexagon/macros.h |  4 +--
>  target/hexagon/attribs_def.h.inc|  1 +
>  target/hexagon/gen_helper_protos.py | 10 ++-
>  target/hexagon/hex_common.py| 44 +
>  5 files changed, 54 insertions(+), 8 deletions(-)
> 
> -- 
> 2.34.1
> 

Series:
Reviewed-by: Anton Johansson 
Tested-by: Anton Johansson 

-- 
Anton Johansson
rev.ng Labs Srl.

Re: [PATCH 00/33] hw/core: Introduce CPUClass hook for mmu_index

[Anton Johansson via]

On 30/01/24, Richard Henderson wrote:
> While the primary use of mmu_index is for the softmmu index for
> system-mode tcg, it has a secondary use in encoding cpu state for
> the page table walker, and thus depending on the target may also
> be used by memory_rw_debug with kvm et al.
> 
> This is why I placed the hook in CPUClass not TCGCPUOps.
> 
> 
> r~

This is a welcome change, I'll drop my cpu_mmu_index changes and rebase 
on this.

Thanks!:)

//Anton

Re: [PATCH 9/9] target/i386: Extract x86_cpu_exec_halt() from accel/tcg/

[Anton Johansson via]

On 24/01/24, Philippe Mathieu-Daudé wrote:
> Move this x86-specific code out of the generic accel/tcg/.
> 
> Reported-by: Anton Johansson 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/i386/tcg/helper-tcg.h|  1 +
>  accel/tcg/cpu-exec.c| 12 
>  target/i386/tcg/sysemu/seg_helper.c | 13 +
>  target/i386/tcg/tcg-cpu.c   |  1 +
>  4 files changed, 15 insertions(+), 12 deletions(-)
> 
> diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h
> index 253b1f561e..effc2c1c98 100644
> --- a/target/i386/tcg/helper-tcg.h
> +++ b/target/i386/tcg/helper-tcg.h
> @@ -39,6 +39,7 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > 
> TARGET_PHYS_ADDR_SPACE_BITS);
>   */
>  void x86_cpu_do_interrupt(CPUState *cpu);
>  #ifndef CONFIG_USER_ONLY
> +void x86_cpu_exec_halt(CPUState *cpu);
>  bool x86_need_replay_interrupt(int interrupt_request);
>  bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
>  #endif
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index 390a9644da..7662f4973d 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -30,9 +30,6 @@
>  #include "qemu/rcu.h"
>  #include "exec/log.h"
>  #include "qemu/main-loop.h"
> -#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
> -#include "hw/i386/apic.h"
> -#endif
>  #include "sysemu/cpus.h"
>  #include "exec/cpu-all.h"
>  #include "sysemu/cpu-timers.h"
> @@ -672,15 +669,6 @@ static inline bool cpu_handle_halt(CPUClass *cc, 
> CPUState *cpu)
>  {
>  #ifndef CONFIG_USER_ONLY
>  if (cpu->halted) {
> -#if defined(TARGET_I386)
> -if (cpu->interrupt_request & CPU_INTERRUPT_POLL) {
> -X86CPU *x86_cpu = X86_CPU(cpu);
> -bql_lock();
> -apic_poll_irq(x86_cpu->apic_state);
> -cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL);
> -bql_unlock();
> -}
> -#endif /* TARGET_I386 */
>  if (cc->tcg_ops->cpu_exec_halt) {
>  cc->tcg_ops->cpu_exec_halt(cpu);
>  }
> diff --git a/target/i386/tcg/sysemu/seg_helper.c 
> b/target/i386/tcg/sysemu/seg_helper.c
> index e6f42282bb..2db8083748 100644
> --- a/target/i386/tcg/sysemu/seg_helper.c
> +++ b/target/i386/tcg/sysemu/seg_helper.c
> @@ -20,6 +20,7 @@
>  
>  #include "qemu/osdep.h"
>  #include "qemu/log.h"
> +#include "qemu/main-loop.h"
>  #include "cpu.h"
>  #include "exec/helper-proto.h"
>  #include "exec/cpu_ldst.h"
> @@ -127,6 +128,18 @@ void x86_cpu_do_interrupt(CPUState *cs)
>  }
>  }
>  
> +void x86_cpu_exec_halt(CPUState *cpu)
> +{
> +if (cpu->interrupt_request & CPU_INTERRUPT_POLL) {
> +X86CPU *x86_cpu = X86_CPU(cpu);
> +
> +bql_lock();
> +apic_poll_irq(x86_cpu->apic_state);
> +cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL);
> +bql_unlock();
> +}
> +}
> +
>  bool x86_need_replay_interrupt(int interrupt_request)
>  {
>  /*
> diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
> index 255d56d4c3..3028b57c97 100644
> --- a/target/i386/tcg/tcg-cpu.c
> +++ b/target/i386/tcg/tcg-cpu.c
> @@ -119,6 +119,7 @@ static const struct TCGCPUOps x86_tcg_ops = {
>  #else
>  .tlb_fill = x86_cpu_tlb_fill,
>  .do_interrupt = x86_cpu_do_interrupt,
> +.cpu_exec_halt = x86_cpu_exec_halt,
>  .cpu_exec_interrupt = x86_cpu_exec_interrupt,
>  .do_unaligned_access = x86_cpu_do_unaligned_access,
>  .debug_excp_handler = breakpoint_handler,
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH 8/9] accel/tcg: Introduce TCGCPUOps::cpu_exec_halt() handler

[Anton Johansson via]

On 24/01/24, Philippe Mathieu-Daudé wrote:
> In order to make accel/tcg/ target agnostic,
> introduce the cpu_exec_halt() handler.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  include/hw/core/tcg-cpu-ops.h | 2 ++
>  accel/tcg/cpu-exec.c  | 3 +++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
> index 2fae3ac70f..3307338c80 100644
> --- a/include/hw/core/tcg-cpu-ops.h
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -114,6 +114,8 @@ struct TCGCPUOps {
>  void (*record_sigbus)(CPUState *cpu, vaddr addr,
>MMUAccessType access_type, uintptr_t ra);
>  #else
> +/** @cpu_exec_halt: Callback for handling halt in cpu_exec */
> +void (*cpu_exec_halt)(CPUState *cpu);
>  /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec 
> */
>  bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
>  /**
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index 5a978a9e72..390a9644da 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -681,6 +681,9 @@ static inline bool cpu_handle_halt(CPUClass *cc, CPUState 
> *cpu)
>  bql_unlock();
>  }
>  #endif /* TARGET_I386 */
> +if (cc->tcg_ops->cpu_exec_halt) {
> +cc->tcg_ops->cpu_exec_halt(cpu);
> +}
>  if (!cpu_has_work(cpu)) {
>  return true;
>  }
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH 7/9] target/i386: Extract x86_need_replay_interrupt() from accel/tcg/

[Anton Johansson via]

On 24/01/24, Philippe Mathieu-Daudé wrote:
> Move this x86-specific code out of the generic accel/tcg/.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/i386/tcg/helper-tcg.h|  1 +
>  accel/tcg/cpu-exec.c|  9 -
>  target/i386/tcg/sysemu/seg_helper.c | 10 ++
>  target/i386/tcg/tcg-cpu.c   |  1 +
>  4 files changed, 12 insertions(+), 9 deletions(-)
> 
> diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h
> index ce34b737bb..253b1f561e 100644
> --- a/target/i386/tcg/helper-tcg.h
> +++ b/target/i386/tcg/helper-tcg.h
> @@ -39,6 +39,7 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > 
> TARGET_PHYS_ADDR_SPACE_BITS);
>   */
>  void x86_cpu_do_interrupt(CPUState *cpu);
>  #ifndef CONFIG_USER_ONLY
> +bool x86_need_replay_interrupt(int interrupt_request);
>  bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
>  #endif
>  
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index 4ab7d6c896..5a978a9e72 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -768,21 +768,12 @@ static inline bool cpu_handle_exception(CPUClass *cc, 
> CPUState *cpu, int *ret)
>  }
>  
>  #ifndef CONFIG_USER_ONLY
> -/*
> - * CPU_INTERRUPT_POLL is a virtual event which gets converted into a
> - * "real" interrupt event later. It does not need to be recorded for
> - * replay purposes.
> - */
>  static inline bool need_replay_interrupt(CPUClass *cc, int interrupt_request)
>  {
> -#if defined(TARGET_I386)
> -return !(interrupt_request & CPU_INTERRUPT_POLL);
> -#else
>  if (!cc->tcg_ops->need_replay_interrupt) {
>  return true;
>  }
>  return cc->tcg_ops->need_replay_interrupt(interrupt_request);
> -#endif
>  }
>  #endif /* !CONFIG_USER_ONLY */
>  
> diff --git a/target/i386/tcg/sysemu/seg_helper.c 
> b/target/i386/tcg/sysemu/seg_helper.c
> index 1cb5a0db45..e6f42282bb 100644
> --- a/target/i386/tcg/sysemu/seg_helper.c
> +++ b/target/i386/tcg/sysemu/seg_helper.c
> @@ -127,6 +127,16 @@ void x86_cpu_do_interrupt(CPUState *cs)
>  }
>  }
>  
> +bool x86_need_replay_interrupt(int interrupt_request)
> +{
> +/*
> + * CPU_INTERRUPT_POLL is a virtual event which gets converted into a
> + * "real" interrupt event later. It does not need to be recorded for
> + * replay purposes.
> + */
> +return !(interrupt_request & CPU_INTERRUPT_POLL);
> +}
> +
>  bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
>  {
>  X86CPU *cpu = X86_CPU(cs);
> diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
> index e1405b7be9..255d56d4c3 100644
> --- a/target/i386/tcg/tcg-cpu.c
> +++ b/target/i386/tcg/tcg-cpu.c
> @@ -123,6 +123,7 @@ static const struct TCGCPUOps x86_tcg_ops = {
>  .do_unaligned_access = x86_cpu_do_unaligned_access,
>  .debug_excp_handler = breakpoint_handler,
>  .debug_check_breakpoint = x86_debug_check_breakpoint,
> +.need_replay_interrupt = x86_need_replay_interrupt,
>  #endif /* !CONFIG_USER_ONLY */
>  };
>  
> -- 
> 2.41.0
> 
Ah this makes me happy!:)
Reviewed-by: Anton Johansson 

Re: [PATCH 6/9] accel/tcg: Introduce TCGCPUOps::need_replay_interrupt() handler

[Anton Johansson via]

On 24/01/24, Philippe Mathieu-Daudé wrote:
> In order to make accel/tcg/ target agnostic,
> introduce the need_replay_interrupt() handler.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  include/hw/core/tcg-cpu-ops.h | 5 +
>  accel/tcg/cpu-exec.c  | 5 -
>  2 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
> index 479713a36e..2fae3ac70f 100644
> --- a/include/hw/core/tcg-cpu-ops.h
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -170,6 +170,11 @@ struct TCGCPUOps {
>   */
>  bool (*io_recompile_replay_branch)(CPUState *cpu,
> const TranslationBlock *tb);
> +/**
> + * @need_replay_interrupt: Return %true if @interrupt_request
> + * needs to be recorded for replay purposes.
> + */
> +bool (*need_replay_interrupt)(int interrupt_request);
>  #endif /* !CONFIG_USER_ONLY */
>  #endif /* NEED_CPU_H */
>  
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index b10472cbc7..4ab7d6c896 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -778,7 +778,10 @@ static inline bool need_replay_interrupt(CPUClass *cc, 
> int interrupt_request)
>  #if defined(TARGET_I386)
>  return !(interrupt_request & CPU_INTERRUPT_POLL);
>  #else
> -return true;
> +if (!cc->tcg_ops->need_replay_interrupt) {
> +return true;
> +}
> +return cc->tcg_ops->need_replay_interrupt(interrupt_request);
>  #endif
>  }
>  #endif /* !CONFIG_USER_ONLY */
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH 5/9] accel/tcg: Hoist CPUClass arg to functions with external linkage

[Anton Johansson via]

On 24/01/24, Philippe Mathieu-Daudé wrote:
> Hoist the CPUClass argument from most of these internal helpers:
> 
>  - check_for_breakpoints_slow
>  - check_for_breakpoints()
>  - cpu_tb_exec()
>  - cpu_exec_enter()
>  - cpu_exec_exit()
>  - cpu_handle_halt()
>  - cpu_handle_debug_exception()
>  - cpu_handle_exception()
>  - need_replay_interrupt()
>  - cpu_handle_interrupt()
>  - cpu_loop_exec_tb()
>  - cpu_exec_loop()
>  - cpu_exec_setjmp()
> 
> to the following ones with external linkage:
> 
>  - lookup_tb_ptr()
>  - cpu_exec_step_atomic()
>  - cpu_exec()
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  accel/tcg/cpu-exec.c | 82 
>  1 file changed, 37 insertions(+), 45 deletions(-)
> 
Reviewed-by: Anton Johansson 

Re: [PATCH 4/9] accel/tcg: Un-inline icount_exit_request() for clarity

[Anton Johansson via]

On 24/01/24, Philippe Mathieu-Daudé wrote:
> Convert packed logic to dumb icount_exit_request() helper.
> No functional change intended.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  accel/tcg/cpu-exec.c | 16 
>  1 file changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index 6b3f66930e..d61b285d5e 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -791,6 +791,17 @@ static inline bool need_replay_interrupt(int 
> interrupt_request)
>  }
>  #endif /* !CONFIG_USER_ONLY */
>  
> +static inline bool icount_exit_request(CPUState *cpu)
> +{
> +if (!icount_enabled()) {
> +return false;
> +}
> +if (cpu->cflags_next_tb != -1 && !(cpu->cflags_next_tb & CF_USE_ICOUNT)) 
> {
> +return false;
> +}
> +return cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0;
> +}
> +
>  static inline bool cpu_handle_interrupt(CPUState *cpu,
>  TranslationBlock **last_tb)
>  {
> @@ -896,10 +907,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
>  }
>  
>  /* Finally, check if we need to exit to the main loop.  */
> -if (unlikely(qatomic_read(>exit_request))
> -|| (icount_enabled()
> -&& (cpu->cflags_next_tb == -1 || cpu->cflags_next_tb & 
> CF_USE_ICOUNT)
> -&& cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0)) {
> +if (unlikely(qatomic_read(>exit_request)) || 
> icount_exit_request(cpu)) {
>  qatomic_set(>exit_request, 0);
>  if (cpu->exception_index == -1) {
>  cpu->exception_index = EXCP_INTERRUPT;
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH 3/9] accel/tcg: Rename tcg_cpus_exec() -> tcg_cpu_exec()

[Anton Johansson via]

On 24/01/24, Philippe Mathieu-Daudé wrote:
> tcg_cpus_exec() operates on a single vCPU, rename it
> as 'tcg_cpu_exec'.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  accel/tcg/tcg-accel-ops.h   | 2 +-
>  accel/tcg/tcg-accel-ops-mttcg.c | 2 +-
>  accel/tcg/tcg-accel-ops-rr.c| 2 +-
>  accel/tcg/tcg-accel-ops.c   | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h
> index 17c7ed00eb..44c4079972 100644
> --- a/accel/tcg/tcg-accel-ops.h
> +++ b/accel/tcg/tcg-accel-ops.h
> @@ -15,7 +15,7 @@
>  #include "sysemu/cpus.h"
>  
>  void tcg_cpu_destroy(CPUState *cpu);
> -int tcg_cpus_exec(CPUState *cpu);
> +int tcg_cpu_exec(CPUState *cpu);
>  void tcg_handle_interrupt(CPUState *cpu, int mask);
>  void tcg_cpu_init_cflags(CPUState *cpu, bool parallel);
>  
> diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c
> index bcba314a65..c552b45b8e 100644
> --- a/accel/tcg/tcg-accel-ops-mttcg.c
> +++ b/accel/tcg/tcg-accel-ops-mttcg.c
> @@ -92,7 +92,7 @@ static void *mttcg_cpu_thread_fn(void *arg)
>  if (cpu_can_run(cpu)) {
>  int r;
>  bql_unlock();
> -r = tcg_cpus_exec(cpu);
> +r = tcg_cpu_exec(cpu);
>  bql_lock();
>  switch (r) {
>  case EXCP_DEBUG:
> diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
> index 0617f66b5b..894e73e52c 100644
> --- a/accel/tcg/tcg-accel-ops-rr.c
> +++ b/accel/tcg/tcg-accel-ops-rr.c
> @@ -258,7 +258,7 @@ static void *rr_cpu_thread_fn(void *arg)
>  if (icount_enabled()) {
>  icount_prepare_for_run(cpu, cpu_budget);
>  }
> -r = tcg_cpus_exec(cpu);
> +r = tcg_cpu_exec(cpu);
>  if (icount_enabled()) {
>  icount_process_data(cpu);
>  }
> diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
> index 9b84b84218..9c957f421c 100644
> --- a/accel/tcg/tcg-accel-ops.c
> +++ b/accel/tcg/tcg-accel-ops.c
> @@ -68,7 +68,7 @@ void tcg_cpu_destroy(CPUState *cpu)
>  cpu_thread_signal_destroyed(cpu);
>  }
>  
> -int tcg_cpus_exec(CPUState *cpu)
> +int tcg_cpu_exec(CPUState *cpu)
>  {
>  int ret;
>  assert(tcg_enabled());
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH 2/9] accel/tcg: Rename tcg_cpus_destroy() -> tcg_cpu_destroy()

[Anton Johansson via]

On 24/01/24, Philippe Mathieu-Daudé wrote:
> tcg_cpus_destroy() operates on a single vCPU, rename it
> as 'tcg_cpu_destroy'.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  accel/tcg/tcg-accel-ops.h   | 2 +-
>  accel/tcg/tcg-accel-ops-mttcg.c | 2 +-
>  accel/tcg/tcg-accel-ops-rr.c| 2 +-
>  accel/tcg/tcg-accel-ops.c   | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h
> index f9bc6330e2..17c7ed00eb 100644
> --- a/accel/tcg/tcg-accel-ops.h
> +++ b/accel/tcg/tcg-accel-ops.h
> @@ -14,7 +14,7 @@
>  
>  #include "sysemu/cpus.h"
>  
> -void tcg_cpus_destroy(CPUState *cpu);
> +void tcg_cpu_destroy(CPUState *cpu);
>  int tcg_cpus_exec(CPUState *cpu);
>  void tcg_handle_interrupt(CPUState *cpu, int mask);
>  void tcg_cpu_init_cflags(CPUState *cpu, bool parallel);
> diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c
> index af7307013a..bcba314a65 100644
> --- a/accel/tcg/tcg-accel-ops-mttcg.c
> +++ b/accel/tcg/tcg-accel-ops-mttcg.c
> @@ -118,7 +118,7 @@ static void *mttcg_cpu_thread_fn(void *arg)
>  qemu_wait_io_event(cpu);
>  } while (!cpu->unplug || cpu_can_run(cpu));
>  
> -tcg_cpus_destroy(cpu);
> +tcg_cpu_destroy(cpu);
>  bql_unlock();
>  rcu_remove_force_rcu_notifier(_rcu.notifier);
>  rcu_unregister_thread();
> diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
> index 3208035d85..0617f66b5b 100644
> --- a/accel/tcg/tcg-accel-ops-rr.c
> +++ b/accel/tcg/tcg-accel-ops-rr.c
> @@ -131,7 +131,7 @@ static void rr_deal_with_unplugged_cpus(void)
>  
>  CPU_FOREACH(cpu) {
>  if (cpu->unplug && !cpu_can_run(cpu)) {
> -tcg_cpus_destroy(cpu);
> +tcg_cpu_destroy(cpu);
>  break;
>  }
>  }
> diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
> index 813065c0ec..9b84b84218 100644
> --- a/accel/tcg/tcg-accel-ops.c
> +++ b/accel/tcg/tcg-accel-ops.c
> @@ -63,7 +63,7 @@ void tcg_cpu_init_cflags(CPUState *cpu, bool parallel)
>  cpu->tcg_cflags |= cflags;
>  }
>  
> -void tcg_cpus_destroy(CPUState *cpu)
> +void tcg_cpu_destroy(CPUState *cpu)
>  {
>  cpu_thread_signal_destroyed(cpu);
>  }
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH 1/9] accel/tcg: Rename tcg_ss[] -> tcg_specific_ss[] in meson

[Anton Johansson via]

On 24/01/24, Philippe Mathieu-Daudé wrote:
> tcg_ss[] source set contains target-specific units.
> Rename it as 'tcg_specific_ss[]' for clarity.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  accel/tcg/meson.build | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
> index 46f7d53eeb..aef80de967 100644
> --- a/accel/tcg/meson.build
> +++ b/accel/tcg/meson.build
> @@ -1,8 +1,8 @@
> -tcg_ss = ss.source_set()
>  common_ss.add(when: 'CONFIG_TCG', if_true: files(
>'cpu-exec-common.c',
>  ))
> -tcg_ss.add(files(
> +tcg_specific_ss = ss.source_set()
> +tcg_specific_ss.add(files(
>'tcg-all.c',
>'cpu-exec.c',
>'tb-maint.c',
> @@ -11,12 +11,12 @@ tcg_ss.add(files(
>'translate-all.c',
>'translator.c',
>  ))
> -tcg_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'))
> -tcg_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec-stub.c'))
> +tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'))
> +tcg_specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: 
> files('user-exec-stub.c'))
>  if get_option('plugins')
> -  tcg_ss.add(files('plugin-gen.c'))
> +  tcg_specific_ss.add(files('plugin-gen.c'))
>  endif
> -specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
> +specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
>  
>  specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
>'cputlb.c',
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [RFC PATCH 26/34] Wrap target macros in functions

[Anton Johansson via]

On 23/01/24, Philippe Mathieu-Daudé wrote:
> Hi Anton,
> 
> On 19/1/24 15:40, Anton Johansson wrote:
> > Adds wrapper functions around common target specific macros required by
> > accel/tcg.
> > 
> > Signed-off-by: Anton Johansson 
> > ---
> >   include/hw/core/cpu.h |  9 +++
> >   cpu-target.c  | 62 +++
> >   2 files changed, 71 insertions(+)
> > 
> > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> > index 57d100c203..a2d65c1d7a 100644
> > --- a/include/hw/core/cpu.h
> > +++ b/include/hw/core/cpu.h
> > @@ -26,6 +26,7 @@
> >   #include "exec/vaddr.h"
> >   #include "exec/memattrs.h"
> >   #include "exec/tlb-common.h"
> > +#include "exec/memop.h"
> >   #include "qapi/qapi-types-run-state.h"
> >   #include "qemu/bitmap.h"
> >   #include "qemu/rcu_queue.h"
> > @@ -1164,6 +1165,14 @@ void cpu_exec_unrealizefn(CPUState *cpu);
> >* what you are doing!
> >*/
> >   bool target_words_bigendian(void);
> > +bool target_supports_mttcg(void);
> > +bool target_has_precise_smc(void);
> > +int target_long_bits(void);
> > +int target_phys_addr_space_bits(void);
> > +uint8_t target_insn_start_words(void);
> > +uint8_t target_default_memory_order(void);
> > +uint8_t target_tlb_dyn_max_bits(void);
> > +MemOp target_endian_memory_order(void);
> 
> None of these helpers take argument. I don't understand
> how they can be called in heterogeneous context.

No you're right, I was focused mostly on getting accel/tcg to compile 
with hetrogeneous being a goal downt the line.

I like the idea of moving these fields to a struct filled out per 
target, but dispatching would also work.

Re: [RFC PATCH 01/34] target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets

[Anton Johansson via]

On 19/01/24, Philippe Mathieu-Daudé wrote:
> On 19/1/24 15:39, Anton Johansson wrote:
> > Allows for future commits to use TargetPageBits to access page bits and
> > mask, thus making TARGET_PAGE_* independent of softmmu target.
> > 
> > In the future, this will also be important fo allowing heterogeneous CPUs
> > on the same board.
> 
> Yeah I carry an almost similar patch :)
> 
> Reviewed-by: Philippe Mathieu-Daudé 

Suspected there might be some overlap with this patchset:) Do you have 
branch I could rebase on to remove conflicts?

Re: [RFC PATCH 30/34] accel/tcg: Make tcg-all.c target indpendent

[Anton Johansson via]

On 23/01/24, Philippe Mathieu-Daudé wrote:
> Hi Anton,
> 
> On 19/1/24 15:40, Anton Johansson wrote:
> > Uses target_supports_mttcg() and target_long_bits() to turn ifdefs into
> > runtime branches.
> > 
> > Signed-off-by: Anton Johansson 
> > ---
> >   accel/tcg/tcg-all.c | 25 +
> >   1 file changed, 9 insertions(+), 16 deletions(-)
> 
> 
> >   static void tcg_accel_instance_init(Object *obj)
> > @@ -137,17 +129,18 @@ static char *tcg_get_thread(Object *obj, Error **errp)
> >   static void tcg_set_thread(Object *obj, const char *value, Error **errp)
> >   {
> >   TCGState *s = TCG_STATE(obj);
> > +const bool oversized_guest = target_long_bits() > TCG_TARGET_REG_BITS;
> >   if (strcmp(value, "multi") == 0) {
> > -if (TCG_OVERSIZED_GUEST) {
> > +if (oversized_guest) {
> >   error_setg(errp, "No MTTCG when guest word size > hosts");
> >   } else if (icount_enabled()) {
> >   error_setg(errp, "No MTTCG when icount is enabled");
> >   } else {
> > -#ifndef TARGET_SUPPORTS_MTTCG
> > -warn_report("Guest not yet converted to MTTCG - "
> > -"you may get unexpected results");
> > -#endif
> > +if (target_supports_mttcg()) {
> 
> I started smth similar but then realized this call has to be per target,
> so put my work on hold. My plan is to have a single common tcg
> accelerator framework, having target-specific code handled by vcpu
> dispatchers. Is your plan to have each target link its own tcg?

Yes I was leaning towards one tcg per target, but hadn't put much 
thought into it. I think your approach is better.  This patchset was
primarily focused on getting accl/tcg/ to compile once, with 
heterogeneous stuff coming down the line. IMO it becomes a bit easier to 
see what target-specific information we really need.

What do you think of a simple TargetConfig struct for information such 
as target_supports_mttcg() and the other functions introduced in 
cpu-target.c? We probably need dispatcher for other stuff but I think we 
can get quite far with struct.

[RFC PATCH 31/34] accel/tcg: Make tcg-runtime-gvec.c target independent

[Anton Johansson via]

Only depends on cpu.h.

Signed-off-by: Anton Johansson 
---
 accel/tcg/tcg-runtime-gvec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index afca89baa1..52f983dd4c 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -19,7 +19,7 @@
 
 #include "qemu/osdep.h"
 #include "qemu/host-utils.h"
-#include "cpu.h"
+#include "qemu/bitops.h"
 #include "exec/helper-proto-common.h"
 #include "tcg/tcg-gvec-desc.h"
 
-- 
2.43.0

[RFC PATCH 32/34] accel/tcg: Make tcg-runtime.c target independent

[Anton Johansson via]

Only depends on cpu.h.

Signed-off-by: Anton Johansson 
---
 accel/tcg/tcg-runtime.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
index 9fa539ad3d..fd78a10fe2 100644
--- a/accel/tcg/tcg-runtime.c
+++ b/accel/tcg/tcg-runtime.c
@@ -23,7 +23,7 @@
  */
 #include "qemu/osdep.h"
 #include "qemu/host-utils.h"
-#include "cpu.h"
+#include "qemu/atomic.h"
 #include "exec/helper-proto-common.h"
 #include "exec/cpu_ldst.h"
 #include "exec/exec-all.h"
-- 
2.43.0

[RFC PATCH 30/34] accel/tcg: Make tcg-all.c target indpendent

[Anton Johansson via]

Uses target_supports_mttcg() and target_long_bits() to turn ifdefs into
runtime branches.

Signed-off-by: Anton Johansson 
---
 accel/tcg/tcg-all.c | 25 +
 1 file changed, 9 insertions(+), 16 deletions(-)

diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index a40e0aee37..b8e920e3a8 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -28,7 +28,6 @@
 #include "exec/replay-core.h"
 #include "sysemu/cpu-timers.h"
 #include "tcg/tcg.h"
-#include "tcg/oversized-guest.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "qemu/accel.h"
@@ -67,20 +66,13 @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE,
  * there is one remaining limitation to check:
  *   - The guest can't be oversized (e.g. 64 bit guest on 32 bit host)
  */
-
 static bool default_mttcg_enabled(void)
 {
-if (icount_enabled() || TCG_OVERSIZED_GUEST) {
+const bool oversized_guest = target_long_bits() > TCG_TARGET_REG_BITS;
+if (icount_enabled() || oversized_guest) {
 return false;
 }
-#ifdef TARGET_SUPPORTS_MTTCG
-# ifndef TCG_GUEST_DEFAULT_MO
-#  error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO"
-# endif
-return true;
-#else
-return false;
-#endif
+return target_supports_mttcg();
 }
 
 static void tcg_accel_instance_init(Object *obj)
@@ -137,17 +129,18 @@ static char *tcg_get_thread(Object *obj, Error **errp)
 static void tcg_set_thread(Object *obj, const char *value, Error **errp)
 {
 TCGState *s = TCG_STATE(obj);
+const bool oversized_guest = target_long_bits() > TCG_TARGET_REG_BITS;
 
 if (strcmp(value, "multi") == 0) {
-if (TCG_OVERSIZED_GUEST) {
+if (oversized_guest) {
 error_setg(errp, "No MTTCG when guest word size > hosts");
 } else if (icount_enabled()) {
 error_setg(errp, "No MTTCG when icount is enabled");
 } else {
-#ifndef TARGET_SUPPORTS_MTTCG
-warn_report("Guest not yet converted to MTTCG - "
-"you may get unexpected results");
-#endif
+if (target_supports_mttcg()) {
+warn_report("Guest not yet converted to MTTCG - "
+"you may get unexpected results");
+}
 s->mttcg_enabled = true;
 }
 } else if (strcmp(value, "single") == 0) {
-- 
2.43.0

[RFC PATCH 34/34] accel/tcg: Compile (a few files) once for system-mode

[Anton Johansson via]

Build a common static library for a few softmmu files.

Signed-off-by: Anton Johansson 
---
 accel/tcg/meson.build | 57 ++-
 1 file changed, 45 insertions(+), 12 deletions(-)

diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 8783edd06e..420050bdbf 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -1,28 +1,61 @@
-tcg_ss = ss.source_set()
+tcg_specific_ss = ss.source_set()
+tcg_user_ss = ss.source_set()
 common_ss.add(when: 'CONFIG_TCG', if_true: files(
   'cpu-exec-common.c',
 ))
-tcg_ss.add(files(
-  'tcg-all.c',
+common_ss.add(when: libdw, if_true: files('debuginfo.c'))
+
+tcg_specific_ss.add(files(
   'cpu-exec.c',
+  'translator.c',
+))
+
+tcg_user_ss.add(files(
+  'user-exec.c',
+  'translate-all.c',
   'tb-maint.c',
   'tcg-runtime-gvec.c',
   'tcg-runtime.c',
-  'translate-all.c',
-  'translator.c',
+  'tcg-all.c',
 ))
-tcg_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'))
-tcg_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec-stub.c'))
 if get_option('plugins')
-  tcg_ss.add(files('plugin-gen.c'))
+  tcg_user_ss.add(files('plugin-gen.c'))
 endif
-tcg_ss.add(when: libdw, if_true: files('debuginfo.c'))
-tcg_ss.add(when: 'CONFIG_LINUX', if_true: files('perf.c'))
-specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
+tcg_specific_ss.add_all(when: 'CONFIG_USER_ONLY', if_true: tcg_user_ss)
+tcg_specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files(
+  'user-exec-stub.c'
+))
+tcg_specific_ss.add(when: 'CONFIG_LINUX', if_true: files('perf.c'))
+specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
 
-specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
+have_tcg = get_option('tcg').allowed()
+tcg_softmmu_ss = ss.source_set()
+tcg_softmmu_ss.add(files(
   'cputlb.c',
+  'translate-all.c',
+  'tb-maint.c',
+  'tcg-runtime-gvec.c',
+  'tcg-runtime.c',
+  'tcg-all.c',
 ))
+if get_option('plugins')
+  tcg_softmmu_ss.add(files('plugin-gen.c'))
+endif
+tcg_softmmu_ss = tcg_softmmu_ss.apply(config_targetos, strict: false)
+
+libacceltcg_softmmu = static_library('acceltcg_softmmu',
+ tcg_softmmu_ss.sources() + genh,
+ name_suffix: 'fa',
+ c_args: '-DCONFIG_SOFTMMU',
+ build_by_default: have_system and
+   have_tcg)
+
+if not get_option('tcg').allowed()
+   subdir_done()
+endif
+tcg_softmmu = declare_dependency(link_with: libacceltcg_softmmu,
+ dependencies: tcg_softmmu_ss.dependencies())
+system_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: tcg_softmmu)
 
 system_ss.add(when: ['CONFIG_TCG'], if_true: files(
   'icount-common.c',
-- 
2.43.0

[RFC PATCH 33/34] accel/tcg: Make translator.c (partially) target independent

[Anton Johansson via]

Make CPUState offset calculations target independent by using that
CPUState and CPUArchState are statically guaranteed to lie next to each
other in memory.

Signed-off-by: Anton Johansson 
---
 accel/tcg/translator.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 65219b52eb..43303577d7 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -19,8 +19,8 @@
 static void gen_io_start(void)
 {
 tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
-   offsetof(ArchCPU, parent_obj.neg.can_do_io) -
-   offsetof(ArchCPU, env));
+   offsetof(CPUState, neg.can_do_io) -
+   sizeof(CPUState));
 }
 
 bool translator_io_start(DisasContextBase *db)
@@ -53,8 +53,8 @@ static TCGOp *gen_tb_start(uint32_t cflags)
 TCGOp *icount_start_insn = NULL;
 
 tcg_gen_ld_i32(count, tcg_env,
-   offsetof(ArchCPU, parent_obj.neg.icount_decr.u32)
-   - offsetof(ArchCPU, env));
+   offsetof(CPUState, neg.icount_decr.u32) -
+   sizeof(CPUState));
 
 if (cflags & CF_USE_ICOUNT) {
 /*
@@ -82,8 +82,8 @@ static TCGOp *gen_tb_start(uint32_t cflags)
 
 if (cflags & CF_USE_ICOUNT) {
 tcg_gen_st16_i32(count, tcg_env,
- offsetof(ArchCPU, parent_obj.neg.icount_decr.u16.low)
- - offsetof(ArchCPU, env));
+ offsetof(CPUState, neg.icount_decr.u16.low) -
+ sizeof(CPUState));
 /*
  * cpu->can_do_io is cleared automatically here at the beginning of
  * each translation block.  The cost is minimal and only paid for
@@ -92,8 +92,8 @@ static TCGOp *gen_tb_start(uint32_t cflags)
  * go with gen_io_start().
  */
 tcg_gen_st_i32(tcg_constant_i32(0), tcg_env,
-   offsetof(ArchCPU, parent_obj.neg.can_do_io) -
-   offsetof(ArchCPU, env));
+   offsetof(CPUState, neg.can_do_io) -
+   sizeof(CPUState));
 }
 
 return icount_start_insn;
-- 
2.43.0

[RFC PATCH 16/34] exec: [CPUTLB] Move cpu_*()/cpu_env() to common header

[Anton Johansson via]

Functions are target independent.

Signed-off-by: Anton Johansson 
---
 include/exec/cpu-all.h| 25 -
 include/exec/cpu-common.h | 25 +
 2 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 968fbd4d16..4778976c4b 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -295,33 +295,8 @@ CPUArchState *cpu_copy(CPUArchState *env);
  | CPU_INTERRUPT_TGT_EXT_3   \
  | CPU_INTERRUPT_TGT_EXT_4)
 
-/* accel/tcg/cpu-exec.c */
-int cpu_exec(CPUState *cpu);
-
 /* Validate correct placement of CPUArchState. */
 QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
 QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
 
-/**
- * env_archcpu(env)
- * @env: The architecture environment
- *
- * Return the ArchCPU associated with the environment.
- */
-static inline ArchCPU *env_archcpu(CPUArchState *env)
-{
-return (void *)env - sizeof(CPUState);
-}
-
-/**
- * env_cpu(env)
- * @env: The architecture environment
- *
- * Return the CPUState associated with the environment.
- */
-static inline CPUState *env_cpu(CPUArchState *env)
-{
-return (void *)env - sizeof(CPUState);
-}
-
 #endif /* CPU_ALL_H */
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index d3c8b2cf55..25e50aaa37 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -347,4 +347,29 @@ G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, 
uintptr_t pc);
  */
 #define PAGE_PASSTHROUGH 0x0800
 
+/* accel/tcg/cpu-exec.c */
+int cpu_exec(CPUState *cpu);
+
+/**
+ * env_archcpu(env)
+ * @env: The architecture environment
+ *
+ * Return the ArchCPU associated with the environment.
+ */
+static inline ArchCPU *env_archcpu(CPUArchState *env)
+{
+return (void *)env - sizeof(CPUState);
+}
+
+/**
+ * env_cpu(env)
+ * @env: The architecture environment
+ *
+ * Return the CPUState associated with the environment.
+ */
+static inline CPUState *env_cpu(CPUArchState *env)
+{
+return (void *)env - sizeof(CPUState);
+}
+
 #endif /* CPU_COMMON_H */
-- 
2.43.0

[RFC PATCH 12/34] target: Uninline cpu_mmu_index()

[Anton Johansson via]

Uninlines the target-defined cpu_mmu_index() function by moving its
definition to target/*/cpu.c.  This allows for compiling memory access
functions in accel/tcg/cputlb.c without having to know target specifics.

Signed-off-by: Anton Johansson 
---
 include/exec/cpu-common.h | 10 ++
 target/alpha/cpu.h|  9 -
 target/arm/cpu.h  | 13 -
 target/avr/cpu.h  |  6 --
 target/cris/cpu.h |  4 
 target/hexagon/cpu.h  |  9 -
 target/hppa/cpu.h | 12 
 target/i386/cpu.h |  7 ---
 target/loongarch/cpu.h| 12 
 target/m68k/cpu.h |  4 
 target/microblaze/cpu.h   | 15 ---
 target/mips/cpu.h | 14 +-
 target/nios2/cpu.h|  6 --
 target/openrisc/cpu.h | 12 
 target/ppc/cpu.h  |  8 
 target/riscv/cpu.h|  2 --
 target/rx/cpu.h   |  5 -
 target/s390x/cpu.h| 31 ---
 target/sh4/cpu.h  | 10 --
 target/sparc/cpu.h| 28 
 target/tricore/cpu.h  |  5 -
 target/xtensa/cpu.h   |  5 -
 target/alpha/cpu.c|  8 
 target/arm/cpu.c  |  5 +
 target/avr/cpu.c  |  5 +
 target/cris/cpu.c |  4 
 target/hexagon/cpu.c  |  9 +
 target/hppa/cpu.c | 12 
 target/i386/cpu.c |  7 +++
 target/loongarch/cpu.c| 12 
 target/m68k/cpu.c |  5 +
 target/microblaze/cpu.c   | 16 
 target/mips/cpu.c | 14 ++
 target/nios2/cpu.c|  6 ++
 target/openrisc/cpu.c | 12 
 target/ppc/cpu.c  |  9 +
 target/riscv/cpu_helper.c |  2 +-
 target/rx/cpu.c   |  5 +
 target/s390x/cpu.c| 31 +++
 target/sh4/cpu.c  | 13 +
 target/sparc/cpu.c| 28 
 target/tricore/cpu.c  |  5 +
 target/xtensa/cpu.c   |  4 
 43 files changed, 222 insertions(+), 217 deletions(-)

diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 2eb6589764..12952c481c 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -60,6 +60,16 @@ void cpu_list_lock(void);
 void cpu_list_unlock(void);
 unsigned int cpu_list_generation_id_get(void);
 
+/**
+ * cpu_mmu_index:
+ * @env: The cpu environment
+ * @ifetch: True for code access, false for data access.
+ *
+ * Return the core mmu index for the current translation regime.
+ * This function is used by generic TCG code paths.
+ */
+int cpu_mmu_index(CPUArchState *env, bool ifetch);
+
 void tcg_flush_softmmu_tlb(CPUState *cs);
 void tcg_flush_jmp_cache(CPUState *cs);
 
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index e2a467ec17..e93186d50e 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -380,15 +380,6 @@ enum {
 
 #define TB_FLAG_UNALIGN   (1u << 1)
 
-static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch)
-{
-int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX;
-if (env->flags & ENV_FLAG_PAL_MODE) {
-ret = MMU_KERNEL_IDX;
-}
-return ret;
-}
-
 enum {
 IR_V0   = 0,
 IR_T0   = 1,
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 51963b6545..3dfca8f3ae 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3167,19 +3167,6 @@ FIELD(TBFLAG_A64, NAA, 30, 1)
 #define EX_TBFLAG_M32(IN, WHICH)   FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
 #define EX_TBFLAG_AM32(IN, WHICH)  FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
 
-/**
- * cpu_mmu_index:
- * @env: The cpu environment
- * @ifetch: True for code access, false for data access.
- *
- * Return the core mmu index for the current translation regime.
- * This function is used by generic TCG code paths.
- */
-static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
-{
-return EX_TBFLAG_ANY(env->hflags, MMUIDX);
-}
-
 /**
  * sve_vq
  * @env: the cpu context
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 4ce22d8e4f..581ba54aae 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -172,12 +172,6 @@ static inline void set_avr_feature(CPUAVRState *env, int 
feature)
 }
 
 #define cpu_list avr_cpu_list
-#define cpu_mmu_index avr_cpu_mmu_index
-
-static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch)
-{
-return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
-}
 
 void avr_cpu_tcg_init(void);
 
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 676b8e93ca..9587a2a229 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -248,10 +248,6 @@ enum {
 
 /* MMU modes definitions */
 #define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
-{
-   return !!(env->pregs[PR_CCS] & U_FLAG);
-}
 
 /* Support function regs.  */
 #define SFR_RW_GC_CFG  0][0
diff --git a/target/hexagon/cpu.h 

[RFC PATCH 17/34] hw/core: [CPUTLB] Move target specifics to end of TCGCPUOps

[Anton Johansson via]

TCGCPUOps contains an extra function pointer when included with
NEED_CPU_H, these are moved from the middle to the end of the struct. As
such offsets to target independent function pointers don't vary in
target specific and independent code.

[Move target specfic fields to separate struct?]

Signed-off-by: Anton Johansson 
---
 include/hw/core/tcg-cpu-ops.h | 32 +---
 1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 479713a36e..feb849051f 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -49,21 +49,6 @@ struct TCGCPUOps {
 /** @debug_excp_handler: Callback for handling debug exceptions */
 void (*debug_excp_handler)(CPUState *cpu);
 
-#ifdef NEED_CPU_H
-#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386)
-/**
- * @fake_user_interrupt: Callback for 'fake exception' handling.
- *
- * Simulate 'fake exception' which will be handled outside the
- * cpu execution loop (hack for x86 user mode).
- */
-void (*fake_user_interrupt)(CPUState *cpu);
-#else
-/**
- * @do_interrupt: Callback for interrupt handling.
- */
-void (*do_interrupt)(CPUState *cpu);
-#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
 #ifdef CONFIG_USER_ONLY
 /**
  * record_sigsegv:
@@ -171,8 +156,25 @@ struct TCGCPUOps {
 bool (*io_recompile_replay_branch)(CPUState *cpu,
const TranslationBlock *tb);
 #endif /* !CONFIG_USER_ONLY */
+
+#ifdef NEED_CPU_H
+#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386)
+/**
+ * @fake_user_interrupt: Callback for 'fake exception' handling.
+ *
+ * Simulate 'fake exception' which will be handled outside the
+ * cpu execution loop (hack for x86 user mode).
+ */
+void (*fake_user_interrupt)(CPUState *cpu);
+#else
+/**
+ * @do_interrupt: Callback for interrupt handling.
+ */
+void (*do_interrupt)(CPUState *cpu);
+#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
 #endif /* NEED_CPU_H */
 
+
 };
 
 #if defined(CONFIG_USER_ONLY)
-- 
2.43.0

[RFC PATCH 14/34] exec: [CPUTLB] Move PAGE_* macros to common header

[Anton Johansson via]

These don't vary across targets and are used in soon-to-be common code
(cputlb.c).

Signed-off-by: Anton Johansson 
---
 include/exec/cpu-all.h| 24 
 include/exec/cpu-common.h | 30 ++
 2 files changed, 30 insertions(+), 24 deletions(-)

diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 483e762f05..219544bad8 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -166,34 +166,10 @@ static inline void stl_phys_notdirty(AddressSpace *as, 
hwaddr addr, uint32_t val
 # error Need to use TARGET_PAGE_BITS_VARY on system mode
 #endif
 
-/* same as PROT_xxx */
-#define PAGE_READ  0x0001
-#define PAGE_WRITE 0x0002
-#define PAGE_EXEC  0x0004
-#define PAGE_BITS  (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
-#define PAGE_VALID 0x0008
-/*
- * Original state of the write flag (used when tracking self-modifying code)
- */
-#define PAGE_WRITE_ORG 0x0010
-/*
- * Invalidate the TLB entry immediately, helpful for s390x
- * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs()
- */
-#define PAGE_WRITE_INV 0x0020
-/* For use with page_set_flags: page is being replaced; target_data cleared. */
-#define PAGE_RESET 0x0040
-/* For linux-user, indicates that the page is MAP_ANON. */
-#define PAGE_ANON  0x0080
-
 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
 /* FIXME: Code that sets/uses this is broken and needs to go away.  */
 #define PAGE_RESERVED  0x0100
 #endif
-/* Target-specific bits that will be used via page_get_flags().  */
-#define PAGE_TARGET_1  0x0200
-#define PAGE_TARGET_2  0x0400
-
 /*
  * For linux-user, indicates that the page is mapped with the same semantics
  * in both guest and host.
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index b5dae4a9d6..63bc0ad150 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -234,4 +234,34 @@ G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, 
uintptr_t pc);
 G_NORETURN void cpu_loop_exit(CPUState *cpu);
 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
 
+/* same as PROT_xxx */
+#define PAGE_READ  0x0001
+#define PAGE_WRITE 0x0002
+#define PAGE_EXEC  0x0004
+#define PAGE_BITS  (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
+#define PAGE_VALID 0x0008
+/*
+ * Original state of the write flag (used when tracking self-modifying code)
+ */
+#define PAGE_WRITE_ORG 0x0010
+/*
+ * Invalidate the TLB entry immediately, helpful for s390x
+ * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs()
+ */
+#define PAGE_WRITE_INV 0x0020
+/* For use with page_set_flags: page is being replaced; target_data cleared. */
+#define PAGE_RESET 0x0040
+/* For linux-user, indicates that the page is MAP_ANON. */
+#define PAGE_ANON  0x0080
+
+/* Target-specific bits that will be used via page_get_flags().  */
+#define PAGE_TARGET_1  0x0200
+#define PAGE_TARGET_2  0x0400
+
+/*
+ * For linux-user, indicates that the page is mapped with the same semantics
+ * in both guest and host.
+ */
+#define PAGE_PASSTHROUGH 0x0800
+
 #endif /* CPU_COMMON_H */
-- 
2.43.0

[RFC PATCH 20/34] accel/tcg: [CPUTLB] Use TCGContext.guest_mo for memory ordering

[Anton Johansson via]

Signed-off-by: Anton Johansson 
---
 accel/tcg/internal-target.h | 11 ---
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h
index 4e36cf858e..3bcd1bbc84 100644
--- a/accel/tcg/internal-target.h
+++ b/accel/tcg/internal-target.h
@@ -9,8 +9,9 @@
 #ifndef ACCEL_TCG_INTERNAL_TARGET_H
 #define ACCEL_TCG_INTERNAL_TARGET_H
 
-#include "exec/exec-all.h"
+#include "exec/exec-common.h"
 #include "exec/translate-all.h"
+#include "tcg/tcg.h"
 
 /*
  * Access to the various translations structures need to be serialised
@@ -108,12 +109,8 @@ extern bool one_insn_per_tb;
  *
  * This is a macro so that it's constant even without optimization.
  */
-#ifdef TCG_GUEST_DEFAULT_MO
-# define tcg_req_mo(type) \
-((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO)
-#else
-# define tcg_req_mo(type) ((type) & ~TCG_TARGET_DEFAULT_MO)
-#endif
+#define tcg_req_mo(type) \
+((type) & tcg_ctx->guest_mo & ~TCG_TARGET_DEFAULT_MO)
 
 /**
  * cpu_req_mo:
-- 
2.43.0

[RFC PATCH 24/34] accel/tcg: [CPUTLB] Set mo_te in TCGContext

[Anton Johansson via]

Initializes mo_te field of TCGContext to the target endian memory order
MO_TE, so it can be used within cputlb.c.

Signed-off-by: Anton Johansson 
---
 accel/tcg/translate-all.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 8cb6ad3511..9c981d1750 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -47,12 +47,13 @@
 #include "exec/translate-all.h"
 #include "exec/translator.h"
 #include "exec/tb-flush.h"
+#include "exec/log.h"
+#include "exec/memop.h"
 #include "qemu/bitmap.h"
 #include "qemu/qemu-print.h"
 #include "qemu/main-loop.h"
 #include "qemu/cacheinfo.h"
 #include "qemu/timer.h"
-#include "exec/log.h"
 #include "sysemu/cpus.h"
 #include "sysemu/cpu-timers.h"
 #include "sysemu/tcg.h"
@@ -342,6 +343,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
 tcg_ctx->gen_tb = tb;
 tcg_ctx->addr_type = TARGET_LONG_BITS == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64;
 #ifdef CONFIG_SOFTMMU
+tcg_ctx->mo_te = MO_TE;
 tcg_ctx->page_bits = TARGET_PAGE_BITS;
 tcg_ctx->page_mask = TARGET_PAGE_MASK;
 tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
-- 
2.43.0

[RFC PATCH 18/34] accel/stubs: [CPUTLB] Move xen.h stubs to xen-stub.c

[Anton Johansson via]

Makes xen.h header independent of softmmu target.  Note:
CONFIG_XEN_IS_POSSIBLE is only used define stubs in xen.h and optimize
xen_enabled().

Required by cpu_physical_memory_set_dirty_range() in ram_addr.h.

Signed-off-by: Anton Johansson 
---
 include/sysemu/xen.h   | 27 ---
 accel/stubs/xen-stub.c | 12 
 2 files changed, 12 insertions(+), 27 deletions(-)

diff --git a/include/sysemu/xen.h b/include/sysemu/xen.h
index bc13ad5692..838bb5a003 100644
--- a/include/sysemu/xen.h
+++ b/include/sysemu/xen.h
@@ -12,16 +12,6 @@
 
 #include "exec/cpu-common.h"
 
-#ifdef NEED_CPU_H
-# ifdef CONFIG_XEN
-#  define CONFIG_XEN_IS_POSSIBLE
-# endif
-#else
-# define CONFIG_XEN_IS_POSSIBLE
-#endif
-
-#ifdef CONFIG_XEN_IS_POSSIBLE
-
 extern bool xen_allowed;
 
 #define xen_enabled()   (xen_allowed)
@@ -32,21 +22,4 @@ void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size,
struct MemoryRegion *mr, Error **errp);
 #endif
 
-#else /* !CONFIG_XEN_IS_POSSIBLE */
-
-#define xen_enabled() 0
-#ifndef CONFIG_USER_ONLY
-static inline void xen_hvm_modified_memory(ram_addr_t start, ram_addr_t length)
-{
-/* nothing */
-}
-static inline void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size,
- MemoryRegion *mr, Error **errp)
-{
-g_assert_not_reached();
-}
-#endif
-
-#endif /* CONFIG_XEN_IS_POSSIBLE */
-
 #endif
diff --git a/accel/stubs/xen-stub.c b/accel/stubs/xen-stub.c
index 7054965c48..73cfa2d291 100644
--- a/accel/stubs/xen-stub.c
+++ b/accel/stubs/xen-stub.c
@@ -14,3 +14,15 @@ bool xen_allowed;
 void qmp_xen_set_global_dirty_log(bool enable, Error **errp)
 {
 }
+
+#ifndef CONFIG_USER_ONLY
+void xen_hvm_modified_memory(ram_addr_t start, ram_addr_t length)
+{
+/* nothing */
+}
+void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size,
+   MemoryRegion *mr, Error **errp)
+{
+g_assert_not_reached();
+}
+#endif
-- 
2.43.0

[RFC PATCH 22/34] accel/tcg: [CPUTLB] Move CPU_TLB_DYN_[DEFAULT|MIN]* to cputlb.c

[Anton Johansson via]

These macros are only used for softmmu targets and only used in
cputlb.c, move definitions there.

Signed-off-by: Anton Johansson 
---
 include/exec/cpu-defs.h | 3 ---
 accel/tcg/cputlb.c  | 3 +++
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index e8ccbe4bef..4b369e39b0 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -55,9 +55,6 @@
 #include "exec/target_long.h"
 
 #if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
-#define CPU_TLB_DYN_MIN_BITS 6
-#define CPU_TLB_DYN_DEFAULT_BITS 8
-
 # if HOST_LONG_BITS == 32
 /* Make sure we do not require a double-word shift for the TLB load */
 #  define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 42be5b6289..a75a52d141 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -43,6 +43,9 @@
 #include "tcg/tcg-ldst.h"
 #include "tcg-target-reg-bits.h"
 
+#define CPU_TLB_DYN_MIN_BITS 6
+#define CPU_TLB_DYN_DEFAULT_BITS 8
+
 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
 /* #define DEBUG_TLB */
 /* #define DEBUG_TLB_LOG */
-- 
2.43.0

[RFC PATCH 10/34] exec: [VADDR] typedef abi_ptr to vaddr

[Anton Johansson via]

Signed-off-by: Anton Johansson 
---
 include/exec/cpu_ldst.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 6061e33ac9..eb8f3f0595 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -121,8 +121,8 @@ static inline bool guest_range_valid_untagged(abi_ulong 
start, abi_ulong len)
 h2g_nocheck(x); \
 })
 #else
-typedef target_ulong abi_ptr;
-#define TARGET_ABI_FMT_ptr TARGET_FMT_lx
+typedef vaddr abi_ptr;
+#define TARGET_ABI_FMT_ptr VADDR_PRIx
 #endif
 
 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
-- 
2.43.0

[RFC PATCH 04/34] exec: [PAGE_VARY] Unpoison TARGET_PAGE_* macros for system mode

[Anton Johansson via]

TARGET_PAGE_* are now target-independent for softmmu targets, and can
safely be accessed common code.

Signed-off-by: Anton Johansson 
---
 include/exec/poison.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/exec/poison.h b/include/exec/poison.h
index 1ea5633eb3..6d87954a91 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -46,10 +46,12 @@
 #pragma GCC poison TARGET_FMT_ld
 #pragma GCC poison TARGET_FMT_lu
 
+#ifdef CONFIG_USER_ONLY
 #pragma GCC poison TARGET_PAGE_SIZE
 #pragma GCC poison TARGET_PAGE_MASK
 #pragma GCC poison TARGET_PAGE_BITS
 #pragma GCC poison TARGET_PAGE_ALIGN
+#endif
 
 #pragma GCC poison CPU_INTERRUPT_HARD
 #pragma GCC poison CPU_INTERRUPT_EXITTB
-- 
2.43.0

[RFC PATCH 03/34] exec: [PAGE_VARY] Move TARGET_PAGE_BITS_VARY to common header

[Anton Johansson via]

We need to be able access the variable TARGET_PAGE_* macros in a
target-independent manner.

Signed-off-by: Anton Johansson 
---
 include/exec/cpu-all.h| 29 ++---
 include/exec/cpu-common.h | 25 +
 2 files changed, 35 insertions(+), 19 deletions(-)

diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index a1e4dee6a2..83165b1ce4 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -149,30 +149,21 @@ static inline void stl_phys_notdirty(AddressSpace *as, 
hwaddr addr, uint32_t val
 #include "exec/memory_ldst_phys.h.inc"
 #endif
 
-/* page related stuff */
-
-#ifdef TARGET_PAGE_BITS_VARY
-# include "exec/page-vary.h"
-extern const TargetPageBits target_page;
-#ifdef CONFIG_DEBUG_TCG
-#define TARGET_PAGE_BITS_MIN ({ assert(target_page.decided); \
-target_page.bits_min; })
-#define TARGET_PAGE_BITS   ({ assert(target_page.decided); target_page.bits; })
-#define TARGET_PAGE_MASK   ({ assert(target_page.decided); \
-  (target_long)target_page.mask; })
-#else
-#define TARGET_PAGE_BITS_MIN target_page.bits_min
-#define TARGET_PAGE_BITS target_page.bits
-#define TARGET_PAGE_MASK ((target_long)target_page.mask)
-#endif
-#define TARGET_PAGE_SIZE   (-(int)TARGET_PAGE_MASK)
-#else
+/* Non-variable page size macros */
+#ifndef TARGET_PAGE_BITS_VARY
 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
 #define TARGET_PAGE_SIZE   (1 << TARGET_PAGE_BITS)
 #define TARGET_PAGE_MASK   ((target_long)-1 << TARGET_PAGE_BITS)
+#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
 #endif
 
-#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
+/*
+ * Check that softmmu targets are using variable page sizes, we need this
+ * for the TARGET_PAGE_* macros to be target independent.
+ */
+#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_PAGE_BITS_VARY)
+# error Need to use TARGET_PAGE_BITS_VARY on system mode
+#endif
 
 /* same as PROT_xxx */
 #define PAGE_READ  0x0001
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 605b160a7e..df53252d51 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -26,6 +26,31 @@ typedef uint64_t vaddr;
 #define VADDR_PRIX PRIX64
 #define VADDR_MAX UINT64_MAX
 
+/**
+ * Variable page size macros
+ *
+ * TARGET_PAGE_BITS_VARY is assumed for softmmu targets so
+ * these macros are target independent.  This is checked in
+ * cpu-all.h.
+ */
+#ifndef CONFIG_USER_ONLY
+# include "exec/page-vary.h"
+extern const TargetPageBits target_page;
+#ifdef CONFIG_DEBUG_TCG
+#define TARGET_PAGE_BITS_MIN ({ assert(target_page.decided); \
+target_page.bits_min; })
+#define TARGET_PAGE_BITS   ({ assert(target_page.decided); target_page.bits; })
+#define TARGET_PAGE_MASK   ({ assert(target_page.decided); \
+  (int)target_page.mask; })
+#else
+#define TARGET_PAGE_BITS_MIN target_page.bits_min
+#define TARGET_PAGE_BITS target_page.bits
+#define TARGET_PAGE_MASK ((int)target_page.mask)
+#endif
+#define TARGET_PAGE_SIZE   (-(int)TARGET_PAGE_MASK)
+#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
+#endif
+
 void cpu_exec_init_all(void);
 void cpu_exec_step_atomic(CPUState *cpu);
 
-- 
2.43.0

[RFC PATCH 00/34] Compile accel/tcg once (partially)

[Anton Johansson via]

Based on an older version of rth/tcg-next and some patches by me, Philippe,
and Richard (most of which have since been merged), base branch here

  https://gitlab.com/AntonJohansson/qemu/-/tree/feature/accel-tcg-once-base

Rebase is in the works, but should not affect the larger parts of this
patchset that I'm looking for feedback on.

This patchset moves forward with the single binary/compile once work and
tries to compile translation units in accel/tcg/ once for system mode.
The following files are compiled once in this patchset

  cputlb.c
  tcg-all.c
  tcg-runtime.c
  tcg-runtime-gvec.c
  tb-maint.c
  plugin-gen.c
  translate-all.c

and debuginfo.c is also moved to common_ss as it doesn't contain any
target specifics.  Work still remains for 

  cpu-exec.c (TARGET_I386 ifdefs)
  translator.c   (tswap(), ldl_p() and friends)

Brackets [...] in patch names are temporary and indicate patches that
"belong" together and can be split out easier.

Major changes which I'm looking for feedback on:

- [PAGE_VARY] patches:

Switches to variable page sizes as a default for all system
mode targets, meaning TARGET_PAGE_* and TLB_* become target
independent.

- "Uninline cpu_mmu_index()"/"Uninline cpu_get_tb_cpu_state()":

Uninlines cpu_mmu_index() (used by cputlb.c) and
cpu_get_tb_cpu_state() (used by translate-all.c) so they can be
called from accel/tcg without pulling in target specifics.

- "Wrap target macros in functions":

Introduces wrapper functions in cpu-target.c around target
macros that I'm not sure how to deal with.

Anton Johansson (34):
  target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets
  target: [PAGE_VARY] Move TARGET_PAGE_BITS_MIN to TargetPageBits
  exec: [PAGE_VARY] Move TARGET_PAGE_BITS_VARY to common header
  exec: [PAGE_VARY] Unpoison TARGET_PAGE_* macros for system mode
  target/tricore: [VADDR] Use target_ulong for EA
  exec: [VADDR] Move vaddr defines to separate file
  hw/core: [VADDR] Include vaddr.h from cpu.h
  target: [VADDR] Use vaddr in gen_intermediate_code
  exec: [VADDR] Use vaddr in DisasContextBase for virtual addresses
  exec: [VADDR] typedef abi_ptr to vaddr
  [IGNORE] Squash of header code shuffling
  target: Uninline cpu_mmu_index()
  target: Uninline cpu_get_tb_cpu_state()
  exec: [CPUTLB] Move PAGE_* macros to common header
  exec: [CPUTLB] Move TLB_*/tlb_*() to common header
  exec: [CPUTLB] Move cpu_*()/cpu_env() to common header
  hw/core: [CPUTLB] Move target specifics to end of TCGCPUOps
  accel/stubs: [CPUTLB] Move xen.h stubs to xen-stub.c
  accel/tcg: [CPUTLB] Use TCGContext.addr_type instead of
TARGET_LONG_BITS
  accel/tcg: [CPUTLB] Use TCGContext.guest_mo for memory ordering
  accel/tcg: [CPUTLB] Use tcg_ctx->tlb_dyn_max_bits
  accel/tcg: [CPUTLB] Move CPU_TLB_DYN_[DEFAULT|MIN]* to cputlb.c
  tcg: [CPUTLB] Add `mo_te` field to TCGContext
  accel/tcg: [CPUTLB] Set mo_te in TCGContext
  accel/tcg: [CPUTLB] Use tcg_ctx->mo_te instead of MO_TE
  Wrap target macros in functions
  accel/tcg: Make translate-all.c target independent
  accel/tcg: Make plugin-gen.c target independent
  accel/tcg: Make tb-maint.c target indpendent
  accel/tcg: Make tcg-all.c target indpendent
  accel/tcg: Make tcg-runtime-gvec.c target independent
  accel/tcg: Make tcg-runtime.c target independent
  accel/tcg: Make translator.c (partially) target independent
  accel/tcg: Compile (a few files) once for system-mode

 accel/tcg/internal-target.h|  11 +-
 accel/tcg/tb-hash.h|   4 +-
 hw/s390x/s390-virtio-hcall.h   |   2 +
 include/exec/cpu-all.h | 156 +-
 include/exec/cpu-common.h  | 185 -
 include/exec/cpu-defs.h|   7 +-
 include/exec/cpu_ldst-target.h |  52 +
 include/exec/cpu_ldst.h|  95 +++--
 include/exec/exec-all.h| 347 +--
 include/exec/exec-common.h | 367 +
 include/exec/memory-internal.h |   2 +-
 include/exec/page-vary.h   |   1 +
 include/exec/poison.h  |   2 +
 include/exec/ram_addr.h|   3 +-
 include/exec/translator.h  |   8 +-
 include/exec/vaddr.h   |  18 ++
 include/hw/core/cpu.h  |  11 +-
 include/hw/core/tcg-cpu-ops.h  |  32 +--
 include/qemu/plugin-memory.h   |   1 -
 include/sysemu/xen.h   |  27 ---
 include/tcg/tcg.h  |   1 +
 target/alpha/cpu-param.h   |   6 +
 target/alpha/cpu.h |  20 --
 target/arm/cpu-param.h |   2 +-
 target/arm/cpu.h   |  16 --
 target/avr/cpu-param.h |   6 +
 target/avr/cpu.h   |  24 ---
 target/cris/cpu-param.h|   7 +
 target/cris/cpu.h  |  14 --
 target/hexagon/cpu.h   |  21 --
 target/hppa/cpu-param.h|   6 +
 target/hppa/cpu.h  |  55 -
 target/i386/cpu-param.h|   6 +
 target/i386/cpu.h  |  16 --
 

[RFC PATCH 15/34] exec: [CPUTLB] Move TLB_*/tlb_*() to common header

[Anton Johansson via]

TLB_* macros and tlb_*() functions are target independent, move to cpu-common.h.

Signed-off-by: Anton Johansson 
---
 include/exec/cpu-all.h| 81 --
 include/exec/cpu-common.h | 83 +++
 2 files changed, 83 insertions(+), 81 deletions(-)

diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 219544bad8..968fbd4d16 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -295,87 +295,6 @@ CPUArchState *cpu_copy(CPUArchState *env);
  | CPU_INTERRUPT_TGT_EXT_3   \
  | CPU_INTERRUPT_TGT_EXT_4)
 
-#ifdef CONFIG_USER_ONLY
-
-/*
- * Allow some level of source compatibility with softmmu.  We do not
- * support any of the more exotic features, so only invalid pages may
- * be signaled by probe_access_flags().
- */
-#define TLB_INVALID_MASK(1 << (TARGET_PAGE_BITS_MIN - 1))
-#define TLB_MMIO(1 << (TARGET_PAGE_BITS_MIN - 2))
-#define TLB_WATCHPOINT  0
-
-#else
-
-/*
- * Flags stored in the low bits of the TLB virtual address.
- * These are defined so that fast path ram access is all zeros.
- * The flags all must be between TARGET_PAGE_BITS and
- * maximum address alignment bit.
- *
- * Use TARGET_PAGE_BITS_MIN so that these bits are constant
- * when TARGET_PAGE_BITS_VARY is in effect.
- *
- * The count, if not the placement of these bits is known
- * to tcg/tcg-op-ldst.c, check_max_alignment().
- */
-/* Zero if TLB entry is valid.  */
-#define TLB_INVALID_MASK(1 << (TARGET_PAGE_BITS_MIN - 1))
-/* Set if TLB entry references a clean RAM page.  The iotlb entry will
-   contain the page physical address.  */
-#define TLB_NOTDIRTY(1 << (TARGET_PAGE_BITS_MIN - 2))
-/* Set if TLB entry is an IO callback.  */
-#define TLB_MMIO(1 << (TARGET_PAGE_BITS_MIN - 3))
-/* Set if TLB entry writes ignored.  */
-#define TLB_DISCARD_WRITE   (1 << (TARGET_PAGE_BITS_MIN - 4))
-/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
-#define TLB_FORCE_SLOW  (1 << (TARGET_PAGE_BITS_MIN - 5))
-
-/*
- * Use this mask to check interception with an alignment mask
- * in a TCG backend.
- */
-#define TLB_FLAGS_MASK \
-(TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
-| TLB_FORCE_SLOW | TLB_DISCARD_WRITE)
-
-/*
- * Flags stored in CPUTLBEntryFull.slow_flags[x].
- * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x].
- */
-/* Set if TLB entry requires byte swap.  */
-#define TLB_BSWAP(1 << 0)
-/* Set if TLB entry contains a watchpoint.  */
-#define TLB_WATCHPOINT   (1 << 1)
-
-#define TLB_SLOW_FLAGS_MASK  (TLB_BSWAP | TLB_WATCHPOINT)
-
-/**
- * tlb_hit_page: return true if page aligned @addr is a hit against the
- * TLB entry @tlb_addr
- *
- * @addr: virtual address to test (must be page aligned)
- * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
- */
-static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr)
-{
-return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
-}
-
-/**
- * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
- *
- * @addr: virtual address to test (need not be page aligned)
- * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
- */
-static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr)
-{
-return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
-}
-
-#endif /* !CONFIG_USER_ONLY */
-
 /* accel/tcg/cpu-exec.c */
 int cpu_exec(CPUState *cpu);
 
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 63bc0ad150..d3c8b2cf55 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -41,6 +41,89 @@ extern const TargetPageBits target_page;
 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
 #endif
 
+#ifdef CONFIG_USER_ONLY
+
+/*
+ * Allow some level of source compatibility with softmmu.  We do not
+ * support any of the more exotic features, so only invalid pages may
+ * be signaled by probe_access_flags().
+ */
+#define TLB_INVALID_MASK(1 << (TARGET_PAGE_BITS_MIN - 1))
+#define TLB_MMIO(1 << (TARGET_PAGE_BITS_MIN - 2))
+#define TLB_WATCHPOINT  0
+
+#else
+
+/*
+ * Flags stored in the low bits of the TLB virtual address.
+ * These are defined so that fast path ram access is all zeros.
+ * The flags all must be between TARGET_PAGE_BITS and
+ * maximum address alignment bit.
+ *
+ * Use TARGET_PAGE_BITS_MIN so that these bits are constant
+ * when TARGET_PAGE_BITS_VARY is in effect.
+ *
+ * The count, if not the placement of these bits is known
+ * to tcg/tcg-op-ldst.c, check_max_alignment().
+ */
+/* Zero if TLB entry is valid.  */
+#define TLB_INVALID_MASK(1 << (TARGET_PAGE_BITS_MIN - 1))
+/*
+ * Set if TLB entry references a clean RAM page.  The iotlb entry will
+ * contain the page physical address.
+ */
+#define TLB_NOTDIRTY(1 << (TARGET_PAGE_BITS_MIN - 2))
+/* Set if TLB entry is an IO callback.  */
+#define TLB_MMIO(1 << (TARGET_PAGE_BITS_MIN - 3))

[RFC PATCH 23/34] tcg: [CPUTLB] Add `mo_te` field to TCGContext

[Anton Johansson via]

Required by cpu_ldub_code() and friends in cputlb.c to access the MO_TE
MemOp in a target-independent way.

Signed-off-by: Anton Johansson 
---
 include/tcg/tcg.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 7743868dc9..4ca626aeae 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -489,6 +489,7 @@ struct TCGContext {
 TCGType addr_type;/* TCG_TYPE_I32 or TCG_TYPE_I64 */
 
 #ifdef CONFIG_SOFTMMU
+MemOp mo_te;
 int page_mask;
 uint8_t page_bits;
 uint8_t tlb_dyn_max_bits;
-- 
2.43.0

[RFC PATCH 08/34] target: [VADDR] Use vaddr in gen_intermediate_code

[Anton Johansson via]

Makes gen_intermediate_code() signature target agnostic so the function
can be called from accel/tcg/translate-all.c without target specifics.

Signed-off-by: Anton Johansson 
---
 include/exec/translator.h | 2 +-
 target/alpha/translate.c  | 2 +-
 target/arm/tcg/translate.c| 2 +-
 target/avr/translate.c| 2 +-
 target/cris/translate.c   | 2 +-
 target/hexagon/translate.c| 2 +-
 target/hppa/translate.c   | 2 +-
 target/i386/tcg/translate.c   | 2 +-
 target/loongarch/translate.c  | 2 +-
 target/m68k/translate.c   | 2 +-
 target/microblaze/translate.c | 2 +-
 target/mips/tcg/translate.c   | 2 +-
 target/nios2/translate.c  | 2 +-
 target/openrisc/translate.c   | 2 +-
 target/ppc/translate.c| 2 +-
 target/riscv/translate.c  | 2 +-
 target/rx/translate.c | 2 +-
 target/s390x/tcg/translate.c  | 2 +-
 target/sh4/translate.c| 2 +-
 target/sparc/translate.c  | 2 +-
 target/tricore/translate.c| 2 +-
 target/xtensa/translate.c | 2 +-
 22 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/include/exec/translator.h b/include/exec/translator.h
index 4e17c4f401..2ab8f58bea 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -33,7 +33,7 @@
  * the target-specific DisasContext, and then invoke translator_loop.
  */
 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
-   target_ulong pc, void *host_pc);
+   vaddr pc, void *host_pc);
 
 /**
  * DisasJumpType:
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 32333081d8..134eb7225b 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2971,7 +2971,7 @@ static const TranslatorOps alpha_tr_ops = {
 };
 
 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
-   target_ulong pc, void *host_pc)
+   vaddr pc, void *host_pc)
 {
 DisasContext dc;
 translator_loop(cpu, tb, max_insns, pc, host_pc, _tr_ops, );
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index bdcb8a6555..0877cb1ce5 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -9682,7 +9682,7 @@ static const TranslatorOps thumb_translator_ops = {
 
 /* generate intermediate code for basic block 'tb'.  */
 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
-   target_ulong pc, void *host_pc)
+   vaddr pc, void *host_pc)
 {
 DisasContext dc = { };
 const TranslatorOps *ops = _translator_ops;
diff --git a/target/avr/translate.c b/target/avr/translate.c
index cdffa04519..e5dd057799 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2805,7 +2805,7 @@ static const TranslatorOps avr_tr_ops = {
 };
 
 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
-   target_ulong pc, void *host_pc)
+   vaddr pc, void *host_pc)
 {
 DisasContext dc = { };
 translator_loop(cs, tb, max_insns, pc, host_pc, _tr_ops, );
diff --git a/target/cris/translate.c b/target/cris/translate.c
index b3974ba0bb..ee1402a9a3 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3172,7 +3172,7 @@ static const TranslatorOps cris_tr_ops = {
 };
 
 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
-   target_ulong pc, void *host_pc)
+   vaddr pc, void *host_pc)
 {
 DisasContext dc;
 translator_loop(cs, tb, max_insns, pc, host_pc, _tr_ops, );
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 663b7bbc3a..2ef6a89622 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -1154,7 +1154,7 @@ static const TranslatorOps hexagon_tr_ops = {
 };
 
 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
-   target_ulong pc, void *host_pc)
+   vaddr pc, void *host_pc)
 {
 DisasContext ctx;
 
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 902cd642ae..f22ec3aeb3 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -4273,7 +4273,7 @@ static const TranslatorOps hppa_tr_ops = {
 };
 
 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
-   target_ulong pc, void *host_pc)
+   vaddr pc, void *host_pc)
 {
 DisasContext ctx;
 translator_loop(cs, tb, max_insns, pc, host_pc, _tr_ops, );
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index c6894d66b1..c97d1e3da8 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -7084,7 +7084,7 @@ static const TranslatorOps i386_tr_ops = {
 
 /* generate intermediate code for basic block 'tb'.  */
 void gen_intermediate_code(CPUState 

[RFC PATCH 07/34] hw/core: [VADDR] Include vaddr.h from cpu.h

[Anton Johansson via]

cpu-common.h is only needed for vaddr

Signed-off-by: Anton Johansson 
---
 include/hw/core/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index f25d53ee90..57d100c203 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -22,8 +22,8 @@
 
 #include "hw/qdev-core.h"
 #include "disas/dis-asm.h"
-#include "exec/cpu-common.h"
 #include "exec/hwaddr.h"
+#include "exec/vaddr.h"
 #include "exec/memattrs.h"
 #include "exec/tlb-common.h"
 #include "qapi/qapi-types-run-state.h"
-- 
2.43.0

[RFC PATCH 02/34] target: [PAGE_VARY] Move TARGET_PAGE_BITS_MIN to TargetPageBits

[Anton Johansson via]

TARGET_PAGE_BITS_MIN is now defined as target_page.bits_min when
PAGE_VARY is used, similar to other TARGET_PAGE_* macros.  We still pick
whatever minimum the target specifies, however in a heterogeneous
context we would want the maximum of all target_page.bits_min.

This also makes TLB_* macros target independent, and the static assert
checking for TLB_* flag overlap is moved to a runtime assert in
tlb_init().

[NOTE: I'm not happy with adding the TARGET_PAGE_BITS_MIN_SPECIFIC
macro, maybe we can remove it and use MachineClass->minimum_page_bits
instead? Other ideas?]

Signed-off-by: Anton Johansson 
---
 include/exec/cpu-all.h| 10 +-
 include/exec/cpu-defs.h   |  4 ++--
 include/exec/page-vary.h  |  1 +
 target/alpha/cpu-param.h  |  2 +-
 target/arm/cpu-param.h|  2 +-
 target/avr/cpu-param.h|  2 +-
 target/cris/cpu-param.h   |  2 +-
 target/hppa/cpu-param.h   |  2 +-
 target/i386/cpu-param.h   |  2 +-
 target/loongarch/cpu-param.h  |  2 +-
 target/m68k/cpu-param.h   |  2 +-
 target/microblaze/cpu-param.h |  2 +-
 target/mips/cpu-param.h   |  2 +-
 target/nios2/cpu-param.h  |  2 +-
 target/openrisc/cpu-param.h   |  2 +-
 target/ppc/cpu-param.h|  2 +-
 target/riscv/cpu-param.h  |  2 +-
 target/rx/cpu-param.h |  2 +-
 target/s390x/cpu-param.h  |  2 +-
 target/sh4/cpu-param.h|  2 +-
 target/sparc/cpu-param.h  |  4 ++--
 target/tricore/cpu-param.h|  2 +-
 target/xtensa/cpu-param.h |  2 +-
 accel/tcg/cputlb.c|  3 +++
 page-vary-common.c|  1 +
 page-vary-target.c|  4 ++--
 target/arm/tcg/translate.c|  4 ++--
 27 files changed, 37 insertions(+), 32 deletions(-)

diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 5340907cfd..a1e4dee6a2 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -155,12 +155,15 @@ static inline void stl_phys_notdirty(AddressSpace *as, 
hwaddr addr, uint32_t val
 # include "exec/page-vary.h"
 extern const TargetPageBits target_page;
 #ifdef CONFIG_DEBUG_TCG
+#define TARGET_PAGE_BITS_MIN ({ assert(target_page.decided); \
+target_page.bits_min; })
 #define TARGET_PAGE_BITS   ({ assert(target_page.decided); target_page.bits; })
 #define TARGET_PAGE_MASK   ({ assert(target_page.decided); \
   (target_long)target_page.mask; })
 #else
-#define TARGET_PAGE_BITS   target_page.bits
-#define TARGET_PAGE_MASK   ((target_long)target_page.mask)
+#define TARGET_PAGE_BITS_MIN target_page.bits_min
+#define TARGET_PAGE_BITS target_page.bits
+#define TARGET_PAGE_MASK ((target_long)target_page.mask)
 #endif
 #define TARGET_PAGE_SIZE   (-(int)TARGET_PAGE_MASK)
 #else
@@ -380,9 +383,6 @@ CPUArchState *cpu_copy(CPUArchState *env);
 
 #define TLB_SLOW_FLAGS_MASK  (TLB_BSWAP | TLB_WATCHPOINT)
 
-/* The two sets of flags must not overlap. */
-QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
-
 /**
  * tlb_hit_page: return true if page aligned @addr is a hit against the
  * TLB entry @tlb_addr
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 3915438b83..e8ccbe4bef 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -44,8 +44,8 @@
 #endif
 #ifndef TARGET_PAGE_BITS
 # ifdef TARGET_PAGE_BITS_VARY
-#  ifndef TARGET_PAGE_BITS_MIN
-#   error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h
+#  ifndef TARGET_PAGE_BITS_MIN_SPECIFIC
+#   error TARGET_PAGE_BITS_MIN_SPECIFIC must be defined in cpu-param.h
 #  endif
 # else
 #  error TARGET_PAGE_BITS must be defined in cpu-param.h
diff --git a/include/exec/page-vary.h b/include/exec/page-vary.h
index 54ddde308a..add1282a7c 100644
--- a/include/exec/page-vary.h
+++ b/include/exec/page-vary.h
@@ -22,6 +22,7 @@
 
 typedef struct {
 bool decided;
+int bits_min;
 int bits;
 uint64_t mask;
 } TargetPageBits;
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
index dc9da45bdf..7001b130d6 100644
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@@ -14,7 +14,7 @@
 #define TARGET_PAGE_BITS 13
 #else
 #define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 13
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 13
 #endif
 
 /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44.  */
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index f9b462a98f..442feb5380 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -29,7 +29,7 @@
  * have to support 1K tiny pages.
  */
 # define TARGET_PAGE_BITS_VARY
-# define TARGET_PAGE_BITS_MIN  10
+# define TARGET_PAGE_BITS_MIN_SPECIFIC  10
 
 #endif
 
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index 87142069fe..e9b011a50d 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@@ -32,7 +32,7 @@
 #define TARGET_PAGE_BITS 8
 #else
 #define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 8
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 8
 #endif
 
 #define 

[RFC PATCH 25/34] accel/tcg: [CPUTLB] Use tcg_ctx->mo_te instead of MO_TE

[Anton Johansson via]

Makes *_code() memory access functions target independent.

Signed-off-by: Anton Johansson 
---
 accel/tcg/cputlb.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index a75a52d141..bfbbfd0fdb 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2988,19 +2988,22 @@ uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr)
 
 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr)
 {
-MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true));
+MemOpIdx oi = make_memop_idx(tcg_ctx->mo_te | MO_UW,
+ cpu_mmu_index(env, true));
 return do_ld2_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH);
 }
 
 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr)
 {
-MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true));
+MemOpIdx oi = make_memop_idx(tcg_ctx->mo_te | MO_UL,
+ cpu_mmu_index(env, true));
 return do_ld4_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH);
 }
 
 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr)
 {
-MemOpIdx oi = make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true));
+MemOpIdx oi = make_memop_idx(tcg_ctx->mo_te | MO_UQ,
+ cpu_mmu_index(env, true));
 return do_ld8_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH);
 }
 
-- 
2.43.0

[RFC PATCH 29/34] accel/tcg: Make tb-maint.c target indpendent

[Anton Johansson via]

Uses target_has_precise_smc() and target_phys_addr_space_bits() to turn
ifdefs into runtime branches.

Signed-off-by: Anton Johansson 
---
 accel/tcg/tb-maint.c | 47 +++-
 1 file changed, 25 insertions(+), 22 deletions(-)

diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c
index b194f8f065..fdc3a30d0d 100644
--- a/accel/tcg/tb-maint.c
+++ b/accel/tcg/tb-maint.c
@@ -148,14 +148,6 @@ static PageForEachNext foreach_tb_next(PageForEachNext tb,
 }
 
 #else
-/*
- * In system mode we want L1_MAP to be based on ram offsets.
- */
-#if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS
-# define L1_MAP_ADDR_SPACE_BITS  HOST_LONG_BITS
-#else
-# define L1_MAP_ADDR_SPACE_BITS  TARGET_PHYS_ADDR_SPACE_BITS
-#endif
 
 /* Size of the L2 (and L3, etc) page tables.  */
 #define V_L2_BITS 10
@@ -186,17 +178,28 @@ struct PageDesc {
 
 void page_table_config_init(void)
 {
+int target_phys_addr_bits = target_phys_addr_space_bits();
+uint32_t l1_map_addr_space_bits;
 uint32_t v_l1_bits;
 
+/*
+ * In system mode we want L1_MAP to be based on ram offsets.
+ */
+if (HOST_LONG_BITS < target_phys_addr_bits) {
+l1_map_addr_space_bits = HOST_LONG_BITS;
+} else {
+l1_map_addr_space_bits = target_phys_addr_bits;
+}
+
 assert(TARGET_PAGE_BITS);
 /* The bits remaining after N lower levels of page tables.  */
-v_l1_bits = (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % V_L2_BITS;
+v_l1_bits = (l1_map_addr_space_bits - TARGET_PAGE_BITS) % V_L2_BITS;
 if (v_l1_bits < V_L1_MIN_BITS) {
 v_l1_bits += V_L2_BITS;
 }
 
 v_l1_size = 1 << v_l1_bits;
-v_l1_shift = L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - v_l1_bits;
+v_l1_shift = l1_map_addr_space_bits - TARGET_PAGE_BITS - v_l1_bits;
 v_l2_levels = v_l1_shift / V_L2_BITS - 1;
 
 assert(v_l1_bits <= V_L1_MAX_BITS);
@@ -1045,14 +1048,15 @@ bool tb_invalidate_phys_page_unwind(tb_page_addr_t 
addr, uintptr_t pc)
 TranslationBlock *tb;
 PageForEachNext n;
 tb_page_addr_t last;
+const bool has_precise_smc = target_has_precise_smc();
 
 /*
  * Without precise smc semantics, or when outside of a TB,
  * we can skip to invalidate.
  */
-#ifndef TARGET_HAS_PRECISE_SMC
-pc = 0;
-#endif
+if (!has_precise_smc) {
+pc = 0;
+}
 if (!pc) {
 tb_invalidate_phys_page(addr);
 return false;
@@ -1102,10 +1106,13 @@ tb_invalidate_phys_page_range__locked(struct 
page_collection *pages,
 {
 TranslationBlock *tb;
 PageForEachNext n;
-#ifdef TARGET_HAS_PRECISE_SMC
+const bool has_precise_smc = target_has_precise_smc();
 bool current_tb_modified = false;
-TranslationBlock *current_tb = retaddr ? tcg_tb_lookup(retaddr) : NULL;
-#endif /* TARGET_HAS_PRECISE_SMC */
+TranslationBlock *current_tb = NULL;
+
+if (has_precise_smc && retaddr) {
+current_tb = tcg_tb_lookup(retaddr);
+}
 
 /* Range may not cross a page. */
 tcg_debug_assert(((start ^ last) & TARGET_PAGE_MASK) == 0);
@@ -1127,8 +1134,7 @@ tb_invalidate_phys_page_range__locked(struct 
page_collection *pages,
 tb_last = tb_start + (tb_last & ~TARGET_PAGE_MASK);
 }
 if (!(tb_last < start || tb_start > last)) {
-#ifdef TARGET_HAS_PRECISE_SMC
-if (current_tb == tb &&
+if (has_precise_smc && current_tb == tb &&
 (tb_cflags(current_tb) & CF_COUNT_MASK) != 1) {
 /*
  * If we are modifying the current TB, we must stop
@@ -1140,7 +1146,6 @@ tb_invalidate_phys_page_range__locked(struct 
page_collection *pages,
 current_tb_modified = true;
 cpu_restore_state_from_tb(current_cpu, current_tb, retaddr);
 }
-#endif /* TARGET_HAS_PRECISE_SMC */
 tb_phys_invalidate__locked(tb);
 }
 }
@@ -1150,15 +1155,13 @@ tb_invalidate_phys_page_range__locked(struct 
page_collection *pages,
 tlb_unprotect_code(start);
 }
 
-#ifdef TARGET_HAS_PRECISE_SMC
-if (current_tb_modified) {
+if (has_precise_smc && current_tb_modified) {
 page_collection_unlock(pages);
 /* Force execution of one insn next time.  */
 current_cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(current_cpu);
 mmap_unlock();
 cpu_loop_exit_noexc(current_cpu);
 }
-#endif
 }
 
 /*
-- 
2.43.0

[RFC PATCH 11/34] [IGNORE] Squash of header code shuffling

[Anton Johansson via]

This commit squashes header changes that are likely to change during
rebase. Code is moved from common to specific headers, or vice versa
to ensure that no target-specific code is pulled by accel/tcg via
headers.

Signed-off-by: Anton Johansson 
---
 accel/tcg/tb-hash.h|   4 +-
 hw/s390x/s390-virtio-hcall.h   |   2 +
 include/exec/cpu-all.h |   1 +
 include/exec/cpu-common.h  |   2 +
 include/exec/cpu_ldst-target.h |  52 +
 include/exec/cpu_ldst.h|  60 ++
 include/exec/exec-all.h| 347 +--
 include/exec/exec-common.h | 367 +
 include/exec/memory-internal.h |   2 +-
 include/exec/ram_addr.h|   3 +-
 include/qemu/plugin-memory.h   |   1 -
 accel/tcg/cpu-exec.c   |   1 +
 plugins/core.c |   1 +
 target/arm/cpu.c   |   1 +
 target/sparc/gdbstub.c |   3 +
 15 files changed, 459 insertions(+), 388 deletions(-)
 create mode 100644 include/exec/cpu_ldst-target.h
 create mode 100644 include/exec/exec-common.h

diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h
index a0c61f25cd..2569810365 100644
--- a/accel/tcg/tb-hash.h
+++ b/accel/tcg/tb-hash.h
@@ -20,8 +20,8 @@
 #ifndef EXEC_TB_HASH_H
 #define EXEC_TB_HASH_H
 
-#include "exec/cpu-defs.h"
-#include "exec/exec-all.h"
+#include "exec/exec-common.h"
+#include "exec/translation-block.h"
 #include "qemu/xxhash.h"
 #include "tb-jmp-cache.h"
 
diff --git a/hw/s390x/s390-virtio-hcall.h b/hw/s390x/s390-virtio-hcall.h
index 9800c4b351..0e48dbf71f 100644
--- a/hw/s390x/s390-virtio-hcall.h
+++ b/hw/s390x/s390-virtio-hcall.h
@@ -12,6 +12,8 @@
 #ifndef HW_S390_VIRTIO_HCALL_H
 #define HW_S390_VIRTIO_HCALL_H
 
+#include "qemu/osdep.h"
+#include "cpu.h"
 #include "standard-headers/asm-s390/virtio-ccw.h"
 
 /* The only thing that we need from the old kvm_virtio.h file */
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 83165b1ce4..483e762f05 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -20,6 +20,7 @@
 #define CPU_ALL_H
 
 #include "exec/cpu-common.h"
+#include "exec/cpu-defs.h"
 #include "exec/memory.h"
 #include "exec/tswap.h"
 #include "qemu/thread.h"
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index c071f1a003..2eb6589764 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -3,6 +3,8 @@
 
 /* CPU interfaces that are target independent.  */
 
+#include "qemu/osdep.h"
+#include "hw/core/cpu.h"
 #ifndef CONFIG_USER_ONLY
 #include "exec/hwaddr.h"
 #endif
diff --git a/include/exec/cpu_ldst-target.h b/include/exec/cpu_ldst-target.h
new file mode 100644
index 00..4fdec4a3ff
--- /dev/null
+++ b/include/exec/cpu_ldst-target.h
@@ -0,0 +1,52 @@
+#ifndef CPU_LDST_SPECIFIC_H
+#define CPU_LDST_SPECIFIC_H
+
+#include "cpu-param.h"
+
+#if TARGET_BIG_ENDIAN
+# define cpu_lduw_datacpu_lduw_be_data
+# define cpu_ldsw_datacpu_ldsw_be_data
+# define cpu_ldl_data cpu_ldl_be_data
+# define cpu_ldq_data cpu_ldq_be_data
+# define cpu_lduw_data_ra cpu_lduw_be_data_ra
+# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
+# define cpu_ldl_data_ra  cpu_ldl_be_data_ra
+# define cpu_ldq_data_ra  cpu_ldq_be_data_ra
+# define cpu_lduw_mmuidx_ra   cpu_lduw_be_mmuidx_ra
+# define cpu_ldsw_mmuidx_ra   cpu_ldsw_be_mmuidx_ra
+# define cpu_ldl_mmuidx_racpu_ldl_be_mmuidx_ra
+# define cpu_ldq_mmuidx_racpu_ldq_be_mmuidx_ra
+# define cpu_stw_data cpu_stw_be_data
+# define cpu_stl_data cpu_stl_be_data
+# define cpu_stq_data cpu_stq_be_data
+# define cpu_stw_data_ra  cpu_stw_be_data_ra
+# define cpu_stl_data_ra  cpu_stl_be_data_ra
+# define cpu_stq_data_ra  cpu_stq_be_data_ra
+# define cpu_stw_mmuidx_racpu_stw_be_mmuidx_ra
+# define cpu_stl_mmuidx_racpu_stl_be_mmuidx_ra
+# define cpu_stq_mmuidx_racpu_stq_be_mmuidx_ra
+#else
+# define cpu_lduw_datacpu_lduw_le_data
+# define cpu_ldsw_datacpu_ldsw_le_data
+# define cpu_ldl_data cpu_ldl_le_data
+# define cpu_ldq_data cpu_ldq_le_data
+# define cpu_lduw_data_ra cpu_lduw_le_data_ra
+# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
+# define cpu_ldl_data_ra  cpu_ldl_le_data_ra
+# define cpu_ldq_data_ra  cpu_ldq_le_data_ra
+# define cpu_lduw_mmuidx_ra   cpu_lduw_le_mmuidx_ra
+# define cpu_ldsw_mmuidx_ra   cpu_ldsw_le_mmuidx_ra
+# define cpu_ldl_mmuidx_racpu_ldl_le_mmuidx_ra
+# define cpu_ldq_mmuidx_racpu_ldq_le_mmuidx_ra
+# define cpu_stw_data cpu_stw_le_data
+# define cpu_stl_data cpu_stl_le_data
+# define cpu_stq_data cpu_stq_le_data
+# define cpu_stw_data_ra  cpu_stw_le_data_ra
+# define cpu_stl_data_ra  cpu_stl_le_data_ra
+# define cpu_stq_data_ra  cpu_stq_le_data_ra
+# define cpu_stw_mmuidx_racpu_stw_le_mmuidx_ra
+# define cpu_stl_mmuidx_racpu_stl_le_mmuidx_ra
+# define cpu_stq_mmuidx_racpu_stq_le_mmuidx_ra
+#endif
+
+#endif

[RFC PATCH 01/34] target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets

[Anton Johansson via]

Allows for future commits to use TargetPageBits to access page bits and
mask, thus making TARGET_PAGE_* independent of softmmu target.

In the future, this will also be important fo allowing heterogeneous CPUs
on the same board.

Signed-off-by: Anton Johansson 
---
 target/alpha/cpu-param.h  |  6 ++
 target/avr/cpu-param.h|  6 ++
 target/cris/cpu-param.h   |  7 +++
 target/hppa/cpu-param.h   |  6 ++
 target/i386/cpu-param.h   |  6 ++
 target/loongarch/cpu-param.h  |  5 +
 target/m68k/cpu-param.h   |  6 ++
 target/microblaze/cpu-param.h |  6 --
 target/nios2/cpu-param.h  |  5 -
 target/openrisc/cpu-param.h   |  8 +++-
 target/ppc/cpu-param.h|  6 ++
 target/riscv/cpu-param.h  |  7 +++
 target/rx/cpu-param.h |  8 +++-
 target/s390x/cpu-param.h  |  8 +++-
 target/sh4/cpu-param.h|  4 +++-
 target/sparc/cpu-param.h  | 17 +++--
 target/tricore/cpu-param.h|  8 +++-
 target/xtensa/cpu-param.h |  8 +---
 18 files changed, 114 insertions(+), 13 deletions(-)

diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
index 68c46f7998..dc9da45bdf 100644
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@@ -9,7 +9,13 @@
 #define ALPHA_CPU_PARAM_H
 
 #define TARGET_LONG_BITS 64
+
+#ifdef CONFIG_USER_ONLY
 #define TARGET_PAGE_BITS 13
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 13
+#endif
 
 /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44.  */
 #define TARGET_PHYS_ADDR_SPACE_BITS  44
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index 9a92bc74fc..87142069fe 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@@ -28,7 +28,13 @@
  * should be implemented as a device and not memory
  * 2.  SRAM starts at the address 0x0100
  */
+#ifdef CONFIG_USER_ONLY
 #define TARGET_PAGE_BITS 8
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 8
+#endif
+
 #define TARGET_PHYS_ADDR_SPACE_BITS 24
 #define TARGET_VIRT_ADDR_SPACE_BITS 24
 
diff --git a/target/cris/cpu-param.h b/target/cris/cpu-param.h
index b31b742c0d..9c66ca9e66 100644
--- a/target/cris/cpu-param.h
+++ b/target/cris/cpu-param.h
@@ -9,7 +9,14 @@
 #define CRIS_CPU_PARAM_H
 
 #define TARGET_LONG_BITS 32
+
+#ifdef CONFIG_USER_ONLY
 #define TARGET_PAGE_BITS 13
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 13
+#endif
+
 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index c2791ae5f2..781dbc17d3 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -28,6 +28,12 @@
 # define TARGET_VIRT_ADDR_SPACE_BITS  64
 # define TARGET_PHYS_ADDR_SPACE_BITS  32
 #endif
+
+#ifdef CONFIG_USER_ONLY
 #define TARGET_PAGE_BITS 12
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 12
+#endif
 
 #endif
diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
index 911b4cd51b..d09d0eb2ed 100644
--- a/target/i386/cpu-param.h
+++ b/target/i386/cpu-param.h
@@ -22,6 +22,12 @@
 # define TARGET_PHYS_ADDR_SPACE_BITS  36
 # define TARGET_VIRT_ADDR_SPACE_BITS  32
 #endif
+
+#ifdef CONFIG_USER_ONLY
 #define TARGET_PAGE_BITS 12
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 12
+#endif
 
 #endif
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index 1265dc7cb5..f537c53ec4 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -12,6 +12,11 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 48
 #define TARGET_VIRT_ADDR_SPACE_BITS 48
 
+#ifdef CONFIG_USER_ONLY
 #define TARGET_PAGE_BITS 14
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 14
+#endif
 
 #endif
diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
index 39dcbcece8..92706969c7 100644
--- a/target/m68k/cpu-param.h
+++ b/target/m68k/cpu-param.h
@@ -14,7 +14,13 @@
  * and m68k linux uses 4k pages
  * use the smallest one
  */
+#ifdef CONFIG_USER_ONLY
 #define TARGET_PAGE_BITS 12
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 12
+#endif
+
 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 
diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h
index 9770b0eb52..51987d330d 100644
--- a/target/microblaze/cpu-param.h
+++ b/target/microblaze/cpu-param.h
@@ -20,13 +20,15 @@
 #define TARGET_LONG_BITS 32
 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
+/* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
+#define TARGET_PAGE_BITS 12
 #else
 #define TARGET_LONG_BITS 64
 #define TARGET_PHYS_ADDR_SPACE_BITS 64
 #define TARGET_VIRT_ADDR_SPACE_BITS 64
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 12
 #endif
 
-/* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
-#define TARGET_PAGE_BITS 12
 
 #endif
diff --git 

[RFC PATCH 27/34] accel/tcg: Make translate-all.c target independent

[Anton Johansson via]

Makes translate-all.c independent of softmmu target by switching

TARGET_LONG_BITS-> target_long_bits()

TARGET_INSN_START_WORDS -> tcg_ctx->insn_start_words,
   target_insn_start_words(),

TCG_GUEST_DEFAULT_MO-> target_default_memory_order()

MO_TE   -> target_endian_memory_order()

Signed-off-by: Anton Johansson 
---
 accel/tcg/translate-all.c | 38 ++
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 9c981d1750..a3ae0c6910 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -65,7 +65,6 @@
 #include "internal-common.h"
 #include "internal-target.h"
 #include "perf.h"
-#include "tcg/insn-start-words.h"
 
 TBContext tb_ctx;
 
@@ -106,7 +105,7 @@ static int64_t decode_sleb128(const uint8_t **pp)
 val |= (int64_t)(byte & 0x7f) << shift;
 shift += 7;
 } while (byte & 0x80);
-if (shift < TARGET_LONG_BITS && (byte & 0x40)) {
+if (shift < target_long_bits() && (byte & 0x40)) {
 val |= -(int64_t)1 << shift;
 }
 
@@ -117,7 +116,7 @@ static int64_t decode_sleb128(const uint8_t **pp)
 /* Encode the data collected about the instructions while compiling TB.
Place the data at BLOCK, and return the number of bytes consumed.
 
-   The logical table consists of TARGET_INSN_START_WORDS target_ulong's,
+   The logical table consists of tcg_ctx->insn_start_words target_ulong's,
which come from the target's insn_start data, followed by a uintptr_t
which comes from the host pc of the end of the code implementing the insn.
 
@@ -128,6 +127,7 @@ static int64_t decode_sleb128(const uint8_t **pp)
 
 static int encode_search(TranslationBlock *tb, uint8_t *block)
 {
+const uint8_t insn_start_words = tcg_ctx->insn_start_words;
 uint8_t *highwater = tcg_ctx->code_gen_highwater;
 uint64_t *insn_data = tcg_ctx->gen_insn_data;
 uint16_t *insn_end_off = tcg_ctx->gen_insn_end_off;
@@ -137,13 +137,13 @@ static int encode_search(TranslationBlock *tb, uint8_t 
*block)
 for (i = 0, n = tb->icount; i < n; ++i) {
 uint64_t prev, curr;
 
-for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
+for (j = 0; j < insn_start_words; ++j) {
 if (i == 0) {
 prev = (!(tb_cflags(tb) & CF_PCREL) && j == 0 ? tb->pc : 0);
 } else {
-prev = insn_data[(i - 1) * TARGET_INSN_START_WORDS + j];
+prev = insn_data[(i - 1) * insn_start_words + j];
 }
-curr = insn_data[i * TARGET_INSN_START_WORDS + j];
+curr = insn_data[i * insn_start_words + j];
 p = encode_sleb128(p, curr - prev);
 }
 prev = (i == 0 ? 0 : insn_end_off[i - 1]);
@@ -165,6 +165,7 @@ static int encode_search(TranslationBlock *tb, uint8_t 
*block)
 static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
uint64_t *data)
 {
+const uint8_t insn_start_words = tcg_ctx->insn_start_words;
 uintptr_t iter_pc = (uintptr_t)tb->tc.ptr;
 const uint8_t *p = tb->tc.ptr + tb->tc.size;
 int i, j, num_insns = tb->icount;
@@ -175,7 +176,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb, 
uintptr_t host_pc,
 return -1;
 }
 
-memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS);
+memset(data, 0, sizeof(uint64_t) * insn_start_words);
 if (!(tb_cflags(tb) & CF_PCREL)) {
 data[0] = tb->pc;
 }
@@ -185,7 +186,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb, 
uintptr_t host_pc,
  * at which the end of the insn exceeds host_pc.
  */
 for (i = 0; i < num_insns; ++i) {
-for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
+for (j = 0; j < insn_start_words; ++j) {
 data[j] += decode_sleb128();
 }
 iter_pc += decode_sleb128();
@@ -203,7 +204,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb, 
uintptr_t host_pc,
 void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
uintptr_t host_pc)
 {
-uint64_t data[TARGET_INSN_START_WORDS];
+uint64_t data[tcg_ctx->insn_start_words];
 int insns_left = cpu_unwind_data_from_tb(tb, host_pc, data);
 
 if (insns_left < 0) {
@@ -341,19 +342,15 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
 }
 
 tcg_ctx->gen_tb = tb;
-tcg_ctx->addr_type = TARGET_LONG_BITS == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64;
+tcg_ctx->addr_type = target_long_bits() == 32 ? TCG_TYPE_I32 : 
TCG_TYPE_I64;
 #ifdef CONFIG_SOFTMMU
-tcg_ctx->mo_te = MO_TE;
+tcg_ctx->mo_te = target_endian_memory_order();
 tcg_ctx->page_bits = TARGET_PAGE_BITS;
 tcg_ctx->page_mask = TARGET_PAGE_MASK;
-tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
-#endif
-tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
-#ifdef TCG_GUEST_DEFAULT_MO
-

[RFC PATCH 21/34] accel/tcg: [CPUTLB] Use tcg_ctx->tlb_dyn_max_bits

[Anton Johansson via]

CPU_TLB_DYN_MAX_BITS depends on TARGET_VIRT_ADDR_SPACE_BITS on 64-bit
hosts, and is not yet target independent.

Signed-off-by: Anton Johansson 
---
 accel/tcg/cputlb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 967d5da6d4..42be5b6289 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -172,7 +172,7 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, 
CPUTLBDescFast *fast,
 rate = desc->window_max_entries * 100 / old_size;
 
 if (rate > 70) {
-new_size = MIN(old_size << 1, 1 << CPU_TLB_DYN_MAX_BITS);
+new_size = MIN(old_size << 1, 1 << tcg_ctx->tlb_dyn_max_bits);
 } else if (rate < 30 && window_expired) {
 size_t ceil = pow2ceil(desc->window_max_entries);
 size_t expected_rate = desc->window_max_entries * 100 / ceil;
-- 
2.43.0

[RFC PATCH 26/34] Wrap target macros in functions

[Anton Johansson via]

Adds wrapper functions around common target specific macros required by
accel/tcg.

Signed-off-by: Anton Johansson 
---
 include/hw/core/cpu.h |  9 +++
 cpu-target.c  | 62 +++
 2 files changed, 71 insertions(+)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 57d100c203..a2d65c1d7a 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -26,6 +26,7 @@
 #include "exec/vaddr.h"
 #include "exec/memattrs.h"
 #include "exec/tlb-common.h"
+#include "exec/memop.h"
 #include "qapi/qapi-types-run-state.h"
 #include "qemu/bitmap.h"
 #include "qemu/rcu_queue.h"
@@ -1164,6 +1165,14 @@ void cpu_exec_unrealizefn(CPUState *cpu);
  * what you are doing!
  */
 bool target_words_bigendian(void);
+bool target_supports_mttcg(void);
+bool target_has_precise_smc(void);
+int target_long_bits(void);
+int target_phys_addr_space_bits(void);
+uint8_t target_insn_start_words(void);
+uint8_t target_default_memory_order(void);
+uint8_t target_tlb_dyn_max_bits(void);
+MemOp target_endian_memory_order(void);
 
 const char *target_name(void);
 
diff --git a/cpu-target.c b/cpu-target.c
index 1a8e730bed..6b67af7a51 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -39,10 +39,13 @@
 #include "exec/tb-flush.h"
 #include "exec/translate-all.h"
 #include "exec/log.h"
+#include "exec/cpu-defs.h"
 #include "hw/core/accel-cpu.h"
 #include "trace/trace-root.h"
 #include "qemu/accel.h"
 #include "qemu/plugin.h"
+#include "tcg/tcg-mo.h"
+#include "tcg/insn-start-words.h"
 
 uintptr_t qemu_host_page_size;
 intptr_t qemu_host_page_mask;
@@ -416,6 +419,65 @@ bool target_words_bigendian(void)
 return TARGET_BIG_ENDIAN;
 }
 
+bool target_supports_mttcg(void)
+{
+#ifdef TARGET_SUPPORTS_MTTCG
+# ifndef TCG_GUEST_DEFAULT_MO
+#  error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO"
+# endif
+return true;
+#else
+return false;
+#endif
+}
+
+bool target_has_precise_smc(void)
+{
+#ifdef TARGET_HAS_PRECISE_SMC
+return true;
+#else
+return false;
+#endif
+}
+
+int target_long_bits(void)
+{
+return TARGET_LONG_BITS;
+}
+
+int target_phys_addr_space_bits(void)
+{
+return TARGET_PHYS_ADDR_SPACE_BITS;
+}
+
+uint8_t target_insn_start_words(void)
+{
+return TARGET_INSN_START_WORDS;
+}
+
+uint8_t target_default_memory_order(void)
+{
+#ifdef TCG_GUEST_DEFAULT_MO
+return TCG_GUEST_DEFAULT_MO;
+#else
+return TCG_MO_ALL;
+#endif
+}
+
+MemOp target_endian_memory_order(void)
+{
+return MO_TE;
+}
+
+uint8_t target_tlb_dyn_max_bits(void)
+{
+#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
+return CPU_TLB_DYN_MAX_BITS;
+#else
+return 0;
+#endif
+}
+
 const char *target_name(void)
 {
 return TARGET_NAME;
-- 
2.43.0

[RFC PATCH 28/34] accel/tcg: Make plugin-gen.c target independent

[Anton Johansson via]

Switches computation of offsets into CPUState to use that the offset
between CPUState and CPUArchState is guaranteed to be sizeof(CPUState).

Signed-off-by: Anton Johansson 
---
 accel/tcg/plugin-gen.c | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index d31c9993ea..ce7635958f 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -43,10 +43,9 @@
  * CPU's index into a TCG temp, since the first callback did it already.
  */
 #include "qemu/osdep.h"
-#include "cpu.h"
 #include "tcg/tcg.h"
 #include "tcg/tcg-temp-internal.h"
-#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-common.h"
 #include "exec/exec-all.h"
 #include "exec/plugin-gen.h"
 #include "exec/translator.h"
@@ -104,8 +103,8 @@ static void gen_empty_udata_cb(void)
 TCGv_ptr udata = tcg_temp_ebb_new_ptr();
 
 tcg_gen_movi_ptr(udata, 0);
-tcg_gen_ld_i32(cpu_index, tcg_env,
-   -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index));
+tcg_gen_ld_i32(cpu_index, tcg_env, offsetof(CPUState, cpu_index) -
+   sizeof(CPUState));
 gen_helper_plugin_vcpu_udata_cb(cpu_index, udata);
 
 tcg_temp_free_ptr(udata);
@@ -138,8 +137,8 @@ static void gen_empty_mem_cb(TCGv_i64 addr, uint32_t info)
 
 tcg_gen_movi_i32(meminfo, info);
 tcg_gen_movi_ptr(udata, 0);
-tcg_gen_ld_i32(cpu_index, tcg_env,
-   -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index));
+tcg_gen_ld_i32(cpu_index, tcg_env, offsetof(CPUState, cpu_index) -
+   sizeof(CPUState));
 
 gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, addr, udata);
 
@@ -158,7 +157,7 @@ static void gen_empty_mem_helper(void)
 
 tcg_gen_movi_ptr(ptr, 0);
 tcg_gen_st_ptr(ptr, tcg_env, offsetof(CPUState, plugin_mem_cbs) -
- offsetof(ArchCPU, env));
+ sizeof(CPUState));
 tcg_temp_free_ptr(ptr);
 }
 
@@ -582,7 +581,7 @@ void plugin_gen_disable_mem_helpers(void)
 return;
 }
 tcg_gen_st_ptr(tcg_constant_ptr(NULL), tcg_env,
-   offsetof(CPUState, plugin_mem_cbs) - offsetof(ArchCPU, 
env));
+   offsetof(CPUState, plugin_mem_cbs) - sizeof(CPUState));
 }
 
 static void plugin_gen_tb_udata(const struct qemu_plugin_tb *ptb,
-- 
2.43.0

[RFC PATCH 06/34] exec: [VADDR] Move vaddr defines to separate file

[Anton Johansson via]

Needed to work around circular includes. vaddr is currently defined in
cpu-common.h and needed by hw/core/cpu.h, but cpu-common.h also need
cpu.h to know the size of the CPUState.

[Maybe we can instead move parts of cpu-common.h w. hw/core/cpu.h to
sort out the circular inclusion.]

Signed-off-by: Anton Johansson 
---
 include/exec/cpu-common.h | 12 
 include/exec/vaddr.h  | 18 ++
 2 files changed, 18 insertions(+), 12 deletions(-)
 create mode 100644 include/exec/vaddr.h

diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index df53252d51..c071f1a003 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -14,18 +14,6 @@
 #define EXCP_YIELD  0x10004 /* cpu wants to yield timeslice to another */
 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
 
-/**
- * vaddr:
- * Type wide enough to contain any #target_ulong virtual address.
- */
-typedef uint64_t vaddr;
-#define VADDR_PRId PRId64
-#define VADDR_PRIu PRIu64
-#define VADDR_PRIo PRIo64
-#define VADDR_PRIx PRIx64
-#define VADDR_PRIX PRIX64
-#define VADDR_MAX UINT64_MAX
-
 /**
  * Variable page size macros
  *
diff --git a/include/exec/vaddr.h b/include/exec/vaddr.h
new file mode 100644
index 00..db48bb16bc
--- /dev/null
+++ b/include/exec/vaddr.h
@@ -0,0 +1,18 @@
+/* Define vaddr if it exists.  */
+
+#ifndef VADDR_H
+#define VADDR_H
+
+/**
+ * vaddr:
+ * Type wide enough to contain any #target_ulong virtual address.
+ */
+typedef uint64_t vaddr;
+#define VADDR_PRId PRId64
+#define VADDR_PRIu PRIu64
+#define VADDR_PRIo PRIo64
+#define VADDR_PRIx PRIx64
+#define VADDR_PRIX PRIX64
+#define VADDR_MAX UINT64_MAX
+
+#endif
-- 
2.43.0

[RFC PATCH 09/34] exec: [VADDR] Use vaddr in DisasContextBase for virtual addresses

[Anton Johansson via]

Updates target/ QEMU_LOG macros to use VADDR_PRIx for printing updated
DisasContextBase fields.

Signed-off-by: Anton Johansson 
---
 include/exec/translator.h   |  6 +++---
 target/mips/tcg/translate.h |  3 ++-
 target/hexagon/translate.c  |  3 ++-
 target/m68k/translate.c |  2 +-
 target/mips/tcg/translate.c | 12 ++--
 5 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/include/exec/translator.h b/include/exec/translator.h
index 2ab8f58bea..c4b46ec8aa 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -77,8 +77,8 @@ typedef enum DisasJumpType {
  */
 typedef struct DisasContextBase {
 TranslationBlock *tb;
-target_ulong pc_first;
-target_ulong pc_next;
+vaddr pc_first;
+vaddr pc_next;
 DisasJumpType is_jmp;
 int num_insns;
 int max_insns;
@@ -231,7 +231,7 @@ void translator_fake_ldb(uint8_t insn8, abi_ptr pc);
  * Translators can use this to enforce the rule that only single-insn
  * translation blocks are allowed to cross page boundaries.
  */
-static inline bool is_same_page(const DisasContextBase *db, target_ulong addr)
+static inline bool is_same_page(const DisasContextBase *db, vaddr addr)
 {
 return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) == 0;
 }
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index cffcfeab8c..93a78b8121 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -202,7 +202,8 @@ extern TCGv bcond;
 do {  \
 if (MIPS_DEBUG_DISAS) {   \
 qemu_log_mask(CPU_LOG_TB_IN_ASM,  \
-  TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
+  "%016" VADDR_PRIx   \
+  ": %08x Invalid %s %03x %03x %03x\n",   \
   ctx->base.pc_next, ctx->opcode, op, \
   ctx->opcode >> 26, ctx->opcode & 0x3F,  \
   ((ctx->opcode >> 16) & 0x1F));  \
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 2ef6a89622..7988e54f7d 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -234,7 +234,8 @@ static int read_packet_words(CPUHexagonState *env, 
DisasContext *ctx,
 g_assert(ctx->base.num_insns == 1);
 }
 
-HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next);
+HEX_DEBUG_LOG("decode_packet: pc = 0x%" VADDR_PRIx "\n",
+  ctx->base.pc_next);
 HEX_DEBUG_LOG("words = { ");
 for (int i = 0; i < nwords; i++) {
 HEX_DEBUG_LOG("0x%x, ", words[i]);
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 3408385fa1..a51fdef32a 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -1474,7 +1474,7 @@ DISAS_INSN(undef)
  * for the 680x0 series, as well as those that are implemented
  * but actually illegal for CPU32 or pre-68020.
  */
-qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n",
+qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %" VADDR_PRIx "\n",
   insn, s->base.pc_next);
 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
 }
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 2cc4945793..c5a7378dee 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -4585,8 +4585,8 @@ static void gen_compute_branch(DisasContext *ctx, 
uint32_t opc,
 
 if (ctx->hflags & MIPS_HFLAG_BMASK) {
 #ifdef MIPS_DEBUG_DISAS
-LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
-  TARGET_FMT_lx "\n", ctx->base.pc_next);
+LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016"
+  VADDR_PRIx "\n", ctx->base.pc_next);
 #endif
 gen_reserved_instruction(ctx);
 goto out;
@@ -9061,8 +9061,8 @@ static void gen_compute_branch1_r6(DisasContext *ctx, 
uint32_t op,
 
 if (ctx->hflags & MIPS_HFLAG_BMASK) {
 #ifdef MIPS_DEBUG_DISAS
-LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
-  "\n", ctx->base.pc_next);
+LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016"
+  VADDR_PRIx "\n", ctx->base.pc_next);
 #endif
 gen_reserved_instruction(ctx);
 return;
@@ -11275,8 +11275,8 @@ static void gen_compute_compact_branch(DisasContext 
*ctx, uint32_t opc,
 
 if (ctx->hflags & MIPS_HFLAG_BMASK) {
 #ifdef MIPS_DEBUG_DISAS
-LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
-  "\n", ctx->base.pc_next);
+LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016"
+  VADDR_PRIx "\n", ctx->base.pc_next);
 #endif
 gen_reserved_instruction(ctx);
 return;
-- 
2.43.0

[RFC PATCH 13/34] target: Uninline cpu_get_tb_cpu_state()

[Anton Johansson via]

Required to compile accel/tcg/translate-all.c once for softmmu targets.
The function gets quite big for some targets so uninlining makes sense.

Signed-off-by: Anton Johansson 
---
 include/exec/cpu-common.h |  4 +++
 target/alpha/cpu.h| 11 ---
 target/arm/cpu.h  |  3 --
 target/avr/cpu.h  | 18 ---
 target/cris/cpu.h | 10 --
 target/hexagon/cpu.h  | 12 ---
 target/hppa/cpu.h | 43 -
 target/i386/cpu.h |  9 --
 target/loongarch/cpu.h| 11 ---
 target/m68k/cpu.h | 16 -
 target/microblaze/cpu.h   |  8 -
 target/mips/cpu.h |  9 --
 target/nios2/cpu.h| 12 ---
 target/openrisc/cpu.h | 10 --
 target/ppc/cpu.h  | 13 
 target/riscv/cpu.h|  3 --
 target/rx/cpu.h   |  9 --
 target/s390x/cpu.h| 22 -
 target/sh4/cpu.h  | 15 -
 target/sparc/cpu.h| 35 
 target/tricore/cpu.h  | 12 ---
 target/xtensa/cpu.h   | 68 ---
 target/alpha/cpu.c| 11 +++
 target/avr/cpu.c  | 18 +++
 target/cris/cpu.c | 10 ++
 target/hexagon/cpu.c  | 12 +++
 target/hppa/cpu.c | 47 +++
 target/i386/cpu.c |  9 ++
 target/loongarch/cpu.c| 11 +++
 target/m68k/cpu.c | 16 +
 target/microblaze/cpu.c   |  7 
 target/mips/cpu.c |  9 ++
 target/nios2/cpu.c| 12 +++
 target/openrisc/cpu.c | 10 ++
 target/ppc/cpu.c  | 11 +++
 target/rx/cpu.c   |  9 ++
 target/s390x/cpu.c| 24 ++
 target/sh4/cpu.c  | 15 +
 target/sparc/cpu.c| 35 
 target/tricore/cpu.c  | 12 +++
 target/xtensa/cpu.c   | 68 +++
 41 files changed, 350 insertions(+), 349 deletions(-)

diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 12952c481c..b5dae4a9d6 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -70,6 +70,10 @@ unsigned int cpu_list_generation_id_get(void);
  */
 int cpu_mmu_index(CPUArchState *env, bool ifetch);
 
+void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc,
+  uint64_t *cs_base, uint32_t *pflags);
+
+
 void tcg_flush_softmmu_tlb(CPUState *cs);
 void tcg_flush_jmp_cache(CPUState *cs);
 
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index e93186d50e..09937b32a2 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -452,17 +452,6 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr 
physaddr,
  MemTxResult response, uintptr_t retaddr);
 #endif
 
-static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc,
-uint64_t *cs_base, uint32_t *pflags)
-{
-*pc = env->pc;
-*cs_base = 0;
-*pflags = env->flags & ENV_FLAG_TB_MASK;
-#ifdef CONFIG_USER_ONLY
-*pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
-#endif
-}
-
 #ifdef CONFIG_USER_ONLY
 /* Copied from linux ieee_swcr_to_fpcr.  */
 static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 3dfca8f3ae..9732c836b2 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3212,9 +3212,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env)
 }
 #endif
 
-void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
-  uint64_t *cs_base, uint32_t *flags);
-
 enum {
 QEMU_PSCI_CONDUIT_DISABLED = 0,
 QEMU_PSCI_CONDUIT_SMC = 1,
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 581ba54aae..e454f3ac3c 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -183,24 +183,6 @@ enum {
 TB_FLAGS_SKIP = 2,
 };
 
-static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc,
-uint64_t *cs_base, uint32_t *pflags)
-{
-uint32_t flags = 0;
-
-*pc = env->pc_w * 2;
-*cs_base = 0;
-
-if (env->fullacc) {
-flags |= TB_FLAGS_FULL_ACCESS;
-}
-if (env->skip) {
-flags |= TB_FLAGS_SKIP;
-}
-
-*pflags = flags;
-}
-
 static inline int cpu_interrupts_enabled(CPUAVRState *env)
 {
 return env->sregI != 0;
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 9587a2a229..1312a719b7 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -261,16 +261,6 @@ enum {
 
 #include "exec/cpu-all.h"
 
-static inline void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc,
-uint64_t *cs_base, uint32_t *flags)
-{
-*pc = env->pc;
-*cs_base = 0;
-*flags = env->dslot |
-(env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
-| X_FLAG | PFIX_FLAG));
-}
-
 #define cpu_list cris_cpu_list
 void cris_cpu_list(void);
 

[RFC PATCH 05/34] target/tricore: [VADDR] Use target_ulong for EA

[Anton Johansson via]

Prepares target for typedef'ing abi_ptr to vaddr.  Fixes sign extension
bug that would result from abi_ptr being unsigned in the future.

Necessary to make memory access function signatures target agnostic.

Signed-off-by: Anton Johansson 
---
 target/tricore/op_helper.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 89be1ed648..f57bb39d1f 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2395,7 +2395,7 @@ static bool cdc_zero(target_ulong *psw)
 return count == 0;
 }
 
-static void save_context_upper(CPUTriCoreState *env, int ea)
+static void save_context_upper(CPUTriCoreState *env, target_ulong ea)
 {
 cpu_stl_data(env, ea, env->PCXI);
 cpu_stl_data(env, ea+4, psw_read(env));
@@ -2415,7 +2415,7 @@ static void save_context_upper(CPUTriCoreState *env, int 
ea)
 cpu_stl_data(env, ea+60, env->gpr_d[15]);
 }
 
-static void save_context_lower(CPUTriCoreState *env, int ea)
+static void save_context_lower(CPUTriCoreState *env, target_ulong ea)
 {
 cpu_stl_data(env, ea, env->PCXI);
 cpu_stl_data(env, ea+4, env->gpr_a[11]);
@@ -2435,7 +2435,7 @@ static void save_context_lower(CPUTriCoreState *env, int 
ea)
 cpu_stl_data(env, ea+60, env->gpr_d[7]);
 }
 
-static void restore_context_upper(CPUTriCoreState *env, int ea,
+static void restore_context_upper(CPUTriCoreState *env, target_ulong ea,
   target_ulong *new_PCXI, target_ulong 
*new_PSW)
 {
 *new_PCXI = cpu_ldl_data(env, ea);
@@ -2456,7 +2456,7 @@ static void restore_context_upper(CPUTriCoreState *env, 
int ea,
 env->gpr_d[15] = cpu_ldl_data(env, ea+60);
 }
 
-static void restore_context_lower(CPUTriCoreState *env, int ea,
+static void restore_context_lower(CPUTriCoreState *env, target_ulong ea,
   target_ulong *ra, target_ulong *pcxi)
 {
 *pcxi = cpu_ldl_data(env, ea);
-- 
2.43.0

[RFC PATCH 19/34] accel/tcg: [CPUTLB] Use TCGContext.addr_type instead of TARGET_LONG_BITS

[Anton Johansson via]

[NOTE: We could also use target_long_bits(), which is introduced later]

Signed-off-by: Anton Johansson 
---
 include/exec/cpu_ldst.h | 31 ---
 accel/tcg/cputlb.c  | 34 --
 2 files changed, 36 insertions(+), 29 deletions(-)

diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 24fe322d72..553e0119f9 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -340,7 +340,7 @@ static inline void clear_helper_retaddr(void)
 
 #else
 
-#include "tcg/oversized-guest.h"
+#include "tcg-target-reg-bits.h"
 
 static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
 MMUAccessType access_type)
@@ -353,20 +353,21 @@ static inline uint64_t tlb_read_idx(const CPUTLBEntry 
*entry,
 QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=
   MMU_INST_FETCH * sizeof(uint64_t));
 
-#if TARGET_LONG_BITS == 32
-/* Use qatomic_read, in case of addr_write; only care about low bits. */
-const uint32_t *ptr = (uint32_t *)>addr_idx[access_type];
-ptr += HOST_BIG_ENDIAN;
-return qatomic_read(ptr);
-#else
-const uint64_t *ptr = >addr_idx[access_type];
-# if TCG_OVERSIZED_GUEST
-return *ptr;
-# else
-/* ofs might correspond to .addr_write, so use qatomic_read */
-return qatomic_read(ptr);
-# endif
-#endif
+if (tcg_ctx->addr_type == TCG_TYPE_I32) {
+/* Use qatomic_read, in case of addr_write; only care about low bits. 
*/
+const uint32_t *ptr = (uint32_t *)>addr_idx[access_type];
+ptr += HOST_BIG_ENDIAN;
+return qatomic_read(ptr);
+} else {
+const uint64_t *ptr = >addr_idx[access_type];
+if (TCG_TARGET_REG_BITS == 32) {
+/* Oversized guest */
+return *ptr;
+} else {
+/* ofs might correspond to .addr_write, so use qatomic_read */
+return qatomic_read(ptr);
+}
+}
 }
 
 static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 449c86301e..967d5da6d4 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -41,7 +41,7 @@
 #include "qemu/plugin-memory.h"
 #endif
 #include "tcg/tcg-ldst.h"
-#include "tcg/oversized-guest.h"
+#include "tcg-target-reg-bits.h"
 
 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
 /* #define DEBUG_TLB */
@@ -815,12 +815,13 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
unsigned bits)
 {
 TLBFlushRangeData d;
+const unsigned long_bits = (tcg_ctx->addr_type == TCG_TYPE_I32) ? 32 : 64;
 
 /*
  * If all bits are significant, and len is small,
  * this devolves to tlb_flush_page.
  */
-if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) {
+if (bits >= long_bits && len <= TARGET_PAGE_SIZE) {
 tlb_flush_page_by_mmuidx(cpu, addr, idxmap);
 return;
 }
@@ -858,12 +859,13 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu,
 {
 TLBFlushRangeData d;
 CPUState *dst_cpu;
+const unsigned long_bits = (tcg_ctx->addr_type == TCG_TYPE_I32) ? 32 : 64;
 
 /*
  * If all bits are significant, and len is small,
  * this devolves to tlb_flush_page.
  */
-if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) {
+if (bits >= long_bits && len <= TARGET_PAGE_SIZE) {
 tlb_flush_page_by_mmuidx_all_cpus(src_cpu, addr, idxmap);
 return;
 }
@@ -908,12 +910,13 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState 
*src_cpu,
 {
 TLBFlushRangeData d, *p;
 CPUState *dst_cpu;
+const unsigned long_bits = (tcg_ctx->addr_type == TCG_TYPE_I32) ? 32 : 64;
 
 /*
  * If all bits are significant, and len is small,
  * this devolves to tlb_flush_page.
  */
-if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) {
+if (bits >= long_bits && len <= TARGET_PAGE_SIZE) {
 tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap);
 return;
 }
@@ -995,16 +998,19 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry 
*tlb_entry,
 addr &= TARGET_PAGE_MASK;
 addr += tlb_entry->addend;
 if ((addr - start) < length) {
-#if TARGET_LONG_BITS == 32
-uint32_t *ptr_write = (uint32_t *)_entry->addr_write;
-ptr_write += HOST_BIG_ENDIAN;
-qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY);
-#elif TCG_OVERSIZED_GUEST
-tlb_entry->addr_write |= TLB_NOTDIRTY;
-#else
-qatomic_set(_entry->addr_write,
-tlb_entry->addr_write | TLB_NOTDIRTY);
-#endif
+if (tcg_ctx->addr_type == TCG_TYPE_I32) {
+/* 32-bit */
+uint32_t *ptr_write = (uint32_t *)_entry->addr_write;
+ptr_write += HOST_BIG_ENDIAN;
+qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY);
+} else if 

Re: [PATCH v2 16/23] exec: Move [b]tswapl() declarations to 'exec/user/tswap-target.h'

[Anton Johansson via]

On 12/12/23, Philippe Mathieu-Daudé wrote:
> tswapl() and bswaptls() are target-dependent and only used
> by user emulation. Move their definitions to a new header:
> "exec/user/tswap-target.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  bsd-user/freebsd/target_os_elf.h   |  1 +
>  bsd-user/freebsd/target_os_stack.h |  1 +
>  bsd-user/netbsd/target_os_elf.h|  1 +
>  bsd-user/openbsd/target_os_elf.h   |  1 +
>  include/exec/cpu-all.h |  8 
>  include/exec/user/abitypes.h   |  1 +
>  include/exec/user/tswap-target.h   | 22 ++
>  bsd-user/signal.c  |  1 +
>  bsd-user/strace.c  |  1 +
>  linux-user/elfload.c   |  1 +
>  linux-user/i386/signal.c   |  1 +
>  linux-user/ppc/signal.c|  1 +
>  12 files changed, 32 insertions(+), 8 deletions(-)
>  create mode 100644 include/exec/user/tswap-target.h
> 
> diff --git a/bsd-user/freebsd/target_os_elf.h 
> b/bsd-user/freebsd/target_os_elf.h
> index 9df17d56d8..27d8ce036c 100644
> --- a/bsd-user/freebsd/target_os_elf.h
> +++ b/bsd-user/freebsd/target_os_elf.h
> @@ -22,6 +22,7 @@
>  
>  #include "target_arch_elf.h"
>  #include "elf.h"
> +#include "exec/user/tswap-target.h"
>  
>  #define bsd_get_ncpu() 1 /* until we pull in bsd-proc.[hc] */
>  
> diff --git a/bsd-user/freebsd/target_os_stack.h 
> b/bsd-user/freebsd/target_os_stack.h
> index d15fc3263f..6125208182 100644
> --- a/bsd-user/freebsd/target_os_stack.h
> +++ b/bsd-user/freebsd/target_os_stack.h
> @@ -23,6 +23,7 @@
>  #include 
>  #include "target_arch_sigtramp.h"
>  #include "qemu/guest-random.h"
> +#include "exec/user/tswap-target.h"
>  
>  /*
>   * The initial FreeBSD stack is as follows:
> diff --git a/bsd-user/netbsd/target_os_elf.h b/bsd-user/netbsd/target_os_elf.h
> index 2f3cb20871..23b422bfce 100644
> --- a/bsd-user/netbsd/target_os_elf.h
> +++ b/bsd-user/netbsd/target_os_elf.h
> @@ -22,6 +22,7 @@
>  
>  #include "target_arch_elf.h"
>  #include "elf.h"
> +#include "exec/user/tswap-target.h"
>  
>  /* this flag is uneffective under linux too, should be deleted */
>  #ifndef MAP_DENYWRITE
> diff --git a/bsd-user/openbsd/target_os_elf.h 
> b/bsd-user/openbsd/target_os_elf.h
> index 6dca9c5a85..fc1dfa2e49 100644
> --- a/bsd-user/openbsd/target_os_elf.h
> +++ b/bsd-user/openbsd/target_os_elf.h
> @@ -22,6 +22,7 @@
>  
>  #include "target_arch_elf.h"
>  #include "elf.h"
> +#include "exec/user/tswap-target.h"
>  
>  /* this flag is uneffective under linux too, should be deleted */
>  #ifndef MAP_DENYWRITE
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index b042d94892..95af418920 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -36,14 +36,6 @@
>  #define BSWAP_NEEDED
>  #endif
>  
> -#if TARGET_LONG_SIZE == 4
> -#define tswapl(s) tswap32(s)
> -#define bswaptls(s) bswap32s(s)
> -#else
> -#define tswapl(s) tswap64(s)
> -#define bswaptls(s) bswap64s(s)
> -#endif
> -
>  /* Target-endianness CPU memory access functions. These fit into the
>   * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
>   */
> diff --git a/include/exec/user/abitypes.h b/include/exec/user/abitypes.h
> index 6178453d94..ed10d5fe7e 100644
> --- a/include/exec/user/abitypes.h
> +++ b/include/exec/user/abitypes.h
> @@ -2,6 +2,7 @@
>  #define EXEC_USER_ABITYPES_H
>  
>  #include "cpu.h"
> +#include "exec/user/tswap-target.h"
>  
>  #ifdef TARGET_ABI32
>  #define TARGET_ABI_BITS 32
> diff --git a/include/exec/user/tswap-target.h 
> b/include/exec/user/tswap-target.h
> new file mode 100644
> index 00..ff302436fe
> --- /dev/null
> +++ b/include/exec/user/tswap-target.h
> @@ -0,0 +1,22 @@
> +/*
> + * target-specific swap() definitions
> + *
> + *  Copyright (c) 2003 Fabrice Bellard
> + *
> + * SPDX-License-Identifier: LGPL-2.1-or-later
> + */
> +#ifndef EXEC_USER_TSWAP_H
> +#define EXEC_USER_TSWAP_H
> +
> +#include "exec/cpu-defs.h"
> +#include "exec/tswap.h"
> +
> +#if TARGET_LONG_SIZE == 4
> +#define tswapl(s) tswap32(s)
> +#define bswaptls(s) bswap32s(s)
> +#else
> +#define tswapl(s) tswap64(s)
> +#define bswaptls(s) bswap64s(s)
> +#endif
> +
> +#endif
> diff --git a/bsd-user/signal.c b/bsd-user/signal.c
> index ca31470772..7b2d25230a 100644
> --- a/bsd-user/signal.c
> +++ b/bsd-user/signal.c
> @@ -21,6 +21,7 @@
>  #include "qemu/osdep.h"
>  #include "qemu/log.h"
>  #include "qemu.h"
> +#include "exec/user/tswap-target.h"
>  #include "gdbstub/user.h"
>  #include "signal-common.h"
>  #include "trace.h"
> diff --git a/bsd-user/strace.c b/bsd-user/strace.c
> index 96499751eb..a1b738e63c 100644
> --- a/bsd-user/strace.c
> +++ b/bsd-user/strace.c
> @@ -22,6 +22,7 @@
>  #include 
>  
>  #include "qemu.h"
> +#include "exec/user/tswap-target.h"
>  
>  #include "os-strace.h"  /* OS dependent strace print functions */
>  
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index cf9e74468b..debea5c355 100644
> --- a/linux-user/elfload.c
> +++ 

Re: [PATCH v2 14/23] exec/cpu-all: Remove unused tswapls() definitions

[Anton Johansson via]

On 12/12/23, Philippe Mathieu-Daudé wrote:
> Last use of tswapls() was removed 2 years ago in commit
> aee14c77f4 ("linux-user: Rewrite do_getdents, do_getdents64").
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  include/exec/cpu-all.h | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index 5b5379b94c..b042d94892 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -38,11 +38,9 @@
>  
>  #if TARGET_LONG_SIZE == 4
>  #define tswapl(s) tswap32(s)
> -#define tswapls(s) tswap32s((uint32_t *)(s))
>  #define bswaptls(s) bswap32s(s)
>  #else
>  #define tswapl(s) tswap64(s)
> -#define tswapls(s) tswap64s((uint64_t *)(s))
>  #define bswaptls(s) bswap64s(s)
>  #endif
>  
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH v2 12/23] exec/cpu-all: Remove unused 'qemu/thread.h' header

[Anton Johansson via]

On 12/12/23, Philippe Mathieu-Daudé wrote:
> Nothing is required from the "qemu/thread.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  include/exec/cpu-all.h | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index 9a7b5737d3..26b44ca125 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -22,7 +22,6 @@
>  #include "exec/cpu-common.h"
>  #include "exec/memory.h"
>  #include "exec/tswap.h"
> -#include "qemu/thread.h"
>  #include "hw/core/cpu.h"
>  #include "qemu/rcu.h"
>  
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH v2 11/23] accel/tcg: Include missing 'hw/core/cpu.h' header

[Anton Johansson via]

On 12/12/23, Philippe Mathieu-Daudé wrote:
> tcg_cpu_init_cflags() accesses CPUState fields, so requires
> "hw/core/cpu.h" to get its structure definition.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  accel/tcg/tcg-accel-ops.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
> index 1b57290682..58806e2d7f 100644
> --- a/accel/tcg/tcg-accel-ops.c
> +++ b/accel/tcg/tcg-accel-ops.c
> @@ -37,6 +37,8 @@
>  #include "exec/tb-flush.h"
>  #include "exec/gdbstub.h"
>  
> +#include "hw/core/cpu.h"
> +
>  #include "tcg-accel-ops.h"
>  #include "tcg-accel-ops-mttcg.h"
>  #include "tcg-accel-ops-rr.h"
> -- 
> 2.41.0
> 
Reviewed-by: Anton Johansson 

Re: [PATCH v2 09/23] host/atomic128: Include missing 'qemu/atomic.h' header

[Anton Johansson via]

On 12/12/23, Philippe Mathieu-Daudé wrote:
> qatomic_cmpxchg__nocheck(), qatomic_read__nocheck(),
> qatomic_set__nocheck() are defined in "qemu/atomic.h".
> Include it in order to avoid:
> 
>   In file included from include/exec/helper-proto.h:10:
>   In file included from include/exec/helper-proto-common.h:10:
>   In file included from include/qemu/atomic128.h:61:
>   In file included from host/include/aarch64/host/atomic128-cas.h:16:
>   host/include/generic/host/atomic128-cas.h:23:11: error: call to undeclared 
> function 'qatomic_cmpxchg__nocheck'; ISO C99 and later do not support 
> implicit function declarations [-Wimplicit-function-declaration]
> r.i = qatomic_cmpxchg__nocheck(ptr_align, c.i, n.i);
>   ^
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  host/include/generic/host/atomic128-cas.h  | 2 ++
>  host/include/generic/host/atomic128-ldst.h | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/host/include/generic/host/atomic128-cas.h 
> b/host/include/generic/host/atomic128-cas.h
> index 6b40cc2271..4824f14659 100644
> --- a/host/include/generic/host/atomic128-cas.h
> +++ b/host/include/generic/host/atomic128-cas.h
> @@ -11,6 +11,8 @@
>  #ifndef HOST_ATOMIC128_CAS_H
>  #define HOST_ATOMIC128_CAS_H
>  
> +#include "qemu/atomic.h"
> +
>  #if defined(CONFIG_ATOMIC128)
>  static inline Int128 ATTRIBUTE_ATOMIC128_OPT
>  atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new)
> diff --git a/host/include/generic/host/atomic128-ldst.h 
> b/host/include/generic/host/atomic128-ldst.h
> index 691e6a8531..12e4aca2da 100644
> --- a/host/include/generic/host/atomic128-ldst.h
> +++ b/host/include/generic/host/atomic128-ldst.h
> @@ -11,6 +11,8 @@
>  #ifndef HOST_ATOMIC128_LDST_H
>  #define HOST_ATOMIC128_LDST_H
>  
> +#include "qemu/atomic.h"
> +
>  #if defined(CONFIG_ATOMIC128)
>  # define HAVE_ATOMIC128_RO 1
>  # define HAVE_ATOMIC128_RW 1
> -- 
> 2.41.0
> 

What about the int128.h includes? I guess those definitions are acquired 
from atomic128.h that includes -cas.h/-ldst.h?

Re: [PATCH v2 08/23] host/load-extract: Include missing 'qemu/atomic.h' and 'qemu/int128.h'

[Anton Johansson via]

On 12/12/23, Philippe Mathieu-Daudé wrote:
> int128_make128(), int128_getlo() and int128_urshift() are
> declared in "qemu/int128.h". qatomic_read__nocheck() is
> declared in "qemu/atomic.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  host/include/generic/host/load-extract-al16-al8.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/host/include/generic/host/load-extract-al16-al8.h 
> b/host/include/generic/host/load-extract-al16-al8.h
> index d95556130f..6b47339b57 100644
> --- a/host/include/generic/host/load-extract-al16-al8.h
> +++ b/host/include/generic/host/load-extract-al16-al8.h
> @@ -8,6 +8,9 @@
>  #ifndef HOST_LOAD_EXTRACT_AL16_AL8_H
>  #define HOST_LOAD_EXTRACT_AL16_AL8_H
>  
> +#include "qemu/atomic.h"
> +#include "qemu/int128.h"
> +
>  /**
>   * load_atom_extract_al16_or_al8:
>   * @pv: host address
> -- 
> 2.41.0
> 

Reviewed-by: Anton Johansson