Re: [PATCH v4 0/3] hw/riscv/virt: pflash improvements
On Thu, May 30, 2024 at 04:37:56AM -0700, Andrea Bolognani wrote: > On Mon, Nov 20, 2023 at 08:06:19PM GMT, Sunil V L wrote: > > On Mon, Nov 20, 2023 at 02:29:28PM +, Andrea Bolognani wrote: > > > On Fri, May 26, 2023 at 11:10:12AM +0200, Andrew Jones wrote: > > > > > > > So, are edk2 users the only ones who would (temporarily) need to > > > > > > > manually turn ACPI off if virt-manager started enabling it by > > > > > > > default? > > > > > > > > > > > > I assume so, but I'm not tracking firmware status. If the firmware > > > > > > doesn't extract the ACPI tables from QEMU and present them to the > > > > > > guest (afaik only edk2 does that), then the guest kernel falls back > > > > > > to DT, which is why it's working for you. > > > > > > > > > > > > I suppose we should wait until Linux merges the ACPI patches, before > > > > > > adding RISC-V to the libvirt capabilities ACPI list. > > > > > > > > > > That sounds reasonable to me, but note that 1) the libvirt change > > > > > might take a while to propagate to distros and 2) someone will have > > > > > to remind me to prepare such a patch when the time comes ;) > > > > > > > > Initial ACPI support will probably be merged for 6.4. So maybe it is > > > > time to get the libvirt side of things going. > > > > > > Randomly remembered about this. Did ACPI support make it into 6.4 > > > after all? Is now a good time to change libvirt? > > > > Hi Andrea, > > > > Not yet. While basic ACPI changes are merged, the interrupt controller > > support is still going on. Looks like it will take few merge windows to > > get ACPI fully supported. So, we still need to wait for libvirt change. > > Hey, > > I've been working on making RISC-V support a bit smoother across the > virtualization stack recently, and I just so happened to remember > that this topic was still pending. > > I've tried manually switching ACPI on for an existing Fedora RISC-V > guest running under TCG and booting via UEFI, which promptly made it > stop working, so I assume the necessary bits haven't made it into the > kernel yet. > > Is anyone actually tracking that work? We've been waiting for it to > land for a fairly long time at this point... > Hi Andrea, It is still WIP. DT patches (which was a dependency for ACPI) for AIA interrupt controllers got merged recently and available in 6.10-rc1. So, I hope ACPI patches will be merged within next couple of merge windows provided maintainers of different subsystems will have sufficient time to review. Thanks, Sunil
[PATCH 1/3] gpex-acpi: Support PCI link devices outside the host bridge
Currently, PCI link devices (PNP0C0F) are always created within the
scope of the PCI root complex. However, RISC-V needs PCI link devices to
be outside the scope of the PCI host bridge to properly enable the probe
order. This matches the example given in the ACPI specification section
6.2.13.1 as well.
Enable creating link devices outside the scope of PCI root complex based
on the flag which gets set currently only for RISC-V.
Signed-off-by: Sunil V L
---
hw/pci-host/gpex-acpi.c| 29 -
hw/riscv/virt-acpi-build.c | 8 +---
include/hw/pci-host/gpex.h | 5 -
3 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index f69413ea2c..cea89a3ed8 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -7,7 +7,7 @@
#include "hw/pci/pcie_host.h"
#include "hw/acpi/cxl.h"
-static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
+static void acpi_dsdt_add_pci_route_table(Aml *scope, Aml *dev, uint32_t irq)
{
Aml *method, *crs;
int i, slot_no;
@@ -45,7 +45,17 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t
irq)
aml_append(dev_gsi, aml_name_decl("_CRS", crs));
method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
aml_append(dev_gsi, method);
-aml_append(dev, dev_gsi);
+
+/*
+ * Some architectures like RISC-V need PCI link devices created
+ * outside the scope of the PCI host bridge similar to the example
+ * given in the section 6.2.13.1 of ACPI spec 6.5.
+ */
+ if (scope) {
+aml_append(scope, dev_gsi);
+} else {
+aml_append(dev, dev_gsi);
+}
}
}
@@ -174,7 +184,11 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
}
-acpi_dsdt_add_pci_route_table(dev, cfg->irq);
+if (cfg->flags & GPEX_FLAGS_EXT_GSI_LINK) {
+acpi_dsdt_add_pci_route_table(scope, dev, cfg->irq);
+} else {
+acpi_dsdt_add_pci_route_table(NULL, dev, cfg->irq);
+}
/*
* Resources defined for PXBs are composed of the following parts:
@@ -205,7 +219,11 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-acpi_dsdt_add_pci_route_table(dev, cfg->irq);
+if (cfg->flags & GPEX_FLAGS_EXT_GSI_LINK) {
+acpi_dsdt_add_pci_route_table(scope, dev, cfg->irq);
+} else {
+acpi_dsdt_add_pci_route_table(NULL, dev, cfg->irq);
+}
method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
aml_append(method, aml_return(aml_int(cfg->ecam.base)));
@@ -282,7 +300,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
crs_range_set_free(_range_set);
}
-void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq)
+void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq, uint32_t flags)
{
bool ambig;
Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, );
@@ -292,5 +310,6 @@ void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq)
}
GPEX_HOST(obj)->gpex_cfg.irq = irq;
+GPEX_HOST(obj)->gpex_cfg.flags = flags;
acpi_dsdt_add_gpex(scope, _HOST(obj)->gpex_cfg);
}
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 0925528160..832a3acb8d 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -417,19 +417,21 @@ static void build_dsdt(GArray *table_data,
virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
memmap[VIRT_VIRTIO].size,
VIRTIO_IRQ, 0, VIRTIO_COUNT);
-acpi_dsdt_add_gpex_host(scope, PCIE_IRQ);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ, GPEX_FLAGS_EXT_GSI_LINK);
} else if (socket_count == 2) {
virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
memmap[VIRT_VIRTIO].size,
VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
VIRTIO_COUNT);
-acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES,
+GPEX_FLAGS_EXT_GSI_LINK);
} else {
virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
memmap[VIRT_VIRTIO].size,
VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
VIRTIO_COUNT);
-acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES *
2);
+acpi_dsdt_add_gpex_host(scope,
[PATCH 2/3] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
PLIC and APLIC should be in namespace as well. So, add them using the
defined HID.
Signed-off-by: Sunil V L
---
hw/riscv/virt-acpi-build.c | 47 ++
1 file changed, 47 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 832a3acb8d..47ec78e432 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -141,6 +141,52 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState
*s)
}
}
+static void acpi_dsdt_add_plic_aplic(Aml *scope, RISCVVirtState *s)
+{
+MachineState *ms = MACHINE(s);
+uint64_t plic_aplic_addr;
+uint32_t gsi_base;
+uint8_t socket;
+
+if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+/* PLICs */
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+plic_aplic_addr = s->memmap[VIRT_PLIC].base +
+ s->memmap[VIRT_PLIC].size * socket;
+gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+Aml *dev = aml_device("IC%.02X", socket);
+aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0001")));
+aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
+aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(plic_aplic_addr,
+ s->memmap[VIRT_PLIC].size,
+ AML_READ_WRITE));
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(scope, dev);
+}
+} else {
+/* APLICs */
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+plic_aplic_addr = s->memmap[VIRT_APLIC_S].base +
+ s->memmap[VIRT_APLIC_S].size * socket;
+gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+Aml *dev = aml_device("IC%.02X", socket);
+aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0002")));
+aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
+aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(plic_aplic_addr,
+ s->memmap[VIRT_APLIC_S].size,
+ AML_READ_WRITE));
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(scope, dev);
+}
+}
+}
+
static void
acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
uint32_t uart_irq)
@@ -411,6 +457,7 @@ static void build_dsdt(GArray *table_data,
socket_count = riscv_socket_count(ms);
+acpi_dsdt_add_plic_aplic(scope, s);
acpi_dsdt_add_uart(scope, [VIRT_UART0], UART0_IRQ);
if (socket_count == 1) {
--
2.40.1
[PATCH 3/3] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
RISC-V is going to use new HID RSCV0003 for generi UART. So, update the
HID.
Signed-off-by: Sunil V L
---
hw/riscv/virt-acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 47ec78e432..7f80368415 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -192,7 +192,7 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry
*uart_memmap,
uint32_t uart_irq)
{
Aml *dev = aml_device("COM0");
-aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
+aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0003")));
aml_append(dev, aml_name_decl("_UID", aml_int(0)));
Aml *crs = aml_resource_template();
--
2.40.1
[PATCH 0/3] RISC-V: ACPI: Namespace updates
This series adds few updates to RISC-V ACPI namespace for virt platform. 1) PCI Link devices need to be created outside the scope of the PCI root complex to ensure correct probe ordering by the OS. This matches the example given in ACPI spec as well. 2) Add PLIC and APLIC as platform devices as well to ensure probing order as per BRS spec [1] requirement. 3) BRS spec requires RISC-V to use new ACPI ID for the generic UART. So, update the HID of the UART. [1] - https://github.com/riscv-non-isa/riscv-brs Sunil V L (3): gpex-acpi: Support PCI link devices outside the host bridge hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART hw/pci-host/gpex-acpi.c| 29 +++ hw/riscv/virt-acpi-build.c | 57 +++--- include/hw/pci-host/gpex.h | 5 +++- 3 files changed, 81 insertions(+), 10 deletions(-) -- 2.40.1
Re: [PATCH v2 06/12] tests/data/acpi/virt: Move ACPI tables under aarch64
On Mon, May 27, 2024 at 12:12:10PM +0200, Philippe Mathieu-Daudé wrote:
> Hi Sunil,
>
> On 24/5/24 08:14, Sunil V L wrote:
> > Since virt is a common machine name across architectures like ARM64 and
> > RISC-V, move existing ARM64 ACPI tables under aarch64 folder so that
> > RISC-V tables can be added under riscv64 folder in future.
> >
> > Signed-off-by: Sunil V L
> > Reviewed-by: Alistair Francis
> > ---
> > tests/data/acpi/virt/{ => aarch64}/APIC | Bin
>
> The usual pattern is {target}/{machine}, so instead of:
>
> microvm/
> pc/
> q35/
> virt/aarch64/
> virt/riscv64/
>
> (which is odd because q35 is the x86 'virt'), I'd rather see:
>
> x86/microvm/
> x86/pc/
> x86/q35/
> aarch64/virt/
> riscv64/virt/
>
> Anyhow just my 2 cents, up to the ACPI maintainers :)
>
Hi Phil,
Your suggestion does make sense to me. Let me wait for feedback from
ARM/ACPI maintainers.
Thanks,
Sunil
[PATCH v2 03/12] tests/data/uefi-boot-images: Add RISC-V ISO image
To test ACPI tables, edk2 needs to be booted with a disk image having
EFI partition. This image is created using UefiTestToolsPkg.
The image is generated using tests/uefi-test-tools source.
Signed-off-by: Sunil V L
---
.../bios-tables-test.riscv64.iso.qcow2 | Bin 0 -> 16896 bytes
tests/uefi-test-tools/uefi-test-build.config| 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
create mode 100644
tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2
diff --git a/tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2
b/tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2
new file mode 100644
index
..c720bf99a45fab6d1e21963cca563ee0ea059b82
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[PATCH v2 07/12] meson.build: Add RISC-V to the edk2-target list
so that ACPI table test can be supported.
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index a9de71d450..576c803a8a 100644
--- a/meson.build
+++ b/meson.build
@@ -93,7 +93,7 @@ else
iasl = find_program(get_option('iasl'), required: true)
endif
-edk2_targets = [ 'arm-softmmu', 'aarch64-softmmu', 'i386-softmmu',
'x86_64-softmmu' ]
+edk2_targets = [ 'arm-softmmu', 'aarch64-softmmu', 'i386-softmmu',
'x86_64-softmmu', 'riscv64-softmmu' ]
unpack_edk2_blobs = false
foreach target : edk2_targets
if target in target_dirs
--
2.40.1
[PATCH v2 10/12] tests/qtest/bios-tables-test: Add empty ACPI data files for RISC-V
As per process documented (steps 1-3) in bios-tables-test.c, add empty AML data files for RISC-V ACPI tables and add the entries in bios-tables-test-allowed-diff.h. Signed-off-by: Sunil V L --- tests/data/acpi/virt/riscv64/APIC | 0 tests/data/acpi/virt/riscv64/DSDT | 0 tests/data/acpi/virt/riscv64/FACP | 0 tests/data/acpi/virt/riscv64/MCFG | 0 tests/data/acpi/virt/riscv64/RHCT | 0 tests/data/acpi/virt/riscv64/SPCR | 0 tests/qtest/bios-tables-test-allowed-diff.h | 6 ++ 7 files changed, 6 insertions(+) create mode 100644 tests/data/acpi/virt/riscv64/APIC create mode 100644 tests/data/acpi/virt/riscv64/DSDT create mode 100644 tests/data/acpi/virt/riscv64/FACP create mode 100644 tests/data/acpi/virt/riscv64/MCFG create mode 100644 tests/data/acpi/virt/riscv64/RHCT create mode 100644 tests/data/acpi/virt/riscv64/SPCR diff --git a/tests/data/acpi/virt/riscv64/APIC b/tests/data/acpi/virt/riscv64/APIC new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/riscv64/DSDT b/tests/data/acpi/virt/riscv64/DSDT new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/riscv64/FACP b/tests/data/acpi/virt/riscv64/FACP new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/riscv64/MCFG b/tests/data/acpi/virt/riscv64/MCFG new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/riscv64/RHCT b/tests/data/acpi/virt/riscv64/RHCT new file mode 100644 index 00..e69de29bb2 diff --git a/tests/data/acpi/virt/riscv64/SPCR b/tests/data/acpi/virt/riscv64/SPCR new file mode 100644 index 00..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..d8610c8d72 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,7 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/riscv64/APIC", +"tests/data/acpi/virt/riscv64/DSDT", +"tests/data/acpi/virt/riscv64/FACP", +"tests/data/acpi/virt/riscv64/MCFG", +"tests/data/acpi/virt/riscv64/RHCT", +"tests/data/acpi/virt/riscv64/SPCR", -- 2.40.1
[PATCH v2 12/12] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
As per the step 5 in the process documented in bios-tables-test.c,
generate the expected ACPI AML data files for RISC-V using the
rebuild-expected-aml.sh script and update the
bios-tables-test-allowed-diff.h.
These are all new files being added for the first time. Hence, iASL diff
output is not added.
Signed-off-by: Sunil V L
---
tests/data/acpi/virt/riscv64/APIC | Bin 0 -> 116 bytes
tests/data/acpi/virt/riscv64/DSDT | Bin 0 -> 3518 bytes
tests/data/acpi/virt/riscv64/FACP | Bin 0 -> 276 bytes
tests/data/acpi/virt/riscv64/MCFG | Bin 0 -> 60 bytes
tests/data/acpi/virt/riscv64/RHCT | Bin 0 -> 314 bytes
tests/data/acpi/virt/riscv64/SPCR | Bin 0 -> 80 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 6 --
7 files changed, 6 deletions(-)
diff --git a/tests/data/acpi/virt/riscv64/APIC
b/tests/data/acpi/virt/riscv64/APIC
index
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..66a25dfd2d6ea2b607c024722b2eab95873a01e9
100644
GIT binary patch
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literal 0
HcmV?d1
diff --git a/tests/data/acpi/virt/riscv64/DSDT
b/tests/data/acpi/virt/riscv64/DSDT
index
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0fb2d5e0e389541209b765d5092d0706f40298f6
100644
GIT binary patch
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literal 0
HcmV?d1
diff --git a/tests/data/acpi/virt/riscv64/FACP
b/tests/data/acpi/virt/riscv64/FACP
index
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..a5276b65ea8ce46cc9b40d96d98f0669c9089ed4
100644
GIT binary patch
literal 276
zcmZ>BbPf<`lE(^DK1@Wog4=(iq&1K
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zK@GjINg;u`)Bd);9H
literal 0
HcmV?d1
diff --git a/tests/data/acpi/virt/riscv64/SPCR
b/tests/data/acpi/virt/riscv64/SPCR
index
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..4da9daf65f71a13ac2b488d4e9728f194b569a43
100644
GIT binary patch
literal 80
zcmWFza1IJ!U|?X{>E!S15v<@85#X!<1dKp25F12;fdT`FDF9*%FmM4$c8~z`e;@#f
G!2kgKJqrN<
literal 0
HcmV?d1
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index d8610c8d72..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,7 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/virt/riscv64/APIC",
-"tests/data/acpi/virt/riscv64/DSDT",
-"tests/data/acpi/virt/riscv64/FACP",
-"tests/data/acpi/virt/riscv64/MCFG",
-"tests/data/acpi/virt/riscv64/RHCT",
-"tests/data/acpi/virt/riscv64/SPCR",
--
2.40.1
[PATCH v2 04/12] qtest: bios-tables-test: Rename aarch64 tests with aarch64 in them
Existing AARCH64 virt test functions do not have AARCH64 in their name.
To add RISC-V virt related test cases, better to rename existing
functions to indicate they are ARM only.
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
---
tests/qtest/bios-tables-test.c | 35 ++
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index d1ff4db7a2..c4a4d1c7bf 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1570,7 +1570,7 @@ static void test_acpi_piix4_tcg_dimm_pxm(void)
test_acpi_tcg_dimm_pxm(MACHINE_PC);
}
-static void test_acpi_virt_tcg_memhp(void)
+static void test_acpi_aarch64_virt_tcg_memhp(void)
{
test_data data = {
.machine = "virt",
@@ -1663,7 +1663,7 @@ static void test_acpi_microvm_ioapic2_tcg(void)
free_test_data();
}
-static void test_acpi_virt_tcg_numamem(void)
+static void test_acpi_aarch64_virt_tcg_numamem(void)
{
test_data data = {
.machine = "virt",
@@ -1685,7 +1685,7 @@ static void test_acpi_virt_tcg_numamem(void)
}
-static void test_acpi_virt_tcg_pxb(void)
+static void test_acpi_aarch64_virt_tcg_pxb(void)
{
test_data data = {
.machine = "virt",
@@ -1758,7 +1758,7 @@ static void test_acpi_piix4_tcg_acpi_hmat(void)
test_acpi_tcg_acpi_hmat(MACHINE_PC);
}
-static void test_acpi_virt_tcg_acpi_hmat(void)
+static void test_acpi_aarch64_virt_tcg_acpi_hmat(void)
{
test_data data = {
.machine = "virt",
@@ -1914,7 +1914,7 @@ static void test_acpi_microvm_acpi_erst(void)
}
#endif /* CONFIG_POSIX */
-static void test_acpi_virt_tcg(void)
+static void test_acpi_aarch64_virt_tcg(void)
{
test_data data = {
.machine = "virt",
@@ -1933,7 +1933,7 @@ static void test_acpi_virt_tcg(void)
free_test_data();
}
-static void test_acpi_virt_tcg_topology(void)
+static void test_acpi_aarch64_virt_tcg_topology(void)
{
test_data data = {
.machine = "virt",
@@ -2016,7 +2016,7 @@ static void test_acpi_q35_cxl(void)
}
#endif /* CONFIG_POSIX */
-static void test_acpi_virt_viot(void)
+static void test_acpi_aarch64_virt_viot(void)
{
test_data data = {
.machine = "virt",
@@ -2192,7 +2192,7 @@ static void test_acpi_microvm_oem_fields(void)
g_free(args);
}
-static void test_acpi_virt_oem_fields(void)
+static void test_acpi_aarch64_virt_oem_fields(void)
{
test_data data = {
.machine = "virt",
@@ -2364,16 +2364,19 @@ int main(int argc, char *argv[])
}
} else if (strcmp(arch, "aarch64") == 0) {
if (has_tcg && qtest_has_device("virtio-blk-pci")) {
-qtest_add_func("acpi/virt", test_acpi_virt_tcg);
+qtest_add_func("acpi/virt", test_acpi_aarch64_virt_tcg);
qtest_add_func("acpi/virt/acpihmatvirt",
-test_acpi_virt_tcg_acpi_hmat);
-qtest_add_func("acpi/virt/topology", test_acpi_virt_tcg_topology);
-qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem);
-qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
-qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
-qtest_add_func("acpi/virt/oem-fields", test_acpi_virt_oem_fields);
+ test_acpi_aarch64_virt_tcg_acpi_hmat);
+qtest_add_func("acpi/virt/topology",
+ test_acpi_aarch64_virt_tcg_topology);
+qtest_add_func("acpi/virt/numamem",
+ test_acpi_aarch64_virt_tcg_numamem);
+qtest_add_func("acpi/virt/memhp",
test_acpi_aarch64_virt_tcg_memhp);
+qtest_add_func("acpi/virt/pxb", test_acpi_aarch64_virt_tcg_pxb);
+qtest_add_func("acpi/virt/oem-fields",
+ test_acpi_aarch64_virt_oem_fields);
if (qtest_has_device("virtio-iommu-pci")) {
-qtest_add_func("acpi/virt/viot", test_acpi_virt_viot);
+qtest_add_func("acpi/virt/viot", test_acpi_aarch64_virt_viot);
}
}
}
--
2.40.1
[PATCH v2 09/12] tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V
Update the list of supported architectures to include RISC-V. Signed-off-by: Sunil V L Reviewed-by: Alistair Francis --- tests/data/acpi/rebuild-expected-aml.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/data/acpi/rebuild-expected-aml.sh b/tests/data/acpi/rebuild-expected-aml.sh index dcf2e2f221..c1092fb8ba 100755 --- a/tests/data/acpi/rebuild-expected-aml.sh +++ b/tests/data/acpi/rebuild-expected-aml.sh @@ -12,7 +12,7 @@ # This work is licensed under the terms of the GNU GPLv2. # See the COPYING.LIB file in the top-level directory. -qemu_arches="x86_64 aarch64" +qemu_arches="x86_64 aarch64 riscv64" if [ ! -e "tests/qtest/bios-tables-test" ]; then echo "Test: bios-tables-test is required! Run make check before this script." @@ -36,7 +36,8 @@ fi if [ -z "$qemu_bins" ]; then echo "Only the following architectures are currently supported: $qemu_arches" echo "None of these configured!" -echo "To fix, run configure --target-list=x86_64-softmmu,aarch64-softmmu" +echo "To fix, run configure \ + --target-list=x86_64-softmmu,aarch64-softmmu,riscv64-softmmu" exit 1; fi -- 2.40.1
[PATCH v2 08/12] pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs
Update list of images supported in unpack_edk2_blobs to enable RISC-V
ACPI table testing.
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
---
pc-bios/meson.build | 2 ++
tests/qtest/meson.build | 3 +++
2 files changed, 5 insertions(+)
diff --git a/pc-bios/meson.build b/pc-bios/meson.build
index 0760612bea..8602b45b9b 100644
--- a/pc-bios/meson.build
+++ b/pc-bios/meson.build
@@ -4,6 +4,8 @@ if unpack_edk2_blobs
'edk2-aarch64-code.fd',
'edk2-arm-code.fd',
'edk2-arm-vars.fd',
+'edk2-riscv-code.fd',
+'edk2-riscv-vars.fd',
'edk2-i386-code.fd',
'edk2-i386-secure-code.fd',
'edk2-i386-vars.fd',
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 86293051dc..2f60f6aed8 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -259,6 +259,9 @@ qtests_s390x = \
qtests_riscv32 = \
(config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ?
['sifive-e-aon-watchdog-test'] : [])
+qtests_riscv64 = \
+ (unpack_edk2_blobs ? ['bios-tables-test'] : [])
+
qos_test_ss = ss.source_set()
qos_test_ss.add(
'ac97-test.c',
--
2.40.1
[PATCH v2 11/12] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
Add basic ACPI table test case for RISC-V.
Signed-off-by: Sunil V L
---
tests/qtest/bios-tables-test.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index c73174ad00..880435a5fa 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1935,6 +1935,29 @@ static void test_acpi_microvm_acpi_erst(void)
}
#endif /* CONFIG_POSIX */
+static void test_acpi_riscv64_virt_tcg(void)
+{
+test_data data = {
+.machine = "virt",
+.arch = "riscv64",
+.tcg_only = true,
+.uefi_fl1 = "pc-bios/edk2-riscv-code.fd",
+.uefi_fl2 = "pc-bios/edk2-riscv-vars.fd",
+.ram_start = 0x8000ULL,
+.scan_len = 128ULL * 1024 * 1024,
+};
+
+/*
+ * RHCT will have ISA string encoded. To reduce the effort
+ * of updating expected AML file for any new default ISA extension,
+ * use the profile rva22s64.
+ */
+test_acpi_one("-cpu rva22s64 -device virtio-blk-device,drive=hd0 "
+ "-drive
file=tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2,id=hd0",
+ );
+free_test_data();
+}
+
static void test_acpi_aarch64_virt_tcg(void)
{
test_data data = {
@@ -2404,6 +2427,10 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/virt/viot", test_acpi_aarch64_virt_viot);
}
}
+} else if (strcmp(arch, "riscv64") == 0) {
+if (has_tcg && qtest_has_device("virtio-blk-pci")) {
+qtest_add_func("acpi/virt", test_acpi_riscv64_virt_tcg);
+}
}
ret = g_test_run();
boot_sector_cleanup(disk);
--
2.40.1
[PATCH v2 06/12] tests/data/acpi/virt: Move ACPI tables under aarch64
Since virt is a common machine name across architectures like ARM64 and
RISC-V, move existing ARM64 ACPI tables under aarch64 folder so that
RISC-V tables can be added under riscv64 folder in future.
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
---
tests/data/acpi/virt/{ => aarch64}/APIC | Bin
.../data/acpi/virt/{ => aarch64}/APIC.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/APIC.topology| Bin
tests/data/acpi/virt/{ => aarch64}/DBG2 | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT | Bin
.../data/acpi/virt/{ => aarch64}/DSDT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT.pxb | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT.topology| Bin
tests/data/acpi/virt/{ => aarch64}/FACP | Bin
tests/data/acpi/virt/{ => aarch64}/GTDT | Bin
.../data/acpi/virt/{ => aarch64}/HMAT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/IORT | Bin
tests/data/acpi/virt/{ => aarch64}/MCFG | Bin
tests/data/acpi/virt/{ => aarch64}/NFIT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/PPTT | Bin
.../data/acpi/virt/{ => aarch64}/PPTT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/PPTT.topology| Bin
tests/data/acpi/virt/{ => aarch64}/SLIT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/SPCR | Bin
.../data/acpi/virt/{ => aarch64}/SRAT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/SRAT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/SRAT.numamem | Bin
tests/data/acpi/virt/{ => aarch64}/SSDT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/VIOT | Bin
25 files changed, 0 insertions(+), 0 deletions(-)
rename tests/data/acpi/virt/{ => aarch64}/APIC (100%)
rename tests/data/acpi/virt/{ => aarch64}/APIC.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/APIC.topology (100%)
rename tests/data/acpi/virt/{ => aarch64}/DBG2 (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.memhp (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.pxb (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.topology (100%)
rename tests/data/acpi/virt/{ => aarch64}/FACP (100%)
rename tests/data/acpi/virt/{ => aarch64}/GTDT (100%)
rename tests/data/acpi/virt/{ => aarch64}/HMAT.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/IORT (100%)
rename tests/data/acpi/virt/{ => aarch64}/MCFG (100%)
rename tests/data/acpi/virt/{ => aarch64}/NFIT.memhp (100%)
rename tests/data/acpi/virt/{ => aarch64}/PPTT (100%)
rename tests/data/acpi/virt/{ => aarch64}/PPTT.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/PPTT.topology (100%)
rename tests/data/acpi/virt/{ => aarch64}/SLIT.memhp (100%)
rename tests/data/acpi/virt/{ => aarch64}/SPCR (100%)
rename tests/data/acpi/virt/{ => aarch64}/SRAT.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/SRAT.memhp (100%)
rename tests/data/acpi/virt/{ => aarch64}/SRAT.numamem (100%)
rename tests/data/acpi/virt/{ => aarch64}/SSDT.memhp (100%)
rename tests/data/acpi/virt/{ => aarch64}/VIOT (100%)
diff --git a/tests/data/acpi/virt/APIC b/tests/data/acpi/virt/aarch64/APIC
similarity index 100%
rename from tests/data/acpi/virt/APIC
rename to tests/data/acpi/virt/aarch64/APIC
diff --git a/tests/data/acpi/virt/APIC.acpihmatvirt
b/tests/data/acpi/virt/aarch64/APIC.acpihmatvirt
similarity index 100%
rename from tests/data/acpi/virt/APIC.acpihmatvirt
rename to tests/data/acpi/virt/aarch64/APIC.acpihmatvirt
diff --git a/tests/data/acpi/virt/APIC.topology
b/tests/data/acpi/virt/aarch64/APIC.topology
similarity index 100%
rename from tests/data/acpi/virt/APIC.topology
rename to tests/data/acpi/virt/aarch64/APIC.topology
diff --git a/tests/data/acpi/virt/DBG2 b/tests/data/acpi/virt/aarch64/DBG2
similarity index 100%
rename from tests/data/acpi/virt/DBG2
rename to tests/data/acpi/virt/aarch64/DBG2
diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/aarch64/DSDT
similarity index 100%
rename from tests/data/acpi/virt/DSDT
rename to tests/data/acpi/virt/aarch64/DSDT
diff --git a/tests/data/acpi/virt/DSDT.acpihmatvirt
b/tests/data/acpi/virt/aarch64/DSDT.acpihmatvirt
similarity index 100%
rename from tests/data/acpi/virt/DSDT.acpihmatvirt
rename to tests/data/acpi/virt/aarch64/DSDT.acpihmatvirt
diff --git a/tests/data/acpi/virt/DSDT.memhp
b/tests/data/acpi/virt/aarch64/DSDT.memhp
similarity index 100%
rename from tests/data/acpi/virt/DSDT.memhp
rename to tests/data/acpi/virt/aarch64/DSDT.memhp
diff --git a/tests/data/acpi/virt/DSDT.pxb
b/tests/data/acpi/virt/aarch64/DSDT.pxb
similarity index 100%
rename from tests/d
[PATCH v2 01/12] uefi-test-tools/UefiTestToolsPkg: Add RISC-V support
Enable building the test application for RISC-V with appropriate dependencies updated. Signed-off-by: Sunil V L Acked-by: Gerd Hoffmann --- tests/uefi-test-tools/UefiTestToolsPkg/UefiTestToolsPkg.dsc | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tests/uefi-test-tools/UefiTestToolsPkg/UefiTestToolsPkg.dsc b/tests/uefi-test-tools/UefiTestToolsPkg/UefiTestToolsPkg.dsc index c8511cd732..0902fd3c73 100644 --- a/tests/uefi-test-tools/UefiTestToolsPkg/UefiTestToolsPkg.dsc +++ b/tests/uefi-test-tools/UefiTestToolsPkg/UefiTestToolsPkg.dsc @@ -19,7 +19,7 @@ PLATFORM_VERSION= 0.1 PLATFORM_NAME = UefiTestTools SKUID_IDENTIFIER= DEFAULT - SUPPORTED_ARCHITECTURES = ARM|AARCH64|IA32|X64 + SUPPORTED_ARCHITECTURES = ARM|AARCH64|IA32|X64|RISCV64 BUILD_TARGETS = DEBUG [BuildOptions.IA32] @@ -60,6 +60,10 @@ [LibraryClasses.IA32, LibraryClasses.X64] BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf + RegisterFilterLib|MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.inf + +[LibraryClasses.RISCV64] + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf [PcdsFixedAtBuild] gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8040004F -- 2.40.1
[PATCH v2 02/12] uefi-test-tools: Add support for python based build script
edk2-funcs.sh which is used in this Makefile, was removed in the commit
c28a2891f3 ("edk2: update build script"). It is replaced with a python
based script. So, update the Makefile and add the configuration file as
required to support the python based build script.
Signed-off-by: Sunil V L
---
tests/uefi-test-tools/Makefile | 19 +++
tests/uefi-test-tools/uefi-test-build.config | 52
2 files changed, 59 insertions(+), 12 deletions(-)
create mode 100644 tests/uefi-test-tools/uefi-test-build.config
diff --git a/tests/uefi-test-tools/Makefile b/tests/uefi-test-tools/Makefile
index 0c003f2877..f4eaebd8ff 100644
--- a/tests/uefi-test-tools/Makefile
+++ b/tests/uefi-test-tools/Makefile
@@ -12,7 +12,7 @@
edk2_dir := ../../roms/edk2
images_dir:= ../data/uefi-boot-images
-emulation_targets := arm aarch64 i386 x86_64
+emulation_targets := arm aarch64 i386 x86_64 riscv64
uefi_binaries := bios-tables-test
intermediate_suffixes := .efi .fat .iso.raw
@@ -56,7 +56,8 @@ Build/%.iso.raw: Build/%.fat
# stripped from, the argument.
map_arm_to_uefi = $(subst arm,ARM,$(1))
map_aarch64_to_uefi = $(subst aarch64,AA64,$(call map_arm_to_uefi,$(1)))
-map_i386_to_uefi= $(subst i386,IA32,$(call map_aarch64_to_uefi,$(1)))
+map_riscv64_to_uefi = $(subst riscv64,RISCV64,$(call map_aarch64_to_uefi,$(1)))
+map_i386_to_uefi= $(subst i386,IA32,$(call map_riscv64_to_uefi,$(1)))
map_x86_64_to_uefi = $(subst x86_64,X64,$(call map_i386_to_uefi,$(1)))
map_to_uefi = $(subst .,,$(call map_x86_64_to_uefi,$(1)))
@@ -70,7 +71,7 @@ Build/%.fat: Build/%.efi
uefi_bin_b=$$(stat --format=%s -- $<) && \
uefi_fat_kb=$$(( (uefi_bin_b * 11 / 10 + 1023) / 1024 )) && \
uefi_fat_kb=$$(( uefi_fat_kb >= 64 ? uefi_fat_kb : 64 )) && \
- mkdosfs -C $@ -n $(basename $(@F)) -- $$uefi_fat_kb
+ mkdosfs -C $@ -n "bios-test" -- $$uefi_fat_kb
MTOOLS_SKIP_CHECK=1 mmd -i $@ ::EFI
MTOOLS_SKIP_CHECK=1 mmd -i $@ ::EFI/BOOT
MTOOLS_SKIP_CHECK=1 mcopy -i $@ -- $< \
@@ -95,15 +96,9 @@ Build/%.fat: Build/%.efi
# we must mark the recipe manually as recursive, by using the "+" indicator.
# This way, when the inner "make" starts a parallel build of the target edk2
# module, it can communicate with the outer "make"'s job server.
-Build/bios-tables-test.%.efi: build-edk2-tools
- +./build.sh $(edk2_dir) BiosTablesTest $* $@
-
-build-edk2-tools:
- cd $(edk2_dir)/BaseTools && git submodule update --init --force
- $(MAKE) -C $(edk2_dir)/BaseTools \
- PYTHON_COMMAND=$${EDK2_PYTHON_COMMAND:-python3} \
- EXTRA_OPTFLAGS='$(EDK2_BASETOOLS_OPTFLAGS)' \
- EXTRA_LDFLAGS='$(EDK2_BASETOOLS_LDFLAGS)'
+Build/bios-tables-test.%.efi:
+ $(PYTHON) ../../roms/edk2-build.py --config uefi-test-build.config \
+ --match $*
clean:
rm -rf Build Conf log
diff --git a/tests/uefi-test-tools/uefi-test-build.config
b/tests/uefi-test-tools/uefi-test-build.config
new file mode 100644
index 00..1f389ae541
--- /dev/null
+++ b/tests/uefi-test-tools/uefi-test-build.config
@@ -0,0 +1,52 @@
+[global]
+core = ../../roms/edk2
+
+
+# arm
+
+[build.arm]
+conf = UefiTestToolsPkg/UefiTestToolsPkg.dsc
+plat = UefiTestTools
+dest = ./Build
+arch = ARM
+cpy1 = ARM/BiosTablesTest.efi bios-tables-test.arm.efi
+
+
+# aarch64
+
+[build.aarch64]
+conf = UefiTestToolsPkg/UefiTestToolsPkg.dsc
+plat = UefiTestTools
+dest = ./Build
+arch = AARCH64
+cpy1 = AARCH64/BiosTablesTest.efi bios-tables-test.aarch64.efi
+
+
+# riscv64
+
+[build.riscv]
+conf = UefiTestToolsPkg/UefiTestToolsPkg.dsc
+plat = UefiTestTools
+dest = ./Build
+arch = RISCV64
+cpy1 = RISCV64/BiosTablesTest.efi bios-tables-test.riscv64.efi
+
+
+# ia32
+
+[build.ia32]
+conf = UefiTestToolsPkg/UefiTestToolsPkg.dsc
+plat = UefiTestTools
+dest = ./Build
+arch = IA32
+cpy1 = IA32/BiosTablesTest.efi bios-tables-test.i386.efi
+
+
+# x64
+
+[build.x64]
+conf = UefiTestToolsPkg/UefiTestToolsPkg.dsc
+plat = UefiTestTools
+dest = ./Build
+arch = X64
+cpy1 = X64/BiosTablesTest.efi bios-tables-test.x86_64.efi
--
2.40.1
[PATCH v2 05/12] tests/qtest/bios-tables-test.c: Add support for arch in path
Since virt machine is common for multiple architectures, add "arch" in
the path to search expected AML files. Since the AML files are still
under old path, support both by searching with and without arch in the
path.
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
---
tests/qtest/bios-tables-test.c | 31 ---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index c4a4d1c7bf..c73174ad00 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -78,6 +78,7 @@
typedef struct {
bool tcg_only;
const char *machine;
+const char *arch;
const char *machine_param;
const char *variant;
const char *uefi_fl1;
@@ -262,8 +263,19 @@ static void dump_aml_files(test_data *data, bool rebuild)
g_assert(exp_sdt->aml);
if (rebuild) {
-aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
+aml_file = g_strdup_printf("%s/%s/%s/%.4s%s", data_dir,
+ data->machine, data->arch,
sdt->aml, ext);
+
+/*
+ * To keep test cases not failing when the DATA files are moved to
+ * ARCH under virt folder, add this check as well.
+ */
+if (!g_file_test(aml_file, G_FILE_TEST_EXISTS)) {
+aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir,
+ data->machine, sdt->aml, ext);
+}
+
if (!g_file_test(aml_file, G_FILE_TEST_EXISTS) &&
sdt->aml_len == exp_sdt->aml_len &&
!memcmp(sdt->aml, exp_sdt->aml, sdt->aml_len)) {
@@ -398,8 +410,13 @@ static GArray *load_expected_aml(test_data *data)
memset(_sdt, 0, sizeof(exp_sdt));
try_again:
-aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
- sdt->aml, ext);
+aml_file = g_strdup_printf("%s/%s/%s/%.4s%s", data_dir, data->machine,
+ data->arch, sdt->aml, ext);
+if (!g_file_test(aml_file, G_FILE_TEST_EXISTS)) {
+aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
+ sdt->aml, ext);
+}
+
if (verbosity_level >= 2) {
fprintf(stderr, "Looking for expected file '%s'\n", aml_file);
}
@@ -1574,6 +1591,7 @@ static void test_acpi_aarch64_virt_tcg_memhp(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
@@ -1667,6 +1685,7 @@ static void test_acpi_aarch64_virt_tcg_numamem(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
@@ -1689,6 +1708,7 @@ static void test_acpi_aarch64_virt_tcg_pxb(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
@@ -1762,6 +1782,7 @@ static void test_acpi_aarch64_virt_tcg_acpi_hmat(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
@@ -1918,6 +1939,7 @@ static void test_acpi_aarch64_virt_tcg(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
@@ -1937,6 +1959,7 @@ static void test_acpi_aarch64_virt_tcg_topology(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.variant = ".topology",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
@@ -2020,6 +2043,7 @@ static void test_acpi_aarch64_virt_viot(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
@@ -2196,6 +2220,7 @@ static void test_acpi_aarch64_virt_oem_fields(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
--
2.40.1
[PATCH v2 00/12] Add support for RISC-V ACPI tests
Currently, bios-table-test doesn't support RISC-V. This series enables
the framework changes required and basic testing. Things like NUMA
related test cases will be added later.
This needs refactoring/renaming of ARM64 bios table tests. Importantly,
the test cases now look for the expected AML files under
tests/data/acpi/virt/aarch64 path instead of directly under
tests/data/acpi/virt. To keep test cases not to fail because of this
movement, they are updated to look for both paths first.
As part of this effort, it is found that uefi-test-tools is currently
broken to build. So, updated its Makefile as well to use python based
edk2 build script.
The changes are also available at branch
https://gitlab.com/vlsunil/qemu/-/tree/riscv_bios_table_test_v2
Changes since v1:
1) Addressed feedback from Gerd and Alistair
2) Rebased and added tags received
Sunil V L (12):
uefi-test-tools/UefiTestToolsPkg: Add RISC-V support
uefi-test-tools: Add support for python based build script
tests/data/uefi-boot-images: Add RISC-V ISO image
qtest: bios-tables-test: Rename aarch64 tests with aarch64 in them
tests/qtest/bios-tables-test.c: Add support for arch in path
tests/data/acpi/virt: Move ACPI tables under aarch64
meson.build: Add RISC-V to the edk2-target list
pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs
tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V
tests/qtest/bios-tables-test: Add empty ACPI data files for RISC-V
tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V
meson.build | 2 +-
pc-bios/meson.build | 2 +
tests/data/acpi/rebuild-expected-aml.sh | 5 +-
tests/data/acpi/virt/{ => aarch64}/APIC | Bin
.../acpi/virt/{ => aarch64}/APIC.acpihmatvirt | Bin
.../acpi/virt/{ => aarch64}/APIC.topology | Bin
tests/data/acpi/virt/{ => aarch64}/DBG2 | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT | Bin
.../acpi/virt/{ => aarch64}/DSDT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT.pxb | Bin
.../acpi/virt/{ => aarch64}/DSDT.topology | Bin
tests/data/acpi/virt/{ => aarch64}/FACP | Bin
tests/data/acpi/virt/{ => aarch64}/GTDT | Bin
.../acpi/virt/{ => aarch64}/HMAT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/IORT | Bin
tests/data/acpi/virt/{ => aarch64}/MCFG | Bin
tests/data/acpi/virt/{ => aarch64}/NFIT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/PPTT | Bin
.../acpi/virt/{ => aarch64}/PPTT.acpihmatvirt | Bin
.../acpi/virt/{ => aarch64}/PPTT.topology | Bin
tests/data/acpi/virt/{ => aarch64}/SLIT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/SPCR | Bin
.../acpi/virt/{ => aarch64}/SRAT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/SRAT.memhp | Bin
.../data/acpi/virt/{ => aarch64}/SRAT.numamem | Bin
tests/data/acpi/virt/{ => aarch64}/SSDT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/VIOT | Bin
tests/data/acpi/virt/riscv64/APIC | Bin 0 -> 116 bytes
tests/data/acpi/virt/riscv64/DSDT | Bin 0 -> 3518 bytes
tests/data/acpi/virt/riscv64/FACP | Bin 0 -> 276 bytes
tests/data/acpi/virt/riscv64/MCFG | Bin 0 -> 60 bytes
tests/data/acpi/virt/riscv64/RHCT | Bin 0 -> 314 bytes
tests/data/acpi/virt/riscv64/SPCR | Bin 0 -> 80 bytes
.../bios-tables-test.riscv64.iso.qcow2| Bin 0 -> 16896 bytes
tests/qtest/bios-tables-test.c| 93 ++
tests/qtest/meson.build | 3 +
tests/uefi-test-tools/Makefile| 19 ++--
.../UefiTestToolsPkg/UefiTestToolsPkg.dsc | 6 +-
tests/uefi-test-tools/uefi-test-build.config | 52 ++
40 files changed, 147 insertions(+), 35 deletions(-)
rename tests/data/acpi/virt/{ => aarch64}/APIC (100%)
rename tests/data/acpi/virt/{ => aarch64}/APIC.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/APIC.topology (100%)
rename tests/data/acpi/virt/{ => aarch64}/DBG2 (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.memhp (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.pxb (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.topology (100%)
rename tests/data/acpi/virt/{ => aarch64}/FACP (100%)
rename tests/data/acpi/virt/{ => aarch64}/GTDT (100%)
rename tests/data/acpi/virt/{ => aarch64}/HMAT.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/IORT (100%)
rename tests/data/acpi/virt/{ => aarch64}/MCFG (100%)
rename tests/data/acpi/virt/{ => aarch64}/NFIT.memhp (100%)
rena
Re: [PATCH v2 2/3] hw/acpi: Upgrade ACPI SPCR table to support SPCR table version 4 format
Hi Sia Jee Heng,
On Mon, May 06, 2024 at 10:22:11PM -0700, Sia Jee Heng wrote:
> Update the SPCR table to accommodate the SPCR Table version 4 [1].
> The SPCR table has been modified to adhere to the version 4 format [2].
>
> [1]:
> https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
> [2]: https://github.com/acpica/acpica/pull/931
>
> Signed-off-by: Sia Jee Heng
> ---
> hw/acpi/aml-build.c | 14 +++---
> hw/arm/virt-acpi-build.c| 10 --
> hw/riscv/virt-acpi-build.c | 12 +---
> include/hw/acpi/acpi-defs.h | 7 +--
> include/hw/acpi/aml-build.h | 2 +-
> 5 files changed, 34 insertions(+), 11 deletions(-)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 6d4517cfbe..7c43573eef 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -1996,7 +1996,7 @@ static void build_processor_hierarchy_node(GArray *tbl,
> uint32_t flags,
>
> void build_spcr(GArray *table_data, BIOSLinker *linker,
> const AcpiSpcrData *f, const uint8_t rev,
> -const char *oem_id, const char *oem_table_id)
> +const char *oem_id, const char *oem_table_id, const char
> *name)
> {
> AcpiTable table = { .sig = "SPCR", .rev = rev, .oem_id = oem_id,
> .oem_table_id = oem_table_id };
> @@ -2042,8 +2042,16 @@ void build_spcr(GArray *table_data, BIOSLinker *linker,
> build_append_int_noprefix(table_data, f->pci_flags, 4);
> /* PCI Segment */
> build_append_int_noprefix(table_data, f->pci_segment, 1);
> -/* Reserved */
> -build_append_int_noprefix(table_data, 0, 4);
> +/* UartClkFreq */
> +build_append_int_noprefix(table_data, f->uart_clk_freq, 4);
> +/* PreciseBaudrate */
> +build_append_int_noprefix(table_data, f->precise_baudrate, 4);
> +/* NameSpaceStringLength */
> +build_append_int_noprefix(table_data, f->namespace_string_length, 2);
> +/* NameSpaceStringOffset */
> +build_append_int_noprefix(table_data, f->namespace_string_offset, 2);
> +/* NamespaceString[] */
> +g_array_append_vals(table_data, name, f->namespace_string_length);
>
Is it possible to check the revision here and add new fields only if the
revision supports it? ARM maintainers are better to comment but IMO, we
better keep ARM's SPCR in the same current version since I don't know
how consumers like linux (and other OSs) react to the change.
Thanks!
Sunil
> acpi_table_end(linker, );
> }
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 6a1bde61ce..cb345e8659 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -428,11 +428,12 @@ build_iort(GArray *table_data, BIOSLinker *linker,
> VirtMachineState *vms)
>
> /*
> * Serial Port Console Redirection Table (SPCR)
> - * Rev: 1.07
> + * Rev: 1.10
> */
> static void
> spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
> {
> +const char name[] = ".";
> AcpiSpcrData serial = {
> .interface_type = 3, /* ARM PL011 UART */
> .base_addr.id = AML_AS_SYSTEM_MEMORY,
> @@ -456,9 +457,14 @@ spcr_setup(GArray *table_data, BIOSLinker *linker,
> VirtMachineState *vms)
> .pci_function = 0,
> .pci_flags = 0,
> .pci_segment = 0,
> +.uart_clk_freq = 0,
> +.precise_baudrate = 0,
> +.namespace_string_length = sizeof(name),
> +.namespace_string_offset = 88,
> };
>
> -build_spcr(table_data, linker, , 2, vms->oem_id,
> vms->oem_table_id);
> +build_spcr(table_data, linker, , 4, vms->oem_id,
> vms->oem_table_id,
> + name);
> }
>
> /*
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 0925528160..5fa3942491 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -176,14 +176,15 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry
> *uart_memmap,
>
> /*
> * Serial Port Console Redirection Table (SPCR)
> - * Rev: 1.07
> + * Rev: 1.10
> */
>
> static void
> spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
> {
> +const char name[] = ".";
> AcpiSpcrData serial = {
> -.interface_type = 0, /* 16550 compatible */
> +.interface_type = 0x12, /* 16550 compatible */
> .base_addr.id = AML_AS_SYSTEM_MEMORY,
> .base_addr.width = 32,
> .base_addr.offset = 0,
> @@ -205,9 +206,14 @@ spcr_setup(GArray *table_data, BIOSLinker *linker,
> RISCVVirtState *s)
> .pci_function = 0,
> .pci_flags = 0,
> .pci_segment = 0,
> +.uart_clk_freq = 0,
> +.precise_baudrate = 0,
> +.namespace_string_length = sizeof(name),
> +.namespace_string_offset = 88,
> };
>
> -build_spcr(table_data, linker, , 2, s->oem_id, s->oem_table_id);
> +build_spcr(table_data, linker, , 4, s->oem_id,
Re: [PATCH 03/12] uefi-test-tools: Add support for python based build script
On Fri, Mar 15, 2024 at 03:17:19PM +0100, Gerd Hoffmann wrote: > > +Build/bios-tables-test.%.efi: > > + $(PYTHON) ../../roms/edk2-build.py --config uefi-test-build.config > > Adding '--match $*' will build one arch instead of all. > Thanks Gerd. Good suggestion. Let me update in next revision. Thanks, Sunil
Re: [PATCH 01/12] roms/edk2-build.py: Add --module support
On Fri, Mar 15, 2024 at 03:13:44PM +0100, Gerd Hoffmann wrote: > On Fri, Mar 15, 2024 at 06:35:08PM +0530, Sunil V L wrote: > > UefiTestToolsPkg which should use edk2-build.py needs --module parameter > > support. Add this optional parameter handling. > > I don't think this is needed. By default everything listed in > [Components] should be built, which is just that one module we > have ;) > Ahh yes. Makes sense. Let me remove this in next revision of the series. Thanks! Sunil
[PATCH 07/12] tests/data/acpi/virt: Move ACPI tables under aarch64
Since virt is a common machine name across architectures like ARM64 and
RISC-V, move existing ARM64 ACPI tables under aarch64 folder so that
RISC-V tables can be added under riscv64 folder in future.
Signed-off-by: Sunil V L
---
tests/data/acpi/virt/{ => aarch64}/APIC | Bin
.../data/acpi/virt/{ => aarch64}/APIC.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/APIC.topology| Bin
tests/data/acpi/virt/{ => aarch64}/DBG2 | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT | Bin
.../data/acpi/virt/{ => aarch64}/DSDT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT.pxb | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT.topology| Bin
tests/data/acpi/virt/{ => aarch64}/FACP | Bin
tests/data/acpi/virt/{ => aarch64}/GTDT | Bin
.../data/acpi/virt/{ => aarch64}/HMAT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/IORT | Bin
tests/data/acpi/virt/{ => aarch64}/MCFG | Bin
tests/data/acpi/virt/{ => aarch64}/NFIT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/PPTT | Bin
.../data/acpi/virt/{ => aarch64}/PPTT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/PPTT.topology| Bin
tests/data/acpi/virt/{ => aarch64}/SLIT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/SPCR | Bin
.../data/acpi/virt/{ => aarch64}/SRAT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/SRAT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/SRAT.numamem | Bin
tests/data/acpi/virt/{ => aarch64}/SSDT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/VIOT | Bin
25 files changed, 0 insertions(+), 0 deletions(-)
rename tests/data/acpi/virt/{ => aarch64}/APIC (100%)
rename tests/data/acpi/virt/{ => aarch64}/APIC.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/APIC.topology (100%)
rename tests/data/acpi/virt/{ => aarch64}/DBG2 (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.memhp (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.pxb (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.topology (100%)
rename tests/data/acpi/virt/{ => aarch64}/FACP (100%)
rename tests/data/acpi/virt/{ => aarch64}/GTDT (100%)
rename tests/data/acpi/virt/{ => aarch64}/HMAT.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/IORT (100%)
rename tests/data/acpi/virt/{ => aarch64}/MCFG (100%)
rename tests/data/acpi/virt/{ => aarch64}/NFIT.memhp (100%)
rename tests/data/acpi/virt/{ => aarch64}/PPTT (100%)
rename tests/data/acpi/virt/{ => aarch64}/PPTT.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/PPTT.topology (100%)
rename tests/data/acpi/virt/{ => aarch64}/SLIT.memhp (100%)
rename tests/data/acpi/virt/{ => aarch64}/SPCR (100%)
rename tests/data/acpi/virt/{ => aarch64}/SRAT.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/SRAT.memhp (100%)
rename tests/data/acpi/virt/{ => aarch64}/SRAT.numamem (100%)
rename tests/data/acpi/virt/{ => aarch64}/SSDT.memhp (100%)
rename tests/data/acpi/virt/{ => aarch64}/VIOT (100%)
diff --git a/tests/data/acpi/virt/APIC b/tests/data/acpi/virt/aarch64/APIC
similarity index 100%
rename from tests/data/acpi/virt/APIC
rename to tests/data/acpi/virt/aarch64/APIC
diff --git a/tests/data/acpi/virt/APIC.acpihmatvirt
b/tests/data/acpi/virt/aarch64/APIC.acpihmatvirt
similarity index 100%
rename from tests/data/acpi/virt/APIC.acpihmatvirt
rename to tests/data/acpi/virt/aarch64/APIC.acpihmatvirt
diff --git a/tests/data/acpi/virt/APIC.topology
b/tests/data/acpi/virt/aarch64/APIC.topology
similarity index 100%
rename from tests/data/acpi/virt/APIC.topology
rename to tests/data/acpi/virt/aarch64/APIC.topology
diff --git a/tests/data/acpi/virt/DBG2 b/tests/data/acpi/virt/aarch64/DBG2
similarity index 100%
rename from tests/data/acpi/virt/DBG2
rename to tests/data/acpi/virt/aarch64/DBG2
diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/aarch64/DSDT
similarity index 100%
rename from tests/data/acpi/virt/DSDT
rename to tests/data/acpi/virt/aarch64/DSDT
diff --git a/tests/data/acpi/virt/DSDT.acpihmatvirt
b/tests/data/acpi/virt/aarch64/DSDT.acpihmatvirt
similarity index 100%
rename from tests/data/acpi/virt/DSDT.acpihmatvirt
rename to tests/data/acpi/virt/aarch64/DSDT.acpihmatvirt
diff --git a/tests/data/acpi/virt/DSDT.memhp
b/tests/data/acpi/virt/aarch64/DSDT.memhp
similarity index 100%
rename from tests/data/acpi/virt/DSDT.memhp
rename to tests/data/acpi/virt/aarch64/DSDT.memhp
diff --git a/tests/data/acpi/virt/DSDT.pxb
b/tests/data/acpi/virt/aarch64/DSDT.pxb
similarity index 100%
rename from tests/data/acpi/virt/DSDT.pxb
rename to te
[PATCH 05/12] qtest: bios-tables-test: Rename aarch64 tests with aarch64 in them
Existing AARCH64 virt test functions do not have AARCH64 in their name.
To add RISC-V virt related test cases, better to rename existing
functions to indicate they are ARM only.
Signed-off-by: Sunil V L
---
tests/qtest/bios-tables-test.c | 35 ++
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 21811a1ab5..ea3ba1992b 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1557,7 +1557,7 @@ static void test_acpi_piix4_tcg_dimm_pxm(void)
test_acpi_tcg_dimm_pxm(MACHINE_PC);
}
-static void test_acpi_virt_tcg_memhp(void)
+static void test_acpi_aarch64_virt_tcg_memhp(void)
{
test_data data = {
.machine = "virt",
@@ -1650,7 +1650,7 @@ static void test_acpi_microvm_ioapic2_tcg(void)
free_test_data();
}
-static void test_acpi_virt_tcg_numamem(void)
+static void test_acpi_aarch64_virt_tcg_numamem(void)
{
test_data data = {
.machine = "virt",
@@ -1672,7 +1672,7 @@ static void test_acpi_virt_tcg_numamem(void)
}
-static void test_acpi_virt_tcg_pxb(void)
+static void test_acpi_aarch64_virt_tcg_pxb(void)
{
test_data data = {
.machine = "virt",
@@ -1745,7 +1745,7 @@ static void test_acpi_piix4_tcg_acpi_hmat(void)
test_acpi_tcg_acpi_hmat(MACHINE_PC);
}
-static void test_acpi_virt_tcg_acpi_hmat(void)
+static void test_acpi_aarch64_virt_tcg_acpi_hmat(void)
{
test_data data = {
.machine = "virt",
@@ -1901,7 +1901,7 @@ static void test_acpi_microvm_acpi_erst(void)
}
#endif /* CONFIG_POSIX */
-static void test_acpi_virt_tcg(void)
+static void test_acpi_aarch64_virt_tcg(void)
{
test_data data = {
.machine = "virt",
@@ -1920,7 +1920,7 @@ static void test_acpi_virt_tcg(void)
free_test_data();
}
-static void test_acpi_virt_tcg_topology(void)
+static void test_acpi_aarch64_virt_tcg_topology(void)
{
test_data data = {
.machine = "virt",
@@ -2003,7 +2003,7 @@ static void test_acpi_q35_cxl(void)
}
#endif /* CONFIG_POSIX */
-static void test_acpi_virt_viot(void)
+static void test_acpi_aarch64_virt_viot(void)
{
test_data data = {
.machine = "virt",
@@ -2135,7 +2135,7 @@ static void test_acpi_microvm_oem_fields(void)
g_free(args);
}
-static void test_acpi_virt_oem_fields(void)
+static void test_acpi_aarch64_virt_oem_fields(void)
{
test_data data = {
.machine = "virt",
@@ -2301,16 +2301,19 @@ int main(int argc, char *argv[])
}
} else if (strcmp(arch, "aarch64") == 0) {
if (has_tcg && qtest_has_device("virtio-blk-pci")) {
-qtest_add_func("acpi/virt", test_acpi_virt_tcg);
+qtest_add_func("acpi/virt", test_acpi_aarch64_virt_tcg);
qtest_add_func("acpi/virt/acpihmatvirt",
-test_acpi_virt_tcg_acpi_hmat);
-qtest_add_func("acpi/virt/topology", test_acpi_virt_tcg_topology);
-qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem);
-qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
-qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
-qtest_add_func("acpi/virt/oem-fields", test_acpi_virt_oem_fields);
+ test_acpi_aarch64_virt_tcg_acpi_hmat);
+qtest_add_func("acpi/virt/topology",
+ test_acpi_aarch64_virt_tcg_topology);
+qtest_add_func("acpi/virt/numamem",
+ test_acpi_aarch64_virt_tcg_numamem);
+qtest_add_func("acpi/virt/memhp",
test_acpi_aarch64_virt_tcg_memhp);
+qtest_add_func("acpi/virt/pxb", test_acpi_aarch64_virt_tcg_pxb);
+qtest_add_func("acpi/virt/oem-fields",
+ test_acpi_aarch64_virt_oem_fields);
if (qtest_has_device("virtio-iommu-pci")) {
-qtest_add_func("acpi/virt/viot", test_acpi_virt_viot);
+qtest_add_func("acpi/virt/viot", test_acpi_aarch64_virt_viot);
}
}
}
--
2.40.1
[PATCH 10/12] tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V
Update the list of supported architectures to include RISC-V. Signed-off-by: Sunil V L --- tests/data/acpi/rebuild-expected-aml.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/data/acpi/rebuild-expected-aml.sh b/tests/data/acpi/rebuild-expected-aml.sh index dcf2e2f221..c1092fb8ba 100755 --- a/tests/data/acpi/rebuild-expected-aml.sh +++ b/tests/data/acpi/rebuild-expected-aml.sh @@ -12,7 +12,7 @@ # This work is licensed under the terms of the GNU GPLv2. # See the COPYING.LIB file in the top-level directory. -qemu_arches="x86_64 aarch64" +qemu_arches="x86_64 aarch64 riscv64" if [ ! -e "tests/qtest/bios-tables-test" ]; then echo "Test: bios-tables-test is required! Run make check before this script." @@ -36,7 +36,8 @@ fi if [ -z "$qemu_bins" ]; then echo "Only the following architectures are currently supported: $qemu_arches" echo "None of these configured!" -echo "To fix, run configure --target-list=x86_64-softmmu,aarch64-softmmu" +echo "To fix, run configure \ + --target-list=x86_64-softmmu,aarch64-softmmu,riscv64-softmmu" exit 1; fi -- 2.40.1
[PATCH 09/12] pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs
Update list of images supported in unpack_edk2_blobs to enable RISC-V
ACPI table testing.
Signed-off-by: Sunil V L
---
pc-bios/meson.build | 2 ++
tests/qtest/meson.build | 3 +++
2 files changed, 5 insertions(+)
diff --git a/pc-bios/meson.build b/pc-bios/meson.build
index 0760612bea..8602b45b9b 100644
--- a/pc-bios/meson.build
+++ b/pc-bios/meson.build
@@ -4,6 +4,8 @@ if unpack_edk2_blobs
'edk2-aarch64-code.fd',
'edk2-arm-code.fd',
'edk2-arm-vars.fd',
+'edk2-riscv-code.fd',
+'edk2-riscv-vars.fd',
'edk2-i386-code.fd',
'edk2-i386-secure-code.fd',
'edk2-i386-vars.fd',
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 36c5c13a7b..dd19711d9f 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -252,6 +252,9 @@ qtests_s390x = \
qtests_riscv32 = \
(config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ?
['sifive-e-aon-watchdog-test'] : [])
+qtests_riscv64 = \
+ (unpack_edk2_blobs ? ['bios-tables-test'] : [])
+
qos_test_ss = ss.source_set()
qos_test_ss.add(
'ac97-test.c',
--
2.40.1
[PATCH 11/12] tests/data/acpi/virt/riscv64: Add expected ACPI tables for RISC-V
Add expected ACPI tables for RISC-V so that bios-table-test can be
enabled for RISC-V.
Signed-off-by: Sunil V L
---
tests/data/acpi/virt/riscv64/APIC | Bin 0 -> 116 bytes
tests/data/acpi/virt/riscv64/BGRT | Bin 0 -> 56 bytes
tests/data/acpi/virt/riscv64/DSDT | Bin 0 -> 3518 bytes
tests/data/acpi/virt/riscv64/FACP | Bin 0 -> 276 bytes
tests/data/acpi/virt/riscv64/MCFG | Bin 0 -> 60 bytes
tests/data/acpi/virt/riscv64/RHCT | Bin 0 -> 314 bytes
tests/data/acpi/virt/riscv64/RSDP | Bin 0 -> 36 bytes
tests/data/acpi/virt/riscv64/SPCR | Bin 0 -> 80 bytes
tests/data/acpi/virt/riscv64/XSDT | Bin 0 -> 84 bytes
9 files changed, 0 insertions(+), 0 deletions(-)
create mode 100755 tests/data/acpi/virt/riscv64/APIC
create mode 100755 tests/data/acpi/virt/riscv64/BGRT
create mode 100755 tests/data/acpi/virt/riscv64/DSDT
create mode 100755 tests/data/acpi/virt/riscv64/FACP
create mode 100755 tests/data/acpi/virt/riscv64/MCFG
create mode 100755 tests/data/acpi/virt/riscv64/RHCT
create mode 100755 tests/data/acpi/virt/riscv64/RSDP
create mode 100755 tests/data/acpi/virt/riscv64/SPCR
create mode 100755 tests/data/acpi/virt/riscv64/XSDT
diff --git a/tests/data/acpi/virt/riscv64/APIC
b/tests/data/acpi/virt/riscv64/APIC
new file mode 100755
index
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diff --git a/tests/data/acpi/virt/riscv64/RSDP
b/tests/data/acpi/virt/riscv64/RSDP
new file mode 100755
index
..55054f8730c389d0d7eba90c24a1dae6d1283b90
GIT binary patch
literal 36
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HcmV?d1
diff --git a/tests/data/acpi/virt/riscv64/XSDT
b/tests/data/acpi/virt/riscv64/XSDT
new file mode 100755
index
..c69474889664d72d075419c0a1dcf1d82ec44268
GIT binary patch
literal 84
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[PATCH 06/12] tests/qtest/bios-tables-test.c: Add support for arch in path
Since virt machine is common for multiple architectures, add "arch" in
the path to search expected AML files. Since the AML files are still
under old path, support both by searching with and without arch in the
path.
Signed-off-by: Sunil V L
---
tests/qtest/bios-tables-test.c | 32 +---
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index ea3ba1992b..c492438ced 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -78,6 +78,7 @@
typedef struct {
bool tcg_only;
const char *machine;
+const char *arch;
const char *machine_param;
const char *variant;
const char *uefi_fl1;
@@ -262,8 +263,20 @@ static void dump_aml_files(test_data *data, bool rebuild)
g_assert(exp_sdt->aml);
if (rebuild) {
-aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
+aml_file = g_strdup_printf("%s/%s/%s/%.4s%s", data_dir,
+ data->machine, data->arch,
sdt->aml, ext);
+
+/*
+ * To keep test cases not failing when the DATA files are moved to
+ * ARCH under virt folder, add this check which can be removed once
+ * the DATA files are moved.
+ */
+if (!g_file_test(aml_file, G_FILE_TEST_EXISTS)) {
+aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir,
data->machine,
+ sdt->aml, ext);
+}
+
if (!g_file_test(aml_file, G_FILE_TEST_EXISTS) &&
sdt->aml_len == exp_sdt->aml_len &&
!memcmp(sdt->aml, exp_sdt->aml, sdt->aml_len)) {
@@ -398,8 +411,13 @@ static GArray *load_expected_aml(test_data *data)
memset(_sdt, 0, sizeof(exp_sdt));
try_again:
-aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
- sdt->aml, ext);
+aml_file = g_strdup_printf("%s/%s/%s/%.4s%s", data_dir, data->machine,
+ data->arch, sdt->aml, ext);
+if (!g_file_test(aml_file, G_FILE_TEST_EXISTS)) {
+aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
+ sdt->aml, ext);
+}
+exp_sdt.aml_file = aml_file;
if (verbosity_level >= 2) {
fprintf(stderr, "Looking for expected file '%s'\n", aml_file);
}
@@ -1561,6 +1579,7 @@ static void test_acpi_aarch64_virt_tcg_memhp(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
@@ -1654,6 +1673,7 @@ static void test_acpi_aarch64_virt_tcg_numamem(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
@@ -1676,6 +1696,7 @@ static void test_acpi_aarch64_virt_tcg_pxb(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
@@ -1749,6 +1770,7 @@ static void test_acpi_aarch64_virt_tcg_acpi_hmat(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
@@ -1905,6 +1927,7 @@ static void test_acpi_aarch64_virt_tcg(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
@@ -1924,6 +1947,7 @@ static void test_acpi_aarch64_virt_tcg_topology(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.variant = ".topology",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
@@ -2007,6 +2031,7 @@ static void test_acpi_aarch64_virt_viot(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
@@ -2139,6 +2164,7 @@ static void test_acpi_aarch64_virt_oem_fields(void)
{
test_data data = {
.machine = "virt",
+.arch = "aarch64",
.tcg_only = true,
.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
--
2.40.1
[PATCH 08/12] meson.build: Add RISC-V to the edk2-target list
so that ACPI table test can be supported.
Signed-off-by: Sunil V L
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index b8ded80cbe..bf50688593 100644
--- a/meson.build
+++ b/meson.build
@@ -93,7 +93,7 @@ else
iasl = find_program(get_option('iasl'), required: true)
endif
-edk2_targets = [ 'arm-softmmu', 'aarch64-softmmu', 'i386-softmmu',
'x86_64-softmmu' ]
+edk2_targets = [ 'arm-softmmu', 'aarch64-softmmu', 'i386-softmmu',
'x86_64-softmmu', 'riscv64-softmmu' ]
unpack_edk2_blobs = false
foreach target : edk2_targets
if target in target_dirs
--
2.40.1
[PATCH 03/12] uefi-test-tools: Add support for python based build script
edk2-funcs.sh which is used in this Makefile, was removed in the commit
c28a2891f3 ("edk2: update build script"). It is replaced with a python
based script. So, update the Makefile and add the configuration file as
required to support the python based build script.
Signed-off-by: Sunil V L
---
tests/uefi-test-tools/Makefile | 18 +++
tests/uefi-test-tools/uefi-test-build.config | 57
2 files changed, 63 insertions(+), 12 deletions(-)
create mode 100644 tests/uefi-test-tools/uefi-test-build.config
diff --git a/tests/uefi-test-tools/Makefile b/tests/uefi-test-tools/Makefile
index 0c003f2877..f94738b645 100644
--- a/tests/uefi-test-tools/Makefile
+++ b/tests/uefi-test-tools/Makefile
@@ -12,7 +12,7 @@
edk2_dir := ../../roms/edk2
images_dir:= ../data/uefi-boot-images
-emulation_targets := arm aarch64 i386 x86_64
+emulation_targets := arm aarch64 i386 x86_64 riscv64
uefi_binaries := bios-tables-test
intermediate_suffixes := .efi .fat .iso.raw
@@ -56,7 +56,8 @@ Build/%.iso.raw: Build/%.fat
# stripped from, the argument.
map_arm_to_uefi = $(subst arm,ARM,$(1))
map_aarch64_to_uefi = $(subst aarch64,AA64,$(call map_arm_to_uefi,$(1)))
-map_i386_to_uefi= $(subst i386,IA32,$(call map_aarch64_to_uefi,$(1)))
+map_riscv64_to_uefi = $(subst riscv64,RISCV64,$(call map_aarch64_to_uefi,$(1)))
+map_i386_to_uefi= $(subst i386,IA32,$(call map_riscv64_to_uefi,$(1)))
map_x86_64_to_uefi = $(subst x86_64,X64,$(call map_i386_to_uefi,$(1)))
map_to_uefi = $(subst .,,$(call map_x86_64_to_uefi,$(1)))
@@ -70,7 +71,7 @@ Build/%.fat: Build/%.efi
uefi_bin_b=$$(stat --format=%s -- $<) && \
uefi_fat_kb=$$(( (uefi_bin_b * 11 / 10 + 1023) / 1024 )) && \
uefi_fat_kb=$$(( uefi_fat_kb >= 64 ? uefi_fat_kb : 64 )) && \
- mkdosfs -C $@ -n $(basename $(@F)) -- $$uefi_fat_kb
+ mkdosfs -C $@ -n "bios-test" -- $$uefi_fat_kb
MTOOLS_SKIP_CHECK=1 mmd -i $@ ::EFI
MTOOLS_SKIP_CHECK=1 mmd -i $@ ::EFI/BOOT
MTOOLS_SKIP_CHECK=1 mcopy -i $@ -- $< \
@@ -95,15 +96,8 @@ Build/%.fat: Build/%.efi
# we must mark the recipe manually as recursive, by using the "+" indicator.
# This way, when the inner "make" starts a parallel build of the target edk2
# module, it can communicate with the outer "make"'s job server.
-Build/bios-tables-test.%.efi: build-edk2-tools
- +./build.sh $(edk2_dir) BiosTablesTest $* $@
-
-build-edk2-tools:
- cd $(edk2_dir)/BaseTools && git submodule update --init --force
- $(MAKE) -C $(edk2_dir)/BaseTools \
- PYTHON_COMMAND=$${EDK2_PYTHON_COMMAND:-python3} \
- EXTRA_OPTFLAGS='$(EDK2_BASETOOLS_OPTFLAGS)' \
- EXTRA_LDFLAGS='$(EDK2_BASETOOLS_LDFLAGS)'
+Build/bios-tables-test.%.efi:
+ $(PYTHON) ../../roms/edk2-build.py --config uefi-test-build.config
clean:
rm -rf Build Conf log
diff --git a/tests/uefi-test-tools/uefi-test-build.config
b/tests/uefi-test-tools/uefi-test-build.config
new file mode 100644
index 00..4fb89f7db9
--- /dev/null
+++ b/tests/uefi-test-tools/uefi-test-build.config
@@ -0,0 +1,57 @@
+[global]
+core = ../../roms/edk2
+
+
+# arm
+
+[build.arm]
+conf = UefiTestToolsPkg/UefiTestToolsPkg.dsc
+plat = UefiTestTools
+module = UefiTestToolsPkg/BiosTablesTest/BiosTablesTest.inf
+dest = ./Build
+arch = ARM
+cpy1 = ARM/BiosTablesTest.efi bios-tables-test.arm.efi
+
+
+# aarch64
+
+[build.aarch64]
+conf = UefiTestToolsPkg/UefiTestToolsPkg.dsc
+plat = UefiTestTools
+module = UefiTestToolsPkg/BiosTablesTest/BiosTablesTest.inf
+dest = ./Build
+arch = AARCH64
+cpy1 = AARCH64/BiosTablesTest.efi bios-tables-test.aarch64.efi
+
+
+# riscv64
+
+[build.riscv]
+conf = UefiTestToolsPkg/UefiTestToolsPkg.dsc
+plat = UefiTestTools
+module = UefiTestToolsPkg/BiosTablesTest/BiosTablesTest.inf
+dest = ./Build
+arch = RISCV64
+cpy1 = RISCV64/BiosTablesTest.efi bios-tables-test.riscv64.efi
+
+
+# ia32
+
+[build.ia32]
+conf = UefiTestToolsPkg/UefiTestToolsPkg.dsc
+plat = UefiTestTools
+module = UefiTestToolsPkg/BiosTablesTest/BiosTablesTest.inf
+dest = ./Build
+arch = IA32
+cpy1 = IA32/BiosTablesTest.efi bios-tables-test.i386.efi
+
+
+# x64
+
+[build.x64]
+conf = UefiTestToolsPkg/UefiTestToolsPkg.dsc
+plat = UefiTestTools
+module = UefiTestToolsPkg/BiosTablesTest/BiosTablesTest.inf
+dest = ./Build
+arch = X64
+cpy1 = X64/BiosTablesTest.efi bios-tables-test.x86_64.efi
--
2.40.1
[PATCH 12/12] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
Add basic ACPI table testing for RISC-V.
Signed-off-by: Sunil V L
---
tests/qtest/bios-tables-test.c | 28
1 file changed, 28 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index c492438ced..033acc8958 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1923,6 +1923,30 @@ static void test_acpi_microvm_acpi_erst(void)
}
#endif /* CONFIG_POSIX */
+static void test_acpi_riscv64_virt_tcg(void)
+{
+test_data data = {
+.machine = "virt",
+.arch = "riscv64",
+.tcg_only = true,
+.uefi_fl1 = "pc-bios/edk2-riscv-code.fd",
+.uefi_fl2 = "pc-bios/edk2-riscv-vars.fd",
+.ram_start = 0x8000ULL,
+.scan_len = 128ULL * 1024 * 1024,
+};
+
+/*
+ * RHCT will have ISA string encoded. To reduce the effort
+ * of updating expected AML file for any new default ISA extension,
+ * use the profile rva22s64. Once profile is ratified, there may
+ * not be new extension possible.
+ */
+test_acpi_one("-cpu rva22s64 -device virtio-blk-device,drive=hd0 "
+ "-drive
file=tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2,id=hd0",
+ );
+free_test_data();
+}
+
static void test_acpi_aarch64_virt_tcg(void)
{
test_data data = {
@@ -2342,6 +2366,10 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/virt/viot", test_acpi_aarch64_virt_viot);
}
}
+} else if (strcmp(arch, "riscv64") == 0) {
+if (has_tcg && qtest_has_device("virtio-blk-pci")) {
+qtest_add_func("acpi/virt", test_acpi_riscv64_virt_tcg);
+}
}
ret = g_test_run();
boot_sector_cleanup(disk);
--
2.40.1
[PATCH 04/12] tests/data/uefi-boot-images: Add RISC-V ISO image
To test ACPI tables, edk2 needs to be booted with a disk image having
EFI partition. This image is created using UefiTestToolsPkg.
Signed-off-by: Sunil V L
---
.../bios-tables-test.riscv64.iso.qcow2 | Bin 0 -> 16896 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
create mode 100644
tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2
diff --git a/tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2
b/tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2
new file mode 100644
index
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zT%+T5%+e}#+pEt@n{;gjGpzCM7w+kom~=ga>>nU
[PATCH 01/12] roms/edk2-build.py: Add --module support
UefiTestToolsPkg which should use edk2-build.py needs --module parameter support. Add this optional parameter handling. Signed-off-by: Sunil V L --- roms/edk2-build.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/roms/edk2-build.py b/roms/edk2-build.py index e564765aaa..3bfe200929 100755 --- a/roms/edk2-build.py +++ b/roms/edk2-build.py @@ -192,6 +192,9 @@ def build_one(cfg, build, jobs = None, silent = False, nologs = False): cmdline += [ '-n', jobs ] for arch in b['arch'].split(): cmdline += [ '-a', arch ] +if 'module' in b: +for module in b['module'].split(): +cmdline += [ '-m', module ] if 'opts' in b: for name in b['opts'].split(): section = 'opts.' + name -- 2.40.1
[PATCH 00/12] Add support for RISC-V ACPI tests
Currently, bios-table-test doesn't support RISC-V. This series enables
the framework changes required and basic testing. Things like NUMA
related test cases will be added later.
This needs refactoring/renaming of ARM64 bios table tests. Importantly,
the test cases now look for the expected AML files under
tests/data/acpi/virt/aarch64 path instead of directly under
tests/data/acpi/virt. To keep test cases not to fail because of this
movement, they are updated to look for both paths first.
As part of this effort, it is found that uefi-test-tools is currently
broken to build. So, updated its Makefile as well to use python based
edk2 build script.
The series depends on Gerd's below series.
https://lists.gnu.org/archive/html/qemu-devel/2024-03/msg03855.html
The changes are also available at branch
https://gitlab.com/vlsunil/qemu/-/tree/riscv_bios_table_test_v1
This branch which is on top of Gerd's series completed CI tests.
https://gitlab.com/vlsunil/qemu/-/pipelines/1214784985
Sunil V L (12):
roms/edk2-build.py: Add --module support
uefi-test-tools/UefiTestToolsPkg: Add RISC-V support
uefi-test-tools: Add support for python based build script
tests/data/uefi-boot-images: Add RISC-V ISO image
qtest: bios-tables-test: Rename aarch64 tests with aarch64 in them
tests/qtest/bios-tables-test.c: Add support for arch in path
tests/data/acpi/virt: Move ACPI tables under aarch64
meson.build: Add RISC-V to the edk2-target list
pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs
tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V
tests/data/acpi/virt/riscv64: Add expected ACPI tables for RISC-V
tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
meson.build | 2 +-
pc-bios/meson.build | 2 +
roms/edk2-build.py| 3 +
tests/data/acpi/rebuild-expected-aml.sh | 5 +-
tests/data/acpi/virt/{ => aarch64}/APIC | Bin
.../acpi/virt/{ => aarch64}/APIC.acpihmatvirt | Bin
.../acpi/virt/{ => aarch64}/APIC.topology | Bin
tests/data/acpi/virt/{ => aarch64}/DBG2 | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT | Bin
.../acpi/virt/{ => aarch64}/DSDT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/DSDT.pxb | Bin
.../acpi/virt/{ => aarch64}/DSDT.topology | Bin
tests/data/acpi/virt/{ => aarch64}/FACP | Bin
tests/data/acpi/virt/{ => aarch64}/GTDT | Bin
.../acpi/virt/{ => aarch64}/HMAT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/IORT | Bin
tests/data/acpi/virt/{ => aarch64}/MCFG | Bin
tests/data/acpi/virt/{ => aarch64}/NFIT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/PPTT | Bin
.../acpi/virt/{ => aarch64}/PPTT.acpihmatvirt | Bin
.../acpi/virt/{ => aarch64}/PPTT.topology | Bin
tests/data/acpi/virt/{ => aarch64}/SLIT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/SPCR | Bin
.../acpi/virt/{ => aarch64}/SRAT.acpihmatvirt | Bin
tests/data/acpi/virt/{ => aarch64}/SRAT.memhp | Bin
.../data/acpi/virt/{ => aarch64}/SRAT.numamem | Bin
tests/data/acpi/virt/{ => aarch64}/SSDT.memhp | Bin
tests/data/acpi/virt/{ => aarch64}/VIOT | Bin
tests/data/acpi/virt/riscv64/APIC | Bin 0 -> 116 bytes
tests/data/acpi/virt/riscv64/BGRT | Bin 0 -> 56 bytes
tests/data/acpi/virt/riscv64/DSDT | Bin 0 -> 3518 bytes
tests/data/acpi/virt/riscv64/FACP | Bin 0 -> 276 bytes
tests/data/acpi/virt/riscv64/MCFG | Bin 0 -> 60 bytes
tests/data/acpi/virt/riscv64/RHCT | Bin 0 -> 314 bytes
tests/data/acpi/virt/riscv64/RSDP | Bin 0 -> 36 bytes
tests/data/acpi/virt/riscv64/SPCR | Bin 0 -> 80 bytes
tests/data/acpi/virt/riscv64/XSDT | Bin 0 -> 84 bytes
.../bios-tables-test.riscv64.iso.qcow2| Bin 0 -> 16896 bytes
tests/qtest/bios-tables-test.c| 95 ++
tests/qtest/meson.build | 3 +
tests/uefi-test-tools/Makefile| 18 ++--
.../UefiTestToolsPkg/UefiTestToolsPkg.dsc | 6 +-
tests/uefi-test-tools/uefi-test-build.config | 57 +++
44 files changed, 156 insertions(+), 35 deletions(-)
rename tests/data/acpi/virt/{ => aarch64}/APIC (100%)
rename tests/data/acpi/virt/{ => aarch64}/APIC.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/APIC.topology (100%)
rename tests/data/acpi/virt/{ => aarch64}/DBG2 (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.acpihmatvirt (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.memhp (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.pxb (100%)
rename tests/data/acpi/virt/{ => aarch64}/DSDT.topology (100%)
renam
[PATCH 02/12] uefi-test-tools/UefiTestToolsPkg: Add RISC-V support
Enable building the test application for RISC-V with appropriate dependencies updated. Signed-off-by: Sunil V L --- tests/uefi-test-tools/UefiTestToolsPkg/UefiTestToolsPkg.dsc | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tests/uefi-test-tools/UefiTestToolsPkg/UefiTestToolsPkg.dsc b/tests/uefi-test-tools/UefiTestToolsPkg/UefiTestToolsPkg.dsc index c8511cd732..0902fd3c73 100644 --- a/tests/uefi-test-tools/UefiTestToolsPkg/UefiTestToolsPkg.dsc +++ b/tests/uefi-test-tools/UefiTestToolsPkg/UefiTestToolsPkg.dsc @@ -19,7 +19,7 @@ PLATFORM_VERSION= 0.1 PLATFORM_NAME = UefiTestTools SKUID_IDENTIFIER= DEFAULT - SUPPORTED_ARCHITECTURES = ARM|AARCH64|IA32|X64 + SUPPORTED_ARCHITECTURES = ARM|AARCH64|IA32|X64|RISCV64 BUILD_TARGETS = DEBUG [BuildOptions.IA32] @@ -60,6 +60,10 @@ [LibraryClasses.IA32, LibraryClasses.X64] BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf + RegisterFilterLib|MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.inf + +[LibraryClasses.RISCV64] + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf [PcdsFixedAtBuild] gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8040004F -- 2.40.1
Re: [PATCH v2 1/2] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
On Thu, Mar 07, 2024 at 11:33:25AM +1000, Alistair Francis wrote:
> On Thu, Mar 7, 2024 at 4:59 AM Daniel Henrique Barboza
> wrote:
> >
> > Hi,
> >
> > This patch break check-qtest, most specifically 'bios-table'test', for
> > aarch64.
> > I found this while running riscv-to-apply.next in the Gitlab pipeline.
> >
> >
> > Here's the output:
> >
> > $ make -j && QTEST_QEMU_BINARY=./qemu-system-aarch64 V=1
> > ./tests/qtest/bios-tables-test
> > TAP version 13
> > # random seed: R02Sf0f2fa0a3fac5d540b1681c820621b7d
> > # starting QEMU: exec ./qemu-system-aarch64 -qtest
> > unix:/tmp/qtest-591353.sock -qtest-log /dev/null -chardev
> > socket,path=/tmp/qtest-591353.qmp,id=char0 -mon chardev=char0,mode=control
> > -display none -audio none -machine none -accel qtest
> > 1..8
> > # Start of aarch64 tests
> > # Start of acpi tests
> > # starting QEMU: exec ./qemu-system-aarch64 -qtest
> > unix:/tmp/qtest-591353.sock -qtest-log /dev/null -chardev
> > socket,path=/tmp/qtest-591353.qmp,id=char0 -mon chardev=char0,mode=control
> > -display none -audio none -machine virt -accel tcg -nodefaults -nographic
> > -drive if=pflash,format=raw,file=pc-bios/edk2-aarch64-code.fd,readonly=on
> > -drive if=pflash,format=raw,file=pc-bios/edk2-arm-vars.fd,snapshot=on
> > -cdrom tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2 -cpu
> > cortex-a57 -smbios type=4,max-speed=2900,current-speed=2700 -accel qtest
> > acpi-test: Warning! SPCR binary file mismatch. Actual
> > [aml:/tmp/aml-9G53J2], Expected [aml:tests/data/acpi/virt/SPCR].
> > See source file tests/qtest/bios-tables-test.c for instructions on how to
> > update expected files.
> > acpi-test: Warning! SPCR mismatch. Actual [asl:/tmp/asl-SR53J2.dsl,
> > aml:/tmp/aml-9G53J2], Expected [asl:/tmp/asl-4Z33J2.dsl,
> > aml:tests/data/acpi/virt/SPCR].
> >
> > The diff is here:
> >
> > --- /tmp/asl-4Z33J2.dsl 2024-03-06 15:40:24.879879348 -0300
> > +++ /tmp/asl-SR53J2.dsl 2024-03-06 15:40:24.877879347 -0300
> > @@ -1,57 +1,49 @@
> > /*
> >* Intel ACPI Component Architecture
> >* AML/ASL+ Disassembler version 20220331 (64-bit version)
> >* Copyright (c) 2000 - 2022 Intel Corporation
> >
> > (...)
> >
> > [000h 4]Signature : "SPCR"[Serial Port
> > Console Redirection Table]
> > -[004h 0004 4] Table Length : 0050
> > +[004h 0004 4] Table Length : 004F
> > [008h 0008 1] Revision : 02
> > -[009h 0009 1] Checksum : B1
> > +[009h 0009 1] Checksum : B2
> > [00Ah 0010 6] Oem ID : "BOCHS "
> >
> > (...)
> >
> > -[042h 0066 2]PCI Vendor ID :
> > +[042h 0066 2]PCI Vendor ID : 00FF
> >
> >
> > After inspecting the common helper and what the original ARM code was doing
> > I found out that we're missing something down there:
> >
> >
> > On 1/15/24 22:09, Sia Jee Heng wrote:
> > > RISC-V should also generate the SPCR in a manner similar to ARM.
> > > Therefore, instead of replicating the code, relocate this function
> > > to the common AML build.
> > >
> > > Signed-off-by: Sia Jee Heng
> > > ---
> > > hw/acpi/aml-build.c | 51
> > > hw/arm/virt-acpi-build.c| 68 +++--
> > > include/hw/acpi/acpi-defs.h | 33 ++
> > > include/hw/acpi/aml-build.h | 4 +++
> > > 4 files changed, 115 insertions(+), 41 deletions(-)
> > >
> > > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> > > index af66bde0f5..f3904650e4 100644
> > > --- a/hw/acpi/aml-build.c
> > > +++ b/hw/acpi/aml-build.c
> > > @@ -1994,6 +1994,57 @@ static void build_processor_hierarchy_node(GArray
> > > *tbl, uint32_t flags,
> > > }
> > > }
> > >
> > > +void build_spcr(GArray *table_data, BIOSLinker *linker,
> > > +const AcpiSpcrData *f, const uint8_t rev,
> > > +const char *oem_id, const char *oem_table_id)
> > > +{
> > > +AcpiTable table = { .sig = "SPCR", .rev = rev, .oem_id = oem_id,
> > > +.oem_table_id = oem_table_id };
> > > +
> > > +acpi_table_begin(, table_data);
> > > +/* Interface type */
> > > +build_append_int_noprefix(table_data, f->interface_type, 1);
> > > +/* Reserved */
> > > +build_append_int_noprefix(table_data, 0, 3);
> > > +/* Base Address */
> > > +build_append_gas(table_data, f->base_addr.id, f->base_addr.width,
> > > + f->base_addr.offset, f->base_addr.size,
> > > + f->base_addr.addr);
> > > +/* Interrupt type */
> > > +build_append_int_noprefix(table_data, f->interrupt_type, 1);
> > > +/* IRQ */
> > > +build_append_int_noprefix(table_data, f->pc_interrupt, 1);
> > > +/* Global System Interrupt */
> > > +build_append_int_noprefix(table_data, f->interrupt, 4);
> > > +/* Baud Rate */
> > > +
Re: [PATCH] target/riscv: fix ACPI MCFG table
On Mon, Feb 19, 2024 at 05:43:56PM +0100, Philippe Mathieu-Daudé wrote:
> On 19/2/24 17:09, X512 via wrote:
> > MCFG segments should point to PCI configuration range, not BAR MMIO.
> >
>
> Fixes: 55ecd83b36 ("hw/riscv/virt-acpi-build.c: Add IO controllers and
> devices")
> Reviewed-by: Philippe Mathieu-Daudé
>
> > Signed-off-by: Ilya Chugin
> > ---
> > Â hw/riscv/virt-acpi-build.c | 4 ++--
> > Â 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> > index fb8baf64f6..fe01b626ea 100644
> > --- a/hw/riscv/virt-acpi-build.c
> > +++ b/hw/riscv/virt-acpi-build.c
> > @@ -558,8 +558,8 @@ static void virt_acpi_build(RISCVVirtState *s,
> > AcpiBuildTables *tables)
> > acpi_add_table(table_offsets, tables_blob);
> > {
> > AcpiMcfgInfo mcfg = {
> > -Â Â .base = s->memmap[VIRT_PCIE_MMIO].base,
> > -Â Â .size = s->memmap[VIRT_PCIE_MMIO].size,
> > +Â Â .base = s->memmap[VIRT_PCIE_ECAM].base,
> > +Â Â .size = s->memmap[VIRT_PCIE_ECAM].size,
Thanks!.
Reviewed-by: Sunil V L
> > };
> > build_mcfg(tables_blob, tables->linker, , s->oem_id,
> > Â Â Â s->oem_table_id);
>
Re: [RESEND v2 1/2] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
Hi Jee Heng,
On Sun, Jan 28, 2024 at 06:14:39PM -0800, Sia Jee Heng wrote:
> RISC-V should also generate the SPCR in a manner similar to ARM.
> Therefore, instead of replicating the code, relocate this function
> to the common AML build.
>
> Signed-off-by: Sia Jee Heng
> ---
> hw/acpi/aml-build.c | 51
> hw/arm/virt-acpi-build.c| 68 +++--
> include/hw/acpi/acpi-defs.h | 33 ++
> include/hw/acpi/aml-build.h | 4 +++
> 4 files changed, 115 insertions(+), 41 deletions(-)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index af66bde0f5..f3904650e4 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -1994,6 +1994,57 @@ static void build_processor_hierarchy_node(GArray
> *tbl, uint32_t flags,
> }
> }
>
> +void build_spcr(GArray *table_data, BIOSLinker *linker,
> +const AcpiSpcrData *f, const uint8_t rev,
> +const char *oem_id, const char *oem_table_id)
> +{
> +AcpiTable table = { .sig = "SPCR", .rev = rev, .oem_id = oem_id,
> +.oem_table_id = oem_table_id };
> +
> +acpi_table_begin(, table_data);
> +/* Interface type */
> +build_append_int_noprefix(table_data, f->interface_type, 1);
> +/* Reserved */
> +build_append_int_noprefix(table_data, 0, 3);
> +/* Base Address */
> +build_append_gas(table_data, f->base_addr.id, f->base_addr.width,
> + f->base_addr.offset, f->base_addr.size,
> + f->base_addr.addr);
> +/* Interrupt type */
> +build_append_int_noprefix(table_data, f->interrupt_type, 1);
> +/* IRQ */
> +build_append_int_noprefix(table_data, f->pc_interrupt, 1);
> +/* Global System Interrupt */
> +build_append_int_noprefix(table_data, f->interrupt, 4);
> +/* Baud Rate */
> +build_append_int_noprefix(table_data, f->baud_rate, 1);
> +/* Parity */
> +build_append_int_noprefix(table_data, f->parity, 1);
> +/* Stop Bits */
> +build_append_int_noprefix(table_data, f->stop_bits, 1);
> +/* Flow Control */
> +build_append_int_noprefix(table_data, f->flow_control, 1);
> +/* Terminal Type */
> +build_append_int_noprefix(table_data, f->terminal_type, 1);
> +/* PCI Device ID */
> +build_append_int_noprefix(table_data, f->pci_device_id, 2);
> +/* PCI Vendor ID */
> +build_append_int_noprefix(table_data, f->pci_vendor_id, 2);
> +/* PCI Bus Number */
> +build_append_int_noprefix(table_data, f->pci_bus, 1);
> +/* PCI Device Number */
> +build_append_int_noprefix(table_data, f->pci_device, 1);
> +/* PCI Function Number */
> +build_append_int_noprefix(table_data, f->pci_function, 1);
> +/* PCI Flags */
> +build_append_int_noprefix(table_data, f->pci_flags, 4);
> +/* PCI Segment */
> +build_append_int_noprefix(table_data, f->pci_segment, 1);
> +/* Reserved */
> +build_append_int_noprefix(table_data, 0, 4);
> +
I think either there should be a comment that this supports only v2 of
SPCR spec or it should be able to create SPCR of any version. IMO, I
think it is better to add support till v4 (latest). Since consumers like
Linux probably doesn't support v4 yet, ARM/RISC-V can continue to create
v2 itself for the time being but the generic build_spcr() should be able
to create v4 also if the arch requires it.
Thanks,
Sunil
> +acpi_table_end(linker, );
> +}
> /*
> * ACPI spec, Revision 6.3
> * 5.2.29 Processor Properties Topology Table (PPTT)
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index a22a2f43a5..195767c0f0 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -431,48 +431,34 @@ build_iort(GArray *table_data, BIOSLinker *linker,
> VirtMachineState *vms)
> * Rev: 1.07
> */
> static void
> -build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
> +spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
> {
> -AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id,
> -.oem_table_id = vms->oem_table_id };
> -
> -acpi_table_begin(, table_data);
> -
> -/* Interface Type */
> -build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */
> -build_append_int_noprefix(table_data, 0, 3); /* Reserved */
> -/* Base Address */
> -build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3,
> - vms->memmap[VIRT_UART].base);
> -/* Interrupt Type */
> -build_append_int_noprefix(table_data,
> -(1 << 3) /* Bit[3] ARMH GIC interrupt */, 1);
> -build_append_int_noprefix(table_data, 0, 1); /* IRQ */
> -/* Global System Interrupt */
> -build_append_int_noprefix(table_data,
> - vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4);
> -build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */
> -
Re: [RESEND RFC v1 1/2] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
On Fri, Jan 05, 2024 at 09:19:14AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 1/5/24 06:06, Sia Jee Heng wrote:
> > RISC-V should also generate the SPCR in a manner similar to ARM.
> > Therefore, instead of replicating the code, relocate this function
> > to the common AML build.
> >
> > Signed-off-by: Sia Jee Heng
> > ---
> > hw/acpi/aml-build.c | 51
> > hw/arm/virt-acpi-build.c| 68 +++--
> > include/hw/acpi/acpi-defs.h | 33 ++
> > include/hw/acpi/aml-build.h | 4 +++
> > 4 files changed, 115 insertions(+), 41 deletions(-)
> >
> > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> > index af66bde0f5..1efa534aa8 100644
> > --- a/hw/acpi/aml-build.c
> > +++ b/hw/acpi/aml-build.c
> > @@ -1994,6 +1994,57 @@ static void build_processor_hierarchy_node(GArray
> > *tbl, uint32_t flags,
> > }
> > }
> > +void build_spcr(GArray *table_data, BIOSLinker *linker,
> > +const AcpiSpcrData *f, const char *oem_id,
> > +const char *oem_table_id)
> > +{
> > +AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = oem_id,
> > +.oem_table_id = oem_table_id };
> > +
> > +acpi_table_begin(, table_data);
> > +/* Interface type */
> > +build_append_int_noprefix(table_data, f->interface_type, 1);
> > +/* Reserved */
> > +build_append_int_noprefix(table_data, 0, 3);
> > +/* Base Address */
> > +build_append_gas(table_data, f->base_addr.id, f->base_addr.width,
> > + f->base_addr.offset, f->base_addr.size,
> > + f->base_addr.addr);
> > +/* Interrupt type */
> > +build_append_int_noprefix(table_data, f->interrupt_type, 1);
> > +/* IRQ */
> > +build_append_int_noprefix(table_data, f->pc_interrupt, 1);
> > +/* Global System Interrupt */
> > +build_append_int_noprefix(table_data, f->interrupt, 4);
> > +/* Baud Rate */
> > +build_append_int_noprefix(table_data, f->baud_rate, 1);
> > +/* Parity */
> > +build_append_int_noprefix(table_data, f->parity, 1);
> > +/* Stop Bits */
> > +build_append_int_noprefix(table_data, f->stop_bits, 1);
> > +/* Flow Control */
> > +build_append_int_noprefix(table_data, f->flow_control, 1);
> > +/* Terminal Type */
> > +build_append_int_noprefix(table_data, f->terminal_type, 1);
> > +/* PCI Device ID */
> > +build_append_int_noprefix(table_data, f->pci_device_id, 2);
> > +/* PCI Vendor ID */
> > +build_append_int_noprefix(table_data, f->pci_vendor_id, 2);
> > +/* PCI Bus Number */
> > +build_append_int_noprefix(table_data, f->pci_bus, 1);
> > +/* PCI Device Number */
> > +build_append_int_noprefix(table_data, f->pci_device, 1);
> > +/* PCI Function Number */
> > +build_append_int_noprefix(table_data, f->pci_function, 1);
> > +/* PCI Flags */
> > +build_append_int_noprefix(table_data, f->pci_flags, 4);
> > +/* PCI Segment */
> > +build_append_int_noprefix(table_data, f->pci_segment, 1);
> > +/* Reserved */
> > +build_append_int_noprefix(table_data, 0, 4);
> > +
> > +acpi_table_end(linker, );
> > +}
> > /*
> >* ACPI spec, Revision 6.3
> >* 5.2.29 Processor Properties Topology Table (PPTT)
> > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> > index 510ab0dcca..a31f736d1a 100644
> > --- a/hw/arm/virt-acpi-build.c
> > +++ b/hw/arm/virt-acpi-build.c
> > @@ -431,48 +431,34 @@ build_iort(GArray *table_data, BIOSLinker *linker,
> > VirtMachineState *vms)
> >* Rev: 1.07
> >*/
> > static void
> > -build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
> > +build_spcr_v2(GArray *table_data, BIOSLinker *linker, VirtMachineState
> > *vms)
>
> Nit: I don't understand the '_v2' in the name of this function. Is it just to
> not collide
> with the now public build_spcr()? Or does it have to do with the SPCR table
> being
> '.rev = 2'? Because if it's the latter, you can name the common helper
> 'build_spcr_rev2'
> (since both ARM and RISC-V use SPCR rev 2), keep this local build_spcr()
> initializing
> the AcpiSpcrData struct with ARM attributes and then call the common
> build_spcr_rev2().
>
My suggestion is, keep the build_spcr() generic and take version as the
parameter.
Thanks,
Sunil
Re: [PATCH v2 1/1] docs/system/riscv: document acpi parameter of virt machine
On Wed, Dec 20, 2023 at 08:34:36PM +0100, Heinrich Schuchardt wrote:
> Since QEMU v8.0.0 the RISC-V virt machine has a switch to disable ACPI
> table generation. Add it to the documentation.
>
> Fixes: 168b8c29cedb ("hw/riscv/virt: Add a switch to disable ACPI")
> Signed-off-by: Heinrich Schuchardt
> ---
> v2:
> mention that acpi=on is the default
> ---
> docs/system/riscv/virt.rst | 5 +
> 1 file changed, 5 insertions(+)
>
Reviewed-by: Sunil V L
Thanks!
Sunil
Re: [PATCH 1/1] docs/system/riscv: document acpi parameter of virt machine
On Tue, Dec 19, 2023 at 03:38:29PM +0100, Heinrich Schuchardt wrote:
> Since QEMU v8.0.0 the RISC-V virt machine has a switch to disable ACPI
> table generation. Add it to the documentation.
>
> Fixes: 168b8c29cedb ("hw/riscv/virt: Add a switch to disable ACPI")
> Signed-off-by: Heinrich Schuchardt
> ---
> docs/system/riscv/virt.rst | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
> index f5fa7b8b29..4e134ff2ac 100644
> --- a/docs/system/riscv/virt.rst
> +++ b/docs/system/riscv/virt.rst
> @@ -95,6 +95,11 @@ The following machine-specific options are supported:
>SiFive CLINT. When not specified, this option is assumed to be "off".
>This option is restricted to the TCG accelerator.
>
> +- acpi=[on|off|auto]
> +
> + When this option is "on", ACPI tables are generated and exposed as firmware
> + tables etc/acpi/rsdp and etc/acpi/tables.
> +
Hi Heinrich,
Should we add, When not specified or set to auto, this option is assumed
to be "on"?
Thanks,
Sunil
[PATCH v8 13/13] hw/riscv/virt-acpi-build.c: Add PLIC in MADT
Add PLIC structures for each socket in the MADT when system is
configured with PLIC as the external interrupt controller.
Signed-off-by: Haibo Xu
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 4d03a27efd..d4a02579d6 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -94,6 +94,12 @@ static void riscv_acpi_madt_add_rintc(uint32_t uid,
arch_ids->cpus[uid].props.node_id,
local_cpu_id),
4);
+} else if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+build_append_int_noprefix(entry,
+ ACPI_BUILD_INTC_ID(
+ arch_ids->cpus[uid].props.node_id,
+ 2 * local_cpu_id + 1),
+ 4);
} else {
build_append_int_noprefix(entry, 0, 4);
}
@@ -494,6 +500,29 @@ static void build_madt(GArray *table_data,
build_append_int_noprefix(table_data,
s->memmap[VIRT_APLIC_S].size, 4);
}
+} else {
+/* PLICs */
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+aplic_addr = s->memmap[VIRT_PLIC].base +
+ s->memmap[VIRT_PLIC].size * socket;
+gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+build_append_int_noprefix(table_data, 0x1B, 1); /* Type */
+build_append_int_noprefix(table_data, 36, 1); /* Length */
+build_append_int_noprefix(table_data, 1, 1); /* Version */
+build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */
+build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */
+/* Total External Interrupt Sources Supported */
+build_append_int_noprefix(table_data,
+ VIRT_IRQCHIP_NUM_SOURCES - 1, 2);
+build_append_int_noprefix(table_data, 0, 2); /* Max Priority */
+build_append_int_noprefix(table_data, 0, 4); /* Flags */
+/* PLIC Size */
+build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size,
4);
+/* PLIC Address */
+build_append_int_noprefix(table_data, aplic_addr, 8);
+/* Global System Interrupt Vector Base */
+build_append_int_noprefix(table_data, gsi_base, 4);
+}
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v8 05/13] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC
Update the RINTC structure in MADT with AIA related fields.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 43 ++
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index d8772c2821..3f9536356e 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -38,6 +38,7 @@
#include "hw/intc/riscv_aclint.h"
#define ACPI_BUILD_TABLE_SIZE 0x2
+#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
typedef struct AcpiBuildState {
/* Copy of table in RAM (for patching) */
@@ -59,17 +60,50 @@ static void acpi_align_size(GArray *blob, unsigned align)
static void riscv_acpi_madt_add_rintc(uint32_t uid,
const CPUArchIdList *arch_ids,
- GArray *entry)
+ GArray *entry,
+ RISCVVirtState *s)
{
+uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
uint64_t hart_id = arch_ids->cpus[uid].arch_id;
+uint32_t imsic_size, local_cpu_id, socket_id;
+uint64_t imsic_socket_addr, imsic_addr;
+MachineState *ms = MACHINE(s);
+socket_id = arch_ids->cpus[uid].props.node_id;
+local_cpu_id = (arch_ids->cpus[uid].arch_id -
+riscv_socket_first_hartid(ms, socket_id)) %
+riscv_socket_hart_count(ms, socket_id);
+imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base +
+(socket_id * VIRT_IMSIC_GROUP_MAX_SIZE);
+imsic_size = IMSIC_HART_SIZE(guest_index_bits);
+imsic_addr = imsic_socket_addr + local_cpu_id * imsic_size;
build_append_int_noprefix(entry, 0x18, 1); /* Type */
-build_append_int_noprefix(entry, 20, 1); /* Length */
+build_append_int_noprefix(entry, 36, 1); /* Length */
build_append_int_noprefix(entry, 1, 1); /* Version */
build_append_int_noprefix(entry, 0, 1); /* Reserved */
build_append_int_noprefix(entry, 0x1, 4);/* Flags*/
build_append_int_noprefix(entry, hart_id, 8);/* Hart ID */
build_append_int_noprefix(entry, uid, 4);/* ACPI Processor UID */
+/* External Interrupt Controller ID */
+if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
+build_append_int_noprefix(entry,
+ ACPI_BUILD_INTC_ID(
+ arch_ids->cpus[uid].props.node_id,
+ local_cpu_id),
+ 4);
+} else {
+build_append_int_noprefix(entry, 0, 4);
+}
+
+if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+/* IMSIC Base address */
+build_append_int_noprefix(entry, imsic_addr, 8);
+/* IMSIC Size */
+build_append_int_noprefix(entry, imsic_size, 4);
+} else {
+build_append_int_noprefix(entry, 0, 8);
+build_append_int_noprefix(entry, 0, 4);
+}
}
static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
@@ -88,7 +122,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
aml_int(arch_ids->cpus[i].arch_id)));
/* build _MAT object */
-riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf);
+riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf, s);
aml_append(dev, aml_name_decl("_MAT",
aml_buffer(madt_buf->len,
(uint8_t *)madt_buf->data)));
@@ -227,6 +261,7 @@ static void build_dsdt(GArray *table_data,
* 5.2.12 Multiple APIC Description Table (MADT)
* REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15
* https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
+ * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view
*/
static void build_madt(GArray *table_data,
BIOSLinker *linker,
@@ -246,7 +281,7 @@ static void build_madt(GArray *table_data,
/* RISC-V Local INTC structures per HART */
for (int i = 0; i < arch_ids->len; i++) {
-riscv_acpi_madt_add_rintc(i, arch_ids, table_data);
+riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s);
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v8 07/13] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT
Add APLIC structures for each socket in the MADT when system is configured
with APLIC as the external wired interrupt controller.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 6bb21014fd..ec49c8804b 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -274,6 +274,8 @@ static void build_madt(GArray *table_data,
uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
uint16_t imsic_max_hart_per_socket = 0;
uint8_t hart_index_bits;
+uint64_t aplic_addr;
+uint32_t gsi_base;
uint8_t socket;
for (socket = 0; socket < riscv_socket_count(ms); socket++) {
@@ -319,6 +321,38 @@ static void build_madt(GArray *table_data,
build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1);
}
+if (s->aia_type != VIRT_AIA_TYPE_NONE) {
+/* APLICs */
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+aplic_addr = s->memmap[VIRT_APLIC_S].base +
+ s->memmap[VIRT_APLIC_S].size * socket;
+gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+build_append_int_noprefix(table_data, 0x1A, 1);/* Type */
+build_append_int_noprefix(table_data, 36, 1); /* Length */
+build_append_int_noprefix(table_data, 1, 1); /* Version */
+build_append_int_noprefix(table_data, socket, 1); /* APLIC ID */
+build_append_int_noprefix(table_data, 0, 4); /* Flags */
+build_append_int_noprefix(table_data, 0, 8); /* Hardware ID
*/
+/* Number of IDCs */
+if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
+build_append_int_noprefix(table_data,
+ s->soc[socket].num_harts,
+ 2);
+} else {
+build_append_int_noprefix(table_data, 0, 2);
+}
+/* Total External Interrupt Sources Supported */
+build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_SOURCES, 2);
+/* Global System Interrupt Base */
+build_append_int_noprefix(table_data, gsi_base, 4);
+/* APLIC Address */
+build_append_int_noprefix(table_data, aplic_addr, 8);
+/* APLIC size */
+build_append_int_noprefix(table_data,
+ s->memmap[VIRT_APLIC_S].size, 4);
+}
+}
+
acpi_table_end(linker, );
}
--
2.39.2
[PATCH v8 09/13] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT
MMU type information is available via MMU node in RHCT. Add this node in
RHCT.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 36 +++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 506d487ede..86c38f7c2b 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -152,6 +152,8 @@ static void build_rhct(GArray *table_data,
size_t len, aligned_len;
uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
RISCVCPU *cpu = >soc[0].harts[0];
+uint32_t mmu_offset = 0;
+uint8_t satp_mode_max;
char *isa;
AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -171,6 +173,10 @@ static void build_rhct(GArray *table_data,
num_rhct_nodes++;
}
+if (cpu->cfg.satp_mode.supported != 0) {
+num_rhct_nodes++;
+}
+
/* Number of RHCT nodes*/
build_append_int_noprefix(table_data, num_rhct_nodes, 4);
@@ -226,6 +232,26 @@ static void build_rhct(GArray *table_data,
}
}
+/* MMU node structure */
+if (cpu->cfg.satp_mode.supported != 0) {
+satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
+mmu_offset = table_data->len - table.table_offset;
+build_append_int_noprefix(table_data, 2, 2);/* Type */
+build_append_int_noprefix(table_data, 8, 2);/* Length */
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+build_append_int_noprefix(table_data, 0, 1);/* Reserved */
+/* MMU Type */
+if (satp_mode_max == VM_1_10_SV57) {
+build_append_int_noprefix(table_data, 2, 1);/* Sv57 */
+} else if (satp_mode_max == VM_1_10_SV48) {
+build_append_int_noprefix(table_data, 1, 1);/* Sv48 */
+} else if (satp_mode_max == VM_1_10_SV39) {
+build_append_int_noprefix(table_data, 0, 1);/* Sv39 */
+} else {
+assert(1);
+}
+}
+
/* Hart Info Node */
for (int i = 0; i < arch_ids->len; i++) {
len = 16;
@@ -238,17 +264,25 @@ static void build_rhct(GArray *table_data,
num_offsets++;
}
+if (mmu_offset) {
+len += 4;
+num_offsets++;
+}
+
build_append_int_noprefix(table_data, len, 2);
build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
/* Number of offsets */
build_append_int_noprefix(table_data, num_offsets, 2);
build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
-
/* Offsets */
build_append_int_noprefix(table_data, isa_offset, 4);
if (cmo_offset) {
build_append_int_noprefix(table_data, cmo_offset, 4);
}
+
+if (mmu_offset) {
+build_append_int_noprefix(table_data, mmu_offset, 4);
+}
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v8 12/13] hw/riscv/virt-acpi-build.c: Add IO controllers and devices
Add basic IO controllers and devices like PCI, VirtIO and UART in the
ACPI namespace.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/Kconfig | 1 +
hw/riscv/virt-acpi-build.c | 79 --
2 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index b6a5eb4452..a50717be87 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -45,6 +45,7 @@ config RISCV_VIRT
select FW_CFG_DMA
select PLATFORM_BUS
select ACPI
+select ACPI_PCI
config SHAKTI_C
bool
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 86c38f7c2b..4d03a27efd 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -27,15 +27,18 @@
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/aml-build.h"
+#include "hw/acpi/pci.h"
#include "hw/acpi/utils.h"
+#include "hw/intc/riscv_aclint.h"
#include "hw/nvram/fw_cfg_acpi.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/riscv/virt.h"
+#include "hw/riscv/numa.h"
+#include "hw/virtio/virtio-acpi.h"
+#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/reset.h"
-#include "migration/vmstate.h"
-#include "hw/riscv/virt.h"
-#include "hw/riscv/numa.h"
-#include "hw/intc/riscv_aclint.h"
#define ACPI_BUILD_TABLE_SIZE 0x2
#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
@@ -132,6 +135,39 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState
*s)
}
}
+static void
+acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
+uint32_t uart_irq)
+{
+Aml *dev = aml_device("COM0");
+aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
+aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(uart_memmap->base,
+ uart_memmap->size, AML_READ_WRITE));
+aml_append(crs,
+aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, _irq, 1));
+aml_append(dev, aml_name_decl("_CRS", crs));
+
+Aml *pkg = aml_package(2);
+aml_append(pkg, aml_string("clock-frequency"));
+aml_append(pkg, aml_int(3686400));
+
+Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301");
+
+Aml *pkg1 = aml_package(1);
+aml_append(pkg1, pkg);
+
+Aml *package = aml_package(2);
+aml_append(package, UUID);
+aml_append(package, pkg1);
+
+aml_append(dev, aml_name_decl("_DSD", package));
+aml_append(scope, dev);
+}
+
/* RHCT Node[N] starts at offset 56 */
#define RHCT_NODE_ARRAY_OFFSET 56
@@ -310,6 +346,8 @@ static void build_dsdt(GArray *table_data,
RISCVVirtState *s)
{
Aml *scope, *dsdt;
+MachineState *ms = MACHINE(s);
+uint8_t socket_count;
const MemMapEntry *memmap = s->memmap;
AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id,
.oem_table_id = s->oem_table_id };
@@ -329,6 +367,29 @@ static void build_dsdt(GArray *table_data,
fw_cfg_acpi_dsdt_add(scope, [VIRT_FW_CFG]);
+socket_count = riscv_socket_count(ms);
+
+acpi_dsdt_add_uart(scope, [VIRT_UART0], UART0_IRQ);
+
+if (socket_count == 1) {
+virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
+ memmap[VIRT_VIRTIO].size,
+ VIRTIO_IRQ, 0, VIRTIO_COUNT);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ);
+} else if (socket_count == 2) {
+virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
+ memmap[VIRT_VIRTIO].size,
+ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
+ VIRTIO_COUNT);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES);
+} else {
+virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
+ memmap[VIRT_VIRTIO].size,
+ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
+ VIRTIO_COUNT);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES *
2);
+}
+
aml_append(dsdt, scope);
/* copy AML table into ACPI tables blob and patch header there */
@@ -465,6 +526,16 @@ static void virt_acpi_build(RISCVVirtState *s,
AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_rhct(tables_blob, tables->linker, s)
[PATCH v8 11/13] hw/riscv/virt: Update GPEX MMIO related properties
Update the GPEX host bridge properties related to MMIO ranges with
values set for the virt machine.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt.c | 47 -
include/hw/riscv/virt.h | 1 +
2 files changed, 33 insertions(+), 15 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 9e7629c51c..a7c4c3508e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1054,21 +1054,45 @@ static void create_fdt(RISCVVirtState *s, const
MemMapEntry *memmap)
}
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
- hwaddr ecam_base, hwaddr ecam_size,
- hwaddr mmio_base, hwaddr mmio_size,
- hwaddr high_mmio_base,
- hwaddr high_mmio_size,
- hwaddr pio_base,
- DeviceState *irqchip)
+ DeviceState *irqchip,
+ RISCVVirtState *s)
{
DeviceState *dev;
MemoryRegion *ecam_alias, *ecam_reg;
MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
+hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base;
+hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size;
+hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base;
+hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size;
+hwaddr high_mmio_base = virt_high_pcie_memmap.base;
+hwaddr high_mmio_size = virt_high_pcie_memmap.size;
+hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base;
+hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size;
qemu_irq irq;
int i;
dev = qdev_new(TYPE_GPEX_HOST);
+/* Set GPEX object properties for the virt machine */
+object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE,
+ecam_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE,
+ecam_size, NULL);
+object_property_set_uint(OBJECT(GPEX_HOST(dev)),
+ PCI_HOST_BELOW_4G_MMIO_BASE,
+ mmio_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)),
PCI_HOST_BELOW_4G_MMIO_SIZE,
+mmio_size, NULL);
+object_property_set_uint(OBJECT(GPEX_HOST(dev)),
+ PCI_HOST_ABOVE_4G_MMIO_BASE,
+ high_mmio_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)),
PCI_HOST_ABOVE_4G_MMIO_SIZE,
+high_mmio_size, NULL);
+object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE,
+pio_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE,
+pio_size, NULL);
+
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
ecam_alias = g_new0(MemoryRegion, 1);
@@ -1099,6 +1123,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion
*sys_mem,
gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
}
+GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus;
return dev;
}
@@ -1494,15 +1519,7 @@ static void virt_machine_init(MachineState *machine)
qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
}
-gpex_pcie_init(system_memory,
- memmap[VIRT_PCIE_ECAM].base,
- memmap[VIRT_PCIE_ECAM].size,
- memmap[VIRT_PCIE_MMIO].base,
- memmap[VIRT_PCIE_MMIO].size,
- virt_high_pcie_memmap.base,
- virt_high_pcie_memmap.size,
- memmap[VIRT_PCIE_PIO].base,
- pcie_irqchip);
+gpex_pcie_init(system_memory, pcie_irqchip, s);
create_platform_bus(s, mmio_irqchip);
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 5b03575ed3..f89790fd58 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -61,6 +61,7 @@ struct RISCVVirtState {
char *oem_table_id;
OnOffAuto acpi;
const MemMapEntry *memmap;
+struct GPEXHost *gpex_host;
};
enum {
--
2.39.2
[PATCH v8 03/13] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT
With common function to add virtio in DSDT created now, update microvm
code also to use it instead of duplicate code.
Suggested-by: Andrew Jones
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/i386/acpi-microvm.c | 15 ++-
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c
index 2909a73933..279da6b4aa 100644
--- a/hw/i386/acpi-microvm.c
+++ b/hw/i386/acpi-microvm.c
@@ -37,6 +37,7 @@
#include "hw/pci/pci.h"
#include "hw/pci/pcie_host.h"
#include "hw/usb/xhci.h"
+#include "hw/virtio/virtio-acpi.h"
#include "hw/virtio/virtio-mmio.h"
#include "hw/input/i8042.h"
@@ -77,19 +78,7 @@ static void acpi_dsdt_add_virtio(Aml *scope,
uint32_t irq = mms->virtio_irq_base + index;
hwaddr base = VIRTIO_MMIO_BASE + index * 512;
hwaddr size = 512;
-
-Aml *dev = aml_device("VR%02u", (unsigned)index);
-aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
-aml_append(dev, aml_name_decl("_UID", aml_int(index)));
-aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
-Aml *crs = aml_resource_template();
-aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
-aml_append(crs,
- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
- AML_EXCLUSIVE, , 1));
-aml_append(dev, aml_name_decl("_CRS", crs));
-aml_append(scope, dev);
+virtio_acpi_dsdt_add(scope, base, size, irq, index, 1);
}
}
}
--
2.39.2
[PATCH v8 10/13] hw/pci-host/gpex: Define properties for MMIO ranges
ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit
and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of
making these values machine specific, create properties for the GPEX
host bridge with default value 0. During initialization, the firmware
can initialize these properties with correct values for the platform.
This basically allows DSDT generator code independent of the machine
specific memory map accesses.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
Reviewed-by: Daniel Henrique Barboza
---
hw/pci-host/gpex-acpi.c| 13 +
hw/pci-host/gpex.c | 12
include/hw/pci-host/gpex.h | 28
3 files changed, 45 insertions(+), 8 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index 1092dc3b70..f69413ea2c 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -281,3 +281,16 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
crs_range_set_free(_range_set);
}
+
+void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq)
+{
+bool ambig;
+Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, );
+
+if (!obj || ambig) {
+return;
+}
+
+GPEX_HOST(obj)->gpex_cfg.irq = irq;
+acpi_dsdt_add_gpex(scope, _HOST(obj)->gpex_cfg);
+}
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
index a6752fac5e..41f4e73f6e 100644
--- a/hw/pci-host/gpex.c
+++ b/hw/pci-host/gpex.c
@@ -154,6 +154,18 @@ static Property gpex_host_properties[] = {
*/
DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost,
allow_unmapped_accesses, true),
+DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0),
+DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_PIO_SIZE, GPEXHost, gpex_cfg.pio.size, 0),
+DEFINE_PROP_UINT64(PCI_HOST_BELOW_4G_MMIO_BASE, GPEXHost,
+ gpex_cfg.mmio32.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MMIO_SIZE, GPEXHost,
+ gpex_cfg.mmio32.size, 0),
+DEFINE_PROP_UINT64(PCI_HOST_ABOVE_4G_MMIO_BASE, GPEXHost,
+ gpex_cfg.mmio64.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost,
+ gpex_cfg.mmio64.size, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h
index b0240bd768..dce883573b 100644
--- a/include/hw/pci-host/gpex.h
+++ b/include/hw/pci-host/gpex.h
@@ -40,6 +40,15 @@ struct GPEXRootState {
/*< public >*/
};
+struct GPEXConfig {
+MemMapEntry ecam;
+MemMapEntry mmio32;
+MemMapEntry mmio64;
+MemMapEntry pio;
+int irq;
+PCIBus *bus;
+};
+
struct GPEXHost {
/*< private >*/
PCIExpressHost parent_obj;
@@ -55,19 +64,22 @@ struct GPEXHost {
int irq_num[GPEX_NUM_IRQS];
bool allow_unmapped_accesses;
-};
-struct GPEXConfig {
-MemMapEntry ecam;
-MemMapEntry mmio32;
-MemMapEntry mmio64;
-MemMapEntry pio;
-int irq;
-PCIBus *bus;
+struct GPEXConfig gpex_cfg;
};
int gpex_set_irq_num(GPEXHost *s, int index, int gsi);
void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg);
+void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq);
+
+#define PCI_HOST_PIO_BASE "x-pio-base"
+#define PCI_HOST_PIO_SIZE "x-pio-size"
+#define PCI_HOST_ECAM_BASE "x-ecam-base"
+#define PCI_HOST_ECAM_SIZE "x-ecam-size"
+#define PCI_HOST_BELOW_4G_MMIO_BASE "x-below-4g-mmio-base"
+#define PCI_HOST_BELOW_4G_MMIO_SIZE "x-below-4g-mmio-size"
+#define PCI_HOST_ABOVE_4G_MMIO_BASE "x-above-4g-mmio-base"
+#define PCI_HOST_ABOVE_4G_MMIO_SIZE "x-above-4g-mmio-size"
#endif /* HW_GPEX_H */
--
2.39.2
[PATCH v8 06/13] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT
Add IMSIC structure in MADT when IMSIC is configured.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 3f9536356e..6bb21014fd 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -270,6 +270,19 @@ static void build_madt(GArray *table_data,
MachineClass *mc = MACHINE_GET_CLASS(s);
MachineState *ms = MACHINE(s);
const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
+uint8_t group_index_bits = imsic_num_bits(riscv_socket_count(ms));
+uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
+uint16_t imsic_max_hart_per_socket = 0;
+uint8_t hart_index_bits;
+uint8_t socket;
+
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
+imsic_max_hart_per_socket = s->soc[socket].num_harts;
+}
+}
+
+hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket);
AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id,
.oem_table_id = s->oem_table_id };
@@ -284,6 +297,28 @@ static void build_madt(GArray *table_data,
riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s);
}
+/* IMSIC */
+if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+/* IMSIC */
+build_append_int_noprefix(table_data, 0x19, 1); /* Type */
+build_append_int_noprefix(table_data, 16, 1); /* Length */
+build_append_int_noprefix(table_data, 1, 1);/* Version */
+build_append_int_noprefix(table_data, 0, 1);/* Reserved */
+build_append_int_noprefix(table_data, 0, 4);/* Flags */
+/* Number of supervisor mode Interrupt Identities */
+build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
+/* Number of guest mode Interrupt Identities */
+build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
+/* Guest Index Bits */
+build_append_int_noprefix(table_data, guest_index_bits, 1);
+/* Hart Index Bits */
+build_append_int_noprefix(table_data, hart_index_bits, 1);
+/* Group Index Bits */
+build_append_int_noprefix(table_data, group_index_bits, 1);
+/* Group Index Shift */
+build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1);
+}
+
acpi_table_end(linker, );
}
--
2.39.2
[PATCH v8 01/13] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location
RISC-V also needs to use the same code to create fw_cfg in DSDT. So,
avoid code duplication by moving the code in arm and riscv to a device
specific file.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/arm/virt-acpi-build.c | 19 ++-
hw/nvram/fw_cfg-acpi.c | 23 +++
hw/nvram/meson.build | 1 +
hw/riscv/virt-acpi-build.c | 19 ++-
include/hw/nvram/fw_cfg_acpi.h | 15 +++
5 files changed, 43 insertions(+), 34 deletions(-)
create mode 100644 hw/nvram/fw_cfg-acpi.c
create mode 100644 include/hw/nvram/fw_cfg_acpi.h
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 8bc35a483c..565af9b7ea 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -35,7 +35,7 @@
#include "target/arm/cpu.h"
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
-#include "hw/nvram/fw_cfg.h"
+#include "hw/nvram/fw_cfg_acpi.h"
#include "hw/acpi/bios-linker-loader.h"
#include "hw/acpi/aml-build.h"
#include "hw/acpi/utils.h"
@@ -94,21 +94,6 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry
*uart_memmap,
aml_append(scope, dev);
}
-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
-{
-Aml *dev = aml_device("FWCF");
-aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
-/* device present, functioning, decoding, not shown in UI */
-aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
-aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
-Aml *crs = aml_resource_template();
-aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
- fw_cfg_memmap->size, AML_READ_WRITE));
-aml_append(dev, aml_name_decl("_CRS", crs));
-aml_append(scope, dev);
-}
-
static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
{
Aml *dev, *crs;
@@ -864,7 +849,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
if (vmc->acpi_expose_flash) {
acpi_dsdt_add_flash(scope, [VIRT_FLASH]);
}
-acpi_dsdt_add_fw_cfg(scope, [VIRT_FW_CFG]);
+fw_cfg_acpi_dsdt_add(scope, [VIRT_FW_CFG]);
acpi_dsdt_add_virtio(scope, [VIRT_MMIO],
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
diff --git a/hw/nvram/fw_cfg-acpi.c b/hw/nvram/fw_cfg-acpi.c
new file mode 100644
index 00..4e48baeaa0
--- /dev/null
+++ b/hw/nvram/fw_cfg-acpi.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Add fw_cfg device in DSDT
+ *
+ */
+
+#include "hw/nvram/fw_cfg_acpi.h"
+#include "hw/acpi/aml-build.h"
+
+void fw_cfg_acpi_dsdt_add(Aml *scope, const MemMapEntry *fw_cfg_memmap)
+{
+Aml *dev = aml_device("FWCF");
+aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
+/* device present, functioning, decoding, not shown in UI */
+aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
+aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
+ fw_cfg_memmap->size, AML_READ_WRITE));
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(scope, dev);
+}
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
index 75e415b1a0..4996c72456 100644
--- a/hw/nvram/meson.build
+++ b/hw/nvram/meson.build
@@ -17,3 +17,4 @@ system_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true:
files(
system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
+specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c'))
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 7331248f59..d8772c2821 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -28,6 +28,7 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/aml-build.h"
#include "hw/acpi/utils.h"
+#include "hw/nvram/fw_cfg_acpi.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/reset.h"
@@ -97,22 +98,6 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
}
}
-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
-{
-Aml *dev = aml_device("FWCF");
-aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
-
-/* device present, fu
[PATCH v8 08/13] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT
When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the
block size for those extensions need to be communicated via CMO node in
RHCT. Add CMO node in RHCT if any of those CMO extensions are detected.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 64 +-
1 file changed, 56 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index ec49c8804b..506d487ede 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -140,6 +140,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState
*s)
* 5.2.36 RISC-V Hart Capabilities Table (RHCT)
* REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16
* https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
+ * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view
*/
static void build_rhct(GArray *table_data,
BIOSLinker *linker,
@@ -149,8 +150,8 @@ static void build_rhct(GArray *table_data,
MachineState *ms = MACHINE(s);
const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
size_t len, aligned_len;
-uint32_t isa_offset, num_rhct_nodes;
-RISCVCPU *cpu;
+uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
+RISCVCPU *cpu = >soc[0].harts[0];
char *isa;
AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -166,6 +167,9 @@ static void build_rhct(GArray *table_data,
/* ISA + N hart info */
num_rhct_nodes = 1 + ms->smp.cpus;
+if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
+num_rhct_nodes++;
+}
/* Number of RHCT nodes*/
build_append_int_noprefix(table_data, num_rhct_nodes, 4);
@@ -177,7 +181,6 @@ static void build_rhct(GArray *table_data,
isa_offset = table_data->len - table.table_offset;
build_append_int_noprefix(table_data, 0, 2); /* Type 0 */
-cpu = >soc[0].harts[0];
isa = riscv_isa_string(cpu);
len = 8 + strlen(isa) + 1;
aligned_len = (len % 2) ? (len + 1) : len;
@@ -193,14 +196,59 @@ static void build_rhct(GArray *table_data,
build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */
}
+/* CMO node */
+if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
+cmo_offset = table_data->len - table.table_offset;
+build_append_int_noprefix(table_data, 1, 2);/* Type */
+build_append_int_noprefix(table_data, 10, 2); /* Length */
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+build_append_int_noprefix(table_data, 0, 1);/* Reserved */
+
+/* CBOM block size */
+if (cpu->cfg.cbom_blocksize) {
+build_append_int_noprefix(table_data,
+ __builtin_ctz(cpu->cfg.cbom_blocksize),
+ 1);
+} else {
+build_append_int_noprefix(table_data, 0, 1);
+}
+
+/* CBOP block size */
+build_append_int_noprefix(table_data, 0, 1);
+
+/* CBOZ block size */
+if (cpu->cfg.cboz_blocksize) {
+build_append_int_noprefix(table_data,
+ __builtin_ctz(cpu->cfg.cboz_blocksize),
+ 1);
+} else {
+build_append_int_noprefix(table_data, 0, 1);
+}
+}
+
/* Hart Info Node */
for (int i = 0; i < arch_ids->len; i++) {
+len = 16;
+int num_offsets = 1;
build_append_int_noprefix(table_data, 0x, 2); /* Type */
-build_append_int_noprefix(table_data, 16, 2); /* Length */
-build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
-build_append_int_noprefix(table_data, 1, 2);/* Number of offsets */
-build_append_int_noprefix(table_data, i, 4);/* ACPI Processor UID
*/
-build_append_int_noprefix(table_data, isa_offset, 4); /* Offsets[0] */
+
+/* Length */
+if (cmo_offset) {
+len += 4;
+num_offsets++;
+}
+
+build_append_int_noprefix(table_data, len, 2);
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+/* Number of offsets */
+build_append_int_noprefix(table_data, num_offsets, 2);
+build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
+
+/* Offsets */
+build_append_int_noprefix(table_data, isa_offset, 4);
+if (cmo_offset) {
+build_append_int_noprefix(table_data, cmo_offset, 4);
+}
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v8 02/13] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location
RISC-V also needs to create the virtio in DSDT in the same way as ARM.
So, instead of duplicating the code, move this function to the device
specific file which is common across architectures.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/arm/virt-acpi-build.c| 32
hw/virtio/meson.build | 1 +
hw/virtio/virtio-acpi.c | 33 +
include/hw/virtio/virtio-acpi.h | 16
4 files changed, 54 insertions(+), 28 deletions(-)
create mode 100644 hw/virtio/virtio-acpi.c
create mode 100644 include/hw/virtio/virtio-acpi.h
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 565af9b7ea..510ab0dcca 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -58,6 +58,7 @@
#include "migration/vmstate.h"
#include "hw/acpi/ghes.h"
#include "hw/acpi/viot.h"
+#include "hw/virtio/virtio-acpi.h"
#define ARM_SPI_BASE 32
@@ -118,32 +119,6 @@ static void acpi_dsdt_add_flash(Aml *scope, const
MemMapEntry *flash_memmap)
aml_append(scope, dev);
}
-static void acpi_dsdt_add_virtio(Aml *scope,
- const MemMapEntry *virtio_mmio_memmap,
- uint32_t mmio_irq, int num)
-{
-hwaddr base = virtio_mmio_memmap->base;
-hwaddr size = virtio_mmio_memmap->size;
-int i;
-
-for (i = 0; i < num; i++) {
-uint32_t irq = mmio_irq + i;
-Aml *dev = aml_device("VR%02u", i);
-aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
-aml_append(dev, aml_name_decl("_UID", aml_int(i)));
-aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
-Aml *crs = aml_resource_template();
-aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
-aml_append(crs,
- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
- AML_EXCLUSIVE, , 1));
-aml_append(dev, aml_name_decl("_CRS", crs));
-aml_append(scope, dev);
-base += size;
-}
-}
-
static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
uint32_t irq, VirtMachineState *vms)
{
@@ -850,8 +825,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
acpi_dsdt_add_flash(scope, [VIRT_FLASH]);
}
fw_cfg_acpi_dsdt_add(scope, [VIRT_FW_CFG]);
-acpi_dsdt_add_virtio(scope, [VIRT_MMIO],
-(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
+virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size,
+ (irqmap[VIRT_MMIO] + ARM_SPI_BASE),
+ 0, NUM_VIRTIO_TRANSPORTS);
acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
if (vms->acpi_dev) {
build_ged_aml(scope, "\\_SB."GED_DEVICE,
diff --git a/hw/virtio/meson.build b/hw/virtio/meson.build
index c0055a7832..9d62097a21 100644
--- a/hw/virtio/meson.build
+++ b/hw/virtio/meson.build
@@ -79,3 +79,4 @@ system_ss.add(when: 'CONFIG_ALL', if_true:
files('virtio-stub.c'))
system_ss.add(files('virtio-hmp-cmds.c'))
specific_ss.add_all(when: 'CONFIG_VIRTIO', if_true: specific_virtio_ss)
+system_ss.add(when: 'CONFIG_ACPI', if_true: files('virtio-acpi.c'))
diff --git a/hw/virtio/virtio-acpi.c b/hw/virtio/virtio-acpi.c
new file mode 100644
index 00..e18cb38bdb
--- /dev/null
+++ b/hw/virtio/virtio-acpi.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * virtio ACPI Support
+ *
+ */
+
+#include "hw/virtio/virtio-acpi.h"
+#include "hw/acpi/aml-build.h"
+
+void virtio_acpi_dsdt_add(Aml *scope, const hwaddr base, const hwaddr size,
+ uint32_t mmio_irq, long int start_index, int num)
+{
+hwaddr virtio_base = base;
+uint32_t irq = mmio_irq;
+long int i;
+
+for (i = start_index; i < start_index + num; i++) {
+Aml *dev = aml_device("VR%02u", (unsigned)i);
+aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
+aml_append(dev, aml_name_decl("_UID", aml_int(i)));
+aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(virtio_base, size, AML_READ_WRITE));
+aml_append(crs,
+ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, , 1));
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(scope, dev);
+virtio_base += size;
+irq++;
+}
+}
diff --git a/include/hw/virtio/virtio-acpi.h b/include
[PATCH v8 04/13] hw/riscv: virt: Make few IMSIC macros and functions public
Some macros and static function related to IMSIC are defined in virt.c.
They are required in virt-acpi-build.c. So, make them public.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt.c | 25 +
include/hw/riscv/virt.h | 25 +
2 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d2eac24156..9e7629c51c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -38,7 +38,6 @@
#include "kvm/kvm_riscv.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/riscv_aplic.h"
-#include "hw/intc/riscv_imsic.h"
#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_test.h"
#include "hw/platform-bus.h"
@@ -54,28 +53,6 @@
#include "hw/acpi/aml-build.h"
#include "qapi/qapi-visit-common.h"
-/*
- * The virt machine physical address space used by some of the devices
- * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
- * number of CPUs, and number of IMSIC guest files.
- *
- * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
- * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
- * of virt machine physical address space.
- */
-
-#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
-#if VIRT_IMSIC_GROUP_MAX_SIZE < \
-IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
-#error "Can't accommodate single IMSIC group in address space"
-#endif
-
-#define VIRT_IMSIC_MAX_SIZE(VIRT_SOCKETS_MAX * \
-VIRT_IMSIC_GROUP_MAX_SIZE)
-#if 0x400 < VIRT_IMSIC_MAX_SIZE
-#error "Can't accommodate all IMSIC groups in address space"
-#endif
-
/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
static bool virt_use_kvm_aia(RISCVVirtState *s)
{
@@ -512,7 +489,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
g_free(plic_cells);
}
-static uint32_t imsic_num_bits(uint32_t count)
+uint32_t imsic_num_bits(uint32_t count)
{
uint32_t ret = 0;
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index e5c474b26e..5b03575ed3 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -23,6 +23,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/sysbus.h"
#include "hw/block/flash.h"
+#include "hw/intc/riscv_imsic.h"
#define VIRT_CPUS_MAX_BITS 9
#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
@@ -127,4 +128,28 @@ enum {
bool virt_is_acpi_enabled(RISCVVirtState *s);
void virt_acpi_setup(RISCVVirtState *vms);
+uint32_t imsic_num_bits(uint32_t count);
+
+/*
+ * The virt machine physical address space used by some of the devices
+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+ * number of CPUs, and number of IMSIC guest files.
+ *
+ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
+ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
+ * of virt machine physical address space.
+ */
+
+#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
+#if VIRT_IMSIC_GROUP_MAX_SIZE < \
+IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
+#error "Can't accomodate single IMSIC group in address space"
+#endif
+
+#define VIRT_IMSIC_MAX_SIZE(VIRT_SOCKETS_MAX * \
+VIRT_IMSIC_GROUP_MAX_SIZE)
+#if 0x400 < VIRT_IMSIC_MAX_SIZE
+#error "Can't accomodate all IMSIC groups in address space"
+#endif
+
#endif
--
2.39.2
[PATCH v8 00/13] RISC-V: ACPI: Enable AIA, PLIC and update RHCT
This series primarily enables external interrupt controllers (AIA and PLIC) in ACPI tables for RISC-V virt platform. It also updates RHCT with CMO and MMU related information. Below ECRs for these changes are approved by ASWG and will be available in next ACPI spec release. 1) MADT (AIA) - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing 2) RHCT - https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view?usp=sharing First two patches in this series are to migrate a couple of functions from ARM architecture to common code so that RISC-V doesn't need to duplicate the same. The patch set is based on Alistair's riscv-to-apply.next branch. These changes are also available in riscv_acpi_b2_v8 branch at: https://github.com/vlsunil/qemu/ Changes since v7: 1) Prefixed gpex property names with "x-" as per feedback from Michael Tsirkin. 2) Rebased to latest riscv-to-apply.next. Changes since v6: 1) Fixed the qtest failure issue reported by Daniel in PATCH 2. Changes since v5: 1) Fixed the issue in PATCH 2 reported by Daniel found when built with clang + --enable-debug. Changes since v4: 1) Updated copyright for new files as per SPDX format suggested by Drew. 2) Updated RINTC patch to avoid code duplication as suggested by Drew. 3) Moved mmu offset below cmo in MMU patch as suggested by Drew. 4) Updated tags. Changes since v3: 1) Addressed comments from Daniel and Drew. 2) Added a new patch in microvm to use common function for virtio in DSDT. 3) Rebased to latest riscv-to-apply.next branch and added tags. Changes since v2: 1) Rebased to latest riscv-to-apply.next branch which needed changing ext_icboz to ext_zicboz in CMO patch. 2) Fixed node type in MMU node. 3) Added latest tags. Changes since v1: 1) As per Igor's suggestion, migrated fw_cfg and virtio creation functions to device specific file instead of generic aml-build.c. Since ACPI is optional, new files are created and enabled for build only when CONFIG_ACPI is enabled. 2) As per Igor's suggestion, properties are added to the GPEX PCI host to indicate MMIO ranges. The platform fw can initialize these to appropriate values and the DSDT generator can fetch the information from the host bus itself. This makes the code generic instead of machine specific. 3) Added PLIC patch from Haibo. 4) Rebased to latest riscv-to-apply.next and added RB tags as appropriate. Sunil V L (13): hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location hw/arm/virt-acpi-build.c: Migrate virtio creation to common location hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT hw/riscv: virt: Make few IMSIC macros and functions public hw/riscv/virt-acpi-build.c: Add AIA support in RINTC hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT hw/riscv/virt-acpi-build.c: Add APLIC in the MADT hw/riscv/virt-acpi-build.c: Add CMO information in RHCT hw/riscv/virt-acpi-build.c: Add MMU node in RHCT hw/pci-host/gpex: Define properties for MMIO ranges hw/riscv/virt: Update GPEX MMIO related properties hw/riscv/virt-acpi-build.c: Add IO controllers and devices hw/riscv/virt-acpi-build.c: Add PLIC in MADT hw/arm/virt-acpi-build.c| 51 + hw/i386/acpi-microvm.c | 15 +- hw/nvram/fw_cfg-acpi.c | 23 +++ hw/nvram/meson.build| 1 + hw/pci-host/gpex-acpi.c | 13 ++ hw/pci-host/gpex.c | 12 ++ hw/riscv/Kconfig| 1 + hw/riscv/virt-acpi-build.c | 323 +--- hw/riscv/virt.c | 72 --- hw/virtio/meson.build | 1 + hw/virtio/virtio-acpi.c | 33 include/hw/nvram/fw_cfg_acpi.h | 15 ++ include/hw/pci-host/gpex.h | 28 ++- include/hw/riscv/virt.h | 26 +++ include/hw/virtio/virtio-acpi.h | 16 ++ 15 files changed, 499 insertions(+), 131 deletions(-) create mode 100644 hw/nvram/fw_cfg-acpi.c create mode 100644 hw/virtio/virtio-acpi.c create mode 100644 include/hw/nvram/fw_cfg_acpi.h create mode 100644 include/hw/virtio/virtio-acpi.h -- 2.39.2
Re: [PATCH 1/1] target/riscv: SMBIOS support for RISC-V virt machine
Hi Heinrich,
Thanks for the patch!.
On Mon, Dec 18, 2023 at 08:40:18AM +0100, Heinrich Schuchardt wrote:
> Generate SMBIOS tables for the RISC-V mach-virt.
> Add CONFIG_SMBIOS=y to the RISC-V default config.
>
> The implementation is based on the corresponding ARM and Loongson code.
>
> With the patch the following firmware tables are provided:
>
> etc/smbios/smbios-anchor
> etc/smbios/smbios-tables
>
> Booting Ubuntu 23.10 via EDK II allowed displaying the SMBIOS table using
> the dmidecode command:
>
> Handle 0x0100, DMI type 1, 27 bytes
> System Information
> Manufacturer: QEMU
> Product Name: QEMU Virtual Machine
> Version: virt
> ...
>
> Signed-off-by: Heinrich Schuchardt
> ---
> hw/riscv/Kconfig | 1 +
> hw/riscv/virt.c | 36
> 2 files changed, 37 insertions(+)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index b6a5eb4452..1e11ac9432 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -41,6 +41,7 @@ config RISCV_VIRT
> select RISCV_IMSIC
> select SIFIVE_PLIC
> select SIFIVE_TEST
> +select SMBIOS
> select VIRTIO_MMIO
> select FW_CFG_DMA
> select PLATFORM_BUS
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index d2eac24156..6c27cb5330 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -36,6 +36,7 @@
> #include "hw/riscv/boot.h"
> #include "hw/riscv/numa.h"
> #include "kvm/kvm_riscv.h"
> +#include "hw/firmware/smbios.h"
> #include "hw/intc/riscv_aclint.h"
> #include "hw/intc/riscv_aplic.h"
> #include "hw/intc/riscv_imsic.h"
> @@ -1249,6 +1250,39 @@ static void create_platform_bus(RISCVVirtState *s,
> DeviceState *irqchip)
> sysbus_mmio_get_region(sysbus, 0));
> }
>
> +static void virt_build_smbios(RISCVVirtState *s)
> +{
Can we avoid duplicating this function which exists in other
architectures?
Thanks,
Sunil
Re: [PATCH v4 0/3] hw/riscv/virt: pflash improvements
On Mon, Nov 20, 2023 at 02:29:28PM +, Andrea Bolognani wrote: > On Fri, May 26, 2023 at 11:10:12AM +0200, Andrew Jones wrote: > > On Fri, May 26, 2023 at 04:42:57AM -0400, Andrea Bolognani wrote: > > > On Fri, May 26, 2023 at 10:34:36AM +0200, Andrew Jones wrote: > > > > On Fri, May 26, 2023 at 03:49:11AM -0400, Andrea Bolognani wrote: > > > > > So, are edk2 users the only ones who would (temporarily) need to > > > > > manually turn ACPI off if virt-manager started enabling it by > > > > > default? > > > > > > > > I assume so, but I'm not tracking firmware status. If the firmware > > > > doesn't extract the ACPI tables from QEMU and present them to the > > > > guest (afaik only edk2 does that), then the guest kernel falls back > > > > to DT, which is why it's working for you. > > > > > > > > I suppose we should wait until Linux merges the ACPI patches, before > > > > adding RISC-V to the libvirt capabilities ACPI list. > > > > > > That sounds reasonable to me, but note that 1) the libvirt change > > > might take a while to propagate to distros and 2) someone will have > > > to remind me to prepare such a patch when the time comes ;) > > > > Initial ACPI support will probably be merged for 6.4. So maybe it is > > time to get the libvirt side of things going. > > Randomly remembered about this. Did ACPI support make it into 6.4 > after all? Is now a good time to change libvirt? > Hi Andrea, Not yet. While basic ACPI changes are merged, the interrupt controller support is still going on. Looks like it will take few merge windows to get ACPI fully supported. So, we still need to wait for libvirt change. Thanks! Sunil
Re: [PATCH v6 00/13] RISC-V: ACPI: Enable AIA, PLIC and update RHCT
On Thu, Nov 02, 2023 at 06:00:22PM -0300, Daniel Henrique Barboza wrote: > Sunil, > > > While doing unrelated work (running Gitlab on my series built on top of > current riscv-to-apply.next), I hit the following error: > > https://gitlab.com/danielhb/qemu/-/jobs/5448178994 > > == > > 4/257 ERROR:../tests/qtest/bios-tables-test.c:535:test_acpi_asl: assertion > failed: (all_tables_match) ERROR > 4/257 qemu:qtest+qtest-i386 / qtest-i386/bios-tables-test > ERROR 7.77s killed by signal 6 SIGABRT > > > > G_TEST_DBUS_DAEMON=/builds/danielhb/qemu/tests/dbus-vmstate-daemon.sh > > > > PYTHON=/builds/danielhb/qemu/build/pyvenv/bin/python3 > > > > MALLOC_PERTURB_=159 QTEST_QEMU_BINARY=./qemu-system-i386 > > > > /builds/danielhb/qemu/build/tests/qtest/bios-tables-test --tap -k > > acpi-test: Warning! DSDT binary file mismatch. Actual [aml:/tmp/aml-IOYVD2], > Expected [aml:tests/data/acpi/microvm/DSDT]. > See source file tests/qtest/bios-tables-test.c for instructions on how to > update expected files. > to see ASL diff between mismatched files install IASL, rebuild QEMU from > scratch and re-run tests with V=1 environment variable set** > ERROR:../tests/qtest/bios-tables-test.c:535:test_acpi_asl: assertion failed: > (all_tables_match) > (test program exited with status code -6) > > (...) > > Summary of Failures: > 4571 4/257 qemu:qtest+qtest-i386 / qtest-i386/bios-tables-test > ERROR 7.77s killed by signal 6 SIGABRT > 4572 7/257 qemu:qtest+qtest-aarch64 / qtest-aarch64/bios-tables-test > ERROR 66.00s killed by signal 6 SIGABRT > 4573 Ok: 247 > 4574 Expected Fail: 0 > 4575 Fail: 2 > 4576 Unexpected Pass:0 > 4577 Skipped:8 > 4578 Timeout:0 > > == > Thanks! Daniel. I sent v7 with this issue fixed. With v7, here is the qtest report I got. $ make check-qtest-i386 V=1 ... Ok: 60 Expected Fail: 0 Fail: 0 Unexpected Pass:0 Skipped:3 Timeout:0 $ make check-qtest-aarch64 V=1 ... Ok: 20 Expected Fail: 0 Fail: 0 Unexpected Pass:0 Skipped:2 Timeout:0 $ make check ... Ok: 765 Expected Fail: 0 Fail: 0 Unexpected Pass:0 Skipped:71 Timeout:0 While I don't see any failures now, there are some tests skipped which look expected. Let me know if I need to run any other tests. Thanks! Sunil
[PATCH v7 06/13] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT
Add IMSIC structure in MADT when IMSIC is configured.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 3f9536356e..6bb21014fd 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -270,6 +270,19 @@ static void build_madt(GArray *table_data,
MachineClass *mc = MACHINE_GET_CLASS(s);
MachineState *ms = MACHINE(s);
const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
+uint8_t group_index_bits = imsic_num_bits(riscv_socket_count(ms));
+uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
+uint16_t imsic_max_hart_per_socket = 0;
+uint8_t hart_index_bits;
+uint8_t socket;
+
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
+imsic_max_hart_per_socket = s->soc[socket].num_harts;
+}
+}
+
+hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket);
AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id,
.oem_table_id = s->oem_table_id };
@@ -284,6 +297,28 @@ static void build_madt(GArray *table_data,
riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s);
}
+/* IMSIC */
+if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+/* IMSIC */
+build_append_int_noprefix(table_data, 0x19, 1); /* Type */
+build_append_int_noprefix(table_data, 16, 1); /* Length */
+build_append_int_noprefix(table_data, 1, 1);/* Version */
+build_append_int_noprefix(table_data, 0, 1);/* Reserved */
+build_append_int_noprefix(table_data, 0, 4);/* Flags */
+/* Number of supervisor mode Interrupt Identities */
+build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
+/* Number of guest mode Interrupt Identities */
+build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
+/* Guest Index Bits */
+build_append_int_noprefix(table_data, guest_index_bits, 1);
+/* Hart Index Bits */
+build_append_int_noprefix(table_data, hart_index_bits, 1);
+/* Group Index Bits */
+build_append_int_noprefix(table_data, group_index_bits, 1);
+/* Group Index Shift */
+build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1);
+}
+
acpi_table_end(linker, );
}
--
2.39.2
[PATCH v7 13/13] hw/riscv/virt-acpi-build.c: Add PLIC in MADT
Add PLIC structures for each socket in the MADT when system is
configured with PLIC as the external interrupt controller.
Signed-off-by: Haibo Xu
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 4d03a27efd..d4a02579d6 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -94,6 +94,12 @@ static void riscv_acpi_madt_add_rintc(uint32_t uid,
arch_ids->cpus[uid].props.node_id,
local_cpu_id),
4);
+} else if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+build_append_int_noprefix(entry,
+ ACPI_BUILD_INTC_ID(
+ arch_ids->cpus[uid].props.node_id,
+ 2 * local_cpu_id + 1),
+ 4);
} else {
build_append_int_noprefix(entry, 0, 4);
}
@@ -494,6 +500,29 @@ static void build_madt(GArray *table_data,
build_append_int_noprefix(table_data,
s->memmap[VIRT_APLIC_S].size, 4);
}
+} else {
+/* PLICs */
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+aplic_addr = s->memmap[VIRT_PLIC].base +
+ s->memmap[VIRT_PLIC].size * socket;
+gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+build_append_int_noprefix(table_data, 0x1B, 1); /* Type */
+build_append_int_noprefix(table_data, 36, 1); /* Length */
+build_append_int_noprefix(table_data, 1, 1); /* Version */
+build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */
+build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */
+/* Total External Interrupt Sources Supported */
+build_append_int_noprefix(table_data,
+ VIRT_IRQCHIP_NUM_SOURCES - 1, 2);
+build_append_int_noprefix(table_data, 0, 2); /* Max Priority */
+build_append_int_noprefix(table_data, 0, 4); /* Flags */
+/* PLIC Size */
+build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size,
4);
+/* PLIC Address */
+build_append_int_noprefix(table_data, aplic_addr, 8);
+/* Global System Interrupt Vector Base */
+build_append_int_noprefix(table_data, gsi_base, 4);
+}
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v7 07/13] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT
Add APLIC structures for each socket in the MADT when system is configured
with APLIC as the external wired interrupt controller.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 6bb21014fd..ec49c8804b 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -274,6 +274,8 @@ static void build_madt(GArray *table_data,
uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
uint16_t imsic_max_hart_per_socket = 0;
uint8_t hart_index_bits;
+uint64_t aplic_addr;
+uint32_t gsi_base;
uint8_t socket;
for (socket = 0; socket < riscv_socket_count(ms); socket++) {
@@ -319,6 +321,38 @@ static void build_madt(GArray *table_data,
build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1);
}
+if (s->aia_type != VIRT_AIA_TYPE_NONE) {
+/* APLICs */
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+aplic_addr = s->memmap[VIRT_APLIC_S].base +
+ s->memmap[VIRT_APLIC_S].size * socket;
+gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+build_append_int_noprefix(table_data, 0x1A, 1);/* Type */
+build_append_int_noprefix(table_data, 36, 1); /* Length */
+build_append_int_noprefix(table_data, 1, 1); /* Version */
+build_append_int_noprefix(table_data, socket, 1); /* APLIC ID */
+build_append_int_noprefix(table_data, 0, 4); /* Flags */
+build_append_int_noprefix(table_data, 0, 8); /* Hardware ID
*/
+/* Number of IDCs */
+if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
+build_append_int_noprefix(table_data,
+ s->soc[socket].num_harts,
+ 2);
+} else {
+build_append_int_noprefix(table_data, 0, 2);
+}
+/* Total External Interrupt Sources Supported */
+build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_SOURCES, 2);
+/* Global System Interrupt Base */
+build_append_int_noprefix(table_data, gsi_base, 4);
+/* APLIC Address */
+build_append_int_noprefix(table_data, aplic_addr, 8);
+/* APLIC size */
+build_append_int_noprefix(table_data,
+ s->memmap[VIRT_APLIC_S].size, 4);
+}
+}
+
acpi_table_end(linker, );
}
--
2.39.2
[PATCH v7 12/13] hw/riscv/virt-acpi-build.c: Add IO controllers and devices
Add basic IO controllers and devices like PCI, VirtIO and UART in the
ACPI namespace.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/Kconfig | 1 +
hw/riscv/virt-acpi-build.c | 79 --
2 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index b6a5eb4452..a50717be87 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -45,6 +45,7 @@ config RISCV_VIRT
select FW_CFG_DMA
select PLATFORM_BUS
select ACPI
+select ACPI_PCI
config SHAKTI_C
bool
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 86c38f7c2b..4d03a27efd 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -27,15 +27,18 @@
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/aml-build.h"
+#include "hw/acpi/pci.h"
#include "hw/acpi/utils.h"
+#include "hw/intc/riscv_aclint.h"
#include "hw/nvram/fw_cfg_acpi.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/riscv/virt.h"
+#include "hw/riscv/numa.h"
+#include "hw/virtio/virtio-acpi.h"
+#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/reset.h"
-#include "migration/vmstate.h"
-#include "hw/riscv/virt.h"
-#include "hw/riscv/numa.h"
-#include "hw/intc/riscv_aclint.h"
#define ACPI_BUILD_TABLE_SIZE 0x2
#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
@@ -132,6 +135,39 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState
*s)
}
}
+static void
+acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
+uint32_t uart_irq)
+{
+Aml *dev = aml_device("COM0");
+aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
+aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(uart_memmap->base,
+ uart_memmap->size, AML_READ_WRITE));
+aml_append(crs,
+aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, _irq, 1));
+aml_append(dev, aml_name_decl("_CRS", crs));
+
+Aml *pkg = aml_package(2);
+aml_append(pkg, aml_string("clock-frequency"));
+aml_append(pkg, aml_int(3686400));
+
+Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301");
+
+Aml *pkg1 = aml_package(1);
+aml_append(pkg1, pkg);
+
+Aml *package = aml_package(2);
+aml_append(package, UUID);
+aml_append(package, pkg1);
+
+aml_append(dev, aml_name_decl("_DSD", package));
+aml_append(scope, dev);
+}
+
/* RHCT Node[N] starts at offset 56 */
#define RHCT_NODE_ARRAY_OFFSET 56
@@ -310,6 +346,8 @@ static void build_dsdt(GArray *table_data,
RISCVVirtState *s)
{
Aml *scope, *dsdt;
+MachineState *ms = MACHINE(s);
+uint8_t socket_count;
const MemMapEntry *memmap = s->memmap;
AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id,
.oem_table_id = s->oem_table_id };
@@ -329,6 +367,29 @@ static void build_dsdt(GArray *table_data,
fw_cfg_acpi_dsdt_add(scope, [VIRT_FW_CFG]);
+socket_count = riscv_socket_count(ms);
+
+acpi_dsdt_add_uart(scope, [VIRT_UART0], UART0_IRQ);
+
+if (socket_count == 1) {
+virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
+ memmap[VIRT_VIRTIO].size,
+ VIRTIO_IRQ, 0, VIRTIO_COUNT);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ);
+} else if (socket_count == 2) {
+virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
+ memmap[VIRT_VIRTIO].size,
+ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
+ VIRTIO_COUNT);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES);
+} else {
+virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
+ memmap[VIRT_VIRTIO].size,
+ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
+ VIRTIO_COUNT);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES *
2);
+}
+
aml_append(dsdt, scope);
/* copy AML table into ACPI tables blob and patch header there */
@@ -465,6 +526,16 @@ static void virt_acpi_build(RISCVVirtState *s,
AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_rhct(tables_blob, tables->linker, s)
[PATCH v7 10/13] hw/pci-host/gpex: Define properties for MMIO ranges
ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit
and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of
making these values machine specific, create properties for the GPEX
host bridge with default value 0. During initialization, the firmware
can initialize these properties with correct values for the platform.
This basically allows DSDT generator code independent of the machine
specific memory map accesses.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
Reviewed-by: Daniel Henrique Barboza
---
hw/pci-host/gpex-acpi.c| 13 +
hw/pci-host/gpex.c | 12
include/hw/pci-host/gpex.h | 28
3 files changed, 45 insertions(+), 8 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index 1092dc3b70..f69413ea2c 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -281,3 +281,16 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
crs_range_set_free(_range_set);
}
+
+void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq)
+{
+bool ambig;
+Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, );
+
+if (!obj || ambig) {
+return;
+}
+
+GPEX_HOST(obj)->gpex_cfg.irq = irq;
+acpi_dsdt_add_gpex(scope, _HOST(obj)->gpex_cfg);
+}
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
index a6752fac5e..41f4e73f6e 100644
--- a/hw/pci-host/gpex.c
+++ b/hw/pci-host/gpex.c
@@ -154,6 +154,18 @@ static Property gpex_host_properties[] = {
*/
DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost,
allow_unmapped_accesses, true),
+DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0),
+DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_PIO_SIZE, GPEXHost, gpex_cfg.pio.size, 0),
+DEFINE_PROP_UINT64(PCI_HOST_BELOW_4G_MMIO_BASE, GPEXHost,
+ gpex_cfg.mmio32.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MMIO_SIZE, GPEXHost,
+ gpex_cfg.mmio32.size, 0),
+DEFINE_PROP_UINT64(PCI_HOST_ABOVE_4G_MMIO_BASE, GPEXHost,
+ gpex_cfg.mmio64.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost,
+ gpex_cfg.mmio64.size, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h
index b0240bd768..441c6b8b20 100644
--- a/include/hw/pci-host/gpex.h
+++ b/include/hw/pci-host/gpex.h
@@ -40,6 +40,15 @@ struct GPEXRootState {
/*< public >*/
};
+struct GPEXConfig {
+MemMapEntry ecam;
+MemMapEntry mmio32;
+MemMapEntry mmio64;
+MemMapEntry pio;
+int irq;
+PCIBus *bus;
+};
+
struct GPEXHost {
/*< private >*/
PCIExpressHost parent_obj;
@@ -55,19 +64,22 @@ struct GPEXHost {
int irq_num[GPEX_NUM_IRQS];
bool allow_unmapped_accesses;
-};
-struct GPEXConfig {
-MemMapEntry ecam;
-MemMapEntry mmio32;
-MemMapEntry mmio64;
-MemMapEntry pio;
-int irq;
-PCIBus *bus;
+struct GPEXConfig gpex_cfg;
};
int gpex_set_irq_num(GPEXHost *s, int index, int gsi);
void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg);
+void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq);
+
+#define PCI_HOST_PIO_BASE "pio-base"
+#define PCI_HOST_PIO_SIZE "pio-size"
+#define PCI_HOST_ECAM_BASE "ecam-base"
+#define PCI_HOST_ECAM_SIZE "ecam-size"
+#define PCI_HOST_BELOW_4G_MMIO_BASE "below-4g-mmio-base"
+#define PCI_HOST_BELOW_4G_MMIO_SIZE "below-4g-mmio-size"
+#define PCI_HOST_ABOVE_4G_MMIO_BASE "above-4g-mmio-base"
+#define PCI_HOST_ABOVE_4G_MMIO_SIZE "above-4g-mmio-size"
#endif /* HW_GPEX_H */
--
2.39.2
[PATCH v7 03/13] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT
With common function to add virtio in DSDT created now, update microvm
code also to use it instead of duplicate code.
Suggested-by: Andrew Jones
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/i386/acpi-microvm.c | 15 ++-
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c
index 2909a73933..279da6b4aa 100644
--- a/hw/i386/acpi-microvm.c
+++ b/hw/i386/acpi-microvm.c
@@ -37,6 +37,7 @@
#include "hw/pci/pci.h"
#include "hw/pci/pcie_host.h"
#include "hw/usb/xhci.h"
+#include "hw/virtio/virtio-acpi.h"
#include "hw/virtio/virtio-mmio.h"
#include "hw/input/i8042.h"
@@ -77,19 +78,7 @@ static void acpi_dsdt_add_virtio(Aml *scope,
uint32_t irq = mms->virtio_irq_base + index;
hwaddr base = VIRTIO_MMIO_BASE + index * 512;
hwaddr size = 512;
-
-Aml *dev = aml_device("VR%02u", (unsigned)index);
-aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
-aml_append(dev, aml_name_decl("_UID", aml_int(index)));
-aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
-Aml *crs = aml_resource_template();
-aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
-aml_append(crs,
- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
- AML_EXCLUSIVE, , 1));
-aml_append(dev, aml_name_decl("_CRS", crs));
-aml_append(scope, dev);
+virtio_acpi_dsdt_add(scope, base, size, irq, index, 1);
}
}
}
--
2.39.2
[PATCH v7 09/13] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT
MMU type information is available via MMU node in RHCT. Add this node in
RHCT.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 36 +++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 506d487ede..86c38f7c2b 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -152,6 +152,8 @@ static void build_rhct(GArray *table_data,
size_t len, aligned_len;
uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
RISCVCPU *cpu = >soc[0].harts[0];
+uint32_t mmu_offset = 0;
+uint8_t satp_mode_max;
char *isa;
AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -171,6 +173,10 @@ static void build_rhct(GArray *table_data,
num_rhct_nodes++;
}
+if (cpu->cfg.satp_mode.supported != 0) {
+num_rhct_nodes++;
+}
+
/* Number of RHCT nodes*/
build_append_int_noprefix(table_data, num_rhct_nodes, 4);
@@ -226,6 +232,26 @@ static void build_rhct(GArray *table_data,
}
}
+/* MMU node structure */
+if (cpu->cfg.satp_mode.supported != 0) {
+satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
+mmu_offset = table_data->len - table.table_offset;
+build_append_int_noprefix(table_data, 2, 2);/* Type */
+build_append_int_noprefix(table_data, 8, 2);/* Length */
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+build_append_int_noprefix(table_data, 0, 1);/* Reserved */
+/* MMU Type */
+if (satp_mode_max == VM_1_10_SV57) {
+build_append_int_noprefix(table_data, 2, 1);/* Sv57 */
+} else if (satp_mode_max == VM_1_10_SV48) {
+build_append_int_noprefix(table_data, 1, 1);/* Sv48 */
+} else if (satp_mode_max == VM_1_10_SV39) {
+build_append_int_noprefix(table_data, 0, 1);/* Sv39 */
+} else {
+assert(1);
+}
+}
+
/* Hart Info Node */
for (int i = 0; i < arch_ids->len; i++) {
len = 16;
@@ -238,17 +264,25 @@ static void build_rhct(GArray *table_data,
num_offsets++;
}
+if (mmu_offset) {
+len += 4;
+num_offsets++;
+}
+
build_append_int_noprefix(table_data, len, 2);
build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
/* Number of offsets */
build_append_int_noprefix(table_data, num_offsets, 2);
build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
-
/* Offsets */
build_append_int_noprefix(table_data, isa_offset, 4);
if (cmo_offset) {
build_append_int_noprefix(table_data, cmo_offset, 4);
}
+
+if (mmu_offset) {
+build_append_int_noprefix(table_data, mmu_offset, 4);
+}
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v7 11/13] hw/riscv/virt: Update GPEX MMIO related properties
Update the GPEX host bridge properties related to MMIO ranges with
values set for the virt machine.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt.c | 47 -
include/hw/riscv/virt.h | 1 +
2 files changed, 33 insertions(+), 15 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 085654ab2f..e64886a4d8 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1049,21 +1049,45 @@ static void create_fdt(RISCVVirtState *s, const
MemMapEntry *memmap)
}
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
- hwaddr ecam_base, hwaddr ecam_size,
- hwaddr mmio_base, hwaddr mmio_size,
- hwaddr high_mmio_base,
- hwaddr high_mmio_size,
- hwaddr pio_base,
- DeviceState *irqchip)
+ DeviceState *irqchip,
+ RISCVVirtState *s)
{
DeviceState *dev;
MemoryRegion *ecam_alias, *ecam_reg;
MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
+hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base;
+hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size;
+hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base;
+hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size;
+hwaddr high_mmio_base = virt_high_pcie_memmap.base;
+hwaddr high_mmio_size = virt_high_pcie_memmap.size;
+hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base;
+hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size;
qemu_irq irq;
int i;
dev = qdev_new(TYPE_GPEX_HOST);
+/* Set GPEX object properties for the virt machine */
+object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE,
+ecam_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE,
+ecam_size, NULL);
+object_property_set_uint(OBJECT(GPEX_HOST(dev)),
+ PCI_HOST_BELOW_4G_MMIO_BASE,
+ mmio_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)),
PCI_HOST_BELOW_4G_MMIO_SIZE,
+mmio_size, NULL);
+object_property_set_uint(OBJECT(GPEX_HOST(dev)),
+ PCI_HOST_ABOVE_4G_MMIO_BASE,
+ high_mmio_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)),
PCI_HOST_ABOVE_4G_MMIO_SIZE,
+high_mmio_size, NULL);
+object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE,
+pio_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE,
+pio_size, NULL);
+
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
ecam_alias = g_new0(MemoryRegion, 1);
@@ -1094,6 +1118,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion
*sys_mem,
gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
}
+GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus;
return dev;
}
@@ -1492,15 +1517,7 @@ static void virt_machine_init(MachineState *machine)
qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
}
-gpex_pcie_init(system_memory,
- memmap[VIRT_PCIE_ECAM].base,
- memmap[VIRT_PCIE_ECAM].size,
- memmap[VIRT_PCIE_MMIO].base,
- memmap[VIRT_PCIE_MMIO].size,
- virt_high_pcie_memmap.base,
- virt_high_pcie_memmap.size,
- memmap[VIRT_PCIE_PIO].base,
- pcie_irqchip);
+gpex_pcie_init(system_memory, pcie_irqchip, s);
create_platform_bus(s, mmio_irqchip);
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 5b03575ed3..f89790fd58 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -61,6 +61,7 @@ struct RISCVVirtState {
char *oem_table_id;
OnOffAuto acpi;
const MemMapEntry *memmap;
+struct GPEXHost *gpex_host;
};
enum {
--
2.39.2
[PATCH v7 04/13] hw/riscv: virt: Make few IMSIC macros and functions public
Some macros and static function related to IMSIC are defined in virt.c.
They are required in virt-acpi-build.c. So, make them public.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt.c | 25 +
include/hw/riscv/virt.h | 25 +
2 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 1732c42915..085654ab2f 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -38,7 +38,6 @@
#include "kvm/kvm_riscv.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/riscv_aplic.h"
-#include "hw/intc/riscv_imsic.h"
#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_test.h"
#include "hw/platform-bus.h"
@@ -54,28 +53,6 @@
#include "hw/acpi/aml-build.h"
#include "qapi/qapi-visit-common.h"
-/*
- * The virt machine physical address space used by some of the devices
- * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
- * number of CPUs, and number of IMSIC guest files.
- *
- * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
- * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
- * of virt machine physical address space.
- */
-
-#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
-#if VIRT_IMSIC_GROUP_MAX_SIZE < \
-IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
-#error "Can't accommodate single IMSIC group in address space"
-#endif
-
-#define VIRT_IMSIC_MAX_SIZE(VIRT_SOCKETS_MAX * \
-VIRT_IMSIC_GROUP_MAX_SIZE)
-#if 0x400 < VIRT_IMSIC_MAX_SIZE
-#error "Can't accommodate all IMSIC groups in address space"
-#endif
-
/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
static bool virt_use_kvm_aia(RISCVVirtState *s)
{
@@ -512,7 +489,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
g_free(plic_cells);
}
-static uint32_t imsic_num_bits(uint32_t count)
+uint32_t imsic_num_bits(uint32_t count)
{
uint32_t ret = 0;
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index e5c474b26e..5b03575ed3 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -23,6 +23,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/sysbus.h"
#include "hw/block/flash.h"
+#include "hw/intc/riscv_imsic.h"
#define VIRT_CPUS_MAX_BITS 9
#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
@@ -127,4 +128,28 @@ enum {
bool virt_is_acpi_enabled(RISCVVirtState *s);
void virt_acpi_setup(RISCVVirtState *vms);
+uint32_t imsic_num_bits(uint32_t count);
+
+/*
+ * The virt machine physical address space used by some of the devices
+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+ * number of CPUs, and number of IMSIC guest files.
+ *
+ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
+ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
+ * of virt machine physical address space.
+ */
+
+#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
+#if VIRT_IMSIC_GROUP_MAX_SIZE < \
+IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
+#error "Can't accomodate single IMSIC group in address space"
+#endif
+
+#define VIRT_IMSIC_MAX_SIZE(VIRT_SOCKETS_MAX * \
+VIRT_IMSIC_GROUP_MAX_SIZE)
+#if 0x400 < VIRT_IMSIC_MAX_SIZE
+#error "Can't accomodate all IMSIC groups in address space"
+#endif
+
#endif
--
2.39.2
[PATCH v7 00/13] RISC-V: ACPI: Enable AIA, PLIC and update RHCT
This series primarily enables external interrupt controllers (AIA and PLIC) in ACPI tables for RISC-V virt platform. It also updates RHCT with CMO and MMU related information. Below ECRs for these changes are approved by ASWG and will be available in next ACPI spec release. 1) MADT (AIA) - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing 2) RHCT - https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view?usp=sharing First two patches in this series are to migrate a couple of functions from ARM architecture to common code so that RISC-V doesn't need to duplicate the same. The patch set is based on Alistair's riscv-to-apply.next branch. These changes are also available in riscv_acpi_b2_v7 branch at: https://github.com/vlsunil/qemu/ Changes since v6: 1) Fixed the qtest failure issue reported by Daniel in PATCH 2. Changes since v5: 1) Fixed the issue in PATCH 2 reported by Daniel found when built with clang + --enable-debug. Changes since v4: 1) Updated copyright for new files as per SPDX format suggested by Drew. 2) Updated RINTC patch to avoid code duplication as suggested by Drew. 3) Moved mmu offset below cmo in MMU patch as suggested by Drew. 4) Updated tags. Changes since v3: 1) Addressed comments from Daniel and Drew. 2) Added a new patch in microvm to use common function for virtio in DSDT. 3) Rebased to latest riscv-to-apply.next branch and added tags. Changes since v2: 1) Rebased to latest riscv-to-apply.next branch which needed changing ext_icboz to ext_zicboz in CMO patch. 2) Fixed node type in MMU node. 3) Added latest tags. Changes since v1: 1) As per Igor's suggestion, migrated fw_cfg and virtio creation functions to device specific file instead of generic aml-build.c. Since ACPI is optional, new files are created and enabled for build only when CONFIG_ACPI is enabled. 2) As per Igor's suggestion, properties are added to the GPEX PCI host to indicate MMIO ranges. The platform fw can initialize these to appropriate values and the DSDT generator can fetch the information from the host bus itself. This makes the code generic instead of machine specific. 3) Added PLIC patch from Haibo. 4) Rebased to latest riscv-to-apply.next and added RB tags as appropriate. Sunil V L (13): hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location hw/arm/virt-acpi-build.c: Migrate virtio creation to common location hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT hw/riscv: virt: Make few IMSIC macros and functions public hw/riscv/virt-acpi-build.c: Add AIA support in RINTC hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT hw/riscv/virt-acpi-build.c: Add APLIC in the MADT hw/riscv/virt-acpi-build.c: Add CMO information in RHCT hw/riscv/virt-acpi-build.c: Add MMU node in RHCT hw/pci-host/gpex: Define properties for MMIO ranges hw/riscv/virt: Update GPEX MMIO related properties hw/riscv/virt-acpi-build.c: Add IO controllers and devices hw/riscv/virt-acpi-build.c: Add PLIC in MADT hw/arm/virt-acpi-build.c| 51 + hw/i386/acpi-microvm.c | 15 +- hw/nvram/fw_cfg-acpi.c | 23 +++ hw/nvram/meson.build| 1 + hw/pci-host/gpex-acpi.c | 13 ++ hw/pci-host/gpex.c | 12 ++ hw/riscv/Kconfig| 1 + hw/riscv/virt-acpi-build.c | 323 +--- hw/riscv/virt.c | 72 --- hw/virtio/meson.build | 1 + hw/virtio/virtio-acpi.c | 33 include/hw/nvram/fw_cfg_acpi.h | 15 ++ include/hw/pci-host/gpex.h | 28 ++- include/hw/riscv/virt.h | 26 +++ include/hw/virtio/virtio-acpi.h | 16 ++ 15 files changed, 499 insertions(+), 131 deletions(-) create mode 100644 hw/nvram/fw_cfg-acpi.c create mode 100644 hw/virtio/virtio-acpi.c create mode 100644 include/hw/nvram/fw_cfg_acpi.h create mode 100644 include/hw/virtio/virtio-acpi.h -- 2.39.2
[PATCH v7 08/13] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT
When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the
block size for those extensions need to be communicated via CMO node in
RHCT. Add CMO node in RHCT if any of those CMO extensions are detected.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 64 +-
1 file changed, 56 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index ec49c8804b..506d487ede 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -140,6 +140,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState
*s)
* 5.2.36 RISC-V Hart Capabilities Table (RHCT)
* REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16
* https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
+ * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view
*/
static void build_rhct(GArray *table_data,
BIOSLinker *linker,
@@ -149,8 +150,8 @@ static void build_rhct(GArray *table_data,
MachineState *ms = MACHINE(s);
const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
size_t len, aligned_len;
-uint32_t isa_offset, num_rhct_nodes;
-RISCVCPU *cpu;
+uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
+RISCVCPU *cpu = >soc[0].harts[0];
char *isa;
AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -166,6 +167,9 @@ static void build_rhct(GArray *table_data,
/* ISA + N hart info */
num_rhct_nodes = 1 + ms->smp.cpus;
+if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
+num_rhct_nodes++;
+}
/* Number of RHCT nodes*/
build_append_int_noprefix(table_data, num_rhct_nodes, 4);
@@ -177,7 +181,6 @@ static void build_rhct(GArray *table_data,
isa_offset = table_data->len - table.table_offset;
build_append_int_noprefix(table_data, 0, 2); /* Type 0 */
-cpu = >soc[0].harts[0];
isa = riscv_isa_string(cpu);
len = 8 + strlen(isa) + 1;
aligned_len = (len % 2) ? (len + 1) : len;
@@ -193,14 +196,59 @@ static void build_rhct(GArray *table_data,
build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */
}
+/* CMO node */
+if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
+cmo_offset = table_data->len - table.table_offset;
+build_append_int_noprefix(table_data, 1, 2);/* Type */
+build_append_int_noprefix(table_data, 10, 2); /* Length */
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+build_append_int_noprefix(table_data, 0, 1);/* Reserved */
+
+/* CBOM block size */
+if (cpu->cfg.cbom_blocksize) {
+build_append_int_noprefix(table_data,
+ __builtin_ctz(cpu->cfg.cbom_blocksize),
+ 1);
+} else {
+build_append_int_noprefix(table_data, 0, 1);
+}
+
+/* CBOP block size */
+build_append_int_noprefix(table_data, 0, 1);
+
+/* CBOZ block size */
+if (cpu->cfg.cboz_blocksize) {
+build_append_int_noprefix(table_data,
+ __builtin_ctz(cpu->cfg.cboz_blocksize),
+ 1);
+} else {
+build_append_int_noprefix(table_data, 0, 1);
+}
+}
+
/* Hart Info Node */
for (int i = 0; i < arch_ids->len; i++) {
+len = 16;
+int num_offsets = 1;
build_append_int_noprefix(table_data, 0x, 2); /* Type */
-build_append_int_noprefix(table_data, 16, 2); /* Length */
-build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
-build_append_int_noprefix(table_data, 1, 2);/* Number of offsets */
-build_append_int_noprefix(table_data, i, 4);/* ACPI Processor UID
*/
-build_append_int_noprefix(table_data, isa_offset, 4); /* Offsets[0] */
+
+/* Length */
+if (cmo_offset) {
+len += 4;
+num_offsets++;
+}
+
+build_append_int_noprefix(table_data, len, 2);
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+/* Number of offsets */
+build_append_int_noprefix(table_data, num_offsets, 2);
+build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
+
+/* Offsets */
+build_append_int_noprefix(table_data, isa_offset, 4);
+if (cmo_offset) {
+build_append_int_noprefix(table_data, cmo_offset, 4);
+}
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v7 05/13] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC
Update the RINTC structure in MADT with AIA related fields.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 43 ++
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index d8772c2821..3f9536356e 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -38,6 +38,7 @@
#include "hw/intc/riscv_aclint.h"
#define ACPI_BUILD_TABLE_SIZE 0x2
+#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
typedef struct AcpiBuildState {
/* Copy of table in RAM (for patching) */
@@ -59,17 +60,50 @@ static void acpi_align_size(GArray *blob, unsigned align)
static void riscv_acpi_madt_add_rintc(uint32_t uid,
const CPUArchIdList *arch_ids,
- GArray *entry)
+ GArray *entry,
+ RISCVVirtState *s)
{
+uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
uint64_t hart_id = arch_ids->cpus[uid].arch_id;
+uint32_t imsic_size, local_cpu_id, socket_id;
+uint64_t imsic_socket_addr, imsic_addr;
+MachineState *ms = MACHINE(s);
+socket_id = arch_ids->cpus[uid].props.node_id;
+local_cpu_id = (arch_ids->cpus[uid].arch_id -
+riscv_socket_first_hartid(ms, socket_id)) %
+riscv_socket_hart_count(ms, socket_id);
+imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base +
+(socket_id * VIRT_IMSIC_GROUP_MAX_SIZE);
+imsic_size = IMSIC_HART_SIZE(guest_index_bits);
+imsic_addr = imsic_socket_addr + local_cpu_id * imsic_size;
build_append_int_noprefix(entry, 0x18, 1); /* Type */
-build_append_int_noprefix(entry, 20, 1); /* Length */
+build_append_int_noprefix(entry, 36, 1); /* Length */
build_append_int_noprefix(entry, 1, 1); /* Version */
build_append_int_noprefix(entry, 0, 1); /* Reserved */
build_append_int_noprefix(entry, 0x1, 4);/* Flags*/
build_append_int_noprefix(entry, hart_id, 8);/* Hart ID */
build_append_int_noprefix(entry, uid, 4);/* ACPI Processor UID */
+/* External Interrupt Controller ID */
+if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
+build_append_int_noprefix(entry,
+ ACPI_BUILD_INTC_ID(
+ arch_ids->cpus[uid].props.node_id,
+ local_cpu_id),
+ 4);
+} else {
+build_append_int_noprefix(entry, 0, 4);
+}
+
+if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+/* IMSIC Base address */
+build_append_int_noprefix(entry, imsic_addr, 8);
+/* IMSIC Size */
+build_append_int_noprefix(entry, imsic_size, 4);
+} else {
+build_append_int_noprefix(entry, 0, 8);
+build_append_int_noprefix(entry, 0, 4);
+}
}
static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
@@ -88,7 +122,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
aml_int(arch_ids->cpus[i].arch_id)));
/* build _MAT object */
-riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf);
+riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf, s);
aml_append(dev, aml_name_decl("_MAT",
aml_buffer(madt_buf->len,
(uint8_t *)madt_buf->data)));
@@ -227,6 +261,7 @@ static void build_dsdt(GArray *table_data,
* 5.2.12 Multiple APIC Description Table (MADT)
* REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15
* https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
+ * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view
*/
static void build_madt(GArray *table_data,
BIOSLinker *linker,
@@ -246,7 +281,7 @@ static void build_madt(GArray *table_data,
/* RISC-V Local INTC structures per HART */
for (int i = 0; i < arch_ids->len; i++) {
-riscv_acpi_madt_add_rintc(i, arch_ids, table_data);
+riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s);
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v7 02/13] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location
RISC-V also needs to create the virtio in DSDT in the same way as ARM.
So, instead of duplicating the code, move this function to the device
specific file which is common across architectures.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/arm/virt-acpi-build.c| 32
hw/virtio/meson.build | 1 +
hw/virtio/virtio-acpi.c | 33 +
include/hw/virtio/virtio-acpi.h | 16
4 files changed, 54 insertions(+), 28 deletions(-)
create mode 100644 hw/virtio/virtio-acpi.c
create mode 100644 include/hw/virtio/virtio-acpi.h
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index dd2e95f0ea..b73ddd0c38 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -58,6 +58,7 @@
#include "migration/vmstate.h"
#include "hw/acpi/ghes.h"
#include "hw/acpi/viot.h"
+#include "hw/virtio/virtio-acpi.h"
#define ARM_SPI_BASE 32
@@ -118,32 +119,6 @@ static void acpi_dsdt_add_flash(Aml *scope, const
MemMapEntry *flash_memmap)
aml_append(scope, dev);
}
-static void acpi_dsdt_add_virtio(Aml *scope,
- const MemMapEntry *virtio_mmio_memmap,
- uint32_t mmio_irq, int num)
-{
-hwaddr base = virtio_mmio_memmap->base;
-hwaddr size = virtio_mmio_memmap->size;
-int i;
-
-for (i = 0; i < num; i++) {
-uint32_t irq = mmio_irq + i;
-Aml *dev = aml_device("VR%02u", i);
-aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
-aml_append(dev, aml_name_decl("_UID", aml_int(i)));
-aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
-Aml *crs = aml_resource_template();
-aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
-aml_append(crs,
- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
- AML_EXCLUSIVE, , 1));
-aml_append(dev, aml_name_decl("_CRS", crs));
-aml_append(scope, dev);
-base += size;
-}
-}
-
static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
uint32_t irq, VirtMachineState *vms)
{
@@ -850,8 +825,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
acpi_dsdt_add_flash(scope, [VIRT_FLASH]);
}
fw_cfg_acpi_dsdt_add(scope, [VIRT_FW_CFG]);
-acpi_dsdt_add_virtio(scope, [VIRT_MMIO],
-(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
+virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size,
+ (irqmap[VIRT_MMIO] + ARM_SPI_BASE),
+ 0, NUM_VIRTIO_TRANSPORTS);
acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
if (vms->acpi_dev) {
build_ged_aml(scope, "\\_SB."GED_DEVICE,
diff --git a/hw/virtio/meson.build b/hw/virtio/meson.build
index c0055a7832..9d62097a21 100644
--- a/hw/virtio/meson.build
+++ b/hw/virtio/meson.build
@@ -79,3 +79,4 @@ system_ss.add(when: 'CONFIG_ALL', if_true:
files('virtio-stub.c'))
system_ss.add(files('virtio-hmp-cmds.c'))
specific_ss.add_all(when: 'CONFIG_VIRTIO', if_true: specific_virtio_ss)
+system_ss.add(when: 'CONFIG_ACPI', if_true: files('virtio-acpi.c'))
diff --git a/hw/virtio/virtio-acpi.c b/hw/virtio/virtio-acpi.c
new file mode 100644
index 00..e18cb38bdb
--- /dev/null
+++ b/hw/virtio/virtio-acpi.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * virtio ACPI Support
+ *
+ */
+
+#include "hw/virtio/virtio-acpi.h"
+#include "hw/acpi/aml-build.h"
+
+void virtio_acpi_dsdt_add(Aml *scope, const hwaddr base, const hwaddr size,
+ uint32_t mmio_irq, long int start_index, int num)
+{
+hwaddr virtio_base = base;
+uint32_t irq = mmio_irq;
+long int i;
+
+for (i = start_index; i < start_index + num; i++) {
+Aml *dev = aml_device("VR%02u", (unsigned)i);
+aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
+aml_append(dev, aml_name_decl("_UID", aml_int(i)));
+aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(virtio_base, size, AML_READ_WRITE));
+aml_append(crs,
+ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, , 1));
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(scope, dev);
+virtio_base += size;
+irq++;
+}
+}
diff --git a/include/hw/virtio/virtio-acpi.h b/include
[PATCH v7 01/13] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location
RISC-V also needs to use the same code to create fw_cfg in DSDT. So,
avoid code duplication by moving the code in arm and riscv to a device
specific file.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/arm/virt-acpi-build.c | 19 ++-
hw/nvram/fw_cfg-acpi.c | 23 +++
hw/nvram/meson.build | 1 +
hw/riscv/virt-acpi-build.c | 19 ++-
include/hw/nvram/fw_cfg_acpi.h | 15 +++
5 files changed, 43 insertions(+), 34 deletions(-)
create mode 100644 hw/nvram/fw_cfg-acpi.c
create mode 100644 include/hw/nvram/fw_cfg_acpi.h
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 9ce136cd88..dd2e95f0ea 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -35,7 +35,7 @@
#include "target/arm/cpu.h"
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
-#include "hw/nvram/fw_cfg.h"
+#include "hw/nvram/fw_cfg_acpi.h"
#include "hw/acpi/bios-linker-loader.h"
#include "hw/acpi/aml-build.h"
#include "hw/acpi/utils.h"
@@ -94,21 +94,6 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry
*uart_memmap,
aml_append(scope, dev);
}
-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
-{
-Aml *dev = aml_device("FWCF");
-aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
-/* device present, functioning, decoding, not shown in UI */
-aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
-aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
-Aml *crs = aml_resource_template();
-aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
- fw_cfg_memmap->size, AML_READ_WRITE));
-aml_append(dev, aml_name_decl("_CRS", crs));
-aml_append(scope, dev);
-}
-
static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
{
Aml *dev, *crs;
@@ -864,7 +849,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
if (vmc->acpi_expose_flash) {
acpi_dsdt_add_flash(scope, [VIRT_FLASH]);
}
-acpi_dsdt_add_fw_cfg(scope, [VIRT_FW_CFG]);
+fw_cfg_acpi_dsdt_add(scope, [VIRT_FW_CFG]);
acpi_dsdt_add_virtio(scope, [VIRT_MMIO],
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
diff --git a/hw/nvram/fw_cfg-acpi.c b/hw/nvram/fw_cfg-acpi.c
new file mode 100644
index 00..4e48baeaa0
--- /dev/null
+++ b/hw/nvram/fw_cfg-acpi.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Add fw_cfg device in DSDT
+ *
+ */
+
+#include "hw/nvram/fw_cfg_acpi.h"
+#include "hw/acpi/aml-build.h"
+
+void fw_cfg_acpi_dsdt_add(Aml *scope, const MemMapEntry *fw_cfg_memmap)
+{
+Aml *dev = aml_device("FWCF");
+aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
+/* device present, functioning, decoding, not shown in UI */
+aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
+aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
+ fw_cfg_memmap->size, AML_READ_WRITE));
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(scope, dev);
+}
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
index 75e415b1a0..4996c72456 100644
--- a/hw/nvram/meson.build
+++ b/hw/nvram/meson.build
@@ -17,3 +17,4 @@ system_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true:
files(
system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
+specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c'))
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 7331248f59..d8772c2821 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -28,6 +28,7 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/aml-build.h"
#include "hw/acpi/utils.h"
+#include "hw/nvram/fw_cfg_acpi.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/reset.h"
@@ -97,22 +98,6 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
}
}
-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
-{
-Aml *dev = aml_device("FWCF");
-aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
-
-/* device present, fu
[PATCH v6 12/13] hw/riscv/virt-acpi-build.c: Add IO controllers and devices
Add basic IO controllers and devices like PCI, VirtIO and UART in the
ACPI namespace.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/Kconfig | 1 +
hw/riscv/virt-acpi-build.c | 79 --
2 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index b6a5eb4452..a50717be87 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -45,6 +45,7 @@ config RISCV_VIRT
select FW_CFG_DMA
select PLATFORM_BUS
select ACPI
+select ACPI_PCI
config SHAKTI_C
bool
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 86c38f7c2b..4d03a27efd 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -27,15 +27,18 @@
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/aml-build.h"
+#include "hw/acpi/pci.h"
#include "hw/acpi/utils.h"
+#include "hw/intc/riscv_aclint.h"
#include "hw/nvram/fw_cfg_acpi.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/riscv/virt.h"
+#include "hw/riscv/numa.h"
+#include "hw/virtio/virtio-acpi.h"
+#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/reset.h"
-#include "migration/vmstate.h"
-#include "hw/riscv/virt.h"
-#include "hw/riscv/numa.h"
-#include "hw/intc/riscv_aclint.h"
#define ACPI_BUILD_TABLE_SIZE 0x2
#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
@@ -132,6 +135,39 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState
*s)
}
}
+static void
+acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
+uint32_t uart_irq)
+{
+Aml *dev = aml_device("COM0");
+aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
+aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(uart_memmap->base,
+ uart_memmap->size, AML_READ_WRITE));
+aml_append(crs,
+aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, _irq, 1));
+aml_append(dev, aml_name_decl("_CRS", crs));
+
+Aml *pkg = aml_package(2);
+aml_append(pkg, aml_string("clock-frequency"));
+aml_append(pkg, aml_int(3686400));
+
+Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301");
+
+Aml *pkg1 = aml_package(1);
+aml_append(pkg1, pkg);
+
+Aml *package = aml_package(2);
+aml_append(package, UUID);
+aml_append(package, pkg1);
+
+aml_append(dev, aml_name_decl("_DSD", package));
+aml_append(scope, dev);
+}
+
/* RHCT Node[N] starts at offset 56 */
#define RHCT_NODE_ARRAY_OFFSET 56
@@ -310,6 +346,8 @@ static void build_dsdt(GArray *table_data,
RISCVVirtState *s)
{
Aml *scope, *dsdt;
+MachineState *ms = MACHINE(s);
+uint8_t socket_count;
const MemMapEntry *memmap = s->memmap;
AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id,
.oem_table_id = s->oem_table_id };
@@ -329,6 +367,29 @@ static void build_dsdt(GArray *table_data,
fw_cfg_acpi_dsdt_add(scope, [VIRT_FW_CFG]);
+socket_count = riscv_socket_count(ms);
+
+acpi_dsdt_add_uart(scope, [VIRT_UART0], UART0_IRQ);
+
+if (socket_count == 1) {
+virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
+ memmap[VIRT_VIRTIO].size,
+ VIRTIO_IRQ, 0, VIRTIO_COUNT);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ);
+} else if (socket_count == 2) {
+virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
+ memmap[VIRT_VIRTIO].size,
+ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
+ VIRTIO_COUNT);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES);
+} else {
+virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
+ memmap[VIRT_VIRTIO].size,
+ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
+ VIRTIO_COUNT);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES *
2);
+}
+
aml_append(dsdt, scope);
/* copy AML table into ACPI tables blob and patch header there */
@@ -465,6 +526,16 @@ static void virt_acpi_build(RISCVVirtState *s,
AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_rhct(tables_blob, tables->linker, s)
[PATCH v6 04/13] hw/riscv: virt: Make few IMSIC macros and functions public
Some macros and static function related to IMSIC are defined in virt.c.
They are required in virt-acpi-build.c. So, make them public.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt.c | 25 +
include/hw/riscv/virt.h | 25 +
2 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 1732c42915..085654ab2f 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -38,7 +38,6 @@
#include "kvm/kvm_riscv.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/riscv_aplic.h"
-#include "hw/intc/riscv_imsic.h"
#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_test.h"
#include "hw/platform-bus.h"
@@ -54,28 +53,6 @@
#include "hw/acpi/aml-build.h"
#include "qapi/qapi-visit-common.h"
-/*
- * The virt machine physical address space used by some of the devices
- * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
- * number of CPUs, and number of IMSIC guest files.
- *
- * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
- * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
- * of virt machine physical address space.
- */
-
-#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
-#if VIRT_IMSIC_GROUP_MAX_SIZE < \
-IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
-#error "Can't accommodate single IMSIC group in address space"
-#endif
-
-#define VIRT_IMSIC_MAX_SIZE(VIRT_SOCKETS_MAX * \
-VIRT_IMSIC_GROUP_MAX_SIZE)
-#if 0x400 < VIRT_IMSIC_MAX_SIZE
-#error "Can't accommodate all IMSIC groups in address space"
-#endif
-
/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
static bool virt_use_kvm_aia(RISCVVirtState *s)
{
@@ -512,7 +489,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
g_free(plic_cells);
}
-static uint32_t imsic_num_bits(uint32_t count)
+uint32_t imsic_num_bits(uint32_t count)
{
uint32_t ret = 0;
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index e5c474b26e..5b03575ed3 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -23,6 +23,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/sysbus.h"
#include "hw/block/flash.h"
+#include "hw/intc/riscv_imsic.h"
#define VIRT_CPUS_MAX_BITS 9
#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
@@ -127,4 +128,28 @@ enum {
bool virt_is_acpi_enabled(RISCVVirtState *s);
void virt_acpi_setup(RISCVVirtState *vms);
+uint32_t imsic_num_bits(uint32_t count);
+
+/*
+ * The virt machine physical address space used by some of the devices
+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+ * number of CPUs, and number of IMSIC guest files.
+ *
+ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
+ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
+ * of virt machine physical address space.
+ */
+
+#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
+#if VIRT_IMSIC_GROUP_MAX_SIZE < \
+IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
+#error "Can't accomodate single IMSIC group in address space"
+#endif
+
+#define VIRT_IMSIC_MAX_SIZE(VIRT_SOCKETS_MAX * \
+VIRT_IMSIC_GROUP_MAX_SIZE)
+#if 0x400 < VIRT_IMSIC_MAX_SIZE
+#error "Can't accomodate all IMSIC groups in address space"
+#endif
+
#endif
--
2.39.2
[PATCH v6 13/13] hw/riscv/virt-acpi-build.c: Add PLIC in MADT
Add PLIC structures for each socket in the MADT when system is
configured with PLIC as the external interrupt controller.
Signed-off-by: Haibo Xu
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 4d03a27efd..d4a02579d6 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -94,6 +94,12 @@ static void riscv_acpi_madt_add_rintc(uint32_t uid,
arch_ids->cpus[uid].props.node_id,
local_cpu_id),
4);
+} else if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+build_append_int_noprefix(entry,
+ ACPI_BUILD_INTC_ID(
+ arch_ids->cpus[uid].props.node_id,
+ 2 * local_cpu_id + 1),
+ 4);
} else {
build_append_int_noprefix(entry, 0, 4);
}
@@ -494,6 +500,29 @@ static void build_madt(GArray *table_data,
build_append_int_noprefix(table_data,
s->memmap[VIRT_APLIC_S].size, 4);
}
+} else {
+/* PLICs */
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+aplic_addr = s->memmap[VIRT_PLIC].base +
+ s->memmap[VIRT_PLIC].size * socket;
+gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+build_append_int_noprefix(table_data, 0x1B, 1); /* Type */
+build_append_int_noprefix(table_data, 36, 1); /* Length */
+build_append_int_noprefix(table_data, 1, 1); /* Version */
+build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */
+build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */
+/* Total External Interrupt Sources Supported */
+build_append_int_noprefix(table_data,
+ VIRT_IRQCHIP_NUM_SOURCES - 1, 2);
+build_append_int_noprefix(table_data, 0, 2); /* Max Priority */
+build_append_int_noprefix(table_data, 0, 4); /* Flags */
+/* PLIC Size */
+build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size,
4);
+/* PLIC Address */
+build_append_int_noprefix(table_data, aplic_addr, 8);
+/* Global System Interrupt Vector Base */
+build_append_int_noprefix(table_data, gsi_base, 4);
+}
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v6 05/13] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC
Update the RINTC structure in MADT with AIA related fields.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 43 ++
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index d8772c2821..3f9536356e 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -38,6 +38,7 @@
#include "hw/intc/riscv_aclint.h"
#define ACPI_BUILD_TABLE_SIZE 0x2
+#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
typedef struct AcpiBuildState {
/* Copy of table in RAM (for patching) */
@@ -59,17 +60,50 @@ static void acpi_align_size(GArray *blob, unsigned align)
static void riscv_acpi_madt_add_rintc(uint32_t uid,
const CPUArchIdList *arch_ids,
- GArray *entry)
+ GArray *entry,
+ RISCVVirtState *s)
{
+uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
uint64_t hart_id = arch_ids->cpus[uid].arch_id;
+uint32_t imsic_size, local_cpu_id, socket_id;
+uint64_t imsic_socket_addr, imsic_addr;
+MachineState *ms = MACHINE(s);
+socket_id = arch_ids->cpus[uid].props.node_id;
+local_cpu_id = (arch_ids->cpus[uid].arch_id -
+riscv_socket_first_hartid(ms, socket_id)) %
+riscv_socket_hart_count(ms, socket_id);
+imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base +
+(socket_id * VIRT_IMSIC_GROUP_MAX_SIZE);
+imsic_size = IMSIC_HART_SIZE(guest_index_bits);
+imsic_addr = imsic_socket_addr + local_cpu_id * imsic_size;
build_append_int_noprefix(entry, 0x18, 1); /* Type */
-build_append_int_noprefix(entry, 20, 1); /* Length */
+build_append_int_noprefix(entry, 36, 1); /* Length */
build_append_int_noprefix(entry, 1, 1); /* Version */
build_append_int_noprefix(entry, 0, 1); /* Reserved */
build_append_int_noprefix(entry, 0x1, 4);/* Flags*/
build_append_int_noprefix(entry, hart_id, 8);/* Hart ID */
build_append_int_noprefix(entry, uid, 4);/* ACPI Processor UID */
+/* External Interrupt Controller ID */
+if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
+build_append_int_noprefix(entry,
+ ACPI_BUILD_INTC_ID(
+ arch_ids->cpus[uid].props.node_id,
+ local_cpu_id),
+ 4);
+} else {
+build_append_int_noprefix(entry, 0, 4);
+}
+
+if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+/* IMSIC Base address */
+build_append_int_noprefix(entry, imsic_addr, 8);
+/* IMSIC Size */
+build_append_int_noprefix(entry, imsic_size, 4);
+} else {
+build_append_int_noprefix(entry, 0, 8);
+build_append_int_noprefix(entry, 0, 4);
+}
}
static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
@@ -88,7 +122,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
aml_int(arch_ids->cpus[i].arch_id)));
/* build _MAT object */
-riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf);
+riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf, s);
aml_append(dev, aml_name_decl("_MAT",
aml_buffer(madt_buf->len,
(uint8_t *)madt_buf->data)));
@@ -227,6 +261,7 @@ static void build_dsdt(GArray *table_data,
* 5.2.12 Multiple APIC Description Table (MADT)
* REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15
* https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
+ * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view
*/
static void build_madt(GArray *table_data,
BIOSLinker *linker,
@@ -246,7 +281,7 @@ static void build_madt(GArray *table_data,
/* RISC-V Local INTC structures per HART */
for (int i = 0; i < arch_ids->len; i++) {
-riscv_acpi_madt_add_rintc(i, arch_ids, table_data);
+riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s);
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v6 06/13] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT
Add IMSIC structure in MADT when IMSIC is configured.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 3f9536356e..6bb21014fd 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -270,6 +270,19 @@ static void build_madt(GArray *table_data,
MachineClass *mc = MACHINE_GET_CLASS(s);
MachineState *ms = MACHINE(s);
const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
+uint8_t group_index_bits = imsic_num_bits(riscv_socket_count(ms));
+uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
+uint16_t imsic_max_hart_per_socket = 0;
+uint8_t hart_index_bits;
+uint8_t socket;
+
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
+imsic_max_hart_per_socket = s->soc[socket].num_harts;
+}
+}
+
+hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket);
AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id,
.oem_table_id = s->oem_table_id };
@@ -284,6 +297,28 @@ static void build_madt(GArray *table_data,
riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s);
}
+/* IMSIC */
+if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+/* IMSIC */
+build_append_int_noprefix(table_data, 0x19, 1); /* Type */
+build_append_int_noprefix(table_data, 16, 1); /* Length */
+build_append_int_noprefix(table_data, 1, 1);/* Version */
+build_append_int_noprefix(table_data, 0, 1);/* Reserved */
+build_append_int_noprefix(table_data, 0, 4);/* Flags */
+/* Number of supervisor mode Interrupt Identities */
+build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
+/* Number of guest mode Interrupt Identities */
+build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
+/* Guest Index Bits */
+build_append_int_noprefix(table_data, guest_index_bits, 1);
+/* Hart Index Bits */
+build_append_int_noprefix(table_data, hart_index_bits, 1);
+/* Group Index Bits */
+build_append_int_noprefix(table_data, group_index_bits, 1);
+/* Group Index Shift */
+build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1);
+}
+
acpi_table_end(linker, );
}
--
2.39.2
[PATCH v6 08/13] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT
When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the
block size for those extensions need to be communicated via CMO node in
RHCT. Add CMO node in RHCT if any of those CMO extensions are detected.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 64 +-
1 file changed, 56 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index ec49c8804b..506d487ede 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -140,6 +140,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState
*s)
* 5.2.36 RISC-V Hart Capabilities Table (RHCT)
* REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16
* https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
+ * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view
*/
static void build_rhct(GArray *table_data,
BIOSLinker *linker,
@@ -149,8 +150,8 @@ static void build_rhct(GArray *table_data,
MachineState *ms = MACHINE(s);
const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
size_t len, aligned_len;
-uint32_t isa_offset, num_rhct_nodes;
-RISCVCPU *cpu;
+uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
+RISCVCPU *cpu = >soc[0].harts[0];
char *isa;
AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -166,6 +167,9 @@ static void build_rhct(GArray *table_data,
/* ISA + N hart info */
num_rhct_nodes = 1 + ms->smp.cpus;
+if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
+num_rhct_nodes++;
+}
/* Number of RHCT nodes*/
build_append_int_noprefix(table_data, num_rhct_nodes, 4);
@@ -177,7 +181,6 @@ static void build_rhct(GArray *table_data,
isa_offset = table_data->len - table.table_offset;
build_append_int_noprefix(table_data, 0, 2); /* Type 0 */
-cpu = >soc[0].harts[0];
isa = riscv_isa_string(cpu);
len = 8 + strlen(isa) + 1;
aligned_len = (len % 2) ? (len + 1) : len;
@@ -193,14 +196,59 @@ static void build_rhct(GArray *table_data,
build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */
}
+/* CMO node */
+if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
+cmo_offset = table_data->len - table.table_offset;
+build_append_int_noprefix(table_data, 1, 2);/* Type */
+build_append_int_noprefix(table_data, 10, 2); /* Length */
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+build_append_int_noprefix(table_data, 0, 1);/* Reserved */
+
+/* CBOM block size */
+if (cpu->cfg.cbom_blocksize) {
+build_append_int_noprefix(table_data,
+ __builtin_ctz(cpu->cfg.cbom_blocksize),
+ 1);
+} else {
+build_append_int_noprefix(table_data, 0, 1);
+}
+
+/* CBOP block size */
+build_append_int_noprefix(table_data, 0, 1);
+
+/* CBOZ block size */
+if (cpu->cfg.cboz_blocksize) {
+build_append_int_noprefix(table_data,
+ __builtin_ctz(cpu->cfg.cboz_blocksize),
+ 1);
+} else {
+build_append_int_noprefix(table_data, 0, 1);
+}
+}
+
/* Hart Info Node */
for (int i = 0; i < arch_ids->len; i++) {
+len = 16;
+int num_offsets = 1;
build_append_int_noprefix(table_data, 0x, 2); /* Type */
-build_append_int_noprefix(table_data, 16, 2); /* Length */
-build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
-build_append_int_noprefix(table_data, 1, 2);/* Number of offsets */
-build_append_int_noprefix(table_data, i, 4);/* ACPI Processor UID
*/
-build_append_int_noprefix(table_data, isa_offset, 4); /* Offsets[0] */
+
+/* Length */
+if (cmo_offset) {
+len += 4;
+num_offsets++;
+}
+
+build_append_int_noprefix(table_data, len, 2);
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+/* Number of offsets */
+build_append_int_noprefix(table_data, num_offsets, 2);
+build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
+
+/* Offsets */
+build_append_int_noprefix(table_data, isa_offset, 4);
+if (cmo_offset) {
+build_append_int_noprefix(table_data, cmo_offset, 4);
+}
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v6 02/13] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location
RISC-V also needs to create the virtio in DSDT in the same way as ARM.
So, instead of duplicating the code, move this function to the device
specific file which is common across architectures.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/arm/virt-acpi-build.c| 32
hw/virtio/meson.build | 1 +
hw/virtio/virtio-acpi.c | 32
include/hw/virtio/virtio-acpi.h | 16
4 files changed, 53 insertions(+), 28 deletions(-)
create mode 100644 hw/virtio/virtio-acpi.c
create mode 100644 include/hw/virtio/virtio-acpi.h
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index dd2e95f0ea..b73ddd0c38 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -58,6 +58,7 @@
#include "migration/vmstate.h"
#include "hw/acpi/ghes.h"
#include "hw/acpi/viot.h"
+#include "hw/virtio/virtio-acpi.h"
#define ARM_SPI_BASE 32
@@ -118,32 +119,6 @@ static void acpi_dsdt_add_flash(Aml *scope, const
MemMapEntry *flash_memmap)
aml_append(scope, dev);
}
-static void acpi_dsdt_add_virtio(Aml *scope,
- const MemMapEntry *virtio_mmio_memmap,
- uint32_t mmio_irq, int num)
-{
-hwaddr base = virtio_mmio_memmap->base;
-hwaddr size = virtio_mmio_memmap->size;
-int i;
-
-for (i = 0; i < num; i++) {
-uint32_t irq = mmio_irq + i;
-Aml *dev = aml_device("VR%02u", i);
-aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
-aml_append(dev, aml_name_decl("_UID", aml_int(i)));
-aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
-Aml *crs = aml_resource_template();
-aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
-aml_append(crs,
- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
- AML_EXCLUSIVE, , 1));
-aml_append(dev, aml_name_decl("_CRS", crs));
-aml_append(scope, dev);
-base += size;
-}
-}
-
static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
uint32_t irq, VirtMachineState *vms)
{
@@ -850,8 +825,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
acpi_dsdt_add_flash(scope, [VIRT_FLASH]);
}
fw_cfg_acpi_dsdt_add(scope, [VIRT_FW_CFG]);
-acpi_dsdt_add_virtio(scope, [VIRT_MMIO],
-(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
+virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size,
+ (irqmap[VIRT_MMIO] + ARM_SPI_BASE),
+ 0, NUM_VIRTIO_TRANSPORTS);
acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
if (vms->acpi_dev) {
build_ged_aml(scope, "\\_SB."GED_DEVICE,
diff --git a/hw/virtio/meson.build b/hw/virtio/meson.build
index c0055a7832..9d62097a21 100644
--- a/hw/virtio/meson.build
+++ b/hw/virtio/meson.build
@@ -79,3 +79,4 @@ system_ss.add(when: 'CONFIG_ALL', if_true:
files('virtio-stub.c'))
system_ss.add(files('virtio-hmp-cmds.c'))
specific_ss.add_all(when: 'CONFIG_VIRTIO', if_true: specific_virtio_ss)
+system_ss.add(when: 'CONFIG_ACPI', if_true: files('virtio-acpi.c'))
diff --git a/hw/virtio/virtio-acpi.c b/hw/virtio/virtio-acpi.c
new file mode 100644
index 00..b55905dbc6
--- /dev/null
+++ b/hw/virtio/virtio-acpi.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * virtio ACPI Support
+ *
+ */
+
+#include "hw/virtio/virtio-acpi.h"
+#include "hw/acpi/aml-build.h"
+
+void virtio_acpi_dsdt_add(Aml *scope, const hwaddr base, const hwaddr size,
+ uint32_t mmio_irq, long int start_index, int num)
+{
+long int i;
+hwaddr virtio_base = base;
+
+for (i = start_index; i < start_index + num; i++) {
+uint32_t irq = mmio_irq + i;
+Aml *dev = aml_device("VR%02u", (unsigned)i);
+aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
+aml_append(dev, aml_name_decl("_UID", aml_int(i)));
+aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(virtio_base, size, AML_READ_WRITE));
+aml_append(crs,
+ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, , 1));
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(scope, dev);
+virtio_base += size;
+}
+}
diff --git a/include/hw/virtio/virtio-acpi.h b/include/hw/virtio/
[PATCH v6 10/13] hw/pci-host/gpex: Define properties for MMIO ranges
ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit
and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of
making these values machine specific, create properties for the GPEX
host bridge with default value 0. During initialization, the firmware
can initialize these properties with correct values for the platform.
This basically allows DSDT generator code independent of the machine
specific memory map accesses.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
Reviewed-by: Daniel Henrique Barboza
---
hw/pci-host/gpex-acpi.c| 13 +
hw/pci-host/gpex.c | 12
include/hw/pci-host/gpex.h | 28
3 files changed, 45 insertions(+), 8 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index 1092dc3b70..f69413ea2c 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -281,3 +281,16 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
crs_range_set_free(_range_set);
}
+
+void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq)
+{
+bool ambig;
+Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, );
+
+if (!obj || ambig) {
+return;
+}
+
+GPEX_HOST(obj)->gpex_cfg.irq = irq;
+acpi_dsdt_add_gpex(scope, _HOST(obj)->gpex_cfg);
+}
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
index a6752fac5e..41f4e73f6e 100644
--- a/hw/pci-host/gpex.c
+++ b/hw/pci-host/gpex.c
@@ -154,6 +154,18 @@ static Property gpex_host_properties[] = {
*/
DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost,
allow_unmapped_accesses, true),
+DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0),
+DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_PIO_SIZE, GPEXHost, gpex_cfg.pio.size, 0),
+DEFINE_PROP_UINT64(PCI_HOST_BELOW_4G_MMIO_BASE, GPEXHost,
+ gpex_cfg.mmio32.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MMIO_SIZE, GPEXHost,
+ gpex_cfg.mmio32.size, 0),
+DEFINE_PROP_UINT64(PCI_HOST_ABOVE_4G_MMIO_BASE, GPEXHost,
+ gpex_cfg.mmio64.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost,
+ gpex_cfg.mmio64.size, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h
index b0240bd768..441c6b8b20 100644
--- a/include/hw/pci-host/gpex.h
+++ b/include/hw/pci-host/gpex.h
@@ -40,6 +40,15 @@ struct GPEXRootState {
/*< public >*/
};
+struct GPEXConfig {
+MemMapEntry ecam;
+MemMapEntry mmio32;
+MemMapEntry mmio64;
+MemMapEntry pio;
+int irq;
+PCIBus *bus;
+};
+
struct GPEXHost {
/*< private >*/
PCIExpressHost parent_obj;
@@ -55,19 +64,22 @@ struct GPEXHost {
int irq_num[GPEX_NUM_IRQS];
bool allow_unmapped_accesses;
-};
-struct GPEXConfig {
-MemMapEntry ecam;
-MemMapEntry mmio32;
-MemMapEntry mmio64;
-MemMapEntry pio;
-int irq;
-PCIBus *bus;
+struct GPEXConfig gpex_cfg;
};
int gpex_set_irq_num(GPEXHost *s, int index, int gsi);
void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg);
+void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq);
+
+#define PCI_HOST_PIO_BASE "pio-base"
+#define PCI_HOST_PIO_SIZE "pio-size"
+#define PCI_HOST_ECAM_BASE "ecam-base"
+#define PCI_HOST_ECAM_SIZE "ecam-size"
+#define PCI_HOST_BELOW_4G_MMIO_BASE "below-4g-mmio-base"
+#define PCI_HOST_BELOW_4G_MMIO_SIZE "below-4g-mmio-size"
+#define PCI_HOST_ABOVE_4G_MMIO_BASE "above-4g-mmio-base"
+#define PCI_HOST_ABOVE_4G_MMIO_SIZE "above-4g-mmio-size"
#endif /* HW_GPEX_H */
--
2.39.2
[PATCH v6 00/13] RISC-V: ACPI: Enable AIA, PLIC and update RHCT
This series primarily enables external interrupt controllers (AIA and PLIC) in ACPI tables for RISC-V virt platform. It also updates RHCT with CMO and MMU related information. Below ECRs for these changes are approved by ASWG and will be available in next ACPI spec release. 1) MADT (AIA) - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing 2) RHCT - https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view?usp=sharing First two patches in this series are to migrate a couple of functions from ARM architecture to common code so that RISC-V doesn't need to duplicate the same. The patch set is based on Alistair's riscv-to-apply.next branch. These changes are also available in riscv_acpi_b2_v6 branch at: https://github.com/vlsunil/qemu/ Changes since v5: 1) Fixed the issue in PATCH 2 reported by Daniel found when built with clang + --enable-debug. Changes since v4: 1) Updated copyright for new files as per SPDX format suggested by Drew. 2) Updated RINTC patch to avoid code duplication as suggested by Drew. 3) Moved mmu offset below cmo in MMU patch as suggested by Drew. 4) Updated tags. Changes since v3: 1) Addressed comments from Daniel and Drew. 2) Added a new patch in microvm to use common function for virtio in DSDT. 3) Rebased to latest riscv-to-apply.next branch and added tags. Changes since v2: 1) Rebased to latest riscv-to-apply.next branch which needed changing ext_icboz to ext_zicboz in CMO patch. 2) Fixed node type in MMU node. 3) Added latest tags. Changes since v1: 1) As per Igor's suggestion, migrated fw_cfg and virtio creation functions to device specific file instead of generic aml-build.c. Since ACPI is optional, new files are created and enabled for build only when CONFIG_ACPI is enabled. 2) As per Igor's suggestion, properties are added to the GPEX PCI host to indicate MMIO ranges. The platform fw can initialize these to appropriate values and the DSDT generator can fetch the information from the host bus itself. This makes the code generic instead of machine specific. 3) Added PLIC patch from Haibo. 4) Rebased to latest riscv-to-apply.next and added RB tags as appropriate. Sunil V L (13): hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location hw/arm/virt-acpi-build.c: Migrate virtio creation to common location hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT hw/riscv: virt: Make few IMSIC macros and functions public hw/riscv/virt-acpi-build.c: Add AIA support in RINTC hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT hw/riscv/virt-acpi-build.c: Add APLIC in the MADT hw/riscv/virt-acpi-build.c: Add CMO information in RHCT hw/riscv/virt-acpi-build.c: Add MMU node in RHCT hw/pci-host/gpex: Define properties for MMIO ranges hw/riscv/virt: Update GPEX MMIO related properties hw/riscv/virt-acpi-build.c: Add IO controllers and devices hw/riscv/virt-acpi-build.c: Add PLIC in MADT hw/arm/virt-acpi-build.c| 51 + hw/i386/acpi-microvm.c | 15 +- hw/nvram/fw_cfg-acpi.c | 23 +++ hw/nvram/meson.build| 1 + hw/pci-host/gpex-acpi.c | 13 ++ hw/pci-host/gpex.c | 12 ++ hw/riscv/Kconfig| 1 + hw/riscv/virt-acpi-build.c | 323 +--- hw/riscv/virt.c | 72 --- hw/virtio/meson.build | 1 + hw/virtio/virtio-acpi.c | 32 include/hw/nvram/fw_cfg_acpi.h | 15 ++ include/hw/pci-host/gpex.h | 28 ++- include/hw/riscv/virt.h | 26 +++ include/hw/virtio/virtio-acpi.h | 16 ++ 15 files changed, 498 insertions(+), 131 deletions(-) create mode 100644 hw/nvram/fw_cfg-acpi.c create mode 100644 hw/virtio/virtio-acpi.c create mode 100644 include/hw/nvram/fw_cfg_acpi.h create mode 100644 include/hw/virtio/virtio-acpi.h -- 2.39.2
[PATCH v6 07/13] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT
Add APLIC structures for each socket in the MADT when system is configured
with APLIC as the external wired interrupt controller.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 6bb21014fd..ec49c8804b 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -274,6 +274,8 @@ static void build_madt(GArray *table_data,
uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
uint16_t imsic_max_hart_per_socket = 0;
uint8_t hart_index_bits;
+uint64_t aplic_addr;
+uint32_t gsi_base;
uint8_t socket;
for (socket = 0; socket < riscv_socket_count(ms); socket++) {
@@ -319,6 +321,38 @@ static void build_madt(GArray *table_data,
build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1);
}
+if (s->aia_type != VIRT_AIA_TYPE_NONE) {
+/* APLICs */
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+aplic_addr = s->memmap[VIRT_APLIC_S].base +
+ s->memmap[VIRT_APLIC_S].size * socket;
+gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+build_append_int_noprefix(table_data, 0x1A, 1);/* Type */
+build_append_int_noprefix(table_data, 36, 1); /* Length */
+build_append_int_noprefix(table_data, 1, 1); /* Version */
+build_append_int_noprefix(table_data, socket, 1); /* APLIC ID */
+build_append_int_noprefix(table_data, 0, 4); /* Flags */
+build_append_int_noprefix(table_data, 0, 8); /* Hardware ID
*/
+/* Number of IDCs */
+if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
+build_append_int_noprefix(table_data,
+ s->soc[socket].num_harts,
+ 2);
+} else {
+build_append_int_noprefix(table_data, 0, 2);
+}
+/* Total External Interrupt Sources Supported */
+build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_SOURCES, 2);
+/* Global System Interrupt Base */
+build_append_int_noprefix(table_data, gsi_base, 4);
+/* APLIC Address */
+build_append_int_noprefix(table_data, aplic_addr, 8);
+/* APLIC size */
+build_append_int_noprefix(table_data,
+ s->memmap[VIRT_APLIC_S].size, 4);
+}
+}
+
acpi_table_end(linker, );
}
--
2.39.2
[PATCH v6 09/13] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT
MMU type information is available via MMU node in RHCT. Add this node in
RHCT.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 36 +++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 506d487ede..86c38f7c2b 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -152,6 +152,8 @@ static void build_rhct(GArray *table_data,
size_t len, aligned_len;
uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
RISCVCPU *cpu = >soc[0].harts[0];
+uint32_t mmu_offset = 0;
+uint8_t satp_mode_max;
char *isa;
AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -171,6 +173,10 @@ static void build_rhct(GArray *table_data,
num_rhct_nodes++;
}
+if (cpu->cfg.satp_mode.supported != 0) {
+num_rhct_nodes++;
+}
+
/* Number of RHCT nodes*/
build_append_int_noprefix(table_data, num_rhct_nodes, 4);
@@ -226,6 +232,26 @@ static void build_rhct(GArray *table_data,
}
}
+/* MMU node structure */
+if (cpu->cfg.satp_mode.supported != 0) {
+satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
+mmu_offset = table_data->len - table.table_offset;
+build_append_int_noprefix(table_data, 2, 2);/* Type */
+build_append_int_noprefix(table_data, 8, 2);/* Length */
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+build_append_int_noprefix(table_data, 0, 1);/* Reserved */
+/* MMU Type */
+if (satp_mode_max == VM_1_10_SV57) {
+build_append_int_noprefix(table_data, 2, 1);/* Sv57 */
+} else if (satp_mode_max == VM_1_10_SV48) {
+build_append_int_noprefix(table_data, 1, 1);/* Sv48 */
+} else if (satp_mode_max == VM_1_10_SV39) {
+build_append_int_noprefix(table_data, 0, 1);/* Sv39 */
+} else {
+assert(1);
+}
+}
+
/* Hart Info Node */
for (int i = 0; i < arch_ids->len; i++) {
len = 16;
@@ -238,17 +264,25 @@ static void build_rhct(GArray *table_data,
num_offsets++;
}
+if (mmu_offset) {
+len += 4;
+num_offsets++;
+}
+
build_append_int_noprefix(table_data, len, 2);
build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
/* Number of offsets */
build_append_int_noprefix(table_data, num_offsets, 2);
build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
-
/* Offsets */
build_append_int_noprefix(table_data, isa_offset, 4);
if (cmo_offset) {
build_append_int_noprefix(table_data, cmo_offset, 4);
}
+
+if (mmu_offset) {
+build_append_int_noprefix(table_data, mmu_offset, 4);
+}
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v6 11/13] hw/riscv/virt: Update GPEX MMIO related properties
Update the GPEX host bridge properties related to MMIO ranges with
values set for the virt machine.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt.c | 47 -
include/hw/riscv/virt.h | 1 +
2 files changed, 33 insertions(+), 15 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 085654ab2f..e64886a4d8 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1049,21 +1049,45 @@ static void create_fdt(RISCVVirtState *s, const
MemMapEntry *memmap)
}
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
- hwaddr ecam_base, hwaddr ecam_size,
- hwaddr mmio_base, hwaddr mmio_size,
- hwaddr high_mmio_base,
- hwaddr high_mmio_size,
- hwaddr pio_base,
- DeviceState *irqchip)
+ DeviceState *irqchip,
+ RISCVVirtState *s)
{
DeviceState *dev;
MemoryRegion *ecam_alias, *ecam_reg;
MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
+hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base;
+hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size;
+hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base;
+hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size;
+hwaddr high_mmio_base = virt_high_pcie_memmap.base;
+hwaddr high_mmio_size = virt_high_pcie_memmap.size;
+hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base;
+hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size;
qemu_irq irq;
int i;
dev = qdev_new(TYPE_GPEX_HOST);
+/* Set GPEX object properties for the virt machine */
+object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE,
+ecam_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE,
+ecam_size, NULL);
+object_property_set_uint(OBJECT(GPEX_HOST(dev)),
+ PCI_HOST_BELOW_4G_MMIO_BASE,
+ mmio_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)),
PCI_HOST_BELOW_4G_MMIO_SIZE,
+mmio_size, NULL);
+object_property_set_uint(OBJECT(GPEX_HOST(dev)),
+ PCI_HOST_ABOVE_4G_MMIO_BASE,
+ high_mmio_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)),
PCI_HOST_ABOVE_4G_MMIO_SIZE,
+high_mmio_size, NULL);
+object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE,
+pio_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE,
+pio_size, NULL);
+
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
ecam_alias = g_new0(MemoryRegion, 1);
@@ -1094,6 +1118,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion
*sys_mem,
gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
}
+GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus;
return dev;
}
@@ -1492,15 +1517,7 @@ static void virt_machine_init(MachineState *machine)
qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
}
-gpex_pcie_init(system_memory,
- memmap[VIRT_PCIE_ECAM].base,
- memmap[VIRT_PCIE_ECAM].size,
- memmap[VIRT_PCIE_MMIO].base,
- memmap[VIRT_PCIE_MMIO].size,
- virt_high_pcie_memmap.base,
- virt_high_pcie_memmap.size,
- memmap[VIRT_PCIE_PIO].base,
- pcie_irqchip);
+gpex_pcie_init(system_memory, pcie_irqchip, s);
create_platform_bus(s, mmio_irqchip);
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 5b03575ed3..f89790fd58 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -61,6 +61,7 @@ struct RISCVVirtState {
char *oem_table_id;
OnOffAuto acpi;
const MemMapEntry *memmap;
+struct GPEXHost *gpex_host;
};
enum {
--
2.39.2
[PATCH v6 01/13] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location
RISC-V also needs to use the same code to create fw_cfg in DSDT. So,
avoid code duplication by moving the code in arm and riscv to a device
specific file.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/arm/virt-acpi-build.c | 19 ++-
hw/nvram/fw_cfg-acpi.c | 23 +++
hw/nvram/meson.build | 1 +
hw/riscv/virt-acpi-build.c | 19 ++-
include/hw/nvram/fw_cfg_acpi.h | 15 +++
5 files changed, 43 insertions(+), 34 deletions(-)
create mode 100644 hw/nvram/fw_cfg-acpi.c
create mode 100644 include/hw/nvram/fw_cfg_acpi.h
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 9ce136cd88..dd2e95f0ea 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -35,7 +35,7 @@
#include "target/arm/cpu.h"
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
-#include "hw/nvram/fw_cfg.h"
+#include "hw/nvram/fw_cfg_acpi.h"
#include "hw/acpi/bios-linker-loader.h"
#include "hw/acpi/aml-build.h"
#include "hw/acpi/utils.h"
@@ -94,21 +94,6 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry
*uart_memmap,
aml_append(scope, dev);
}
-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
-{
-Aml *dev = aml_device("FWCF");
-aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
-/* device present, functioning, decoding, not shown in UI */
-aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
-aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
-Aml *crs = aml_resource_template();
-aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
- fw_cfg_memmap->size, AML_READ_WRITE));
-aml_append(dev, aml_name_decl("_CRS", crs));
-aml_append(scope, dev);
-}
-
static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
{
Aml *dev, *crs;
@@ -864,7 +849,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
if (vmc->acpi_expose_flash) {
acpi_dsdt_add_flash(scope, [VIRT_FLASH]);
}
-acpi_dsdt_add_fw_cfg(scope, [VIRT_FW_CFG]);
+fw_cfg_acpi_dsdt_add(scope, [VIRT_FW_CFG]);
acpi_dsdt_add_virtio(scope, [VIRT_MMIO],
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
diff --git a/hw/nvram/fw_cfg-acpi.c b/hw/nvram/fw_cfg-acpi.c
new file mode 100644
index 00..4e48baeaa0
--- /dev/null
+++ b/hw/nvram/fw_cfg-acpi.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Add fw_cfg device in DSDT
+ *
+ */
+
+#include "hw/nvram/fw_cfg_acpi.h"
+#include "hw/acpi/aml-build.h"
+
+void fw_cfg_acpi_dsdt_add(Aml *scope, const MemMapEntry *fw_cfg_memmap)
+{
+Aml *dev = aml_device("FWCF");
+aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
+/* device present, functioning, decoding, not shown in UI */
+aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
+aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
+ fw_cfg_memmap->size, AML_READ_WRITE));
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(scope, dev);
+}
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
index 75e415b1a0..4996c72456 100644
--- a/hw/nvram/meson.build
+++ b/hw/nvram/meson.build
@@ -17,3 +17,4 @@ system_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true:
files(
system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
+specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c'))
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 7331248f59..d8772c2821 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -28,6 +28,7 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/aml-build.h"
#include "hw/acpi/utils.h"
+#include "hw/nvram/fw_cfg_acpi.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/reset.h"
@@ -97,22 +98,6 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
}
}
-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
-{
-Aml *dev = aml_device("FWCF");
-aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
-
-/* device present, fu
[PATCH v6 03/13] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT
With common function to add virtio in DSDT created now, update microvm
code also to use it instead of duplicate code.
Suggested-by: Andrew Jones
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/i386/acpi-microvm.c | 15 ++-
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c
index 2909a73933..279da6b4aa 100644
--- a/hw/i386/acpi-microvm.c
+++ b/hw/i386/acpi-microvm.c
@@ -37,6 +37,7 @@
#include "hw/pci/pci.h"
#include "hw/pci/pcie_host.h"
#include "hw/usb/xhci.h"
+#include "hw/virtio/virtio-acpi.h"
#include "hw/virtio/virtio-mmio.h"
#include "hw/input/i8042.h"
@@ -77,19 +78,7 @@ static void acpi_dsdt_add_virtio(Aml *scope,
uint32_t irq = mms->virtio_irq_base + index;
hwaddr base = VIRTIO_MMIO_BASE + index * 512;
hwaddr size = 512;
-
-Aml *dev = aml_device("VR%02u", (unsigned)index);
-aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
-aml_append(dev, aml_name_decl("_UID", aml_int(index)));
-aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
-Aml *crs = aml_resource_template();
-aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
-aml_append(crs,
- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
- AML_EXCLUSIVE, , 1));
-aml_append(dev, aml_name_decl("_CRS", crs));
-aml_append(scope, dev);
+virtio_acpi_dsdt_add(scope, base, size, irq, index, 1);
}
}
}
--
2.39.2
Re: [PATCH v5 02/13] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location
On Thu, Nov 02, 2023 at 09:10:05AM -0300, Daniel Henrique Barboza wrote:
> Alistair, Sunil,
>
> This patch is breaking riscv-to-apply.next build when using 'clang' and
> --enable-debug:
>
> URCE=600 -DNCURSES_WIDECHAR=1 -DSTRUCT_IOVEC_DEFINED -MD -MQ
> libcommon.fa.p/hw_virtio_virtio-acpi.c.o -MF
> libcommon.fa.p/hw_virtio_virtio-acpi.c.o.d -o
> libcommon.fa.p/hw_virtio_virtio-acpi.c.o -c ../hw/virtio/virtio-acpi.c
> ../hw/virtio/virtio-acpi.c:14:12: error: variable 'virtio_base' set but not
> used [-Werror,-Wunused-but-set-variable]
> hwaddr virtio_base = base;
>^
> 1 error generated.
>
>
> Looking at the code:
>
> void virtio_acpi_dsdt_add(Aml *scope, const hwaddr base, const hwaddr size,
> uint32_t mmio_irq, long int start_index, int num)
> {
> long int i;
> hwaddr virtio_base = base; <--
>
> for (i = start_index; i < start_index + num; i++) {
> uint32_t irq = mmio_irq + i;
> Aml *dev = aml_device("VR%02u", (unsigned)i);
> aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
> aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
>
> Aml *crs = aml_resource_template();
> aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
> aml_append(crs,
>aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
> AML_EXCLUSIVE, , 1));
> aml_append(dev, aml_name_decl("_CRS", crs));
> aml_append(scope, dev);
> virtio_base += size; <--
> }
> }
>
> 'virtio_base' is initialized with 'base', and it is incremented in the loop,
> but
> nothing else is done with it.
>
>
> This solves it:
>
>
> $ git diff
> diff --git a/hw/virtio/virtio-acpi.c b/hw/virtio/virtio-acpi.c
> index 682283800f..eaf6028e93 100644
> --- a/hw/virtio/virtio-acpi.c
> +++ b/hw/virtio/virtio-acpi.c
> @@ -11,7 +11,6 @@ void virtio_acpi_dsdt_add(Aml *scope, const hwaddr base,
> const hwaddr size,
>uint32_t mmio_irq, long int start_index, int num)
> {
> long int i;
> -hwaddr virtio_base = base;
> for (i = start_index; i < start_index + num; i++) {
> uint32_t irq = mmio_irq + i;
> @@ -27,6 +26,5 @@ void virtio_acpi_dsdt_add(Aml *scope, const hwaddr base,
> const hwaddr size,
> AML_EXCLUSIVE, , 1));
> aml_append(dev, aml_name_decl("_CRS", crs));
> aml_append(scope, dev);
> -virtio_base += size;
Thanks Daniel for catching this. But proper fix would be to use
virtio_base. Let me send next version with proper fix. Sorry about this.
Thanks,
Sunil
[PATCH v5 06/13] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT
Add IMSIC structure in MADT when IMSIC is configured.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
---
hw/riscv/virt-acpi-build.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 3f9536356e..6bb21014fd 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -270,6 +270,19 @@ static void build_madt(GArray *table_data,
MachineClass *mc = MACHINE_GET_CLASS(s);
MachineState *ms = MACHINE(s);
const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
+uint8_t group_index_bits = imsic_num_bits(riscv_socket_count(ms));
+uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
+uint16_t imsic_max_hart_per_socket = 0;
+uint8_t hart_index_bits;
+uint8_t socket;
+
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
+imsic_max_hart_per_socket = s->soc[socket].num_harts;
+}
+}
+
+hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket);
AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id,
.oem_table_id = s->oem_table_id };
@@ -284,6 +297,28 @@ static void build_madt(GArray *table_data,
riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s);
}
+/* IMSIC */
+if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+/* IMSIC */
+build_append_int_noprefix(table_data, 0x19, 1); /* Type */
+build_append_int_noprefix(table_data, 16, 1); /* Length */
+build_append_int_noprefix(table_data, 1, 1);/* Version */
+build_append_int_noprefix(table_data, 0, 1);/* Reserved */
+build_append_int_noprefix(table_data, 0, 4);/* Flags */
+/* Number of supervisor mode Interrupt Identities */
+build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
+/* Number of guest mode Interrupt Identities */
+build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
+/* Guest Index Bits */
+build_append_int_noprefix(table_data, guest_index_bits, 1);
+/* Hart Index Bits */
+build_append_int_noprefix(table_data, hart_index_bits, 1);
+/* Group Index Bits */
+build_append_int_noprefix(table_data, group_index_bits, 1);
+/* Group Index Shift */
+build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1);
+}
+
acpi_table_end(linker, );
}
--
2.39.2
[PATCH v5 10/13] hw/pci-host/gpex: Define properties for MMIO ranges
ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit
and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of
making these values machine specific, create properties for the GPEX
host bridge with default value 0. During initialization, the firmware
can initialize these properties with correct values for the platform.
This basically allows DSDT generator code independent of the machine
specific memory map accesses.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
---
hw/pci-host/gpex-acpi.c| 13 +
hw/pci-host/gpex.c | 12
include/hw/pci-host/gpex.h | 28
3 files changed, 45 insertions(+), 8 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index 1092dc3b70..f69413ea2c 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -281,3 +281,16 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
crs_range_set_free(_range_set);
}
+
+void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq)
+{
+bool ambig;
+Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, );
+
+if (!obj || ambig) {
+return;
+}
+
+GPEX_HOST(obj)->gpex_cfg.irq = irq;
+acpi_dsdt_add_gpex(scope, _HOST(obj)->gpex_cfg);
+}
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
index a6752fac5e..41f4e73f6e 100644
--- a/hw/pci-host/gpex.c
+++ b/hw/pci-host/gpex.c
@@ -154,6 +154,18 @@ static Property gpex_host_properties[] = {
*/
DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost,
allow_unmapped_accesses, true),
+DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0),
+DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_PIO_SIZE, GPEXHost, gpex_cfg.pio.size, 0),
+DEFINE_PROP_UINT64(PCI_HOST_BELOW_4G_MMIO_BASE, GPEXHost,
+ gpex_cfg.mmio32.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MMIO_SIZE, GPEXHost,
+ gpex_cfg.mmio32.size, 0),
+DEFINE_PROP_UINT64(PCI_HOST_ABOVE_4G_MMIO_BASE, GPEXHost,
+ gpex_cfg.mmio64.base, 0),
+DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost,
+ gpex_cfg.mmio64.size, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h
index b0240bd768..441c6b8b20 100644
--- a/include/hw/pci-host/gpex.h
+++ b/include/hw/pci-host/gpex.h
@@ -40,6 +40,15 @@ struct GPEXRootState {
/*< public >*/
};
+struct GPEXConfig {
+MemMapEntry ecam;
+MemMapEntry mmio32;
+MemMapEntry mmio64;
+MemMapEntry pio;
+int irq;
+PCIBus *bus;
+};
+
struct GPEXHost {
/*< private >*/
PCIExpressHost parent_obj;
@@ -55,19 +64,22 @@ struct GPEXHost {
int irq_num[GPEX_NUM_IRQS];
bool allow_unmapped_accesses;
-};
-struct GPEXConfig {
-MemMapEntry ecam;
-MemMapEntry mmio32;
-MemMapEntry mmio64;
-MemMapEntry pio;
-int irq;
-PCIBus *bus;
+struct GPEXConfig gpex_cfg;
};
int gpex_set_irq_num(GPEXHost *s, int index, int gsi);
void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg);
+void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq);
+
+#define PCI_HOST_PIO_BASE "pio-base"
+#define PCI_HOST_PIO_SIZE "pio-size"
+#define PCI_HOST_ECAM_BASE "ecam-base"
+#define PCI_HOST_ECAM_SIZE "ecam-size"
+#define PCI_HOST_BELOW_4G_MMIO_BASE "below-4g-mmio-base"
+#define PCI_HOST_BELOW_4G_MMIO_SIZE "below-4g-mmio-size"
+#define PCI_HOST_ABOVE_4G_MMIO_BASE "above-4g-mmio-base"
+#define PCI_HOST_ABOVE_4G_MMIO_SIZE "above-4g-mmio-size"
#endif /* HW_GPEX_H */
--
2.39.2
[PATCH v5 08/13] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT
When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the
block size for those extensions need to be communicated via CMO node in
RHCT. Add CMO node in RHCT if any of those CMO extensions are detected.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
---
hw/riscv/virt-acpi-build.c | 64 +-
1 file changed, 56 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index ec49c8804b..506d487ede 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -140,6 +140,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState
*s)
* 5.2.36 RISC-V Hart Capabilities Table (RHCT)
* REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16
* https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
+ * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view
*/
static void build_rhct(GArray *table_data,
BIOSLinker *linker,
@@ -149,8 +150,8 @@ static void build_rhct(GArray *table_data,
MachineState *ms = MACHINE(s);
const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
size_t len, aligned_len;
-uint32_t isa_offset, num_rhct_nodes;
-RISCVCPU *cpu;
+uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
+RISCVCPU *cpu = >soc[0].harts[0];
char *isa;
AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -166,6 +167,9 @@ static void build_rhct(GArray *table_data,
/* ISA + N hart info */
num_rhct_nodes = 1 + ms->smp.cpus;
+if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
+num_rhct_nodes++;
+}
/* Number of RHCT nodes*/
build_append_int_noprefix(table_data, num_rhct_nodes, 4);
@@ -177,7 +181,6 @@ static void build_rhct(GArray *table_data,
isa_offset = table_data->len - table.table_offset;
build_append_int_noprefix(table_data, 0, 2); /* Type 0 */
-cpu = >soc[0].harts[0];
isa = riscv_isa_string(cpu);
len = 8 + strlen(isa) + 1;
aligned_len = (len % 2) ? (len + 1) : len;
@@ -193,14 +196,59 @@ static void build_rhct(GArray *table_data,
build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */
}
+/* CMO node */
+if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
+cmo_offset = table_data->len - table.table_offset;
+build_append_int_noprefix(table_data, 1, 2);/* Type */
+build_append_int_noprefix(table_data, 10, 2); /* Length */
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+build_append_int_noprefix(table_data, 0, 1);/* Reserved */
+
+/* CBOM block size */
+if (cpu->cfg.cbom_blocksize) {
+build_append_int_noprefix(table_data,
+ __builtin_ctz(cpu->cfg.cbom_blocksize),
+ 1);
+} else {
+build_append_int_noprefix(table_data, 0, 1);
+}
+
+/* CBOP block size */
+build_append_int_noprefix(table_data, 0, 1);
+
+/* CBOZ block size */
+if (cpu->cfg.cboz_blocksize) {
+build_append_int_noprefix(table_data,
+ __builtin_ctz(cpu->cfg.cboz_blocksize),
+ 1);
+} else {
+build_append_int_noprefix(table_data, 0, 1);
+}
+}
+
/* Hart Info Node */
for (int i = 0; i < arch_ids->len; i++) {
+len = 16;
+int num_offsets = 1;
build_append_int_noprefix(table_data, 0x, 2); /* Type */
-build_append_int_noprefix(table_data, 16, 2); /* Length */
-build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
-build_append_int_noprefix(table_data, 1, 2);/* Number of offsets */
-build_append_int_noprefix(table_data, i, 4);/* ACPI Processor UID
*/
-build_append_int_noprefix(table_data, isa_offset, 4); /* Offsets[0] */
+
+/* Length */
+if (cmo_offset) {
+len += 4;
+num_offsets++;
+}
+
+build_append_int_noprefix(table_data, len, 2);
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+/* Number of offsets */
+build_append_int_noprefix(table_data, num_offsets, 2);
+build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
+
+/* Offsets */
+build_append_int_noprefix(table_data, isa_offset, 4);
+if (cmo_offset) {
+build_append_int_noprefix(table_data, cmo_offset, 4);
+}
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v5 11/13] hw/riscv/virt: Update GPEX MMIO related properties
Update the GPEX host bridge properties related to MMIO ranges with
values set for the virt machine.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 47 -
include/hw/riscv/virt.h | 1 +
2 files changed, 33 insertions(+), 15 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 085654ab2f..e64886a4d8 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1049,21 +1049,45 @@ static void create_fdt(RISCVVirtState *s, const
MemMapEntry *memmap)
}
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
- hwaddr ecam_base, hwaddr ecam_size,
- hwaddr mmio_base, hwaddr mmio_size,
- hwaddr high_mmio_base,
- hwaddr high_mmio_size,
- hwaddr pio_base,
- DeviceState *irqchip)
+ DeviceState *irqchip,
+ RISCVVirtState *s)
{
DeviceState *dev;
MemoryRegion *ecam_alias, *ecam_reg;
MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
+hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base;
+hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size;
+hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base;
+hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size;
+hwaddr high_mmio_base = virt_high_pcie_memmap.base;
+hwaddr high_mmio_size = virt_high_pcie_memmap.size;
+hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base;
+hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size;
qemu_irq irq;
int i;
dev = qdev_new(TYPE_GPEX_HOST);
+/* Set GPEX object properties for the virt machine */
+object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE,
+ecam_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE,
+ecam_size, NULL);
+object_property_set_uint(OBJECT(GPEX_HOST(dev)),
+ PCI_HOST_BELOW_4G_MMIO_BASE,
+ mmio_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)),
PCI_HOST_BELOW_4G_MMIO_SIZE,
+mmio_size, NULL);
+object_property_set_uint(OBJECT(GPEX_HOST(dev)),
+ PCI_HOST_ABOVE_4G_MMIO_BASE,
+ high_mmio_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)),
PCI_HOST_ABOVE_4G_MMIO_SIZE,
+high_mmio_size, NULL);
+object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE,
+pio_base, NULL);
+object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE,
+pio_size, NULL);
+
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
ecam_alias = g_new0(MemoryRegion, 1);
@@ -1094,6 +1118,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion
*sys_mem,
gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
}
+GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus;
return dev;
}
@@ -1492,15 +1517,7 @@ static void virt_machine_init(MachineState *machine)
qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
}
-gpex_pcie_init(system_memory,
- memmap[VIRT_PCIE_ECAM].base,
- memmap[VIRT_PCIE_ECAM].size,
- memmap[VIRT_PCIE_MMIO].base,
- memmap[VIRT_PCIE_MMIO].size,
- virt_high_pcie_memmap.base,
- virt_high_pcie_memmap.size,
- memmap[VIRT_PCIE_PIO].base,
- pcie_irqchip);
+gpex_pcie_init(system_memory, pcie_irqchip, s);
create_platform_bus(s, mmio_irqchip);
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 5b03575ed3..f89790fd58 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -61,6 +61,7 @@ struct RISCVVirtState {
char *oem_table_id;
OnOffAuto acpi;
const MemMapEntry *memmap;
+struct GPEXHost *gpex_host;
};
enum {
--
2.39.2
[PATCH v5 00/13] RISC-V: ACPI: Enable AIA, PLIC and update RHCT
This series primarily enables external interrupt controllers (AIA and PLIC) in ACPI tables for RISC-V virt platform. It also updates RHCT with CMO and MMU related information. Below ECRs for these changes are approved by ASWG and will be available in next ACPI spec release. 1) MADT (AIA) - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing 2) RHCT - https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view?usp=sharing First two patches in this series are to migrate a couple of functions from ARM architecture to common code so that RISC-V doesn't need to duplicate the same. The patch set is based on Alistair's riscv-to-apply.next branch. These changes are also available in riscv_acpi_b2_v5 branch at: https://github.com/vlsunil/qemu/ Changes since v4: 1) Updated copyright for new files as per SPDX format suggested by Drew. 2) Updated RINTC patch to avoid code duplication as suggested by Drew. 3) Moved mmu offset below cmo in MMU patch as suggested by Drew. 4) Updated tags. Changes since v3: 1) Addressed comments from Daniel and Drew. 2) Added a new patch in microvm to use common function for virtio in DSDT. 3) Rebased to latest riscv-to-apply.next branch and added tags. Changes since v2: 1) Rebased to latest riscv-to-apply.next branch which needed changing ext_icboz to ext_zicboz in CMO patch. 2) Fixed node type in MMU node. 3) Added latest tags. Changes since v1: 1) As per Igor's suggestion, migrated fw_cfg and virtio creation functions to device specific file instead of generic aml-build.c. Since ACPI is optional, new files are created and enabled for build only when CONFIG_ACPI is enabled. 2) As per Igor's suggestion, properties are added to the GPEX PCI host to indicate MMIO ranges. The platform fw can initialize these to appropriate values and the DSDT generator can fetch the information from the host bus itself. This makes the code generic instead of machine specific. 3) Added PLIC patch from Haibo. 4) Rebased to latest riscv-to-apply.next and added RB tags as appropriate. Sunil V L (13): hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location hw/arm/virt-acpi-build.c: Migrate virtio creation to common location hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT hw/riscv: virt: Make few IMSIC macros and functions public hw/riscv/virt-acpi-build.c: Add AIA support in RINTC hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT hw/riscv/virt-acpi-build.c: Add APLIC in the MADT hw/riscv/virt-acpi-build.c: Add CMO information in RHCT hw/riscv/virt-acpi-build.c: Add MMU node in RHCT hw/pci-host/gpex: Define properties for MMIO ranges hw/riscv/virt: Update GPEX MMIO related properties hw/riscv/virt-acpi-build.c: Add IO controllers and devices hw/riscv/virt-acpi-build.c: Add PLIC in MADT hw/arm/virt-acpi-build.c| 51 + hw/i386/acpi-microvm.c | 15 +- hw/nvram/fw_cfg-acpi.c | 23 +++ hw/nvram/meson.build| 1 + hw/pci-host/gpex-acpi.c | 13 ++ hw/pci-host/gpex.c | 12 ++ hw/riscv/Kconfig| 1 + hw/riscv/virt-acpi-build.c | 323 +--- hw/riscv/virt.c | 72 --- hw/virtio/meson.build | 1 + hw/virtio/virtio-acpi.c | 32 include/hw/nvram/fw_cfg_acpi.h | 15 ++ include/hw/pci-host/gpex.h | 28 ++- include/hw/riscv/virt.h | 26 +++ include/hw/virtio/virtio-acpi.h | 16 ++ 15 files changed, 498 insertions(+), 131 deletions(-) create mode 100644 hw/nvram/fw_cfg-acpi.c create mode 100644 hw/virtio/virtio-acpi.c create mode 100644 include/hw/nvram/fw_cfg_acpi.h create mode 100644 include/hw/virtio/virtio-acpi.h -- 2.39.2
[PATCH v5 07/13] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT
Add APLIC structures for each socket in the MADT when system is configured
with APLIC as the external wired interrupt controller.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
---
hw/riscv/virt-acpi-build.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 6bb21014fd..ec49c8804b 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -274,6 +274,8 @@ static void build_madt(GArray *table_data,
uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
uint16_t imsic_max_hart_per_socket = 0;
uint8_t hart_index_bits;
+uint64_t aplic_addr;
+uint32_t gsi_base;
uint8_t socket;
for (socket = 0; socket < riscv_socket_count(ms); socket++) {
@@ -319,6 +321,38 @@ static void build_madt(GArray *table_data,
build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1);
}
+if (s->aia_type != VIRT_AIA_TYPE_NONE) {
+/* APLICs */
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+aplic_addr = s->memmap[VIRT_APLIC_S].base +
+ s->memmap[VIRT_APLIC_S].size * socket;
+gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+build_append_int_noprefix(table_data, 0x1A, 1);/* Type */
+build_append_int_noprefix(table_data, 36, 1); /* Length */
+build_append_int_noprefix(table_data, 1, 1); /* Version */
+build_append_int_noprefix(table_data, socket, 1); /* APLIC ID */
+build_append_int_noprefix(table_data, 0, 4); /* Flags */
+build_append_int_noprefix(table_data, 0, 8); /* Hardware ID
*/
+/* Number of IDCs */
+if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
+build_append_int_noprefix(table_data,
+ s->soc[socket].num_harts,
+ 2);
+} else {
+build_append_int_noprefix(table_data, 0, 2);
+}
+/* Total External Interrupt Sources Supported */
+build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_SOURCES, 2);
+/* Global System Interrupt Base */
+build_append_int_noprefix(table_data, gsi_base, 4);
+/* APLIC Address */
+build_append_int_noprefix(table_data, aplic_addr, 8);
+/* APLIC size */
+build_append_int_noprefix(table_data,
+ s->memmap[VIRT_APLIC_S].size, 4);
+}
+}
+
acpi_table_end(linker, );
}
--
2.39.2
[PATCH v5 02/13] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location
RISC-V also needs to create the virtio in DSDT in the same way as ARM.
So, instead of duplicating the code, move this function to the device
specific file which is common across architectures.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
---
hw/arm/virt-acpi-build.c| 32
hw/virtio/meson.build | 1 +
hw/virtio/virtio-acpi.c | 32
include/hw/virtio/virtio-acpi.h | 16
4 files changed, 53 insertions(+), 28 deletions(-)
create mode 100644 hw/virtio/virtio-acpi.c
create mode 100644 include/hw/virtio/virtio-acpi.h
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index dd2e95f0ea..b73ddd0c38 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -58,6 +58,7 @@
#include "migration/vmstate.h"
#include "hw/acpi/ghes.h"
#include "hw/acpi/viot.h"
+#include "hw/virtio/virtio-acpi.h"
#define ARM_SPI_BASE 32
@@ -118,32 +119,6 @@ static void acpi_dsdt_add_flash(Aml *scope, const
MemMapEntry *flash_memmap)
aml_append(scope, dev);
}
-static void acpi_dsdt_add_virtio(Aml *scope,
- const MemMapEntry *virtio_mmio_memmap,
- uint32_t mmio_irq, int num)
-{
-hwaddr base = virtio_mmio_memmap->base;
-hwaddr size = virtio_mmio_memmap->size;
-int i;
-
-for (i = 0; i < num; i++) {
-uint32_t irq = mmio_irq + i;
-Aml *dev = aml_device("VR%02u", i);
-aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
-aml_append(dev, aml_name_decl("_UID", aml_int(i)));
-aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
-Aml *crs = aml_resource_template();
-aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
-aml_append(crs,
- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
- AML_EXCLUSIVE, , 1));
-aml_append(dev, aml_name_decl("_CRS", crs));
-aml_append(scope, dev);
-base += size;
-}
-}
-
static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
uint32_t irq, VirtMachineState *vms)
{
@@ -850,8 +825,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
acpi_dsdt_add_flash(scope, [VIRT_FLASH]);
}
fw_cfg_acpi_dsdt_add(scope, [VIRT_FW_CFG]);
-acpi_dsdt_add_virtio(scope, [VIRT_MMIO],
-(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
+virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size,
+ (irqmap[VIRT_MMIO] + ARM_SPI_BASE),
+ 0, NUM_VIRTIO_TRANSPORTS);
acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
if (vms->acpi_dev) {
build_ged_aml(scope, "\\_SB."GED_DEVICE,
diff --git a/hw/virtio/meson.build b/hw/virtio/meson.build
index c0055a7832..9d62097a21 100644
--- a/hw/virtio/meson.build
+++ b/hw/virtio/meson.build
@@ -79,3 +79,4 @@ system_ss.add(when: 'CONFIG_ALL', if_true:
files('virtio-stub.c'))
system_ss.add(files('virtio-hmp-cmds.c'))
specific_ss.add_all(when: 'CONFIG_VIRTIO', if_true: specific_virtio_ss)
+system_ss.add(when: 'CONFIG_ACPI', if_true: files('virtio-acpi.c'))
diff --git a/hw/virtio/virtio-acpi.c b/hw/virtio/virtio-acpi.c
new file mode 100644
index 00..682283800f
--- /dev/null
+++ b/hw/virtio/virtio-acpi.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * virtio ACPI Support
+ *
+ */
+
+#include "hw/virtio/virtio-acpi.h"
+#include "hw/acpi/aml-build.h"
+
+void virtio_acpi_dsdt_add(Aml *scope, const hwaddr base, const hwaddr size,
+ uint32_t mmio_irq, long int start_index, int num)
+{
+long int i;
+hwaddr virtio_base = base;
+
+for (i = start_index; i < start_index + num; i++) {
+uint32_t irq = mmio_irq + i;
+Aml *dev = aml_device("VR%02u", (unsigned)i);
+aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
+aml_append(dev, aml_name_decl("_UID", aml_int(i)));
+aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
+aml_append(crs,
+ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, , 1));
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(scope, dev);
+virtio_base += size;
+}
+}
diff --git a/include/hw/virtio/virtio-acpi.h b/include/hw/virtio/virtio-acpi.h
new file mode 100644
inde
[PATCH v5 09/13] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT
MMU type information is available via MMU node in RHCT. Add this node in
RHCT.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
hw/riscv/virt-acpi-build.c | 36 +++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 506d487ede..86c38f7c2b 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -152,6 +152,8 @@ static void build_rhct(GArray *table_data,
size_t len, aligned_len;
uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
RISCVCPU *cpu = >soc[0].harts[0];
+uint32_t mmu_offset = 0;
+uint8_t satp_mode_max;
char *isa;
AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -171,6 +173,10 @@ static void build_rhct(GArray *table_data,
num_rhct_nodes++;
}
+if (cpu->cfg.satp_mode.supported != 0) {
+num_rhct_nodes++;
+}
+
/* Number of RHCT nodes*/
build_append_int_noprefix(table_data, num_rhct_nodes, 4);
@@ -226,6 +232,26 @@ static void build_rhct(GArray *table_data,
}
}
+/* MMU node structure */
+if (cpu->cfg.satp_mode.supported != 0) {
+satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
+mmu_offset = table_data->len - table.table_offset;
+build_append_int_noprefix(table_data, 2, 2);/* Type */
+build_append_int_noprefix(table_data, 8, 2);/* Length */
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+build_append_int_noprefix(table_data, 0, 1);/* Reserved */
+/* MMU Type */
+if (satp_mode_max == VM_1_10_SV57) {
+build_append_int_noprefix(table_data, 2, 1);/* Sv57 */
+} else if (satp_mode_max == VM_1_10_SV48) {
+build_append_int_noprefix(table_data, 1, 1);/* Sv48 */
+} else if (satp_mode_max == VM_1_10_SV39) {
+build_append_int_noprefix(table_data, 0, 1);/* Sv39 */
+} else {
+assert(1);
+}
+}
+
/* Hart Info Node */
for (int i = 0; i < arch_ids->len; i++) {
len = 16;
@@ -238,17 +264,25 @@ static void build_rhct(GArray *table_data,
num_offsets++;
}
+if (mmu_offset) {
+len += 4;
+num_offsets++;
+}
+
build_append_int_noprefix(table_data, len, 2);
build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
/* Number of offsets */
build_append_int_noprefix(table_data, num_offsets, 2);
build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
-
/* Offsets */
build_append_int_noprefix(table_data, isa_offset, 4);
if (cmo_offset) {
build_append_int_noprefix(table_data, cmo_offset, 4);
}
+
+if (mmu_offset) {
+build_append_int_noprefix(table_data, mmu_offset, 4);
+}
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v5 01/13] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location
RISC-V also needs to use the same code to create fw_cfg in DSDT. So,
avoid code duplication by moving the code in arm and riscv to a device
specific file.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
---
hw/arm/virt-acpi-build.c | 19 ++-
hw/nvram/fw_cfg-acpi.c | 23 +++
hw/nvram/meson.build | 1 +
hw/riscv/virt-acpi-build.c | 19 ++-
include/hw/nvram/fw_cfg_acpi.h | 15 +++
5 files changed, 43 insertions(+), 34 deletions(-)
create mode 100644 hw/nvram/fw_cfg-acpi.c
create mode 100644 include/hw/nvram/fw_cfg_acpi.h
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 9ce136cd88..dd2e95f0ea 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -35,7 +35,7 @@
#include "target/arm/cpu.h"
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
-#include "hw/nvram/fw_cfg.h"
+#include "hw/nvram/fw_cfg_acpi.h"
#include "hw/acpi/bios-linker-loader.h"
#include "hw/acpi/aml-build.h"
#include "hw/acpi/utils.h"
@@ -94,21 +94,6 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry
*uart_memmap,
aml_append(scope, dev);
}
-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
-{
-Aml *dev = aml_device("FWCF");
-aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
-/* device present, functioning, decoding, not shown in UI */
-aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
-aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
-Aml *crs = aml_resource_template();
-aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
- fw_cfg_memmap->size, AML_READ_WRITE));
-aml_append(dev, aml_name_decl("_CRS", crs));
-aml_append(scope, dev);
-}
-
static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
{
Aml *dev, *crs;
@@ -864,7 +849,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
if (vmc->acpi_expose_flash) {
acpi_dsdt_add_flash(scope, [VIRT_FLASH]);
}
-acpi_dsdt_add_fw_cfg(scope, [VIRT_FW_CFG]);
+fw_cfg_acpi_dsdt_add(scope, [VIRT_FW_CFG]);
acpi_dsdt_add_virtio(scope, [VIRT_MMIO],
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
diff --git a/hw/nvram/fw_cfg-acpi.c b/hw/nvram/fw_cfg-acpi.c
new file mode 100644
index 00..4e48baeaa0
--- /dev/null
+++ b/hw/nvram/fw_cfg-acpi.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Add fw_cfg device in DSDT
+ *
+ */
+
+#include "hw/nvram/fw_cfg_acpi.h"
+#include "hw/acpi/aml-build.h"
+
+void fw_cfg_acpi_dsdt_add(Aml *scope, const MemMapEntry *fw_cfg_memmap)
+{
+Aml *dev = aml_device("FWCF");
+aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
+/* device present, functioning, decoding, not shown in UI */
+aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
+aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
+ fw_cfg_memmap->size, AML_READ_WRITE));
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(scope, dev);
+}
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
index 75e415b1a0..4996c72456 100644
--- a/hw/nvram/meson.build
+++ b/hw/nvram/meson.build
@@ -17,3 +17,4 @@ system_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true:
files(
system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
+specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c'))
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 7331248f59..d8772c2821 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -28,6 +28,7 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/aml-build.h"
#include "hw/acpi/utils.h"
+#include "hw/nvram/fw_cfg_acpi.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/reset.h"
@@ -97,22 +98,6 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
}
}
-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
-{
-Aml *dev = aml_device("FWCF");
-aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
-
-/* device present, functioning, decoding, not shown in UI *
[PATCH v5 05/13] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC
Update the RINTC structure in MADT with AIA related fields.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
---
hw/riscv/virt-acpi-build.c | 43 ++
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index d8772c2821..3f9536356e 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -38,6 +38,7 @@
#include "hw/intc/riscv_aclint.h"
#define ACPI_BUILD_TABLE_SIZE 0x2
+#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
typedef struct AcpiBuildState {
/* Copy of table in RAM (for patching) */
@@ -59,17 +60,50 @@ static void acpi_align_size(GArray *blob, unsigned align)
static void riscv_acpi_madt_add_rintc(uint32_t uid,
const CPUArchIdList *arch_ids,
- GArray *entry)
+ GArray *entry,
+ RISCVVirtState *s)
{
+uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
uint64_t hart_id = arch_ids->cpus[uid].arch_id;
+uint32_t imsic_size, local_cpu_id, socket_id;
+uint64_t imsic_socket_addr, imsic_addr;
+MachineState *ms = MACHINE(s);
+socket_id = arch_ids->cpus[uid].props.node_id;
+local_cpu_id = (arch_ids->cpus[uid].arch_id -
+riscv_socket_first_hartid(ms, socket_id)) %
+riscv_socket_hart_count(ms, socket_id);
+imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base +
+(socket_id * VIRT_IMSIC_GROUP_MAX_SIZE);
+imsic_size = IMSIC_HART_SIZE(guest_index_bits);
+imsic_addr = imsic_socket_addr + local_cpu_id * imsic_size;
build_append_int_noprefix(entry, 0x18, 1); /* Type */
-build_append_int_noprefix(entry, 20, 1); /* Length */
+build_append_int_noprefix(entry, 36, 1); /* Length */
build_append_int_noprefix(entry, 1, 1); /* Version */
build_append_int_noprefix(entry, 0, 1); /* Reserved */
build_append_int_noprefix(entry, 0x1, 4);/* Flags*/
build_append_int_noprefix(entry, hart_id, 8);/* Hart ID */
build_append_int_noprefix(entry, uid, 4);/* ACPI Processor UID */
+/* External Interrupt Controller ID */
+if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
+build_append_int_noprefix(entry,
+ ACPI_BUILD_INTC_ID(
+ arch_ids->cpus[uid].props.node_id,
+ local_cpu_id),
+ 4);
+} else {
+build_append_int_noprefix(entry, 0, 4);
+}
+
+if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+/* IMSIC Base address */
+build_append_int_noprefix(entry, imsic_addr, 8);
+/* IMSIC Size */
+build_append_int_noprefix(entry, imsic_size, 4);
+} else {
+build_append_int_noprefix(entry, 0, 8);
+build_append_int_noprefix(entry, 0, 4);
+}
}
static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
@@ -88,7 +122,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
aml_int(arch_ids->cpus[i].arch_id)));
/* build _MAT object */
-riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf);
+riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf, s);
aml_append(dev, aml_name_decl("_MAT",
aml_buffer(madt_buf->len,
(uint8_t *)madt_buf->data)));
@@ -227,6 +261,7 @@ static void build_dsdt(GArray *table_data,
* 5.2.12 Multiple APIC Description Table (MADT)
* REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15
* https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
+ * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view
*/
static void build_madt(GArray *table_data,
BIOSLinker *linker,
@@ -246,7 +281,7 @@ static void build_madt(GArray *table_data,
/* RISC-V Local INTC structures per HART */
for (int i = 0; i < arch_ids->len; i++) {
-riscv_acpi_madt_add_rintc(i, arch_ids, table_data);
+riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s);
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v5 13/13] hw/riscv/virt-acpi-build.c: Add PLIC in MADT
Add PLIC structures for each socket in the MADT when system is
configured with PLIC as the external interrupt controller.
Signed-off-by: Haibo Xu
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
---
hw/riscv/virt-acpi-build.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 4d03a27efd..d4a02579d6 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -94,6 +94,12 @@ static void riscv_acpi_madt_add_rintc(uint32_t uid,
arch_ids->cpus[uid].props.node_id,
local_cpu_id),
4);
+} else if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+build_append_int_noprefix(entry,
+ ACPI_BUILD_INTC_ID(
+ arch_ids->cpus[uid].props.node_id,
+ 2 * local_cpu_id + 1),
+ 4);
} else {
build_append_int_noprefix(entry, 0, 4);
}
@@ -494,6 +500,29 @@ static void build_madt(GArray *table_data,
build_append_int_noprefix(table_data,
s->memmap[VIRT_APLIC_S].size, 4);
}
+} else {
+/* PLICs */
+for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+aplic_addr = s->memmap[VIRT_PLIC].base +
+ s->memmap[VIRT_PLIC].size * socket;
+gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+build_append_int_noprefix(table_data, 0x1B, 1); /* Type */
+build_append_int_noprefix(table_data, 36, 1); /* Length */
+build_append_int_noprefix(table_data, 1, 1); /* Version */
+build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */
+build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */
+/* Total External Interrupt Sources Supported */
+build_append_int_noprefix(table_data,
+ VIRT_IRQCHIP_NUM_SOURCES - 1, 2);
+build_append_int_noprefix(table_data, 0, 2); /* Max Priority */
+build_append_int_noprefix(table_data, 0, 4); /* Flags */
+/* PLIC Size */
+build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size,
4);
+/* PLIC Address */
+build_append_int_noprefix(table_data, aplic_addr, 8);
+/* Global System Interrupt Vector Base */
+build_append_int_noprefix(table_data, gsi_base, 4);
+}
}
acpi_table_end(linker, );
--
2.39.2
[PATCH v5 12/13] hw/riscv/virt-acpi-build.c: Add IO controllers and devices
Add basic IO controllers and devices like PCI, VirtIO and UART in the
ACPI namespace.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
---
hw/riscv/Kconfig | 1 +
hw/riscv/virt-acpi-build.c | 79 --
2 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index b6a5eb4452..a50717be87 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -45,6 +45,7 @@ config RISCV_VIRT
select FW_CFG_DMA
select PLATFORM_BUS
select ACPI
+select ACPI_PCI
config SHAKTI_C
bool
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 86c38f7c2b..4d03a27efd 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -27,15 +27,18 @@
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/aml-build.h"
+#include "hw/acpi/pci.h"
#include "hw/acpi/utils.h"
+#include "hw/intc/riscv_aclint.h"
#include "hw/nvram/fw_cfg_acpi.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/riscv/virt.h"
+#include "hw/riscv/numa.h"
+#include "hw/virtio/virtio-acpi.h"
+#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/reset.h"
-#include "migration/vmstate.h"
-#include "hw/riscv/virt.h"
-#include "hw/riscv/numa.h"
-#include "hw/intc/riscv_aclint.h"
#define ACPI_BUILD_TABLE_SIZE 0x2
#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
@@ -132,6 +135,39 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState
*s)
}
}
+static void
+acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
+uint32_t uart_irq)
+{
+Aml *dev = aml_device("COM0");
+aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
+aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(uart_memmap->base,
+ uart_memmap->size, AML_READ_WRITE));
+aml_append(crs,
+aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, _irq, 1));
+aml_append(dev, aml_name_decl("_CRS", crs));
+
+Aml *pkg = aml_package(2);
+aml_append(pkg, aml_string("clock-frequency"));
+aml_append(pkg, aml_int(3686400));
+
+Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301");
+
+Aml *pkg1 = aml_package(1);
+aml_append(pkg1, pkg);
+
+Aml *package = aml_package(2);
+aml_append(package, UUID);
+aml_append(package, pkg1);
+
+aml_append(dev, aml_name_decl("_DSD", package));
+aml_append(scope, dev);
+}
+
/* RHCT Node[N] starts at offset 56 */
#define RHCT_NODE_ARRAY_OFFSET 56
@@ -310,6 +346,8 @@ static void build_dsdt(GArray *table_data,
RISCVVirtState *s)
{
Aml *scope, *dsdt;
+MachineState *ms = MACHINE(s);
+uint8_t socket_count;
const MemMapEntry *memmap = s->memmap;
AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id,
.oem_table_id = s->oem_table_id };
@@ -329,6 +367,29 @@ static void build_dsdt(GArray *table_data,
fw_cfg_acpi_dsdt_add(scope, [VIRT_FW_CFG]);
+socket_count = riscv_socket_count(ms);
+
+acpi_dsdt_add_uart(scope, [VIRT_UART0], UART0_IRQ);
+
+if (socket_count == 1) {
+virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
+ memmap[VIRT_VIRTIO].size,
+ VIRTIO_IRQ, 0, VIRTIO_COUNT);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ);
+} else if (socket_count == 2) {
+virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
+ memmap[VIRT_VIRTIO].size,
+ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
+ VIRTIO_COUNT);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES);
+} else {
+virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
+ memmap[VIRT_VIRTIO].size,
+ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
+ VIRTIO_COUNT);
+acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES *
2);
+}
+
aml_append(dsdt, scope);
/* copy AML table into ACPI tables blob and patch header there */
@@ -465,6 +526,16 @@ static void virt_acpi_build(RISCVVirtState *s,
AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_rhct(tables_blob, tables->linker, s);
+acpi_add_table(table_offsets, tables_
[PATCH v5 04/13] hw/riscv: virt: Make few IMSIC macros and functions public
Some macros and static function related to IMSIC are defined in virt.c.
They are required in virt-acpi-build.c. So, make them public.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
---
hw/riscv/virt.c | 25 +
include/hw/riscv/virt.h | 25 +
2 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 1732c42915..085654ab2f 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -38,7 +38,6 @@
#include "kvm/kvm_riscv.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/riscv_aplic.h"
-#include "hw/intc/riscv_imsic.h"
#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_test.h"
#include "hw/platform-bus.h"
@@ -54,28 +53,6 @@
#include "hw/acpi/aml-build.h"
#include "qapi/qapi-visit-common.h"
-/*
- * The virt machine physical address space used by some of the devices
- * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
- * number of CPUs, and number of IMSIC guest files.
- *
- * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
- * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
- * of virt machine physical address space.
- */
-
-#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
-#if VIRT_IMSIC_GROUP_MAX_SIZE < \
-IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
-#error "Can't accommodate single IMSIC group in address space"
-#endif
-
-#define VIRT_IMSIC_MAX_SIZE(VIRT_SOCKETS_MAX * \
-VIRT_IMSIC_GROUP_MAX_SIZE)
-#if 0x400 < VIRT_IMSIC_MAX_SIZE
-#error "Can't accommodate all IMSIC groups in address space"
-#endif
-
/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
static bool virt_use_kvm_aia(RISCVVirtState *s)
{
@@ -512,7 +489,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
g_free(plic_cells);
}
-static uint32_t imsic_num_bits(uint32_t count)
+uint32_t imsic_num_bits(uint32_t count)
{
uint32_t ret = 0;
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index e5c474b26e..5b03575ed3 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -23,6 +23,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/sysbus.h"
#include "hw/block/flash.h"
+#include "hw/intc/riscv_imsic.h"
#define VIRT_CPUS_MAX_BITS 9
#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
@@ -127,4 +128,28 @@ enum {
bool virt_is_acpi_enabled(RISCVVirtState *s);
void virt_acpi_setup(RISCVVirtState *vms);
+uint32_t imsic_num_bits(uint32_t count);
+
+/*
+ * The virt machine physical address space used by some of the devices
+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+ * number of CPUs, and number of IMSIC guest files.
+ *
+ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
+ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
+ * of virt machine physical address space.
+ */
+
+#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
+#if VIRT_IMSIC_GROUP_MAX_SIZE < \
+IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
+#error "Can't accomodate single IMSIC group in address space"
+#endif
+
+#define VIRT_IMSIC_MAX_SIZE(VIRT_SOCKETS_MAX * \
+VIRT_IMSIC_GROUP_MAX_SIZE)
+#if 0x400 < VIRT_IMSIC_MAX_SIZE
+#error "Can't accomodate all IMSIC groups in address space"
+#endif
+
#endif
--
2.39.2
