Re: [PATCH v3 1/4] hw/intc: Remove loongarch_ipi.c
在 2024/6/5 上午10:15, Jiaxun Yang 写道:
It was missed out in previous commit.
Fixes: b4a12dfc2132 ("hw/intc/loongarch_ipi: Rename as loongson_ipi")
Signed-off-by: Jiaxun Yang
---
Reviewed-by: Song Gao
Thanks.
Song Gao
hw/intc/loongarch_ipi.c | 347
1 file changed, 347 deletions(-)
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
deleted file mode 100644
index 44b3b9c138d6..
--- a/hw/intc/loongarch_ipi.c
+++ /dev/null
@@ -1,347 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * LoongArch ipi interrupt support
- *
- * Copyright (C) 2021 Loongson Technology Corporation Limited
- */
-
-#include "qemu/osdep.h"
-#include "hw/boards.h"
-#include "hw/sysbus.h"
-#include "hw/intc/loongarch_ipi.h"
-#include "hw/irq.h"
-#include "hw/qdev-properties.h"
-#include "qapi/error.h"
-#include "qemu/log.h"
-#include "exec/address-spaces.h"
-#include "migration/vmstate.h"
-#include "target/loongarch/cpu.h"
-#include "trace.h"
-
-static MemTxResult loongarch_ipi_readl(void *opaque, hwaddr addr,
- uint64_t *data,
- unsigned size, MemTxAttrs attrs)
-{
-IPICore *s;
-LoongArchIPI *ipi = opaque;
-uint64_t ret = 0;
-int index = 0;
-
-s = >cpu[attrs.requester_id];
-addr &= 0xff;
-switch (addr) {
-case CORE_STATUS_OFF:
-ret = s->status;
-break;
-case CORE_EN_OFF:
-ret = s->en;
-break;
-case CORE_SET_OFF:
-ret = 0;
-break;
-case CORE_CLEAR_OFF:
-ret = 0;
-break;
-case CORE_BUF_20 ... CORE_BUF_38 + 4:
-index = (addr - CORE_BUF_20) >> 2;
-ret = s->buf[index];
-break;
-default:
-qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr);
-break;
-}
-
-trace_loongarch_ipi_read(size, (uint64_t)addr, ret);
-*data = ret;
-return MEMTX_OK;
-}
-
-static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr,
- MemTxAttrs attrs)
-{
-int i, mask = 0, data = 0;
-
-/*
- * bit 27-30 is mask for byte writing,
- * if the mask is 0, we need not to do anything.
- */
-if ((val >> 27) & 0xf) {
-data = address_space_ldl(env->address_space_iocsr, addr,
- attrs, NULL);
-for (i = 0; i < 4; i++) {
-/* get mask for byte writing */
-if (val & (0x1 << (27 + i))) {
-mask |= 0xff << (i * 8);
-}
-}
-}
-
-data &= mask;
-data |= (val >> 32) & ~mask;
-address_space_stl(env->address_space_iocsr, addr,
- data, attrs, NULL);
-}
-
-static int archid_cmp(const void *a, const void *b)
-{
- CPUArchId *archid_a = (CPUArchId *)a;
- CPUArchId *archid_b = (CPUArchId *)b;
-
- return archid_a->arch_id - archid_b->arch_id;
-}
-
-static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
-{
-CPUArchId apic_id, *found_cpu;
-
-apic_id.arch_id = id;
-found_cpu = bsearch(_id, ms->possible_cpus->cpus,
-ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
-archid_cmp);
-
-return found_cpu;
-}
-
-static CPUState *ipi_getcpu(int arch_id)
-{
-MachineState *machine = MACHINE(qdev_get_machine());
-CPUArchId *archid;
-
-archid = find_cpu_by_archid(machine, arch_id);
-if (archid) {
-return CPU(archid->cpu);
-}
-
-return NULL;
-}
-
-static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
-{
-uint32_t cpuid;
-hwaddr addr;
-CPUState *cs;
-
-cpuid = extract32(val, 16, 10);
-cs = ipi_getcpu(cpuid);
-if (cs == NULL) {
-return MEMTX_DECODE_ERROR;
-}
-
-/* override requester_id */
-addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
-attrs.requester_id = cs->cpu_index;
-send_ipi_data(_CPU(cs)->env, val, addr, attrs);
-return MEMTX_OK;
-}
-
-static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
-{
-uint32_t cpuid;
-hwaddr addr;
-CPUState *cs;
-
-cpuid = extract32(val, 16, 10);
-cs = ipi_getcpu(cpuid);
-if (cs == NULL) {
-return MEMTX_DECODE_ERROR;
-}
-
-/* override requester_id */
-addr = val & 0x;
-attrs.requester_id = cs->cpu_index;
-send_ipi_data(_CPU(cs)->env, val, addr, attrs);
-return MEMTX_OK;
-}
-
-static MemTxResult loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t
val,
-unsigned size, MemTxAttrs attrs)
-{
-LoongArchIPI *ipi = opaque;
-IPICore *s;
-int index = 0;
-uint32_t cpuid;
-uint8_t vector;
-CPUState *cs;
-
-s = >cpu[attrs.requester_id];
-addr &= 0xff;
-trace_loongarch_ipi_write(size, (uint64_t)addr, val);
-switch (addr) {
-case CORE_STATUS_OFF:
-qemu_log_mask(LOG_GUEST_ERROR, "can not be written");
-break;
-case CORE_EN_OFF:
-
Re: [PATCH v3 4/4] hw/intc/loongson_ipi: Replace ipi_getcpu with cpu_by_arch_id
在 2024/6/5 上午10:15, Jiaxun Yang 写道:
cpu_by_arch_id is doing the same thing as our ipi_getcpu logic.
Signed-off-by: Jiaxun Yang
---
Reviewed-by: Song Gao
Thanks.
Song Gao
hw/intc/loongson_ipi.c | 39 +++
1 file changed, 3 insertions(+), 36 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index c8a25b4eb8e2..b3cda5972793 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -118,39 +118,6 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t
val, hwaddr addr,
return MEMTX_OK;
}
-static int archid_cmp(const void *a, const void *b)
-{
- CPUArchId *archid_a = (CPUArchId *)a;
- CPUArchId *archid_b = (CPUArchId *)b;
-
- return archid_a->arch_id - archid_b->arch_id;
-}
-
-static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
-{
-CPUArchId apic_id, *found_cpu;
-
-apic_id.arch_id = id;
-found_cpu = bsearch(_id, ms->possible_cpus->cpus,
-ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
-archid_cmp);
-
-return found_cpu;
-}
-
-static CPUState *ipi_getcpu(int arch_id)
-{
-MachineState *machine = MACHINE(qdev_get_machine());
-CPUArchId *archid;
-
-archid = find_cpu_by_archid(machine, arch_id);
-if (archid) {
-return CPU(archid->cpu);
-}
-
-return NULL;
-}
-
static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
@@ -158,7 +125,7 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
CPUState *cs;
cpuid = extract32(val, 16, 10);
-cs = ipi_getcpu(cpuid);
+cs = cpu_by_arch_id(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
@@ -176,7 +143,7 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
CPUState *cs;
cpuid = extract32(val, 16, 10);
-cs = ipi_getcpu(cpuid);
+cs = cpu_by_arch_id(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
@@ -227,7 +194,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque,
hwaddr addr,
cpuid = extract32(val, 16, 10);
/* IPI status vector */
vector = extract8(val, 0, 5);
-cs = ipi_getcpu(cpuid);
+cs = cpu_by_arch_id(cpuid);
if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
return MEMTX_DECODE_ERROR;
}
Re: [PATCH] target/loongarch: fix a wrong print in cpu dump
在 2024/6/4 下午3:38, lanyanzhi...@ict.ac.cn 写道: From: lanyanzhi description: loongarch_cpu_dump_state() want to dump all loongarch cpu state registers, but there is a tiny typographical error when printing "PRCFG2". Signed-off-by: lanyanzhi --- target/loongarch/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Song Gao Thanks. Song Gao diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index b5c1ec94af..270f711f11 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -707,7 +707,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY); qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 "," " PRCFG3=%016" PRIx64 "\n", - env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3); + env->CSR_PRCFG1, env->CSR_PRCFG2, env->CSR_PRCFG3); qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY); qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV); qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
Re: [PATCH 0/5] hw/mips/loongson3_virt: Implement IPI support
在 2024/6/3 下午11:35, Philippe Mathieu-Daudé 写道: On 16/5/24 12:53, Jiaxun Yang wrote: 在2024年5月8日五月 下午10:41，Philippe Mathieu-Daudé写道： On 8/5/24 15:06, Jiaxun Yang wrote: Hi all, This series enabled IPI support for loongson3 virt board, loosely based on my previous work[1]. It generalized loongarch_ipi device to share among both loongarch and MIPS machines. Signed-off-by: Jiaxun Yang --- Jiaxun Yang (5): hw/intc/loongarch_ipi: Remove pointless MAX_CPU check hw/intc/loongarch_ipi: Rename as loongson_ipi hw/intc/loongson_ipi: Implement IOCSR address space for MIPS So far patches 1-3 queued to hw-misc tree, thanks. Hi Philippe, Thanks! What's your plan with the rest of the series Patches LGTM, but I'd like an Acked-by from Song Gao ;) Patch 1 - 4: Acked-by: Song Gao and patch2 missed to delete the file loongarch_ipi.c. Thanks. Song Gao and earlier MIPS CPS SMP series? No plan, just lack of time :/ Let me know if you need help on testing etc. Thanks
Re: [PATCH 3/5] hw/intc/loongson_ipi: Implement IOCSR address space for MIPS
在 2024/6/4 下午6:35, Jiaxun Yang 写道:
在2024年6月3日六月 下午4:45，Philippe Mathieu-Daudé写道：
[...]
LoongsonIPI should have an array of CPUState[] and MemoryRegion[].
(Or maybe add them to IPICore.)
Expose them as QOM link properties.
Caller wire them while creating the LoongsonIPI.
Then loongson_ipi_realize() resolves them once.
No need to call get_cpu_iocsr_as() and ipi_getcpu() for each MMIO
access IMO.
I was tempted to do so but realized that arch_id might be discontinuous
for LoongArch.
@Song, can you confirm if it's viable?
I confirmed from Bibo that the arch_id may not be continuous in the future.
Thanks.
Song Gao
Thanks
- Jiaxun
+
+if (!iocsr_as) {
+return MEMTX_DECODE_ERROR;
+}
Re: [PATCH] tests/avocado: Update LoongArch bios file
在 2024/6/3 下午11:58, Peter Maydell 写道:
On Thu, 30 May 2024 at 13:59, Song Gao wrote:
The VM uses old bios to boot up only 1 cpu, causing the test case to fail.
Update the bios to solve this problem.
Reported-by: Thomas Huth
Signed-off-by: Song Gao
---
tests/avocado/machine_loongarch.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/avocado/machine_loongarch.py
b/tests/avocado/machine_loongarch.py
index 7d8a3c1fa5..12cc5ed814 100644
--- a/tests/avocado/machine_loongarch.py
+++ b/tests/avocado/machine_loongarch.py
@@ -38,7 +38,7 @@ def test_loongarch64_devices(self):
bios_url = ('https://github.com/yangxiaojuan-loongson/qemu-binary/'
'releases/download/binary-files/QEMU_EFI.fd')
-bios_hash = ('dfc1bfba4853cd763b9d392d0031827e8addbca8')
+bios_hash = ('f4d0966b5117d4cd82327c050dd668741046be69')
This doesn't look right -- the file has the same URL but a different
hash. This causes problems because the test suite on older
versions of QEMU (eg our stable branches) will still be using
this same URL but the old hash. So instead of running the test with
the old BIOS version as they should, they'll skip the test if Avocado
doesn't have the old file in its content cache.
Is it possible for this test to use a file which doesn't change
its contents arbitrarily? e.g. some fixed released version with
a version number. Then if we need to use a newer BIOS version
we can update both the bios_url and the bios_hash, and the
old stable branches will continue to use the old URL and hash
to download the old version they expect.
Thanks for your sugesstion.
I will send a patch to fix it,
Thanks.
Song Gao
Re: [PATCH] tests/qtest: Add numa test for loongarch system
在 2024/5/28 下午4:21, Bibo Mao 写道:
Add numa test case for loongarch system, it passes to run
with command "make check-qtest".
Signed-off-by: Bibo Mao
---
tests/qtest/meson.build | 2 +-
tests/qtest/numa-test.c | 53 +
2 files changed, 54 insertions(+), 1 deletion(-)
Tested-by: Song Gao
Thanks.
Song Gao
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index b98fae6a6d..12792948ff 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -140,7 +140,7 @@ qtests_hppa = ['boot-serial-test'] + \
(config_all_devices.has_key('CONFIG_VGA') ? ['display-vga-test'] : [])
qtests_loongarch64 = qtests_filter + \
- ['boot-serial-test']
+ ['boot-serial-test', 'numa-test']
qtests_m68k = ['boot-serial-test'] + \
qtests_filter
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
index 7aa262dbb9..5518f6596b 100644
--- a/tests/qtest/numa-test.c
+++ b/tests/qtest/numa-test.c
@@ -265,6 +265,54 @@ static void aarch64_numa_cpu(const void *data)
qtest_quit(qts);
}
+static void loongarch64_numa_cpu(const void *data)
+{
+QDict *resp;
+QList *cpus;
+QObject *e;
+QTestState *qts;
+g_autofree char *cli = NULL;
+
+cli = make_cli(data, "-machine "
+"smp.cpus=2,smp.sockets=2,smp.cores=1,smp.threads=1 "
+"-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
+"-numa cpu,node-id=0,socket-id=1,core-id=0,thread-id=0 "
+"-numa cpu,node-id=1,socket-id=0,core-id=0,thread-id=0");
+qts = qtest_init(cli);
+cpus = get_cpus(qts, );
+g_assert(cpus);
+
+while ((e = qlist_pop(cpus))) {
+QDict *cpu, *props;
+int64_t socket, core, thread, node;
+
+cpu = qobject_to(QDict, e);
+g_assert(qdict_haskey(cpu, "props"));
+props = qdict_get_qdict(cpu, "props");
+
+g_assert(qdict_haskey(props, "node-id"));
+node = qdict_get_int(props, "node-id");
+g_assert(qdict_haskey(props, "socket-id"));
+socket = qdict_get_int(props, "socket-id");
+g_assert(qdict_haskey(props, "core-id"));
+core = qdict_get_int(props, "core-id");
+g_assert(qdict_haskey(props, "thread-id"));
+thread = qdict_get_int(props, "thread-id");
+
+if (socket == 0 && core == 0 && thread == 0) {
+g_assert_cmpint(node, ==, 1);
+} else if (socket == 1 && core == 0 && thread == 0) {
+g_assert_cmpint(node, ==, 0);
+} else {
+g_assert(false);
+}
+qobject_unref(e);
+}
+
+qobject_unref(resp);
+qtest_quit(qts);
+}
+
static void pc_dynamic_cpu_cfg(const void *data)
{
QObject *e;
@@ -593,6 +641,11 @@ int main(int argc, char **argv)
aarch64_numa_cpu);
}
+if (!strcmp(arch, "loongarch64")) {
+qtest_add_data_func("/numa/loongarch64/cpu/explicit", args,
+loongarch64_numa_cpu);
+}
+
out:
return g_test_run();
}
Re: [PATCH v2] tests/libqos: Add loongarch virt machine node
在 2024/5/30 上午10:15, Bibo Mao 写道:
Add loongarch virt machine to the graph. It is a modified copy of
the existing riscv virtmachine in riscv-virt-machine.c
It contains a generic-pcihost controller, and an extra function
loongarch_config_qpci_bus() to configure GPEX pci host controller
information, such as ecam and pio_base addresses.
Also hotplug handle checking about TYPE_VIRTIO_IOMMU_PCI device is
added on loongarch virt machine, since virtio_mmu_pci device requires
it.
Signed-off-by: Bibo Mao
Acked-by: Thomas Huth
---
v1 ... v2:
1. Update copyright licence notation with file loongarch-virt-machine.c
---
Tested-by: Song Gao
Thanks.
Song Gao
hw/loongarch/virt.c | 2 +
tests/qtest/libqos/loongarch-virt-machine.c | 115
tests/qtest/libqos/meson.build | 1 +
3 files changed, 118 insertions(+)
create mode 100644 tests/qtest/libqos/loongarch-virt-machine.c
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 3e6e93edf3..2d7f718570 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -45,6 +45,7 @@
#include "sysemu/tpm.h"
#include "sysemu/block-backend.h"
#include "hw/block/flash.h"
+#include "hw/virtio/virtio-iommu.h"
#include "qemu/error-report.h"
static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms,
@@ -1213,6 +1214,7 @@ static HotplugHandler
*virt_get_hotplug_handler(MachineState *machine,
MachineClass *mc = MACHINE_GET_CLASS(machine);
if (device_is_dynamic_sysbus(mc, dev) ||
+object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
memhp_type_supported(dev)) {
return HOTPLUG_HANDLER(machine);
}
diff --git a/tests/qtest/libqos/loongarch-virt-machine.c
b/tests/qtest/libqos/loongarch-virt-machine.c
new file mode 100644
index 00..1eece28eba
--- /dev/null
+++ b/tests/qtest/libqos/loongarch-virt-machine.c
@@ -0,0 +1,115 @@
+/*
+ * libqos driver framework
+ *
+ * Copyright (c) 2018 Emanuele Giuseppe Esposito
+ * Copyright (c) 2024 Loongson Technology Corporation Limited
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2.1 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
Re: tests/avocado: Add LoongArch machine start test
在 2024/5/31 下午1:34, Jiaxun Yang 写道: 在2024年5月31日五月 上午2:52，gaosong写道： 在 2024/5/30 下午9:16, Jiaxun Yang 写道: 在2024年5月30日五月 下午2:00，gaosong写道： [...] FYI, the test does not seem to work anymore - apparently the binaries have changed and now the hashes do not match anymore. Could you please update it? (preferably with some versioned binaries that do not change in the course of time?) Thank you, I had send a patch to fix it. Hi Song, As LoongArch EDK2 support has been merged long ago, do you to make a clean build and add it to pc-bios directory? EDK2 LoongArchVirt under OvmfPkg is being committed to upstream. PR: https://github.com/tianocore/edk2/pull/5208 I meant here: https://gitlab.com/qemu-project/qemu/-/tree/master/pc-bios?ref_type=heads Sorry, I didn't explain it well. We already send a patch[1] to the QEMU community, this patch create a submodule 'roms/edk2-platform', because the LoongArch BIOS code is all in edk2-platform repo. but the QEMU community think that the edk2-platform project is too large. so we plan to move the LoongArch BIOS code from edk2-platfrom to the edk2 repo. The PR[2] is to move edk2-platform to edk2 repo. but not merged in yet. [1]: https://patchew.org/QEMU/260307952ffe5382a55d66a4999034490e04f7df.1691653307.git.lixiang...@loongson.cn/ [2]: https://github.com/tianocore/edk2/pull/5208 Related Discussions : https://lore.kernel.org/all/1f1d3d9f-c3df-4f29-df66-886410994...@xen0n.name/ Thanks. Song Gao Thanks - Jiaxun
Re: tests/avocado: Add LoongArch machine start test
在 2024/5/30 下午9:16, Jiaxun Yang 写道: 在2024年5月30日五月 下午2:00，gaosong写道： [...] FYI, the test does not seem to work anymore - apparently the binaries have changed and now the hashes do not match anymore. Could you please update it? (preferably with some versioned binaries that do not change in the course of time?) Thank you, I had send a patch to fix it. Hi Song, As LoongArch EDK2 support has been merged long ago, do you to make a clean build and add it to pc-bios directory? EDK2 LoongArchVirt under OvmfPkg is being committed to upstream. PR: https://github.com/tianocore/edk2/pull/5208 Thanks Song Gao Thanks - Jiaxun
Re: tests/avocado: Add LoongArch machine start test
在 2024/5/29 下午6:31, Thomas Huth 写道:
On 15/05/2023 13.19, Song Gao wrote:
Add a new test in tests/avocado to check LoongArch virt machine start.
Reviewed-by: Thomas Huth
Signed-off-by: Song Gao
Reviewed-by: Cédric Le Goater
Message-Id: <20230513012744.1885728-1-gaos...@loongson.cn>
---
MAINTAINERS | 1 +
tests/avocado/machine_loongarch.py | 58 ++
2 files changed, 59 insertions(+)
create mode 100644 tests/avocado/machine_loongarch.py
diff --git a/MAINTAINERS b/MAINTAINERS
index ff2aa53bb9..50585117a0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -245,6 +245,7 @@ M: Xiaojuan Yang
S: Maintained
F: target/loongarch/
F: tests/tcg/loongarch64/
+F: tests/avocado/machine_loongarch.py
M68K TCG CPUs
M: Laurent Vivier
diff --git a/tests/avocado/machine_loongarch.py
b/tests/avocado/machine_loongarch.py
new file mode 100644
index 00..7d8a3c1fa5
--- /dev/null
+++ b/tests/avocado/machine_loongarch.py
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# LoongArch virt test.
+#
+# Copyright (c) 2023 Loongson Technology Corporation Limited
+#
+
+from avocado_qemu import QemuSystemTest
+from avocado_qemu import exec_command_and_wait_for_pattern
+from avocado_qemu import wait_for_console_pattern
+
+class LoongArchMachine(QemuSystemTest):
+ KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
+
+ timeout = 120
+
+ def wait_for_console_pattern(self, success_message, vm=None):
+ wait_for_console_pattern(self, success_message,
+ failure_message='Kernel panic - not
syncing',
+ vm=vm)
+
+ def test_loongarch64_devices(self):
+
+ """
+ :avocado: tags=arch:loongarch64
+ :avocado: tags=machine:virt
+ """
+
+ kernel_url =
('https://github.com/yangxiaojuan-loongson/qemu-binary/'
+ 'releases/download/binary-files/vmlinuz.efi')
+ kernel_hash = '951b485b16e3788b6db03a3e1793c067009e31a2'
+ kernel_path = self.fetch_asset(kernel_url,
asset_hash=kernel_hash)
+
+ initrd_url =
('https://github.com/yangxiaojuan-loongson/qemu-binary/'
+ 'releases/download/binary-files/ramdisk')
+ initrd_hash = 'c67658d9b2a447ce7db2f73ba3d373c9b2b90ab2'
+ initrd_path = self.fetch_asset(initrd_url,
asset_hash=initrd_hash)
+
+ bios_url =
('https://github.com/yangxiaojuan-loongson/qemu-binary/'
+ 'releases/download/binary-files/QEMU_EFI.fd')
+ bios_hash = ('dfc1bfba4853cd763b9d392d0031827e8addbca8')
+ bios_path = self.fetch_asset(bios_url, asset_hash=bios_hash)
Hi!
FYI, the test does not seem to work anymore - apparently the binaries
have changed and now the hashes do not match anymore. Could you please
update it? (preferably with some versioned binaries that do not change
in the course of time?)
Thank you, I had send a patch to fix it.
Thanks.
Song Gao
Re: [RFC v2 1/2] target/loongarch: Add loongson binary translation feature
在 2024/5/28 上午9:07, maobibo 写道:
Hi Philippe,
Thanks for reviewing my patch.
I reply inline.
On 2024/5/27 下午6:37, Philippe Mathieu-Daudé wrote:
Hi Bibo,
On 27/5/24 10:35, Bibo Mao wrote:
Loongson Binary Translation (LBT) is used to accelerate binary
translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
eflags (eflags) and x87 fpu stack pointer (ftop).
Now LBT feature is added in kvm mode, not supported in TCG mode since
it is not emulated. There are two feature flags such as forced_features
and default_features for each vcpu, the real feature is still in
cpucfg.
Flag forced_features is parsed from command line, default_features is
parsed from cpu type.
Flag forced_features has higher priority than flag default_features,
default_features will be used if there is no command line option for
LBT
feature. If the feature is not supported with KVM host, it reports
error
and exits if forced_features is set, else it disables feature and
continues
if default_features is set.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu.c | 69
+++
target/loongarch/cpu.h | 12 +
target/loongarch/kvm/kvm.c | 26 ++
target/loongarch/kvm/kvm_loongarch.h | 16 +++
target/loongarch/loongarch-qmp-cmds.c | 2 +-
5 files changed, 124 insertions(+), 1 deletion(-)
+static void loongarch_set_lbt(Object *obj, bool value, Error **errp)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+
+ if (!kvm_enabled()) {
Either set errp, ...
+ return;
+ }
+
+ if (value) {
+ /* Enable binary translation for all architectures */
+ cpu->env.forced_features |= BIT_ULL(LOONGARCH_FEATURE_LBT);
+ } else {
+ /* Disable default features also */
+ cpu->env.default_features &= ~BIT_ULL(LOONGARCH_FEATURE_LBT);
+ }
+}
+
void loongarch_cpu_post_init(Object *obj)
{
object_property_add_bool(obj, "lsx", loongarch_get_lsx,
loongarch_set_lsx);
object_property_add_bool(obj, "lasx", loongarch_get_lasx,
loongarch_set_lasx);
... or only add the property if KVM is enabled:
if (kvm_enabled()) {
Sure, will do. I think this method is better.
By the way bitmap method forced_features/default_feature is variant
of OnOffAuto method. Bitmap method uses two bit, OnOffAuto method uses
separate feature variable. We do not know which method is better or
which is the future trend.
I think the OnOffAuto variable is better.
The default_features is just a copy of cpucfg, and is not required.
Thanks.
Song Gao
Regards
Bibo Mao
+ object_property_add_bool(obj, "lbt", loongarch_get_lbt,
+ loongarch_set_lbt);
}
Re: [PULL 01/10] target/loongarch/kvm: Fix VM recovery from disk failures
在 2024/5/24 下午6:00, Michael Tokarev 写道:
23.05.2024 04:46, Song Gao wrote:
vmstate does not save kvm_state_conter,
which can cause VM recovery from disk to fail.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Song Gao
Acked-by: Peter Xu
Message-Id: <20240508024732.3127792-1-gaos...@loongson.cn>
---
target/loongarch/machine.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
index 9cd9e848d6..08a7fa5370 100644
--- a/target/loongarch/machine.c
+++ b/target/loongarch/machine.c
@@ -145,8 +145,8 @@ static const VMStateDescription vmstate_tlb = {
/* LoongArch CPU state */
const VMStateDescription vmstate_loongarch_cpu = {
.name = "cpu",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (const VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
VMSTATE_UINTTL(env.pc, LoongArchCPU),
@@ -208,6 +208,8 @@ const VMStateDescription vmstate_loongarch_cpu = {
VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
+ VMSTATE_UINT64(kvm_state_counter, LoongArchCPU),
+
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription * const []) {
Should this really be part of any stable releases?
[...]
Wouldn't it break migration between, say, 8.2 with this change
and without?
Yes, I didn't take this into consideration, please ignore this patch.
Thanks.
Song Gao
Thanks,
/mjt
Re: [PATCH 2/2] target/loongarch: Add loongson binary translation feature
在 2024/5/21 下午4:05, Bibo Mao 写道:
Loongson Binary Translation (LBT) is used to accelerate binary
translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
eflags (eflags) and x87 fpu stack pointer (ftop).
Now LBT feature is added in kvm mode, not supported in TCG mode since
it is not emulated. And only LBT feature is added here, LBT register
saving and restoring is not supported since it depeeds on LBT feautre
implemented in KVM kernel.
Signed-off-by: Bibo Mao
---
Reviewed-by: Song Gao
Thanks.
Song Gao
target/loongarch/cpu.c| 32 +++
target/loongarch/cpu.h| 1 +
target/loongarch/loongarch-qmp-cmds.c | 2 +-
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index b5c1ec94af..84254c0f42 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -412,6 +412,9 @@ static void loongarch_la464_initfn(Object *obj)
data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1);
data = FIELD_DP32(data, CPUCFG2, LSPW, 1);
data = FIELD_DP32(data, CPUCFG2, LAM, 1);
+if (kvm_enabled()) {
+data = FIELD_DP32(data, CPUCFG2, LBT_ALL, 7);
+}
env->cpucfg[2] = data;
env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */
@@ -643,12 +646,41 @@ static void loongarch_set_lasx(Object *obj, bool value,
Error **errp)
}
}
+static bool loongarch_get_lbt(Object *obj, Error **errp)
+ {
+LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+bool ret;
+
+ret = false;
+/* lbt is enabled only in kvm mode, not supported in tcg mode */
+if (kvm_enabled() &&
+(FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LBT_ALL) == 7)) {
+ret = true;
+ }
+return ret;
+}
+
+static void loongarch_set_lbt(Object *obj, bool value, Error **errp)
+{
+LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+int lbt;
+
+lbt = 0;
+if (kvm_enabled() && value) {
+/* Enable binary translation for all architectures */
+lbt = 7;
+}
+cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LBT_ALL, lbt);
+}
+
void loongarch_cpu_post_init(Object *obj)
{
object_property_add_bool(obj, "lsx", loongarch_get_lsx,
loongarch_set_lsx);
object_property_add_bool(obj, "lasx", loongarch_get_lasx,
loongarch_set_lasx);
+object_property_add_bool(obj, "lbt", loongarch_get_lbt,
+ loongarch_set_lbt);
}
static void loongarch_cpu_init(Object *obj)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 41b8e6d96d..2021e85303 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -152,6 +152,7 @@ FIELD(CPUCFG2, LLFTP_VER, 15, 3)
FIELD(CPUCFG2, LBT_X86, 18, 1)
FIELD(CPUCFG2, LBT_ARM, 19, 1)
FIELD(CPUCFG2, LBT_MIPS, 20, 1)
+FIELD(CPUCFG2, LBT_ALL, 18, 3)
FIELD(CPUCFG2, LSPW, 21, 1)
FIELD(CPUCFG2, LAM, 22, 1)
diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loongarch-qmp-cmds.c
index 8721a5eb13..c6f6e1ef85 100644
--- a/target/loongarch/loongarch-qmp-cmds.c
+++ b/target/loongarch/loongarch-qmp-cmds.c
@@ -40,7 +40,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
}
static const char *cpu_model_advertised_features[] = {
-"lsx", "lasx", NULL
+"lsx", "lasx", "lbt", NULL
};
CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
Re: [PATCH 1/2] target/loongarch: Add loongarch vector property unconditionally
在 2024/5/21 下午4:05, Bibo Mao 写道:
Currently LSX/LASX vector property is decided by the default value.
Instead vector property should be added unconditionally, and it is
irrelative with its default value. If vector is disabled by default,
vector also can be enabled from command line.
Signed-off-by: Bibo Mao
---
Reviewed-by: Song Gao
Thanks.
Song Gao
target/loongarch/cpu.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index a0cad53676..b5c1ec94af 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -645,16 +645,10 @@ static void loongarch_set_lasx(Object *obj, bool value,
Error **errp)
void loongarch_cpu_post_init(Object *obj)
{
-LoongArchCPU *cpu = LOONGARCH_CPU(obj);
-
-if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
-object_property_add_bool(obj, "lsx", loongarch_get_lsx,
- loongarch_set_lsx);
-}
-if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) {
-object_property_add_bool(obj, "lasx", loongarch_get_lasx,
- loongarch_set_lasx);
-}
+object_property_add_bool(obj, "lsx", loongarch_get_lsx,
+ loongarch_set_lsx);
+object_property_add_bool(obj, "lasx", loongarch_get_lasx,
+ loongarch_set_lasx);
}
static void loongarch_cpu_init(Object *obj)
Re: [PATCH v3 0/6] hw/loongarch: Refine numa memory map
在 2024/5/15 下午5:39, Bibo Mao 写道: One LoongArch virt machine platform, there is limitation for memory map information. The minimum memory size is 256M and minimum memory size for numa node0 is 256M also. With qemu numa qtest, it is possible that memory size of numa node0 is 128M. Limitations for minimum memory size for both total memory and numa node0 is removed here, including acpi srat table, fadt memory map table and fw_cfg memory map table. Also remove numa node about memory region, there is only low memory region and how memory region. --- v2 ... v3: 1. Modify numa test case for loongarch system. 2. Rebase the patch based on the latest version. v1 ... v2: 1. Refresh the patch based on the latest qemu version, solve the confliction issue. 2. Add numa test case for loongarch system. --- Bibo Mao (6): hw/loongarch: Refine acpi srat table for numa memory hw/loongarch: Refine fadt memory table for numa memory hw/loongarch: Refine fwcfg memory map hw/loongarch: Refine system dram memory region hw/loongarch: Remove minimum and default memory size tests/qtest: Add numa test for loongarch system Patches 1 -5 queued to loongarch-next, thanks. Thanks. Song Gao hw/loongarch/acpi-build.c | 58 +++-- hw/loongarch/virt.c | 166 +++--- tests/qtest/meson.build | 2 +- tests/qtest/numa-test.c | 53 4 files changed, 206 insertions(+), 73 deletions(-) base-commit: dafec285bdbfe415ac6823abdc510e0b92c3f094
Re: [PATCH v3 5/6] hw/loongarch: Remove minimum and default memory size
在 2024/5/15 下午5:39, Bibo Mao 写道:
Some qtest test cases such as numa use default memory size of generic
machine class, which is 128M by fault.
Here generic default memory size is used, and also remove minimum memory
size which is 1G originally.
Signed-off-by: Bibo Mao
---
Reviewed-by: Song Gao
Thanks.
Song Gao
hw/loongarch/virt.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index ac980aec8e..7d3d1d1689 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -984,10 +984,6 @@ static void virt_init(MachineState *machine)
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
}
-if (ram_size < 1 * GiB) {
-error_report("ram_size must be greater than 1G.");
-exit(1);
-}
create_fdt(lvms);
/* Create IOCSR space */
@@ -1273,7 +1269,6 @@ static void virt_class_init(ObjectClass *oc, void *data)
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
mc->init = virt_init;
-mc->default_ram_size = 1 * GiB;
mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
mc->default_ram_id = "loongarch.ram";
mc->max_cpus = LOONGARCH_MAX_CPUS;
Re: [PATCH v3 4/6] hw/loongarch: Refine system dram memory region
在 2024/5/15 下午5:39, Bibo Mao 写道:
For system dram memory region, it is not necessary to use numa node
information. There is only low memory region and high memory region.
Remove numa node information for ddr memory region here, it can reduce
memory region number on LoongArch virt machine.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 55 +++--
1 file changed, 18 insertions(+), 37 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index b67d691fa5..ac980aec8e 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -972,14 +972,10 @@ static void virt_init(MachineState *machine)
{
LoongArchCPU *lacpu;
const char *cpu_model = machine->cpu_type;
-ram_addr_t offset = 0;
-ram_addr_t ram_size = machine->ram_size;
-uint64_t highram_size = 0, phyAddr = 0;
MemoryRegion *address_space_mem = get_system_memory();
LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine);
-int nb_numa_nodes = machine->numa_state->num_nodes;
-NodeInfo *numa_info = machine->numa_state->nodes;
int i;
+hwaddr base, size, ram_size = machine->ram_size;
const CPUArchIdList *possible_cpus;
MachineClass *mc = MACHINE_GET_CLASS(machine);
CPUState *cpu;
@@ -1017,40 +1013,27 @@ static void virt_init(MachineState *machine)
fw_cfg_add_memory(machine);
/* Node0 memory */
-memory_region_init_alias(>lowmem, NULL, "loongarch.node0.lowram",
- machine->ram, offset, VIRT_LOWMEM_SIZE);
-memory_region_add_subregion(address_space_mem, phyAddr, >lowmem);
-
-offset += VIRT_LOWMEM_SIZE;
-if (nb_numa_nodes > 0) {
-assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE);
-highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE;
-} else {
-highram_size = ram_size - VIRT_LOWMEM_SIZE;
-}
-phyAddr = VIRT_HIGHMEM_BASE;
-memory_region_init_alias(>highmem, NULL, "loongarch.node0.highram",
- machine->ram, offset, highram_size);
-memory_region_add_subregion(address_space_mem, phyAddr, >highmem);
-
-/* Node1 - Nodemax memory */
-offset += highram_size;
-phyAddr += highram_size;
-
-for (i = 1; i < nb_numa_nodes; i++) {
-MemoryRegion *nodemem = g_new(MemoryRegion, 1);
-g_autofree char *ramName = g_strdup_printf("loongarch.node%d.ram", i);
-memory_region_init_alias(nodemem, NULL, ramName, machine->ram,
- offset, numa_info[i].node_mem);
-memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
-offset += numa_info[i].node_mem;
-phyAddr += numa_info[i].node_mem;
+size = ram_size;
+base = VIRT_LOWMEM_BASE;
+if (size > VIRT_LOWMEM_SIZE) {
+size = VIRT_LOWMEM_SIZE;
}
+memory_region_init_alias(>lowmem, NULL, "loongarch.lowram",
+ machine->ram, base, size);
+memory_region_add_subregion(address_space_mem, base, >lowmem);
+base += size;
+if (ram_size - size) {
+base = VIRT_HIGHMEM_BASE;
+memory_region_init_alias(>highmem, NULL, "loongarch.highram",
+machine->ram, VIRT_LOWMEM_BASE + size, ram_size - size);
+memory_region_add_subregion(address_space_mem, base, >highmem);
+base += ram_size - size;
+ }
an extra space before '}'
Reviewed-by: Song Gao
Thanks.
Song Gao
+
/* initialize device memory address space */
if (machine->ram_size < machine->maxram_size) {
ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
-hwaddr device_mem_base;
if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
error_report("unsupported amount of memory slots: %"PRIu64,
@@ -1064,9 +1047,7 @@ static void virt_init(MachineState *machine)
"%d bytes", TARGET_PAGE_SIZE);
exit(EXIT_FAILURE);
}
-/* device memory base is the top of high memory address. */
-device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB);
-machine_memory_devices_init(machine, device_mem_base, device_mem_size);
+machine_memory_devices_init(machine, base, device_mem_size);
}
/* load the BIOS image. */
Re: [PATCH v3 3/6] hw/loongarch: Refine fwcfg memory map
在 2024/5/15 下午5:39, Bibo Mao 写道:
Memory map table for fwcfg is used for UEFI BIOS, UEFI BIOS uses the first
entry from fwcfg memory map as the first memory HOB, the second memory HOB
will be used if the first memory HOB is used up.
Memory map table for fwcfg does not care about numa node, however in
generic the first memory HOB is part of numa node0, so that runtime
memory of UEFI which is allocated from the first memory HOB is located
at numa node0.
Signed-off-by: Bibo Mao
---
Reviewed-by: Song Gao
Thanks.
Song Gao
hw/loongarch/virt.c | 60 ++---
1 file changed, 57 insertions(+), 3 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index c996305d87..b67d691fa5 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -912,6 +912,62 @@ static const MemoryRegionOps virt_iocsr_misc_ops = {
},
};
+static void fw_cfg_add_memory(MachineState *ms)
+{
+hwaddr base, size, ram_size, gap;
+int nb_numa_nodes, nodes;
+NodeInfo *numa_info;
+
+ram_size = ms->ram_size;
+base = VIRT_LOWMEM_BASE;
+gap = VIRT_LOWMEM_SIZE;
+nodes = nb_numa_nodes = ms->numa_state->num_nodes;
+numa_info = ms->numa_state->nodes;
+if (!nodes) {
+nodes = 1;
+}
+
+/* add fw_cfg memory map of node0 */
+if (nb_numa_nodes) {
+size = numa_info[0].node_mem;
+} else {
+size = ram_size;
+}
+
+if (size >= gap) {
+memmap_add_entry(base, gap, 1);
+size -= gap;
+base = VIRT_HIGHMEM_BASE;
+gap = ram_size - VIRT_LOWMEM_SIZE;
+}
+
+if (size) {
+memmap_add_entry(base, size, 1);
+base += size;
+}
+
+if (nodes < 2) {
+return;
+}
+
+/* add fw_cfg memory map of other nodes */
+size = ram_size - numa_info[0].node_mem;
+gap = VIRT_LOWMEM_BASE + VIRT_LOWMEM_SIZE;
+if (base < gap && (base + size) > gap) {
+/*
+ * memory map for the maining nodes splited into two part
+ * lowram: [base, +(gap - base))
+ * highram: [VIRT_HIGHMEM_BASE, +(size - (gap - base)))
+ */
+memmap_add_entry(base, gap - base, 1);
+size -= gap - base;
+base = VIRT_HIGHMEM_BASE;
+}
+
+ if (size)
+memmap_add_entry(base, size, 1);
+}
+
static void virt_init(MachineState *machine)
{
LoongArchCPU *lacpu;
@@ -958,9 +1014,9 @@ static void virt_init(MachineState *machine)
}
fdt_add_cpu_nodes(lvms);
fdt_add_memory_nodes(machine);
+fw_cfg_add_memory(machine);
/* Node0 memory */
-memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1);
memory_region_init_alias(>lowmem, NULL, "loongarch.node0.lowram",
machine->ram, offset, VIRT_LOWMEM_SIZE);
memory_region_add_subregion(address_space_mem, phyAddr, >lowmem);
@@ -973,7 +1029,6 @@ static void virt_init(MachineState *machine)
highram_size = ram_size - VIRT_LOWMEM_SIZE;
}
phyAddr = VIRT_HIGHMEM_BASE;
-memmap_add_entry(phyAddr, highram_size, 1);
memory_region_init_alias(>highmem, NULL, "loongarch.node0.highram",
machine->ram, offset, highram_size);
memory_region_add_subregion(address_space_mem, phyAddr, >highmem);
@@ -988,7 +1043,6 @@ static void virt_init(MachineState *machine)
memory_region_init_alias(nodemem, NULL, ramName, machine->ram,
offset, numa_info[i].node_mem);
memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
-memmap_add_entry(phyAddr, numa_info[i].node_mem, 1);
offset += numa_info[i].node_mem;
phyAddr += numa_info[i].node_mem;
}
Re: [PATCH v3 2/6] hw/loongarch: Refine fadt memory table for numa memory
在 2024/5/15 下午5:39, Bibo Mao 写道:
One LoongArch virt machine platform, there is limitation for memory
map information. The minimum memory size is 256M and minimum memory
size for numa node0 is 256M also. With qemu numa qtest, it is possible
that memory size of numa node0 is 128M.
Limitations for minimum memory size for both total memory and numa
node0 is removed for fadt numa memory table creation.
Signed-off-by: Bibo Mao
---
Reviewed-by: Song Gao
Thanks.
Song Gao
hw/loongarch/virt.c | 46 ++---
1 file changed, 43 insertions(+), 3 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index f0640d2d80..c996305d87 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -473,6 +473,48 @@ static void fdt_add_memory_node(MachineState *ms,
g_free(nodename);
}
+static void fdt_add_memory_nodes(MachineState *ms)
+{
+hwaddr base, size, ram_size, gap;
+int i, nb_numa_nodes, nodes;
+NodeInfo *numa_info;
+
+ram_size = ms->ram_size;
+base = VIRT_LOWMEM_BASE;
+gap = VIRT_LOWMEM_SIZE;
+nodes = nb_numa_nodes = ms->numa_state->num_nodes;
+numa_info = ms->numa_state->nodes;
+if (!nodes) {
+nodes = 1;
+}
+
+for (i = 0; i < nodes; i++) {
+if (nb_numa_nodes) {
+size = numa_info[i].node_mem;
+} else {
+size = ram_size;
+}
+
+/*
+ * memory for the node splited into two part
+ * lowram: [base, +gap)
+ * highram: [VIRT_HIGHMEM_BASE, +(len - gap))
+ */
+if (size >= gap) {
+fdt_add_memory_node(ms, base, gap, i);
+size -= gap;
+base = VIRT_HIGHMEM_BASE;
+gap = ram_size - VIRT_LOWMEM_SIZE;
+}
+
+if (size) {
+fdt_add_memory_node(ms, base, size, i);
+base += size;
+gap -= size;
+}
+}
+}
+
static void virt_build_smbios(LoongArchVirtMachineState *lvms)
{
MachineState *ms = MACHINE(lvms);
@@ -915,10 +957,10 @@ static void virt_init(MachineState *machine)
lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id;
}
fdt_add_cpu_nodes(lvms);
+fdt_add_memory_nodes(machine);
/* Node0 memory */
memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1);
-fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0);
memory_region_init_alias(>lowmem, NULL, "loongarch.node0.lowram",
machine->ram, offset, VIRT_LOWMEM_SIZE);
memory_region_add_subregion(address_space_mem, phyAddr, >lowmem);
@@ -932,7 +974,6 @@ static void virt_init(MachineState *machine)
}
phyAddr = VIRT_HIGHMEM_BASE;
memmap_add_entry(phyAddr, highram_size, 1);
-fdt_add_memory_node(machine, phyAddr, highram_size, 0);
memory_region_init_alias(>highmem, NULL, "loongarch.node0.highram",
machine->ram, offset, highram_size);
memory_region_add_subregion(address_space_mem, phyAddr, >highmem);
@@ -948,7 +989,6 @@ static void virt_init(MachineState *machine)
offset, numa_info[i].node_mem);
memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
memmap_add_entry(phyAddr, numa_info[i].node_mem, 1);
-fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i);
offset += numa_info[i].node_mem;
phyAddr += numa_info[i].node_mem;
}
Re: [PATCH v3 1/6] hw/loongarch: Refine acpi srat table for numa memory
在 2024/5/15 下午5:39, Bibo Mao 写道:
One LoongArch virt machine platform, there is limitation for memory
map information. The minimum memory size is 256M and minimum memory
size for numa node0 is 256M also. With qemu numa qtest, it is possible
that memory size of numa node0 is 128M.
Limitations for minimum memory size for both total memory and numa
node0 is removed for acpi srat table creation.
Signed-off-by: Bibo Mao
---
Reviewed-by: Song Gao
Thanks.
Song Gao
hw/loongarch/acpi-build.c | 58 +++
1 file changed, 34 insertions(+), 24 deletions(-)
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index 5ef010d4da..af45ce526d 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -166,8 +166,9 @@ static void
build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
{
int i, arch_id, node_id;
-uint64_t mem_len, mem_base;
-int nb_numa_nodes = machine->numa_state->num_nodes;
+hwaddr len, base, gap;
+NodeInfo *numa_info;
+int nodes, nb_numa_nodes = machine->numa_state->num_nodes;
LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(lvms);
const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(machine);
@@ -196,35 +197,44 @@ build_srat(GArray *table_data, BIOSLinker *linker,
MachineState *machine)
build_append_int_noprefix(table_data, 0, 4); /* Reserved */
}
-/* Node0 */
-build_srat_memory(table_data, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE,
- 0, MEM_AFFINITY_ENABLED);
-mem_base = VIRT_HIGHMEM_BASE;
-if (!nb_numa_nodes) {
-mem_len = machine->ram_size - VIRT_LOWMEM_SIZE;
-} else {
-mem_len = machine->numa_state->nodes[0].node_mem - VIRT_LOWMEM_SIZE;
+base = VIRT_LOWMEM_BASE;
+gap = VIRT_LOWMEM_SIZE;
+numa_info = machine->numa_state->nodes;
+nodes = nb_numa_nodes;
+if (!nodes) {
+nodes = 1;
}
-if (mem_len)
-build_srat_memory(table_data, mem_base, mem_len, 0,
MEM_AFFINITY_ENABLED);
-
-/* Node1 - Nodemax */
-if (nb_numa_nodes) {
-mem_base += mem_len;
-for (i = 1; i < nb_numa_nodes; ++i) {
-if (machine->numa_state->nodes[i].node_mem > 0) {
-build_srat_memory(table_data, mem_base,
- machine->numa_state->nodes[i].node_mem, i,
- MEM_AFFINITY_ENABLED);
-mem_base += machine->numa_state->nodes[i].node_mem;
-}
+
+for (i = 0; i < nodes; i++) {
+if (nb_numa_nodes) {
+len = numa_info[i].node_mem;
+} else {
+len = machine->ram_size;
+}
+
+/*
+ * memory for the node splited into two part
+ * lowram: [base, +gap)
+ * highram: [VIRT_HIGHMEM_BASE, +(len - gap))
+ */
+if (len >= gap) {
+build_srat_memory(table_data, base, len, i, MEM_AFFINITY_ENABLED);
+len -= gap;
+base = VIRT_HIGHMEM_BASE;
+gap = machine->ram_size - VIRT_LOWMEM_SIZE;
+}
+
+if (len) {
+build_srat_memory(table_data, base, len, i, MEM_AFFINITY_ENABLED);
+base += len;
+gap -= len;
}
}
if (machine->device_memory) {
build_srat_memory(table_data, machine->device_memory->base,
memory_region_size(>device_memory->mr),
- nb_numa_nodes - 1,
+ nodes - 1,
MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
}
Re: [PATCH] hw/loongarch/virt: Fix FDT memory node address width
在 2024/5/21 上午5:06, Jiaxun Yang 写道:
Higher bits for memory nodes were omitted at qemu_fdt_setprop_cells.
Signed-off-by: Jiaxun Yang
---
This should be stable backported, otherwise DT boot is totally broken.
---
hw/loongarch/virt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Thank you.
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index f0640d2d8035..f97626bacf65 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -463,7 +463,8 @@ static void fdt_add_memory_node(MachineState *ms,
char *nodename = g_strdup_printf("/memory@%" PRIx64, base);
qemu_fdt_add_subnode(ms->fdt, nodename);
-qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, 0, size);
+qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", base >> 32, base,
+ size >> 32, size);
qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
if (ms->numa_state && ms->numa_state->num_nodes) {
---
base-commit: 85ef20f1673feaa083f4acab8cf054df77b0dbed
change-id: 20240520-loongarch-fdt-memnode-e36c01ae9b6e
Best regards,
Re: [PULL 0/5] loongarch-to-apply queue
在 2024/5/16 下午5:28, Peter Maydell 写道: On Thu, 16 May 2024 at 10:12, Song Gao wrote: The following changes since commit 922582ace2df59572a671f5c0c5c6c5c706995e5: Merge tag 'pull-hppa-20240515' of https://gitlab.com/rth7680/qemu into staging (2024-05-15 11:46:58 +0200) are available in the Git repository at: https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240516 for you to fetch changes up to d55d16700a2e2b36c7e34724d4d77f4a75c5243a: target/loongarch/kvm: fpu save the vreg registers high 192bit (2024-05-16 16:32:35 +0800) pull-loongarch-20240516 Bibo Mao (3): hw/loongarch: Add compat machine for 9.1 hw/loongarch: Remove minimum and default memory size tests: Add migration test for loongarch64 RTH: I had a comment about adding the versioned machine type, so we should hold off on applying this until that is resolved, I think. Agreed, We will try resolved it. Thanks for your explanation. Thanks. Song Gao thanks -- PMM
Re: [PATCH] tests/libqos: Add loongarch virt machine node
在 2024/5/14 下午7:51, Bibo Mao 写道:
Add loongarch virt machine to the graph. It is a modified copy of
the existing riscv virtmachine in riscv-virt-machine.c
It contains a generic-pcihost controller, and an extra function
loongarch_config_qpci_bus() to configure GPEX pci host controller
information, such as ecam and pio_base addresses.
Also hotplug handle checking about TYPE_VIRTIO_IOMMU_PCI device is
added on loongarch virt machine, since virtio_mmu_pci device requires
it.
Signed-off-by: Bibo Mao
---
qos-test failed.
6/14 qemu:qtest+qtest-loongarch64 /
qtest-loongarch64/qos-test TIMEOUT 120.01s
killed by signal 11 SIGSEGV
>>> QTEST_QEMU_IMG=./qemu-img
PYTHON=/root/work/code/clean/github/qemu/build/pyvenv/bin/python3
QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon
MALLOC_PERTURB_=47
G_TEST_DBUS_DAEMON=/root/work/code/clean/github/qemu/tests/dbus-vmstate-daemon.sh
QTEST_QEMU_BINARY=./qemu-system-loongarch64
/root/work/code/clean/github/qemu/build/tests/qtest/qos-test --tap -k
― ✀
―
stderr:
qemu-system-loongarch64: ram_size must be greater than 1G.
Broken pipe
../tests/qtest/libqtest.c:195: kill_qemu() tried to terminate QEMU
process but encountered exit status 1 (expected 0)
TAP parsing error: Too few tests run (expected 128, got 60)
I think this patch depends on your numa series and migration series patches.
Thanks.
Song Gao
hw/loongarch/virt.c | 2 +
tests/qtest/libqos/loongarch-virt-machine.c | 114
tests/qtest/libqos/meson.build | 1 +
3 files changed, 117 insertions(+)
create mode 100644 tests/qtest/libqos/loongarch-virt-machine.c
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index db43b2fe4b..7f5ef87be4 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -45,6 +45,7 @@
#include "sysemu/tpm.h"
#include "sysemu/block-backend.h"
#include "hw/block/flash.h"
+#include "hw/virtio/virtio-iommu.h"
#include "qemu/error-report.h"
static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms,
@@ -1212,6 +1213,7 @@ static HotplugHandler
*virt_get_hotplug_handler(MachineState *machine,
MachineClass *mc = MACHINE_GET_CLASS(machine);
if (device_is_dynamic_sysbus(mc, dev) ||
+object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
memhp_type_supported(dev)) {
return HOTPLUG_HANDLER(machine);
}
diff --git a/tests/qtest/libqos/loongarch-virt-machine.c
b/tests/qtest/libqos/loongarch-virt-machine.c
new file mode 100644
index 00..c12089c015
--- /dev/null
+++ b/tests/qtest/libqos/loongarch-virt-machine.c
@@ -0,0 +1,114 @@
+/*
+ * libqos driver framework
+ *
+ * Copyright (c) 2018 Emanuele Giuseppe Esposito
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2.1 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
Re: [PATCH v5 2/3] hw/loongarch: Remove minimum and default memory size
在 2024/5/11 上午11:42, Bibo Mao 写道:
Some qtest test cases such as numa use default memory size of generic
machine class, which is 128M by fault.
Here generic default memory size is used, and also remove minimum memory
size which is 1G originally.
Signed-off-by: Bibo Mao
---
This patch has already appeared in the numa series.
but again.
Reviewed-by: Song Gao
Thanks.
Song Gao
hw/loongarch/virt.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index f24ff5fcf4..d87d9be576 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -890,10 +890,6 @@ static void virt_init(MachineState *machine)
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
}
-if (ram_size < 1 * GiB) {
-error_report("ram_size must be greater than 1G.");
-exit(1);
-}
create_fdt(lvms);
/* Create IOCSR space */
@@ -1198,7 +1194,6 @@ static void virt_class_init(ObjectClass *oc, void *data)
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
mc->init = virt_init;
-mc->default_ram_size = 1 * GiB;
mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
mc->default_ram_id = "loongarch.ram";
mc->max_cpus = LOONGARCH_MAX_CPUS;
Re: [PATCH v5 1/3] hw/loongarch: Add compat machine for 9.1
在 2024/5/11 上午11:42, Bibo Mao 写道:
Since migration test case requires compat machine type support,
compat machine is added for qemu 9.1 here.
Signed-off-by: Bibo Mao
---
Reviewed-by: Song Gao
Thanks.
Song Gao
hw/loongarch/virt.c | 61 +++--
1 file changed, 48 insertions(+), 13 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index f0640d2d80..f24ff5fcf4 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -1231,18 +1231,53 @@ static void virt_class_init(ObjectClass *oc, void *data)
#endif
}
-static const TypeInfo virt_machine_types[] = {
-{
-.name = TYPE_LOONGARCH_VIRT_MACHINE,
-.parent = TYPE_MACHINE,
-.instance_size = sizeof(LoongArchVirtMachineState),
-.class_init = virt_class_init,
-.instance_init = virt_initfn,
-.interfaces = (InterfaceInfo[]) {
- { TYPE_HOTPLUG_HANDLER },
- { }
-},
-}
+#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
+static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
+void *data) \
+{ \
+MachineClass *mc = MACHINE_CLASS(oc); \
+virt_machine_##major##_##minor##_options(mc); \
+mc->desc = "QEMU " # major "." # minor " LoongArch Virtual Machine"; \
+if (latest) { \
+mc->alias = "virt"; \
+} \
+} \
+static const TypeInfo machvirt_##major##_##minor##_info = { \
+.name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
+.parent = TYPE_LOONGARCH_VIRT_MACHINE, \
+.class_init = virt_##major##_##minor##_class_init, \
+}; \
+static void machvirt_machine_##major##_##minor##_init(void) \
+{ \
+type_register_static(_##major##_##minor##_info); \
+} \
+type_init(machvirt_machine_##major##_##minor##_init);
+
+#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
+DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
+#define DEFINE_VIRT_MACHINE(major, minor) \
+DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
+
+static const TypeInfo virt_machine_info = {
+.name = TYPE_LOONGARCH_VIRT_MACHINE,
+.parent = TYPE_MACHINE,
+.abstract = true,
+.instance_size = sizeof(LoongArchVirtMachineState),
+.class_init = virt_class_init,
+.instance_init = virt_initfn,
+.interfaces = (InterfaceInfo[]) {
+{ TYPE_HOTPLUG_HANDLER },
+{ }
+},
};
-DEFINE_TYPES(virt_machine_types)
+static void machvirt_machine_init(void)
+{
+type_register_static(_machine_info);
+}
+type_init(machvirt_machine_init);
+
+static void virt_machine_9_1_options(MachineClass *mc)
+{
+}
+DEFINE_VIRT_MACHINE_AS_LATEST(9, 1)
Re: [PATCH v5 3/3] tests: Add migration test for loongarch64
在 2024/5/11 上午11:42, Bibo Mao 写道:
This patch adds migration test support for loongarch64. The test code
comes from aarch64 mostly, only that it booted as bios in qemu since
kernel requires elf format and bios uses binary format.
In addition to providing the binary, this patch also includes the source
code and the build script in tests/migration/loongarch64. So users can
change the source and/or re-compile the binary as they wish.
Signed-off-by: Bibo Mao
Acked-by: Thomas Huth
Acked-by: Peter Xu
Reviewed-by: Fabiano Rosas
---
Tested-by: Song Gao
Reviewed-by: Song Gao
Thanks.
Song Gao
tests/migration/Makefile | 2 +-
tests/migration/loongarch64/Makefile | 18 +
tests/migration/loongarch64/a-b-kernel.S | 49
tests/migration/loongarch64/a-b-kernel.h | 16
tests/migration/migration-test.h | 3 ++
tests/qtest/meson.build | 2 +-
tests/qtest/migration-test.c | 10 +
7 files changed, 98 insertions(+), 2 deletions(-)
create mode 100644 tests/migration/loongarch64/Makefile
create mode 100644 tests/migration/loongarch64/a-b-kernel.S
create mode 100644 tests/migration/loongarch64/a-b-kernel.h
diff --git a/tests/migration/Makefile b/tests/migration/Makefile
index 13e99b1692..cfebfe23f8 100644
--- a/tests/migration/Makefile
+++ b/tests/migration/Makefile
@@ -5,7 +5,7 @@
# See the COPYING file in the top-level directory.
#
-TARGET_LIST = i386 aarch64 s390x
+TARGET_LIST = i386 aarch64 s390x loongarch64
SRC_PATH = ../..
diff --git a/tests/migration/loongarch64/Makefile b/tests/migration/loongarch64/Makefile
new file mode 100644
index 00..5d8719205f
--- /dev/null
+++ b/tests/migration/loongarch64/Makefile
@@ -0,0 +1,18 @@
+# To specify cross compiler prefix, use CROSS_PREFIX=
+# $ make CROSS_PREFIX=loongarch64-linux-gnu-
+
+.PHONY: all clean
+all: a-b-kernel.h
+
+a-b-kernel.h: loongarch64.kernel
+ echo "$$__note" > $@
+ xxd -i $< | sed -e 's/.*int.*//' >> $@
+
+loongarch64.kernel: loongarch64.elf
+ $(CROSS_PREFIX)objcopy -j .text -O binary $< $@
+
+loongarch64.elf: a-b-kernel.S
+ $(CROSS_PREFIX)gcc -o $@ -nostdlib -Wl,--build-id=none $<
+
+clean:
+ $(RM) *.kernel *.elf
diff --git a/tests/migration/loongarch64/a-b-kernel.S
b/tests/migration/loongarch64/a-b-kernel.S
new file mode 100644
index 00..cd543345fe
--- /dev/null
+++ b/tests/migration/loongarch64/a-b-kernel.S
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2024 Loongson Technology Corporation Limited
+ */
+#include "../migration-test.h"
+
+#define LOONGARCH_CSR_CRMD 0
+#define LOONGARCH_VIRT_UART 0x1FE001E0
+.section .text
+
+.globl _start
+_start:
+/* output char 'A' to UART16550 */
+li.d$t0, LOONGARCH_VIRT_UART
+li.w$t1, 'A'
+st.b$t1, $t0, 0
+
+/* traverse test memory region */
+li.d$t0, LOONGARCH_TEST_MEM_START
+li.d$t1, LOONGARCH_TEST_MEM_END
+li.d$t2, TEST_MEM_PAGE_SIZE
+li.d$t4, LOONGARCH_VIRT_UART
+li.w$t5, 'B'
+
+clean:
+st.b$zero, $t0, 0
+add.d $t0, $t0, $t2
+bne $t0, $t1, clean
+/* keeps a counter so we can limit the output speed */
+addi.d $t6, $zero, 0
+
+mainloop:
+li.d$t0, LOONGARCH_TEST_MEM_START
+
+innerloop:
+ld.bu $t3, $t0, 0
+addi.w $t3, $t3, 1
+ext.w.b $t3, $t3
+st.b$t3, $t0, 0
+add.d $t0, $t0, $t2
+bne $t0, $t1, innerloop
+
+addi.d $t6, $t6, 1
+andi$t6, $t6, 31
+bnez$t6, mainloop
+
+st.b$t5, $t4, 0
+b mainloop
+nop
diff --git a/tests/migration/loongarch64/a-b-kernel.h
b/tests/migration/loongarch64/a-b-kernel.h
new file mode 100644
index 00..b3fe466754
--- /dev/null
+++ b/tests/migration/loongarch64/a-b-kernel.h
@@ -0,0 +1,16 @@
+/* This file is automatically generated from the assembly file in
+* tests/migration/loongarch64. Edit that file and then run "make all"
+* inside tests/migration to update, and then remember to send both
+* the header and the assembler differences in your patch submission.
+*/
+unsigned char loongarch64_kernel[] = {
+ 0x0c, 0xc0, 0x3f, 0x14, 0x8c, 0x81, 0x87, 0x03, 0x0d, 0x04, 0x81, 0x03,
+ 0x8d, 0x01, 0x00, 0x29, 0x0c, 0x00, 0x04, 0x14, 0x0d, 0x80, 0x0c, 0x14,
+ 0x2e, 0x00, 0x00, 0x14, 0x10, 0xc0, 0x3f, 0x14, 0x10, 0x82, 0x87, 0x03,
+ 0x11, 0x08, 0x81, 0x03, 0x80, 0x01, 0x00, 0x29, 0x8c, 0xb9, 0x10, 0x00,
+ 0x8d, 0xf9, 0xff, 0x5f, 0x12, 0x00, 0xc0, 0x02, 0x0c, 0x00, 0x04, 0x14,
+ 0x8f, 0x01, 0x00, 0x2a, 0xef, 0x05, 0x80, 0x02, 0xef, 0x5d, 0x00, 0x00,
+ 0x8f, 0x01, 0x00, 0x29, 0x8c, 0xb9, 0x10, 0x00, 0x8d, 0xed, 0xff, 0x5f,
+ 0x52, 0x06, 0xc0, 0x02, 0x52, 0x7e, 0x40, 0x03, 0x5f, 0xde, 0xff, 0x47,
+ 0x11, 0x02, 0x00, 0x29, 0xff, 0xd7, 0xff, 0x53, 0x00, 0x00, 0x40, 0x03
+};
diff --git a/tests/migration/migration-test.h b/tests/migration/migration-test.h
Re: [PATCH v2 0/6] hw/loongarch: Refine numa memory map
在 2024/5/7 上午11:48, Bibo Mao 写道: One LoongArch virt machine platform, there is limitation for memory map information. The minimum memory size is 256M and minimum memory size for numa node0 is 256M also. With qemu numa qtest, it is possible that memory size of numa node0 is 128M. Limitations for minimum memory size for both total memory and numa node0 is removed here, including acpi srat table, fadt memory map table and fw_cfg memory map table. Also remove numa node about memory region, there is only low memory region and how memory region. Hi, This series need rebase. And for this series. Reviewed-by: Song Gao Thanks. Song Gao --- v1 ... v2: 1. Refresh the patch based on the latest qemu version, solve the confliction issue. 2. Add numa test case for loongarch system. --- Bibo Mao (6): hw/loongarch: Refine acpi srat table for numa memory hw/loongarch: Refine fadt memory table for numa memory hw/loongarch: Refine fwcfg memory map hw/loongarch: Refine system dram memory region hw/loongarch: Remove minimum and default memory size tests/qtest: Add numa test for loongarch system hw/loongarch/acpi-build.c | 58 +++-- hw/loongarch/virt.c | 167 +++--- tests/qtest/meson.build | 2 + 3 files changed, 154 insertions(+), 73 deletions(-) base-commit: 248f6f62df073a3b4158fd0093863ab885feabb5
Re: [PATCH] hw/loongarch: Add VM mode in IOCSR feature register in kvm mode
在 2024/5/14 上午10:51, Bibo Mao 写道:
If VM runs in kvm mode, VM mode is added in IOCSR feature register.
So guest can detect kvm hypervisor type and enable possible pv functions.
Signed-off-by: Bibo Mao
---
Reviewed-by: Song Gao
Thanks.
Song Gao
hw/loongarch/virt.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index d87d9be576..44bcf25aee 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -10,6 +10,7 @@
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/char/serial.h"
+#include "sysemu/kvm.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
#include "sysemu/runstate.h"
@@ -840,18 +841,23 @@ static void virt_iocsr_misc_write(void *opaque, hwaddr
addr,
static uint64_t virt_iocsr_misc_read(void *opaque, hwaddr addr, unsigned size)
{
+uint64_t ret;
+
switch (addr) {
case VERSION_REG:
return 0x11ULL;
case FEATURE_REG:
-return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI |
- 1ULL << IOCSRF_CSRIPI;
+ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI);
+if (kvm_enabled()) {
+ret |= BIT(IOCSRF_VM);
+}
+return ret;
case VENDOR_REG:
return 0x6e6f73676e6f6f4cULL; /* "Loongson" */
case CPUNAME_REG:
return 0x303030354133ULL; /* "3A5000" */
case MISC_FUNC_REG:
-return 1ULL << IOCSRM_EXTIOI_EN;
+return BIT_ULL(IOCSRM_EXTIOI_EN);
}
return 0ULL;
}
Re: [PATCH] tcg/loongarch64: Fill out tcg_out_{ld, st} for vector regs
在 2024/5/10 下午5:12, Richard Henderson 写道:
TCG register spill/fill uses tcg_out_ld/st with all types,
not necessarily going through INDEX_op_{ld,st}_vec.
Cc: qemu-sta...@nongnu.org
Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2336
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 103 ---
1 file changed, 80 insertions(+), 23 deletions(-)
Tested-by: Song Gao
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 69c5b8ac4f..06ca1ab11c 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -808,18 +808,88 @@ static void tcg_out_ldst(TCGContext *s, LoongArchInsn
opc, TCGReg data,
}
}
-static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg dest,
+ TCGReg base, intptr_t offset)
{
-bool is_32bit = type == TCG_TYPE_I32;
-tcg_out_ldst(s, is_32bit ? OPC_LD_W : OPC_LD_D, arg, arg1, arg2);
+switch (type) {
+case TCG_TYPE_I32:
+if (dest < TCG_REG_V0) {
+tcg_out_ldst(s, OPC_LD_W, dest, base, offset);
+} else {
+tcg_out_dupm_vec(s, TCG_TYPE_I128, MO_32, dest, base, offset);
+}
+break;
+case TCG_TYPE_I64:
+if (dest < TCG_REG_V0) {
+tcg_out_ldst(s, OPC_LD_D, dest, base, offset);
+} else {
+tcg_out_dupm_vec(s, TCG_TYPE_I128, MO_64, dest, base, offset);
+}
+break;
+case TCG_TYPE_V128:
+if (-0x800 <= offset && offset <= 0x7ff) {
+tcg_out_opc_vld(s, dest, base, offset);
+} else {
+tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset);
+tcg_out_opc_vldx(s, dest, base, TCG_REG_TMP0);
+}
+break;
+default:
+g_assert_not_reached();
+}
}
-static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src,
+ TCGReg base, intptr_t offset)
{
-bool is_32bit = type == TCG_TYPE_I32;
-tcg_out_ldst(s, is_32bit ? OPC_ST_W : OPC_ST_D, arg, arg1, arg2);
+switch (type) {
+case TCG_TYPE_I32:
+if (src < TCG_REG_V0) {
+tcg_out_ldst(s, OPC_ST_W, src, base, offset);
+} else {
+/* TODO: Could use fst_s, fstx_s */
+if (offset < -0x100 || offset > 0xff || (offset & 3)) {
+if (-0x800 <= offset && offset <= 0x7ff) {
+tcg_out_opc_addi_d(s, TCG_REG_TMP0, base, offset);
+} else {
+tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset);
+tcg_out_opc_add_d(s, TCG_REG_TMP0, TCG_REG_TMP0, base);
+}
+base = TCG_REG_TMP0;
+offset = 0;
+}
+tcg_out_opc_vstelm_w(s, src, base, offset, 0);
+}
+break;
+case TCG_TYPE_I64:
+if (src < TCG_REG_V0) {
+tcg_out_ldst(s, OPC_ST_D, src, base, offset);
+} else {
+/* TODO: Could use fst_d, fstx_d */
+if (offset < -0x100 || offset > 0xff || (offset & 7)) {
+if (-0x800 <= offset && offset <= 0x7ff) {
+tcg_out_opc_addi_d(s, TCG_REG_TMP0, base, offset);
+} else {
+tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset);
+tcg_out_opc_add_d(s, TCG_REG_TMP0, TCG_REG_TMP0, base);
+}
+base = TCG_REG_TMP0;
+offset = 0;
+}
+tcg_out_opc_vstelm_d(s, src, base, offset, 0);
+}
+break;
+case TCG_TYPE_V128:
+if (-0x800 <= offset && offset <= 0x7ff) {
+tcg_out_opc_vst(s, src, base, offset);
+} else {
+tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset);
+tcg_out_opc_vstx(s, src, base, TCG_REG_TMP0);
+}
+break;
+default:
+g_assert_not_reached();
+}
}
static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
@@ -1740,7 +1810,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
{
TCGType type = vecl + TCG_TYPE_V64;
TCGArg a0, a1, a2, a3;
-TCGReg temp = TCG_REG_TMP0;
TCGReg temp_vec = TCG_VEC_TMP0;
static const LoongArchInsn cmp_vec_insn[16][4] = {
@@ -1820,22 +1889,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
switch (opc) {
case INDEX_op_st_vec:
-/* Try to fit vst imm */
-if (-0x800 <= a2 && a2 <= 0x7ff) {
-tcg_out_opc_vst(s, a0, a1, a2);
-} else {
-tcg_out_movi(s, TCG_TYPE_I64, temp, a2);
-
Re: [PATCH] hw/loongarch/virt: Fix memory leak
在 2024/5/7 下午5:52, Michael Tokarev 写道:
07.05.2024 05:22, Song Gao wrote:
for (i = 1; i < nb_numa_nodes; i++) {
MemoryRegion *nodemem = g_new(MemoryRegion, 1);
- ramName = g_strdup_printf("loongarch.node%d.ram", i);
+ g_autofree char *ramName =
g_strdup_printf("loongarch.node%d.ram", i);
Can't this be a fixed-size buffer on stack?
Maybe I'm old-minded, but such obviously fixed and
very small allocations on the heap hurt my eyes ;)
I had send v2 patch.
Thanks.
Song Gao
/mjt
Re: [PATCH] target/loongarch/kvm: Fix VM recovery from disk failures
Thanks for the comments !
在 2024/5/2 下午8:45, Fabiano Rosas 写道:
Peter Xu writes:
On Tue, Apr 30, 2024 at 11:00:24AM -0300, Fabiano Rosas wrote:
Philippe Mathieu-Daudé writes:
(Cc'ing migration maintainers)
On 30/4/24 03:23, Song Gao wrote:
vmstate does not save kvm_state_conter,
which can cause VM recovery from disk to fail.
Cc: qemu-sta...@nongnu.org
Fixes: d11681c94f ("target/loongarch: Implement kvm_arch_init_vcpu")
Signed-off-by: Song Gao
---
target/loongarch/machine.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
index c7029fb9b4..4cd1bf06ff 100644
--- a/target/loongarch/machine.c
+++ b/target/loongarch/machine.c
@@ -191,6 +191,8 @@ const VMStateDescription vmstate_loongarch_cpu = {
VMSTATE_STRUCT_ARRAY(env.tlb, LoongArchCPU, LOONGARCH_TLB_MAX,
0, vmstate_tlb, LoongArchTLB),
+VMSTATE_UINT64(kvm_state_counter, LoongArchCPU),
+
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription * const []) {
The migration stream is versioned, so you should increase it,
but this field is only relevant for KVM (it shouldn't be there
in non-KVM builds). IMHO the correct migration way to fix that
is (untested):
-- >8 --
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
index c7029fb9b4..08032c6d71 100644
--- a/target/loongarch/machine.c
+++ b/target/loongarch/machine.c
@@ -8,8 +8,27 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "migration/cpu.h"
+#include "sysemu/kvm.h"
#include "vec.h"
+#ifdef CONFIG_KVM
+static bool kvmcpu_needed(void *opaque)
+{
+return kvm_enabled();
+}
+
+static const VMStateDescription vmstate_kvmtimer = {
+.name = "cpu/kvmtimer",
+.version_id = 1,
+.minimum_version_id = 1,
+.needed = kvmcpu_needed,
+.fields = (const VMStateField[]) {
+VMSTATE_UINT64(kvm_state_counter, LoongArchCPU),
+VMSTATE_END_OF_LIST()
+}
+};
+#endif /* CONFIG_KVM */
+
static const VMStateDescription vmstate_fpu_reg = {
.name = "fpu_reg",
.version_id = 1,
@@ -194,6 +213,9 @@ const VMStateDescription vmstate_loongarch_cpu = {
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription * const []) {
+#ifdef CONFIG_KVM
+_kvmcpu,
+#endif
_fpu,
_lsx,
_lasx,
---
LGTM, I'd just leave only the .needed function under CONFIG_KVM instead
of the whole subsection.
But when !KVM it means there's no ".needed" and it'll still be migrated?
I expressed myself poorly, I meant put the return from .needed under
CONFIG_KVM. But that is not even necessary, kvm_enabled() is enough.
IMHO it depends on whether loongarch is in the state already of trying to
keep its ABI at all. I think we should still try to enjoy the time when
that ABI is not required, then we can simply add whatever fields, and let
things break with no big deal.
Note that if with CONFIG_KVM it means it can break migration between kvm
v.s. tcg when only one qemu enabled kvm when compile.
Just remove CONIFG_KVM would be OK?
Thanks.
Song Gao
Considering the
patch is from the maintainer (which seems to say "breaking that is all
fine!") I'd say the original patch looks good actually, as it allows kvm /
tcg migrations too as a baseline.
I'm fine with this approach as well.
Thanks,
Re: [PULL 3/5] hw/loongarch: Add numa support
在 2024/5/3 下午8:50, Peter Maydell 写道:
On Fri, 16 Jun 2023 at 11:03, Song Gao wrote:
From: Tianrui Zhao
1. Implement some functions for LoongArch numa support;
2. Implement fdt_add_memory_node() for fdt;
3. build_srat() fills node_id and adds build numa memory.
Reviewed-by: Song Gao
Signed-off-by: Tianrui Zhao
Signed-off-by: Song Gao
Message-Id: <20230613122613.2471743-1-zhaotian...@loongson.cn>
Hi; Coverity has pointed out a memory leak in this commit
(CID 1544773):
@@ -799,17 +823,43 @@ static void loongarch_init(MachineState *machine)
machine->possible_cpus->cpus[i].cpu = OBJECT(cpu);
}
fdt_add_cpu_nodes(lams);
-/* Add memory region */
-memory_region_init_alias(>lowmem, NULL, "loongarch.lowram",
- machine->ram, 0, 256 * MiB);
-memory_region_add_subregion(address_space_mem, offset, >lowmem);
-offset += 256 * MiB;
-memmap_add_entry(0, 256 * MiB, 1);
-highram_size = ram_size - 256 * MiB;
-memory_region_init_alias(>highmem, NULL, "loongarch.highmem",
- machine->ram, offset, highram_size);
-memory_region_add_subregion(address_space_mem, 0x9000, >highmem);
-memmap_add_entry(0x9000, highram_size, 1);
+
+/* Node0 memory */
+memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1);
+fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0);
+memory_region_init_alias(>lowmem, NULL, "loongarch.node0.lowram",
+ machine->ram, offset, VIRT_LOWMEM_SIZE);
+memory_region_add_subregion(address_space_mem, phyAddr, >lowmem);
+
+offset += VIRT_LOWMEM_SIZE;
+if (nb_numa_nodes > 0) {
+assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE);
+highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE;
+} else {
+highram_size = ram_size - VIRT_LOWMEM_SIZE;
+}
+phyAddr = VIRT_HIGHMEM_BASE;
+memmap_add_entry(phyAddr, highram_size, 1);
+fdt_add_memory_node(machine, phyAddr, highram_size, 0);
+memory_region_init_alias(>highmem, NULL, "loongarch.node0.highram",
+ machine->ram, offset, highram_size);
+memory_region_add_subregion(address_space_mem, phyAddr, >highmem);
+
+/* Node1 - Nodemax memory */
+offset += highram_size;
+phyAddr += highram_size;
+
+for (i = 1; i < nb_numa_nodes; i++) {
+MemoryRegion *nodemem = g_new(MemoryRegion, 1);
+ramName = g_strdup_printf("loongarch.node%d.ram", i);
+memory_region_init_alias(nodemem, NULL, ramName, machine->ram,
+ offset, numa_info[i].node_mem);
+memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
+memmap_add_entry(phyAddr, numa_info[i].node_mem, 1);
+fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i);
+offset += numa_info[i].node_mem;
+phyAddr += numa_info[i].node_mem;
In this loop, we allocate memory via g_strdup_printf(),
but never free it. The nicest fix for this is to use the
g_autofree mechanism so that the memory is automatically
freed when execution reaches the end of the block:
g_autofree ramName = g_strdup_printf("", ...);
Thank you. I will fix it.
Thanks
Song Gao
thanks
-- PMM
Re: [PATCH 0/5] hw/loongarch: Refine numa memory map
Hi, 在 2024/3/18 下午4:01, Bibo Mao 写道: One LoongArch virt machine platform, there is limitation for memory map information. The minimum memory size is 256M and minimum memory size for numa node0 is 256M also. With qemu numa qtest, it is possible that memory size of numa node0 is 128M. Limitations for minimum memory size for both total memory and numa node0 is removed here, including acpi srat table, fadt memory map table and fw_cfg memory map table. Also remove numa node about memory region, there is only low memory region and how memory region. For this series, Reviewed-by: Song Gao After PR[1] merge in, patch3 and patch4 need Rebase. Also, how about enabling LoongArch architecture numa-test? like this: --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -127,6 +127,8 @@ else dbus_vmstate1 = [] endif +qtests_loongarch64 = ['numa-test'] + qtests_filter + qtests_x86_64 = qtests_i386 qtests_alpha = ['boot-serial-test'] + \ [1] https://patchew.org/QEMU/20240429023043.2607982-1-gaos...@loongson.cn/ Thanks. Song Gao Bibo Mao (5): hw/loongarch: Refine acpi srat table for numa memory hw/loongarch: Refine fadt memory table for numa memory hw/loongarch: Refine fwcfg memory map hw/loongarch: Refine system dram memory region hw/loongarch: Remove minimum and default memory size hw/loongarch/acpi-build.c | 58 +++-- hw/loongarch/virt.c | 168 ++ 2 files changed, 152 insertions(+), 74 deletions(-) base-commit: ba49d760eb04630e7b15f423ebecf6c871b8f77b
Re: [PATCH] hw/loongarch: Refine default numa id calculation
在 2024/3/19 上午10:26, Bibo Mao 写道:
With numa_test test case, there is subcase named test_def_cpu_split(),
there are 8 sockets and 2 numa nodes. Here is command line:
"-machine smp.cpus=8,smp.sockets=8 -numa node,memdev=ram -numa node"
The required result is:
node 0 cpus: 0 2 4 6
node 1 cpus: 1 3 5 7
Test case numa_test fails on LoongArch, since the actual result is:
node 0 cpus: 0 1 2 3
node 1 cpus: 4 5 6 7
It will be better if all the cpus in one socket share the same numa
node. Here socket id is used to calculate numa id in function
virt_get_default_cpu_node_id().
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index deb3750d81..29885f6777 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -1219,15 +1219,14 @@ virt_cpu_index_to_props(MachineState *ms, unsigned
cpu_index)
static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
{
-int64_t nidx = 0;
+int64_t socket_id;
if (ms->numa_state->num_nodes) {
-nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes);
-if (ms->numa_state->num_nodes <= nidx) {
-nidx = ms->numa_state->num_nodes - 1;
-}
+socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
+return socket_id % ms->numa_state->num_nodes;
+} else {
+return 0;
}
-return nidx;
}
static void loongarch_class_init(ObjectClass *oc, void *data)
Re: [PATCH] target/loongarch: Put cpucfg operation before CSR register
在 2024/4/28 上午11:16, Bibo Mao 写道:
On Loongarch, cpucfg is register for cpu feature, some other registers
depend on cpucfg feature such as perf CSR registers. Here put cpucfg
read/write operations before CSR register, so that KVM knows how many
perf CSR registers are valid from pre-set cpucfg feature information.
Signed-off-by: Bibo Mao
---
target/loongarch/kvm/kvm.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index 8224d94333..bc75552d0f 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -587,22 +587,22 @@ int kvm_arch_get_registers(CPUState *cs)
return ret;
}
-ret = kvm_loongarch_get_csr(cs);
+ret = kvm_loongarch_get_cpucfg(cs);
if (ret) {
return ret;
}
-ret = kvm_loongarch_get_regs_fp(cs);
+ret = kvm_loongarch_get_csr(cs);
if (ret) {
return ret;
}
-ret = kvm_loongarch_get_mpstate(cs);
+ret = kvm_loongarch_get_regs_fp(cs);
if (ret) {
return ret;
}
-ret = kvm_loongarch_get_cpucfg(cs);
+ret = kvm_loongarch_get_mpstate(cs);
return ret;
}
@@ -615,22 +615,22 @@ int kvm_arch_put_registers(CPUState *cs, int level)
return ret;
}
-ret = kvm_loongarch_put_csr(cs, level);
+ret = kvm_loongarch_put_cpucfg(cs);
if (ret) {
return ret;
}
-ret = kvm_loongarch_put_regs_fp(cs);
+ret = kvm_loongarch_put_csr(cs, level);
if (ret) {
return ret;
}
-ret = kvm_loongarch_put_mpstate(cs);
+ret = kvm_loongarch_put_regs_fp(cs);
if (ret) {
return ret;
}
-ret = kvm_loongarch_put_cpucfg(cs);
+ret = kvm_loongarch_put_mpstate(cs);
return ret;
}
base-commit: a118c4aff4087eafb68f7132b233ad548cf16376
Re: [PULL 02/17] hw/loongarch: Add load initrd
在 2024/4/29 上午2:59, Richard Henderson 写道:
On 4/28/24 01:51, Song Gao wrote:
we load initrd ramdisk after kernel_high address
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-3-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 29 -
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 9feed17db3..a9522d6912 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@ -22,7 +22,8 @@ static uint64_t cpu_loongarch_virt_to_phys(void
*opaque, uint64_t addr)
static int64_t load_kernel_info(struct loongarch_boot_info *info)
{
- uint64_t kernel_entry, kernel_low, kernel_high;
+ uint64_t kernel_entry, kernel_low, kernel_high, initrd_size;
+ ram_addr_t initrd_offset;
ssize_t kernel_size;
kernel_size = load_elf(info->kernel_filename, NULL,
@@ -37,6 +38,32 @@ static int64_t load_kernel_info(struct
loongarch_boot_info *info)
load_elf_strerror(kernel_size));
exit(1);
}
+
+ if (info->initrd_filename) {
+ initrd_size = get_image_size(info->initrd_filename);
+ if (initrd_size > 0) {
+ initrd_offset = ROUND_UP(kernel_high + 4 * kernel_size,
64 * KiB);
+
+ if (initrd_offset + initrd_size > info->ram_size) {
+ error_report("memory too small for initial ram disk
'%s'",
+ info->initrd_filename);
+ exit(1);
+ }
+
+ initrd_size = load_image_targphys(info->initrd_filename,
initrd_offset,
+ info->ram_size -
initrd_offset);
+ }
+
+ if (initrd_size == (target_ulong)-1) {
+ error_report("could not load initial ram disk '%s'",
+ info->initrd_filename);
+ exit(1);
+ }
+ } else {
+ error_report("Need initrd!");
+ exit(1);
+ }
+
return kernel_entry;
}
This doesn't simply allow initrd, it requires an initrd.
This causes make check-tcg to fail:
TEST interrupt on loongarch64
qemu-system-loongarch64: Need initrd!
https://gitlab.com/qemu-project/qemu/-/jobs/6733983794
I'm sorry I missed this test. I will send v2 fix this problem and the
job [1] failed
[1] https://gitlab.com/qemu-project/qemu/-/jobs/6733983763
Thanks.
Song gao
Re: [PATCH v7 06/17] hw/loongarch: Init efi_boot_memmap table
在 2024/4/28 上午9:34, maobibo 写道:
On 2024/4/26 下午5:15, Song Gao wrote:
Message test is also missing there :(
Signed-off-by: Song Gao
Message-Id: <20240307164835.300412-7-gaos...@loongson.cn>
---
include/hw/loongarch/boot.h | 27 +
include/hw/loongarch/virt.h | 10 ++
hw/loongarch/boot.c | 40 +
hw/loongarch/virt.c | 11 ++
4 files changed, 79 insertions(+), 9 deletions(-)
diff --git a/include/hw/loongarch/boot.h b/include/hw/loongarch/boot.h
index cf0e4d4f91..76622af2e2 100644
--- a/include/hw/loongarch/boot.h
+++ b/include/hw/loongarch/boot.h
@@ -21,6 +21,15 @@ typedef struct {
uint8_t b[16];
} efi_guid_t QEMU_ALIGNED(8);
+#define EFI_GUID(a, b, c, d...) (efi_guid_t){
{ \
+ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >>
24) & 0xff, \
+ (b) & 0xff, ((b) >> 8) &
0xff, \
+ (c) & 0xff, ((c) >> 8) & 0xff, d } }
+
+#define LINUX_EFI_BOOT_MEMMAP_GUID \
+ EFI_GUID(0x800f683f, 0xd08b, 0x423a, 0xa2, 0x93, \
+ 0x96, 0x5c, 0x3c, 0x6f, 0xe2, 0xb4)
+
struct efi_config_table {
efi_guid_t guid;
uint64_t *ptr;
@@ -56,6 +65,24 @@ struct efi_system_table {
struct efi_configuration_table *tables;
};
+typedef struct {
+ uint32_t type;
+ uint32_t pad;
+ uint64_t phys_addr;
+ uint64_t virt_addr;
+ uint64_t num_pages;
+ uint64_t attribute;
+} efi_memory_desc_t;
+
+struct efi_boot_memmap {
+ uint64_t map_size;
+ uint64_t desc_size;
+ uint32_t desc_ver;
+ uint64_t map_key;
+ uint64_t buff_size;
+ efi_memory_desc_t map[32];
+};
+
struct loongarch_boot_info {
uint64_t ram_size;
const char *kernel_filename;
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index d7a074d69f..8a9fe4053d 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -35,6 +35,16 @@
#define COMMAND_LINE_SIZE 512
+extern struct memmap_entry *memmap_table;
+extern unsigned memmap_entries;
+
+struct memmap_entry {
+ uint64_t address;
+ uint64_t length;
+ uint32_t type;
+ uint32_t reserved;
+};
+
struct LoongArchMachineState {
/*< private >*/
MachineState parent_obj;
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 46a241a04c..18aae3434d 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@ -63,8 +63,41 @@ static const unsigned int slave_boot_code[] = {
0x4c20, /* jirl $zero, $ra,0 */
};
+static inline void *guidcpy(void *dst, const void *src)
+{
+ return memcpy(dst, src, sizeof(efi_guid_t));
+}
+
+static void init_efi_boot_memmap(struct efi_system_table *systab,
+ void *p, void *start)
+{
+ unsigned i;
+ struct efi_boot_memmap *boot_memmap = p;
+ efi_guid_t tbl_guid = LINUX_EFI_BOOT_MEMMAP_GUID;
+
+ /* efi_configuration_table 1 */
+ guidcpy(>tables[0].guid, _guid);
+ systab->tables[0].table = (struct efi_configuration_table *)(p -
start);
+ systab->nr_tables = 1;
+
+ boot_memmap->desc_size = sizeof(efi_memory_desc_t);
+ boot_memmap->desc_ver = 1;
+ boot_memmap->map_size = 0;
+
+ efi_memory_desc_t *map = p + sizeof(struct efi_boot_memmap);
+ for (i = 0; i < memmap_entries; i++) {
+ map = (void *)boot_memmap + sizeof(*map);
+ map[i].type = memmap_table[i].type;
+ map[i].phys_addr = ROUND_UP(memmap_table[i].address, 64 * KiB);
+ map[i].num_pages = ROUND_DOWN(memmap_table[i].address +
+ memmap_table[i].length - map[i].phys_addr,
64 * KiB);
+ p += sizeof(efi_memory_desc_t);
+ }
+}
Do you verify that memory size of VM is the same with qemu command
line setting? I am ok if the test result is the same.
Yes. e.g 4G
[ 4.061717] Run /sbin/init as init process
/ # free -h
total used free shared buff/cache
available
Mem: 3.9G 61.3M 3.8G 0 11.4M 3.5G
Swap: 0 0 0
Reviewed-by: Bibo Mao
+
static void init_systab(struct loongarch_boot_info *info, void *p,
void *start)
{
+ void *bp_tables_start;
struct efi_system_table *systab = p;
info->a2 = (uint64_t)p - (uint64_t)start;
@@ -80,6 +113,13 @@ static void init_systab(struct
loongarch_boot_info *info, void *p, void *start)
p += ROUND_UP(sizeof(struct efi_system_table), 64 * KiB);
systab->tables = p;
+ bp_tables_start = p;
+
+ init_efi_boot_memmap(systab, p, start);
+ p += ROUND_UP(sizeof(struct efi_boot_memmap) +
+ sizeof(efi_memory_desc_t) * memmap_entries, 64 *
KiB);
+
+ systab->tables = (struct efi_configuration_table
*)(bp_tables_start - start);
}
static void init_cmdline(struct loongarch_boot_info *info, void
*p, void *start)
diff --git a/hw/loongarch/virt.c
Re: [PATCH v7 03/17] hw/loongarch: Add slave cpu boot_code
在 2024/4/28 上午9:15, maobibo 写道:
On 2024/4/26 下午5:15, Song Gao wrote:
Message text is missing here :(
Signed-off-by: Song Gao
Message-Id: <20240307164835.300412-4-gaos...@loongson.cn>
It is strange that there is "Message-Id:" string. Is it required here?
Message_ID helps to find the original email and see more comments.
Here we can not add it, but it is required in QEMU PR.
Thanks.
Song Gao
The others look good to me, especially when bootrom for AP is put at
BIOS flash area.
Regards
Bibo Mao
---
hw/loongarch/boot.c | 62 -
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index a9522d6912..d1a8434127 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@ -15,6 +15,54 @@
#include "sysemu/reset.h"
#include "sysemu/qtest.h"
+static const unsigned int slave_boot_code[] = {
+ /* Configure reset ebase. */
+ 0x0400302c, /* csrwr $t0, LOONGARCH_CSR_EENTRY */
+
+ /* Disable interrupt. */
+ 0x0380100c, /* ori $t0, $zero,0x4 */
+ 0x04000180, /* csrxchg $zero, $t0, LOONGARCH_CSR_CRMD */
+
+ /* Clear mailbox. */
+ 0x142d, /* lu12i.w $t1, 1(0x1) */
+ 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
+ 0x06481da0, /* iocsrwr.d $zero, $t1 */
+
+ /* Enable IPI interrupt. */
+ 0x142c, /* lu12i.w $t0, 1(0x1) */
+ 0x0400118c, /* csrxchg $t0, $t0, LOONGARCH_CSR_ECFG */
+ 0x02fffc0c, /* addi.d $t0, $r0,-1(0xfff) */
+ 0x142d, /* lu12i.w $t1, 1(0x1) */
+ 0x038011ad, /* ori $t1, $t1, CORE_EN_OFF */
+ 0x064819ac, /* iocsrwr.w $t0, $t1 */
+ 0x142d, /* lu12i.w $t1, 1(0x1) */
+ 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
+
+ /* Wait for wakeup <.L11>: */
+ 0x06488000, /* idle 0x0 */
+ 0x0340, /* andi $zero, $zero, 0x0 */
+ 0x064809ac, /* iocsrrd.w $t0, $t1 */
+ 0x43fff59f, /* beqz $t0, -12(0x74) # 48 <.L11> */
+
+ /* Read and clear IPI interrupt. */
+ 0x142d, /* lu12i.w $t1, 1(0x1) */
+ 0x064809ac, /* iocsrrd.w $t0, $t1 */
+ 0x142d, /* lu12i.w $t1, 1(0x1) */
+ 0x038031ad, /* ori $t1, $t1, CORE_CLEAR_OFF */
+ 0x064819ac, /* iocsrwr.w $t0, $t1 */
+
+ /* Disable IPI interrupt. */
+ 0x142c, /* lu12i.w $t0, 1(0x1) */
+ 0x04001180, /* csrxchg $zero, $t0, LOONGARCH_CSR_ECFG */
+
+ /* Read mail buf and jump to specified entry */
+ 0x142d, /* lu12i.w $t1, 1(0x1) */
+ 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
+ 0x06480dac, /* iocsrrd.d $t0, $t1 */
+ 0x00150181, /* move $ra, $t0 */
+ 0x4c20, /* jirl $zero, $ra,0 */
+};
+
static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t
addr)
{
return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
@@ -126,11 +174,23 @@ static void loongarch_direct_kernel_boot(struct
loongarch_boot_info *info)
}
}
+ /* Load slave boot code at pflash0 . */
+ void *boot_code = g_malloc0(VIRT_FLASH0_SIZE);
+ memcpy(boot_code, _boot_code, sizeof(slave_boot_code));
+ rom_add_blob_fixed("boot_code", boot_code, VIRT_FLASH0_SIZE,
VIRT_FLASH0_BASE);
+
CPU_FOREACH(cs) {
lacpu = LOONGARCH_CPU(cs);
lacpu->env.load_elf = true;
- lacpu->env.elf_address = kernel_addr;
+ if (cs == first_cpu) {
+ lacpu->env.elf_address = kernel_addr;
+ } else {
+ lacpu->env.elf_address = VIRT_FLASH0_BASE;
+ }
+ lacpu->env.boot_info = info;
}
+
+ g_free(boot_code);
}
void loongarch_load_kernel(MachineState *ms, struct
loongarch_boot_info *info)
Re: [PULL 1/1] target/loongarch: Fix qemu-system-loongarch64 assert failed with the option '-d int'
Cc: qemu-sta...@nongnu.org 在 2024/3/22 下午10:58, Michael Tokarev 写道: 22.03.2024 13:03, Song Gao : qemu-system-loongarch64 assert failed with the option '-d int', the helper_idle() raise an exception EXCP_HLT, but the exception name is undefined. Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240321123606.1704900-1-gaos...@loongson.cn> Is this another qemu-stable material? You Cc'd it to me but I'm not sure what should I do with it. For patches suitable for -stable, please Cc: qemu-sta...@nongnu.org. Thanks, /mjt
Re: [PULL 3/3] target/loongarch: Fix qemu-loongarch64 hang when executing 'll.d $t0, $t0, 0'
在 2024/3/22 上午1:13, Michael Tokarev 写道: 20.03.2024 05:40, Song Gao : On gen_ll, if a->imm is zero, make_address_x return src1, but the load to destination may clobber src1. We use a new destination to fix this problem. Fixes: c5af6628f4be (target/loongarch: Extract make_address_i() helper) Reviewed-by: Richard Henderson Suggested-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20240320013955.1561311-1-gaos...@loongson.cn> Is it a stable-8.2 material? Yes. Thanks. Song Gao Thanks, /mjt
Re: [PATCH v1] target/loongarch: Fix qemu-system-loongarch64 assert failed with the option '-d int'
在 2024/3/21 上午10:50, Richard Henderson 写道:
On 3/20/24 16:11, Song Gao wrote:
qemu-system-loongarch64 assert failed with the option '-d int',
the helper_idle() raise an exception EXCP_HLT, but the exception name
is undefined.
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 75 ++
1 file changed, 46 insertions(+), 29 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index f6ffb3aadb..17a923de02 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -45,33 +45,46 @@ const char * const fregnames[32] = {
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
};
-static const char * const excp_names[] = {
- [EXCCODE_INT] = "Interrupt",
- [EXCCODE_PIL] = "Page invalid exception for load",
- [EXCCODE_PIS] = "Page invalid exception for store",
- [EXCCODE_PIF] = "Page invalid exception for fetch",
- [EXCCODE_PME] = "Page modified exception",
- [EXCCODE_PNR] = "Page Not Readable exception",
- [EXCCODE_PNX] = "Page Not Executable exception",
- [EXCCODE_PPI] = "Page Privilege error",
- [EXCCODE_ADEF] = "Address error for instruction fetch",
- [EXCCODE_ADEM] = "Address error for Memory access",
- [EXCCODE_SYS] = "Syscall",
- [EXCCODE_BRK] = "Break",
- [EXCCODE_INE] = "Instruction Non-Existent",
- [EXCCODE_IPE] = "Instruction privilege error",
- [EXCCODE_FPD] = "Floating Point Disabled",
- [EXCCODE_FPE] = "Floating Point Exception",
- [EXCCODE_DBP] = "Debug breakpoint",
- [EXCCODE_BCE] = "Bound Check Exception",
- [EXCCODE_SXD] = "128 bit vector instructions Disable exception",
- [EXCCODE_ASXD] = "256 bit vector instructions Disable exception",
+struct TypeExcp {
+ int32_t exccode;
+ const char *name;
+};
+
+static const struct TypeExcp excp_names[] = {
+ {EXCCODE_INT, "Interrupt"},
+ {EXCCODE_PIL, "Page invalid exception for load"},
+ {EXCCODE_PIS, "Page invalid exception for store"},
+ {EXCCODE_PIF, "Page invalid exception for fetch"},
+ {EXCCODE_PME, "Page modified exception"},
+ {EXCCODE_PNR, "Page Not Readable exception"},
+ {EXCCODE_PNX, "Page Not Executable exception"},
+ {EXCCODE_PPI, "Page Privilege error"},
+ {EXCCODE_ADEF, "Address error for instruction fetch"},
+ {EXCCODE_ADEM, "Address error for Memory access"},
+ {EXCCODE_SYS, "Syscall"},
+ {EXCCODE_BRK, "Break"},
+ {EXCCODE_INE, "Instruction Non-Existent"},
+ {EXCCODE_IPE, "Instruction privilege error"},
+ {EXCCODE_FPD, "Floating Point Disabled"},
+ {EXCCODE_FPE, "Floating Point Exception"},
+ {EXCCODE_DBP, "Debug breakpoint"},
+ {EXCCODE_BCE, "Bound Check Exception"},
+ {EXCCODE_SXD, "128 bit vector instructions Disable exception"},
+ {EXCCODE_ASXD, "256 bit vector instructions Disable exception"},
};
const char *loongarch_exception_name(int32_t exception)
{
- assert(excp_names[exception]);
- return excp_names[exception];
+ int i;
+ const char *name = "unknown";
+
+ for (i = 0; i < ARRAY_SIZE(excp_names); i++) {
+ if (excp_names[i].exccode == exception) {
+ name = excp_names[i].name;
+ break;
+ }
+ }
+ return name;
}
I think you should return null for unknown, and then...
void G_NORETURN do_raise_exception(CPULoongArchState *env,
@@ -79,11 +92,17 @@ void G_NORETURN
do_raise_exception(CPULoongArchState *env,
uintptr_t pc)
{
CPUState *cs = env_cpu(env);
+ const char *name;
+ if (exception == EXCP_HLT) {
+ name = "EXCP_HLT";
+ } else {
+ name = loongarch_exception_name(exception);
+ }
qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n",
__func__,
exception,
- loongarch_exception_name(exception));
+ name);
... use two different printfs, one of which prints the exception number.
Why would you special case HLT here instead of putting it in the table?
Hmm, put HLT in the table no problem. I will correct it.
I considered HLT not a real exception to the LoongAarh architecture, so
I didn't put it in the table.
Thanks.
Song Gao
r~
Re: [PATCH] hw/intc/loongarch_extioi: Fix interrupt routing update
在 2024/3/13 下午5:39, Bibo Mao 写道:
Interrupt number in loop sentence should be base irq plus
loop index, it is missing on checking whether the irq
is pending.
Fixes: 428a6ef4396 ("Add vmstate post_load support")
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index bdfa3b481e..0b358548eb 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -151,7 +151,7 @@ static inline void extioi_update_sw_coremap(LoongArchExtIOI
*s, int irq,
continue;
}
-if (notify && test_bit(irq, (unsigned long *)s->isr)) {
+if (notify && test_bit(irq + i, (unsigned long *)s->isr)) {
/*
* lower irq at old cpu and raise irq at new cpu
*/
Re: [PATCH v6 03/17] hw/loongarch: Add slave cpu boot_code
在 2024/3/14 10:28, chen huacai 写道:
Song,
On Fri, Mar 8, 2024 at 12:51 AM Song Gao wrote:
Signed-off-by: Song Gao
Message-Id: <20240301093839.663947-4-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 70 -
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 149deb2e01..e560ac178a 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@ -15,6 +15,54 @@
#include "sysemu/reset.h"
#include "sysemu/qtest.h"
+static const unsigned int slave_boot_code[] = {
+ /* Configure reset ebase. */
+0x0400302c, /* csrwr $r12,0xc*/
Use reg-names may be a little better than reg-nums.
Got it.
Thanks.
Song Gao
Huacai
+
+ /* Disable interrupt. */
+0x0380100c, /* ori$r12,$r0,0x4*/
+0x04000180, /* csrxchg$r0,$r12,0x0*/
+
+ /* Clear mailbox. */
+0x142d, /* lu12i.w$r13,1(0x1) */
+0x038081ad, /* ori$r13,$r13,0x20 */
+0x06481da0, /* iocsrwr.d $r0,$r13*/
+
+ /* Enable IPI interrupt. */
+0x142c, /* lu12i.w$r12,1(0x1) */
+0x0400118c, /* csrxchg$r12,$r12,0x4 */
+0x02fffc0c, /* addi.d $r12,$r0,-1(0xfff) */
+0x142d, /* lu12i.w$r13,1(0x1) */
+0x038011ad, /* ori$r13,$r13,0x4 */
+0x064819ac, /* iocsrwr.w $r12,$r13 */
+0x142d, /* lu12i.w$r13,1(0x1) */
+0x038081ad, /* ori$r13,$r13,0x20 */
+
+ /* Wait for wakeup <.L11>: */
+0x06488000, /* idle 0x0 */
+0x0340, /* andi $r0,$r0,0x0 */
+0x064809ac, /* iocsrrd.w $r12,$r13 */
+0x43fff59f, /* beqz $r12,-12(0x74) # 48 <.L11> */
+
+ /* Read and clear IPI interrupt. */
+0x142d, /* lu12i.w$r13,1(0x1) */
+0x064809ac, /* iocsrrd.w $r12,$r13 */
+0x142d, /* lu12i.w$r13,1(0x1) */
+0x038031ad, /* ori$r13,$r13,0xc */
+0x064819ac, /* iocsrwr.w $r12,$r13 */
+
+ /* Disable IPI interrupt.*/
+0x142c, /* lu12i.w$r12,1(0x1) */
+0x04001180, /* csrxchg$r0,$r12,0x4*/
+
+ /* Read mail buf and jump to specified entry */
+0x142d, /* lu12i.w$r13,1(0x1) */
+0x038081ad, /* ori$r13,$r13,0x20 */
+0x06480dac, /* iocsrrd.d $r12,$r13 */
+0x00150181, /* move $r1,$r12*/
+0x4c20, /* jirl $r0,$r1,0 */
+};
+
static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
{
return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
@@ -111,8 +159,15 @@ static void loongarch_firmware_boot(LoongArchMachineState
*lams,
fw_cfg_add_kernel_info(info, lams->fw_cfg);
}
+static void init_boot_rom(struct loongarch_boot_info *info, void *p)
+{
+memcpy(p, _boot_code, sizeof(slave_boot_code));
+p += sizeof(slave_boot_code);
+}
+
static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info)
{
+void *p, *bp;
int64_t kernel_addr = 0;
LoongArchCPU *lacpu;
CPUState *cs;
@@ -126,11 +181,24 @@ static void loongarch_direct_kernel_boot(struct
loongarch_boot_info *info)
}
}
+/* Load 'boot_rom' at [0 - 1MiB] */
+p = g_malloc0(1 * MiB);
+bp = p;
+init_boot_rom(info, p);
+rom_add_blob_fixed("boot_rom", bp, 1 * MiB, 0);
+
CPU_FOREACH(cs) {
lacpu = LOONGARCH_CPU(cs);
lacpu->env.load_elf = true;
-lacpu->env.elf_address = kernel_addr;
+if (cs == first_cpu) {
+lacpu->env.elf_address = kernel_addr;
+} else {
+lacpu->env.elf_address = 0;
+}
+lacpu->env.boot_info = info;
}
+
+g_free(bp);
}
void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *info)
--
2.34.1
Re: [PATCH v6 03/17] hw/loongarch: Add slave cpu boot_code
在 2024/3/14 9:31, maobibo 写道:
On 2024/3/11 下午2:50, maobibo wrote:
On 2024/3/8 下午5:36, gaosong wrote:
在 2024/3/8 16:27, maobibo 写道:
On 2024/3/8 上午12:48, Song Gao wrote:
Signed-off-by: Song Gao
Message-Id: <20240301093839.663947-4-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 70
-
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 149deb2e01..e560ac178a 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@ -15,6 +15,54 @@
#include "sysemu/reset.h"
#include "sysemu/qtest.h"
+static const unsigned int slave_boot_code[] = {
+ /* Configure reset ebase. */
+ 0x0400302c, /* csrwr $r12,0xc */
+
+ /* Disable interrupt. */
+ 0x0380100c, /* ori $r12,$r0,0x4 */
+ 0x04000180, /* csrxchg $r0,$r12,0x0 */
+
+ /* Clear mailbox. */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038081ad, /* ori $r13,$r13,0x20 */
+ 0x06481da0, /* iocsrwr.d $r0,$r13 */
+
+ /* Enable IPI interrupt. */
+ 0x142c, /* lu12i.w $r12,1(0x1) */
+ 0x0400118c, /* csrxchg $r12,$r12,0x4 */
+ 0x02fffc0c, /* addi.d $r12,$r0,-1(0xfff) */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038011ad, /* ori $r13,$r13,0x4 */
+ 0x064819ac, /* iocsrwr.w $r12,$r13 */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038081ad, /* ori $r13,$r13,0x20 */
+
+ /* Wait for wakeup <.L11>: */
+ 0x06488000, /* idle 0x0 */
+ 0x0340, /* andi $r0,$r0,0x0 */
+ 0x064809ac, /* iocsrrd.w $r12,$r13 */
+ 0x43fff59f, /* beqz $r12,-12(0x74) # 48 <.L11> */
+
+ /* Read and clear IPI interrupt. */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x064809ac, /* iocsrrd.w $r12,$r13 */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038031ad, /* ori $r13,$r13,0xc */
+ 0x064819ac, /* iocsrwr.w $r12,$r13 */
+
+ /* Disable IPI interrupt. */
+ 0x142c, /* lu12i.w $r12,1(0x1) */
+ 0x04001180, /* csrxchg $r0,$r12,0x4 */
+
+ /* Read mail buf and jump to specified entry */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038081ad, /* ori $r13,$r13,0x20 */
+ 0x06480dac, /* iocsrrd.d $r12,$r13 */
+ 0x00150181, /* move $r1,$r12 */
+ 0x4c20, /* jirl $r0,$r1,0 */
+};
+
static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t
addr)
{
return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
@@ -111,8 +159,15 @@ static void
loongarch_firmware_boot(LoongArchMachineState *lams,
fw_cfg_add_kernel_info(info, lams->fw_cfg);
}
+static void init_boot_rom(struct loongarch_boot_info *info, void *p)
+{
+ memcpy(p, _boot_code, sizeof(slave_boot_code));
+ p += sizeof(slave_boot_code);
+}
+
static void loongarch_direct_kernel_boot(struct
loongarch_boot_info *info)
{
+ void *p, *bp;
int64_t kernel_addr = 0;
LoongArchCPU *lacpu;
CPUState *cs;
@@ -126,11 +181,24 @@ static void
loongarch_direct_kernel_boot(struct loongarch_boot_info *info)
}
}
+ /* Load 'boot_rom' at [0 - 1MiB] */
+ p = g_malloc0(1 * MiB);
+ bp = p;
+ init_boot_rom(info, p);
+ rom_add_blob_fixed("boot_rom", bp, 1 * MiB, 0);
+
The secondary cpu waiting on the bootrom located memory address
0x0-0x10.
Is it possible that primary cpu clears the memory located at bootrom
and then wakeup the secondary cpu?
I think it impossible，0-1M is ROM。
I am not sure whether it is ok if area between 0-1M is ROM.
For the memory map table, low memory area (0 - 256M) is still ddr ram.
And it is passed to kernel with fdt system table, rather than
area(1-256M). Is that right?
There are some lines like this:
/* Node0 memory */
memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1);
Song,
Can the base memory address of bootrom for secondary cpus be set as base
address of flash like bios, such as VIRT_FLASH0_BASE/VIRT_FLASH1_BASE?
> And ddr memory map area is kept unchanged.
Good suggestions, I wil do this on v7.
Thanks.
Song Gao
Regards
Bibo Mao
Regards
Bibo Mao
Thanks.
Song Gao
Regards
Bibo Mao
CPU_FOREACH(cs) {
lacpu = LOONGARCH_CPU(cs);
lacpu->env.load_elf = true;
- lacpu->env.elf_address = kernel_addr;
+ if (cs == first_cpu) {
+ lacpu->env.elf_address = kernel_addr;
+ } else {
+ l
Re: [PATCH v6 06/17] hw/loongarch: Init efi_boot_memmap table
在 2024/3/8 16:37, maobibo 写道:
On 2024/3/8 上午12:48, Song Gao wrote:
Signed-off-by: Song Gao
Message-Id: <20240301093839.663947-7-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 39 +
hw/loongarch/virt.c | 11 ++-
include/hw/loongarch/boot.h | 27 +
include/hw/loongarch/virt.h | 10 ++
4 files changed, 78 insertions(+), 9 deletions(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 1e31e2a59f..2896c1ea40 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@ -63,8 +63,40 @@ static const unsigned int slave_boot_code[] = {
0x4c20, /* jirl $r0,$r1,0 */
};
+static inline void *guidcpy(void *dst, const void *src)
+{
+ return memcpy(dst, src, sizeof(efi_guid_t));
+}
+
+static void init_efi_boot_memmap(struct efi_system_table *systab,
+ void *p, void *start)
+{
+ unsigned i;
+ struct efi_boot_memmap *boot_memmap = p;
+ efi_guid_t tbl_guid = LINUX_EFI_BOOT_MEMMAP_GUID;
+
+ /* efi_configuration_table 1 */
+ guidcpy(>tables[0].guid, _guid);
+ systab->tables[0].table = (struct efi_configuration_table *)(p -
start);
+ systab->nr_tables = 1;
+
+ boot_memmap->desc_size = sizeof(efi_memory_desc_t);
+ boot_memmap->desc_ver = 1;
+ boot_memmap->map_size = 0;
+
+ efi_memory_desc_t *map = p + sizeof(struct efi_boot_memmap);
+ for (i = 0; i < memmap_entries; i++) {
+ map = (void *)boot_memmap + sizeof(*map);
+ map[i].type = memmap_table[i].type;
+ map[i].phys_addr = memmap_table[i].address;
+ map[i].num_pages = memmap_table[i].length >> 16; /* 64KB align*/
64KB aligned or 64KB page size? In generic page size is 4K by EFI spec
IIRC.
Thank you for pointing it out., I will correct it on v7.
Regards
Bibo Mao
+ p += sizeof(efi_memory_desc_t);
+ }
+}
+
static void init_systab(struct loongarch_boot_info *info, void *p,
void *start)
{
+ void *bp_tables_start;
struct efi_system_table *systab = p;
info->a2 = (uint64_t)p - (uint64_t)start;
@@ -80,6 +112,13 @@ static void init_systab(struct loongarch_boot_info
*info, void *p, void *start)
p += ROUND_UP(sizeof(struct efi_system_table), 64);
systab->tables = p;
+ bp_tables_start = p;
+
+ init_efi_boot_memmap(systab, p, start);
+ p += ROUND_UP(sizeof(struct efi_boot_memmap) +
+ sizeof(efi_memory_desc_t) * memmap_entries, 64);
+
+ systab->tables = (struct efi_configuration_table
*)(bp_tables_start - start);
}
static void init_cmdline(struct loongarch_boot_info *info, void *p,
void *start)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index bbd5cc1d4d..8981b57b12 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -377,15 +377,8 @@ static void virt_powerdown_req(Notifier
*notifier, void *opaque)
acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS);
}
-struct memmap_entry {
- uint64_t address;
- uint64_t length;
- uint32_t type;
- uint32_t reserved;
-};
-
-static struct memmap_entry *memmap_table;
-static unsigned memmap_entries;
+struct memmap_entry *memmap_table;
+unsigned memmap_entries;
static void memmap_add_entry(uint64_t address, uint64_t length,
uint32_t type)
{
diff --git a/include/hw/loongarch/boot.h b/include/hw/loongarch/boot.h
index 65ad406f02..f71c693f43 100644
--- a/include/hw/loongarch/boot.h
+++ b/include/hw/loongarch/boot.h
@@ -21,6 +21,15 @@ typedef struct {
uint8_t b[16];
} efi_guid_t __attribute__((aligned(8)));
+#define EFI_GUID(a, b, c, d...) (efi_guid_t){
{ \
+ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >>
24) & 0xff, \
+ (b) & 0xff, ((b) >> 8) &
0xff, \
+ (c) & 0xff, ((c) >> 8) & 0xff, d } }
+
+#define LINUX_EFI_BOOT_MEMMAP_GUID \
+ EFI_GUID(0x800f683f, 0xd08b, 0x423a, 0xa2, 0x93, \
+ 0x96, 0x5c, 0x3c, 0x6f, 0xe2, 0xb4)
+
struct efi_config_table {
efi_guid_t guid;
uint64_t *ptr;
@@ -56,6 +65,24 @@ struct efi_system_table {
struct efi_configuration_table *tables;
};
+typedef struct {
+ uint32_t type;
+ uint32_t pad;
+ uint64_t phys_addr;
+ uint64_t virt_addr;
+ uint64_t num_pages;
+ uint64_t attribute;
+} efi_memory_desc_t;
+
+struct efi_boot_memmap {
+ uint64_t map_size;
+ uint64_t desc_size;
+ uint32_t desc_ver;
+ uint64_t map_key;
+ uint64_t buff_size;
+ efi_memory_desc_t map[32];
+};
+
struct loongarch_boot_info {
uint64_t ram_size;
const char *kernel_filename;
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index d7a074d69f..8a9fe4053d 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -35,6 +35,16 @@
#define COMMAND_LINE_SIZE 512
+extern struct memmap_entry *memmap_table;
+extern unsigned memmap_entries;
+
Re: [PATCH v6 03/17] hw/loongarch: Add slave cpu boot_code
在 2024/3/8 16:27, maobibo 写道:
On 2024/3/8 上午12:48, Song Gao wrote:
Signed-off-by: Song Gao
Message-Id: <20240301093839.663947-4-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 70 -
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 149deb2e01..e560ac178a 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@ -15,6 +15,54 @@
#include "sysemu/reset.h"
#include "sysemu/qtest.h"
+static const unsigned int slave_boot_code[] = {
+ /* Configure reset ebase. */
+ 0x0400302c, /* csrwr $r12,0xc */
+
+ /* Disable interrupt. */
+ 0x0380100c, /* ori $r12,$r0,0x4 */
+ 0x04000180, /* csrxchg $r0,$r12,0x0 */
+
+ /* Clear mailbox. */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038081ad, /* ori $r13,$r13,0x20 */
+ 0x06481da0, /* iocsrwr.d $r0,$r13 */
+
+ /* Enable IPI interrupt. */
+ 0x142c, /* lu12i.w $r12,1(0x1) */
+ 0x0400118c, /* csrxchg $r12,$r12,0x4 */
+ 0x02fffc0c, /* addi.d $r12,$r0,-1(0xfff) */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038011ad, /* ori $r13,$r13,0x4 */
+ 0x064819ac, /* iocsrwr.w $r12,$r13 */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038081ad, /* ori $r13,$r13,0x20 */
+
+ /* Wait for wakeup <.L11>: */
+ 0x06488000, /* idle 0x0 */
+ 0x0340, /* andi $r0,$r0,0x0 */
+ 0x064809ac, /* iocsrrd.w $r12,$r13 */
+ 0x43fff59f, /* beqz $r12,-12(0x74) # 48 <.L11> */
+
+ /* Read and clear IPI interrupt. */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x064809ac, /* iocsrrd.w $r12,$r13 */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038031ad, /* ori $r13,$r13,0xc */
+ 0x064819ac, /* iocsrwr.w $r12,$r13 */
+
+ /* Disable IPI interrupt. */
+ 0x142c, /* lu12i.w $r12,1(0x1) */
+ 0x04001180, /* csrxchg $r0,$r12,0x4 */
+
+ /* Read mail buf and jump to specified entry */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038081ad, /* ori $r13,$r13,0x20 */
+ 0x06480dac, /* iocsrrd.d $r12,$r13 */
+ 0x00150181, /* move $r1,$r12 */
+ 0x4c20, /* jirl $r0,$r1,0 */
+};
+
static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
{
return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
@@ -111,8 +159,15 @@ static void
loongarch_firmware_boot(LoongArchMachineState *lams,
fw_cfg_add_kernel_info(info, lams->fw_cfg);
}
+static void init_boot_rom(struct loongarch_boot_info *info, void *p)
+{
+ memcpy(p, _boot_code, sizeof(slave_boot_code));
+ p += sizeof(slave_boot_code);
+}
+
static void loongarch_direct_kernel_boot(struct loongarch_boot_info
*info)
{
+ void *p, *bp;
int64_t kernel_addr = 0;
LoongArchCPU *lacpu;
CPUState *cs;
@@ -126,11 +181,24 @@ static void loongarch_direct_kernel_boot(struct
loongarch_boot_info *info)
}
}
+ /* Load 'boot_rom' at [0 - 1MiB] */
+ p = g_malloc0(1 * MiB);
+ bp = p;
+ init_boot_rom(info, p);
+ rom_add_blob_fixed("boot_rom", bp, 1 * MiB, 0);
+
The secondary cpu waiting on the bootrom located memory address
0x0-0x10.
Is it possible that primary cpu clears the memory located at bootrom
and then wakeup the secondary cpu?
I think it impossible，0-1M is ROM。
Thanks.
Song Gao
Regards
Bibo Mao
CPU_FOREACH(cs) {
lacpu = LOONGARCH_CPU(cs);
lacpu->env.load_elf = true;
- lacpu->env.elf_address = kernel_addr;
+ if (cs == first_cpu) {
+ lacpu->env.elf_address = kernel_addr;
+ } else {
+ lacpu->env.elf_address = 0;
+ }
+ lacpu->env.boot_info = info;
}
+
+ g_free(bp);
}
void loongarch_load_kernel(MachineState *ms, struct
loongarch_boot_info *info)
Re: [PATCH v6 07/17] hw/loongarch: Init efi_initrd table
在 2024/3/8 16:36, Philippe Mathieu-Daudé 写道:
Hi Song,
On 7/3/24 17:48, Song Gao wrote:
Signed-off-by: Song Gao
Message-Id: <20240301093839.663947-8-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 23 +--
include/hw/loongarch/boot.h | 9 +
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 2896c1ea40..6126a37858 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@ -15,6 +15,9 @@
#include "sysemu/reset.h"
#include "sysemu/qtest.h"
+ram_addr_t initrd_offset;
+uint64_t initrd_size;
Where is that used?
patch1 load_kernel_info() and patch7 init_efi_initrd_table()
Thanks.
Song Gao
static const unsigned int slave_boot_code[] = {
/* Configure reset ebase. */
0x0400302c, /* csrwr $r12,0xc */
@@ -94,6 +97,21 @@ static void init_efi_boot_memmap(struct
efi_system_table *systab,
}
}
+static void init_efi_initrd_table(struct efi_system_table *systab,
+ void *p, void *start)
+{
+ efi_guid_t tbl_guid = LINUX_EFI_INITRD_MEDIA_GUID;
+ struct efi_initrd *initrd_table = p;
+
+ /* efi_configuration_table 2 */
+ guidcpy(>tables[1].guid, _guid);
+ systab->tables[1].table = (struct efi_configuration_table *)(p -
start);
+ systab->nr_tables = 2;
+
+ initrd_table->base = initrd_offset;
+ initrd_table->size = initrd_size;
+}
+
static void init_systab(struct loongarch_boot_info *info, void *p,
void *start)
{
void *bp_tables_start;
@@ -117,6 +135,8 @@ static void init_systab(struct loongarch_boot_info
*info, void *p, void *start)
init_efi_boot_memmap(systab, p, start);
p += ROUND_UP(sizeof(struct efi_boot_memmap) +
sizeof(efi_memory_desc_t) * memmap_entries, 64);
+ init_efi_initrd_table(systab, p, start);
+ p += ROUND_UP(sizeof(struct efi_initrd), 64);
systab->tables = (struct efi_configuration_table
*)(bp_tables_start - start);
}
@@ -138,8 +158,7 @@ static uint64_t cpu_loongarch_virt_to_phys(void
*opaque, uint64_t addr)
static int64_t load_kernel_info(struct loongarch_boot_info *info)
{
- uint64_t kernel_entry, kernel_low, kernel_high, initrd_size;
- ram_addr_t initrd_offset;
+ uint64_t kernel_entry, kernel_low, kernel_high;
ssize_t kernel_size;
kernel_size = load_elf(info->kernel_filename, NULL,
diff --git a/include/hw/loongarch/boot.h b/include/hw/loongarch/boot.h
index f71c693f43..ddcb279874 100644
--- a/include/hw/loongarch/boot.h
+++ b/include/hw/loongarch/boot.h
@@ -30,6 +30,10 @@ typedef struct {
EFI_GUID(0x800f683f, 0xd08b, 0x423a, 0xa2, 0x93, \
0x96, 0x5c, 0x3c, 0x6f, 0xe2, 0xb4)
+#define LINUX_EFI_INITRD_MEDIA_GUID \
+ EFI_GUID(0x5568e427, 0x68fc, 0x4f3d, 0xac, 0x74, \
+ 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68)
+
struct efi_config_table {
efi_guid_t guid;
uint64_t *ptr;
@@ -83,6 +87,11 @@ struct efi_boot_memmap {
efi_memory_desc_t map[32];
};
+struct efi_initrd {
+ uint64_t base;
+ uint64_t size;
+};
+
struct loongarch_boot_info {
uint64_t ram_size;
const char *kernel_filename;
Re: [PULL v2 00/17] loongarch-to-apply queue
在 2024/3/7 23:37, Peter Maydell 写道: On Thu, 7 Mar 2024 at 15:28, Song Gao wrote: The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87: Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +) are available in the Git repository at: https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240307 for you to fetch changes up to 4dc2edfd6f8abfc38f0ba110502790aa5051b1b5: hw/loongarch: Add cells missing from rtc node (2024-03-07 21:58:00 +0800) pull-loongarch-20240307 Song Gao (17): hw/loongarch: Move boot fucntions to boot.c hw/loongarch: Add load initrd hw/loongarch: Add slave cpu boot_code hw/loongarch: Add init_cmdline hw/loongarch: Init efi_system_table hw/loongarch: Init efi_boot_memmap table hw/loongarch: Init efi_initrd table hw/loongarch: Init efi_fdt table hw/loongarch: Fix fdt memory node wrong 'reg' hw/loongarch: fdt adds cpu interrupt controller node hw/loongarch: fdt adds Extend I/O Interrupt Controller hw/loongarch: fdt adds pch_pic Controller hw/loongarch: fdt adds pch_msi Controller hw/loongarch: fdt adds pcie irq_map node hw/loongarch: fdt remove unused irqchip node hw/loongarch: Add cells missing from uart node hw/loongarch: Add cells missing from rtc node Looks like our emails crossed, but see my remarks on v1 about test/compilation failures. Ah, I'll fix these issues. Also I have just noticed that none of these patches have Reviewed-by: tags. Please make sure patches are code reviewed before submitting them in pull requests. OK. and BiBo, Could you help review the v6 series? Thanks. Song Gao thanks -- PMM
Re: [PULL 00/17] loongarch-to-apply queue
Hi, Missing patch16.,17, please see v2 version Thanks. Song Gao 在 2024/3/7 22:51, Song Gao 写道: The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87: Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +) are available in the Git repository at: https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240307 for you to fetch changes up to 4dc2edfd6f8abfc38f0ba110502790aa5051b1b5: hw/loongarch: Add cells missing from rtc node (2024-03-07 21:58:00 +0800) pull-loongarch-20240307 Song Gao (17): hw/loongarch: Move boot fucntions to boot.c hw/loongarch: Add load initrd hw/loongarch: Add slave cpu boot_code hw/loongarch: Add init_cmdline hw/loongarch: Init efi_system_table hw/loongarch: Init efi_boot_memmap table hw/loongarch: Init efi_initrd table hw/loongarch: Init efi_fdt table hw/loongarch: Fix fdt memory node wrong 'reg' hw/loongarch: fdt adds cpu interrupt controller node hw/loongarch: fdt adds Extend I/O Interrupt Controller hw/loongarch: fdt adds pch_pic Controller hw/loongarch: fdt adds pch_msi Controller hw/loongarch: fdt adds pcie irq_map node hw/loongarch: fdt remove unused irqchip node hw/loongarch: Add cells missing from uart node hw/loongarch: Add cells missing from rtc node hw/loongarch/boot.c| 330 + hw/loongarch/meson.build | 1 + hw/loongarch/virt.c| 363 + include/hw/intc/loongarch_extioi.h | 1 + include/hw/loongarch/boot.h| 109 +++ include/hw/loongarch/virt.h| 14 ++ include/hw/pci-host/ls7a.h | 2 + target/loongarch/cpu.h | 2 + 8 files changed, 662 insertions(+), 160 deletions(-) create mode 100644 hw/loongarch/boot.c create mode 100644 include/hw/loongarch/boot.h
Re: [PATCH v2 3/5] hw/loongarch: Add compat machine for 9.0
在 2024/2/27 10:30, Bibo Mao 写道:
Since migration test case requires compat machine type support,
compat machine is added for qemu 9.0 here.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 60 +++--
1 file changed, 47 insertions(+), 13 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 3bc35c58c9..f37f642ede 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -46,6 +46,32 @@
#include "hw/block/flash.h"
#include "qemu/error-report.h"
+#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
+static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
+void *data) \
+{ \
+MachineClass *mc = MACHINE_CLASS(oc); \
+virt_machine_##major##_##minor##_options(mc); \
+mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
+if (latest) { \
+mc->alias = "virt"; \
+} \
+} \
+static const TypeInfo machvirt_##major##_##minor##_info = { \
+.name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
+.parent = TYPE_VIRT_MACHINE, \
+.class_init = virt_##major##_##minor##_class_init, \
+}; \
+static void machvirt_machine_##major##_##minor##_init(void) \
+{ \
+type_register_static(_##major##_##minor##_info); \
+} \
+type_init(machvirt_machine_##major##_##minor##_init);
+
+#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
+DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
+#define DEFINE_VIRT_MACHINE(major, minor) \
+DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
struct loaderparams {
uint64_t ram_size;
@@ -1200,18 +1226,26 @@ static void virt_class_init(ObjectClass *oc, void *data)
#endif
}
-static const TypeInfo virt_machine_types[] = {
-{
-.name = TYPE_VIRT_MACHINE,
-.parent = TYPE_MACHINE,
-.instance_size = sizeof(VirtMachineState),
-.class_init = virt_class_init,
-.instance_init = virt_machine_initfn,
-.interfaces = (InterfaceInfo[]) {
- { TYPE_HOTPLUG_HANDLER },
- { }
-},
-}
+static const TypeInfo virt_machine_info = {
+.name = TYPE_VIRT_MACHINE,
+.parent = TYPE_MACHINE,
+.abstract = true,
+.instance_size = sizeof(VirtMachineState),
+.class_init = virt_class_init,
+.instance_init = virt_machine_initfn,
+.interfaces = (InterfaceInfo[]) {
+{ TYPE_HOTPLUG_HANDLER },
+{ }
+},
};
-DEFINE_TYPES(virt_machine_types)
+static void machvirt_machine_init(void)
+{
+type_register_static(_machine_info);
+}
+type_init(machvirt_machine_init);
+
+static void virt_machine_9_0_options(MachineClass *mc)
+{
+}
+DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
Re: [PATCH v2 4/5] hw/loongarch: Set minimium memory size as 256M
在 2024/2/27 10:30, Bibo Mao 写道:
The minimum memory size for LoongArch UEFI bios is 256M, also some
test cases such as migration and qos use 256M memory by default.
Here set minimum memory size for Loongarch VirtMachine with 256M rather
than 1G, so that test cases with 256M memory can pass to run.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index f37f642ede..1dadb8e299 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -864,8 +864,8 @@ static void virt_init(MachineState *machine)
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
}
-if (ram_size < 1 * GiB) {
-error_report("ram_size must be greater than 1G.");
+if (ram_size < 256 * MiB) {
+error_report("ram_size must be greater than 256M.");
exit(1);
}
create_fdt(vms);
Re: [PATCH 3/5] hw/loongarch: Add compat machine for 9.0
在 2024/2/20 20:41, Bibo Mao 写道:
Since migration test case requires compat machine type support,
compat machine is added for qemu 9.0 here.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 60 +++--
1 file changed, 47 insertions(+), 13 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index d0827aafab..a7d700497d 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -46,6 +46,32 @@
#include "hw/block/flash.h"
#include "qemu/error-report.h"
+#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
+static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
+void *data) \
+{ \
+MachineClass *mc = MACHINE_CLASS(oc); \
+virt_machine_##major##_##minor##_options(mc); \
+mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
+if (latest) { \
+mc->alias = "virt"; \
+} \
+} \
+static const TypeInfo machvirt_##major##_##minor##_info = { \
+.name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
+.parent = TYPE_VIRT_MACHINE, \
+.class_init = virt_##major##_##minor##_class_init, \
+}; \
+static void machvirt_machine_##major##_##minor##_init(void) \
+{ \
+type_register_static(_##major##_##minor##_info); \
+} \
+type_init(machvirt_machine_##major##_##minor##_init);
+
+#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
+DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
+#define DEFINE_VIRT_MACHINE(major, minor) \
+DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
struct loaderparams {
uint64_t ram_size;
@@ -1151,18 +1177,26 @@ static void virt_class_init(ObjectClass *oc, void *data)
#endif
}
-static const TypeInfo virt_machine_types[] = {
-{
-.name = TYPE_VIRT_MACHINE,
-.parent = TYPE_MACHINE,
-.instance_size = sizeof(VirtMachineState),
-.class_init = virt_class_init,
-.instance_init = virt_machine_initfn,
-.interfaces = (InterfaceInfo[]) {
- { TYPE_HOTPLUG_HANDLER },
- { }
-},
-}
+static const TypeInfo virt_machine_info = {
+.name = TYPE_VIRT_MACHINE,
+.parent = TYPE_MACHINE,
+.abstract = true,
+.instance_size = sizeof(VirtMachineState),
+.class_init = virt_class_init,
+.instance_init = virt_machine_initfn,
+.interfaces = (InterfaceInfo[]) {
+{ TYPE_HOTPLUG_HANDLER },
+{ }
+},
};
-DEFINE_TYPES(virt_machine_types)
+static void machvirt_machine_init(void)
+{
+type_register_static(_machine_info);
+}
+type_init(machvirt_machine_init);
+
+static void virt_machine_9_0_options(MachineClass *mc)
+{
+}
+DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
Re: [PATCH v2] target/loongarch: Add TCG macro in structure CPUArchState
在 2024/3/4 10:18, Bibo Mao 写道:
In structure CPUArchState some struct elements are only used in TCG
mode, and it is not used in KVM mode. Macro CONFIG_TCG is added to
make it simpiler in KVM mode, also there is the same modification
in c code when these struct elements are used.
When VM runs in KVM mode, TLB entries are not used and do not need
migrate. It is only useful when it runs in TCG mode.
Signed-off-by: Bibo Mao
Change-Id: Id30d663f5d7bc3436520638f606f99d93926eb2e
---
v1 --> v2:
- Add field needed in structure vmstate_tlb, dynamically judge whether
tlb should be migrated, since mostly qemu-system-loongarch64 is compiled
with both kvm and tcg accl enabled.
---
target/loongarch/cpu.c| 14 +++---
target/loongarch/cpu.h| 16 ++--
target/loongarch/cpu_helper.c | 9 +
target/loongarch/machine.c| 34 +-
4 files changed, 59 insertions(+), 14 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index bc2684179f..35db8e244d 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -517,7 +517,9 @@ static void loongarch_cpu_reset_hold(Object *obj)
lacc->parent_phases.hold(obj);
}
+#ifdef CONFIG_TCG
env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
+#endif
env->fcsr0 = 0x0;
int n;
@@ -562,7 +564,9 @@ static void loongarch_cpu_reset_hold(Object *obj)
#ifndef CONFIG_USER_ONLY
env->pc = 0x1c00;
+#ifdef CONFIG_TCG
memset(env->tlb, 0, sizeof(env->tlb));
+#endif
if (kvm_enabled()) {
kvm_arch_reset_vcpu(env);
}
@@ -696,11 +700,15 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int
flags)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = >env;
-int i;
+int i, fp_status;
+#ifdef CONFIG_TCG
+fp_status = get_float_exception_flags(>fp_status);
+#else
+fp_status = 0;
+#endif
qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
-qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0,
- get_float_exception_flags(>fp_status));
+qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0,
fp_status);
/* gpr */
for (i = 0; i < 32; i++) {
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index ec37579fd6..c25ad112b1 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -272,6 +272,7 @@ union fpr_t {
VReg vreg;
};
+#ifdef CONFIG_TCG
struct LoongArchTLB {
uint64_t tlb_misc;
/* Fields corresponding to CSR_TLBELO0/1 */
@@ -279,23 +280,18 @@ struct LoongArchTLB {
uint64_t tlb_entry1;
};
typedef struct LoongArchTLB LoongArchTLB;
+#endif
typedef struct CPUArchState {
uint64_t gpr[32];
uint64_t pc;
fpr_t fpr[32];
-float_status fp_status;
bool cf[8];
-
uint32_t fcsr0;
-uint32_t fcsr0_mask;
uint32_t cpucfg[21];
-uint64_t lladdr; /* LL virtual address compared against SC */
-uint64_t llval;
-
/* LoongArch CSRs */
uint64_t CSR_CRMD;
uint64_t CSR_PRMD;
@@ -352,8 +348,16 @@ typedef struct CPUArchState {
uint64_t CSR_DERA;
uint64_t CSR_DSAVE;
+#ifdef CONFIG_TCG
+float_status fp_status;
+uint32_t fcsr0_mask;
+uint64_t lladdr; /* LL virtual address compared against SC */
+uint64_t llval;
+#endif
#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_TCG
LoongArchTLB tlb[LOONGARCH_TLB_MAX];
+#endif
AddressSpace *address_space_iocsr;
bool load_elf;
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 45f821d086..d1cdbe30ba 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -11,6 +11,7 @@
#include "internals.h"
#include "cpu-csr.h"
+#ifdef CONFIG_TCG
static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
int *prot, target_ulong address,
int access_type, int index, int mmu_idx)
@@ -154,6 +155,14 @@ static int loongarch_map_address(CPULoongArchState *env,
hwaddr *physical,
return TLBRET_NOMATCH;
}
+#else
+static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ MMUAccessType access_type, int mmu_idx)
+{
+return TLBRET_NOMATCH;
+}
+#endif
static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
target_ulong dmw)
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
index c7029fb9b4..77890f07cc 100644
--- a/target/loongarch/machine.c
+++ b/target/loongarch/machine.c
@@ -8,6 +8,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "migration/cpu.h"
+#include "sysemu/kvm.h"
#include "vec.h"
static const VMStateDescription vmstate_fpu_reg = {
Re: [PATCH] Fixed tlb huge page loading issue
Hi,
Title 'target/loongarch: ' ...
Thanks.
Song Gao
在 2024/2/28 14:55, Xianglai Li 写道:
The lddir and ldpte instruction emulation has
a problem with the use of large page processing above level 2.
The page size is not correctly calculated,
resulting in the wrong page size of the table entry found by tlb.
Signed-off-by: Xianglai Li
---
target/loongarch/cpu.h| 1 +
target/loongarch/tcg/tlb_helper.c | 21 -
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index ec37579fd6..eab3e41c71 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -292,6 +292,7 @@ typedef struct CPUArchState {
uint32_t fcsr0_mask;
uint32_t cpucfg[21];
+uint32_t lddir_ps;
uint64_t lladdr; /* LL virtual address compared against SC */
uint64_t llval;
diff --git a/target/loongarch/tcg/tlb_helper.c
b/target/loongarch/tcg/tlb_helper.c
index a08c08b05a..3594c800b3 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -38,6 +38,7 @@ static void raise_mmu_exception(CPULoongArchState *env,
target_ulong address,
cs->exception_index = EXCCODE_PIF;
}
env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR,
1);
+env->lddir_ps = 0;
break;
case TLBRET_INVALID:
/* TLB match with no valid bit */
@@ -488,13 +489,6 @@ target_ulong helper_lddir(CPULoongArchState *env,
target_ulong base,
uint64_t dir_base, dir_width;
bool huge = (base >> LOONGARCH_PAGE_HUGE_SHIFT) & 0x1;
-badvaddr = env->CSR_TLBRBADV;
-base = base & TARGET_PHYS_MASK;
-
-/* 0:64bit, 1:128bit, 2:192bit, 3:256bit */
-shift = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTEWIDTH);
-shift = (shift + 1) * 3;
-
if (huge) {
return base;
}
@@ -519,9 +513,18 @@ target_ulong helper_lddir(CPULoongArchState *env,
target_ulong base,
do_raise_exception(env, EXCCODE_INE, GETPC());
return 0;
}
+
+/* 0:64bit, 1:128bit, 2:192bit, 3:256bit */
+shift = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTEWIDTH);
+shift = (shift + 1) * 3;
+badvaddr = env->CSR_TLBRBADV;
+base = base & TARGET_PHYS_MASK;
index = (badvaddr >> dir_base) & ((1 << dir_width) - 1);
phys = base | index << shift;
ret = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK;
+if (ret & BIT_ULL(LOONGARCH_PAGE_HUGE_SHIFT)) {
+env->lddir_ps = dir_base;
+}
return ret;
}
@@ -538,13 +541,13 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
base = base & TARGET_PHYS_MASK;
if (huge) {
-/* Huge Page. base is paddr */
tmp0 = base ^ (1 << LOONGARCH_PAGE_HUGE_SHIFT);
/* Move Global bit */
tmp0 = ((tmp0 & (1 << LOONGARCH_HGLOBAL_SHIFT)) >>
LOONGARCH_HGLOBAL_SHIFT) << R_TLBENTRY_G_SHIFT |
(tmp0 & (~(1 << LOONGARCH_HGLOBAL_SHIFT)));
-ps = ptbase + ptwidth - 1;
+
+ps = env->lddir_ps - 1;
if (odd) {
tmp0 += MAKE_64BIT_MASK(ps, 1);
}
Re: [PATCH v5 00/17] Add boot LoongArch elf kernel with FDT
Hi, If there are no new comments, I'll add this series to the loongarch-next branch next week. Thanks. Song Gao 在 2024/3/1 下午5:38, Song Gao 写道: Hi, All We already support boot efi kernel with bios, but not support boot elf kernel. This series adds boot elf kernel with FDT. 'LoongArch supports ACPI and FDT. The information that needs to be passed to the kernel includes the memmap, the initrd, the command line, optionally the ACPI/FDT tables, and so on' see [1]. Patch 2-8 : Create efi system table, and three efi configuration table boot_memmap, initd, FDT. Patch 9-17 : Fixes FDT problems. Test: - Start kernel See [2] start_kernel.sh - Start qcow2 See [2] start_qcow2.sh V5: - Rebase; V4: - patch 3 change slave_boot_code[] to const, and 'static void *p ' to 'void *p'; - patch 4 fixes build error; - patch 10-13, add project and commit link. V3: - Load initrd at kernel_high + 4 * kernel_size; - Load 'boot_rom' at [0 - 1M], the 'boot_rom' includes slave_boot_code, cmdline_buf and systab_tables; - R-b and rebase. V2: - FDT pcie node adds cells 'msi-map'; [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arch/loongarch/booting.rst?h=v6.7-rc4 [2]: https://github.com/gaosong-loongson/loongarch-binary/releases Please review! Thanks. Song Gao Song Gao (17): hw/loongarch: Move boot fucntions to boot.c hw/loongarch: Add load initrd hw/loongarch: Add slave cpu boot_code hw/loongarch: Add init_cmdline hw/loongarch: Init efi_system_table hw/loongarch: Init efi_boot_memmap table hw/loongarch: Init efi_initrd table hw/loongarch: Init efi_fdt table hw/loongarch: Fix fdt memory node wrong 'reg' hw/loongarch: fdt adds cpu interrupt controller node hw/loongarch: fdt adds Extend I/O Interrupt Controller hw/loongarch: fdt adds pch_pic Controller hw/loongarch: fdt adds pch_msi Controller hw/loongarch: fdt adds pcie irq_map node hw/loongarch: fdt remove unused irqchip node hw/loongarch: Add cells missing from uart node hw/loongarch: Add cells missing from rtc node include/hw/intc/loongarch_extioi.h | 1 + include/hw/loongarch/boot.h| 109 + include/hw/loongarch/virt.h| 14 ++ include/hw/pci-host/ls7a.h | 2 + target/loongarch/cpu.h | 2 + hw/loongarch/boot.c| 330 ++ hw/loongarch/virt.c| 364 - hw/loongarch/meson.build | 1 + 8 files changed, 661 insertions(+), 162 deletions(-) create mode 100644 include/hw/loongarch/boot.h create mode 100644 hw/loongarch/boot.c
Re: [PATCH 1/3] linux-user/loongarch64: Remove TARGET_FORCE_SHMLBA
在 2024/2/23 上午11:03, Richard Henderson 写道:
The upstream linux kernel does not define __ARCH_FORCE_SHMLBA.
Cc: Song Gao
Signed-off-by: Richard Henderson
---
Did this definition come from the port before it was merged upstream?
Yes,
The patch [1] dropped it .
[1]
https://patchew.org/linux/20240106145501.3370364-1-chenhua...@loongson.cn/
Reviewed-by: Song Gao
Thanks.
Song Gao
Or was it incorrectly copied from MIPS?
---
linux-user/loongarch64/target_syscall.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/linux-user/loongarch64/target_syscall.h
b/linux-user/loongarch64/target_syscall.h
index 8b5de52124..39f229bb9c 100644
--- a/linux-user/loongarch64/target_syscall.h
+++ b/linux-user/loongarch64/target_syscall.h
@@ -38,11 +38,4 @@ struct target_pt_regs {
#define TARGET_MCL_FUTURE 2
#define TARGET_MCL_ONFAULT 4
-#define TARGET_FORCE_SHMLBA
-
-static inline abi_ulong target_shmlba(CPULoongArchState *env)
-{
-return 64 * KiB;
-}
-
#endif
Re: [PULL 0/1] loongarch-to-apply queue
在 2024/2/22 下午8:42, Peter Maydell 写道:
On Wed, 21 Feb 2024 at 09:11, Song Gao wrote:
The following changes since commit 760b4dcdddba4a40b9fa0eb78fdfc7eda7cb83d0:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2024-02-20 10:11:08 +)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240221
for you to fetch changes up to be57fd1e526e70fd55f1e87b0b70fab3c6baf089:
loongarch: Change the UEFI loading mode to loongarch (2024-02-21 17:06:23
+0800)
pull-loongarch-20240221
Xianglai Li (1):
loongarch: Change the UEFI loading mode to loongarch
Hi; this fails to build for mipsel:
https://gitlab.com/qemu-project/qemu/-/jobs/6232698129
../hw/loongarch/acpi-build.c: In function ‘build_flash_aml’:
../hw/loongarch/acpi-build.c:327:19: error: incompatible types when
assigning to type ‘hwaddr’ {aka ‘long long unsigned int’} from type
‘Int128’
327 | flash0_size = flash_mem->size;
| ^
../hw/loongarch/acpi-build.c:331:19: error: incompatible types when
assigning to type ‘hwaddr’ {aka ‘long long unsigned int’} from type
‘Int128’
331 | flash1_size = flash_mem->size;
| ^
../hw/loongarch/virt.c: In function ‘fdt_add_flash_node’:
../hw/loongarch/virt.c:131:19: error: incompatible types when
assigning to type ‘hwaddr’ {aka ‘long long unsigned int’} from type
‘Int128’
131 | flash0_size = flash_mem->size;
| ^
../hw/loongarch/virt.c:135:19: error: incompatible types when
assigning to type ‘hwaddr’ {aka ‘long long unsigned int’} from type
‘Int128’
135 | flash1_size = flash_mem->size;
| ^
The value you get back from pflash_cfi01_get_memory() is a
MemoryRegion -- this should be an opaque struct to you, not
something you can reach in and get the 'size' field from.
(The 'size' field is an Int128, which is not necessarily an
integer type known to the compiler -- on some platforms it is
a struct -- which is why this doesn't compile here.)
Your board code created these memory regions so typically it
should already know how big they are. If you really
do need to get the size of a MemoryRegion, the function
to use is memory_region_size(
Got it , I will correct it.
Thanks.
Song Gao
thanks
-- PMM
Re: [PATCH V2 1/1] loongarch: Change the UEFI loading mode to loongarch
在 2024/2/19 下午6:34, Xianglai Li 写道:
The UEFI loading mode in loongarch is very different
from that in other architectures:loongarch's UEFI code
is in rom, while other architectures' UEFI code is in flash.
loongarch UEFI can be loaded as follows:
-machine virt,pflash=pflash0-format
-bios ./QEMU_EFI.fd
Other architectures load UEFI using the following methods:
-machine virt,pflash0=pflash0-format,pflash1=pflash1-format
loongarch's UEFI loading method makes qemu and libvirt incompatible
when using NVRAM, and the cost of loongarch's current loading method
far outweighs the benefits, so we decided to use the same UEFI loading
scheme as other architectures.
Cc: Andrea Bolognani
Cc: maob...@loongson.cn
Cc: Philippe Mathieu-Daudé
Cc: Song Gao
Cc: zhaotian...@loongson.cn
Signed-off-by: Xianglai Li
Tested-by: Andrea Bolognani
---
hw/loongarch/acpi-build.c | 29 +--
hw/loongarch/virt.c | 101 ++--
include/hw/loongarch/virt.h | 10 ++--
3 files changed, 107 insertions(+), 33 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index a1c4198741..6c75f216ea 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -314,16 +314,39 @@ static void build_pci_device_aml(Aml *scope,
LoongArchMachineState *lams)
static void build_flash_aml(Aml *scope, LoongArchMachineState *lams)
{
Aml *dev, *crs;
+MemoryRegion *flash_mem;
-hwaddr flash_base = VIRT_FLASH_BASE;
-hwaddr flash_size = VIRT_FLASH_SIZE;
+hwaddr flash0_base;
+hwaddr flash0_size;
+
+hwaddr flash1_base;
+hwaddr flash1_size;
+
+flash_mem = pflash_cfi01_get_memory(lams->flash[0]);
+flash0_base = flash_mem->addr;
+flash0_size = flash_mem->size;
+
+flash_mem = pflash_cfi01_get_memory(lams->flash[1]);
+flash1_base = flash_mem->addr;
+flash1_size = flash_mem->size;
dev = aml_device("FLS0");
aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
aml_append(dev, aml_name_decl("_UID", aml_int(0)));
crs = aml_resource_template();
-aml_append(crs, aml_memory32_fixed(flash_base, flash_size,
AML_READ_WRITE));
+aml_append(crs, aml_memory32_fixed(flash0_base, flash0_size,
+ AML_READ_WRITE));
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(scope, dev);
+
+dev = aml_device("FLS1");
+aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
+aml_append(dev, aml_name_decl("_UID", aml_int(1)));
+
+crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(flash1_base, flash1_size,
+ AML_READ_WRITE));
aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(scope, dev);
}
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 0ad7d8c887..a7b9199e70 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -54,7 +54,9 @@ struct loaderparams {
const char *initrd_filename;
};
-static void virt_flash_create(LoongArchMachineState *lams)
+static PFlashCFI01 *virt_flash_create1(LoongArchMachineState *lams,
+ const char *name,
+ const char *alias_prop_name)
{
DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
@@ -66,45 +68,78 @@ static void virt_flash_create(LoongArchMachineState *lams)
qdev_prop_set_uint16(dev, "id1", 0x18);
qdev_prop_set_uint16(dev, "id2", 0x00);
qdev_prop_set_uint16(dev, "id3", 0x00);
-qdev_prop_set_string(dev, "name", "virt.flash");
-object_property_add_child(OBJECT(lams), "virt.flash", OBJECT(dev));
-object_property_add_alias(OBJECT(lams), "pflash",
+qdev_prop_set_string(dev, "name", name);
+object_property_add_child(OBJECT(lams), name, OBJECT(dev));
+object_property_add_alias(OBJECT(lams), alias_prop_name,
OBJECT(dev), "drive");
+return PFLASH_CFI01(dev);
+}
-lams->flash = PFLASH_CFI01(dev);
+static void virt_flash_create(LoongArchMachineState *lams)
+{
+lams->flash[0] = virt_flash_create1(lams, "virt.flash0", "pflash0");
+lams->flash[1] = virt_flash_create1(lams, "virt.flash1", "pflash1");
}
-static void virt_flash_map(LoongArchMachineState *lams,
- MemoryRegion *sysmem)
+static void virt_flash_map1(PFlashCFI01 *flash,
+hwaddr base, hwaddr size,
+MemoryRegion *sysmem)
{
-PFlashCFI01 *flash = lams->flash;
DeviceState *dev = DEVICE(flash);
-hwaddr base = VIRT_FLASH_BASE;
-hwaddr size = VIRT_FLASH_SIZE;
+BlockBackend *blk;
+hwaddr real_size = size;
+
+blk = pflash_cfi01_get_blk(flash);
+if (blk) {
+real_size = blk_getlength(blk);
+assert(real_size && real_size <= size);
+}
-assert(QEMU_IS_ALIGNED(size,
Re: [RESEND PATCH v4 00/17] Add boot LoongArch elf kernel with FDT
Ping ! 在 2024/1/18 下午7:31, Song Gao 写道: Hi, All We already support boot efi kernel with bios, but not support boot elf kernel. This series adds boot elf kernel with FDT. 'LoongArch supports ACPI and FDT. The information that needs to be passed to the kernel includes the memmap, the initrd, the command line, optionally the ACPI/FDT tables, and so on' see [1]. Patch 2-8 : Create efi system table, and three efi configuration table boot_memmap, initd, FDT. Patch 9-17 : Fixes FDT problems. Test: - Start kernel See [2] start_kernel.sh - Start qcow2 See [2] start_qcow2.sh V4: - patch 3 change slave_boot_code[] to const, and 'static void *p ' to 'void *p'; - patch 4 fixes build error; - patch 10-13, add project and commit link. V3: - Load initrd at kernel_high + 4 * kernel_size; - Load 'boot_rom' at [0 - 1M], the 'boot_rom' includes slave_boot_code, cmdline_buf and systab_tables; - R-b and rebase. V2: - FDT pcie node adds cells 'msi-map'; [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arch/loongarch/booting.rst?h=v6.7-rc4 [2]: https://github.com/gaosong-loongson/loongarch-binary/releases Please review! Thanks. Song Gao Song Gao (17): hw/loongarch: Move boot fucntions to boot.c hw/loongarch: Add load initrd hw/loongarch: Add slave cpu boot_code hw/loongarch: Add init_cmdline hw/loongarch: Init efi_system_table hw/loongarch: Init efi_boot_memmap table hw/loongarch: Init efi_initrd table hw/loongarch: Init efi_fdt table hw/loongarch: Fix fdt memory node wrong 'reg' hw/loongarch: fdt adds cpu interrupt controller node hw/loongarch: fdt adds Extend I/O Interrupt Controller hw/loongarch: fdt adds pch_pic Controller hw/loongarch: fdt adds pch_msi Controller hw/loongarch: fdt adds pcie irq_map node hw/loongarch: fdt remove unused irqchip node hw/loongarch: Add cells missing from uart node hw/loongarch: Add cells missing from rtc node include/hw/intc/loongarch_extioi.h | 1 + include/hw/loongarch/boot.h| 109 + include/hw/loongarch/virt.h| 14 ++ include/hw/pci-host/ls7a.h | 2 + target/loongarch/cpu.h | 2 + hw/loongarch/boot.c| 330 ++ hw/loongarch/virt.c| 364 - hw/loongarch/meson.build | 1 + 8 files changed, 661 insertions(+), 162 deletions(-) create mode 100644 include/hw/loongarch/boot.h create mode 100644 hw/loongarch/boot.c
Re: [PATCH] tcg/loongarch64: Set vector registers call clobbered
在 2024/2/2 上午7:34, Richard Henderson 写道:
Because there are more call clobbered registers than
call saved registers, we begin with all registers as
call clobbered and then reset those that are saved.
This was missed when we introduced the LSX support.
Cc: qemu-sta...@nongnu.org
Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2136
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Thank you !
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index bab0a173a3..dcf0205458 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -2327,7 +2327,7 @@ static void tcg_target_init(TCGContext *s)
tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
-tcg_target_call_clobber_regs = ALL_GENERAL_REGS;
+tcg_target_call_clobber_regs = ALL_GENERAL_REGS | ALL_VECTOR_REGS;
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
Re: [PATCH] tcg: Fixes set const_args[i] wrong value when instructions imm is 0
在 2024/2/1 上午5:16, Richard Henderson 写道:
On 1/31/24 17:27, Song Gao wrote:
It seems that tcg_reg_alloc_op() set const_args[i] wrong value
when instructions imm is 0. The LoongArch tcg_out_vec_op() cmp_vec
use the wrong const_args[2].
e.g
The wrong const_args[2] is 0.
IN: vslti.w v5, v4, 0x0 OUT: vslt.w v1, v1, v0
The right const_args[2] is 1.
IN: vslti.w v5, v4, 0x0 OUT: vslti.w v1, v1, 0x0
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2136
Signed-off-by: Song Gao
---
tcg/tcg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index e2c38f6d11..5b290123bc 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -4808,7 +4808,7 @@ static void tcg_reg_alloc_op(TCGContext *s,
const TCGOp *op)
arg_ct = >args_ct[i];
ts = arg_temp(arg);
- if (ts->val_type == TEMP_VAL_CONST
+ if ((ts->val_type == TEMP_VAL_CONST || ts->kind == TEMP_CONST)
&& tcg_target_const_match(ts->val, ts->type,
arg_ct->ct, TCGOP_VECE(op))) {
/* constant is OK for instruction */
const_args[i] = 1;
This is wrong.
I strongly suspect that the TEMP_CONST value 0 has been loaded into a
register for use in another operation, and the register allocator sees
that it is still there.
Ah, I'm not familiar with this piece of code, I just try to fix the bug,
and thanks for your suggestion.
Thanks.
Song Gao
r~
Re: [NOTFORMERGE PATCH 2/2] gitlab: Add Loongarch64 KVM-only build
Hi,
在 2024/1/11 下午7:26, Philippe Mathieu-Daudé 写道:
On 11/1/24 10:51, gaosong wrote:
在 2024/1/11 下午5:04, Thomas Huth 写道:
On 11/01/2024 09.50, gaosong wrote:
在 2024/1/11 下午4:20, Thomas Huth 写道:
On 11/01/2024 08.37, gaosong wrote:
LoongArch no support these cmds or some problems .
- "gva2gpa 0",
- "memsave 0 4096 \"/dev/null\"",
- "x /8i 0x100",
- "xp /16x 0",
Could we disable these 4 cmds or the test_temp check?
After we fix the cmds problems, we can enable them.
Even if loongarch does not support one of these commands, it should
not crash QEMU. So please fix the crashes first before considering
to enable the KVM-only test in the CI.
Sure, we will fix the cmds problems first.
The issue might be missing get_phys_page_attrs_debug() implementation.
We use '--enable-kvm --disable-tcg ',
the get_phys_page_debug() is NULL, so the test-hmp failed.
target/loongarch/cpu.c
...
#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps loongarch_sysemu_ops = {
#ifdef CONFIG_TCG
.get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
#endif
};
...
I see the other architectures only implement
get_phys_page_attrs_debug() or get_phys_page_debug()
and not only build these functions on tcg mode.
Should we need implement get_phys_page_attrs_debug() ? or just use
get_phys_page_debug()
Thanks.
Song Gao
Re: [PATCH] target/loongarch: Set cpuid CSR register only once with kvm mode
在 2024/1/15 下午4:51, Bibo Mao 写道:
CSR cpuid register is used for routing irq to different vcpus, its
value is kept unchanged since poweron. So it is not necessary to
set CSR cpuid register after system resets, and it is only set at
vm creation stage.
Signed-off-by: Bibo Mao
---
target/loongarch/kvm/kvm.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index 84bcdf5f86..2230f029d0 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -250,7 +250,7 @@ static int kvm_loongarch_get_csr(CPUState *cs)
return ret;
}
-static int kvm_loongarch_put_csr(CPUState *cs)
+static int kvm_loongarch_put_csr(CPUState *cs, int level)
{
int ret = 0;
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
@@ -322,8 +322,11 @@ static int kvm_loongarch_put_csr(CPUState *cs)
ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_RVACFG),
>CSR_RVACFG);
-ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CPUID),
+/* CPUID is constant after poweron, it should be set only once */
+if (level >= KVM_PUT_FULL_STATE) {
+ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CPUID),
>CSR_CPUID);
+}
ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG1),
>CSR_PRCFG1);
@@ -598,7 +601,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
return ret;
}
-ret = kvm_loongarch_put_csr(cs);
+ret = kvm_loongarch_put_csr(cs, level);
if (ret) {
return ret;
}
base-commit: 977542ded7e6b28d2bc077bcda24568c716e393c
Re: [PATCH 1/1] target/loongarch/kvm: Enable LSX/LASX extension
在 2024/1/22 下午3:12, maobibo 写道:
On 2024/1/22 下午2:09, Song Gao wrote:
The kernel had already support LSX and LASX [1],
but QEMU is disable LSX/LASX for kvm. This patch adds
kvm_check_cpucfg to check CPUCFG2.
[1]:
https://lore.kernel.org/all/cabgobfzhrf7e_7jk4uprmsyxty3eiuuywhc35jqncnl9s-z...@mail.gmail.com/
Signed-off-by: Song Gao
---
linux-headers/asm-loongarch/kvm.h | 1 +
target/loongarch/kvm/kvm.c | 35 ---
2 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/linux-headers/asm-loongarch/kvm.h
b/linux-headers/asm-loongarch/kvm.h
index c6ad2ee610..923d0bd382 100644
--- a/linux-headers/asm-loongarch/kvm.h
+++ b/linux-headers/asm-loongarch/kvm.h
@@ -79,6 +79,7 @@ struct kvm_fpu {
#define LOONGARCH_REG_64(TYPE, REG) (TYPE | KVM_REG_SIZE_U64 |
(REG << LOONGARCH_REG_SHIFT))
#define KVM_IOC_CSRID(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CSR,
REG)
#define KVM_IOC_CPUCFG(REG)
LOONGARCH_REG_64(KVM_REG_LOONGARCH_CPUCFG, REG)
+#define KVM_LOONGARCH_VCPU_CPUCFG 0
struct kvm_debug_exit_arch {
};
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index 84bcdf5f86..41b6947c7b 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -537,6 +537,28 @@ static int kvm_loongarch_get_cpucfg(CPUState *cs)
return ret;
}
+static int kvm_check_cpucfg(int id, CPUState *cs)
+{
+ int ret;
+ uint64_t val;
+ struct kvm_device_attr attr = {
+ .group = KVM_LOONGARCH_VCPU_CPUCFG,
+ .attr = id,
+ .addr = (uint64_t),
+ };
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = >env;
+
+ ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, );
+
+ if (!ret) {
+ kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, );
+ env->cpucfg[id] &= val;
With feature bit represents supported or disabled, it is ok to use
logic of qemu feature bitmap and kvm supported feature bitmap.
However about feature version, there will be problem with "and logic".
Can we use minimal version here?
Yes, we can, I will correct it on v2.
Thanks.
Song Gao
Regards
Bibo Mao
+ }
+
+ return ret;
+}
+
static int kvm_loongarch_put_cpucfg(CPUState *cs)
{
int i, ret = 0;
@@ -545,14 +567,13 @@ static int kvm_loongarch_put_cpucfg(CPUState *cs)
uint64_t val;
for (i = 0; i < 21; i++) {
+ if (i == 2) {
+ ret = kvm_check_cpucfg(i, cs);
+ if (ret) {
+ return ret;
+ }
+ }
val = env->cpucfg[i];
- /* LSX and LASX and LBT are not supported in kvm now */
- if (i == 2) {
- val &= ~(BIT(R_CPUCFG2_LSX_SHIFT) |
BIT(R_CPUCFG2_LASX_SHIFT));
- val &= ~(BIT(R_CPUCFG2_LBT_X86_SHIFT) |
- BIT(R_CPUCFG2_LBT_ARM_SHIFT) |
- BIT(R_CPUCFG2_LBT_MIPS_SHIFT));
- }
ret = kvm_set_one_reg(cs, KVM_IOC_CPUCFG(i), );
if (ret < 0) {
trace_kvm_failed_put_cpucfg(strerror(errno));
Re: [PATCH v4 00/17] Add boot LoongArch elf kernel with FDT
Please ignore this, I will resend it. 在 2024/1/18 下午7:18, Song Gao 写道: Hi, All We already support boot efi kernel with bios, but not support boot elf kernel. This series adds boot elf kernel with FDT. 'LoongArch supports ACPI and FDT. The information that needs to be passed to the kernel includes the memmap, the initrd, the command line, optionally the ACPI/FDT tables, and so on' see [1]. Patch 2-8 : Create efi system table, and three efi configuration table boot_memmap, initd, FDT. Patch 9-17 : Fixes FDT problems. Test: - Start kernel See [2] start_kernel.sh - Start qcow2 See [2] start_qcow2.sh V4: - patch 3 change slave_boot_code[] to const, and 'static void *p ' to 'void *p'; - patch 4 fixes build error; - patch 10-13, add project and commit link. V3: - Load initrd at kernel_high + 4 * kernel_size; - Load 'boot_rom' at [0 - 1M], the 'boot_rom' includes V3: - Load initrd at kernel_high + 4 * kernel_size; - Load 'boot_rom' at [0 - 1M], the 'boot_rom' includes slave_boot_code, cmdline_buf and systab_tables; - R-b and rebase. V2: - FDT pcie node adds cells 'msi-map'; [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arch/loongarch/booting.rst?h=v6.7-rc4 [2]: https://github.com/gaosong-loongson/loongarch-binary/releases Please review! Thanks. Song Gao Song Gao (17): hw/loongarch: Move boot fucntions to boot.c hw/loongarch: Add load initrd hw/loongarch: Add slave cpu boot_code hw/loongarch: Add init_cmdline hw/loongarch: Init efi_system_table hw/loongarch: Init efi_boot_memmap table hw/loongarch: Init efi_initrd table hw/loongarch: Init efi_fdt table hw/loongarch: Fix fdt memory node wrong 'reg' hw/loongarch: fdt adds cpu interrupt controller node hw/loongarch: fdt adds Extend I/O Interrupt Controller hw/loongarch: fdt adds pch_pic Controller hw/loongarch: fdt adds pch_msi Controller hw/loongarch: fdt adds pcie irq_map node hw/loongarch: fdt remove unused irqchip node hw/loongarch: Add cells missing from uart node hw/loongarch: Add cells missing from rtc node include/hw/intc/loongarch_extioi.h | 1 + include/hw/loongarch/boot.h| 109 + include/hw/loongarch/virt.h| 14 ++ include/hw/pci-host/ls7a.h | 2 + target/loongarch/cpu.h | 2 + hw/loongarch/boot.c| 330 ++ hw/loongarch/virt.c| 364 - hw/loongarch/meson.build | 1 + 8 files changed, 661 insertions(+), 162 deletions(-) create mode 100644 include/hw/loongarch/boot.h create mode 100644 hw/loongarch/boot.c
Re: [PATCH 1/2] gitlab: Introduce Loongarch64 runner
在 2024/1/12 下午5:52, gaosong 写道:
在 2024/1/11 下午4:26, Thomas Huth 写道:
On 11/01/2024 08.25, gaosong wrote:
Hi,
在 2024/1/11 下午3:08, Thomas Huth 写道:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Full build config to run CI tests on a Loongarch64 host.
Forks might enable this by setting LOONGARCH64_RUNNER_AVAILABLE
in their CI namespace settings, see:
https://www.qemu.org/docs/master/devel/ci.html#maintainer-controlled-job-variables
Signed-off-by: Philippe Mathieu-Daudé
---
docs/devel/ci-jobs.rst.inc | 6 ++
.gitlab-ci.d/custom-runners.yml | 1 +
.../openeuler-22.03-loongarch64.yml | 21
+++
3 files changed, 28 insertions(+)
create mode 100644
.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
...
diff --git a/.gitlab-ci.d/custom-runners.yml
b/.gitlab-ci.d/custom-runners.yml
index 8e5b9500f4..152ace4492 100644
--- a/.gitlab-ci.d/custom-runners.yml
+++ b/.gitlab-ci.d/custom-runners.yml
@@ -32,3 +32,4 @@ include:
- local: '/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml'
- local: '/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch32.yml'
- local:
'/.gitlab-ci.d/custom-runners/centos-stream-8-x86_64.yml'
+ - local:
'/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml'
diff --git
a/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
b/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
new file mode 100644
index 00..86d18f820e
--- /dev/null
+++ b/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
@@ -0,0 +1,21 @@
+openeuler-22.03-loongarch64-all:
+ extends: .custom_runner_template :-)
+ needs: []
+ stage: build
+ tags:
+ - oe2203
+ - loongarch64
+ rules:
+ - if: '$CI_PROJECT_NAMESPACE == "qemu-project" &&
$CI_COMMIT_BRANCH =~ /^staging/'
+ when: manual
+ allow_failure: true
+ - if: "$LOONGARCH64_RUNNER_AVAILABLE"
+ when: manual
+ allow_failure: true
+ script:
+ - mkdir build
+ - cd build
+ - ../configure
+ || { cat config.log meson-logs/meson-log.txt; exit 1; }
+ - make --output-sync -j`nproc --ignore=40`
+ - make --output-sync -j`nproc --ignore=40` check
Does this system really have more than 40 CPU threads? Or is this a
copy-n-past from one of the other scripts? In the latter case, I'd
suggest to adjust the --ignore=40 to a more reasonable value.
Thomas
No, only 32. I think it should be --ignore=32 or 16.
--ignore=32 then also does not make much sense, that would still be
the same as simply omitting the -j parameter. I guess --ignore=16
should be fine.
I create a same runner on this machine, and I find some check error.
but I am not sure how to fix it. :-)
See:
https://gitlab.com/gaosong/qemu/-/jobs/5906269934
Seems to be related to RAM backing... for example, the erst-test is
failing, which is doing something like:
setup_vm_cmd(,
"-object memory-backend-file,"
"mem-path=acpi-erst.XX,"
"size=64K,"
Hi,
We tested this on
LoongArch host with the 5.10 kernel, (openEuler 22.03),
x86_64 host with 5.10 kernel, (openEuler 22.03)
x86_64 host with 5.15kernel , (Ubuntu 20.04.3 LTS)
and didn't get any error.
but the CI machine use the 6.7_rc4 kernel.
we didn't update the x86_64 host kernel to tested this.
Is it possible that the new kernel is causing the problem?
Hi,
The kernel adds the patch[1] can fix this problem.
[1]
https://patchew.org/linux/20240106145501.3370364-1-chenhua...@loongson.cn/
So
Tested-by: Song Gao
Reviewed-by: Song Gao
Thanks.
Song Gao
"share=on,"
"id=nvram "
"-device acpi-erst,"
"memdev=nvram");
So it seems like -object memory-backend-file" is not correctly
working in your gitlab runner? Is there some setup missing?
Thomas
Re: [PATCH 1/2] gitlab: Introduce Loongarch64 runner
在 2024/1/11 下午4:26, Thomas Huth 写道:
On 11/01/2024 08.25, gaosong wrote:
Hi,
在 2024/1/11 下午3:08, Thomas Huth 写道:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Full build config to run CI tests on a Loongarch64 host.
Forks might enable this by setting LOONGARCH64_RUNNER_AVAILABLE
in their CI namespace settings, see:
https://www.qemu.org/docs/master/devel/ci.html#maintainer-controlled-job-variables
Signed-off-by: Philippe Mathieu-Daudé
---
docs/devel/ci-jobs.rst.inc | 6 ++
.gitlab-ci.d/custom-runners.yml | 1 +
.../openeuler-22.03-loongarch64.yml | 21
+++
3 files changed, 28 insertions(+)
create mode 100644
.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
...
diff --git a/.gitlab-ci.d/custom-runners.yml
b/.gitlab-ci.d/custom-runners.yml
index 8e5b9500f4..152ace4492 100644
--- a/.gitlab-ci.d/custom-runners.yml
+++ b/.gitlab-ci.d/custom-runners.yml
@@ -32,3 +32,4 @@ include:
- local: '/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml'
- local: '/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch32.yml'
- local: '/.gitlab-ci.d/custom-runners/centos-stream-8-x86_64.yml'
+ - local:
'/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml'
diff --git
a/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
b/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
new file mode 100644
index 00..86d18f820e
--- /dev/null
+++ b/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
@@ -0,0 +1,21 @@
+openeuler-22.03-loongarch64-all:
+ extends: .custom_runner_template :-)
+ needs: []
+ stage: build
+ tags:
+ - oe2203
+ - loongarch64
+ rules:
+ - if: '$CI_PROJECT_NAMESPACE == "qemu-project" &&
$CI_COMMIT_BRANCH =~ /^staging/'
+ when: manual
+ allow_failure: true
+ - if: "$LOONGARCH64_RUNNER_AVAILABLE"
+ when: manual
+ allow_failure: true
+ script:
+ - mkdir build
+ - cd build
+ - ../configure
+ || { cat config.log meson-logs/meson-log.txt; exit 1; }
+ - make --output-sync -j`nproc --ignore=40`
+ - make --output-sync -j`nproc --ignore=40` check
Does this system really have more than 40 CPU threads? Or is this a
copy-n-past from one of the other scripts? In the latter case, I'd
suggest to adjust the --ignore=40 to a more reasonable value.
Thomas
No, only 32. I think it should be --ignore=32 or 16.
--ignore=32 then also does not make much sense, that would still be
the same as simply omitting the -j parameter. I guess --ignore=16
should be fine.
I create a same runner on this machine, and I find some check error.
but I am not sure how to fix it. :-)
See:
https://gitlab.com/gaosong/qemu/-/jobs/5906269934
Seems to be related to RAM backing... for example, the erst-test is
failing, which is doing something like:
setup_vm_cmd(,
"-object memory-backend-file,"
"mem-path=acpi-erst.XX,"
"size=64K,"
Hi,
We tested this on
LoongArch host with the 5.10 kernel, (openEuler 22.03),
x86_64 host with 5.10 kernel, (openEuler 22.03)
x86_64 host with 5.15kernel , (Ubuntu 20.04.3 LTS)
and didn't get any error.
but the CI machine use the 6.7_rc4 kernel.
we didn't update the x86_64 host kernel to tested this.
Is it possible that the new kernel is causing the problem?
"share=on,"
"id=nvram "
"-device acpi-erst,"
"memdev=nvram");
So it seems like -object memory-backend-file" is not correctly working
in your gitlab runner? Is there some setup missing?
Thomas
Re: [PATCH 1/2] gitlab: Introduce Loongarch64 runner
在 2024/1/11 下午4:26, Thomas Huth 写道:
On 11/01/2024 08.25, gaosong wrote:
Hi,
在 2024/1/11 下午3:08, Thomas Huth 写道:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Full build config to run CI tests on a Loongarch64 host.
Forks might enable this by setting LOONGARCH64_RUNNER_AVAILABLE
in their CI namespace settings, see:
https://www.qemu.org/docs/master/devel/ci.html#maintainer-controlled-job-variables
Signed-off-by: Philippe Mathieu-Daudé
---
docs/devel/ci-jobs.rst.inc | 6 ++
.gitlab-ci.d/custom-runners.yml | 1 +
.../openeuler-22.03-loongarch64.yml | 21
+++
3 files changed, 28 insertions(+)
create mode 100644
.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
...
diff --git a/.gitlab-ci.d/custom-runners.yml
b/.gitlab-ci.d/custom-runners.yml
index 8e5b9500f4..152ace4492 100644
--- a/.gitlab-ci.d/custom-runners.yml
+++ b/.gitlab-ci.d/custom-runners.yml
@@ -32,3 +32,4 @@ include:
- local: '/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml'
- local: '/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch32.yml'
- local: '/.gitlab-ci.d/custom-runners/centos-stream-8-x86_64.yml'
+ - local:
'/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml'
diff --git
a/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
b/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
new file mode 100644
index 00..86d18f820e
--- /dev/null
+++ b/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
@@ -0,0 +1,21 @@
+openeuler-22.03-loongarch64-all:
+ extends: .custom_runner_template :-)
+ needs: []
+ stage: build
+ tags:
+ - oe2203
+ - loongarch64
+ rules:
+ - if: '$CI_PROJECT_NAMESPACE == "qemu-project" &&
$CI_COMMIT_BRANCH =~ /^staging/'
+ when: manual
+ allow_failure: true
+ - if: "$LOONGARCH64_RUNNER_AVAILABLE"
+ when: manual
+ allow_failure: true
+ script:
+ - mkdir build
+ - cd build
+ - ../configure
+ || { cat config.log meson-logs/meson-log.txt; exit 1; }
+ - make --output-sync -j`nproc --ignore=40`
+ - make --output-sync -j`nproc --ignore=40` check
Does this system really have more than 40 CPU threads? Or is this a
copy-n-past from one of the other scripts? In the latter case, I'd
suggest to adjust the --ignore=40 to a more reasonable value.
Thomas
No, only 32. I think it should be --ignore=32 or 16.
--ignore=32 then also does not make much sense, that would still be
the same as simply omitting the -j parameter. I guess --ignore=16
should be fine.
I create a same runner on this machine, and I find some check error.
but I am not sure how to fix it. :-)
See:
https://gitlab.com/gaosong/qemu/-/jobs/5906269934
Seems to be related to RAM backing... for example, the erst-test is
failing, which is doing something like:
setup_vm_cmd(,
"-object memory-backend-file,"
"mem-path=acpi-erst.XX,"
"size=64K,"
"share=on,"
"id=nvram "
"-device acpi-erst,"
"memdev=nvram");
So it seems like -object memory-backend-file" is not correctly working
in your gitlab runner? Is there some setup missing?
Thomas
This is my runner config.
concurrent = 32
check_interval = 0
shutdown_timeout = 0
[session_server]
session_timeout = 1800
...
[[runners]]
name = "loongarch64"
request_concurrency = 24
url = "https://gitlab.com;
id = 31426483
token = "glrt-bGugocYrR2yqcu3ma7ka"
token_obtained_at = 2024-01-10T08:31:29Z
token_expires_at = 0001-01-01T00:00:00Z
executor = "shell"
builds_dir = "/data/gitlab-runner/builds"
cache_dir = "/data/gitlab-runner/cache"
[runners.cache]
MaxUploadedArchiveSize = 0
I create a project runner 'loongarch64' for my branch ci-master.
Do we need some special configuration?
and I just './configure --target-list="x86_64-softmmu"
--enable-debug' on LoongArch host. make , make check.
I got the same error.
[7/361] qemu:qtest+qtest-x86_64 /
qtest-x86_64/qos-test 2928s 60
subtests passed
^CWARNING: Received SIGTERM, exiting
7/361 qemu:qtest+qtest-x86_64 /
qtest-x86_64/qos-test INTERRUPT 4671.32s killed
by signal 11 SIGSEGV
>>> PYTHON=/home/gs/gitlab/qemu/build/pyvenv/bin/python3
G_TEST_DBUS_DAEMON=/home/gs/gitlab/qemu/tests/dbus-vmstate-daemon.sh
MALLOC_PERTURB_=198 QTEST_QEMU_IMG=./qemu-img
QTEST_QEMU_BINARY=./qemu-system-x86_64
QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon
/home/gs/gitlab/qemu/build/tests/qtest/qos-test --tap -k
― ✀
―
Re: [NOTFORMERGE PATCH 2/2] gitlab: Add Loongarch64 KVM-only build
在 2024/1/11 下午7:26, Philippe Mathieu-Daudé 写道: On 11/1/24 10:51, gaosong wrote: 在 2024/1/11 下午5:04, Thomas Huth 写道: On 11/01/2024 09.50, gaosong wrote: 在 2024/1/11 下午4:20, Thomas Huth 写道: On 11/01/2024 08.37, gaosong wrote: LoongArch no support these cmds or some problems . - "gva2gpa 0", - "memsave 0 4096 \"/dev/null\"", - "x /8i 0x100", - "xp /16x 0", Could we disable these 4 cmds or the test_temp check? After we fix the cmds problems, we can enable them. Even if loongarch does not support one of these commands, it should not crash QEMU. So please fix the crashes first before considering to enable the KVM-only test in the CI. Sure, we will fix the cmds problems first. The issue might be missing get_phys_page_attrs_debug() implementation. yes, I see, from hmp_gva2gpa(). I think we need implement it. Thanks. Song Gao
Re: [NOTFORMERGE PATCH 2/2] gitlab: Add Loongarch64 KVM-only build
在 2024/1/11 下午5:04, Thomas Huth 写道: On 11/01/2024 09.50, gaosong wrote: 在 2024/1/11 下午4:20, Thomas Huth 写道: On 11/01/2024 08.37, gaosong wrote: Hi, 在 2024/1/11 下午3:10, Thomas Huth 写道: On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé --- Used to test https://lore.kernel.org/qemu-devel/20231228084051.3235354-1-zhaotian...@loongson.cn/ So why is it NOTFORMERGE ? Don't we want to test KVM-only builds for loongarch in the long run? Thomas I think we can drop this title. I tested this job by the latest loongarch kvm patches. buf I find a test-hmp check error. Can you recreate the error manually? i.e. compile with configure --disable-tcg and then run: V=2 QTEST_QEMU_BINARY=./qemu-system-loongarch64 tests/qtest/test-hmp That should likely provide you with a hint where it is crashing Thomas Thank you, LoongArch no support these cmds or some problems . - "gva2gpa 0", - "memsave 0 4096 \"/dev/null\"", - "x /8i 0x100", - "xp /16x 0", Could we disable these 4 cmds or the test_temp check? After we fix the cmds problems, we can enable them. Even if loongarch does not support one of these commands, it should not crash QEMU. So please fix the crashes first before considering to enable the KVM-only test in the CI. Sure, we will fix the cmds problems first. Thanks. Song Gao
Re: [NOTFORMERGE PATCH 2/2] gitlab: Add Loongarch64 KVM-only build
在 2024/1/11 下午4:20, Thomas Huth 写道: On 11/01/2024 08.37, gaosong wrote: Hi, 在 2024/1/11 下午3:10, Thomas Huth 写道: On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé --- Used to test https://lore.kernel.org/qemu-devel/20231228084051.3235354-1-zhaotian...@loongson.cn/ So why is it NOTFORMERGE ? Don't we want to test KVM-only builds for loongarch in the long run? Thomas I think we can drop this title. I tested this job by the latest loongarch kvm patches. buf I find a test-hmp check error. Can you recreate the error manually? i.e. compile with configure --disable-tcg and then run: V=2 QTEST_QEMU_BINARY=./qemu-system-loongarch64 tests/qtest/test-hmp That should likely provide you with a hint where it is crashing Thomas Thank you, LoongArch no support these cmds or some problems . - "gva2gpa 0", - "memsave 0 4096 \"/dev/null\"", - "x /8i 0x100", - "xp /16x 0", Could we disable these 4 cmds or the test_temp check? After we fix the cmds problems, we can enable them. Thanks. Song gao
Re: [NOTFORMERGE PATCH 2/2] gitlab: Add Loongarch64 KVM-only build
Hi,
在 2024/1/11 下午3:10, Thomas Huth 写道:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
Used to test
https://lore.kernel.org/qemu-devel/20231228084051.3235354-1-zhaotian...@loongson.cn/
So why is it NOTFORMERGE ? Don't we want to test KVM-only builds for
loongarch in the long run?
Thomas
I think we can drop this title.
I tested this job by the latest loongarch kvm patches. buf I find a
test-hmp check error.
See:
https://gitlab.com/gaosong/qemu/-/jobs/5906385234
If you want to log in to this machine, we can create an account for you.
Thanks.
Song Gao
---
.../openeuler-22.03-loongarch64.yml | 22 +++
1 file changed, 22 insertions(+)
diff --git
a/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
b/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
index 86d18f820e..60674b8d0f 100644
--- a/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
+++ b/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
@@ -19,3 +19,25 @@ openeuler-22.03-loongarch64-all:
|| { cat config.log meson-logs/meson-log.txt; exit 1; }
- make --output-sync -j`nproc --ignore=40`
- make --output-sync -j`nproc --ignore=40` check
+
+openeuler-22.03-loongarch64-kvm:
+ extends: .custom_runner_template
+ needs: []
+ stage: build
+ tags:
+ - oe2203
+ - loongarch64
+ rules:
+ - if: '$CI_PROJECT_NAMESPACE == "qemu-project" && $CI_COMMIT_BRANCH
=~ /^staging/'
+ when: manual
+ allow_failure: true
+ - if: "$LOONGARCH64_RUNNER_AVAILABLE"
+ when: manual
+ allow_failure: true
+ script:
+ - mkdir build
+ - cd build
+ - ../configure --enable-kvm --disable-tcg
+ || { cat config.log meson-logs/meson-log.txt; exit 1; }
+ - make --output-sync -j`nproc --ignore=40`
+ - make --output-sync -j`nproc --ignore=40` check
Re: [PATCH 1/2] gitlab: Introduce Loongarch64 runner
Hi,
在 2024/1/11 下午3:08, Thomas Huth 写道:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Full build config to run CI tests on a Loongarch64 host.
Forks might enable this by setting LOONGARCH64_RUNNER_AVAILABLE
in their CI namespace settings, see:
https://www.qemu.org/docs/master/devel/ci.html#maintainer-controlled-job-variables
Signed-off-by: Philippe Mathieu-Daudé
---
docs/devel/ci-jobs.rst.inc | 6 ++
.gitlab-ci.d/custom-runners.yml | 1 +
.../openeuler-22.03-loongarch64.yml | 21 +++
3 files changed, 28 insertions(+)
create mode 100644
.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
...
diff --git a/.gitlab-ci.d/custom-runners.yml
b/.gitlab-ci.d/custom-runners.yml
index 8e5b9500f4..152ace4492 100644
--- a/.gitlab-ci.d/custom-runners.yml
+++ b/.gitlab-ci.d/custom-runners.yml
@@ -32,3 +32,4 @@ include:
- local: '/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml'
- local: '/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch32.yml'
- local: '/.gitlab-ci.d/custom-runners/centos-stream-8-x86_64.yml'
+ - local:
'/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml'
diff --git
a/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
b/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
new file mode 100644
index 00..86d18f820e
--- /dev/null
+++ b/.gitlab-ci.d/custom-runners/openeuler-22.03-loongarch64.yml
@@ -0,0 +1,21 @@
+openeuler-22.03-loongarch64-all:
+ extends: .custom_runner_template :-)
+ needs: []
+ stage: build
+ tags:
+ - oe2203
+ - loongarch64
+ rules:
+ - if: '$CI_PROJECT_NAMESPACE == "qemu-project" && $CI_COMMIT_BRANCH
=~ /^staging/'
+ when: manual
+ allow_failure: true
+ - if: "$LOONGARCH64_RUNNER_AVAILABLE"
+ when: manual
+ allow_failure: true
+ script:
+ - mkdir build
+ - cd build
+ - ../configure
+ || { cat config.log meson-logs/meson-log.txt; exit 1; }
+ - make --output-sync -j`nproc --ignore=40`
+ - make --output-sync -j`nproc --ignore=40` check
Does this system really have more than 40 CPU threads? Or is this a
copy-n-past from one of the other scripts? In the latter case, I'd
suggest to adjust the --ignore=40 to a more reasonable value.
Thomas
No, only 32. I think it should be --ignore=32 or 16.
I create a same runner on this machine, and I find some check error.
but I am not sure how to fix it. :-)
See:
https://gitlab.com/gaosong/qemu/-/jobs/5906269934
Thanks.
Song Gao
Re: [PATCH v4 8/9b] target/loongarch: Implement set vcpu intr for kvm
Hi,
在 2024/1/10 下午5:41, Philippe Mathieu-Daudé 写道:
From: Tianrui Zhao
Implement loongarch kvm set vcpu interrupt interface,
when a irq is set in vcpu, we use the KVM_INTERRUPT
ioctl to set intr into kvm.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Song Gao
Message-ID: <20240105075804.1228596-9-zhaotian...@loongson.cn>
[PMD: Split from bigger patch, part 2]
Signed-off-by: Philippe Mathieu-Daudé
---
target/loongarch/kvm/kvm_loongarch.h | 16
target/loongarch/cpu.c | 9 -
target/loongarch/kvm/kvm.c | 15 +++
target/loongarch/trace-events| 1 +
4 files changed, 40 insertions(+), 1 deletion(-)
create mode 100644 target/loongarch/kvm/kvm_loongarch.h
diff --git a/target/loongarch/kvm/kvm_loongarch.h
b/target/loongarch/kvm/kvm_loongarch.h
new file mode 100644
index 00..d945b6bb82
--- /dev/null
+++ b/target/loongarch/kvm/kvm_loongarch.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch kvm interface
+ *
+ * Copyright (c) 2023 Loongson Technology Corporation Limited
+ */
+
+#include "cpu.h"
+
+#ifndef QEMU_KVM_LOONGARCH_H
+#define QEMU_KVM_LOONGARCH_H
+
+int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level);
+void kvm_arch_reset_vcpu(CPULoongArchState *env);
+
+#endif
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index d9f8661cfd..d3a8a2f521 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -12,6 +12,7 @@
#include "qemu/module.h"
#include "sysemu/qtest.h"
#include "sysemu/tcg.h"
+#include "sysemu/kvm.h"
#include "exec/exec-all.h"
#include "cpu.h"
#include "internals.h"
@@ -21,6 +22,10 @@
#include "sysemu/reset.h"
#endif
#include "vec.h"
+#ifdef CONFIG_KVM
+#include "kvm/kvm_loongarch.h"
This broken tcg 'loongarch64-softmmu' build on X86 host, :-[
../target/loongarch/cpu.c: In function ‘loongarch_cpu_set_irq’:
../target/loongarch/cpu.c:122:9: error: implicit declaration of function
‘kvm_loongarch_set_interrupt’ [-Werror=implicit-function-declaration]
122 | kvm_loongarch_set_interrupt(cpu, irq, level);
| ^~~
../target/loongarch/cpu.c:122:9: error: nested extern declaration of
‘kvm_loongarch_set_interrupt’ [-Werror=nested-externs]
../target/loongarch/cpu.c: In function ‘loongarch_cpu_reset_hold’:
../target/loongarch/cpu.c:557:9: error: implicit declaration of function
‘kvm_arch_reset_vcpu’; did you mean ‘kvm_arch_init_vcpu’?
[-Werror=implicit-function-declaration]
557 | kvm_arch_reset_vcpu(env);
| ^~~
| kvm_arch_init_vcpu
../target/loongarch/cpu.c:557:9: error: nested extern declaration of
‘kvm_arch_reset_vcpu’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
I will move it out of '#ifdef CONFIG_KVM'
Thanks.
Song Gao
+#include
+#endif
#ifdef CONFIG_TCG
#include "exec/cpu_ldst.h"
#include "tcg/tcg.h"
@@ -113,7 +118,9 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int level)
return;
}
-if (tcg_enabled()) {
+if (kvm_enabled()) {
+kvm_loongarch_set_interrupt(cpu, irq, level);
+} else if (tcg_enabled()) {
env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index d2dab3fef4..bd33ec2114 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -748,6 +748,21 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
return ret;
}
+int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level)
+{
+struct kvm_interrupt intr;
+CPUState *cs = CPU(cpu);
+
+if (level) {
+intr.irq = irq;
+} else {
+intr.irq = -irq;
+}
+
+trace_kvm_set_intr(irq, level);
+return kvm_vcpu_ioctl(cs, KVM_INTERRUPT, );
+}
+
void kvm_arch_accel_class_init(ObjectClass *oc)
{
}
diff --git a/target/loongarch/trace-events b/target/loongarch/trace-events
index 021839880e..dea11edc0f 100644
--- a/target/loongarch/trace-events
+++ b/target/loongarch/trace-events
@@ -12,3 +12,4 @@ kvm_failed_put_counter(const char *msg) "Failed to put counter
into KVM: %s"
kvm_failed_get_cpucfg(const char *msg) "Failed to get cpucfg from KVM: %s"
kvm_failed_put_cpucfg(const char *msg) "Failed to put cpucfg into KVM: %s"
kvm_arch_handle_exit(int num) "kvm arch handle exit, the reason number: %d"
+kvm_set_intr(int irq, int level) "kvm set interrupt, irq num: %d, level: %d"
Re: [PATCH v4 0/9] Add loongarch kvm accel support
在 2024/1/10 下午5:42, Philippe Mathieu-Daudé 写道: Hi Song, On 10/1/24 03:46, gaosong wrote: 在 2024/1/5 下午3:57, Tianrui Zhao 写道: This series add loongarch kvm support, mainly implement some interfaces used by kvm, such as kvm_arch_get/set_regs, kvm_arch_handle_exit, kvm_loongarch_set_interrupt, etc. Tianrui Zhao (9): linux-headers: Synchronize linux headers from linux v6.7.0-rc8 target/loongarch: Define some kvm_arch interfaces target/loongarch: Supplement vcpu env initial when vcpu reset target/loongarch: Implement kvm get/set registers target/loongarch: Implement kvm_arch_init function target/loongarch: Implement kvm_arch_init_vcpu target/loongarch: Implement kvm_arch_handle_exit target/loongarch: Implement set vcpu intr for kvm target/loongarch: Add loongarch kvm into meson build Applied to loongarch-next. Sorry it took me some time to test this on a loongarch64 host. I made minor changes to patch #8, please consider the alternative: https://lore.kernel.org/qemu-devel/20240110094152.52138-1-phi...@linaro.org/ and https://lore.kernel.org/qemu-devel/20240110094152.52138-2-phi...@linaro.org/ Thank you , I wll apply them to loongarch-next. if no new problem with this series, I think we can merge it on this week. Thanks. Song Gao
Re: [PATCH v2 0/4] hw/loongarch/virt: Set iocsr address space per-board rather percpu
在 2023/12/15 下午6:03, Bibo Mao 写道: On LoongArch system, there is iocsr address space simliar system io address space on x86. And each cpu has its separate iocsr address space now, with this patch, iocsr address space is changed with per-board, and MemTxAttrs.requester_id is used to differentiate cpu cores. --- Changes in v2: 1. Add num-cpu property for extioi interrupt controller 2. Add post_load support for extioi vmstate to calculate sw_ipmap/sw_coremap info --- Bibo Mao (4): hw/intc/loongarch_ipi: Use MemTxAttrs interface for ipi ops hw/loongarch/virt: Set iocsr address space per-board rather than percpu hw/intc/loongarch_extioi: Add dynamic cpu number support hw/intc/loongarch_extioi: Add vmstate post_load support hw/intc/loongarch_extioi.c | 230 ++--- hw/intc/loongarch_ipi.c| 191 +++- hw/loongarch/virt.c| 94 include/hw/intc/loongarch_extioi.h | 12 +- include/hw/intc/loongarch_ipi.h| 3 +- include/hw/loongarch/virt.h| 3 + target/loongarch/cpu.c | 48 -- target/loongarch/cpu.h | 4 +- target/loongarch/iocsr_helper.c| 16 +- 9 files changed, 358 insertions(+), 243 deletions(-) Applied to loongarch-next. Thanks. Song Gao
Re: [PATCH v4 0/9] Add loongarch kvm accel support
在 2024/1/5 下午3:57, Tianrui Zhao 写道: The linux headers in this patch synchronized from linux kernel v6.7.0-rc8, and the loongarch kvm part of this patch series based on the header files. And the linux kernel has added the loongarch kvm support in master branch. This series add loongarch kvm support, mainly implement some interfaces used by kvm, such as kvm_arch_get/set_regs, kvm_arch_handle_exit, kvm_loongarch_set_interrupt, etc. Currently, we are able to boot LoongArch KVM Linux Guests. In loongarch VM, mmio devices and iocsr devices are emulated in user space such as APIC, IPI, pci devices, etc, other hardwares such as MMU, timer and csr are emulated in kernel. The running environment of LoongArch virt machine: 1. Get the Linux KVM environment of LoongArch in Linux mainline. make ARCH=loongarch CROSS_COMPILE=loongarch64-unknown-linux-gnu- loongson3_defconfig make ARCH=loongarch CROSS_COMPILE=loongarch64-unknown-linux-gnu- 2. Get the qemu source: https://github.com/loongson/qemu git checkout kvm-loongarch ./configure --target-list="loongarch64-softmmu" --enable-kvm make 3. Get uefi bios of LoongArch virt machine: Link: https://github.com/tianocore/edk2-platforms/tree/master/Platform/Loongson/LoongArchQemuPkg#readme 4. Also you can access the binary files we have already built: https://github.com/yangxiaojuan-loongson/qemu-binary The command to boot loongarch virt machine: $ qemu-system-loongarch64 -machine virt -m 4G -cpu la464 \ -smp 1 -bios QEMU_EFI.fd -kernel vmlinuz.efi -initrd ramdisk \ -serial stdio -monitor telnet:localhost:4495,server,nowait \ -append "root=/dev/ram rdinit=/sbin/init console=ttyS0,115200" \ --nographic Changes for v4: 1. Synchronize linux headers from linux v6.7.0-rc8. 2. Move kvm.c and kvm_loongarch.h into target/loongarch/kvm/ directory. 3. Add "#ifndef CONFIG_USER_ONLY" before loongarch_cpu_do_interrupt to fix compiling issue. 4. Remove "#ifdef CONFIG_TCG" before "#include "exec/cpu_ldst.h"" in fpu_helper.c, As it has been changed in other patches. Changes for v3: 1. Synchronize linux headers from linux v6.7.0-rc7. 2. Fix compiling error when config enable-kvm and disable-tcg at one time. Changes for v2: 1. Synchronize linux headers from linux v6.7.0-rc6. 2. Remove the stub function: kvm_loongarch_set_interrupt, as kvm_enabled 3. Move the kvm function such as kvm_arch_reset_vcpu from cpu.h to loongarch_kvm.h, and supplement "#include " in loongarch_kvm.h. Changes for v1: 1. Synchronous KVM headers about LoongArch KVM form linux kernel, as the LoongArch KVM patch series have been accepted by linux kernel. 2. Remove the KVM_GET/SET_ONE_UREG64 macro in target/loongarch, and use the common interface kvm_get/set_one_reg to replace it. 3. Resolve the compiling errors when LoongArch is built by other archs. Tianrui Zhao (9): linux-headers: Synchronize linux headers from linux v6.7.0-rc8 target/loongarch: Define some kvm_arch interfaces target/loongarch: Supplement vcpu env initial when vcpu reset target/loongarch: Implement kvm get/set registers target/loongarch: Implement kvm_arch_init function target/loongarch: Implement kvm_arch_init_vcpu target/loongarch: Implement kvm_arch_handle_exit target/loongarch: Implement set vcpu intr for kvm target/loongarch: Add loongarch kvm into meson build include/standard-headers/drm/drm_fourcc.h | 2 + include/standard-headers/linux/fuse.h | 10 +- include/standard-headers/linux/pci_regs.h | 24 +- include/standard-headers/linux/vhost_types.h | 7 + .../standard-headers/linux/virtio_config.h| 5 + include/standard-headers/linux/virtio_pci.h | 11 + linux-headers/asm-arm64/kvm.h | 32 + linux-headers/asm-generic/unistd.h| 14 +- linux-headers/asm-loongarch/bitsperlong.h | 1 + linux-headers/asm-loongarch/kvm.h | 108 +++ linux-headers/asm-loongarch/mman.h| 1 + linux-headers/asm-loongarch/unistd.h | 5 + linux-headers/asm-mips/unistd_n32.h | 4 + linux-headers/asm-mips/unistd_n64.h | 4 + linux-headers/asm-mips/unistd_o32.h | 4 + linux-headers/asm-powerpc/unistd_32.h | 4 + linux-headers/asm-powerpc/unistd_64.h | 4 + linux-headers/asm-riscv/kvm.h | 12 + linux-headers/asm-s390/unistd_32.h| 4 + linux-headers/asm-s390/unistd_64.h| 4 + linux-headers/asm-x86/unistd_32.h | 4 + linux-headers/asm-x86/unistd_64.h | 3 + linux-headers/asm-x86/unistd_x32.h| 3 + linux-headers/linux/iommufd.h | 180 +++- linux-headers/linux/kvm.h | 11 + linux-headers/linux/psp-sev.h | 1 + linux-headers/linux/stddef.h | 9 +- linux-headers/linux/userfaultfd.h | 9 +- linux-headers/linux/vfio.h
Re: [PATCH v4 9/9] target/loongarch: Add loongarch kvm into meson build
在 2024/1/5 下午3:58, Tianrui Zhao 写道:
Add kvm.c into meson.build to compile it when kvm
is configed. Meanwhile in meson.build, we set the
kvm_targets to loongarch64-softmmu when the cpu is
loongarch. And fix the compiling error when config
is enable-kvm,disable-tcg.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Richard Henderson
---
meson.build | 2 ++
target/loongarch/kvm/meson.build | 1 +
target/loongarch/meson.build | 1 +
3 files changed, 4 insertions(+)
create mode 100644 target/loongarch/kvm/meson.build
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/meson.build b/meson.build
index 445f2b7c2b..0c62b4156d 100644
--- a/meson.build
+++ b/meson.build
@@ -114,6 +114,8 @@ elif cpu in ['riscv32']
kvm_targets = ['riscv32-softmmu']
elif cpu in ['riscv64']
kvm_targets = ['riscv64-softmmu']
+elif cpu in ['loongarch64']Reviewed-by: Song Gao
+ kvm_targets = ['loongarch64-softmmu']
else
kvm_targets = []
endif
diff --git a/target/loongarch/kvm/meson.build b/target/loongarch/kvm/meson.build
new file mode 100644
index 00..2266de6ca9
--- /dev/null
+++ b/target/loongarch/kvm/meson.build
@@ -0,0 +1 @@
+loongarch_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index 18e8191e2b..7f86caf373 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -31,3 +31,4 @@ loongarch_ss.add_all(when: 'CONFIG_TCG', if_true:
[loongarch_tcg_ss])
target_arch += {'loongarch': loongarch_ss}
target_system_arch += {'loongarch': loongarch_system_ss}
+subdir('kvm')
Re: [PATCH v2 4/4] hw/intc/loongarch_extioi: Add vmstate post_load support
在 2023/12/15 下午6:03, Bibo Mao 写道:
There are elements sw_ipmap and sw_coremap, which is usd to speed
up irq injection flow. They are saved and restored in vmstate during
migration, indeed they can calculated from hw registers. Here
post_load is added for get sw_ipmap and sw_coremap from extioi hw
state.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c | 120 +++--
1 file changed, 76 insertions(+), 44 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index d9d5066c3f..e0fd57f962 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -130,12 +130,66 @@ static inline void extioi_enable_irq(LoongArchExtIOI *s,
int index,\
}
}
+static inline void extioi_update_sw_coremap(LoongArchExtIOI *s, int irq,
+uint64_t val, bool notify)
+{
+int i, cpu;
+
+/*
+ * loongarch only support little endian,
+ * so we paresd the value with little endian.
+ */
+val = cpu_to_le64(val);
+
+for (i = 0; i < 4; i++) {
+cpu = val & 0xff;
+cpu = ctz32(cpu);
+cpu = (cpu >= 4) ? 0 : cpu;
+val = val >> 8;
+
+if (s->sw_coremap[irq + i] == cpu) {
+continue;
+}
+
+if (notify && test_bit(irq, (unsigned long *)s->isr)) {
+/*
+ * lower irq at old cpu and raise irq at new cpu
+ */
+extioi_update_irq(s, irq + i, 0);
+s->sw_coremap[irq + i] = cpu;
+extioi_update_irq(s, irq + i, 1);
+} else {
+s->sw_coremap[irq + i] = cpu;
+}
+}
+}
+
+static inline void extioi_update_sw_ipmap(LoongArchExtIOI *s, int index,
+ uint64_t val)
+{
+int i;
+uint8_t ipnum;
+
+/*
+ * loongarch only support little endian,
+ * so we paresd the value with little endian.
+ */
+val = cpu_to_le64(val);
+for (i = 0; i < 4; i++) {
+ipnum = val & 0xff;
+ipnum = ctz32(ipnum);
+ipnum = (ipnum >= 4) ? 0 : ipnum;
+s->sw_ipmap[index * 4 + i] = ipnum;
+val = val >> 8;
+}
+}
+
static MemTxResult extioi_writew(void *opaque, hwaddr addr,
uint64_t val, unsigned size,
MemTxAttrs attrs)
{
LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
-int i, cpu, index, old_data, irq;
+int cpu, index, old_data, irq;
uint32_t offset;
trace_loongarch_extioi_writew(addr, val);
@@ -153,20 +207,7 @@ static MemTxResult extioi_writew(void *opaque, hwaddr addr,
*/
index = (offset - EXTIOI_IPMAP_START) >> 2;
s->ipmap[index] = val;
-/*
- * loongarch only support little endian,
- * so we paresd the value with little endian.
- */
-val = cpu_to_le64(val);
-for (i = 0; i < 4; i++) {
-uint8_t ipnum;
-ipnum = val & 0xff;
-ipnum = ctz32(ipnum);
-ipnum = (ipnum >= 4) ? 0 : ipnum;
-s->sw_ipmap[index * 4 + i] = ipnum;
-val = val >> 8;
-}
-
+extioi_update_sw_ipmap(s, index, val);
break;
case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
index = (offset - EXTIOI_ENABLE_START) >> 2;
@@ -205,33 +246,8 @@ static MemTxResult extioi_writew(void *opaque, hwaddr addr,
irq = offset - EXTIOI_COREMAP_START;
index = irq / 4;
s->coremap[index] = val;
-/*
- * loongarch only support little endian,
- * so we paresd the value with little endian.
- */
-val = cpu_to_le64(val);
-
-for (i = 0; i < 4; i++) {
-cpu = val & 0xff;
-cpu = ctz32(cpu);
-cpu = (cpu >= 4) ? 0 : cpu;
-val = val >> 8;
-
-if (s->sw_coremap[irq + i] == cpu) {
-continue;
-}
-
-if (test_bit(irq, (unsigned long *)s->isr)) {
-/*
- * lower irq at old cpu and raise irq at new cpu
- */
-extioi_update_irq(s, irq + i, 0);
-s->sw_coremap[irq + i] = cpu;
-extioi_update_irq(s, irq + i, 1);
-} else {
-s->sw_coremap[irq + i] = cpu;
-}
-}
+
+extioi_update_sw_coremap(s, irq, val, true);
break;
default:
break;
@@ -288,6 +304,23 @@ static void loongarch_extioi_finalize(Object *obj)
g_free(s->cpu);
}
+static int vmstate_extioi_post_load(void *opaque, int version_id)
+{
+LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+int i, start_irq;
+
+for (i = 0; i < (EXTIOI_IRQS / 4); i++) {
+start_irq = i * 4;
+extioi_update_sw_coremap(s, start_irq, s->coremap[i], false);
+}
+
+for (i = 0; i < (EXTIOI_IRQS_IPMAP_SIZE / 4); i++) {
+
Re: [PATCH v2 3/4] hw/intc/loongarch_extioi: Add dynamic cpu number support
在 2023/12/15 下午6:03, Bibo Mao 写道:
On LoongArch physical machine, one extioi interrupt controller only
supports 4 cpus. With processor more than 4 cpus, there are multiple
extioi interrupt controllers; if interrupts need to be routed to
other cpus, they are forwarded from extioi node0 to other extioi nodes.
On virt machine model, there is simple extioi interrupt device model.
All cpus can access register of extioi interrupt controller, however
interrupt can only be route to 4 vcpu for compatible with old kernel.
This patch adds dynamic cpu number support about extioi interrupt.
With old kernel legacy extioi model is used, however kernel can detect
and choose new route method in future, so that interrupt can be routed to
all vcpus.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c | 107 +++--
hw/loongarch/virt.c| 3 +-
include/hw/intc/loongarch_extioi.h | 11 ++-
3 files changed, 81 insertions(+), 40 deletions(-)
Reviewed-by: Song Gao
Thanks. Song Gao
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index 77b4776958..d9d5066c3f 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -8,6 +8,7 @@
#include "qemu/osdep.h"
#include "qemu/module.h"
#include "qemu/log.h"
+#include "qapi/error.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "hw/loongarch/virt.h"
@@ -32,23 +33,23 @@ static void extioi_update_irq(LoongArchExtIOI *s, int irq,
int level)
if (((s->enable[irq_index]) & irq_mask) == 0) {
return;
}
-s->coreisr[cpu][irq_index] |= irq_mask;
-found = find_first_bit(s->sw_isr[cpu][ipnum], EXTIOI_IRQS);
-set_bit(irq, s->sw_isr[cpu][ipnum]);
+s->cpu[cpu].coreisr[irq_index] |= irq_mask;
+found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS);
+set_bit(irq, s->cpu[cpu].sw_isr[ipnum]);
if (found < EXTIOI_IRQS) {
/* other irq is handling, need not update parent irq level */
return;
}
} else {
-s->coreisr[cpu][irq_index] &= ~irq_mask;
-clear_bit(irq, s->sw_isr[cpu][ipnum]);
-found = find_first_bit(s->sw_isr[cpu][ipnum], EXTIOI_IRQS);
+s->cpu[cpu].coreisr[irq_index] &= ~irq_mask;
+clear_bit(irq, s->cpu[cpu].sw_isr[ipnum]);
+found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS);
if (found < EXTIOI_IRQS) {
/* other irq is handling, need not update parent irq level */
return;
}
}
-qemu_set_irq(s->parent_irq[cpu][ipnum], level);
+qemu_set_irq(s->cpu[cpu].parent_irq[ipnum], level);
}
static void extioi_setirq(void *opaque, int irq, int level)
@@ -96,7 +97,7 @@ static MemTxResult extioi_readw(void *opaque, hwaddr addr,
uint64_t *data,
index = (offset - EXTIOI_COREISR_START) >> 2;
/* using attrs to get current cpu index */
cpu = attrs.requester_id;
-*data = s->coreisr[cpu][index];
+*data = s->cpu[cpu].coreisr[index];
break;
case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
index = (offset - EXTIOI_COREMAP_START) >> 2;
@@ -189,8 +190,8 @@ static MemTxResult extioi_writew(void *opaque, hwaddr addr,
index = (offset - EXTIOI_COREISR_START) >> 2;
/* using attrs to get current cpu index */
cpu = attrs.requester_id;
-old_data = s->coreisr[cpu][index];
-s->coreisr[cpu][index] = old_data & ~val;
+old_data = s->cpu[cpu].coreisr[index];
+s->cpu[cpu].coreisr[index] = old_data & ~val;
/* write 1 to clear interrupt */
old_data &= val;
irq = ctz32(old_data);
@@ -248,14 +249,61 @@ static const MemoryRegionOps extioi_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static const VMStateDescription vmstate_loongarch_extioi = {
-.name = TYPE_LOONGARCH_EXTIOI,
+static void loongarch_extioi_realize(DeviceState *dev, Error **errp)
+{
+LoongArchExtIOI *s = LOONGARCH_EXTIOI(dev);
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+int i, pin;
+
+if (s->num_cpu == 0) {
+error_setg(errp, "num-cpu must be at least 1");
+return;
+}
+
+for (i = 0; i < EXTIOI_IRQS; i++) {
+sysbus_init_irq(sbd, >irq[i]);
+}
+
+qdev_init_gpio_in(dev, extioi_setirq, EXTIOI_IRQS);
+memory_region_init_io(>extioi_system_mem, OBJECT(s), _ops,
+ s, "extioi_system_mem", 0x900);
+sysbus_init_mmio(sbd, >extioi_system_mem);
+s->cpu = g_new0(ExtIOICore, s->num_cpu);
+if (s->cpu == NULL) {
+error_setg(errp, "Memory allocation for ExtIOICore faile");
+return;
+}
+
+for (i = 0; i < s->num_cpu; i++) {
+for (pin = 0; pin < LS3A_INTC_IP; pin++) {
+qdev_init_gpio_out(dev, >cpu[i].parent_irq[pin], 1);
+}
+}
+}
+
+static void loongarch_extioi_finalize(Object *obj)
+{
+
Re: [PATCH v2 2/4] hw/loongarch/virt: Set iocsr address space per-board rather than percpu
在 2023/12/15 下午6:03, Bibo Mao 写道:
LoongArch system has iocsr address space, most iocsr registers are
per-board, however some iocsr register spaces banked for percpu such
as ipi mailbox and extioi interrupt status. For banked iocsr space,
each cpu has the same iocsr space, but separate data.
This patch changes iocsr address space per-board rather percpu,
for iocsr registers specified for cpu, MemTxAttrs.requester_id
can be parsed for the cpu. With this patches, the total address space
on board will be simple, only iocsr address space and system memory,
rather than the number of cpu and system memory.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c | 3 -
hw/intc/loongarch_ipi.c| 61 +++-
hw/loongarch/virt.c| 91 ++
include/hw/intc/loongarch_extioi.h | 1 -
include/hw/intc/loongarch_ipi.h| 3 +-
include/hw/loongarch/virt.h| 3 +
target/loongarch/cpu.c | 48
target/loongarch/cpu.h | 4 +-
target/loongarch/iocsr_helper.c| 16 +++---
9 files changed, 127 insertions(+), 103 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index 24fb3af8cc..77b4776958 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -282,9 +282,6 @@ static void loongarch_extioi_instance_init(Object *obj)
qdev_init_gpio_in(DEVICE(obj), extioi_setirq, EXTIOI_IRQS);
for (cpu = 0; cpu < EXTIOI_CPUS; cpu++) {
-memory_region_init_io(>extioi_iocsr_mem[cpu], OBJECT(s),
_ops,
- s, "extioi_iocsr", 0x900);
-sysbus_init_mmio(dev, >extioi_iocsr_mem[cpu]);
for (pin = 0; pin < LS3A_INTC_IP; pin++) {
qdev_init_gpio_out(DEVICE(obj), >parent_irq[cpu][pin], 1);
}
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index 1d3449e77d..bca01c88f6 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -9,6 +9,7 @@
#include "hw/sysbus.h"
#include "hw/intc/loongarch_ipi.h"
#include "hw/irq.h"
+#include "hw/qdev-properties.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "exec/address-spaces.h"
@@ -26,7 +27,7 @@ static MemTxResult loongarch_ipi_readl(void *opaque, hwaddr
addr,
uint64_t ret = 0;
int index = 0;
-s = >ipi_core;
+s = >cpu[attrs.requester_id];
addr &= 0xff;
switch (addr) {
case CORE_STATUS_OFF:
@@ -65,7 +66,7 @@ static void send_ipi_data(CPULoongArchState *env, uint64_t
val, hwaddr addr,
* if the mask is 0, we need not to do anything.
*/
if ((val >> 27) & 0xf) {
-data = address_space_ldl(>address_space_iocsr, addr,
+data = address_space_ldl(env->address_space_iocsr, addr,
attrs, NULL);
for (i = 0; i < 4; i++) {
/* get mask for byte writing */
@@ -77,7 +78,7 @@ static void send_ipi_data(CPULoongArchState *env, uint64_t
val, hwaddr addr,
data &= mask;
data |= (val >> 32) & ~mask;
-address_space_stl(>address_space_iocsr, addr,
+address_space_stl(env->address_space_iocsr, addr,
data, attrs, NULL);
}
@@ -172,7 +173,7 @@ static MemTxResult loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
uint8_t vector;
CPUState *cs;
-s = >ipi_core;
+s = >cpu[attrs.requester_id];
addr &= 0xff;loongarch_ipi_finalize
trace_loongarch_ipi_write(size, (uint64_t)addr, val);
switch (addr) {
@@ -214,7 +215,6 @@ static MemTxResult loongarch_ipi_writel(void *opaque,
hwaddr addr, uint64_t val,
/* override requester_id */
attrs.requester_id = cs->cpu_index;
-ipi = LOONGARCH_IPI(LOONGARCH_CPU(cs)->env.ipistate);
loongarch_ipi_writel(ipi, CORE_SET_OFF, BIT(vector), 4, attrs);
break;
default:
@@ -265,12 +265,18 @@ static const MemoryRegionOps loongarch_ipi64_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void loongarch_ipi_init(Object *obj)
+static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
{
-LoongArchIPI *s = LOONGARCH_IPI(obj);
-SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+LoongArchIPI *s = LOONGARCH_IPI(dev);
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+int i;
+
+if (s->num_cpu == 0) {
+error_setg(errp, "num-cpu must be at least 1");
+return;
+}
-memory_region_init_io(>ipi_iocsr_mem, obj, _ipi_ops,
+memory_region_init_io(>ipi_iocsr_mem, OBJECT(dev), _ipi_ops,
s, "loongarch_ipi_iocsr", 0x48);
/* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */
@@ -278,10 +284,20 @@ static void loongarch_ipi_init(Object *obj)
sysbus_init_mmio(sbd, >ipi_iocsr_mem);
-memory_region_init_io(>ipi64_iocsr_mem, obj, _ipi64_ops,
+
Re: [PATCH v2 1/4] hw/intc/loongarch_ipi: Use MemTxAttrs interface for ipi ops
在 2023/12/15 下午6:03, Bibo Mao 写道:
There are two interface pairs for MemoryRegionOps, read/write and
read_with_attrs/write_with_attrs. The later is better for ipi device
emulation since initial cpu can be parsed from attrs.requester_id.
And requester_id can be overrided for IOCSR_IPI_SEND and mail_send
function when it is to forward message to another vcpu.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 136 +++-
1 file changed, 77 insertions(+), 59 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index 67858b521c..1d3449e77d 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -17,14 +17,16 @@
#include "target/loongarch/internals.h"
#include "trace.h"
-static void loongarch_ipi_writel(void *, hwaddr, uint64_t, unsigned);
-
-static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size)
+static MemTxResult loongarch_ipi_readl(void *opaque, hwaddr addr,
+ uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
{
-IPICore *s = opaque;
+IPICore *s;
+LoongArchIPI *ipi = opaque;
uint64_t ret = 0;
int index = 0;
+s = >ipi_core;
addr &= 0xff;
switch (addr) {
case CORE_STATUS_OFF:
@@ -49,10 +51,12 @@ static uint64_t loongarch_ipi_readl(void *opaque, hwaddr
addr, unsigned size)
}
trace_loongarch_ipi_read(size, (uint64_t)addr, ret);
-return ret;
+*data = ret;
+return MEMTX_OK;
}
-static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr)
+static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr,
+ MemTxAttrs attrs)
{
int i, mask = 0, data = 0;
@@ -62,7 +66,7 @@ static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr)
*/
if ((val >> 27) & 0xf) {
data = address_space_ldl(>address_space_iocsr, addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
+ attrs, NULL);
for (i = 0; i < 4; i++) {
/* get mask for byte writing */
if (val & (0x1 << (27 + i))) {
@@ -74,7 +78,7 @@ static void send_ipi_data(CPULoongArchState *env, uint64_t
val, hwaddr addr)
data &= mask;
data |= (val >> 32) & ~mask;
address_space_stl(>address_space_iocsr, addr,
- data, MEMTXATTRS_UNSPECIFIED, NULL);
+ data, attrs, NULL);
}
static int archid_cmp(const void *a, const void *b)
@@ -103,80 +107,72 @@ static CPUState *ipi_getcpu(int arch_id)
CPUArchId *archid;
archid = find_cpu_by_archid(machine, arch_id);
-return CPU(archid->cpu);
-}
-
-static void ipi_send(uint64_t val)
-{
-uint32_t cpuid;
-uint8_t vector;
-CPUState *cs;
-LoongArchCPU *cpu;
-LoongArchIPI *s;
-
-cpuid = extract32(val, 16, 10);
-if (cpuid >= LOONGARCH_MAX_CPUS) {
-trace_loongarch_ipi_unsupported_cpuid("IOCSR_IPI_SEND", cpuid);
-return;
+if (archid) {
+return CPU(archid->cpu);
}
-/* IPI status vector */
-vector = extract8(val, 0, 5);
-
-cs = ipi_getcpu(cpuid);
-cpu = LOONGARCH_CPU(cs);
-s = LOONGARCH_IPI(cpu->env.ipistate);
-loongarch_ipi_writel(>ipi_core, CORE_SET_OFF, BIT(vector), 4);
+return NULL;
}
-static void mail_send(uint64_t val)
+static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
hwaddr addr;
-CPULoongArchState *env;
CPUState *cs;
-LoongArchCPU *cpu;
cpuid = extract32(val, 16, 10);
if (cpuid >= LOONGARCH_MAX_CPUS) {
trace_loongarch_ipi_unsupported_cpuid("IOCSR_MAIL_SEND", cpuid);
-return;
+return MEMTX_DECODE_ERROR;
}
-addr = 0x1020 + (val & 0x1c);
cs = ipi_getcpu(cpuid);
-cpu = LOONGARCH_CPU(cs);
-env = >env;
-send_ipi_data(env, val, addr);
+if (cs == NULL) {
+return MEMTX_DECODE_ERROR;
+}
+
+/* override requester_id */
+addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
+attrs.requester_id = cs->cpu_index;
+send_ipi_data(_CPU(cs)->env, val, addr, attrs);
+return MEMTX_OK;
}
-static void any_send(uint64_t val)
+static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
hwaddr addr;
-CPULoongArchState *env;
CPUState *cs;
-LoongArchCPU *cpu;
cpuid = extract32(val, 16, 10);
if (cpuid >= LOONGARCH_MAX_CPUS) {
trace_loongarch_ipi_unsupported_cpuid("IOCSR_ANY_SEND", cpuid);
-return;
+return MEMTX_DECODE_ERROR;
}
-addr = val & 0x;
cs = ipi_getcpu(cpuid);
-cpu = LOONGARCH_CPU(cs);
-env = >env;
-send_ipi_data(env, val, addr);
+if (cs == NULL) {
+return MEMTX_DECODE_ERROR;
+}
+
+
Re: [PATCH v3 11/46] hw/loongarch: use pci_init_nic_devices()
在 2024/1/9 上午4:26, David Woodhouse 写道:
From: David Woodhouse
Signed-off-by: David Woodhouse
---
hw/loongarch/virt.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 4b7dc67a2d..c48804ac38 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -504,9 +504,7 @@ static void loongarch_devices_init(DeviceState *pch_pic,
LoongArchMachineState *
fdt_add_uart_node(lams);
/* Network init */
-for (i = 0; i < nb_nics; i++) {
-pci_nic_init_nofail(_table[i], pci_bus, mc->default_nic, NULL);
-}
+pci_init_nic_devices(pci_bus, mc->default_nic);
/*
* There are some invalid guest memory access.
Re: [PULL 0/2] loongarch-to-apply queue
在 2024/1/5 下午9:34, Peter Maydell 写道: On Fri, 5 Jan 2024 at 01:30, Song Gao wrote: The following changes since commit d328fef93ae757a0dd65ed786a4086e27952eef3: Merge tag 'pull-20231230' of https://gitlab.com/rth7680/qemu into staging (2024-01-04 10:23:34 +) are available in the Git repository at: https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240105 for you to fetch changes up to 0cd8b379081fa71c23836052feb65da4685f8ec7: target/loongarch: move translate modules to tcg/ (2024-01-05 09:31:05 +0800) pull-loongarch-20240105 Song Gao (2): target/loongarch/meson: move gdbstub.c to loongarch.ss target/loongarch: move translate modules to tcg/ Hi; this fails to build, with ../target/loongarch/tcg/meson.build:1:3: ERROR: Unknown variable "config_all". (eg https://gitlab.com/qemu-project/qemu/-/jobs/5868662017) I think your pullreq has unfortunately got a conflict with the meson cleanup patches that I just applied from Paolo. Could you have a look at this and respin the pullreq, please? Sure, I will. Thanks. Song Gao.
Re: [PATCH v3 7/9] target/loongarch: Implement kvm_arch_handle_exit
在 2023/12/28 下午4:40, Tianrui Zhao 写道:
Implement kvm_arch_handle_exit for loongarch. In this
function, the KVM_EXIT_LOONGARCH_IOCSR is handled,
we read or write the iocsr address space by the addr,
length and is_write argument in kvm_run.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Richard Henderson
---
target/loongarch/kvm.c| 24 +++-
target/loongarch/trace-events | 1 +
2 files changed, 24 insertions(+), 1 deletion(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/target/loongarch/kvm.c b/target/loongarch/kvm.c
index 85e7aeb083..d2dab3fef4 100644
--- a/target/loongarch/kvm.c
+++ b/target/loongarch/kvm.c
@@ -723,7 +723,29 @@ bool kvm_arch_cpu_check_are_resettable(void)
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
{
-return 0;
+int ret = 0;
+LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+CPULoongArchState *env = >env;
+MemTxAttrs attrs = {};
+
+attrs.requester_id = env_cpu(env)->cpu_index;
+
+trace_kvm_arch_handle_exit(run->exit_reason);
+switch (run->exit_reason) {
+case KVM_EXIT_LOONGARCH_IOCSR:
+address_space_rw(>address_space_iocsr,
+ run->iocsr_io.phys_addr,
+ attrs,
+ run->iocsr_io.data,
+ run->iocsr_io.len,
+ run->iocsr_io.is_write);
+break;
+default:
+ret = -1;
+warn_report("KVM: unknown exit reason %d", run->exit_reason);
+break;
+}
+return ret;
}
void kvm_arch_accel_class_init(ObjectClass *oc)
diff --git a/target/loongarch/trace-events b/target/loongarch/trace-events
index 937c3c7c0c..021839880e 100644
--- a/target/loongarch/trace-events
+++ b/target/loongarch/trace-events
@@ -11,3 +11,4 @@ kvm_failed_get_counter(const char *msg) "Failed to get counter
from KVM: %s"
kvm_failed_put_counter(const char *msg) "Failed to put counter into KVM: %s"
kvm_failed_get_cpucfg(const char *msg) "Failed to get cpucfg from KVM: %s"
kvm_failed_put_cpucfg(const char *msg) "Failed to put cpucfg into KVM: %s"
+kvm_arch_handle_exit(int num) "kvm arch handle exit, the reason number: %d"
Re: [PATCH v3 4/9] target/loongarch: Implement kvm get/set registers
在 2023/12/28 下午4:40, Tianrui Zhao 写道:
+static int kvm_loongarch_get_regs_fp(CPUState *cs)
+{
+int ret, i;
+struct kvm_fpu fpu;
+
+LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+CPULoongArchState *env = >env;
+
+ret = kvm_vcpu_ioctl(cs, KVM_GET_FPU, );
+if (ret < 0) {
+trace_kvm_failed_get_fpu(strerror(errno));
+return ret;
+}
+
+env->fcsr0 = fpu.fcsr;
+for (i = 0; i < 32; i++) {
+env->fpr[i].vreg.UD[0] = fpu.fpr[i].val64[0];
+}
+for (i = 0; i < 8; i++) {
+env->cf[i] = fpu.fcc & 0xFF;
+fpu.fcc = fpu.fcc >> 8;
+}
+
Use write_fcc(env, fpu.fcc)
+return ret;
+}
+
+static int kvm_loongarch_put_regs_fp(CPUState *cs)
+{
+int ret, i;
+struct kvm_fpu fpu;
+
+LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+CPULoongArchState *env = >env;
+
+fpu.fcsr = env->fcsr0;
+fpu.fcc = 0;
+for (i = 0; i < 32; i++) {
+fpu.fpr[i].val64[0] = env->fpr[i].vreg.UD[0];
+}
+
+for (i = 0; i < 8; i++) {
+fpu.fcc |= env->cf[i] << (8 * i);
+}
+
Use fpu.fcc = read_fcc(env)
+ret = kvm_vcpu_ioctl(cs, KVM_SET_FPU, );
+if (ret < 0) {
+trace_kvm_failed_put_fpu(strerror(errno));
+}
+
+return ret;
+}
Re: [PATCH v3 6/9] target/loongarch: Implement kvm_arch_init_vcpu
在 2023/12/28 下午4:40, Tianrui Zhao 写道:
Implement kvm_arch_init_vcpu interface for loongarch,
in this function, we register VM change state handler.
And when VM state changes to running, the counter value
should be put into kvm to keep consistent with kvm,
and when state change to stop, counter value should be
refreshed from kvm.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
---
target/loongarch/cpu.h| 2 ++
target/loongarch/kvm.c| 23 +++
target/loongarch/trace-events | 2 ++
3 files changed, 27 insertions(+)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index f4a89bd626..8ebd6fa1a7 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -381,6 +381,8 @@ struct ArchCPU {
/* 'compatible' string for this CPU for Linux device trees */
const char *dtb_compatible;
+/* used by KVM_REG_LOONGARCH_COUNTER ioctl to access guest time counters */
+uint64_t kvm_state_counter;
};
/**
diff --git a/target/loongarch/kvm.c b/target/loongarch/kvm.c
index 29944b9ef8..85e7aeb083 100644
--- a/target/loongarch/kvm.c
+++ b/target/loongarch/kvm.c
@@ -617,8 +617,31 @@ int kvm_arch_put_registers(CPUState *cs, int level)
return ret;
}
+static void kvm_loongarch_vm_stage_change(void *opaque, bool running,
+ RunState state)
+{
+int ret;
+CPUState *cs = opaque;
+LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+
+if (running) {
+ret = kvm_set_one_reg(cs, KVM_REG_LOONGARCH_COUNTER,
+ >kvm_state_counter);
+if (ret < 0) {
+trace_kvm_failed_put_counter(strerror(errno));
+}
+} else {
+ret = kvm_get_one_reg(cs, KVM_REG_LOONGARCH_COUNTER,
+ >kvm_state_counter);
+if (ret < 0) {
+trace_kvm_failed_get_counter(strerror(errno));
+}
+}
+}
+
int kvm_arch_init_vcpu(CPUState *cs)
{
+qemu_add_vm_change_state_handler(kvm_loongarch_vm_stage_change, cs);
return 0;
}
diff --git a/target/loongarch/trace-events b/target/loongarch/trace-events
index 6827ab566a..937c3c7c0c 100644
--- a/target/loongarch/trace-events
+++ b/target/loongarch/trace-events
@@ -7,5 +7,7 @@ kvm_failed_get_fpu(const char *msg) "Failed to get fpu from KVM:
%s"
kvm_failed_put_fpu(const char *msg) "Failed to put fpu into KVM: %s"
kvm_failed_get_mpstate(const char *msg) "Failed to get mp_state from KVM: %s"
kvm_failed_put_mpstate(const char *msg) "Failed to put mp_state into KVM: %s"
+kvm_failed_get_counter(const char *msg) "Failed to get counter from KVM: %s"
+kvm_failed_put_counter(const char *msg) "Failed to put counter into KVM: %s"
kvm_failed_get_cpucfg(const char *msg) "Failed to get cpucfg from KVM: %s"
kvm_failed_put_cpucfg(const char *msg) "Failed to put cpucfg into KVM: %s"
Re: [PATCH v3 5/9] target/loongarch: Implement kvm_arch_init function
在 2023/12/28 下午4:40, Tianrui Zhao 写道:
Implement the kvm_arch_init of loongarch, in the function, the
KVM_CAP_MP_STATE cap is checked by kvm ioctl.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Richard Henderson
---
target/loongarch/kvm.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/target/loongarch/kvm.c b/target/loongarch/kvm.c
index e7c9ef830c..29944b9ef8 100644
--- a/target/loongarch/kvm.c
+++ b/target/loongarch/kvm.c
@@ -665,6 +665,7 @@ int kvm_arch_get_default_type(MachineState *ms)
int kvm_arch_init(MachineState *ms, KVMState *s)
{
+cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
return 0;
}
Re: [PATCH v3 4/9] target/loongarch: Implement kvm get/set registers
在 2023/12/28 下午4:40, Tianrui Zhao 写道:
Implement kvm_arch_get/set_registers interfaces, many regs
can be get/set in the function, such as core regs, csr regs,
fpu regs, mp state, etc.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
---
meson.build | 1 +
target/loongarch/cpu.c| 3 +
target/loongarch/cpu.h| 1 +
target/loongarch/fpu_helper.c | 2 +
target/loongarch/internals.h | 5 +-
target/loongarch/kvm.c| 580 +-
target/loongarch/trace-events | 11 +
target/loongarch/trace.h | 1 +
8 files changed, 601 insertions(+), 3 deletions(-)
create mode 100644 target/loongarch/trace-events
create mode 100644 target/loongarch/trace.h
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/meson.build b/meson.build
index 6c77d9687d..445f2b7c2b 100644
--- a/meson.build
+++ b/meson.build
@@ -3358,6 +3358,7 @@ if have_system or have_user
'target/hppa',
'target/i386',
'target/i386/kvm',
+'target/loongarch',
'target/mips/tcg',
'target/nios2',
'target/ppc',
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 4432a0081d..83899c673f 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -555,6 +555,9 @@ static void loongarch_cpu_reset_hold(Object *obj)
#ifndef CONFIG_USER_ONLY
env->pc = 0x1c00;
memset(env->tlb, 0, sizeof(env->tlb));
+if (kvm_enabled()) {
+kvm_arch_reset_vcpu(env);
+}
#endif
restore_fp_status(env);
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index f6d5ef0852..f4a89bd626 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -360,6 +360,7 @@ typedef struct CPUArchState {
MemoryRegion iocsr_mem;
bool load_elf;
uint64_t elf_address;
+uint32_t mp_state;
/* Store ipistate to access from this struct */
DeviceState *ipistate;
#endif
diff --git a/target/loongarch/fpu_helper.c b/target/loongarch/fpu_helper.c
index f6753c5875..1b71ea46d3 100644
--- a/target/loongarch/fpu_helper.c
+++ b/target/loongarch/fpu_helper.c
@@ -9,7 +9,9 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
+#ifdef CONFIG_TCG
#include "exec/cpu_ldst.h"
+#endif
#include "fpu/softfloat.h"
#include "internals.h"
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index c492863cc5..0beb034748 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -31,8 +31,10 @@ void G_NORETURN do_raise_exception(CPULoongArchState *env,
const char *loongarch_exception_name(int32_t exception);
+#ifdef CONFIG_TCG
int ieee_ex_to_loongarch(int xcpt);
void restore_fp_status(CPULoongArchState *env);
+#endif
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_loongarch_cpu;
@@ -44,12 +46,13 @@ uint64_t
cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu);
uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu);
void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
uint64_t value);
-
+#ifdef CONFIG_TCG
bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+#endif
#endif /* !CONFIG_USER_ONLY */
uint64_t read_fcc(CPULoongArchState *env);
diff --git a/target/loongarch/kvm.c b/target/loongarch/kvm.c
index 0d67322fd9..e7c9ef830c 100644
--- a/target/loongarch/kvm.c
+++ b/target/loongarch/kvm.c
@@ -26,19 +26,595 @@
#include "sysemu/runstate.h"
#include "cpu-csr.h"
#include "kvm_loongarch.h"
+#include "trace.h"
static bool cap_has_mp_state;
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
};
+static int kvm_loongarch_get_regs_core(CPUState *cs)
+{
+int ret = 0;
+int i;
+struct kvm_regs regs;
+LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+CPULoongArchState *env = >env;
+
+/* Get the current register set as KVM seems it */
+ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, );
+if (ret < 0) {
+trace_kvm_failed_get_regs_core(strerror(errno));
+return ret;
+}
+/* gpr[0] value is always 0 */
+env->gpr[0] = 0;
+for (i = 1; i < 32; i++) {
+env->gpr[i] = regs.gpr[i];
+}
+
+env->pc = regs.pc;
+return ret;
+}
+
+static int kvm_loongarch_put_regs_core(CPUState *cs)
+{
+int ret = 0;
+int i;
+struct kvm_regs regs;
+LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+CPULoongArchState *env = >env;
+
+/* Set the registers based on QEMU's view of things */
+for (i = 0; i < 32; i++) {
+regs.gpr[i] = env->gpr[i];
+}
+
+regs.pc = env->pc;
+ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, );
+if (ret < 0) {
+
Re: [PATCH v3 2/9] target/loongarch: Define some kvm_arch interfaces
在 2023/12/28 下午4:40, Tianrui Zhao 写道:
Define some functions in target/loongarch/kvm.c, such as
kvm_arch_put_registers, kvm_arch_get_registers and
kvm_arch_handle_exit, etc. which are needed by kvm/kvm-all.c.
Now the most functions has no content and they will be
implemented in the next patches.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Richard Henderson
---
target/loongarch/kvm.c | 131 +
1 file changed, 131 insertions(+)
create mode 100644 target/loongarch/kvm.c
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/target/loongarch/kvm.c b/target/loongarch/kvm.c
new file mode 100644
index 00..0d67322fd9
--- /dev/null
+++ b/target/loongarch/kvm.c
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch KVM
+ *
+ * Copyright (c) 2023 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include
+#include
+
+#include "qemu/timer.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "sysemu/kvm_int.h"
+#include "hw/pci/pci.h"
+#include "exec/memattrs.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "qemu/log.h"
+#include "hw/loader.h"
+#include "migration/migration.h"
+#include "sysemu/runstate.h"
+#include "cpu-csr.h"
+#include "kvm_loongarch.h"
+
+static bool cap_has_mp_state;
+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+KVM_CAP_LAST_INFO
+};
+
+int kvm_arch_get_registers(CPUState *cs)
+{
+return 0;
+}
+int kvm_arch_put_registers(CPUState *cs, int level)
+{
+return 0;
+}
+
+int kvm_arch_init_vcpu(CPUState *cs)
+{
+return 0;
+}
+
+int kvm_arch_destroy_vcpu(CPUState *cs)
+{
+return 0;
+}
+
+unsigned long kvm_arch_vcpu_id(CPUState *cs)
+{
+return cs->cpu_index;
+}
+
+int kvm_arch_release_virq_post(int virq)
+{
+return 0;
+}
+
+int kvm_arch_msi_data_to_gsi(uint32_t data)
+{
+abort();
+}
+
+int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
+ uint64_t address, uint32_t data, PCIDevice *dev)
+{
+return 0;
+}
+
+int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
+int vector, PCIDevice *dev)
+{
+return 0;
+}
+
+void kvm_arch_init_irq_routing(KVMState *s)
+{
+}
+
+int kvm_arch_get_default_type(MachineState *ms)
+{
+return 0;
+}
+
+int kvm_arch_init(MachineState *ms, KVMState *s)
+{
+return 0;
+}
+
+int kvm_arch_irqchip_create(KVMState *s)
+{
+return 0;
+}
+
+void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
+{
+}
+
+MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
+{
+return MEMTXATTRS_UNSPECIFIED;
+}
+
+int kvm_arch_process_async_events(CPUState *cs)
+{
+return cs->halted;
+}
+
+bool kvm_arch_stop_on_emulation_error(CPUState *cs)
+{
+return true;
+}
+
+bool kvm_arch_cpu_check_are_resettable(void)
+{
+return true;
+}
+
+int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+{
+return 0;
+}
+
+void kvm_arch_accel_class_init(ObjectClass *oc)
+{
+}
Re: [PATCH v3 3/9] target/loongarch: Supplement vcpu env initial when vcpu reset
在 2023/12/28 下午4:40, Tianrui Zhao 写道:
Supplement vcpu env initial when vcpu reset, including
init vcpu CSR_CPUID,CSR_TID to cpu->cpu_index. The two
regs will be used in kvm_get/set_csr_ioctl.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index b26187dfde..4432a0081d 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -533,10 +533,12 @@ static void loongarch_cpu_reset_hold(Object *obj)
env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2));
env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0);
+env->CSR_CPUID = cs->cpu_index;
env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0);
env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);
+env->CSR_TID = cs->cpu_index;
env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2);
env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63);
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 00d1fba597..f6d5ef0852 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -319,6 +319,7 @@ typedef struct CPUArchState {
uint64_t CSR_PWCH;
uint64_t CSR_STLBPS;
uint64_t CSR_RVACFG;
+uint64_t CSR_CPUID;
uint64_t CSR_PRCFG1;
uint64_t CSR_PRCFG2;
uint64_t CSR_PRCFG3;
@@ -350,7 +351,6 @@ typedef struct CPUArchState {
uint64_t CSR_DBG;
uint64_t CSR_DERA;
uint64_t CSR_DSAVE;
-uint64_t CSR_CPUID;
#ifndef CONFIG_USER_ONLY
LoongArchTLB tlb[LOONGARCH_TLB_MAX];
Re: [PATCH v3 1/9] linux-headers: Synchronize linux headers from linux v6.7.0-rc7
在 2023/12/28 下午4:40, Tianrui Zhao 写道:
Use the scripts/update-linux-headers.sh to synchronize linux
headers from linux v6.7.0-rc7. We mainly want to add the
loongarch linux headers and then add the loongarch kvm support
based on it.
Signed-off-by: Tianrui Zhao
---
include/standard-headers/drm/drm_fourcc.h | 2 +
include/standard-headers/linux/fuse.h | 10 +-
include/standard-headers/linux/pci_regs.h | 24 ++-
include/standard-headers/linux/vhost_types.h | 7 +
.../standard-headers/linux/virtio_config.h| 5 +
include/standard-headers/linux/virtio_pci.h | 11 ++
linux-headers/asm-arm64/kvm.h | 32
linux-headers/asm-generic/unistd.h| 14 +-
linux-headers/asm-loongarch/bitsperlong.h | 1 +
linux-headers/asm-loongarch/kvm.h | 108 +++
linux-headers/asm-loongarch/mman.h| 1 +
linux-headers/asm-loongarch/unistd.h | 5 +
linux-headers/asm-mips/unistd_n32.h | 4 +
linux-headers/asm-mips/unistd_n64.h | 4 +
linux-headers/asm-mips/unistd_o32.h | 4 +
linux-headers/asm-powerpc/unistd_32.h | 4 +
linux-headers/asm-powerpc/unistd_64.h | 4 +
linux-headers/asm-riscv/kvm.h | 12 ++
linux-headers/asm-s390/unistd_32.h| 4 +
linux-headers/asm-s390/unistd_64.h| 4 +
linux-headers/asm-x86/unistd_32.h | 4 +
linux-headers/asm-x86/unistd_64.h | 3 +
linux-headers/asm-x86/unistd_x32.h| 3 +
linux-headers/linux/iommufd.h | 180 +-
linux-headers/linux/kvm.h | 11 ++
linux-headers/linux/psp-sev.h | 1 +
linux-headers/linux/stddef.h | 9 +-
linux-headers/linux/userfaultfd.h | 9 +-
linux-headers/linux/vfio.h| 47 +++--
linux-headers/linux/vhost.h | 8 +
30 files changed, 504 insertions(+), 31 deletions(-)
create mode 100644 linux-headers/asm-loongarch/bitsperlong.h
create mode 100644 linux-headers/asm-loongarch/kvm.h
create mode 100644 linux-headers/asm-loongarch/mman.h
create mode 100644 linux-headers/asm-loongarch/unistd.h
Acked-by: Song Gao
Thanks.
Song Gao
diff --git a/include/standard-headers/drm/drm_fourcc.h
b/include/standard-headers/drm/drm_fourcc.h
index 72279f4d25..3afb70160f 100644
--- a/include/standard-headers/drm/drm_fourcc.h
+++ b/include/standard-headers/drm/drm_fourcc.h
@@ -322,6 +322,8 @@ extern "C" {
* index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
*/
#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2
subsampled Cr:Cb plane */
+#define DRM_FORMAT_NV20fourcc_code('N', 'V', '2', '0') /* 2x1
subsampled Cr:Cb plane */
+#define DRM_FORMAT_NV30fourcc_code('N', 'V', '3', '0') /*
non-subsampled Cr:Cb plane */
/*
* 2 plane YCbCr MSB aligned
diff --git a/include/standard-headers/linux/fuse.h
b/include/standard-headers/linux/fuse.h
index 6b9793842c..fc0dcd10ae 100644
--- a/include/standard-headers/linux/fuse.h
+++ b/include/standard-headers/linux/fuse.h
@@ -209,7 +209,7 @@
* - add FUSE_HAS_EXPIRE_ONLY
*
* 7.39
- * - add FUSE_DIRECT_IO_RELAX
+ * - add FUSE_DIRECT_IO_ALLOW_MMAP
* - add FUSE_STATX and related structures
*/
@@ -405,8 +405,7 @@ struct fuse_file_lock {
* FUSE_CREATE_SUPP_GROUP: add supplementary group info to create, mkdir,
*symlink and mknod (single group that matches parent)
* FUSE_HAS_EXPIRE_ONLY: kernel supports expiry-only entry invalidation
- * FUSE_DIRECT_IO_RELAX: relax restrictions in FOPEN_DIRECT_IO mode, for now
- * allow shared mmap
+ * FUSE_DIRECT_IO_ALLOW_MMAP: allow shared mmap in FOPEN_DIRECT_IO mode.
*/
#define FUSE_ASYNC_READ (1 << 0)
#define FUSE_POSIX_LOCKS (1 << 1)
@@ -445,7 +444,10 @@ struct fuse_file_lock {
#define FUSE_HAS_INODE_DAX(1ULL << 33)
#define FUSE_CREATE_SUPP_GROUP(1ULL << 34)
#define FUSE_HAS_EXPIRE_ONLY (1ULL << 35)
-#define FUSE_DIRECT_IO_RELAX (1ULL << 36)
+#define FUSE_DIRECT_IO_ALLOW_MMAP (1ULL << 36)
+
+/* Obsolete alias for FUSE_DIRECT_IO_ALLOW_MMAP */
+#define FUSE_DIRECT_IO_RELAX FUSE_DIRECT_IO_ALLOW_MMAP
/**
* CUSE INIT request/reply flags
diff --git a/include/standard-headers/linux/pci_regs.h
b/include/standard-headers/linux/pci_regs.h
index e5f558d964..a39193213f 100644
--- a/include/standard-headers/linux/pci_regs.h
+++ b/include/standard-headers/linux/pci_regs.h
@@ -80,6 +80,7 @@
#define PCI_HEADER_TYPE_NORMAL 0
#define PCI_HEADER_TYPE_BRIDGE 1
#define PCI_HEADER_TYPE_CARDBUS 2
+#define PCI_HEADER_TYPE_MFD 0x80/* Multi-Function Device
(possible) */
#define PCI_BIST 0x0f /* 8 bits */
#define PCI_BIST_CODE_MASK 0x0f/* Return
Re: [PATCH v2 1/2] target/loongarch/meson: move gdbstub.c to loongarch.ss
在 2024/1/2 下午5:46, Philippe Mathieu-Daudé 写道: On 2/1/24 03:01, Song Gao wrote: gdbstub.c is not specific to TCG and can be used by other accelerators, such as KVM accelerator Suggested-by: Philippe Mathieu-Daudé I didn't really suggested the change but the split ;) Ah, I can drop it for pull request. Thanks. Song Gao. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Song Gao --- target/loongarch/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Re: [PATCH v3 8/9] target/loongarch: Implement set vcpu intr for kvm
This patch also broken 'loongarch64-linux-user' build
在 2023/12/28 下午4:40, Tianrui Zhao 写道:
Implement loongarch kvm set vcpu interrupt interface,
when a irq is set in vcpu, we use the KVM_INTERRUPT
ioctl to set intr into kvm.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
---
target/loongarch/cpu.c | 32 +++-
target/loongarch/kvm.c | 15 +++
target/loongarch/kvm_loongarch.h | 16
target/loongarch/trace-events| 1 +
4 files changed, 55 insertions(+), 9 deletions(-)
create mode 100644 target/loongarch/kvm_loongarch.h
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 83899c673f..caf82f9133 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -11,7 +11,6 @@
#include "qapi/error.h"
#include "qemu/module.h"
#include "sysemu/qtest.h"
-#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
#include "cpu.h"
#include "internals.h"
@@ -20,8 +19,16 @@
#ifndef CONFIG_USER_ONLY
#include "sysemu/reset.h"
#endif
-#include "tcg/tcg.h"
#include "vec.h"
+#include "sysemu/kvm.h"
+#include "kvm_loongarch.h"
+#ifdef CONFIG_KVM
+#include
+#endif
+#ifdef CONFIG_TCG
+#include "exec/cpu_ldst.h"
+#include "tcg/tcg.h"
+#endif
const char * const regnames[32] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
@@ -110,12 +117,15 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int
level)
return;
}
-env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
-
-if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
-cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+if (kvm_enabled()) {
+kvm_loongarch_set_interrupt(cpu, irq, level);
} else {
-cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
+if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
+cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+} else {
+cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+}
}
}
@@ -140,7 +150,9 @@ static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
return (pending & status) != 0;
}
+#endif
+#ifdef CONFIG_TCG
here
+#ifndef CONFIG_USER_ONLY
static void loongarch_cpu_do_interrupt(CPUState *cs)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
@@ -320,9 +332,7 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
}
return false;
}
-#endif
-#ifdef CONFIG_TCG
here
+#endif
Otherwise
Reviewed-by: Song Gao
Thanks.
Song Gao
static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@@ -560,7 +570,9 @@ static void loongarch_cpu_reset_hold(Object *obj)
}
#endif
+#ifdef CONFIG_TCG
restore_fp_status(env);
+#endif
cs->exception_index = -1;
}
@@ -802,7 +814,9 @@ static struct TCGCPUOps loongarch_tcg_ops = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps loongarch_sysemu_ops = {
+#ifdef CONFIG_TCG
.get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
+#endif
};
static int64_t loongarch_cpu_get_arch_id(CPUState *cs)
diff --git a/target/loongarch/kvm.c b/target/loongarch/kvm.c
index d2dab3fef4..bd33ec2114 100644
--- a/target/loongarch/kvm.c
+++ b/target/loongarch/kvm.c
@@ -748,6 +748,21 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
return ret;
}
+int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level)
+{
+struct kvm_interrupt intr;
+CPUState *cs = CPU(cpu);
+
+if (level) {
+intr.irq = irq;
+} else {
+intr.irq = -irq;
+}
+
+trace_kvm_set_intr(irq, level);
+return kvm_vcpu_ioctl(cs, KVM_INTERRUPT, );
+}
+
void kvm_arch_accel_class_init(ObjectClass *oc)
{
}
diff --git a/target/loongarch/kvm_loongarch.h b/target/loongarch/kvm_loongarch.h
new file mode 100644
index 00..d945b6bb82
--- /dev/null
+++ b/target/loongarch/kvm_loongarch.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch kvm interface
+ *
+ * Copyright (c) 2023 Loongson Technology Corporation Limited
+ */
+
+#include "cpu.h"
+
+#ifndef QEMU_KVM_LOONGARCH_H
+#define QEMU_KVM_LOONGARCH_H
+
+int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level);
+void kvm_arch_reset_vcpu(CPULoongArchState *env);
+
+#endif
diff --git a/target/loongarch/trace-events b/target/loongarch/trace-events
index 021839880e..dea11edc0f 100644
--- a/target/loongarch/trace-events
+++ b/target/loongarch/trace-events
@@ -12,3 +12,4 @@ kvm_failed_put_counter(const char *msg) "Failed to put counter
into KVM: %s"
kvm_failed_get_cpucfg(const char *msg) "Failed to get cpucfg from KVM: %s"
kvm_failed_put_cpucfg(const char *msg) "Failed to put cpucfg into KVM: %s"
kvm_arch_handle_exit(int num) "kvm arch handle exit,
Re: [PATCH v3 9/9] target/loongarch: Add loongarch kvm into meson build
Hi, TianRui
在 2023/12/28 下午4:40, Tianrui Zhao 写道:
Add kvm.c into meson.build to compile it when kvm
is configed. Meanwhile in meson.build, we set the
kvm_targets to loongarch64-softmmu when the cpu is
loongarch. And fix the compiling error when config
is enable-kvm,disable-tcg.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Richard Henderson
---
meson.build | 2 ++
target/loongarch/meson.build | 9 +
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/meson.build b/meson.build
index 445f2b7c2b..0c62b4156d 100644
--- a/meson.build
+++ b/meson.build
@@ -114,6 +114,8 @@ elif cpu in ['riscv32']
kvm_targets = ['riscv32-softmmu']
elif cpu in ['riscv64']
kvm_targets = ['riscv64-softmmu']
+elif cpu in ['loongarch64']
+ kvm_targets = ['loongarch64-softmmu']
else
kvm_targets = []
endif
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index 18e8191e2b..4a59356d0f 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -10,8 +10,10 @@ loongarch_tcg_ss.add(files(
'fpu_helper.c',
'op_helper.c',
'translate.c',
- 'gdbstub.c',
'vec_helper.c',
+ 'tlb_helper.c',
+ 'iocsr_helper.c',
+ 'csr_helper.c',
))
loongarch_tcg_ss.add(zlib)
this is broken 'loongarch64-linux-user' build.
I had moved tcg code to target/loongarch/tcg. see [1]
you just need rebase it.
[1]:
https://lore.kernel.org/all/20240102020200.3462097-2-gaos...@loongson.cn/
@@ -19,14 +21,13 @@ loongarch_system_ss = ss.source_set()
loongarch_system_ss.add(files(
'loongarch-qmp-cmds.c',
'machine.c',
- 'tlb_helper.c',
'constant_timer.c',
- 'csr_helper.c',
- 'iocsr_helper.c',
+ 'gdbstub.c',
))
'gdbstub.c' should move to loongarch_ss, because linus-user also
need it.
I had send a patch [1] to fix it . see [2]
[2]:
https://lore.kernel.org/all/20240102020200.3462097-1-gaos...@loongson.cn/
Thanks.
Song Gao
common_ss.add(when: 'CONFIG_LOONGARCH_DIS', if_true: [files('disas.c'), gen])
+loongarch_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
target_arch += {'loongarch': loongarch_ss}
Re: [PATCH 1/1] target/loongarch: move translate modules to tcg/
在 2023/12/29 下午6:08, Philippe Mathieu-Daudé 写道:
Hi,
On 29/12/23 10:24, Song Gao wrote:
Introduce the target/loongarch/tcg directory. Its purpose is to hold
the TCG
code that is selected by CONFIG_TCG
Signed-off-by: Song Gao
---
target/loongarch/{ => tcg}/constant_timer.c | 0
target/loongarch/{ => tcg}/csr_helper.c | 0
target/loongarch/{ => tcg}/fpu_helper.c | 0
target/loongarch/{ => tcg}/iocsr_helper.c | 0
target/loongarch/{ => tcg}/op_helper.c | 0
target/loongarch/{ => tcg}/tlb_helper.c | 0
target/loongarch/{ => tcg}/translate.c | 0
target/loongarch/{ => tcg}/vec_helper.c | 0
.../{ => tcg}/insn_trans/trans_arith.c.inc | 0
.../{ => tcg}/insn_trans/trans_atomic.c.inc | 0
.../{ => tcg}/insn_trans/trans_bit.c.inc | 0
.../{ => tcg}/insn_trans/trans_branch.c.inc | 0
.../{ => tcg}/insn_trans/trans_extra.c.inc | 0
.../{ => tcg}/insn_trans/trans_farith.c.inc | 0
.../{ => tcg}/insn_trans/trans_fcmp.c.inc | 0
.../{ => tcg}/insn_trans/trans_fcnv.c.inc | 0
.../{ => tcg}/insn_trans/trans_fmemory.c.inc | 0
.../{ => tcg}/insn_trans/trans_fmov.c.inc | 0
.../{ => tcg}/insn_trans/trans_memory.c.inc | 0
.../{ => tcg}/insn_trans/trans_privileged.c.inc | 0
.../{ => tcg}/insn_trans/trans_shift.c.inc | 0
.../{ => tcg}/insn_trans/trans_vec.c.inc | 0
target/loongarch/meson.build | 17 ++---
target/loongarch/tcg/meson.build | 15 +++
24 files changed, 17 insertions(+), 15 deletions(-)
rename target/loongarch/{ => tcg}/constant_timer.c (100%)
rename target/loongarch/{ => tcg}/csr_helper.c (100%)
rename target/loongarch/{ => tcg}/fpu_helper.c (100%)
rename target/loongarch/{ => tcg}/iocsr_helper.c (100%)
rename target/loongarch/{ => tcg}/op_helper.c (100%)
rename target/loongarch/{ => tcg}/tlb_helper.c (100%)
rename target/loongarch/{ => tcg}/translate.c (100%)
rename target/loongarch/{ => tcg}/vec_helper.c (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_arith.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_atomic.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_bit.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_branch.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_extra.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_farith.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_fcmp.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_fcnv.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_fmemory.c.inc
(100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_fmov.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_memory.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_privileged.c.inc
(100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_shift.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_vec.c.inc (100%)
create mode 100644 target/loongarch/tcg/meson.build
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index 18e8191e2b..a004523439 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -3,31 +3,18 @@ gen = decodetree.process('insns.decode')
loongarch_ss = ss.source_set()
loongarch_ss.add(files(
'cpu.c',
+ 'gdbstub.c'
Preferably a preliminary commit "gdbstub.c is not specific to TCG and
can be used by other accelerators ...". Otherwise just mention it in
this patch description.
I will split it to a new patch.
))
-loongarch_tcg_ss = ss.source_set()
-loongarch_tcg_ss.add(gen)
-loongarch_tcg_ss.add(files(
- 'fpu_helper.c',
- 'op_helper.c',
- 'translate.c',
- 'gdbstub.c',
- 'vec_helper.c',
-))
-loongarch_tcg_ss.add(zlib)
loongarch_system_ss = ss.source_set()
loongarch_system_ss.add(files(
'loongarch-qmp-cmds.c',
'machine.c',
- 'tlb_helper.c',
- 'constant_timer.c',
- 'csr_helper.c',
- 'iocsr_helper.c',
))
common_ss.add(when: 'CONFIG_LOONGARCH_DIS', if_true:
[files('disas.c'), gen])
-loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
+subdir('tcg')
target_arch += {'loongarch': loongarch_ss}
target_system_arch += {'loongarch': loongarch_system_ss}
diff --git a/target/loongarch/tcg/meson.build
b/target/loongarch/tcg/meson.build
new file mode 100644
index 00..bb7411e5e5
--- /dev/null
+++ b/target/loongarch/tcg/meson.build
@@ -0,0 +1,15 @@
You missed the CONFIG_TCG check, you can use either:
if 'CONFIG_TCG' in config_all
subdir('tcg')
endif
in target/loongarch/meson.build, but since your target seems well
designed and doesn't require TCG stub, you can do directly here:
if 'CONFIG_TCG' not in config_all
subdir_done()
endif
so the rest of this file isn't processed.
Got it
+loongarch_ss.add([zlib, gen])
+
Re: [PATCH v3 03/17] hw/loongarch: Add slave cpu boot_code
在 2023/12/27 下午4:52, Philippe Mathieu-Daudé 写道:
Hi,
On 27/12/23 09:08, Song Gao wrote:
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 71 -
1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 3075c276d4..faff880153 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@ -14,6 +14,54 @@
#include "qemu/error-report.h"
#include "sysemu/reset.h"
+static unsigned int slave_boot_code[] = {
'const'
Got it.
+ /* Configure reset ebase. */
+ 0x0400302c, /* csrwr $r12,0xc */
+
+ /* Disable interrupt. */
+ 0x0380100c, /* ori $r12,$r0,0x4 */
+ 0x04000180, /* csrxchg $r0,$r12,0x0 */
+
+ /* Clear mailbox. */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038081ad, /* ori $r13,$r13,0x20 */
+ 0x06481da0, /* iocsrwr.d $r0,$r13 */
+
+ /* Enable IPI interrupt. */
+ 0x142c, /* lu12i.w $r12,1(0x1) */
+ 0x0400118c, /* csrxchg $r12,$r12,0x4 */
+ 0x02fffc0c, /* addi.d $r12,$r0,-1(0xfff) */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038011ad, /* ori $r13,$r13,0x4 */
+ 0x064819ac, /* iocsrwr.w $r12,$r13 */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038081ad, /* ori $r13,$r13,0x20 */
+
+ /* Wait for wakeup <.L11>: */
+ 0x06488000, /* idle 0x0 */
+ 0x0340, /* andi $r0,$r0,0x0 */
+ 0x064809ac, /* iocsrrd.w $r12,$r13 */
+ 0x43fff59f, /* beqz $r12,-12(0x74) # 48 <.L11> */
+
+ /* Read and clear IPI interrupt. */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x064809ac, /* iocsrrd.w $r12,$r13 */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038031ad, /* ori $r13,$r13,0xc */
+ 0x064819ac, /* iocsrwr.w $r12,$r13 */
+
+ /* Disable IPI interrupt. */
+ 0x142c, /* lu12i.w $r12,1(0x1) */
+ 0x04001180, /* csrxchg $r0,$r12,0x4 */
+
+ /* Read mail buf and jump to specified entry */
+ 0x142d, /* lu12i.w $r13,1(0x1) */
+ 0x038081ad, /* ori $r13,$r13,0x20 */
+ 0x06480dac, /* iocsrrd.d $r12,$r13 */
+ 0x00150181, /* move $r1,$r12 */
+ 0x4c20, /* jirl $r0,$r1,0 */
+};
+
static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t
addr)
{
return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
@@ -110,11 +158,19 @@ static void
loongarch_firmware_boot(LoongArchMachineState *lams,
fw_cfg_add_kernel_info(info, lams->fw_cfg);
}
+static void init_boot_rom(struct loongarch_boot_info *info, void *p)
+{
+ memcpy(p, _boot_code, sizeof(slave_boot_code));
+ p += sizeof(slave_boot_code);
+}
+
static void loongarch_direct_kernel_boot(struct loongarch_boot_info
*info)
{
+ static void *p;
Why 'static'?
I will drop it.
int64_t kernel_addr = 0;
LoongArchCPU *lacpu;
CPUState *cs;
+ void *bp;
if (info->kernel_filename) {
kernel_addr = load_kernel_info(info);
@@ -123,11 +179,24 @@ static void loongarch_direct_kernel_boot(struct
loongarch_boot_info *info)
exit(1);
}
+ /* Load 'boot_rom' at [0 - 1MiB] */
+ p = g_malloc0(1 * MiB);
+ bp = p;
+ init_boot_rom(info, p);
+ rom_add_blob_fixed("boot_rom", bp, 1 * MiB, 0);
+
CPU_FOREACH(cs) {
lacpu = LOONGARCH_CPU(cs);
lacpu->env.load_elf = true;
- lacpu->env.elf_address = kernel_addr;
+ if (cs == first_cpu) {
+ lacpu->env.elf_address = kernel_addr;
+ } else {
+ lacpu->env.elf_address = 0;
+ }
+ lacpu->env.boot_info = info;
}
+
+ g_free(bp);
(besides, IIUC 'p' now points to released memory).
Yes.
Thanks.
Song Gao
}
void loongarch_load_kernel(MachineState *ms, struct
loongarch_boot_info *info)
Re: [PATCH v3 04/17] hw/loongarch: Add init_cmdline
在 2023/12/27 下午4:49, Philippe Mathieu-Daudé 写道: Hi, On 27/12/23 09:08, Song Gao wrote: Add init_cmline and set boot_info->a0, a1 Signed-off-by: Song Gao --- hw/loongarch/boot.c | 20 target/loongarch/cpu.h | 2 ++ 2 files changed, 22 insertions(+) diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c index faff880153..27eae6f0cb 100644 --- a/hw/loongarch/boot.c +++ b/hw/loongarch/boot.c @@ -13,6 +13,7 @@ #include "elf.h" #include "qemu/error-report.h" #include "sysemu/reset.h" +#include Build failure on Darwin host: [1135/1207] Compiling C object libqemu-loongarch64-softmmu.fa.p/hw_loongarch_boot.c.o FAILED: libqemu-loongarch64-softmmu.fa.p/hw_loongarch_boot.c.o ../../hw/loongarch/boot.c:16:10: fatal error: 'asm-generic/setup.h' file not found #include ^ 1 error generated. ninja: build stopped: subcommand failed. I will drop it , use #define COMAND_LINE_SIZE 512. Thanks. Song Gao
Re: [PATCH v3 11/17] hw/loongarch: fdt adds Extend I/O Interrupt Controller
在 2023/12/27 下午5:02, Philippe Mathieu-Daudé 写道: Hi, On 27/12/23 09:08, Song Gao wrote: fdt adds Extend I/O Interrupt Controller, we use 'loongson,ls2k2000-eiointc'. See: drivers/irqchip/irq-loongson-eiointc.c Better reference a fixed commit/tag, and mention Linux project. Suggestion: 'See https://github.com/torvalds/linux/blob/v6.6/drivers/irqchip/irq-loongson-eiointc.c'. Got it. Thanks. Song Gao Signed-off-by: Song Gao --- hw/loongarch/virt.c | 30 +- include/hw/intc/loongarch_extioi.h | 1 + 2 files changed, 30 insertions(+), 1 deletion(-)
