Re: [PATCH 1/2] ppc/pnv: Begin a more complete ADU LPC model for POWER9/10
On Fri May 3, 2024 at 3:44 PM AEST, Cédric Le Goater wrote: > On 5/3/24 06:51, Nicholas Piggin wrote: > > On Thu May 2, 2024 at 6:47 PM AEST, Cédric Le Goater wrote: > >> On 5/1/24 14:39, Nicholas Piggin wrote: > >>> On Wed Apr 17, 2024 at 9:25 PM AEST, Cédric Le Goater wrote: > Hello Nick, > > On 4/17/24 13:02, Nicholas Piggin wrote: > > This implements a framework for an ADU unit model. > > > > The ADU unit actually implements XSCOM, which is the bridge between MMIO > > and PIB. However it also includes control and status registers and other > > functions that are exposed as PIB (xscom) registers. > > > > To keep things simple, pnv_xscom.c remains the XSCOM bridge > > implementation, and pnv_adu.c implements the ADU registers and other > > functions. > > > > So far, just the ADU no-op registers in the pnv_xscom.c default handler > > are moved over to the adu model. > > > > Signed-off-by: Nicholas Piggin > > --- > > include/hw/ppc/pnv_adu.h | 34 > > include/hw/ppc/pnv_chip.h | 3 + > > include/hw/ppc/pnv_xscom.h | 6 ++ > > hw/ppc/pnv.c | 16 ++ > > hw/ppc/pnv_adu.c | 111 > > + > > hw/ppc/pnv_xscom.c | 9 --- > > hw/ppc/meson.build | 1 + > > hw/ppc/trace-events| 4 ++ > > 8 files changed, 175 insertions(+), 9 deletions(-) > > create mode 100644 include/hw/ppc/pnv_adu.h > > create mode 100644 hw/ppc/pnv_adu.c > > > > diff --git a/include/hw/ppc/pnv_adu.h b/include/hw/ppc/pnv_adu.h > > new file mode 100644 > > index 00..9dc91857a9 > > --- /dev/null > > +++ b/include/hw/ppc/pnv_adu.h > > @@ -0,0 +1,34 @@ > > +/* > > + * QEMU PowerPC PowerNV Emulation of some ADU behaviour > > + * > > + * Copyright (c) 2024, IBM Corporation. > > + * > > + * SPDX-License-Identifier: LGPL-2.1-or-later > > > Did you mean GPL-2.0-or-later ? > >>> > >>> Hey Cedric, > >>> > >>> Thanks for reviewing, I've been away so sorry for the late reply. > >>> > >>> It just came from one of the headers I copied which was LGPL. But > >>> there's really nothing much in it and could find a GPL header to > >>> copy. Is GPL-2.0-or-later preferred? > >> > >> I would since all pnv models are GPL. > > > > Some of pnv is actually LGPL. > > I was grepping for 'LGPL' and not 'Lesser' ... Indeed you are right. > Most files miss an SPDX-License-Identifier tag also. > > > That's okay I'll change to GPL. > > LGPL is more relaxed if the code needs to be used in libraries, but > I am not sure it applies to the PNV models. What would you prefer ? GPL seems to be more common and I don't see a need for LGPL here, so maybe GPL? We could probably switch all LGPL pnv over to GPL if we wanted to. I think LGPL permits such relicensing. Will leave this discussion for another time though. Thanks, Nick
Re: [PATCH 1/2] ppc/pnv: Begin a more complete ADU LPC model for POWER9/10
On 5/3/24 06:51, Nicholas Piggin wrote: On Thu May 2, 2024 at 6:47 PM AEST, Cédric Le Goater wrote: On 5/1/24 14:39, Nicholas Piggin wrote: On Wed Apr 17, 2024 at 9:25 PM AEST, Cédric Le Goater wrote: Hello Nick, On 4/17/24 13:02, Nicholas Piggin wrote: This implements a framework for an ADU unit model. The ADU unit actually implements XSCOM, which is the bridge between MMIO and PIB. However it also includes control and status registers and other functions that are exposed as PIB (xscom) registers. To keep things simple, pnv_xscom.c remains the XSCOM bridge implementation, and pnv_adu.c implements the ADU registers and other functions. So far, just the ADU no-op registers in the pnv_xscom.c default handler are moved over to the adu model. Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv_adu.h | 34 include/hw/ppc/pnv_chip.h | 3 + include/hw/ppc/pnv_xscom.h | 6 ++ hw/ppc/pnv.c | 16 ++ hw/ppc/pnv_adu.c | 111 + hw/ppc/pnv_xscom.c | 9 --- hw/ppc/meson.build | 1 + hw/ppc/trace-events| 4 ++ 8 files changed, 175 insertions(+), 9 deletions(-) create mode 100644 include/hw/ppc/pnv_adu.h create mode 100644 hw/ppc/pnv_adu.c diff --git a/include/hw/ppc/pnv_adu.h b/include/hw/ppc/pnv_adu.h new file mode 100644 index 00..9dc91857a9 --- /dev/null +++ b/include/hw/ppc/pnv_adu.h @@ -0,0 +1,34 @@ +/* + * QEMU PowerPC PowerNV Emulation of some ADU behaviour + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: LGPL-2.1-or-later Did you mean GPL-2.0-or-later ? Hey Cedric, Thanks for reviewing, I've been away so sorry for the late reply. It just came from one of the headers I copied which was LGPL. But there's really nothing much in it and could find a GPL header to copy. Is GPL-2.0-or-later preferred? I would since all pnv models are GPL. Some of pnv is actually LGPL. I was grepping for 'LGPL' and not 'Lesser' ... Indeed you are right. Most files miss an SPDX-License-Identifier tag also. That's okay I'll change to GPL. LGPL is more relaxed if the code needs to be used in libraries, but I am not sure it applies to the PNV models. What would you prefer ? C. I think some parts of QEMU were initially LGPL (there used to be a library, may be that's the reason ?) and other parts are relaxed to LGPL because they are reused in libraries. Thanks, Nick
Re: [PATCH 1/2] ppc/pnv: Begin a more complete ADU LPC model for POWER9/10
On Thu May 2, 2024 at 6:47 PM AEST, Cédric Le Goater wrote: > On 5/1/24 14:39, Nicholas Piggin wrote: > > On Wed Apr 17, 2024 at 9:25 PM AEST, Cédric Le Goater wrote: > >> Hello Nick, > >> > >> On 4/17/24 13:02, Nicholas Piggin wrote: > >>> This implements a framework for an ADU unit model. > >>> > >>> The ADU unit actually implements XSCOM, which is the bridge between MMIO > >>> and PIB. However it also includes control and status registers and other > >>> functions that are exposed as PIB (xscom) registers. > >>> > >>> To keep things simple, pnv_xscom.c remains the XSCOM bridge > >>> implementation, and pnv_adu.c implements the ADU registers and other > >>> functions. > >>> > >>> So far, just the ADU no-op registers in the pnv_xscom.c default handler > >>> are moved over to the adu model. > >>> > >>> Signed-off-by: Nicholas Piggin > >>> --- > >>>include/hw/ppc/pnv_adu.h | 34 > >>>include/hw/ppc/pnv_chip.h | 3 + > >>>include/hw/ppc/pnv_xscom.h | 6 ++ > >>>hw/ppc/pnv.c | 16 ++ > >>>hw/ppc/pnv_adu.c | 111 + > >>>hw/ppc/pnv_xscom.c | 9 --- > >>>hw/ppc/meson.build | 1 + > >>>hw/ppc/trace-events| 4 ++ > >>>8 files changed, 175 insertions(+), 9 deletions(-) > >>>create mode 100644 include/hw/ppc/pnv_adu.h > >>>create mode 100644 hw/ppc/pnv_adu.c > >>> > >>> diff --git a/include/hw/ppc/pnv_adu.h b/include/hw/ppc/pnv_adu.h > >>> new file mode 100644 > >>> index 00..9dc91857a9 > >>> --- /dev/null > >>> +++ b/include/hw/ppc/pnv_adu.h > >>> @@ -0,0 +1,34 @@ > >>> +/* > >>> + * QEMU PowerPC PowerNV Emulation of some ADU behaviour > >>> + * > >>> + * Copyright (c) 2024, IBM Corporation. > >>> + * > >>> + * SPDX-License-Identifier: LGPL-2.1-or-later > >> > >> > >> Did you mean GPL-2.0-or-later ? > > > > Hey Cedric, > > > > Thanks for reviewing, I've been away so sorry for the late reply. > > > > It just came from one of the headers I copied which was LGPL. But > > there's really nothing much in it and could find a GPL header to > > copy. Is GPL-2.0-or-later preferred? > > I would since all pnv models are GPL. Some of pnv is actually LGPL. That's okay I'll change to GPL. > I think some parts of QEMU were initially LGPL (there used to be > a library, may be that's the reason ?) and other parts are relaxed > to LGPL because they are reused in libraries. Thanks, Nick
Re: [PATCH 1/2] ppc/pnv: Begin a more complete ADU LPC model for POWER9/10
On 5/1/24 14:39, Nicholas Piggin wrote: On Wed Apr 17, 2024 at 9:25 PM AEST, Cédric Le Goater wrote: Hello Nick, On 4/17/24 13:02, Nicholas Piggin wrote: This implements a framework for an ADU unit model. The ADU unit actually implements XSCOM, which is the bridge between MMIO and PIB. However it also includes control and status registers and other functions that are exposed as PIB (xscom) registers. To keep things simple, pnv_xscom.c remains the XSCOM bridge implementation, and pnv_adu.c implements the ADU registers and other functions. So far, just the ADU no-op registers in the pnv_xscom.c default handler are moved over to the adu model. Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv_adu.h | 34 include/hw/ppc/pnv_chip.h | 3 + include/hw/ppc/pnv_xscom.h | 6 ++ hw/ppc/pnv.c | 16 ++ hw/ppc/pnv_adu.c | 111 + hw/ppc/pnv_xscom.c | 9 --- hw/ppc/meson.build | 1 + hw/ppc/trace-events| 4 ++ 8 files changed, 175 insertions(+), 9 deletions(-) create mode 100644 include/hw/ppc/pnv_adu.h create mode 100644 hw/ppc/pnv_adu.c diff --git a/include/hw/ppc/pnv_adu.h b/include/hw/ppc/pnv_adu.h new file mode 100644 index 00..9dc91857a9 --- /dev/null +++ b/include/hw/ppc/pnv_adu.h @@ -0,0 +1,34 @@ +/* + * QEMU PowerPC PowerNV Emulation of some ADU behaviour + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: LGPL-2.1-or-later Did you mean GPL-2.0-or-later ? Hey Cedric, Thanks for reviewing, I've been away so sorry for the late reply. It just came from one of the headers I copied which was LGPL. But there's really nothing much in it and could find a GPL header to copy. Is GPL-2.0-or-later preferred? I would since all pnv models are GPL. I think some parts of QEMU were initially LGPL (there used to be a library, may be that's the reason ?) and other parts are relaxed to LGPL because they are reused in libraries. Thanks, C.
Re: [PATCH 1/2] ppc/pnv: Begin a more complete ADU LPC model for POWER9/10
On Wed Apr 17, 2024 at 9:25 PM AEST, Cédric Le Goater wrote: > Hello Nick, > > On 4/17/24 13:02, Nicholas Piggin wrote: > > This implements a framework for an ADU unit model. > > > > The ADU unit actually implements XSCOM, which is the bridge between MMIO > > and PIB. However it also includes control and status registers and other > > functions that are exposed as PIB (xscom) registers. > > > > To keep things simple, pnv_xscom.c remains the XSCOM bridge > > implementation, and pnv_adu.c implements the ADU registers and other > > functions. > > > > So far, just the ADU no-op registers in the pnv_xscom.c default handler > > are moved over to the adu model. > > > > Signed-off-by: Nicholas Piggin > > --- > > include/hw/ppc/pnv_adu.h | 34 > > include/hw/ppc/pnv_chip.h | 3 + > > include/hw/ppc/pnv_xscom.h | 6 ++ > > hw/ppc/pnv.c | 16 ++ > > hw/ppc/pnv_adu.c | 111 + > > hw/ppc/pnv_xscom.c | 9 --- > > hw/ppc/meson.build | 1 + > > hw/ppc/trace-events| 4 ++ > > 8 files changed, 175 insertions(+), 9 deletions(-) > > create mode 100644 include/hw/ppc/pnv_adu.h > > create mode 100644 hw/ppc/pnv_adu.c > > > > diff --git a/include/hw/ppc/pnv_adu.h b/include/hw/ppc/pnv_adu.h > > new file mode 100644 > > index 00..9dc91857a9 > > --- /dev/null > > +++ b/include/hw/ppc/pnv_adu.h > > @@ -0,0 +1,34 @@ > > +/* > > + * QEMU PowerPC PowerNV Emulation of some ADU behaviour > > + * > > + * Copyright (c) 2024, IBM Corporation. > > + * > > + * SPDX-License-Identifier: LGPL-2.1-or-later > > > Did you mean GPL-2.0-or-later ? Hey Cedric, Thanks for reviewing, I've been away so sorry for the late reply. It just came from one of the headers I copied which was LGPL. But there's really nothing much in it and could find a GPL header to copy. Is GPL-2.0-or-later preferred? Thanks, Nick
Re: [PATCH 1/2] ppc/pnv: Begin a more complete ADU LPC model for POWER9/10
Hello Nick,
On 4/17/24 13:02, Nicholas Piggin wrote:
This implements a framework for an ADU unit model.
The ADU unit actually implements XSCOM, which is the bridge between MMIO
and PIB. However it also includes control and status registers and other
functions that are exposed as PIB (xscom) registers.
To keep things simple, pnv_xscom.c remains the XSCOM bridge
implementation, and pnv_adu.c implements the ADU registers and other
functions.
So far, just the ADU no-op registers in the pnv_xscom.c default handler
are moved over to the adu model.
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_adu.h | 34
include/hw/ppc/pnv_chip.h | 3 +
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv.c | 16 ++
hw/ppc/pnv_adu.c | 111 +
hw/ppc/pnv_xscom.c | 9 ---
hw/ppc/meson.build | 1 +
hw/ppc/trace-events| 4 ++
8 files changed, 175 insertions(+), 9 deletions(-)
create mode 100644 include/hw/ppc/pnv_adu.h
create mode 100644 hw/ppc/pnv_adu.c
diff --git a/include/hw/ppc/pnv_adu.h b/include/hw/ppc/pnv_adu.h
new file mode 100644
index 00..9dc91857a9
--- /dev/null
+++ b/include/hw/ppc/pnv_adu.h
@@ -0,0 +1,34 @@
+/*
+ * QEMU PowerPC PowerNV Emulation of some ADU behaviour
+ *
+ * Copyright (c) 2024, IBM Corporation.
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
Did you mean GPL-2.0-or-later ?
The rest looks good.
Thanks,
C.
+ */
+
+#ifndef PPC_PNV_ADU_H
+#define PPC_PNV_ADU_H
+
+#include "hw/ppc/pnv.h"
+#include "hw/qdev-core.h"
+
+#define TYPE_PNV_ADU "pnv-adu"
+
+OBJECT_DECLARE_TYPE(PnvADU, PnvADUClass, PNV_ADU)
+
+struct PnvADU {
+DeviceState xd;
+
+MemoryRegion xscom_regs;
+};
+
+struct PnvADUClass {
+DeviceClass parent_class;
+
+int xscom_ctrl_size;
+int xscom_mbox_size;
+const MemoryRegionOps *xscom_ctrl_ops;
+const MemoryRegionOps *xscom_mbox_ops;
+};
+
+#endif /* PPC_PNV_ADU_H */
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index 8589f3291e..96e50a2983 100644
--- a/include/hw/ppc/pnv_chip.h
+++ b/include/hw/ppc/pnv_chip.h
@@ -2,6 +2,7 @@
#define PPC_PNV_CHIP_H
#include "hw/pci-host/pnv_phb4.h"
+#include "hw/ppc/pnv_adu.h"
#include "hw/ppc/pnv_chiptod.h"
#include "hw/ppc/pnv_core.h"
#include "hw/ppc/pnv_homer.h"
@@ -77,6 +78,7 @@ struct Pnv9Chip {
PnvChip parent_obj;
/*< public >*/
+PnvADU adu;
PnvXive xive;
Pnv9Psi psi;
PnvLpcController lpc;
@@ -110,6 +112,7 @@ struct Pnv10Chip {
PnvChip parent_obj;
/*< public >*/
+PnvADU adu;
PnvXive2 xive;
Pnv9Psi psi;
PnvLpcController lpc;
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 6209e18492..e93d310e79 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -82,6 +82,9 @@ struct PnvXScomInterfaceClass {
#define PNV_XSCOM_PBCQ_SPCI_BASE 0x9013c00
#define PNV_XSCOM_PBCQ_SPCI_SIZE 0x5
+#define PNV9_XSCOM_ADU_BASE 0x009
+#define PNV9_XSCOM_ADU_SIZE 0x55
+
/*
* Layout of the XSCOM PCB addresses (POWER 9)
*/
@@ -128,6 +131,9 @@ struct PnvXScomInterfaceClass {
#define PNV9_XSCOM_PEC_PCI_STK1 0x140
#define PNV9_XSCOM_PEC_PCI_STK2 0x180
+#define PNV10_XSCOM_ADU_BASE 0x009
+#define PNV10_XSCOM_ADU_SIZE 0x55
+
/*
* Layout of the XSCOM PCB addresses (POWER 10)
*/
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6e3a5ccdec..5869aac89a 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1530,6 +1530,7 @@ static void pnv_chip_power9_instance_init(Object *obj)
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
int i;
+object_initialize_child(obj, "adu", >adu, TYPE_PNV_ADU);
object_initialize_child(obj, "xive", >xive, TYPE_PNV_XIVE);
object_property_add_alias(obj, "xive-fabric", OBJECT(>xive),
"xive-fabric");
@@ -1640,6 +1641,13 @@ static void pnv_chip_power9_realize(DeviceState *dev,
Error **errp)
return;
}
+/* ADU */
+if (!qdev_realize(DEVICE(>adu), NULL, errp)) {
+return;
+}
+pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE,
+>adu.xscom_regs);
+
pnv_chip_quad_realize(chip9, _err);
if (local_err) {
error_propagate(errp, local_err);
@@ -1806,6 +1814,7 @@ static void pnv_chip_power10_instance_init(Object *obj)
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
int i;
+object_initialize_child(obj, "adu", >adu, TYPE_PNV_ADU);
object_initialize_child(obj, "xive", >xive, TYPE_PNV_XIVE2);
object_property_add_alias(obj, "xive-fabric", OBJECT(>xive),
"xive-fabric");
@@ -1898,6 +1907,13 @@ static void pnv_chip_power10_realize(DeviceState *dev,
Error **errp)
return;
}
+/* ADU */
+if (!qdev_realize(DEVICE(>adu),
[PATCH 1/2] ppc/pnv: Begin a more complete ADU LPC model for POWER9/10
This implements a framework for an ADU unit model.
The ADU unit actually implements XSCOM, which is the bridge between MMIO
and PIB. However it also includes control and status registers and other
functions that are exposed as PIB (xscom) registers.
To keep things simple, pnv_xscom.c remains the XSCOM bridge
implementation, and pnv_adu.c implements the ADU registers and other
functions.
So far, just the ADU no-op registers in the pnv_xscom.c default handler
are moved over to the adu model.
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_adu.h | 34
include/hw/ppc/pnv_chip.h | 3 +
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv.c | 16 ++
hw/ppc/pnv_adu.c | 111 +
hw/ppc/pnv_xscom.c | 9 ---
hw/ppc/meson.build | 1 +
hw/ppc/trace-events| 4 ++
8 files changed, 175 insertions(+), 9 deletions(-)
create mode 100644 include/hw/ppc/pnv_adu.h
create mode 100644 hw/ppc/pnv_adu.c
diff --git a/include/hw/ppc/pnv_adu.h b/include/hw/ppc/pnv_adu.h
new file mode 100644
index 00..9dc91857a9
--- /dev/null
+++ b/include/hw/ppc/pnv_adu.h
@@ -0,0 +1,34 @@
+/*
+ * QEMU PowerPC PowerNV Emulation of some ADU behaviour
+ *
+ * Copyright (c) 2024, IBM Corporation.
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef PPC_PNV_ADU_H
+#define PPC_PNV_ADU_H
+
+#include "hw/ppc/pnv.h"
+#include "hw/qdev-core.h"
+
+#define TYPE_PNV_ADU "pnv-adu"
+
+OBJECT_DECLARE_TYPE(PnvADU, PnvADUClass, PNV_ADU)
+
+struct PnvADU {
+DeviceState xd;
+
+MemoryRegion xscom_regs;
+};
+
+struct PnvADUClass {
+DeviceClass parent_class;
+
+int xscom_ctrl_size;
+int xscom_mbox_size;
+const MemoryRegionOps *xscom_ctrl_ops;
+const MemoryRegionOps *xscom_mbox_ops;
+};
+
+#endif /* PPC_PNV_ADU_H */
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index 8589f3291e..96e50a2983 100644
--- a/include/hw/ppc/pnv_chip.h
+++ b/include/hw/ppc/pnv_chip.h
@@ -2,6 +2,7 @@
#define PPC_PNV_CHIP_H
#include "hw/pci-host/pnv_phb4.h"
+#include "hw/ppc/pnv_adu.h"
#include "hw/ppc/pnv_chiptod.h"
#include "hw/ppc/pnv_core.h"
#include "hw/ppc/pnv_homer.h"
@@ -77,6 +78,7 @@ struct Pnv9Chip {
PnvChip parent_obj;
/*< public >*/
+PnvADU adu;
PnvXive xive;
Pnv9Psi psi;
PnvLpcController lpc;
@@ -110,6 +112,7 @@ struct Pnv10Chip {
PnvChip parent_obj;
/*< public >*/
+PnvADU adu;
PnvXive2 xive;
Pnv9Psi psi;
PnvLpcController lpc;
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 6209e18492..e93d310e79 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -82,6 +82,9 @@ struct PnvXScomInterfaceClass {
#define PNV_XSCOM_PBCQ_SPCI_BASE 0x9013c00
#define PNV_XSCOM_PBCQ_SPCI_SIZE 0x5
+#define PNV9_XSCOM_ADU_BASE 0x009
+#define PNV9_XSCOM_ADU_SIZE 0x55
+
/*
* Layout of the XSCOM PCB addresses (POWER 9)
*/
@@ -128,6 +131,9 @@ struct PnvXScomInterfaceClass {
#define PNV9_XSCOM_PEC_PCI_STK1 0x140
#define PNV9_XSCOM_PEC_PCI_STK2 0x180
+#define PNV10_XSCOM_ADU_BASE 0x009
+#define PNV10_XSCOM_ADU_SIZE 0x55
+
/*
* Layout of the XSCOM PCB addresses (POWER 10)
*/
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6e3a5ccdec..5869aac89a 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1530,6 +1530,7 @@ static void pnv_chip_power9_instance_init(Object *obj)
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
int i;
+object_initialize_child(obj, "adu", >adu, TYPE_PNV_ADU);
object_initialize_child(obj, "xive", >xive, TYPE_PNV_XIVE);
object_property_add_alias(obj, "xive-fabric", OBJECT(>xive),
"xive-fabric");
@@ -1640,6 +1641,13 @@ static void pnv_chip_power9_realize(DeviceState *dev,
Error **errp)
return;
}
+/* ADU */
+if (!qdev_realize(DEVICE(>adu), NULL, errp)) {
+return;
+}
+pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE,
+>adu.xscom_regs);
+
pnv_chip_quad_realize(chip9, _err);
if (local_err) {
error_propagate(errp, local_err);
@@ -1806,6 +1814,7 @@ static void pnv_chip_power10_instance_init(Object *obj)
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
int i;
+object_initialize_child(obj, "adu", >adu, TYPE_PNV_ADU);
object_initialize_child(obj, "xive", >xive, TYPE_PNV_XIVE2);
object_property_add_alias(obj, "xive-fabric", OBJECT(>xive),
"xive-fabric");
@@ -1898,6 +1907,13 @@ static void pnv_chip_power10_realize(DeviceState *dev,
Error **errp)
return;
}
+/* ADU */
+if (!qdev_realize(DEVICE(>adu), NULL, errp)) {
+return;
+}
+pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE,
+>adu.xscom_regs);
+
pnv_chip_power10_quad_realize(chip10, _err);
if
