Re: [PATCH RESEND v5 03/57] target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector instructions

[gaosong]

在 2023/9/8 上午1:34, Richard Henderson 写道:

On 9/7/23 01:31, Song Gao wrote:
+static bool gen__ptr_vl(DisasContext *ctx, arg_ *a, uint32_t 
oprsz,

+    gen_helper_gvec_4_ptr *fn)
+{
+    tcg_gen_gvec_4_ptr(vec_full_offset(a->vd),
+   vec_full_offset(a->vj),
+   vec_full_offset(a->vk),
+   vec_full_offset(a->va),
+   cpu_env,
+   oprsz, ctx->vl / 8, oprsz, fn);

   ^

This next to last argument is 'data', which is unused for this case.
Just use 0 here.


Got it,  I will correct the other 6 similar patches.

Thanks.
Song Gao

Re: [PATCH RESEND v5 03/57] target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector instructions

[Richard Henderson]

On 9/7/23 01:31, Song Gao wrote:

+static bool gen__ptr_vl(DisasContext *ctx, arg_ *a, uint32_t oprsz,
+gen_helper_gvec_4_ptr *fn)
+{
+tcg_gen_gvec_4_ptr(vec_full_offset(a->vd),
+   vec_full_offset(a->vj),
+   vec_full_offset(a->vk),
+   vec_full_offset(a->va),
+   cpu_env,
+   oprsz, ctx->vl / 8, oprsz, fn);

  ^

This next to last argument is 'data', which is unused for this case.
Just use 0 here.

Otherwise,
Reviewed-by: Richard Henderson 


r~

[PATCH RESEND v5 03/57] target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector instructions

[Song Gao]

Signed-off-by: Song Gao 
---
 target/loongarch/helper.h   | 16 +-
 target/loongarch/vec_helper.c   | 12 +++
 target/loongarch/insn_trans/trans_vec.c.inc | 35 -
 3 files changed, 41 insertions(+), 22 deletions(-)

diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index ffb1e0b0bf..ead16567c2 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -528,14 +528,14 @@ DEF_HELPER_4(vfmul_d, void, env, i32, i32, i32)
 DEF_HELPER_4(vfdiv_s, void, env, i32, i32, i32)
 DEF_HELPER_4(vfdiv_d, void, env, i32, i32, i32)
 
-DEF_HELPER_5(vfmadd_s, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(vfmadd_d, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(vfmsub_s, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(vfmsub_d, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(vfnmadd_s, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(vfnmadd_d, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(vfnmsub_s, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(vfnmsub_d, void, env, i32, i32, i32, i32)
+DEF_HELPER_FLAGS_6(vfmadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, 
i32)
+DEF_HELPER_FLAGS_6(vfmadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, 
i32)
+DEF_HELPER_FLAGS_6(vfmsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, 
i32)
+DEF_HELPER_FLAGS_6(vfmsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, 
i32)
+DEF_HELPER_FLAGS_6(vfnmadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, 
i32)
+DEF_HELPER_FLAGS_6(vfnmadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, 
i32)
+DEF_HELPER_FLAGS_6(vfnmsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, 
i32)
+DEF_HELPER_FLAGS_6(vfnmsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, 
i32)
 
 DEF_HELPER_4(vfmax_s, void, env, i32, i32, i32)
 DEF_HELPER_4(vfmax_d, void, env, i32, i32, i32)
diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c
index 73f0974744..3a7a620227 100644
--- a/target/loongarch/vec_helper.c
+++ b/target/loongarch/vec_helper.c
@@ -2129,14 +2129,14 @@ DO_3OP_F(vfmina_s, 32, UW, float32_minnummag)
 DO_3OP_F(vfmina_d, 64, UD, float64_minnummag)
 
 #define DO_4OP_F(NAME, BIT, E, FN, flags)\
-void HELPER(NAME)(CPULoongArchState *env,\
-  uint32_t vd, uint32_t vj, uint32_t vk, uint32_t va)\
+void HELPER(NAME)(void *vd, void *vj, void *vk, void *va,\
+  CPULoongArchState *env, uint32_t desc) \
 {\
 int i;   \
-VReg *Vd = &(env->fpr[vd].vreg); \
-VReg *Vj = &(env->fpr[vj].vreg); \
-VReg *Vk = &(env->fpr[vk].vreg); \
-VReg *Va = &(env->fpr[va].vreg); \
+VReg *Vd = (VReg *)vd;   \
+VReg *Vj = (VReg *)vj;   \
+VReg *Vk = (VReg *)vk;   \
+VReg *Va = (VReg *)va;   \
  \
 vec_clear_cause(env);\
 for (i = 0; i < LSX_LEN/BIT; i++) {  \
diff --git a/target/loongarch/insn_trans/trans_vec.c.inc 
b/target/loongarch/insn_trans/trans_vec.c.inc
index aeeb2df41c..85bc8670a7 100644
--- a/target/loongarch/insn_trans/trans_vec.c.inc
+++ b/target/loongarch/insn_trans/trans_vec.c.inc
@@ -15,6 +15,25 @@
 #define CHECK_SXE
 #endif
 
+static bool gen__ptr_vl(DisasContext *ctx, arg_ *a, uint32_t oprsz,
+gen_helper_gvec_4_ptr *fn)
+{
+tcg_gen_gvec_4_ptr(vec_full_offset(a->vd),
+   vec_full_offset(a->vj),
+   vec_full_offset(a->vk),
+   vec_full_offset(a->va),
+   cpu_env,
+   oprsz, ctx->vl / 8, oprsz, fn);
+return true;
+}
+
+static bool gen__ptr(DisasContext *ctx, arg_ *a,
+ gen_helper_gvec_4_ptr *fn)
+{
+CHECK_SXE;
+return gen__ptr_vl(ctx, a, 16, fn);
+}
+
 static bool gen_(DisasContext *ctx, arg_ *a,
  void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32,
   TCGv_i32, TCGv_i32))
@@ -3634,14 +3653,14 @@ TRANS(vfmul_d, LSX, gen_vvv, gen_helper_vfmul_d)
 TRANS(vfdiv_s, LSX, gen_vvv, gen_helper_vfdiv_s)
 TRANS(vfdiv_d, LSX, gen_vvv, gen_helper_vfdiv_d)
 
-TRANS(vfmadd_s, LSX, gen_, gen_helper_vfmadd_s)
-TRANS(vfmadd_d, LSX, gen_, gen_helper_vfmadd_d)
-TRANS(vfmsub_s, LSX, gen_, gen_helper_vfmsub_s)