[Qemu-devel] [RFC qom-cpu 17/41] cpu: Move tlb_flush_{addr, mask} fields from CPU_COMMON_TLB to CPUState
Change their type to vaddr but keep comparing target_ulongs for now.
Signed-off-by: Andreas Färber afaer...@suse.de
---
cputlb.c| 27 ++-
include/exec/cpu-defs.h | 2 --
include/qom/cpu.h | 3 +++
3 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index e8131d8..e02663c 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -74,8 +74,8 @@ void tlb_flush(CPUArchState *env, int flush_global)
memset(cpu-tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof(void *));
-env-tlb_flush_addr = -1;
-env-tlb_flush_mask = 0;
+cpu-tlb_flush_addr = -1;
+cpu-tlb_flush_mask = 0;
tlb_flush_count++;
}
@@ -101,11 +101,11 @@ void tlb_flush_page(CPUArchState *env, target_ulong addr)
printf(tlb_flush_page: TARGET_FMT_lx \n, addr);
#endif
/* Check if we need to flush due to large pages. */
-if ((addr env-tlb_flush_mask) == env-tlb_flush_addr) {
+if ((addr cpu-tlb_flush_mask) == cpu-tlb_flush_addr) {
#if defined(DEBUG_TLB)
-printf(tlb_flush_page: forced full flush (
- TARGET_FMT_lx / TARGET_FMT_lx )\n,
- env-tlb_flush_addr, env-tlb_flush_mask);
+printf(tlb_flush_page: forced full flush (%
+ VADDR_PRIx /% VADDR_PRIx )\n,
+ cpu-tlb_flush_addr, cpu-tlb_flush_mask);
#endif
tlb_flush(env, 1);
return;
@@ -215,22 +215,23 @@ void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
target_ulong size)
{
+CPUState *cpu = ENV_GET_CPU(env);
target_ulong mask = ~(size - 1);
-if (env-tlb_flush_addr == (target_ulong)-1) {
-env-tlb_flush_addr = vaddr mask;
-env-tlb_flush_mask = mask;
+if ((target_ulong)cpu-tlb_flush_addr == (target_ulong)-1) {
+cpu-tlb_flush_addr = vaddr mask;
+cpu-tlb_flush_mask = mask;
return;
}
/* Extend the existing region to include the new page.
This is a compromise between unnecessary flushes and the cost
of maintaining a full variable size TLB. */
-mask = env-tlb_flush_mask;
-while (((env-tlb_flush_addr ^ vaddr) mask) != 0) {
+mask = cpu-tlb_flush_mask;
+while (((cpu-tlb_flush_addr ^ vaddr) mask) != 0) {
mask = 1;
}
-env-tlb_flush_addr = mask;
-env-tlb_flush_mask = mask;
+cpu-tlb_flush_addr = mask;
+cpu-tlb_flush_mask = mask;
}
/* Add a new TLB entry. At most one entry for a given virtual address
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index d090594..460f7cf 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -103,8 +103,6 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1
CPU_TLB_ENTRY_BITS));
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
-target_ulong tlb_flush_addr;\
-target_ulong tlb_flush_mask;
#else
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index fc3d345..5349805 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -252,6 +252,9 @@ struct CPUState {
void *opaque;
+vaddr tlb_flush_addr;
+vaddr tlb_flush_mask;
+
/* In order to avoid passing too many arguments to the MMIO helpers,
* we store some rarely used information in the CPU context.
*/
--
1.8.1.4
[Qemu-devel] [RFC qom-cpu 19/41] cpu-exec: Change cpu_loop_exit() argument to CPUState
Signed-off-by: Andreas Färber afaer...@suse.de
---
cpu-exec.c| 14 ++
exec.c| 2 +-
include/exec/exec-all.h | 2 +-
target-alpha/helper.c | 4 ++--
target-alpha/mem_helper.c | 4 ++--
target-arm/op_helper.c| 6 +++---
target-cris/op_helper.c | 4 ++--
target-i386/excp_helper.c | 2 +-
target-i386/misc_helper.c | 4 ++--
target-i386/seg_helper.c | 2 +-
target-i386/svm_helper.c | 8
target-lm32/op_helper.c | 6 +++---
target-m68k/op_helper.c | 6 +++---
target-microblaze/op_helper.c | 4 ++--
target-mips/op_helper.c | 4 ++--
target-moxie/helper.c | 6 +++---
target-openrisc/exception.c | 2 +-
target-openrisc/mmu_helper.c | 2 +-
target-ppc/excp_helper.c | 2 +-
target-s390x/cc_helper.c | 2 +-
target-s390x/mem_helper.c | 6 +++---
target-s390x/misc_helper.c| 10 +-
target-sh4/op_helper.c| 4 ++--
target-sparc/helper.c | 6 +++---
target-sparc/ldst_helper.c| 2 +-
target-unicore32/op_helper.c | 4 ++--
target-xtensa/op_helper.c | 4 ++--
user-exec.c | 4 ++--
28 files changed, 62 insertions(+), 64 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 209380d..a1b8b96 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -23,10 +23,8 @@
#include qemu/atomic.h
#include sysemu/qtest.h
-void cpu_loop_exit(CPUArchState *env)
+void cpu_loop_exit(CPUState *cpu)
{
-CPUState *cpu = ENV_GET_CPU(env);
-
cpu-current_tb = NULL;
siglongjmp(cpu-jmp_env, 1);
}
@@ -305,7 +303,7 @@ int cpu_exec(CPUArchState *env)
if (interrupt_request CPU_INTERRUPT_DEBUG) {
cpu-interrupt_request = ~CPU_INTERRUPT_DEBUG;
cpu-exception_index = EXCP_DEBUG;
-cpu_loop_exit(env);
+cpu_loop_exit(cpu);
}
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
@@ -314,7 +312,7 @@ int cpu_exec(CPUArchState *env)
cpu-interrupt_request = ~CPU_INTERRUPT_HALT;
cpu-halted = 1;
cpu-exception_index = EXCP_HLT;
-cpu_loop_exit(env);
+cpu_loop_exit(cpu);
}
#endif
#if defined(TARGET_I386)
@@ -329,7 +327,7 @@ int cpu_exec(CPUArchState *env)
0);
do_cpu_init(x86_env_get_cpu(env));
cpu-exception_index = EXCP_HALTED;
-cpu_loop_exit(env);
+cpu_loop_exit(cpu);
} else if (interrupt_request CPU_INTERRUPT_SIPI) {
do_cpu_sipi(x86_env_get_cpu(env));
} else if (env-hflags2 HF2_GIF_MASK) {
@@ -578,7 +576,7 @@ int cpu_exec(CPUArchState *env)
if (unlikely(cpu-exit_request)) {
cpu-exit_request = 0;
cpu-exception_index = EXCP_INTERRUPT;
-cpu_loop_exit(env);
+cpu_loop_exit(cpu);
}
#if defined(DEBUG_DISAS)
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
@@ -665,7 +663,7 @@ int cpu_exec(CPUArchState *env)
}
cpu-exception_index = EXCP_INTERRUPT;
next_tb = 0;
-cpu_loop_exit(env);
+cpu_loop_exit(cpu);
}
break;
}
diff --git a/exec.c b/exec.c
index 6ae5a21..06fb881 100644
--- a/exec.c
+++ b/exec.c
@@ -1483,7 +1483,7 @@ static void check_watchpoint(int offset, int len_mask,
int flags)
tb_check_watchpoint(env);
if (wp-flags BP_STOP_BEFORE_ACCESS) {
cpu-exception_index = EXCP_DEBUG;
-cpu_loop_exit(env);
+cpu_loop_exit(cpu);
} else {
cc-get_tb_cpu_state(cpu, pc, cs_base, cpu_flags);
tb_gen_code(env, pc, cs_base, cpu_flags, 1);
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 4429924..f6b9eac 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -88,7 +88,7 @@ TranslationBlock *tb_gen_code(CPUArchState *env,
target_ulong pc, target_ulong cs_base, int flags,
int cflags);
void cpu_exec_init(CPUArchState *env);
-void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1);
+void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
void tb_invalidate_phys_page_range(tb_page_addr_t start
[Qemu-devel] [RFC qom-cpu 22/41] translate-all: Change tb_check_watchpoint() argument to CPUState
Signed-off-by: Andreas Färber afaer...@suse.de
---
exec.c | 2 +-
translate-all.c | 4 ++--
translate-all.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/exec.c b/exec.c
index 06fb881..0a81967 100644
--- a/exec.c
+++ b/exec.c
@@ -1480,7 +1480,7 @@ static void check_watchpoint(int offset, int len_mask,
int flags)
wp-flags |= BP_WATCHPOINT_HIT;
if (!cpu-watchpoint_hit) {
cpu-watchpoint_hit = wp;
-tb_check_watchpoint(env);
+tb_check_watchpoint(cpu);
if (wp-flags BP_STOP_BEFORE_ACCESS) {
cpu-exception_index = EXCP_DEBUG;
cpu_loop_exit(cpu);
diff --git a/translate-all.c b/translate-all.c
index 0dd6a60..22a5b80 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1384,9 +1384,9 @@ void tb_invalidate_phys_addr(hwaddr addr)
}
#endif /* TARGET_HAS_ICE !defined(CONFIG_USER_ONLY) */
-void tb_check_watchpoint(CPUArchState *env)
+void tb_check_watchpoint(CPUState *cpu)
{
-CPUState *cpu = ENV_GET_CPU(env);
+CPUArchState *env = cpu-env_ptr;
TranslationBlock *tb;
tb = tb_find_pc(cpu-mem_io_pc);
diff --git a/translate-all.h b/translate-all.h
index 5c38819..78e88d3 100644
--- a/translate-all.h
+++ b/translate-all.h
@@ -29,6 +29,6 @@
/* translate-all.c */
void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len);
void cpu_unlink_tb(CPUState *cpu);
-void tb_check_watchpoint(CPUArchState *env);
+void tb_check_watchpoint(CPUState *cpu);
#endif /* TRANSLATE_ALL_H */
--
1.8.1.4
[Qemu-devel] [RFC qom-cpu 21/41] translate-all: Change cpu_restore_state_from_tb() argument to CPUState
And normalize the argument order.
Signed-off-by: Andreas Färber afaer...@suse.de
---
translate-all.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/translate-all.c b/translate-all.c
index 5673420..0dd6a60 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -193,10 +193,10 @@ int cpu_gen_code(CPUArchState *env, TranslationBlock *tb,
int *gen_code_size_ptr
/* The cpu state corresponding to 'searched_pc' is restored.
*/
-static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env,
+static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
uintptr_t searched_pc)
{
-CPUState *cpu = ENV_GET_CPU(env);
+CPUArchState *env = cpu-env_ptr;
TCGContext *s = tcg_ctx;
int j;
uintptr_t tc_ptr;
@@ -251,12 +251,11 @@ static int cpu_restore_state_from_tb(TranslationBlock
*tb, CPUArchState *env,
bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
{
-CPUArchState *env = cpu-env_ptr;
TranslationBlock *tb;
tb = tb_find_pc(retaddr);
if (tb) {
-cpu_restore_state_from_tb(tb, env, retaddr);
+cpu_restore_state_from_tb(cpu, tb, retaddr);
return true;
}
return false;
@@ -1074,7 +1073,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start,
tb_page_addr_t end,
restore the CPU state */
current_tb_modified = 1;
-cpu_restore_state_from_tb(current_tb, env, cpu-mem_io_pc);
+cpu_restore_state_from_tb(cpu, current_tb, cpu-mem_io_pc);
cc-get_tb_cpu_state(cpu, current_pc, current_cs_base,
current_flags);
}
@@ -1195,7 +1194,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
restore the CPU state */
current_tb_modified = 1;
-cpu_restore_state_from_tb(current_tb, env, pc);
+cpu_restore_state_from_tb(cpu, current_tb, pc);
cc-get_tb_cpu_state(cpu, current_pc, current_cs_base,
current_flags);
}
@@ -1395,7 +1394,7 @@ void tb_check_watchpoint(CPUArchState *env)
cpu_abort(env, check_watchpoint: could not find TB for pc=%p,
(void *)cpu-mem_io_pc);
}
-cpu_restore_state_from_tb(tb, env, cpu-mem_io_pc);
+cpu_restore_state_from_tb(cpu, tb, cpu-mem_io_pc);
tb_phys_invalidate(tb, -1);
}
@@ -1447,7 +1446,7 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t
retaddr)
(void *)retaddr);
}
n = cpu-icount_decr.u16.low + tb-icount;
-cpu_restore_state_from_tb(tb, env, retaddr);
+cpu_restore_state_from_tb(cpu, tb, retaddr);
/* Calculate how many instructions had been executed before the fault
occurred. */
n = n - cpu-icount_decr.u16.low;
--
1.8.1.4
[Qemu-devel] [RFC qom-cpu 18/41] exec: Change tlb_fill() argument to CPUState
Signed-off-by: Andreas Färber afaer...@suse.de
---
include/exec/exec-all.h | 2 +-
include/exec/softmmu_template.h | 4 ++--
target-alpha/mem_helper.c | 8 +---
target-arm/op_helper.c | 12 +++-
target-cris/op_helper.c | 7 ---
target-i386/mem_helper.c| 12 +++-
target-lm32/op_helper.c | 13 -
target-m68k/op_helper.c | 8 +---
target-microblaze/op_helper.c | 13 -
target-mips/op_helper.c | 7 ---
target-moxie/helper.c | 7 ---
target-openrisc/mmu_helper.c| 8 +---
target-ppc/mmu_helper.c | 9 +
target-s390x/mem_helper.c | 8 +---
target-sh4/op_helper.c | 8 +---
target-sparc/ldst_helper.c | 8 +---
target-unicore32/op_helper.c| 8 +---
target-xtensa/op_helper.c | 6 --
18 files changed, 89 insertions(+), 59 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index e61b3f1..4429924 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -374,7 +374,7 @@ bool io_mem_read(struct MemoryRegion *mr, hwaddr addr,
bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
uint64_t value, unsigned size);
-void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr);
uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index bbfda31..8dc0901 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -114,7 +114,7 @@ glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)(CPUArchState
*env,
do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
}
#endif
-tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
+tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
tlb_addr = env-tlb_table[mmu_idx][index].ADDR_READ;
}
@@ -230,7 +230,7 @@ glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(CPUArchState
*env,
do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
}
#endif
-tlb_fill(env, addr, 1, mmu_idx, retaddr);
+tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
tlb_addr = env-tlb_table[mmu_idx][index].addr_write;
}
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 22fcbe1..c6c0182 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -144,14 +144,16 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr
addr,
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUAlphaState *env, target_ulong addr, int is_write,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
{
-AlphaCPU *cpu = alpha_env_get_cpu(env);
int ret;
-ret = alpha_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ret = alpha_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
+AlphaCPU *cpu = ALPHA_CPU(cs);
+CPUAlphaState *env = cpu-env;
+
if (retaddr) {
cpu_restore_state(env, retaddr);
}
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 2c2b3b7..d05f522 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -72,17 +72,19 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg,
uint32_t def,
#include exec/softmmu_template.h
/* try to fill the TLB and return an exception if error. If retaddr is
- NULL, it means that the function was called in C code (i.e. not
- from generated code or from helper.c) */
-void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
+ * NULL, it means that the function was called in C code (i.e. not
+ * from generated code or from helper.c)
+ */
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
-ARMCPU *cpu = arm_env_get_cpu(env);
-CPUState *cs = CPU(cpu);
int ret;
ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
+ARMCPU *cpu = ARM_CPU(cs);
+CPUARMState *env = cpu-env;
+
if (retaddr) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index 9b20b94..68a5caa 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -54,15 +54,16 @@
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-void tlb_fill
[Qemu-devel] [RFC qom-cpu 28/41] exec: Change cpu_breakpoint_{insert, remove{, _by_ref, _all}} argument
Use CPUState. Allows to clean up CPUArchState in gdbstub.
Signed-off-by: Andreas Färber afaer...@suse.de
---
exec.c | 20
gdbstub.c | 20
include/exec/cpu-all.h | 15 ---
include/qom/cpu.h | 15 +++
linux-user/main.c | 2 +-
target-i386/cpu.c | 2 +-
target-i386/helper.c | 4 ++--
target-i386/machine.c | 2 +-
8 files changed, 36 insertions(+), 44 deletions(-)
diff --git a/exec.c b/exec.c
index cfd0ecb..7ea864a 100644
--- a/exec.c
+++ b/exec.c
@@ -507,11 +507,10 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
#endif
/* Add a breakpoint. */
-int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
+int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
CPUBreakpoint **breakpoint)
{
#if defined(TARGET_HAS_ICE)
-CPUState *cpu = ENV_GET_CPU(env);
CPUBreakpoint *bp;
bp = g_malloc(sizeof(*bp));
@@ -538,15 +537,14 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong
pc, int flags,
}
/* Remove a specific breakpoint. */
-int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags)
+int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
{
#if defined(TARGET_HAS_ICE)
-CPUState *cpu = ENV_GET_CPU(env);
CPUBreakpoint *bp;
QTAILQ_FOREACH(bp, cpu-breakpoints, entry) {
if (bp-pc == pc bp-flags == flags) {
-cpu_breakpoint_remove_by_ref(env, bp);
+cpu_breakpoint_remove_by_ref(cpu, bp);
return 0;
}
}
@@ -557,11 +555,9 @@ int cpu_breakpoint_remove(CPUArchState *env, target_ulong
pc, int flags)
}
/* Remove a specific breakpoint by reference. */
-void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
+void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
{
#if defined(TARGET_HAS_ICE)
-CPUState *cpu = ENV_GET_CPU(env);
-
QTAILQ_REMOVE(cpu-breakpoints, breakpoint, entry);
breakpoint_invalidate(cpu, breakpoint-pc);
@@ -571,15 +567,15 @@ void cpu_breakpoint_remove_by_ref(CPUArchState *env,
CPUBreakpoint *breakpoint)
}
/* Remove all matching breakpoints. */
-void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
+void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
{
#if defined(TARGET_HAS_ICE)
-CPUState *cpu = ENV_GET_CPU(env);
CPUBreakpoint *bp, *next;
QTAILQ_FOREACH_SAFE(bp, cpu-breakpoints, entry, next) {
-if (bp-flags mask)
-cpu_breakpoint_remove_by_ref(env, bp);
+if (bp-flags mask) {
+cpu_breakpoint_remove_by_ref(cpu, bp);
+}
}
#endif
}
diff --git a/gdbstub.c b/gdbstub.c
index 1e0dea4..8bdefe2 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -638,7 +638,6 @@ static const int xlat_gdb_type[] = {
static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
{
CPUState *cpu;
-CPUArchState *env;
int err = 0;
if (kvm_enabled()) {
@@ -649,10 +648,10 @@ static int gdb_breakpoint_insert(target_ulong addr,
target_ulong len, int type)
case GDB_BREAKPOINT_SW:
case GDB_BREAKPOINT_HW:
CPU_FOREACH(cpu) {
-env = cpu-env_ptr;
-err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
-if (err)
+err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL);
+if (err) {
break;
+}
}
return err;
#ifndef CONFIG_USER_ONLY
@@ -675,7 +674,6 @@ static int gdb_breakpoint_insert(target_ulong addr,
target_ulong len, int type)
static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
{
CPUState *cpu;
-CPUArchState *env;
int err = 0;
if (kvm_enabled()) {
@@ -686,10 +684,10 @@ static int gdb_breakpoint_remove(target_ulong addr,
target_ulong len, int type)
case GDB_BREAKPOINT_SW:
case GDB_BREAKPOINT_HW:
CPU_FOREACH(cpu) {
-env = cpu-env_ptr;
-err = cpu_breakpoint_remove(env, addr, BP_GDB);
-if (err)
+err = cpu_breakpoint_remove(cpu, addr, BP_GDB);
+if (err) {
break;
+}
}
return err;
#ifndef CONFIG_USER_ONLY
@@ -711,7 +709,6 @@ static int gdb_breakpoint_remove(target_ulong addr,
target_ulong len, int type)
static void gdb_breakpoint_remove_all(void)
{
CPUState *cpu;
-CPUArchState *env;
if (kvm_enabled()) {
kvm_remove_all_breakpoints(gdbserver_state-c_cpu);
@@ -719,8 +716,7 @@ static void gdb_breakpoint_remove_all(void)
}
CPU_FOREACH(cpu) {
-env = cpu-env_ptr;
-cpu_breakpoint_remove_all(env, BP_GDB);
+cpu_breakpoint_remove_all(cpu, BP_GDB);
#ifndef CONFIG_USER_ONLY
cpu_watchpoint_remove_all(cpu, BP_GDB);
#endif
@@ -1604,7 +1600,7 @@ void gdbserver_fork(CPUArchState *env)
}
close(s-fd);
s
[Qemu-devel] [RFC qom-cpu 26/41] target-ppc: Use PowerPCCPU in PowerPCCPUClass::handle_mmu_fault hook
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-ppc/cpu-qom.h| 8 +---
target-ppc/mmu-hash32.c | 5 +++--
target-ppc/mmu-hash32.h | 2 +-
target-ppc/mmu-hash64.c | 5 +++--
target-ppc/mmu-hash64.h | 2 +-
target-ppc/mmu_helper.c | 2 +-
6 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index f3c710a..c213589 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -38,6 +38,8 @@
#define POWERPC_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
+typedef struct PowerPCCPU PowerPCCPU;
+
/**
* PowerPCCPUClass:
* @parent_realize: The parent class' realize handler.
@@ -70,7 +72,7 @@ typedef struct PowerPCCPUClass {
void (*init_proc)(CPUPPCState *env);
int (*check_pow)(CPUPPCState *env);
#if defined(CONFIG_SOFTMMU)
-int (*handle_mmu_fault)(CPUPPCState *env, target_ulong eaddr, int rwx,
+int (*handle_mmu_fault)(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
int mmu_idx);
#endif
} PowerPCCPUClass;
@@ -81,13 +83,13 @@ typedef struct PowerPCCPUClass {
*
* A PowerPC CPU.
*/
-typedef struct PowerPCCPU {
+struct PowerPCCPU {
/* private */
CPUState parent_obj;
/* public */
CPUPPCState env;
-} PowerPCCPU;
+};
static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
{
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index aa87084..6a4d6a8 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -381,10 +381,11 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr,
ppc_hash_pte32_t pte,
return (rpn ~mask) | (eaddr mask);
}
-int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
+int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
int mmu_idx)
{
-CPUState *cs = CPU(ppc_env_get_cpu(env));
+CPUState *cs = CPU(cpu);
+CPUPPCState *env = cpu-env;
target_ulong sr;
hwaddr pte_offset;
ppc_hash_pte32_t pte;
diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h
index 884786b..4a49ceb 100644
--- a/target-ppc/mmu-hash32.h
+++ b/target-ppc/mmu-hash32.h
@@ -5,7 +5,7 @@
hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash);
hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
-int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
+int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw,
int mmu_idx);
/*
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 04dcfb3..82bfa7c 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -396,10 +396,11 @@ static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb,
ppc_hash_pte64_t pte,
return (rpn ~mask) | (eaddr mask);
}
-int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
+int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
int rwx, int mmu_idx)
{
-CPUState *cs = CPU(ppc_env_get_cpu(env));
+CPUState *cs = CPU(cpu);
+CPUPPCState *env = cpu-env;
ppc_slb_t *slb;
hwaddr pte_offset;
ppc_hash_pte64_t pte;
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 55f5a23..41b0ac4 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -7,7 +7,7 @@
void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
-int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
+int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw,
int mmu_idx);
#endif
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index e214316..5a237ce 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -2901,7 +2901,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
is_write, int mmu_idx,
int ret;
if (pcc-handle_mmu_fault) {
-ret = pcc-handle_mmu_fault(env, addr, is_write, mmu_idx);
+ret = pcc-handle_mmu_fault(cpu, addr, is_write, mmu_idx);
} else {
ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx);
}
--
1.8.1.4
[Qemu-devel] [RFC qom-cpu 37/41] target-microblaze: Replace DisasContext::env field with MicroBlazeCPU
This cleans up some mb_env_get_cpu() needed for cpu_abort().
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-microblaze/translate.c | 84 +--
1 file changed, 40 insertions(+), 44 deletions(-)
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 4471f5a..611ed82 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -54,7 +54,7 @@ static TCGv env_iflags;
/* This is the state at translation time. */
typedef struct DisasContext {
-CPUMBState *env;
+MicroBlazeCPU *cpu;
target_ulong pc;
/* Decoder. */
@@ -321,8 +321,8 @@ static void dec_pattern(DisasContext *dc)
int l1;
if ((dc-tb_flags MSR_EE_FLAG)
- (dc-env-pvr.regs[2] PVR2_ILL_OPCODE_EXC_MASK)
- !((dc-env-pvr.regs[2] PVR2_USE_PCMP_INSTR))) {
+ (dc-cpu-env.pvr.regs[2] PVR2_ILL_OPCODE_EXC_MASK)
+ !((dc-cpu-env.pvr.regs[2] PVR2_USE_PCMP_INSTR))) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
@@ -364,7 +364,7 @@ static void dec_pattern(DisasContext *dc)
}
break;
default:
-cpu_abort(CPU(mb_env_get_cpu(dc-env)),
+cpu_abort(CPU(dc-cpu),
unsupported pattern insn opcode=%x\n, dc-opcode);
break;
}
@@ -438,8 +438,7 @@ static inline void msr_write(DisasContext *dc, TCGv v)
static void dec_msr(DisasContext *dc)
{
-MicroBlazeCPU *cpu = mb_env_get_cpu(dc-env);
-CPUState *cs = CPU(cpu);
+CPUState *cs = CPU(dc-cpu);
TCGv t0, t1;
unsigned int sr, to, rn;
int mem_index = cpu_mmu_index(cs);
@@ -457,7 +456,7 @@ static void dec_msr(DisasContext *dc)
LOG_DIS(msr%s r%d imm=%x\n, clr ? clr : set,
dc-rd, dc-imm);
-if (!(dc-env-pvr.regs[2] PVR2_USE_MSR_INSTR)) {
+if (!(dc-cpu-env.pvr.regs[2] PVR2_USE_MSR_INSTR)) {
/* nop??? */
return;
}
@@ -536,7 +535,7 @@ static void dec_msr(DisasContext *dc)
tcg_gen_st_tl(cpu_R[dc-ra], cpu_env, offsetof(CPUMBState,
shr));
break;
default:
-cpu_abort(CPU(mb_env_get_cpu(dc-env)), unknown mts reg
%x\n, sr);
+cpu_abort(CPU(dc-cpu), unknown mts reg %x\n, sr);
break;
}
} else {
@@ -642,8 +641,8 @@ static void dec_mul(DisasContext *dc)
unsigned int subcode;
if ((dc-tb_flags MSR_EE_FLAG)
- (dc-env-pvr.regs[2] PVR2_ILL_OPCODE_EXC_MASK)
- !(dc-env-pvr.regs[0] PVR0_USE_HW_MUL_MASK)) {
+ (dc-cpu-env.pvr.regs[2] PVR2_ILL_OPCODE_EXC_MASK)
+ !(dc-cpu-env.pvr.regs[0] PVR0_USE_HW_MUL_MASK)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
@@ -661,7 +660,7 @@ static void dec_mul(DisasContext *dc)
/* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is 2. */
if (subcode = 1 subcode = 3
- !((dc-env-pvr.regs[2] PVR2_USE_MUL64_MASK))) {
+ !((dc-cpu-env.pvr.regs[2] PVR2_USE_MUL64_MASK))) {
/* nop??? */
}
@@ -683,7 +682,7 @@ static void dec_mul(DisasContext *dc)
t_gen_mulu(d[0], cpu_R[dc-rd], cpu_R[dc-ra], cpu_R[dc-rb]);
break;
default:
-cpu_abort(CPU(mb_env_get_cpu(dc-env)), unknown MUL insn %x\n,
subcode);
+cpu_abort(CPU(dc-cpu), unknown MUL insn %x\n, subcode);
break;
}
done:
@@ -699,8 +698,8 @@ static void dec_div(DisasContext *dc)
u = dc-imm 2;
LOG_DIS(div\n);
-if ((dc-env-pvr.regs[2] PVR2_ILL_OPCODE_EXC_MASK)
- !((dc-env-pvr.regs[0] PVR0_USE_DIV_MASK))) {
+if ((dc-cpu-env.pvr.regs[2] PVR2_ILL_OPCODE_EXC_MASK)
+ !((dc-cpu-env.pvr.regs[0] PVR0_USE_DIV_MASK))) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
@@ -721,8 +720,8 @@ static void dec_barrel(DisasContext *dc)
unsigned int s, t;
if ((dc-tb_flags MSR_EE_FLAG)
- (dc-env-pvr.regs[2] PVR2_ILL_OPCODE_EXC_MASK)
- !(dc-env-pvr.regs[0] PVR0_USE_BARREL_MASK)) {
+ (dc-cpu-env.pvr.regs[2] PVR2_ILL_OPCODE_EXC_MASK)
+ !(dc-cpu-env.pvr.regs[0] PVR0_USE_BARREL_MASK)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
@@ -751,8 +750,7 @@ static void dec_barrel(DisasContext *dc)
static void dec_bit(DisasContext *dc)
{
-MicroBlazeCPU *cpu = mb_env_get_cpu(dc-env);
-CPUState *cs = CPU(cpu);
+CPUState *cs = CPU(dc-cpu);
TCGv t0, t1;
unsigned int op;
int mem_index = cpu_mmu_index(cs);
@@ -830,12 +828,12 @@ static void dec_bit(DisasContext *dc)
break;
case 0xe0:
if ((dc-tb_flags
[Qemu-devel] [RFC qom-cpu 24/41] translate-all: Change tb_gen_code() argument to CPUState
Signed-off-by: Andreas Färber afaer...@suse.de
---
cpu-exec.c | 4 ++--
exec.c | 2 +-
hw/i386/kvmvapic.c | 2 +-
include/exec/exec-all.h | 2 +-
translate-all.c | 9 +
5 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index a1b8b96..a984b7c 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -85,7 +85,7 @@ static void cpu_exec_nocache(CPUArchState *env, int
max_cycles,
if (max_cycles CF_COUNT_MASK)
max_cycles = CF_COUNT_MASK;
-tb = tb_gen_code(env, orig_tb-pc, orig_tb-cs_base, orig_tb-flags,
+tb = tb_gen_code(cpu, orig_tb-pc, orig_tb-cs_base, orig_tb-flags,
max_cycles);
cpu-current_tb = tb;
/* execute the generated code */
@@ -138,7 +138,7 @@ static TranslationBlock *tb_find_slow(CPUArchState *env,
}
not_found:
/* if no translated code available, then translate it now */
-tb = tb_gen_code(env, pc, cs_base, flags, 0);
+tb = tb_gen_code(cpu, pc, cs_base, flags, 0);
found:
/* Move the last found TB to the head of the list */
diff --git a/exec.c b/exec.c
index 0a81967..1b5a0cd 100644
--- a/exec.c
+++ b/exec.c
@@ -1486,7 +1486,7 @@ static void check_watchpoint(int offset, int len_mask,
int flags)
cpu_loop_exit(cpu);
} else {
cc-get_tb_cpu_state(cpu, pc, cs_base, cpu_flags);
-tb_gen_code(env, pc, cs_base, cpu_flags, 1);
+tb_gen_code(cpu, pc, cs_base, cpu_flags, 1);
cpu_resume_from_signal(env, NULL);
}
}
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 5757a1b..bcf8d9d 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -450,7 +450,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU
*cpu, target_ulong ip)
if (!kvm_enabled()) {
cs-current_tb = NULL;
-tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
+tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1);
cpu_resume_from_signal(env, NULL);
}
}
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 40d5931..73abf9e 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -84,7 +84,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
-TranslationBlock *tb_gen_code(CPUArchState *env,
+TranslationBlock *tb_gen_code(CPUState *cpu,
target_ulong pc, target_ulong cs_base, int flags,
int cflags);
void cpu_exec_init(CPUArchState *env);
diff --git a/translate-all.c b/translate-all.c
index 1158681..6e5bfee 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -933,10 +933,11 @@ static void build_page_bitmap(PageDesc *p)
}
}
-TranslationBlock *tb_gen_code(CPUArchState *env,
+TranslationBlock *tb_gen_code(CPUState *cpu,
target_ulong pc, target_ulong cs_base,
int flags, int cflags)
{
+CPUArchState *env = cpu-env_ptr;
TranslationBlock *tb;
uint8_t *tc_ptr;
tb_page_addr_t phys_pc, phys_page2;
@@ -1110,7 +,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start,
tb_page_addr_t end,
modifying the memory. It will ensure that it cannot modify
itself */
cpu-current_tb = NULL;
-tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
+tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
cpu_resume_from_signal(env, NULL);
}
#endif
@@ -1209,7 +1210,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
modifying the memory. It will ensure that it cannot modify
itself */
cpu-current_tb = NULL;
-tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
+tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
if (locked) {
mmap_unlock();
}
@@ -1482,7 +1483,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
tb_phys_invalidate(tb, -1);
/* FIXME: In theory this could raise an exception. In practice
we have already translated the block once so it's probably ok. */
-tb_gen_code(env, pc, cs_base, flags, cflags);
+tb_gen_code(cpu, pc, cs_base, flags, cflags);
/* TODO: If env-pc != tb-pc (i.e. the faulting instruction was not
the first in the TB) then we end up generating a whole new TB and
repeating the fault, which is horribly inefficient.
--
1.8.1.4
[Qemu-devel] [RFC qom-cpu 27/41] exec: Change cpu_watchpoint_{insert, remove{, _by_ref, _all}} argument
Use CPUState. This lets us drop a few local env usages.
Signed-off-by: Andreas Färber afaer...@suse.de
---
exec.c| 34 +-
gdbstub.c | 17 +
include/exec/cpu-all.h| 6 --
include/qom/cpu.h | 7 +++
linux-user/main.c | 5 +++--
target-i386/cpu.c | 2 +-
target-i386/helper.c | 11 ---
target-i386/machine.c | 3 ++-
target-xtensa/op_helper.c | 9 ++---
9 files changed, 53 insertions(+), 41 deletions(-)
diff --git a/exec.c b/exec.c
index 1b5a0cd..cfd0ecb 100644
--- a/exec.c
+++ b/exec.c
@@ -35,6 +35,7 @@
#include hw/xen/xen.h
#include qemu/timer.h
#include qemu/config-file.h
+#include qemu/error-report.h
#include exec/memory.h
#include sysemu/dma.h
#include exec/address-spaces.h
@@ -417,30 +418,30 @@ static void breakpoint_invalidate(CPUState *cpu,
target_ulong pc)
#endif /* TARGET_HAS_ICE */
#if defined(CONFIG_USER_ONLY)
-void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
+void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
{
}
-int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong
len,
+int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
int flags, CPUWatchpoint **watchpoint)
{
return -ENOSYS;
}
#else
/* Add a watchpoint. */
-int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong
len,
+int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
int flags, CPUWatchpoint **watchpoint)
{
-CPUState *cpu = ENV_GET_CPU(env);
-target_ulong len_mask = ~(len - 1);
+CPUArchState *env = cpu-env_ptr;
+vaddr len_mask = ~(len - 1);
CPUWatchpoint *wp;
/* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
if ((len (len - 1)) || (addr ~len_mask) ||
len == 0 || len TARGET_PAGE_SIZE) {
-fprintf(stderr, qemu: tried to set invalid watchpoint at
-TARGET_FMT_lx , len= TARGET_FMT_lu \n, addr, len);
+error_report(tried to set invalid watchpoint at %
+ VADDR_PRIx , len=% VADDR_PRIu, addr, len);
return -EINVAL;
}
wp = g_malloc(sizeof(*wp));
@@ -464,17 +465,16 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong
addr, target_ulong len
}
/* Remove a specific watchpoint. */
-int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong
len,
+int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
int flags)
{
-CPUState *cpu = ENV_GET_CPU(env);
-target_ulong len_mask = ~(len - 1);
+vaddr len_mask = ~(len - 1);
CPUWatchpoint *wp;
QTAILQ_FOREACH(wp, cpu-watchpoints, entry) {
if (addr == wp-vaddr len_mask == wp-len_mask
flags == (wp-flags ~BP_WATCHPOINT_HIT)) {
-cpu_watchpoint_remove_by_ref(env, wp);
+cpu_watchpoint_remove_by_ref(cpu, wp);
return 0;
}
}
@@ -482,9 +482,9 @@ int cpu_watchpoint_remove(CPUArchState *env, target_ulong
addr, target_ulong len
}
/* Remove a specific watchpoint by reference. */
-void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint)
+void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
{
-CPUState *cpu = ENV_GET_CPU(env);
+CPUArchState *env = cpu-env_ptr;
QTAILQ_REMOVE(cpu-watchpoints, watchpoint, entry);
@@ -494,14 +494,14 @@ void cpu_watchpoint_remove_by_ref(CPUArchState *env,
CPUWatchpoint *watchpoint)
}
/* Remove all matching watchpoints. */
-void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
+void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
{
-CPUState *cpu = ENV_GET_CPU(env);
CPUWatchpoint *wp, *next;
QTAILQ_FOREACH_SAFE(wp, cpu-watchpoints, entry, next) {
-if (wp-flags mask)
-cpu_watchpoint_remove_by_ref(env, wp);
+if (wp-flags mask) {
+cpu_watchpoint_remove_by_ref(cpu, wp);
+}
}
}
#endif
diff --git a/gdbstub.c b/gdbstub.c
index 05b76e0..1e0dea4 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -660,8 +660,7 @@ static int gdb_breakpoint_insert(target_ulong addr,
target_ulong len, int type)
case GDB_WATCHPOINT_READ:
case GDB_WATCHPOINT_ACCESS:
CPU_FOREACH(cpu) {
-env = cpu-env_ptr;
-err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
+err = cpu_watchpoint_insert(cpu, addr, len, xlat_gdb_type[type],
NULL);
if (err)
break;
@@ -698,8 +697,7 @@ static int gdb_breakpoint_remove(target_ulong addr,
target_ulong len, int type)
case GDB_WATCHPOINT_READ:
case GDB_WATCHPOINT_ACCESS:
CPU_FOREACH(cpu) {
-env = cpu-env_ptr;
-err = cpu_watchpoint_remove(env, addr, len
[Qemu-devel] [RFC qom-cpu 31/41] exec: Change memory_region_section_get_iotlb() argument to CPUState
It no longer needs CPUArchState since moving watchpoints to CPUState.
Signed-off-by: Andreas Färber afaer...@suse.de
---
cputlb.c | 3 ++-
exec.c| 3 +--
include/exec/cputlb.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index bd5cf0e..e5b6145 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -241,6 +241,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size)
{
+CPUState *cpu = ENV_GET_CPU(env);
MemoryRegionSection *section;
unsigned int index;
target_ulong address;
@@ -276,7 +277,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
}
code_address = address;
-iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, xlat,
+iotlb = memory_region_section_get_iotlb(cpu, section, vaddr, paddr, xlat,
prot, address);
index = (vaddr TARGET_PAGE_BITS) (CPU_TLB_SIZE - 1);
diff --git a/exec.c b/exec.c
index 5f133e4..ffbf4c3 100644
--- a/exec.c
+++ b/exec.c
@@ -677,14 +677,13 @@ static int cpu_physical_memory_set_dirty_tracking(int
enable)
return ret;
}
-hwaddr memory_region_section_get_iotlb(CPUArchState *env,
+hwaddr memory_region_section_get_iotlb(CPUState *cpu,
MemoryRegionSection *section,
target_ulong vaddr,
hwaddr paddr, hwaddr xlat,
int prot,
target_ulong *address)
{
-CPUState *cpu = ENV_GET_CPU(env);
hwaddr iotlb;
CPUWatchpoint *wp;
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
index 31df03c..b8ecd6f 100644
--- a/include/exec/cputlb.h
+++ b/include/exec/cputlb.h
@@ -36,7 +36,7 @@ void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
MemoryRegionSection *
address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat,
hwaddr *plen);
-hwaddr memory_region_section_get_iotlb(CPUArchState *env,
+hwaddr memory_region_section_get_iotlb(CPUState *cpu,
MemoryRegionSection *section,
target_ulong vaddr,
hwaddr paddr, hwaddr xlat,
--
1.8.1.4
[Qemu-devel] [RFC qom-cpu 33/41] cputlb: Change tlb_set_page() argument to CPUState
Signed-off-by: Andreas Färber afaer...@suse.de
---
cputlb.c | 4 ++--
include/exec/exec-all.h| 2 +-
target-alpha/helper.c | 2 +-
target-arm/helper.c| 2 +-
target-cris/helper.c | 2 +-
target-i386/helper.c | 2 +-
target-lm32/helper.c | 6 +++---
target-m68k/helper.c | 3 +--
target-microblaze/helper.c | 4 ++--
target-mips/helper.c | 2 +-
target-moxie/helper.c | 2 +-
target-openrisc/mmu.c | 2 +-
target-ppc/mmu-hash32.c| 8
target-ppc/mmu-hash64.c| 4 ++--
target-ppc/mmu_helper.c| 2 +-
target-s390x/helper.c | 2 +-
target-sh4/helper.c| 2 +-
target-sparc/mmu_helper.c | 6 +++---
target-unicore32/softmmu.c | 2 +-
target-xtensa/op_helper.c | 8
20 files changed, 33 insertions(+), 34 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index ddcd2cd..f8b9566 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -236,11 +236,11 @@ static void tlb_add_large_page(CPUState *cpu,
target_ulong vaddr,
/* Add a new TLB entry. At most one entry for a given virtual address
is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
supplied size is only used by tlb_flush_page. */
-void tlb_set_page(CPUArchState *env, target_ulong vaddr,
+void tlb_set_page(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size)
{
-CPUState *cpu = ENV_GET_CPU(env);
+CPUArchState *env = cpu-env_ptr;
MemoryRegionSection *section;
unsigned int index;
target_ulong address;
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 1838ae1..847ed84 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -98,7 +98,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start,
tb_page_addr_t end,
/* cputlb.c */
void tlb_flush_page(CPUArchState *env, target_ulong addr);
void tlb_flush(CPUArchState *env, int flush_global);
-void tlb_set_page(CPUArchState *env, target_ulong vaddr,
+void tlb_set_page(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
void tb_invalidate_phys_addr(hwaddr addr);
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index f0ba5dd..fd4a70c 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -344,7 +344,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
int rw,
return 1;
}
-tlb_set_page(env, addr TARGET_PAGE_MASK, phys TARGET_PAGE_MASK,
+tlb_set_page(cs, addr TARGET_PAGE_MASK, phys TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index bc00858..06dd57c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3040,7 +3040,7 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
/* Map a single [sub]page. */
phys_addr = ~(hwaddr)0x3ff;
address = ~(uint32_t)0x3ff;
-tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
+tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
return 0;
}
diff --git a/target-cris/helper.c b/target-cris/helper.c
index 3c4501c..08b3864 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -106,7 +106,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int rw,
*/
phy = res.phy ~0x8000;
prot = res.prot;
-tlb_set_page(env, address TARGET_PAGE_MASK, phy,
+tlb_set_page(cs, address TARGET_PAGE_MASK, phy,
prot, mmu_idx, TARGET_PAGE_SIZE);
r = 0;
}
diff --git a/target-i386/helper.c b/target-i386/helper.c
index a6d64a6..e0df092 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -864,7 +864,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
paddr = (pte TARGET_PAGE_MASK) + page_offset;
vaddr = virt_addr + page_offset;
-tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
+tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return 0;
do_fault_protect:
error_code = PG_ERROR_P_MASK;
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index b2093a8..daf0f2f 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -30,10 +30,10 @@ int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int rw,
address = TARGET_PAGE_MASK;
prot = PAGE_BITS;
if (env-flags LM32_FLAG_IGNORE_MSB) {
-tlb_set_page(env, address, address 0x7fff, prot, mmu_idx,
-TARGET_PAGE_SIZE);
+tlb_set_page(cs, address, address 0x7fff, prot, mmu_idx,
+ TARGET_PAGE_SIZE);
} else {
-tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
+tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
}
return 0;
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index
[Qemu-devel] [RFC qom-cpu 32/41] cputlb: Change tlb_set_page() argument to CPUState
It no longer needs CPUArchState since moving tlb_flush_* to CPUState.
Signed-off-by: Andreas Färber afaer...@suse.de
---
cputlb.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index e5b6145..ddcd2cd 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -212,10 +212,9 @@ void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
/* Our TLB does not support large pages, so remember the area covered by
large pages and trigger a full TLB flush if these are invalidated. */
-static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
+static void tlb_add_large_page(CPUState *cpu, target_ulong vaddr,
target_ulong size)
{
-CPUState *cpu = ENV_GET_CPU(env);
target_ulong mask = ~(size - 1);
if ((target_ulong)cpu-tlb_flush_addr == (target_ulong)-1) {
@@ -252,7 +251,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
assert(size = TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
-tlb_add_large_page(env, vaddr, size);
+tlb_add_large_page(cpu, vaddr, size);
}
sz = size;
--
1.8.1.4
[Qemu-devel] [RFC qom-cpu 41/41] user-exec: Change exception_action() argument to CPUState
Signed-off-by: Andreas Färber afaer...@suse.de
---
user-exec.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/user-exec.c b/user-exec.c
index 3b795c1..bc58056 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -38,11 +38,12 @@
//#define DEBUG_SIGNAL
-static void exception_action(CPUArchState *env1)
+static void exception_action(CPUState *cpu)
{
-CPUState *cpu = ENV_GET_CPU(env1);
-
#if defined(TARGET_I386)
+X86CPU *x86_cpu = X86_CPU(cpu);
+CPUX86State *env1 = x86_cpu-env;
+
raise_exception_err(env1, cpu-exception_index, env1-error_code);
#else
cpu_loop_exit(cpu);
@@ -86,7 +87,6 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned
long address,
{
CPUState *cpu;
CPUClass *cc;
-CPUArchState *env;
int ret;
#if defined(DEBUG_SIGNAL)
@@ -105,7 +105,6 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned
long address,
cpu = current_cpu;
cc = CPU_GET_CLASS(cpu);
-env = cpu-env_ptr;
/* see if it is an MMU fault */
g_assert(cc-handle_mmu_fault);
ret = cc-handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
@@ -121,7 +120,7 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned
long address,
/* we restore the process signal mask as the sigreturn should
do it (XXX: use sigsetjmp) */
sigprocmask(SIG_SETMASK, old_set, NULL);
-exception_action(env);
+exception_action(cpu);
/* never comes here */
return 1;
--
1.8.1.4
[Qemu-devel] [RFC qom-cpu 36/41] target-lm32: Replace DisasContext::env field with LM32CPU
This cleans up some lm32_env_get_cpu() introduced for cpu_abort().
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-lm32/translate.c | 60 -
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 532345b..57b91c4 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -64,7 +64,7 @@ enum {
/* This is the state at translation time. */
typedef struct DisasContext {
-CPULM32State *env;
+LM32CPU *cpu;
target_ulong pc;
/* Decoder. */
@@ -421,8 +421,8 @@ static void dec_divu(DisasContext *dc)
LOG_DIS(divu r%d, r%d, r%d\n, dc-r2, dc-r0, dc-r1);
-if (!(dc-env-features LM32_FEATURE_DIVIDE)) {
-cpu_abort(CPU(lm32_env_get_cpu(dc-env)), hardware divider is not
available\n);
+if (!(dc-cpu-env.features LM32_FEATURE_DIVIDE)) {
+cpu_abort(CPU(dc-cpu), hardware divider is not available\n);
}
l1 = gen_new_label();
@@ -499,8 +499,8 @@ static void dec_modu(DisasContext *dc)
LOG_DIS(modu r%d, r%d, %d\n, dc-r2, dc-r0, dc-r1);
-if (!(dc-env-features LM32_FEATURE_DIVIDE)) {
-cpu_abort(CPU(lm32_env_get_cpu(dc-env)), hardware divider is not
available\n);
+if (!(dc-cpu-env.features LM32_FEATURE_DIVIDE)) {
+cpu_abort(CPU(dc-cpu), hardware divider is not available\n);
}
l1 = gen_new_label();
@@ -520,8 +520,8 @@ static void dec_mul(DisasContext *dc)
LOG_DIS(mul r%d, r%d, r%d\n, dc-r2, dc-r0, dc-r1);
}
-if (!(dc-env-features LM32_FEATURE_MULTIPLY)) {
-cpu_abort(CPU(lm32_env_get_cpu(dc-env)), hardware multiplier is not
available\n);
+if (!(dc-cpu-env.features LM32_FEATURE_MULTIPLY)) {
+cpu_abort(CPU(dc-cpu), hardware multiplier is not available\n);
}
if (dc-format == OP_FMT_RI) {
@@ -590,7 +590,7 @@ static void dec_scall(DisasContext *dc)
} else if (dc-imm5 == 2) {
LOG_DIS(break\n);
} else {
-cpu_abort(CPU(lm32_env_get_cpu(dc-env)), invalid opcode\n);
+cpu_abort(CPU(dc-cpu), invalid opcode\n);
}
if (dc-imm5 == 7) {
@@ -647,10 +647,10 @@ static void dec_rcsr(DisasContext *dc)
case CSR_WP1:
case CSR_WP2:
case CSR_WP3:
-cpu_abort(CPU(lm32_env_get_cpu(dc-env)), invalid read access
csr=%x\n, dc-csr);
+cpu_abort(CPU(dc-cpu), invalid read access csr=%x\n, dc-csr);
break;
default:
-cpu_abort(CPU(lm32_env_get_cpu(dc-env)), read_csr: unknown
csr=%x\n, dc-csr);
+cpu_abort(CPU(dc-cpu), read_csr: unknown csr=%x\n, dc-csr);
break;
}
}
@@ -671,8 +671,8 @@ static void dec_sextb(DisasContext *dc)
{
LOG_DIS(sextb r%d, r%d\n, dc-r2, dc-r0);
-if (!(dc-env-features LM32_FEATURE_SIGN_EXTEND)) {
-cpu_abort(CPU(lm32_env_get_cpu(dc-env)), hardware sign extender is
not available\n);
+if (!(dc-cpu-env.features LM32_FEATURE_SIGN_EXTEND)) {
+cpu_abort(CPU(dc-cpu), hardware sign extender is not available\n);
}
tcg_gen_ext8s_tl(cpu_R[dc-r2], cpu_R[dc-r0]);
@@ -682,8 +682,8 @@ static void dec_sexth(DisasContext *dc)
{
LOG_DIS(sexth r%d, r%d\n, dc-r2, dc-r0);
-if (!(dc-env-features LM32_FEATURE_SIGN_EXTEND)) {
-cpu_abort(CPU(lm32_env_get_cpu(dc-env)), hardware sign extender is
not available\n);
+if (!(dc-cpu-env.features LM32_FEATURE_SIGN_EXTEND)) {
+cpu_abort(CPU(dc-cpu), hardware sign extender is not available\n);
}
tcg_gen_ext16s_tl(cpu_R[dc-r2], cpu_R[dc-r0]);
@@ -709,8 +709,8 @@ static void dec_sl(DisasContext *dc)
LOG_DIS(sl r%d, r%d, r%d\n, dc-r2, dc-r0, dc-r1);
}
-if (!(dc-env-features LM32_FEATURE_SHIFT)) {
-cpu_abort(CPU(lm32_env_get_cpu(dc-env)), hardware shifter is not
available\n);
+if (!(dc-cpu-env.features LM32_FEATURE_SHIFT)) {
+cpu_abort(CPU(dc-cpu), hardware shifter is not available\n);
}
if (dc-format == OP_FMT_RI) {
@@ -731,12 +731,12 @@ static void dec_sr(DisasContext *dc)
LOG_DIS(sr r%d, r%d, r%d\n, dc-r2, dc-r0, dc-r1);
}
-if (!(dc-env-features LM32_FEATURE_SHIFT)) {
+if (!(dc-cpu-env.features LM32_FEATURE_SHIFT)) {
if (dc-format == OP_FMT_RI) {
/* TODO: check r1 == 1 during runtime */
} else {
if (dc-imm5 != 1) {
-cpu_abort(CPU(lm32_env_get_cpu(dc-env)), hardware shifter is
not available\n);
+cpu_abort(CPU(dc-cpu), hardware shifter is not available\n);
}
}
}
@@ -759,12 +759,12 @@ static void dec_sru(DisasContext *dc)
LOG_DIS(sru r%d, r%d, r%d\n, dc-r2, dc-r0, dc-r1);
}
-if (!(dc-env-features LM32_FEATURE_SHIFT)) {
+if (!(dc-cpu-env.features LM32_FEATURE_SHIFT)) {
if (dc-format == OP_FMT_RI) {
/* TODO: check r1 == 1 during runtime */
} else {
if (dc-imm5 != 1
[Qemu-devel] [RFC qom-cpu 38/41] target-lm32: Move features field from CPULM32State to LM32CPU
This simplifies the code after conversion to DisasContext::cpu.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-lm32/cpu-qom.h | 3 +++
target-lm32/cpu.h | 2 --
target-lm32/helper.c| 2 +-
target-lm32/translate.c | 16
4 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h
index 723f604..16ef037 100644
--- a/target-lm32/cpu-qom.h
+++ b/target-lm32/cpu-qom.h
@@ -51,6 +51,7 @@ typedef struct LM32CPUClass {
/**
* LM32CPU:
* @env: #CPULM32State
+ * @features: Processor core features.
*
* A LatticeMico32 CPU.
*/
@@ -60,6 +61,8 @@ typedef struct LM32CPU {
/* public */
CPULM32State env;
+
+uint32_t features;
} LM32CPU;
static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env)
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 85c89e8..0ff8e7c 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -173,8 +173,6 @@ struct CPULM32State {
/* JTAG UART handle for callbacks */
DeviceState *juart_state;
-/* processor core features */
-uint32_t features;
uint32_t flags;
uint8_t num_bps;
uint8_t num_wps;
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 8f2b9fd..68de4ee 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -218,7 +218,7 @@ LM32CPU *cpu_lm32_init(const char *cpu_model)
cpu = LM32_CPU(object_new(TYPE_LM32_CPU));
env = cpu-env;
-env-features = def-features;
+cpu-features = def-features;
env-num_bps = def-num_breakpoints;
env-num_wps = def-num_watchpoints;
env-cfg = cfg_by_def(def);
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 57b91c4..d4e8106 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -421,7 +421,7 @@ static void dec_divu(DisasContext *dc)
LOG_DIS(divu r%d, r%d, r%d\n, dc-r2, dc-r0, dc-r1);
-if (!(dc-cpu-env.features LM32_FEATURE_DIVIDE)) {
+if (!(dc-cpu-features LM32_FEATURE_DIVIDE)) {
cpu_abort(CPU(dc-cpu), hardware divider is not available\n);
}
@@ -499,7 +499,7 @@ static void dec_modu(DisasContext *dc)
LOG_DIS(modu r%d, r%d, %d\n, dc-r2, dc-r0, dc-r1);
-if (!(dc-cpu-env.features LM32_FEATURE_DIVIDE)) {
+if (!(dc-cpu-features LM32_FEATURE_DIVIDE)) {
cpu_abort(CPU(dc-cpu), hardware divider is not available\n);
}
@@ -520,7 +520,7 @@ static void dec_mul(DisasContext *dc)
LOG_DIS(mul r%d, r%d, r%d\n, dc-r2, dc-r0, dc-r1);
}
-if (!(dc-cpu-env.features LM32_FEATURE_MULTIPLY)) {
+if (!(dc-cpu-features LM32_FEATURE_MULTIPLY)) {
cpu_abort(CPU(dc-cpu), hardware multiplier is not available\n);
}
@@ -671,7 +671,7 @@ static void dec_sextb(DisasContext *dc)
{
LOG_DIS(sextb r%d, r%d\n, dc-r2, dc-r0);
-if (!(dc-cpu-env.features LM32_FEATURE_SIGN_EXTEND)) {
+if (!(dc-cpu-features LM32_FEATURE_SIGN_EXTEND)) {
cpu_abort(CPU(dc-cpu), hardware sign extender is not available\n);
}
@@ -682,7 +682,7 @@ static void dec_sexth(DisasContext *dc)
{
LOG_DIS(sexth r%d, r%d\n, dc-r2, dc-r0);
-if (!(dc-cpu-env.features LM32_FEATURE_SIGN_EXTEND)) {
+if (!(dc-cpu-features LM32_FEATURE_SIGN_EXTEND)) {
cpu_abort(CPU(dc-cpu), hardware sign extender is not available\n);
}
@@ -709,7 +709,7 @@ static void dec_sl(DisasContext *dc)
LOG_DIS(sl r%d, r%d, r%d\n, dc-r2, dc-r0, dc-r1);
}
-if (!(dc-cpu-env.features LM32_FEATURE_SHIFT)) {
+if (!(dc-cpu-features LM32_FEATURE_SHIFT)) {
cpu_abort(CPU(dc-cpu), hardware shifter is not available\n);
}
@@ -731,7 +731,7 @@ static void dec_sr(DisasContext *dc)
LOG_DIS(sr r%d, r%d, r%d\n, dc-r2, dc-r0, dc-r1);
}
-if (!(dc-cpu-env.features LM32_FEATURE_SHIFT)) {
+if (!(dc-cpu-features LM32_FEATURE_SHIFT)) {
if (dc-format == OP_FMT_RI) {
/* TODO: check r1 == 1 during runtime */
} else {
@@ -759,7 +759,7 @@ static void dec_sru(DisasContext *dc)
LOG_DIS(sru r%d, r%d, r%d\n, dc-r2, dc-r0, dc-r1);
}
-if (!(dc-cpu-env.features LM32_FEATURE_SHIFT)) {
+if (!(dc-cpu-features LM32_FEATURE_SHIFT)) {
if (dc-format == OP_FMT_RI) {
/* TODO: check r1 == 1 during runtime */
} else {
--
1.8.1.4
[Qemu-devel] [RFC qom-cpu 40/41] cputlb: Change tlb_flush() argument to CPUState
Signed-off-by: Andreas Färber afaer...@suse.de
---
cputlb.c | 6 +++---
exec.c | 4 +---
hw/sh4/sh7750.c| 2 +-
include/exec/exec-all.h| 4 ++--
target-alpha/cpu.c | 2 +-
target-alpha/sys_helper.c | 2 +-
target-arm/cpu.c | 2 +-
target-arm/helper.c| 28 +---
target-cris/cpu.c | 2 +-
target-i386/cpu.c | 2 +-
target-i386/helper.c | 17 ++-
target-i386/machine.c | 2 +-
target-i386/svm_helper.c | 2 +-
target-lm32/cpu.c | 2 +-
target-m68k/cpu.c | 2 +-
target-microblaze/cpu.c| 2 +-
target-microblaze/mmu.c| 2 +-
target-mips/cpu.c | 2 +-
target-mips/machine.c | 3 ++-
target-mips/op_helper.c| 4 +++-
target-moxie/cpu.c | 2 +-
target-openrisc/cpu.c | 2 +-
target-openrisc/interrupt.c| 2 +-
target-openrisc/interrupt_helper.c | 2 +-
target-openrisc/sys_helper.c | 2 +-
target-ppc/excp_helper.c | 4 ++--
target-ppc/helper_regs.h | 2 +-
target-ppc/misc_helper.c | 4 +++-
target-ppc/mmu-hash64.c| 6 --
target-ppc/mmu_helper.c| 44 --
target-ppc/translate_init.c| 2 +-
target-s390x/cpu.c | 5 ++---
target-s390x/mem_helper.c | 13 +++
target-sh4/cpu.c | 2 +-
target-sh4/helper.c| 2 +-
target-sparc/cpu.c | 2 +-
target-sparc/ldst_helper.c | 16 --
target-sparc/machine.c | 3 ++-
target-unicore32/cpu.c | 2 +-
target-unicore32/helper.c | 4 +++-
target-xtensa/op_helper.c | 4 +++-
41 files changed, 132 insertions(+), 85 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 817180e..bfa7417 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -52,9 +52,9 @@ static const CPUTLBEntry s_cputlb_empty_entry = {
* entries from the TLB at any time, so flushing more entries than
* required is only an efficiency issue, not a correctness issue.
*/
-void tlb_flush(CPUArchState *env, int flush_global)
+void tlb_flush(CPUState *cpu, int flush_global)
{
-CPUState *cpu = ENV_GET_CPU(env);
+CPUArchState *env = cpu-env_ptr;
int i;
#if defined(DEBUG_TLB)
@@ -107,7 +107,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
VADDR_PRIx /% VADDR_PRIx )\n,
cpu-tlb_flush_addr, cpu-tlb_flush_mask);
#endif
-tlb_flush(env, 1);
+tlb_flush(cpu, 1);
return;
}
/* must reset current TB so that interrupts cannot modify the
diff --git a/exec.c b/exec.c
index 9210834..8e514e8 100644
--- a/exec.c
+++ b/exec.c
@@ -1720,9 +1720,7 @@ static void tcg_commit(MemoryListener *listener)
reset the modified entries */
/* XXX: slow ! */
CPU_FOREACH(cpu) {
-CPUArchState *env = cpu-env_ptr;
-
-tlb_flush(env, 1);
+tlb_flush(cpu, 1);
}
}
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
index 1439ba4..4a39357 100644
--- a/hw/sh4/sh7750.c
+++ b/hw/sh4/sh7750.c
@@ -416,7 +416,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,
case SH7750_PTEH_A7:
/* If asid changes, clear all registered tlb entries. */
if ((s-cpu-env.pteh 0xff) != (mem_value 0xff)) {
-tlb_flush(s-cpu-env, 1);
+tlb_flush(CPU(s-cpu), 1);
}
s-cpu-env.pteh = mem_value;
return;
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 550e58d..f2d1c6c 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -97,7 +97,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start,
tb_page_addr_t end,
#if !defined(CONFIG_USER_ONLY)
/* cputlb.c */
void tlb_flush_page(CPUState *cpu, target_ulong addr);
-void tlb_flush(CPUArchState *env, int flush_global);
+void tlb_flush(CPUState *cpu, int flush_global);
void tlb_set_page(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
@@ -107,7 +107,7 @@ static inline void tlb_flush_page(CPUState *cpu,
target_ulong addr)
{
}
-static inline void tlb_flush(CPUArchState *env, int flush_global)
+static inline void tlb_flush(CPUState *cpu, int flush_global)
{
}
#endif
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 9931f9f..d839d53 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -294,7 +294,7 @@ static void alpha_cpu_initfn(Object *obj)
cs-env_ptr = env;
cpu_exec_init(env);
-tlb_flush(env, 1);
+tlb_flush(cs, 1);
alpha_translate_init();
diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c
index 5f7d7dd..187ccf7 100644
[Qemu-devel] [RFC qom-cpu 39/41] cputlb: Change tlb_flush_page() argument to CPUState
Signed-off-by: Andreas Färber afaer...@suse.de
---
cputlb.c | 4 +--
exec.c | 7 ++
include/exec/exec-all.h | 4 +--
target-alpha/sys_helper.c| 2 +-
target-arm/helper.c | 8 --
target-cris/mmu.c| 3 ++-
target-cris/op_helper.c | 12 ++---
target-i386/misc_helper.c| 4 ++-
target-i386/svm_helper.c | 3 ++-
target-microblaze/mmu.c | 3 ++-
target-mips/helper.c | 8 --
target-openrisc/sys_helper.c | 4 +--
target-ppc/mmu_helper.c | 58 +---
target-s390x/mem_helper.c| 7 +++---
target-s390x/misc_helper.c | 6 +++--
target-sh4/helper.c | 19 +--
target-sparc/ldst_helper.c | 7 --
target-xtensa/op_helper.c| 11 ++---
18 files changed, 103 insertions(+), 67 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 20a1efe..817180e 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -91,9 +91,9 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry,
target_ulong addr)
}
}
-void tlb_flush_page(CPUArchState *env, target_ulong addr)
+void tlb_flush_page(CPUState *cpu, target_ulong addr)
{
-CPUState *cpu = ENV_GET_CPU(env);
+CPUArchState *env = cpu-env_ptr;
int i;
int mmu_idx;
diff --git a/exec.c b/exec.c
index 16e3c4d..9210834 100644
--- a/exec.c
+++ b/exec.c
@@ -433,7 +433,6 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr
len,
int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
int flags, CPUWatchpoint **watchpoint)
{
-CPUArchState *env = cpu-env_ptr;
vaddr len_mask = ~(len - 1);
CPUWatchpoint *wp;
@@ -457,7 +456,7 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr
len,
QTAILQ_INSERT_TAIL(cpu-watchpoints, wp, entry);
}
-tlb_flush_page(env, addr);
+tlb_flush_page(cpu, addr);
if (watchpoint)
*watchpoint = wp;
@@ -484,11 +483,9 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr
len,
/* Remove a specific watchpoint by reference. */
void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
{
-CPUArchState *env = cpu-env_ptr;
-
QTAILQ_REMOVE(cpu-watchpoints, watchpoint, entry);
-tlb_flush_page(env, watchpoint-vaddr);
+tlb_flush_page(cpu, watchpoint-vaddr);
g_free(watchpoint);
}
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 847ed84..550e58d 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -96,14 +96,14 @@ void tb_invalidate_phys_range(tb_page_addr_t start,
tb_page_addr_t end,
int is_cpu_write_access);
#if !defined(CONFIG_USER_ONLY)
/* cputlb.c */
-void tlb_flush_page(CPUArchState *env, target_ulong addr);
+void tlb_flush_page(CPUState *cpu, target_ulong addr);
void tlb_flush(CPUArchState *env, int flush_global);
void tlb_set_page(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
void tb_invalidate_phys_addr(hwaddr addr);
#else
-static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
+static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
{
}
diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c
index 035810c..5f7d7dd 100644
--- a/target-alpha/sys_helper.c
+++ b/target-alpha/sys_helper.c
@@ -69,7 +69,7 @@ void helper_tbia(CPUAlphaState *env)
void helper_tbis(CPUAlphaState *env, uint64_t p)
{
-tlb_flush_page(env, p);
+tlb_flush_page(CPU(alpha_env_get_cpu(env)), p);
}
void helper_tb_flush(CPUAlphaState *env)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 34407a1..4daf82e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -311,8 +311,10 @@ static int tlbiall_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ARMCPU *cpu = arm_env_get_cpu(env);
+
/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
-tlb_flush_page(env, value TARGET_PAGE_MASK);
+tlb_flush_page(CPU(cpu), value TARGET_PAGE_MASK);
return 0;
}
@@ -327,8 +329,10 @@ static int tlbiasid_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ARMCPU *cpu = arm_env_get_cpu(env);
+
/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
-tlb_flush_page(env, value TARGET_PAGE_MASK);
+tlb_flush_page(CPU(cpu), value TARGET_PAGE_MASK);
return 0;
}
diff --git a/target-cris/mmu.c b/target-cris/mmu.c
index 512e28b..1c95a41 100644
--- a/target-cris/mmu.c
+++ b/target-cris/mmu.c
@@ -290,6 +290,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result
*res,
void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
{
+CRISCPU *cpu
[Qemu-devel] [RFC qom-cpu 20/41] translate-all: Change cpu_restore_state() argument to CPUState
This lets us drop some local variables in tlb_fill() functions.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/i386/kvmvapic.c| 2 +-
include/exec/exec-all.h | 2 +-
target-alpha/helper.c | 2 +-
target-alpha/mem_helper.c | 7 ++-
target-arm/op_helper.c| 2 +-
target-cris/op_helper.c | 2 +-
target-i386/helper.c | 2 +-
target-i386/mem_helper.c | 2 +-
target-lm32/op_helper.c | 5 +
target-m68k/op_helper.c | 5 +
target-microblaze/op_helper.c | 5 +
target-mips/op_helper.c | 2 +-
target-moxie/helper.c | 6 ++
target-openrisc/mmu_helper.c | 5 +
target-ppc/mmu_helper.c | 2 +-
target-s390x/mem_helper.c | 5 +
target-s390x/misc_helper.c| 2 +-
target-sh4/op_helper.c| 7 ++-
target-sparc/helper.c | 12 ++--
target-sparc/ldst_helper.c| 7 ++-
target-unicore32/op_helper.c | 5 +
target-xtensa/op_helper.c | 4 ++--
translate-all.c | 3 ++-
user-exec.c | 2 +-
24 files changed, 35 insertions(+), 63 deletions(-)
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 01e1117..5757a1b 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -408,7 +408,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU
*cpu, target_ulong ip)
if (!kvm_enabled()) {
CPUClass *cc = CPU_GET_CLASS(cs);
-cpu_restore_state(env, cs-mem_io_pc);
+cpu_restore_state(cs, cs-mem_io_pc);
cc-get_tb_cpu_state(cs, current_pc, current_cs_base,
current_flags);
}
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index f6b9eac..c25951c 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -80,7 +80,7 @@ void restore_state_to_opc(CPUArchState *env, struct
TranslationBlock *tb,
void cpu_gen_init(void);
int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
int *gen_code_size_ptr);
-bool cpu_restore_state(CPUArchState *env, uintptr_t searched_pc);
+bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr);
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index 41a1394..f0ba5dd 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -525,7 +525,7 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env,
uintptr_t retaddr,
cs-exception_index = excp;
env-error_code = error;
if (retaddr) {
-cpu_restore_state(env, retaddr);
+cpu_restore_state(cs, retaddr);
}
cpu_loop_exit(cs);
}
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index c2bd64a..a807aa0 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -97,7 +97,7 @@ static void do_unaligned_access(CPUAlphaState *env,
target_ulong addr,
uint32_t insn;
if (retaddr) {
-cpu_restore_state(env, retaddr);
+cpu_restore_state(cs, retaddr);
}
pc = env-pc;
@@ -151,11 +151,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
is_write,
ret = alpha_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
-AlphaCPU *cpu = ALPHA_CPU(cs);
-CPUAlphaState *env = cpu-env;
-
if (retaddr) {
-cpu_restore_state(env, retaddr);
+cpu_restore_state(cs, retaddr);
}
/* Exception index and error code are already set */
cpu_loop_exit(cs);
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 552ca3d..7bd698c 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -87,7 +87,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
int mmu_idx,
if (retaddr) {
/* now we have a real cpu fault */
-cpu_restore_state(env, retaddr);
+cpu_restore_state(cs, retaddr);
}
raise_exception(env, cs-exception_index);
}
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index d80b6c9..d28bd61 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
int mmu_idx,
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
-if (cpu_restore_state(env, retaddr)) {
+if (cpu_restore_state(cs, retaddr)) {
/* Evaluate flags after retranslation. */
helper_top_evaluate_flags(env);
}
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 557c94f..c571589 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1258,7 +1258,7 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess
access)
cpu_interrupt(cs, CPU_INTERRUPT_TPR);
} else
[Qemu-devel] [RFC qom-cpu 25/41] translate-all: Change tb_flush_jmp_cache() argument to CPUState
Signed-off-by: Andreas Färber afaer...@suse.de
---
cputlb.c | 2 +-
include/exec/cputlb.h | 2 +-
translate-all.c | 3 +--
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index e02663c..3721bfc 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -120,7 +120,7 @@ void tlb_flush_page(CPUArchState *env, target_ulong addr)
tlb_flush_entry(env-tlb_table[mmu_idx][i], addr);
}
-tb_flush_jmp_cache(env, addr);
+tb_flush_jmp_cache(cpu, addr);
}
/* update the TLBs so that writes to code in the virtual page 'addr'
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
index e21cb60..e1eb4d9 100644
--- a/include/exec/cputlb.h
+++ b/include/exec/cputlb.h
@@ -31,7 +31,7 @@ void tlb_set_dirty(CPUArchState *env, target_ulong vaddr);
extern int tlb_flush_count;
/* exec.c */
-void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr);
+void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
MemoryRegionSection *
address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat,
diff --git a/translate-all.c b/translate-all.c
index 6e5bfee..2254b9f 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1492,9 +1492,8 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
cpu_resume_from_signal(env, NULL);
}
-void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr)
+void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr)
{
-CPUState *cpu = ENV_GET_CPU(env);
unsigned int i;
/* Discard jump cache entries for any tb which might potentially
--
1.8.1.4
[Qemu-devel] [RFC qom-cpu 29/41] cpu-exec: Change cpu_resume_from_signal() argument to CPUState
Signed-off-by: Andreas Färber afaer...@suse.de
---
cpu-exec.c | 4 +---
exec.c | 3 +--
hw/i386/kvmvapic.c | 3 +--
include/exec/exec-all.h | 2 +-
target-i386/helper.c| 2 +-
target-xtensa/helper.c | 2 +-
translate-all.c | 12 ++--
user-exec.c | 3 +--
8 files changed, 13 insertions(+), 18 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index a984b7c..6016a10 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -33,10 +33,8 @@ void cpu_loop_exit(CPUState *cpu)
restored in a state compatible with the CPU emulator
*/
#if defined(CONFIG_SOFTMMU)
-void cpu_resume_from_signal(CPUArchState *env, void *puc)
+void cpu_resume_from_signal(CPUState *cpu, void *puc)
{
-CPUState *cpu = ENV_GET_CPU(env);
-
/* XXX: restore cpu registers saved in host registers */
cpu-exception_index = -1;
diff --git a/exec.c b/exec.c
index 7ea864a..5f133e4 100644
--- a/exec.c
+++ b/exec.c
@@ -1455,7 +1455,6 @@ static const MemoryRegionOps notdirty_mem_ops = {
static void check_watchpoint(int offset, int len_mask, int flags)
{
CPUState *cpu = current_cpu;
-CPUArchState *env = cpu-env_ptr;
CPUClass *cc = CPU_GET_CLASS(cpu);
vaddr pc, cs_base;
target_ulong vaddr;
@@ -1483,7 +1482,7 @@ static void check_watchpoint(int offset, int len_mask,
int flags)
} else {
cc-get_tb_cpu_state(cpu, pc, cs_base, cpu_flags);
tb_gen_code(cpu, pc, cs_base, cpu_flags, 1);
-cpu_resume_from_signal(env, NULL);
+cpu_resume_from_signal(cpu, NULL);
}
}
} else {
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index bcf8d9d..95449f7 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -391,7 +391,6 @@ static void patch_call(VAPICROMState *s, X86CPU *cpu,
target_ulong ip,
static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
{
CPUState *cs = CPU(cpu);
-CPUX86State *env = cpu-env;
VAPICHandlers *handlers;
uint8_t opcode[2];
uint32_t imm32;
@@ -451,7 +450,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU
*cpu, target_ulong ip)
if (!kvm_enabled()) {
cs-current_tb = NULL;
tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1);
-cpu_resume_from_signal(env, NULL);
+cpu_resume_from_signal(cs, NULL);
}
}
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 73abf9e..1838ae1 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -82,7 +82,7 @@ int cpu_gen_code(CPUArchState *env, struct TranslationBlock
*tb,
int *gen_code_size_ptr);
bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
-void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
+void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc);
void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
TranslationBlock *tb_gen_code(CPUState *cpu,
target_ulong pc, target_ulong cs_base, int flags,
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 1cd7688..a6d64a6 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1097,7 +1097,7 @@ void breakpoint_handler(CPUX86State *env)
if (check_hw_breakpoints(env, false)) {
raise_exception(env, EXCP01_DB);
} else {
-cpu_resume_from_signal(env, NULL);
+cpu_resume_from_signal(cs, NULL);
}
}
} else {
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index c44cf71..9e5af25 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -92,7 +92,7 @@ void xtensa_breakpoint_handler(CPUXtensaState *env)
if (cause) {
debug_exception_env(env, cause);
}
-cpu_resume_from_signal(env, NULL);
+cpu_resume_from_signal(cs, NULL);
}
}
}
diff --git a/translate-all.c b/translate-all.c
index 2254b9f..9b62b07 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1002,7 +1002,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start,
tb_page_addr_t end,
{
TranslationBlock *tb, *tb_next, *saved_tb;
CPUState *cpu = current_cpu;
-#if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
CPUArchState *env = NULL;
#endif
tb_page_addr_t tb_start, tb_end;
@@ -1030,7 +1030,9 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start,
tb_page_addr_t end,
}
#if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY)
if (cpu != NULL) {
+#ifndef CONFIG_USER_ONLY
env = cpu-env_ptr;
+#endif
#ifdef TARGET_HAS_PRECISE_SMC
cc = CPU_GET_CLASS(cpu);
#endif
@@ -1112,7 +1114,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start,
tb_page_addr_t end,
itself */
cpu
[Qemu-devel] [RFC qom-cpu 12/41] cpu: Move cpu_copy() into linux-user
It is only used there and is deemed very fragile if not incorrect in its
current memcpy() form. Moving it into linux-user will allow to move
parts into target_cpu.h headers and only copy what the ABI mandates.
Signed-off-by: Andreas Färber afaer...@suse.de
---
exec.c| 32
linux-user/main.c | 31 +++
2 files changed, 31 insertions(+), 32 deletions(-)
diff --git a/exec.c b/exec.c
index 508f1e2..93958c3 100644
--- a/exec.c
+++ b/exec.c
@@ -625,38 +625,6 @@ void cpu_abort(CPUArchState *env, const char *fmt, ...)
abort();
}
-CPUArchState *cpu_copy(CPUArchState *env)
-{
-CPUArchState *new_env = cpu_init(env-cpu_model_str);
-#if defined(TARGET_HAS_ICE)
-CPUBreakpoint *bp;
-CPUWatchpoint *wp;
-#endif
-
-/* Reset non arch specific state */
-cpu_reset(ENV_GET_CPU(new_env));
-
-/* Copy arch specific state into the new CPU */
-memcpy(new_env, env, sizeof(CPUArchState));
-
-/* Clone all break/watchpoints.
- Note: Once we support ptrace with hw-debug register access, make sure
- BP_CPU break/watchpoints are handled correctly on clone. */
-QTAILQ_INIT(env-breakpoints);
-QTAILQ_INIT(env-watchpoints);
-#if defined(TARGET_HAS_ICE)
-QTAILQ_FOREACH(bp, env-breakpoints, entry) {
-cpu_breakpoint_insert(new_env, bp-pc, bp-flags, NULL);
-}
-QTAILQ_FOREACH(wp, env-watchpoints, entry) {
-cpu_watchpoint_insert(new_env, wp-vaddr, (~wp-len_mask) + 1,
- wp-flags, NULL);
-}
-#endif
-
-return new_env;
-}
-
#if !defined(CONFIG_USER_ONLY)
static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t end,
uintptr_t length)
diff --git a/linux-user/main.c b/linux-user/main.c
index 5c2f7b2..afc3ce4 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3189,6 +3189,37 @@ void init_task_state(TaskState *ts)
ts-sigqueue_table[i].next = NULL;
}
+CPUArchState *cpu_copy(CPUArchState *env)
+{
+CPUArchState *new_env = cpu_init(env-cpu_model_str);
+#if defined(TARGET_HAS_ICE)
+CPUBreakpoint *bp;
+CPUWatchpoint *wp;
+#endif
+
+/* Reset non arch specific state */
+cpu_reset(ENV_GET_CPU(new_env));
+
+memcpy(new_env, env, sizeof(CPUArchState));
+
+/* Clone all break/watchpoints.
+ Note: Once we support ptrace with hw-debug register access, make sure
+ BP_CPU break/watchpoints are handled correctly on clone. */
+QTAILQ_INIT(env-breakpoints);
+QTAILQ_INIT(env-watchpoints);
+#if defined(TARGET_HAS_ICE)
+QTAILQ_FOREACH(bp, env-breakpoints, entry) {
+cpu_breakpoint_insert(new_env, bp-pc, bp-flags, NULL);
+}
+QTAILQ_FOREACH(wp, env-watchpoints, entry) {
+cpu_watchpoint_insert(new_env, wp-vaddr, (~wp-len_mask) + 1,
+ wp-flags, NULL);
+}
+#endif
+
+return new_env;
+}
+
static void handle_arg_help(const char *arg)
{
usage();
--
1.8.1.4
[Qemu-devel] [RFC qom-cpu 30/41] cputlb: Change tlb_update_dirty() argument to CPUState
This allows to drop env in tb_invalidate_phys_page_range().
Note that the argument is unused.
Signed-off-by: Andreas Färber afaer...@suse.de
---
cputlb.c | 2 +-
include/exec/cputlb.h | 2 +-
translate-all.c | 12 ++--
3 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 3721bfc..bd5cf0e 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -134,7 +134,7 @@ void tlb_protect_code(ram_addr_t ram_addr)
/* update the TLB so that writes in physical page 'phys_addr' are no longer
tested for self modifying code */
-void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
+void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr,
target_ulong vaddr)
{
cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG);
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
index e1eb4d9..31df03c 100644
--- a/include/exec/cputlb.h
+++ b/include/exec/cputlb.h
@@ -22,7 +22,7 @@
#if !defined(CONFIG_USER_ONLY)
/* cputlb.c */
void tlb_protect_code(ram_addr_t ram_addr);
-void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
+void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr,
target_ulong vaddr);
void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
uintptr_t length);
diff --git a/translate-all.c b/translate-all.c
index 9b62b07..37b573b 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1002,9 +1002,6 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start,
tb_page_addr_t end,
{
TranslationBlock *tb, *tb_next, *saved_tb;
CPUState *cpu = current_cpu;
-#if !defined(CONFIG_USER_ONLY)
-CPUArchState *env = NULL;
-#endif
tb_page_addr_t tb_start, tb_end;
PageDesc *p;
int n;
@@ -1028,14 +1025,9 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start,
tb_page_addr_t end,
/* build code bitmap */
build_page_bitmap(p);
}
-#if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY)
+#if defined(TARGET_HAS_PRECISE_SMC)
if (cpu != NULL) {
-#ifndef CONFIG_USER_ONLY
-env = cpu-env_ptr;
-#endif
-#ifdef TARGET_HAS_PRECISE_SMC
cc = CPU_GET_CLASS(cpu);
-#endif
}
#endif
@@ -1103,7 +1095,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start,
tb_page_addr_t end,
if (!p-first_tb) {
invalidate_page_bitmap(p);
if (is_cpu_write_access) {
-tlb_unprotect_code_phys(env, start, cpu-mem_io_vaddr);
+tlb_unprotect_code_phys(cpu, start, cpu-mem_io_vaddr);
}
}
#endif
--
1.8.1.4
[Qemu-devel] [RFC qom-cpu 23/41] translate-all: Change cpu_io_recompile() argument to CPUState
Signed-off-by: Andreas Färber afaer...@suse.de
---
include/exec/exec-all.h | 2 +-
include/exec/softmmu_template.h | 4 ++--
translate-all.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index c25951c..40d5931 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -83,7 +83,7 @@ int cpu_gen_code(CPUArchState *env, struct TranslationBlock
*tb,
bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
-void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr);
+void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
TranslationBlock *tb_gen_code(CPUArchState *env,
target_ulong pc, target_ulong cs_base, int flags,
int cflags);
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index 8dc0901..e424d7e 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -82,7 +82,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState
*env,
physaddr = (physaddr TARGET_PAGE_MASK) + addr;
cpu-mem_io_pc = retaddr;
if (mr != io_mem_rom mr != io_mem_notdirty !cpu_can_do_io(cpu)) {
-cpu_io_recompile(env, retaddr);
+cpu_io_recompile(cpu, retaddr);
}
cpu-mem_io_vaddr = addr;
@@ -202,7 +202,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
physaddr = (physaddr TARGET_PAGE_MASK) + addr;
if (mr != io_mem_rom mr != io_mem_notdirty !cpu_can_do_io(cpu)) {
-cpu_io_recompile(env, retaddr);
+cpu_io_recompile(cpu, retaddr);
}
cpu-mem_io_vaddr = addr;
diff --git a/translate-all.c b/translate-all.c
index 22a5b80..1158681 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1432,9 +1432,9 @@ CPUInterruptHandler cpu_interrupt_handler =
tcg_handle_interrupt;
/* in deterministic execution mode, instructions doing device I/Os
must be at the end of the TB */
-void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr)
+void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
{
-CPUState *cpu = ENV_GET_CPU(env);
+CPUArchState *env = cpu-env_ptr;
TranslationBlock *tb;
uint32_t n, cflags;
target_ulong pc, cs_base;
--
1.8.1.4
[Qemu-devel] [RFC qom-cpu 35/41] target-cris: Replace DisasContext::env field with CRISCPU
This cleans up repeated cris_env_get_cpu() for cpu_abort().
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-cris/translate.c | 16
target-cris/translate_v10.c | 16
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target-cris/translate.c b/target-cris/translate.c
index bf15ed6..6f593d6 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -74,7 +74,7 @@ static TCGv env_pc;
/* This is the state at translation time. */
typedef struct DisasContext {
-CPUCRISState *env;
+CRISCPU *cpu;
target_ulong pc, ppc;
/* Decoder. */
@@ -129,7 +129,7 @@ static void gen_BUG(DisasContext *dc, const char *file, int
line)
{
printf(BUG: pc=%x %s %d\n, dc-pc, file, line);
qemu_log(BUG: pc=%x %s %d\n, dc-pc, file, line);
-cpu_abort(CPU(cris_env_get_cpu(dc-env)), %s:%d\n, file, line);
+cpu_abort(CPU(dc-cpu), %s:%d\n, file, line);
}
static const char *regnames[] =
@@ -272,7 +272,7 @@ static int cris_fetch(CPUCRISState *env, DisasContext *dc,
uint32_t addr,
break;
}
default:
-cpu_abort(CPU(cris_env_get_cpu(dc-env)), Invalid fetch size %d\n,
size);
+cpu_abort(CPU(dc-cpu), Invalid fetch size %d\n, size);
break;
}
return r;
@@ -1125,7 +1125,7 @@ static inline void cris_prepare_jmp (DisasContext *dc,
unsigned int type)
static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
{
-int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc-env)));
+int mem_index = cpu_mmu_index(CPU(dc-cpu));
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
@@ -1139,7 +1139,7 @@ static void gen_load64(DisasContext *dc, TCGv_i64 dst,
TCGv addr)
static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
unsigned int size, int sign)
{
-int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc-env)));
+int mem_index = cpu_mmu_index(CPU(dc-cpu));
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
@@ -1169,7 +1169,7 @@ static void gen_load(DisasContext *dc, TCGv dst, TCGv
addr,
static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
unsigned int size)
{
-int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc-env)));
+int mem_index = cpu_mmu_index(CPU(dc-cpu));
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
@@ -3191,7 +3191,7 @@ gen_intermediate_code_internal(CRISCPU *cpu,
TranslationBlock *tb,
* delayslot, like in real hw.
*/
pc_start = tb-pc ~1;
-dc-env = env;
+dc-cpu = cpu;
dc-tb = tb;
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
@@ -3412,7 +3412,7 @@ gen_intermediate_code_internal(CRISCPU *cpu,
TranslationBlock *tb,
#if !DISAS_CRIS
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
log_target_disas(env, pc_start, dc-pc - pc_start,
- dc-env-pregs[PR_VR]);
+ env-pregs[PR_VR]);
qemu_log(\nisize=%d osize=%td\n,
dc-pc - pc_start, tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf);
}
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 734225f..4d77f16 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -96,7 +96,7 @@ static void gen_store_v10_conditional(DisasContext *dc, TCGv
addr, TCGv val,
static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
unsigned int size)
{
-int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc-env)));
+int mem_index = cpu_mmu_index(CPU(dc-cpu));
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
@@ -340,7 +340,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
default:
LOG_DIS(pc=%x mode=%x quickimm %d r%d r%d\n,
dc-pc, dc-mode, dc-opcode, dc-src, dc-dst);
-cpu_abort(CPU(cris_env_get_cpu(dc-env)), Unhandled quickimm\n);
+cpu_abort(CPU(dc-cpu), Unhandled quickimm\n);
break;
}
return 2;
@@ -651,7 +651,7 @@ static unsigned int dec10_reg(DisasContext *dc)
case 2: tmp = 1; break;
case 1: tmp = 0; break;
default:
-cpu_abort(CPU(cris_env_get_cpu(dc-env)), Unhandled
BIAP);
+cpu_abort(CPU(dc-cpu), Unhandled BIAP);
break;
}
@@ -669,7 +669,7 @@ static unsigned int dec10_reg(DisasContext *dc)
default:
LOG_DIS(pc=%x reg %d r%d r%d\n, dc-pc,
dc-opcode, dc-src, dc-dst);
-cpu_abort(CPU(cris_env_get_cpu(dc-env)), Unhandled opcode
Re: [Qemu-devel] [RFC qom-cpu 03/41] cpu: Turn cpu_get_tb_cpu_state() into a CPUClass hook
Am 04.09.2013 12:26, schrieb Paolo Bonzini:
Il 04/09/2013 11:04, Andreas Färber ha scritto:
static inline TranslationBlock *tb_find_fast(CPUArchState *env)
{
+CPUState *cpu = ENV_GET_CPU(env);
+CPUClass *cc = CPU_GET_CLASS(cpu);
TranslationBlock *tb;
-target_ulong cs_base, pc;
+vaddr cs_base, pc;
int flags;
/* we record a subset of the CPU state. It will
always be the same before a given translated block
is executed. */
-cpu_get_tb_cpu_state(env, pc, cs_base, flags);
+cc-get_tb_cpu_state(cpu, pc, cs_base, flags);
I'm afraid you cannot turn inline functions into indirect calls like
this in hot paths.
One alternative would be to hoist the function call to the beginning of
cpu_exec, and ensure that any place that modifies the result calls
cpu_exit. It may be a problem for SPARC's npc stuff, for which I have
no idea how it works.
Sorry, you lost me here...
Another is to change cpu-exec.c into a file that is #included by
target-*/helper.c or something like that. This way cpu-exec.c can still
use the inline functions.
I don't see how that would help with compiling multiple CPU types into
one executable. A common CPU struct type is needed to compile the core
CPU code once, which in turn requires dispatching for target-specific
bits, such as this one or previously gdbstub and TBD monitor.
Combining only targets with target_ulong of the same size and identical
endianness is a restriction we can accept, I think - examples include
32-bit ARM+SH4A, ARM+MicroBlaze, ARM+Hexagon, ARM+Epiphany.
For performance reasons I have been careful not to have an, e.g.,
cpu_get_tb_cpu_state() wrapper that calls CPU_GET_CLASS() each time.
Many of the cpu variables added are being cleaned up later in the
series by argument propagation. And in placement of variables requiring
CPU() cast I have been careful to place them depending on where they
are/will be actually used rather than always placing them at the top.
But if behavior depends on the CPU type, then it cannot be a global
function - cpu.h as-is is a problem and needs to be broken up.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 0/8] [PATCH RFC v3] s390 cpu hotplug
Hello, Am 01.08.2013 16:12, schrieb Jason J. Herne: From: Jason J. Herne jjhe...@us.ibm.com Latest code for cpu Hotplug on S390 architecture. This one is vastly simpler than v2 as we have decided to avoid the command line specification of -device s390-cpu. The last version can be found here: http://lists.gnu.org/archive/html/qemu-devel/2013-06/msg01183.html There is also a patch in this series to add cpu-add to the Qemu monitor interface. Hotplugged cpus are created in the configured state and can be used by the guest after the guest onlines the cpu by: echo 1 /sys/bus/cpu/devices/cpuN/online Hot unplugging is currently not implemented by this code. We have been having several off-list discussions since then that I'll try to briefly summarize here, please correct or extend as needed: 1) CPU topology for QOM Physically a System z machine may have an MCM with, e.g., 6 CPUs with 6 cores each. But unlike x86, there is PR/SM, LPAR and possibly z/VM in between Linux and hardware, so we do actually want to be able to hot-plug in quantities of 1 and not by 6 on s390x for the foreseeable future. We seem willing to set a QOM ABI in stone based on that assumption. = s390-cpu (or future subtypes) to be used with device_add. = Flat /machine/cpu[n] list in composition tree a possibility. 1a) CPU topology for guests STSI instruction topology support not implemented yet. = Guest unaware of any emulated topology today. hyptop tool requires hypfs implementation for KVM. = Guest unaware of sibling VMs today, unlike z/VM and LPAR. 2) CPU hot-unplug Hotplug will always use a unique linear CPU address, even if hot-unplug leads to a sparse address space. = cpu_num != cpu_index With all that in mind, I'll now need to review the s390 patches again. For the HMP patch I am waiting on feedback from Igor once he returns from his vacation and, if there are no objections, would like to see that patch go through Luiz' queue since unrelated to s390x. Regards, Andreas Jason J. Herne (8): s390-qemu: cpu hotplug - Define New SCLP Codes s390-qemu: cpu hotplug - SCLP CPU Info s390-qemu: cpu hotplug - SCLP Event integration s390-qemu: cpu hotplug - Storage key global access s390-qemu: cpu hotplug - ipi_states enhancements s390-qemu: cpu hotplug - s390 cpu init improvements for hotplug s390-qemu: cpu hotplug - Implement hot_add_cpu hook qemu-monitor: HMP cpu-add wrapper hmp-commands.hx | 13 hmp.c | 10 hmp.h |1 + hw/s390x/Makefile.objs|2 +- hw/s390x/event-facility.c |7 +++ hw/s390x/s390-virtio-ccw.c|8 ++- hw/s390x/s390-virtio.c| 47 +-- hw/s390x/s390-virtio.h|2 +- hw/s390x/sclp.c | 53 +++- hw/s390x/sclpcpu.c| 120 + include/hw/s390x/event-facility.h |3 + include/hw/s390x/sclp.h | 41 + target-s390x/cpu.c| 36 ++- target-s390x/cpu.h|7 +++ target-s390x/helper.c | 12 15 files changed, 336 insertions(+), 26 deletions(-) create mode 100644 hw/s390x/sclpcpu.c -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [RFC qom-cpu 02/41] cpu: Turn cpu_mmu_index() into a CPUClass hook
Am 04.09.2013 14:42, schrieb Jia Liu: On Wed, Sep 4, 2013 at 5:04 PM, Andreas Färber afaer...@suse.de wrote: Default to 0. Signed-off-by: Andreas Färber afaer...@suse.de Paolo has indicated that patches 2 and 3 shouldn't be applied since they touch on TCG hot paths, replacing an inline function with a dispatched one, thereby possibly leading to performance regressions. Unfortunately that still means for me that I need to write a boilerplate inline function returning MMU index 0 for each of my new microcontroller targets... :/ Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 0/8] [PATCH RFC v3] s390 cpu hotplug
Am 04.09.2013 14:56, schrieb Luiz Capitulino: On Wed, 04 Sep 2013 14:45:44 +0200 Andreas Färber afaer...@suse.de wrote: For the HMP patch I am waiting on feedback from Igor once he returns from his vacation and, if there are no objections, would like to see that patch go through Luiz' queue since unrelated to s390x. I don't remember seeing that patch, I was CC'ed? Originally no, but you added a Reviewed-by after I CC'ed you. :) Apart from me not being familiar with the HMP infrastructure, I was wondering if there was a reason why this wasn't done from the start. So we don't have some only-new-QMP-commands policy and people are encouraged to implement an HMP command when they do a QMP command? Cheers, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] public key not found?
Am 04.09.2013 15:11, schrieb Anthony Liguori: On Wed, Sep 4, 2013 at 6:47 AM, Michael S. Tsirkin m...@redhat.com wrote: I noticed recent merges of the pci tree have this text: # gpg: Signature made Sun 01 Sep 2013 03:15:36 AM CDT using RSA key # ID D28D5469 # gpg: Can't check signature: public key not found Why is that? Because I haven't signed your key. We'll address this at this year's KVM Forum: http://wiki.qemu.org/KeySigningParty2013 Doesn't public key not found rather indicate that you have not imported that key to your keyring yet, not even with untrusted status? Some days ago I had asked about the indicated keyserver.cryptnet.net, which was ping'able but not reachable via http, https, ldap or hkp. Today there is a Fedora Apache test page via http, but still no success using that server with Seahorse. Eric was said to have succeeded in uploading his key there? Usually it is no problem configuring multiple key servers for you to obtain our (untrusted) keys to at least improve the error message. :) Regards, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 0/8] [PATCH RFC v3] s390 cpu hotplug
Am 05.09.2013 12:40, schrieb Christian Borntraeger: On 04/09/13 14:45, Andreas Färber wrote: Hello, Am 01.08.2013 16:12, schrieb Jason J. Herne: From: Jason J. Herne jjhe...@us.ibm.com Latest code for cpu Hotplug on S390 architecture. This one is vastly simpler than v2 as we have decided to avoid the command line specification of -device s390-cpu. The last version can be found here: http://lists.gnu.org/archive/html/qemu-devel/2013-06/msg01183.html There is also a patch in this series to add cpu-add to the Qemu monitor interface. Hotplugged cpus are created in the configured state and can be used by the guest after the guest onlines the cpu by: echo 1 /sys/bus/cpu/devices/cpuN/online Hot unplugging is currently not implemented by this code. We have been having several off-list discussions since then that I'll try to briefly summarize here, please correct or extend as needed: 1) CPU topology for QOM Physically a System z machine may have an MCM with, e.g., 6 CPUs with 6 cores each. But unlike x86, there is PR/SM, LPAR and possibly z/VM in between Linux and hardware, so we do actually want to be able to hot-plug in quantities of 1 and not by 6 on s390x for the foreseeable future. We seem willing to set a QOM ABI in stone based on that assumption. Just stepping in, Jason is on vacation this week. Everyone is welcome to comment. :) To summarize my understanding: You were thinking if CPU model needs topology (e.g. -device mcm,id=m1, -device cpu,mcm=m1) and s390 was the only arch left, that you were not sure about if topology is needed? All other platforms dont need topology for cpu hotplug? No, on the contrary: I don't want s390x to blindly copy x86 cpu-add, because for x86 we know that what we have is a hack to make it work today, but there we know we want to do device_add Xeon-X42-4242 instead, which then hot-plugs the 6 cores x 2 threads at once that a physical hot-plug would do and not hot-add individual threads. So the question of topology is not about what is below KVM but about what is inside QEMU, since x86 emulates i440fx/q35 based hardware. The understanding I reached on IRC is that s390x (similar to sPAPR) tries to emulate LPAR / z/VM layer rather than the hardware below them, thus no applicable concept of real hardware and arbitrary quantities. Yes, we want to be able to hotplug single cores (not chips, not MCMs). It is pretty hard to pin the vCPUs to a given real topology for KVM. You need to pin on LPAR and KVM. Libvirt could do some pinning of guest vCPUs to host CPUs and LPAR can have dedicated CPUs. But pinning a full chip (6cores) would only make sense in very rare cases. Last time I looked into this, the post-add hook was solely for overall ccw initialization. So we can use device_add s390-cpu today, can't we? The question that I still need to investigate is how the always-incrementing CPU address interacts with maxcpus. Consider maxcpus=6 and smp_cpus=2. 4x device_add should work. Now if we did 1x device_del, then 1x device_add should work again IMO. cpu-add checks the user-supplied id against maxcpus though iirc. Therefore my saying in multiple contexts that we should get the QEMU and KVM CPU count checks into the CPU realizefn so that we get the checks irrespective of the call site with nice error reporting. = s390-cpu (or future subtypes) to be used with device_add. = Flat /machine/cpu[n] list in composition tree a possibility. 1a) CPU topology for guests STSI instruction topology support not implemented yet. Right not implemented yet, but we certainly want to be able to define the guest visible topology at some point in time (grouping of cores basically). But I guess this does not mean that we have to go away from the flat list of CPUs. So STSI would show what real LPAR/CPU we are running on? But QEMU would have /machine/cpu[0]? Or do we need /machine/cpugroup[0]/cpu[0]? The latter is my concern here, to decide about child vs. link properties. To cope with device_add s390-cpu adding the device to /machine/peripheral/id or /machine/peripheral-anon/device[0] I *think* we'll need link, which would then translate back to ipi_states array as backend and the remaining question would be where to expose those properties in the composition tree - i.e. /machine/cpu[n] or /machine/ipi/cpu[n] or something - please suggest. Similarly if those become link properties then the CPUs created by the machine via smp_cpus need a canonical path as well; quite obviously both cannot be the same. Background is that long-term Anthony would like x86 CPU hot-plug to become setting/unsetting some /machine/cpu-socket[n] link property of the machine, and the ipi_states array seems a close equivalent on s390x. = Guest unaware of any emulated topology today. An additional problem is, that for the normal case (linux scheduler, no pinning, also no gang scheduling) the topology would change too fast. The guest would
Re: [Qemu-devel] [PATCH 1/8] [PATCH RFC v3] s390-qemu: cpu hotplug - Define New SCLP Codes
Am 01.08.2013 16:12, schrieb Jason J. Herne: From: Jason J. Herne jjhe...@us.ibm.com Define new SCLP codes to improve code readability. Signed-off-by: Jason J. Herne jjhe...@us.ibm.com s390-qemu: is really bad. For one, all QEMU patches are somehow about QEMU, so that's redundant. For another, sclp: would be much more telling to me which patches to look at than text disappearing at the end of the subject line in the mail client. :) Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 2/8] [PATCH RFC v3] s390-qemu: cpu hotplug - SCLP CPU Info
Am 01.08.2013 16:12, schrieb Jason J. Herne:
From: Jason J. Herne jjhe...@us.ibm.com
Implement the CPU data in SCLP Read SCP Info. And implement Read CPU Info
SCLP command. This data will be used by the guest to get information about hot
plugged cpus.
Signed-off-by: Jason J. Herne jjhe...@us.ibm.com
---
hw/s390x/sclp.c | 51
+++
include/hw/s390x/sclp.h | 32 +
2 files changed, 83 insertions(+)
diff --git a/hw/s390x/sclp.c b/hw/s390x/sclp.c
index cb53d7e..da8cf7a 100644
--- a/hw/s390x/sclp.c
+++ b/hw/s390x/sclp.c
@@ -15,6 +15,7 @@
#include cpu.h
#include sysemu/kvm.h
#include exec/memory.h
+#include sysemu/sysemu.h
#include hw/s390x/sclp.h
@@ -31,7 +32,26 @@ static inline S390SCLPDevice *get_event_facility(void)
static void read_SCP_info(SCCB *sccb)
{
ReadInfo *read_info = (ReadInfo *) sccb;
+CPUState *cpu;
int shift = 0;
+int cpu_count = 0;
+int i = 0;
+
+for (cpu = first_cpu; cpu != NULL; cpu = cpu-next_cpu) {
+cpu_count++;
+}
+
+/* CPU information */
+read_info-entries_cpu = cpu_to_be16(cpu_count);
+read_info-offset_cpu = cpu_to_be16(offsetof(ReadInfo, entries));
+read_info-highest_cpu = cpu_to_be16(max_cpus);
+
+for (i = 0; i cpu_count; i++) {
+read_info-entries[i].address = i;
+read_info-entries[i].type = 0;
+}
+
+read_info-facilities = cpu_to_be64(SCLP_HAS_CPU_INFO);
while ((ram_size (20 + shift)) 65535) {
shift++;
@@ -41,6 +61,34 @@ static void read_SCP_info(SCCB *sccb)
sccb-h.response_code = cpu_to_be16(SCLP_RC_NORMAL_READ_COMPLETION);
}
+/* Provide information about the CPU */
+static void sclp_read_cpu_info(SCCB *sccb)
+{
+ReadCpuInfo *cpu_info = (ReadCpuInfo *) sccb;
+CPUState *cpu;
+int cpu_count = 0;
+int i = 0;
+
+for (cpu = first_cpu; cpu != NULL; cpu = cpu-next_cpu) {
This becomes CPU_FOREACH(cpu) { now.
+cpu_count++;
+}
+
+cpu_info-nr_configured = cpu_to_be16(cpu_count);
+cpu_info-offset_configured = cpu_to_be16(offsetof(ReadCpuInfo,
entries));
+cpu_info-nr_standby = cpu_to_be16(0);
+
+/* The standby offset is 16-byte for each CPU */
+cpu_info-offset_standby = cpu_to_be16(cpu_info-offset_configured
++ cpu_info-nr_configured*sizeof(CpuEntry));
+
+for (i = 0; i cpu_count; i++) {
+cpu_info-entries[i].address = i;
+cpu_info-entries[i].type = 0;
+}
+
+sccb-h.response_code = cpu_to_be16(SCLP_RC_NORMAL_READ_COMPLETION);
+}
+
static void sclp_execute(SCCB *sccb, uint64_t code)
{
S390SCLPDevice *sdev = get_event_facility();
@@ -50,6 +98,9 @@ static void sclp_execute(SCCB *sccb, uint64_t code)
case SCLP_CMDW_READ_SCP_INFO_FORCED:
read_SCP_info(sccb);
break;
+case SCLP_CMDW_READ_CPU_INFO:
+sclp_read_cpu_info(sccb);
+break;
default:
sdev-sclp_command_handler(sdev-ef, sccb, code);
break;
diff --git a/include/hw/s390x/sclp.h b/include/hw/s390x/sclp.h
index 174097d..89ae7d1 100644
--- a/include/hw/s390x/sclp.h
+++ b/include/hw/s390x/sclp.h
@@ -79,12 +79,44 @@ typedef struct SCCBHeader {
#define SCCB_DATA_LEN (SCCB_SIZE - sizeof(SCCBHeader))
+/* CPU information */
+typedef struct CpuEntry {
+uint8_t address;
+uint8_t reserved0[13];
+uint8_t type;
+uint8_t reserved1;
+} QEMU_PACKED CpuEntry;
Feel free to use CPUEntry capitalization if this is not copied from a
Linux struct of that name - your choice.
Andreas
+
typedef struct ReadInfo {
SCCBHeader h;
uint16_t rnmax;
uint8_t rnsize;
+uint8_t _reserved1[16 - 11]; /* 11-15 */
+uint16_t entries_cpu; /* 16-17 */
+uint16_t offset_cpu;/* 18-19 */
+uint8_t _reserved2[24 - 20]; /* 20-23 */
+uint8_t loadparm[8]; /* 24-31 */
+uint8_t _reserved3[48 - 32]; /* 32-47 */
+uint64_t facilities;/* 48-55 */
+uint8_t _reserved0[100 - 56];
+uint32_t rnsize2;
+uint64_t rnmax2;
+uint8_t _reserved4[120-112]; /* 112-119 */
+uint16_t highest_cpu;
+uint8_t _reserved5[128 - 122]; /* 122-127 */
+struct CpuEntry entries[0];
} QEMU_PACKED ReadInfo;
+typedef struct ReadCpuInfo {
+SCCBHeader h;
+uint16_t nr_configured; /* 8-9 */
+uint16_t offset_configured; /* 10-11 */
+uint16_t nr_standby;/* 12-13 */
+uint16_t offset_standby;/* 14-15 */
+uint8_t reserved0[24-16]; /* 16-23 */
+struct CpuEntry entries[0];
+} QEMU_PACKED ReadCpuInfo;
+
typedef struct SCCB {
SCCBHeader h;
char data[SCCB_DATA_LEN];
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix
Re: [Qemu-devel] [PATCH 3/8] [PATCH RFC v3] s390-qemu: cpu hotplug - SCLP Event integration
Am 01.08.2013 16:12, schrieb Jason J. Herne:
From: Jason J. Herne jjhe...@us.ibm.com
Add an sclp event for cpu was hot plugged. This allows Qemu to deliver an
SCLP interrupt to the guest stating that the requested cpu hotplug was
completed.
Signed-off-by: Jason J. Herne jjhe...@us.ibm.com
---
hw/s390x/Makefile.objs|2 +-
hw/s390x/event-facility.c |7 +++
hw/s390x/sclpcpu.c| 120
+
include/hw/s390x/event-facility.h |3 +
include/hw/s390x/sclp.h |1 +
5 files changed, 132 insertions(+), 1 deletion(-)
create mode 100644 hw/s390x/sclpcpu.c
diff --git a/hw/s390x/Makefile.objs b/hw/s390x/Makefile.objs
index 77e1218..104ae8e 100644
--- a/hw/s390x/Makefile.objs
+++ b/hw/s390x/Makefile.objs
@@ -2,7 +2,7 @@ obj-y = s390-virtio-bus.o s390-virtio.o
obj-y += s390-virtio-hcall.o
obj-y += sclp.o
obj-y += event-facility.o
-obj-y += sclpquiesce.o
+obj-y += sclpquiesce.o sclpcpu.o
On a line of its own for consistency and to avoid '-' line?
obj-y += ipl.o
obj-y += css.o
obj-y += s390-virtio-ccw.o
diff --git a/hw/s390x/event-facility.c b/hw/s390x/event-facility.c
index 0faade0..aec35cb 100644
--- a/hw/s390x/event-facility.c
+++ b/hw/s390x/event-facility.c
@@ -317,6 +317,7 @@ static int init_event_facility(S390SCLPDevice *sdev)
{
SCLPEventFacility *event_facility;
DeviceState *quiesce;
+DeviceState *cpu_hotplug;
event_facility = g_malloc0(sizeof(SCLPEventFacility));
sdev-ef = event_facility;
@@ -335,6 +336,12 @@ static int init_event_facility(S390SCLPDevice *sdev)
}
qdev_init_nofail(quiesce);
+cpu_hotplug = qdev_create(event_facility-sbus.qbus, sclpcpuhotplug);
Please don't create devices in such an init function. Also don't access
.qbus please.
Instead, please use object_initialize() followed by
qdev_set_parent_bus() in an instance_init function.
Conversion of the initfn to a realizefn will be a bit more involved so I
won't ask that for this series, but if there were volunteers among your
colleagues that would be appreciated. The effect would be to propagate
errors to the caller of the realizefn rather than asserting here.
+if (!cpu_hotplug) {
+return -1;
+}
+qdev_init_nofail(cpu_hotplug);
+
return 0;
}
diff --git a/hw/s390x/sclpcpu.c b/hw/s390x/sclpcpu.c
new file mode 100644
index 000..5b4139e
--- /dev/null
+++ b/hw/s390x/sclpcpu.c
@@ -0,0 +1,120 @@
+/*
+ * SCLP event type
+ *Signal CPU - Trigger SCLP interrupt for system CPU configure or
+ *de-configure
+ *
+ * Copyright IBM, Corp. 2013
+ *
+ * Authors:
+ * Thang Pham thang.p...@us.ibm.com
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at
your
+ * option) any later version. See the COPYING file in the top-level
directory.
+ *
+ */
+#include hw/qdev.h
hw/qdev.h, but I'm guessing that's redundant with either sclp.h or
event-facility.h?
+#include sysemu/sysemu.h
+#include hw/s390x/sclp.h
+#include hw/s390x/event-facility.h
+#include cpu.h
+#include sysemu/cpus.h
+#include sysemu/kvm.h
+
+typedef struct ConfigMgtData {
+EventBufferHeader ebh;
+uint8_t reserved;
+uint8_t event_qualifier;
+} QEMU_PACKED ConfigMgtData;
+
+static qemu_irq irq_cpu_hotplug; /* Only used in this file */
+
+#define EVENT_QUAL_CPU_CHANGE 1
+
+void raise_irq_cpu_hotplug(void)
+{
+qemu_irq_raise(irq_cpu_hotplug);
+}
+
+static int event_type(void)
+{
+return SCLP_EVENT_CONFIG_MGT_DATA;
+}
+
+static unsigned int send_mask(void)
+{
+return SCLP_EVENT_MASK_CONFIG_MGT_DATA;
+}
+
+static unsigned int receive_mask(void)
+{
+return 0;
+}
+
+static int read_event_data(SCLPEvent *event, EventBufferHeader *evt_buf_hdr,
+ int *slen)
+{
+ConfigMgtData *cdata = (ConfigMgtData *) evt_buf_hdr;
+if (*slen sizeof(ConfigMgtData)) {
+return 0;
+}
+
+/* Event is no longer pending */
+if (!event-event_pending) {
+return 0;
+}
+event-event_pending = false;
+
+/* Event header data */
+cdata-ebh.length = cpu_to_be16(sizeof(ConfigMgtData));
+cdata-ebh.type = SCLP_EVENT_CONFIG_MGT_DATA;
+cdata-ebh.flags |= SCLP_EVENT_BUFFER_ACCEPTED;
+
+/* Trigger a rescan of CPUs by setting event qualifier */
+cdata-event_qualifier = EVENT_QUAL_CPU_CHANGE;
+*slen -= sizeof(ConfigMgtData);
+
+return 1;
+}
+
+static void trigger_signal(void *opaque, int n, int level)
+{
+SCLPEvent *event = opaque;
+event-event_pending = true;
+
+/* Trigger SCLP read operation */
+sclp_service_interrupt(0);
+}
+
+static int irq_cpu_hotplug_init(SCLPEvent *event)
+{
+irq_cpu_hotplug = *qemu_allocate_irqs(trigger_signal, event, 1);
+return 0;
+}
+
+static void cpu_class_init(ObjectClass *klass, void *data)
+{
+
Re: [Qemu-devel] [PATCH 4/8] [PATCH RFC v3] s390-qemu: cpu hotplug - Storage key global access
Am 01.08.2013 16:12, schrieb Jason J. Herne:
From: Jason J. Herne jjhe...@us.ibm.com
Introduces global access to storage key data so we can set it for each cpu in
the S390 cpu initialization routine.
Signed-off-by: Jason J. Herne jjhe...@us.ibm.com
---
hw/s390x/s390-virtio-ccw.c |5 ++---
hw/s390x/s390-virtio.c | 21 -
hw/s390x/s390-virtio.h |2 +-
target-s390x/cpu.h |4
4 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index aebbbf1..b469960 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -65,7 +65,6 @@ static void ccw_init(QEMUMachineInitArgs *args)
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
int shift = 0;
-uint8_t *storage_keys;
int ret;
VirtualCssBus *css_bus;
@@ -94,10 +93,10 @@ static void ccw_init(QEMUMachineInitArgs *args)
memory_region_add_subregion(sysmem, 0, ram);
/* allocate storage keys */
-storage_keys = g_malloc0(my_ram_size / TARGET_PAGE_SIZE);
+s390_alloc_storage_keys(my_ram_size);
/* init CPUs */
-s390_init_cpus(args-cpu_model, storage_keys);
+s390_init_cpus(args-cpu_model);
if (kvm_enabled()) {
kvm_s390_enable_css_support(s390_cpu_addr2state(0));
diff --git a/hw/s390x/s390-virtio.c b/hw/s390x/s390-virtio.c
index 439d732..21e9124 100644
--- a/hw/s390x/s390-virtio.c
+++ b/hw/s390x/s390-virtio.c
@@ -123,6 +123,18 @@ static void s390_virtio_register_hcalls(void)
s390_virtio_hcall_set_status);
}
+static uint8_t *storage_keys;
+
+uint8_t *s390_get_storage_keys(void)
+{
+return storage_keys;
+}
+
+void s390_alloc_storage_keys(ram_addr_t ram_size)
+{
+storage_keys = g_malloc0(ram_size / TARGET_PAGE_SIZE);
+}
+
/*
* The number of running CPUs. On s390 a shutdown is the state of all CPUs
* being either stopped or disabled (for interrupts) waiting. We have to
@@ -176,7 +188,7 @@ void s390_init_ipl_dev(const char *kernel_filename,
qdev_init_nofail(dev);
}
-void s390_init_cpus(const char *cpu_model, uint8_t *storage_keys)
+void s390_init_cpus(const char *cpu_model)
{
int i;
@@ -196,7 +208,7 @@ void s390_init_cpus(const char *cpu_model, uint8_t
*storage_keys)
ipi_states[i] = cpu;
cs-halted = 1;
cpu-env.exception_index = EXCP_HLT;
-cpu-env.storage_keys = storage_keys;
+cpu-env.storage_keys = s390_get_storage_keys();
Why not go this from the CPU initfn? Is there any ccw- vs. non-ccw
difference? Thinking about -device s390-cpu here. I believe it's safe to
assume that machine init and thus allocation has run before the CPU is
instantiated - possibly assert that.
Andreas
}
}
@@ -231,7 +243,6 @@ static void s390_init(QEMUMachineInitArgs *args)
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
int shift = 0;
-uint8_t *storage_keys;
void *virtio_region;
hwaddr virtio_region_len;
hwaddr virtio_region_start;
@@ -270,10 +281,10 @@ static void s390_init(QEMUMachineInitArgs *args)
virtio_region_len);
/* allocate storage keys */
-storage_keys = g_malloc0(my_ram_size / TARGET_PAGE_SIZE);
+s390_alloc_storage_keys(my_ram_size);
/* init CPUs */
-s390_init_cpus(args-cpu_model, storage_keys);
+s390_init_cpus(args-cpu_model);
/* Create VirtIO network adapters */
s390_create_virtio_net((BusState *)s390_bus, virtio-net-s390);
diff --git a/hw/s390x/s390-virtio.h b/hw/s390x/s390-virtio.h
index 5c405e7..c1cb042 100644
--- a/hw/s390x/s390-virtio.h
+++ b/hw/s390x/s390-virtio.h
@@ -20,7 +20,7 @@
typedef int (*s390_virtio_fn)(const uint64_t *args);
void s390_register_virtio_hypercall(uint64_t code, s390_virtio_fn fn);
-void s390_init_cpus(const char *cpu_model, uint8_t *storage_keys);
+void s390_init_cpus(const char *cpu_model);
void s390_init_ipl_dev(const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 65bef86..877eac7 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -374,6 +374,10 @@ static inline void kvm_s390_interrupt_internal(S390CPU
*cpu, int type,
{
}
#endif
+
+uint8_t *s390_get_storage_keys(void);
+void s390_alloc_storage_keys(ram_addr_t ram_size);
+
S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
void s390_add_running_cpu(S390CPU *cpu);
unsigned s390_del_running_cpu(S390CPU *cpu);
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 5/8] [PATCH RFC v3] s390-qemu: cpu hotplug - ipi_states enhancements
Am 01.08.2013 16:12, schrieb Jason J. Herne:
From: Jason J. Herne jjhe...@us.ibm.com
Modify s390_cpu_addr2state to allow fetching state information for cpu
addresses
above smp_cpus. Hotplug requires this capability.
Also add s390_cpu_set_state function to allow modification of ipi_state
entries
during hotplug.
Signed-off-by: Jason J. Herne jjhe...@us.ibm.com
---
hw/s390x/s390-virtio.c |9 +
target-s390x/cpu.h |2 +-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/s390x/s390-virtio.c b/hw/s390x/s390-virtio.c
index 21e9124..5ad9cf3 100644
--- a/hw/s390x/s390-virtio.c
+++ b/hw/s390x/s390-virtio.c
@@ -54,12 +54,13 @@
static VirtIOS390Bus *s390_bus;
static S390CPU **ipi_states;
-S390CPU *s390_cpu_addr2state(uint16_t cpu_addr)
+void s390_cpu_set_ipistate(uint16_t cpu_addr, S390CPU *state)
{
-if (cpu_addr = smp_cpus) {
-return NULL;
-}
+ipi_states[cpu_addr] = state;
+}
+S390CPU *s390_cpu_addr2state(uint16_t cpu_addr)
+{
return ipi_states[cpu_addr];
}
This is what got us into the link discussion last time. If we do
for (i = 0; i ARRAY_SIZE(ipi_states); i++) {
name = g_strdup_printf(cpu[%i], i);
object_property_add_link(qdev_get_machine(), name, TYPE_S390_CPU,
ipi_states[i], err);
}
then we get said /machine/cpu[n] link properties, at a QMP level
either returning nothing or the canonical path to the CPU object.
On IRC I didn't get an answer of whether it was being done the above way
because there is infrastructure missing, and a look at object.h now
confirms that suspicion. CC'ing Anthony and Paolo.
Since object_property_add_link() uses a NULL opaque, my idea would be to
add a single setter hook argument passed through as opaque to
object_set_link_property(), which would call it with the old and the new
value.
The purpose would be to avoid growing our own internal setter API, which
is disjoint from the QMP qom-set we are targetting at.
Regards,
Andreas
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 877eac7..62eb810 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -377,7 +377,7 @@ static inline void kvm_s390_interrupt_internal(S390CPU
*cpu, int type,
uint8_t *s390_get_storage_keys(void);
void s390_alloc_storage_keys(ram_addr_t ram_size);
-
+void s390_cpu_set_ipistate(uint16_t cpu_addr, S390CPU *state);
S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
void s390_add_running_cpu(S390CPU *cpu);
unsigned s390_del_running_cpu(S390CPU *cpu);
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 6/8] [PATCH RFC v3] s390-qemu: cpu hotplug - s390 cpu init improvements for hotplug
Am 01.08.2013 16:12, schrieb Jason J. Herne:
From: Jason J. Herne jjhe...@us.ibm.com
s390_new_cpu is created to encapsulate the creation of a new QOM S390CPU
object given a cpuid and a model string.
All actual cpu initialization code is moved from boot time specific
functions to
s390_cpu_initfn (qom init routine) or to s390_new_cpu. This is done to
allow us
to use the same basic code path for a cpu created at boot time and one
created
during a hotplug operation.
Intentionally indented?
Signed-off-by: Jason J. Herne jjhe...@us.ibm.com
---
hw/s390x/s390-virtio.c | 25 -
target-s390x/cpu.c |4 ++--
target-s390x/cpu.h |1 +
target-s390x/helper.c | 12
4 files changed, 27 insertions(+), 15 deletions(-)
diff --git a/hw/s390x/s390-virtio.c b/hw/s390x/s390-virtio.c
index 5ad9cf3..103f32e 100644
--- a/hw/s390x/s390-virtio.c
+++ b/hw/s390x/s390-virtio.c
@@ -56,11 +56,16 @@ static S390CPU **ipi_states;
void s390_cpu_set_ipistate(uint16_t cpu_addr, S390CPU *state)
{
-ipi_states[cpu_addr] = state;
+if (cpu_addr max_cpus) {
+ipi_states[cpu_addr] = state;
+}
}
S390CPU *s390_cpu_addr2state(uint16_t cpu_addr)
{
+if (cpu_addr = max_cpus) {
+return NULL;
+}
return ipi_states[cpu_addr];
}
@@ -197,19 +202,13 @@ void s390_init_cpus(const char *cpu_model)
cpu_model = host;
}
-ipi_states = g_malloc(sizeof(S390CPU *) * smp_cpus);
-
-for (i = 0; i smp_cpus; i++) {
-S390CPU *cpu;
-CPUState *cs;
+ipi_states = g_malloc(sizeof(S390CPU *) * max_cpus);
-cpu = cpu_s390x_init(cpu_model);
-cs = CPU(cpu);
-
-ipi_states[i] = cpu;
-cs-halted = 1;
-cpu-env.exception_index = EXCP_HLT;
-cpu-env.storage_keys = s390_get_storage_keys();
+for (i = 0; i max_cpus; i++) {
+ipi_states[i] = NULL;
Using g_malloc0() above would hopefully be more efficient and would
allow to leave the loop untouched for easier review.
+if (i smp_cpus) {
+s390_new_cpu(cpu_model, i);
+}
}
}
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 6be6c08..c90a91c 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -116,7 +116,6 @@ static void s390_cpu_initfn(Object *obj)
S390CPU *cpu = S390_CPU(obj);
CPUS390XState *env = cpu-env;
static bool inited;
-static int cpu_num = 0;
#if !defined(CONFIG_USER_ONLY)
struct tm tm;
#endif
@@ -135,8 +134,9 @@ static void s390_cpu_initfn(Object *obj)
* cpu counter in s390_cpu_reset to a negative number at
* initial ipl */
cs-halted = 1;
+cpu-env.exception_index = EXCP_HLT;
+env-storage_keys = s390_get_storage_keys();
4/8?
#endif
-env-cpu_num = cpu_num++;
env-ext_index = -1;
if (tcg_enabled() !inited) {
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 62eb810..0f68dd0 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -315,6 +315,7 @@ static inline int get_ilen(uint8_t opc)
#endif
S390CPU *cpu_s390x_init(const char *cpu_model);
+S390CPU *s390_new_cpu(const char *cpu_model, int64_t cpuid);
void s390x_translate_init(void);
int cpu_s390x_exec(CPUS390XState *s);
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 61abfd7..a39b148 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -70,6 +70,18 @@ void s390x_cpu_timer(void *opaque)
}
#endif
+S390CPU *s390_new_cpu(const char *cpu_model, int64_t cpuid)
Like I said on IRC, I'm not so fond of copying x86 workarounds here...
x86 does not have a fully QOM'ified CPU, s390x does.
+{
+S390CPU *cpu;
+
+cpu = cpu_s390x_init(cpu_model);
+cpu-env.cpu_num = cpuid;
linux-user never calls s390_new_cpu(), so it will change behavior in
always having cpu_num of 0. I guess we can live with that but such a
change needs to be mentioned in the commit message at least.
Why is this moved to after CPU init? Can't we just override the field if
need be? Either Jens or Christian said that we would not want to fill up
holes in ipi_tables to have the CPU address be always unique; which
would mean that it would always be counting as before. if we need to
tweak it, we should add a property to be able to set it from command
line and QMP.
This affects migration btw: We would need to migrate the current or next
CPU address since the last CPU might've been hot-unplugged so that next
CPU address != last non-NULL ipi_states[] slot plus one.
+#if !defined(CONFIG_USER_ONLY)
+s390_cpu_set_ipistate(cpuid, cpu);
+#endif
...leaving only this then. Why not do this from the CPU realizefn so
that errors actually can be propagated? If cpuid = max_cpus the above
will silently do nothing.
In that case we don't need this function any longer.
+return cpu;
+}
+
S390CPU
Re: [Qemu-devel] [PATCH 7/8] [PATCH RFC v3] s390-qemu: cpu hotplug - Implement hot_add_cpu hook
Am 01.08.2013 16:12, schrieb Jason J. Herne:
From: Jason J. Herne jjhe...@us.ibm.com
Implement hot_add_cpu for S390 to allow hot plugging of cpus.
Signed-off-by: Jason J. Herne jjhe...@us.ibm.com
---
hw/s390x/s390-virtio-ccw.c |3 +++
target-s390x/cpu.c | 32
target-s390x/cpu.h |2 ++
3 files changed, 37 insertions(+)
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index b469960..30b6a48 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -117,6 +117,9 @@ static QEMUMachine ccw_machine = {
.alias = s390-ccw,
.desc = VirtIO-ccw based S390 machine,
.init = ccw_init,
+#if !defined(CONFIG_USER_ONLY)
+.hot_add_cpu = ccw_hot_add_cpu,
+#endif
I doubt this #ifdeffery is necessary here?
.block_default_type = IF_VIRTIO,
.no_cdrom = 1,
.no_floppy = 1,
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index c90a91c..60029d9 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -27,6 +27,8 @@
#include qemu-common.h
#include qemu/timer.h
#include hw/hw.h
+#include hw/s390x/sclp.h
+#include sysemu/sysemu.h
#ifndef CONFIG_USER_ONLY
#include sysemu/arch_init.h
#endif
@@ -154,6 +156,36 @@ static void s390_cpu_finalize(Object *obj)
#endif
}
+#if !defined(CONFIG_USER_ONLY)
+void ccw_hot_add_cpu(const int64_t id, Error **errp)
+{
+S390CPU *new_cpu;
+CPUState *cpu;
+const char *model_str;
+int cpu_count = 0;
+
+for (cpu = first_cpu; cpu != NULL; cpu = cpu-next_cpu) {
CPU_FOREACH(cpu) {
+cpu_count++;
+}
+
+if (cpu_count == max_cpus) {
+error_setg(errp, Maximum number of cpus already defined);
+return;
+}
+
+if (id != cpu_count) {
+error_setg(errp, Unable to add CPU: % PRIi64
+ , The next available id is %d, id, cpu_count);
+return;
+}
This logic seems wrong according to your colleagues. It should be
checking against the static cpu_num counter or not checking at all if we
want to allow explicit device_add s390-cpu,cpu-num=42.
+
+model_str = s390_cpu_addr2state(0)-env.cpu_model_str;
+new_cpu = s390_new_cpu(model_str, id);
As announced, a patch in my large series finally sent out removes
cpu_model_str field. Since we don't have any for s390x, I suggest that
you use the QOM constructs so that device_add works as well, i.e.
new_cpu = object_new(TYPE_S390_CPU).
+object_property_set_bool(OBJECT(new_cpu), true, realized, NULL);
+raise_irq_cpu_hotplug();
This would mean moving this line into the realizefn, conditional on
dev-hotplugged (and probably #ifndef CONFIG_USER_ONLY).
Regards,
Andreas
+}
+#endif
+
static const VMStateDescription vmstate_s390_cpu = {
.name = cpu,
.unmigratable = 1,
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 0f68dd0..711aad4 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -383,6 +383,8 @@ S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
void s390_add_running_cpu(S390CPU *cpu);
unsigned s390_del_running_cpu(S390CPU *cpu);
+void ccw_hot_add_cpu(const int64_t id, Error **errp);
+
/* service interrupts are floating therefore we must not pass an cpustate */
void s390_sclp_extint(uint32_t parm);
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 0/8] [PATCH RFC v3] s390 cpu hotplug
Am 05.09.2013 14:54, schrieb Alexander Graf: On 01.08.2013, at 16:12, Jason J. Herne wrote: From: Jason J. Herne jjhe...@us.ibm.com Latest code for cpu Hotplug on S390 architecture. This one is vastly simpler than v2 as we have decided to avoid the command line specification of -device s390-cpu. The last version can be found here: http://lists.gnu.org/archive/html/qemu-devel/2013-06/msg01183.html There is also a patch in this series to add cpu-add to the Qemu monitor interface. Hotplugged cpus are created in the configured state and can be used by the guest after the guest onlines the cpu by: echo 1 /sys/bus/cpu/devices/cpuN/online Hot unplugging is currently not implemented by this code. Very simple and clean patch set. I don't think it deserves the RFC tag. Negative, see my review. If you want to fix up and queue patches 1-2 that's fine with me, but the others need a respin. No major blocker though, just some more footwork mostly related to QOM and Jason's shifted focus on cpu-add rather than device_add. Open issues: * Might ipi_states need to become a device due to migration? * QOM properties considerations * Device creation in qdev initfn * Parent field access * QOM-unfriendly creation and reliance upon helper function Andreas Apart from the minor comments I had consider it Reviewed-by: Alexander Graf ag...@suse.de Alex -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v6] powerpc: add PVR mask support
Am 05.09.2013 08:01, schrieb Alexey Kardashevskiy:
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant change
in behavior between versions, there is no point to add every single CPU
version in QEMU's CPU list. Also, new CPU versions of already supported
CPU won't break the existing code.
This adds PVR value/mask support for KVM, i.e. for -cpu host option.
As CPU family class name for POWER7 is POWER7-family, there is no need
to touch aliases.
Cc: Andreas Färber afaer...@suse.de
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Changes:
v6:
* family classes are abstract again
* POWER7+ moved to a separate patch as it also need a separate family
* added ppc_cpu_class_by_pvr_mask() which is a copy of
ppc_cpu_class_by_pvr() but compares PVRs with masks; this function is
called from KVM code only to support the -cpu host option; unlike
the original search function, the new one also includes abstract family
classes.
v5:
* removed pvr_default
* added hiding of family CPU classes (should not appear in -cpu ?)
* separated POWER7+ into a class (it used to be POWER7) and added a mask for
it
* added mask for POWER8
* added _BASE suffix to PVR mask constants and moved them before actual CPUs
v4:
* removed bogus layer from hierarchy
v3:
* renamed macros to describe the functionality better
* added default PVR value for the powerpc cpu family (what alias used to do)
v2:
* aliases are replaced with another level in class hierarchy
---
target-ppc/cpu-models.c | 1 +
target-ppc/cpu-models.h | 5 +
target-ppc/cpu-qom.h| 2 ++
target-ppc/kvm.c| 4
target-ppc/translate_init.c | 45
-
5 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index 8dea560..04d88c5 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -44,6 +44,7 @@
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); \
\
pcc-pvr = _pvr; \
+pcc-pvr_mask = CPU_POWERPC_DEFAULT_MASK; \
pcc-svr = _svr; \
dc-desc = _desc; \
} \
diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
index d9145d1..731ec4a 100644
--- a/target-ppc/cpu-models.h
+++ b/target-ppc/cpu-models.h
@@ -39,6 +39,7 @@ extern PowerPCCPUAlias ppc_cpu_aliases[];
/*/
/* PVR definitions for most known PowerPC
*/
enum {
+CPU_POWERPC_DEFAULT_MASK = 0x,
/* PowerPC 401 family */
/* Generic PowerPC 401 */
#define CPU_POWERPC_401 CPU_POWERPC_401G2
@@ -552,10 +553,14 @@ enum {
CPU_POWERPC_POWER6 = 0x003E,
CPU_POWERPC_POWER6_5 = 0x0F01, /* POWER6 in POWER5 mode */
CPU_POWERPC_POWER6A= 0x0F02,
+CPU_POWERPC_POWER7_BASE= 0x003F,
+CPU_POWERPC_POWER7_MASK= 0x,
CPU_POWERPC_POWER7_v20 = 0x003F0200,
CPU_POWERPC_POWER7_v21 = 0x003F0201,
CPU_POWERPC_POWER7_v23 = 0x003F0203,
CPU_POWERPC_POWER7P_v21= 0x004A0201,
+CPU_POWERPC_POWER8_BASE= 0x004B,
+CPU_POWERPC_POWER8_MASK= 0x,
CPU_POWERPC_POWER8_v10 = 0x004B0100,
CPU_POWERPC_970= 0x00390202,
CPU_POWERPC_970FX_v10 = 0x00391100,
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index f3c710a..3f82629 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -54,6 +54,7 @@ typedef struct PowerPCCPUClass {
void (*parent_reset)(CPUState *cpu);
uint32_t pvr;
+uint32_t pvr_mask;
uint32_t svr;
uint64_t insns_flags;
uint64_t insns_flags2;
@@ -99,6 +100,7 @@ static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
#define ENV_OFFSET offsetof(PowerPCCPU, env)
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
+PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
void ppc_cpu_do_interrupt(CPUState *cpu);
void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 8a196c6..d10dba2 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1732,6 +1732,7 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc,
void *data)
uint32_t icache_size = kvmppc_read_int_cpu_dt(i-cache-size);
/* Now fix up
Re: [Qemu-devel] [PATCH 0/8] [PATCH RFC v3] s390 cpu hotplug
Am 05.09.2013 15:10, schrieb Alexander Graf: On 05.09.2013, at 15:05, Andreas Färber wrote: Am 05.09.2013 14:54, schrieb Alexander Graf: Very simple and clean patch set. I don't think it deserves the RFC tag. Negative, see my review. If you want to fix up and queue patches 1-2 that's fine with me, but the others need a respin. No major blocker though, just some more footwork mostly related to QOM and Jason's shifted focus on cpu-add rather than device_add. Yeah, that's what I'm referring to. I've seen a lot worse patch sets at v8 than this RFC :). I don't think we should apply it as is, and I'm very happy to see your review and comment on the modeling bits :). But I try to never apply or cherry pick RFC patches - and this set looks like he sent it with the intent of getting it merged. Agreed, we can continue with PATCH v4. I was more upset about the very simple and clean bit after I commented on a number of unclean things to improve - mostly about doing things in different places. If you could find some time to review my two model string patches then I could supply Jason with a branch or even a pull to base on: http://patchwork.ozlabs.org/patch/272511/ http://patchwork.ozlabs.org/patch/272509/ I would also volunteer to provide a base patch for the link issue if there is agreement. Apart from the QOM API question this depends on the contradictory modelling of whether we allow CPU addresses 0..max_cpus as seen in this series or 0..somemax with = max_cpus non-NULL as discussed on #zkvm. (childs390-cpu properties would allow to model the latter sparse address space very well, but an object can only have one parent in the hot-add case. We could of course add cpu[n] links390-cpu properties as CPUs get added, but that doesn't strike me as very clean. My underlying thought is to offload the error handling to QOM so that we don't start hardcoding s/smp_cpus/max_cpus/g (or some max_cpu_address) all around ipi_states.) Btw an unanswered question: ipi_states is just pointers to CPUs currently, no further state. So what's ipi in the name? Will that array need to carry state beyond S390CPU someday? Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [RFC PATCH] spapr: support time base offset migration
Am 05.09.2013 15:39, schrieb Alexander Graf: On 05.09.2013, at 15:36, Benjamin Herrenschmidt wrote: On Thu, 2013-09-05 at 14:37 +0200, Alexander Graf wrote: Hrm, I think I'm starting to understand what this is about. So what we want is - timebase in guest - timebase frequency in guest - wall clock time in host That way the receiving end can then take the timebase and add (new_timebase - old_timebase) * tb_freq to the guest's time base. Which gets me to the next question. Can we modify the tb frequency in guests? No. It's architected at 512Mhz however since P7 I think. Not sure how we did before, it's possible that P6 was the same (at least it's sourced from more/less the same chip TOD facility). I think we should transmit the tb frequency as well to at least allow us to adjust if a later chip derives here. Are you thinking of POWER8 having a different frequency than POWER8 in compat mode? Because migration from one -cpu to another is not supported elsewhere. Even if we want to migrate from one POWER7 revision to another, we should let the destination use the revision of the source (guest ABI!), via property if need be. Anything else will lead to confusion as to what is supported and what is not. That -cpu host is the default for convenience shouldn't relieve admins/libvirt to think about sensible setups like they have to on x86. Andreas But yes, without frequency adjustment I see where you're coming from. We still only need the timebase the guest sees, not the offset. But we also need the host wall clock to allow for adjustments :). Alex -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] Change email address
Am 05.09.2013 14:30, schrieb Peter Maydell: On 19 August 2013 14:51, Anthony Liguori anth...@codemonkey.ws wrote: My IBM email address will be unaccessible after August 23rd, 2013. Signed-off-by: Anthony Liguori anth...@codemonkey.ws --- a/.mailmap +++ b/.mailmap @@ -2,7 +2,7 @@ # into proper addresses so that they are counted properly in git shortlog output. # Andrzej Zaborowski balr...@gmail.com balrog balrog@c046a42c-6fe2-441c-8c8c-71466251a162 -Anthony Liguori aligu...@us.ibm.com aliguori aliguori@c046a42c-6fe2-441c-8c8c-71466251a162 +Anthony Liguori anth...@codemonkey.ws aliguori aliguori@c046a42c-6fe2-441c-8c8c-71466251a162 I've only just noticed this, but you probably want to also add a line mapping your IBM address to your new one: Anthony Liguori anth...@codemonkey.ws Anthony Liguori aligu...@us.ibm.com (perhaps in a new section at the bottom for people who've changed their addresses). Igor Mitsyanko would be another candidate for such a section, CC'ed. As well as making the git shortlog -nse stats look better, Actually I find it convenient to have my work and other commits counted separately in the -nse stats. You can use -ns for the combined stats. On a related MAINTAINERS matter, Paul Brook's emails have been bouncing and he hasn't replied via IRC or private mail so far. If anyone else can reach him and/or fix MAINTAINERS that would be appreciated. (me, I mostly care about automatic CC'ing ;-)) Cheers, Andreas scripts/get_maintainer.pl consults mailmap, so it will mean people using its grab emails from affected commits feature won't use your old email by mistake. (me, I mostly care about the stats scoreboard ;-)) thanks -- PMM -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] target-arm: Implement qmp query-cpu-definitions
Hi, Am 04.09.2013 17:23, schrieb Cole Robinson: Libvirt uses this to introspect available CPU models. Signed-off-by: Cole Robinson crobi...@redhat.com --- Maybe this will be centrally handled after the QOM CPU work is done? No, this API is about a pre-QOM command line switch, whose implementation is target-specific. What got standardized for multiple targets was the CPUClass::class_by_name() hook for the opposite direction of -cpu to ObjectClass lookup (with the goal of obsoleting cpu_init()). It is not wrong to implement query-cpus for arm, but -cpu is considered deprecated. And personally especially for arm I would rather welcome someone contributing a proper, e.g., Raspberry Pi board (with clean separation of what is on the SoC and what on the board to avoid duplication among boards) than tweaking some other unrelated board with -cpu and then complaining that it doesn't work as expected. ;) For machines that use soft-core CPUs (FPGAs) or for mach-virt as non-physical machine it does make sense, but query-cpus gives us a list irrespective of whether they are compatible with the board. Same for ppc btw - plugging, e.g., a 440 CPU into pseries or mac99 won't work. Short-term my view is to use fixed CPU types, ignoring -cpu, where the CPU cannot be exchanged (e.g., DIGIC patch series) and a suitable link type otherwise. The long-term goal is to have machines be config files (thereby user-creatable) assembling QOM objects by specifying memory mapping and IRQ routing. The latter two parts don't work with the old qdev and SysBusDevice APIs. That said, patch itself looks correct, Reviewed-by: Andreas Färber afaer...@suse.de Regards, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [RFC v4 1/5] hw/arm: add very initial support for Canon DIGIC SoC
Am 05.09.2013 09:52, schrieb Antony Pavlov:
DIGIC is Canon Inc.'s name for a family of SoC
for digital cameras and camcorders.
There is no publicly available specification for
DIGIC chips. All information about DIGIC chip
internals is based on reverse engineering efforts
made by CHDK (http://chdk.wikia.com) and
Magic Lantern (http://www.magiclantern.fm) projects
contributors.
Signed-off-by: Antony Pavlov antonynpav...@gmail.com
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs| 2 +-
hw/arm/digic.c | 70
+
include/hw/arm/digic.h | 23 ++
4 files changed, 95 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/digic.c
create mode 100644 include/hw/arm/digic.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index ac0815d..0d1d783 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -63,6 +63,7 @@ CONFIG_FRAMEBUFFER=y
CONFIG_XILINX_SPIPS=y
CONFIG_A9SCU=y
+CONFIG_DIGIC=y
CONFIG_MARVELL_88W8618=y
CONFIG_OMAP=y
CONFIG_TSC210X=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 3671b42..e140485 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -3,5 +3,5 @@ obj-y += integratorcp.o kzm.o mainstone.o musicpal.o nseries.o
obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
obj-y += tosa.o versatilepb.o vexpress.o xilinx_zynq.o z2.o
-obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
+obj-y += armv7m.o digic.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
Please place it on a line of its own, using
obj-$(CONFIG_DIGIC) += digic.o
obj-y += omap1.o omap2.o strongarm.o
diff --git a/hw/arm/digic.c b/hw/arm/digic.c
new file mode 100644
index 000..95a9fcd
--- /dev/null
+++ b/hw/arm/digic.c
@@ -0,0 +1,70 @@
+/*
+ * QEMU model of the Canon DIGIC SoC.
+ *
+ * Copyright (C) 2013 Antony Pavlov antonynpav...@gmail.com
+ *
+ * This model is based on reverse engineering efforts
+ * made by CHDK (http://chdk.wikia.com) and
+ * Magic Lantern (http://www.magiclantern.fm) projects
+ * contributors.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
http://www.gnu.org/licenses/.
+ *
+ */
+
+#include hw/sysbus.h
+#include target-arm/cpu-qom.h
+#include hw/arm/digic.h
+
+static void digic_init(Object *obj)
+{
+DigicState *s = DIGIC(obj);
+
+object_initialize(s-cpu, sizeof(s-cpu), arm946- TYPE_ARM_CPU);
+object_property_add_child(obj, cpu, OBJECT(s-cpu), NULL);
+}
+
+static void digic_realize(DeviceState *dev, Error **errp)
+{
+DigicState *s = DIGIC(dev);
+Error *err = NULL;
+
+object_property_set_bool(OBJECT(s-cpu), true, realized, err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
+}
+
+static void digic_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+dc-realize = digic_realize;
+}
+
+static const TypeInfo digic_type_info = {
+.name = TYPE_DIGIC,
+.parent = TYPE_DEVICE,
+.instance_size = sizeof(DigicState),
+.instance_init = digic_init,
+.class_init = digic_class_init,
+};
+
+static void digic_register_types(void)
+{
+type_register_static(digic_type_info);
+}
+
+type_init(digic_register_types)
diff --git a/include/hw/arm/digic.h b/include/hw/arm/digic.h
new file mode 100644
index 000..0ef4723
--- /dev/null
+++ b/include/hw/arm/digic.h
@@ -0,0 +1,23 @@
+/*
+ * Misc DIGIC declarations
+ *
+ * Copyright (C) 2013 Antony Pavlov antonynpav...@gmail.com
+ *
+ */
+
+#ifndef __DIGIC_H__
+#define __DIGIC_H__
Identifiers starting in underscore are reserved. Suggest DIGIC_H,
HW_ARM_DIGIC_H, QEMU_DIGIC_H or something like that.
+
+#include cpu-qom.h
This looks bogus, cpu-qom.h cannot be included on its own since it
depends in CPUARMState in cpu.h these days.
+
+#define TYPE_DIGIC digic
+
+#define DIGIC(obj) OBJECT_CHECK(DigicState, (obj), TYPE_DIGIC)
+
+typedef struct DigicState {
Please add
/* private */
+Object parent_obj;
/* private */
markers for documentation.
It needs to be DeviceState parent_obj though.
+
+ARMCPU cpu;
+} DigicState;
+
+#endif /* __DIGIC_H__ */
Otherwise looks good.
Regards,
Andreas
--
Re: [Qemu-devel] [PATCH] pl110: Clarify comment about PL110 ID on VersatilePB
Am 05.09.2013 18:43, schrieb Peter Maydell:
Clarify a comment about the ID register value presented by
the PL110 variant present on the VersatilePB board (based
on testing what the actual hardware does), to indicate that
this is not an error in our emulation, and to remove an #if-0.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
I happened to have to check the h/w behaviour in this area today
during a discussion about some kernel pl11x patches, so I thought
I might as well record the info and clean up the #if-0 in the
process.
hw/display/pl110.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/hw/display/pl110.c b/hw/display/pl110.c
index e79ab4b..790e510 100644
--- a/hw/display/pl110.c
+++ b/hw/display/pl110.c
@@ -94,23 +94,21 @@ static const VMStateDescription vmstate_pl110 = {
static const unsigned char pl110_id[] =
{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
-/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
- has a different ID. However Linux only looks for the normal ID. */
-#if 0
-static const unsigned char pl110_versatile_id[] =
-{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
-#else
-#define pl110_versatile_id pl110_id
-#endif
-
static const unsigned char pl111_id[] = {
0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
};
+
/* Indexed by pl110_version */
static const unsigned char *idregs[] = {
pl110_id,
-pl110_versatile_id,
+/* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board
+ * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware
+ * itself has the same ID values as a stock PL110, and guests (in
+ * particular Linux) rely on this. We emulate what the hardware does,
+ * rather than what the docs claim it ought to do.
+ */
+pl110_id,
pl111_id
};
I vaguely remember us having a conversation that we might store these in
the class, but me not wanting to refactor that in my 1.6 candidate
patchset, right? In case you find some time, feel free to improve on
this, I'll get my other pending series polished first.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [RFC v4 1/5] hw/arm: add very initial support for Canon DIGIC SoC
Am 05.09.2013 23:23, schrieb Antony Pavlov:
On Thu, 05 Sep 2013 20:08:34 +0200
Andreas Färber afaer...@suse.de wrote:
Am 05.09.2013 09:52, schrieb Antony Pavlov:
diff --git a/hw/arm/digic.c b/hw/arm/digic.c
new file mode 100644
index 000..95a9fcd
--- /dev/null
+++ b/hw/arm/digic.c
[...]
+static const TypeInfo digic_type_info = {
+.name = TYPE_DIGIC,
+.parent = TYPE_DEVICE,
+.instance_size = sizeof(DigicState),
+.instance_init = digic_init,
+.class_init = digic_class_init,
+};
+
+static void digic_register_types(void)
+{
+type_register_static(digic_type_info);
+}
+
+type_init(digic_register_types)
diff --git a/include/hw/arm/digic.h b/include/hw/arm/digic.h
new file mode 100644
index 000..0ef4723
--- /dev/null
+++ b/include/hw/arm/digic.h
[...]
+typedef struct DigicState {
Please add
/* private */
+Object parent_obj;
/* private */
/* public */ ?
Yes, sorry, copypaste and then noticing Object. ;)
Or just leave the latter out so that all fields are undocumented.
markers for documentation.
It needs to be DeviceState parent_obj though.
In your tegra2 support 'Object parent_obj' is used in a similar situation.
http://repo.or.cz/w/qemu/afaerber.git/blob/refs/heads/tegra:/include/hw/arm/tegra2.h#l42
Thanks for spotting, fixed. (It used to be derived from TYPE_OBJECT, but
we decided to provide QOM realize support only for devices.)
Unfortunately Tegra kernel is still stuck after USB init either way...
Cheers,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [RFC qom-cpu v2 2/8] x86: add x86_cpu_unrealizefn() for cpu apic remove
Am 10.09.2013 11:43, schrieb Chen Fan:
Implement x86_cpu_unrealizefn() for corresponding x86_cpu_realizefn(),
which is mostly used to clear the apic related information at here.
Signed-off-by: Chen Fan chen.fan.f...@cn.fujitsu.com
---
hw/cpu/icc_bus.c| 11 +++
hw/i386/kvm/apic.c | 6 ++
hw/intc/apic.c | 7 +++
hw/intc/apic_common.c | 11 +++
include/hw/cpu/icc_bus.h| 1 +
include/hw/i386/apic_internal.h | 1 +
target-i386/cpu-qom.h | 1 +
target-i386/cpu.c | 35 +++
8 files changed, 73 insertions(+)
Some nitpicks below, mostly about adopting the latest concepts.
diff --git a/hw/cpu/icc_bus.c b/hw/cpu/icc_bus.c
index 8748cc5..45e87d1 100644
--- a/hw/cpu/icc_bus.c
+++ b/hw/cpu/icc_bus.c
@@ -54,11 +54,22 @@ static void icc_device_realize(DeviceState *dev, Error
**errp)
}
}
+static void icc_device_unrealize(DeviceState *dev, Error **errp)
+{
+ICCDevice *id = ICC_DEVICE(dev);
+ICCDeviceClass *idc = ICC_DEVICE_GET_CLASS(id);
+
+if (idc-exit) {
+idc-exit(id);
-unrealize
+}
+}
+
static void icc_device_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc-realize = icc_device_realize;
+dc-unrealize = icc_device_unrealize;
dc-bus_type = TYPE_ICC_BUS;
}
diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c
index 5609063..8f028a1 100644
--- a/hw/i386/kvm/apic.c
+++ b/hw/i386/kvm/apic.c
@@ -181,11 +181,17 @@ static void kvm_apic_init(APICCommonState *s)
}
}
+static void kvm_apic_exit(APICCommonState *s)
kvm_apic_unrealize
+{
+memory_region_destroy(s-io_memory);
+}
+
static void kvm_apic_class_init(ObjectClass *klass, void *data)
{
APICCommonClass *k = APIC_COMMON_CLASS(klass);
k-init = kvm_apic_init;
+k-exit = kvm_apic_exit;
k-set_base = kvm_apic_set_base;
k-set_tpr = kvm_apic_set_tpr;
k-get_tpr = kvm_apic_get_tpr;
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index a913186..23488b4 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -882,11 +882,18 @@ static void apic_init(APICCommonState *s)
msi_supported = true;
}
+static void apic_uninit(APICCommonState *s)
apic_unrealize
+{
+memory_region_destroy(s-io_memory);
+local_apics[s-idx] = NULL;
+}
+
static void apic_class_init(ObjectClass *klass, void *data)
{
APICCommonClass *k = APIC_COMMON_CLASS(klass);
k-init = apic_init;
+k-exit = apic_uninit;
k-set_base = apic_set_base;
k-set_tpr = apic_set_tpr;
k-get_tpr = apic_get_tpr;
diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
index 5568621..32c2f74 100644
--- a/hw/intc/apic_common.c
+++ b/hw/intc/apic_common.c
@@ -316,6 +316,16 @@ static int apic_init_common(ICCDevice *dev)
return 0;
}
+static void apic_exit_common(ICCDevice *dev)
+{
+APICCommonState *s = APIC_COMMON(dev);
+APICCommonClass *info;
acc please
+
+info = APIC_COMMON_GET_CLASS(s);
+if (info-exit)
+info-exit(s);
Braces missing - checkpatch.pl
+}
+
static void apic_dispatch_pre_save(void *opaque)
{
APICCommonState *s = APIC_COMMON(opaque);
@@ -387,6 +397,7 @@ static void apic_common_class_init(ObjectClass *klass,
void *data)
dc-no_user = 1;
dc-props = apic_properties_common;
idc-init = apic_init_common;
+idc-exit = apic_exit_common;
}
static const TypeInfo apic_common_type = {
diff --git a/include/hw/cpu/icc_bus.h b/include/hw/cpu/icc_bus.h
index b550070..15d5374 100644
--- a/include/hw/cpu/icc_bus.h
+++ b/include/hw/cpu/icc_bus.h
@@ -67,6 +67,7 @@ typedef struct ICCDeviceClass {
/* public */
int (*init)(ICCDevice *dev); /* TODO replace with QOM realize */
+void (*exit)(ICCDevice *dev);
DeviceUnrealize unrealize;
} ICCDeviceClass;
#define TYPE_ICC_DEVICE icc-device
diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_internal.h
index 1b0a7fb..87d5248 100644
--- a/include/hw/i386/apic_internal.h
+++ b/include/hw/i386/apic_internal.h
@@ -81,6 +81,7 @@ typedef struct APICCommonClass
ICCDeviceClass parent_class;
void (*init)(APICCommonState *s);
+void (*exit)(APICCommonState *s);
DeviceUnrealize unrealize;
void (*set_base)(APICCommonState *s, uint64_t val);
void (*set_tpr)(APICCommonState *s, uint8_t val);
uint8_t (*get_tpr)(APICCommonState *s);
diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
index c4447c2..1e520be 100644
--- a/target-i386/cpu-qom.h
+++ b/target-i386/cpu-qom.h
@@ -50,6 +50,7 @@ typedef struct X86CPUClass {
/* public */
DeviceRealize parent_realize;
+DeviceUnrealize parent_unrealize;
void (*parent_reset)(CPUState *cpu);
} X86CPUClass;
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
Re: [Qemu-devel] [RFC qom-cpu v2 1/8] apic: remove apic_no from apic_init_common()
Am 10.09.2013 14:09, schrieb Igor Mammedov:
On Tue, 10 Sep 2013 17:43:41 +0800
Chen Fan chen.fan.f...@cn.fujitsu.com wrote:
the 'apic_no' is increased by one when initialize/create a vCPU each time,
which causes APICCommonState s-idx always is increased.
but if we want to re-add a vCPU after removing a vCPU, we need to re-use the
vacant s-idx which the corresponding vCPU had been removed.
so we could use the unique cpu apic_id instead of the progressive s-idx.
Signed-off-by: Chen Fan chen.fan.f...@cn.fujitsu.com
---
hw/intc/apic_common.c | 4 +---
target-i386/cpu.c | 1 +
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
index a0beb10..5568621 100644
--- a/hw/intc/apic_common.c
+++ b/hw/intc/apic_common.c
@@ -289,13 +289,11 @@ static int apic_init_common(ICCDevice *dev)
APICCommonState *s = APIC_COMMON(dev);
APICCommonClass *info;
static DeviceState *vapic;
-static int apic_no;
static bool mmio_registered;
-if (apic_no = MAX_APICS) {
+if (s-idx = MAX_APICS) {
return -1;
}
-s-idx = apic_no++;
info = APIC_COMMON_GET_CLASS(s);
info-init(s);
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 42c5de0..2b99683 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2322,6 +2322,7 @@ static void x86_cpu_apic_create(X86CPU *cpu, Error
**errp)
/* TODO: convert to link */
apic = APIC_COMMON(env-apic_state);
apic-cpu = cpu;
+apic-idx = env-cpuid_apic_id;
earlier here we set:
qdev_prop_set_uint8(env-apic_state, id, env-cpuid_apic_id);
so apic-idx = env-cpuid_apic_id is redundant.
it would be better to search by apic-id and preferably replace O(MAX_APIC)
scans with
a faster approach since for TCG iqr delivery might be a hot path, dropping
MAX_APIC
altogether and using dynamic present APICs list.
Independent of that, the recent removal of X86_CPU() cast from
x86_env_get_cpu() should allow us to finally tackle the TODO above,
moving apic_state field from CPUX86State to X86CPU.
Andreas
}
static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 2/6] qdev: unref qdev when device_add fails
Am 10.09.2013 18:49, schrieb Paolo Bonzini:
Il 10/09/2013 18:21, Stefan Hajnoczi ha scritto:
qdev_device_add() leaks the created qdev upon failure. I suspect this
problem crept in because qdev_free() unparents the qdev but does not
drop a reference - confusing name.
Right, the name a leftover from pre-refcounting days.
BTW, not dropping a reference is the right thing to do because the
reference is dropped much earlier, typically as soon as qdev_device_add
returns. The QOM object tree then will still provide means to access
devices, until they are unparented.
In this case, however, qdev_device_add's caller does not have a
reference to free; doing that is the responsibility of qdev_device_add,
since it returns NULL.
Also drop trailing whitespace after curly bracket.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
qdev-monitor.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/qdev-monitor.c b/qdev-monitor.c
index 410cdcb..5657cdc 100644
--- a/qdev-monitor.c
+++ b/qdev-monitor.c
@@ -512,6 +512,7 @@ DeviceState *qdev_device_add(QemuOpts *opts)
}
if (qemu_opt_foreach(opts, set_property, qdev, 1) != 0) {
qdev_free(qdev);
+object_unref(OBJECT(qdev));
return NULL;
}
if (qdev-id) {
Given that qdev_free() doesn't do what one might expect, I would suggest
to s/qdev_free/object_unparent/g above.
@@ -523,8 +524,9 @@ DeviceState *qdev_device_add(QemuOpts *opts)
object_property_add_child(qdev_get_peripheral_anon(), name,
OBJECT(qdev), NULL);
g_free(name);
-}
+}
if (qdev_init(qdev) 0) {
+object_unref(OBJECT(qdev));
qerror_report(QERR_DEVICE_INIT_FAILED, driver);
return NULL;
}
Reviewed-by: Paolo Bonzini pbonz...@redhat.com
I would like to take this through qom-next tree since I have pending
variable cleanups there (qdev being touched here). Not sure how to
handle that wrt block changes in this series?
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] qdev: rename qdev_free() to qdev_unparent()
Am 11.09.2013 09:45, schrieb Stefan Hajnoczi:
The qdev_free() function name is misleading since all the function does
is unlink the device from its parent. The device is not necessarily
freed.
The device will be freed when its QObject refcount reaches zero. It is
usual for the parent (bus) to hold the final reference but there are
cases where something else holds a reference so free is a misleading
name.
I opted to keep a qdev wrapper function instead of making all callers
use object_unparent(OBJECT(qdev)) directly due to the slightly ugly
cast.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
This patch is based on the [PATCH 0/6] qdev and blockdev refcount leak fixes
series that I sent yesterday.
hw/acpi/piix4.c | 2 +-
hw/core/qdev.c | 10 +-
hw/pci/pci-hotplug-old.c | 2 +-
hw/pci/pci_bridge.c | 2 +-
hw/pci/pcie.c| 2 +-
hw/pci/shpc.c| 2 +-
hw/s390x/virtio-ccw.c| 2 +-
hw/scsi/scsi-bus.c | 6 +++---
hw/usb/bus.c | 4 ++--
hw/usb/dev-storage.c | 2 +-
hw/usb/host-legacy.c | 2 +-
hw/virtio/virtio-bus.c | 2 +-
hw/xen/xen_platform.c| 2 +-
include/hw/qdev-core.h | 2 +-
qdev-monitor.c | 2 +-
15 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 0b8d1d9..2ec9ada 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -326,7 +326,7 @@ static void acpi_piix_eject_slot(PIIX4PMState *s,
unsigned slots)
if (pc-no_hotplug) {
slot_free = false;
} else {
-qdev_free(qdev);
+qdev_unparent(qdev);
}
}
}
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index 533f6dd..ac2352b 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -164,7 +164,7 @@ int qdev_init(DeviceState *dev)
if (local_err != NULL) {
qerror_report_err(local_err);
error_free(local_err);
-qdev_free(dev);
+qdev_unparent(dev);
return -1;
}
return 0;
@@ -258,7 +258,7 @@ void qbus_reset_all_fn(void *opaque)
int qdev_simple_unplug_cb(DeviceState *dev)
{
/* just zap it */
-qdev_free(dev);
+qdev_unparent(dev);
return 0;
}
@@ -280,8 +280,8 @@ void qdev_init_nofail(DeviceState *dev)
}
}
-/* Unlink device from bus and free the structure. */
-void qdev_free(DeviceState *dev)
+/* Unlink device from bus. dev is freed if refcount reaches zero. */
+void qdev_unparent(DeviceState *dev)
{
object_unparent(OBJECT(dev));
}
@@ -458,7 +458,7 @@ static void bus_unparent(Object *obj)
while ((kid = QTAILQ_FIRST(bus-children)) != NULL) {
DeviceState *dev = kid-child;
-qdev_free(dev);
+qdev_unparent(dev);
}
if (bus-parent) {
QLIST_REMOVE(bus, sibling);
diff --git a/hw/pci/pci-hotplug-old.c b/hw/pci/pci-hotplug-old.c
index 619fe47..f197f5f 100644
--- a/hw/pci/pci-hotplug-old.c
+++ b/hw/pci/pci-hotplug-old.c
@@ -248,7 +248,7 @@ static PCIDevice *qemu_pci_hot_add_storage(Monitor *mon,
}
dev = pci_create(bus, devfn, virtio-blk-pci);
if (qdev_prop_set_drive(dev-qdev, drive, dinfo-bdrv) 0) {
-qdev_free(dev-qdev);
+qdev_unparent(dev-qdev);
This should be DEVICE(dev), making most callers outside qdev.c do a cast
after all.
Also we should name the function device_unparent if we decide to keep it
around.
Andreas
dev = NULL;
break;
}
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index e6b22b8..68e0bcb 100644
--- a/hw/pci/pci_bridge.c
+++ b/hw/pci/pci_bridge.c
@@ -391,7 +391,7 @@ void pci_bridge_exitfn(PCIDevice *pci_dev)
pci_bridge_region_cleanup(s, s-windows);
memory_region_destroy(s-address_space_mem);
memory_region_destroy(s-address_space_io);
-/* qbus_free() is called automatically by qdev_free() */
+/* qbus_free() is called automatically by qdev_unparent() */
}
/*
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 50af3c1..edd3f40 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -251,7 +251,7 @@ static int pcie_cap_slot_hotplug(DeviceState *qdev,
PCI_EXP_SLTSTA_PDS);
pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
} else {
-qdev_free(pci_dev-qdev);
+qdev_unparent(pci_dev-qdev);
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
PCI_EXP_SLTSTA_PDS);
pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c
index eb092fd..5ba2b17 100644
--- a/hw/pci/shpc.c
+++ b/hw/pci/shpc.c
@@ -254,7 +254,7 @@ static void shpc_free_devices_in_slot(SHPCDevice *shpc,
int slot)
++devfn) {
PCIDevice *affected_dev = shpc-sec_bus-devices[devfn];
if
Re: [Qemu-devel] [PATCH] target-i386: set model=6 on qemu64 qemu32 CPU models
Am 11.09.2013 10:22, schrieb Igor Mammedov:
On Tue, 10 Sep 2013 17:48:59 -0300
Eduardo Habkost ehabk...@redhat.com wrote:
There's no Intel CPU with family=6,model=2, and Linux and Windows guests
disable SEP when seeing that combination due to Pentium Pro erratum #82.
In addition to just having SEP ignored by guests, Skype (and maybe other
applications) runs sysenter directly without passing through ntdll on
Windows, and crashes because Windows ignored the SEP CPUID bit.
So, having model 2 is a better default on qemu64 and qemu32 for two
reasons: making SEP really available for guests, and avoiding crashing
applications that work on bare metal.
model=3 would fix the problem, but it causes CPU enumeration problems
for Windows guests[1]. So this patch sets model=6, that matches Athlon
(PM core) on AMD and P2 with on-die L2 cache on Intel and it allows
Windows to use all CPUs as well as fixing sysenter.
[1] https://bugzilla.redhat.com/show_bug.cgi?id=508623
Cc: Andrea Arcangeli aarca...@redhat.com
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
---
include/hw/i386/pc.h | 8
target-i386/cpu.c| 4 ++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 7fb04d8..195e962 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -258,6 +258,14 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
.driver = TYPE_X86_CPU,\
.property = pmu,\
.value = on,\
+},{\
+.driver = qemu64- TYPE_X86_CPU,\
+.property = model,\
+.value= stringify(2),\
+},{\
+.driver = qemu32- TYPE_X86_CPU,\
+.property = model,\
+.value= stringify(3),\
}
#define PC_COMPAT_1_4 \
Shouldn't this hunk be in PC_COMPAT_1_6 rather than alongside PMU, which
I believe was for 1_5?
Andreas
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index c36345e..36cfbce 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -544,7 +544,7 @@ static x86_def_t builtin_x86_defs[] = {
.level = 4,
.vendor = CPUID_VENDOR_AMD,
.family = 6,
-.model = 2,
+.model = 6,
.stepping = 3,
.features[FEAT_1_EDX] =
PPRO_FEATURES |
@@ -647,7 +647,7 @@ static x86_def_t builtin_x86_defs[] = {
.level = 4,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
-.model = 3,
+.model = 6,
.stepping = 3,
.features[FEAT_1_EDX] =
PPRO_FEATURES,
Reviewed-By: Igor Mammedov imamm...@redhat.com
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [RFC 0/4] ARM aarch64 disas output libvixl support
Hi Claudio, Am 11.09.2013 14:54, schrieb Claudio Fontana: This is the aarch64 libvixl support patchset in the current state. It provides (limited) support for disassembly output on aarch64. Only host disassembly is enabled, since target for aarch64 is not in yet. An external objdump solution as exemplified before by R.H. seems preferable to me, even if it means giving up the monitor support. [snip] That has been committed August 24th, hasn't it? Regards, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [PATCH v4 17/24] arm11mpcore: Create container MemoryRegion in instance_init
This allows to map the region directly after object initialization.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/cpu/arm11mpcore.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
index 8719634..5f80e7b 100644
--- a/hw/cpu/arm11mpcore.c
+++ b/hw/cpu/arm11mpcore.c
@@ -90,8 +90,6 @@ static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s-gic);
SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s-mptimer);
SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s-wdtimer);
-memory_region_init(s-container, OBJECT(s),
- mpcore-priv-container, 0x2000);
memory_region_init_io(s-iomem, OBJECT(s),
mpcore_scu_ops, s, mpcore-scu, 0x100);
memory_region_add_subregion(s-container, 0, s-iomem);
@@ -155,10 +153,19 @@ static int mpcore_priv_init(SysBusDevice *sbd)
qdev_init_nofail(s-wdtimer);
mpcore_priv_map_setup(s);
-sysbus_init_mmio(sbd, s-container);
return 0;
}
+static void mpcore_priv_initfn(Object *obj)
+{
+SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj);
+
+memory_region_init(s-container, OBJECT(s),
+ mpcore-priv-container, 0x2000);
+sysbus_init_mmio(sbd, s-container);
+}
+
#define TYPE_REALVIEW_MPCORE_RIRQ realview_mpcore
#define REALVIEW_MPCORE_RIRQ(obj) \
OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)
@@ -277,6 +284,7 @@ static const TypeInfo mpcore_priv_info = {
.name = TYPE_ARM11MPCORE_PRIV,
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ARM11MPCorePriveState),
+.instance_init = mpcore_priv_initfn,
.class_init= mpcore_priv_class_init,
};
--
1.8.1.4
[Qemu-devel] [PATCH v4 04/24] a9scu: QOM cleanups
From: Andreas Färber andreas.faer...@web.de
Rename A9SCUState::busdev field to parent_obj and turn realizefn into an
instance_init function to allow early MMIO mapping.
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/misc/a9scu.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
index 601b573..2661014 100644
--- a/hw/misc/a9scu.c
+++ b/hw/misc/a9scu.c
@@ -13,7 +13,10 @@
/* A9MP private memory region. */
typedef struct A9SCUState {
-SysBusDevice busdev;
+/* private */
+SysBusDevice parent_obj;
+/* public */
+
MemoryRegion iomem;
uint32_t control;
uint32_t status;
@@ -114,12 +117,12 @@ static void a9_scu_reset(DeviceState *dev)
s-control = 0;
}
-static void a9_scu_realize(DeviceState *dev, Error ** errp)
+static void a9_scu_init(Object *obj)
{
-A9SCUState *s = A9_SCU(dev);
-SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+A9SCUState *s = A9_SCU(obj);
+SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-memory_region_init_io(s-iomem, OBJECT(dev), a9_scu_ops, s,
+memory_region_init_io(s-iomem, obj, a9_scu_ops, s,
a9-scu, 0x100);
sysbus_init_mmio(sbd, s-iomem);
}
@@ -144,7 +147,6 @@ static void a9_scu_class_init(ObjectClass *klass, void
*data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
-dc-realize = a9_scu_realize;
dc-props = a9_scu_properties;
dc-vmsd = vmstate_a9_scu;
dc-reset = a9_scu_reset;
@@ -154,6 +156,7 @@ static const TypeInfo a9_scu_info = {
.name = TYPE_A9_SCU,
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(A9SCUState),
+.instance_init = a9_scu_init,
.class_init= a9_scu_class_init,
};
--
1.8.1.4
[Qemu-devel] [PATCH v4 00/24] arm: ARM11MPCore+A9MPCore+A15MPCore QOM'ification
From: Andreas Färber andreas.faer...@web.de
Hello Peter,
This series fully QOM'ifies A9MPCore so that it can be embedded for Tegra2.
It goes on to do the same for A15MPCore, which had previously been taken as
template for Cortex-A57 by John Rigby, and since v3 ARM11MPCore.
Separate headers are introduced to only expose device state to whom asks for it.
v4 is a rebase that addresses concerns about potential future GICState
size mismatches by asserting in QOM infrastructure.
Regards,
Andreas
v3 - v4:
* Rebased; object_initialize() now takes additional size argument.
* Subject prefixes unified.
v2 - v3:
* Split off hw/intc/arm_gic_common.h from new arm_gic.h (PMM).
* Added patches converting arm11mpcore, too.
* Split off arm11scu from arm11mpcore, following a9scu/a9mpcore model.
* Added patch to enforce building a9scu only once.
* Split off RealView MPCore from ARM11 MPCore using a new arm11mpcore.h.
v1 - v2:
* Renamed MP_TIMER to MPTIMER (Peter C.).
* Don't include gic_internal.h, introduce new arm_gic.h header (PMM).
* a9mpcore: Init only container MemoryRegion in instance_init (Peter C.).
* a9mpcore/a15mpcore: Replaced all qdev_init_nofail()s for error propagation.
Cc: Peter Maydell peter.mayd...@linaro.org
Cc: Peter Crosthwaite peter.crosthwa...@xilinx.com
Cc: Mian M. Hamayun m.hama...@virtualopensystems.com
Cc: Claudio Fontana claudio.font...@huawei.com
Andreas Färber (24):
a9mpcore: Split off instance_init
arm_gic: Extract headers hw/intc/arm_gic{,_common}.h
a9mpcore: Embed GICState
a9scu: QOM cleanups
a9mpcore: Embed A9SCUState
arm_mptimer: Convert to QOM realize
a9mpcore: Embed ARMMPTimerState
a9mpcore: Convert to QOM realize
a9mpcore: Prepare for QOM embedding
a15mpcore: Split off instance_init
a15mpcore: Embed GICState
a15mpcore: Convert to QOM realize
a15mpcore: Prepare for QOM embedding
a9scu: Build only once
arm11mpcore: Fix typo in MemoryRegion name
arm11mpcore: Drop unused fields
arm11mpcore: Create container MemoryRegion in instance_init
arm11mpcore: Split off SCU device
arm11mpcore: Convert ARM11MPCorePriveState to QOM realize
realview_gic: Convert to QOM realize
realview_gic: Prepare for QOM embedding
arm11mpcore: Convert mpcore_rirq_state to QOM realize
arm11mpcore: Prepare for QOM embedding
arm11mpcore: Split off RealView MPCore
default-configs/arm-softmmu.mak | 1 +
hw/cpu/Makefile.objs | 1 +
hw/cpu/a15mpcore.c | 81 ++---
hw/cpu/a9mpcore.c| 120 +++
hw/cpu/arm11mpcore.c | 251 ++-
hw/cpu/realview_mpcore.c | 139 ++
hw/intc/arm_gic_common.c | 18 +--
hw/intc/gic_internal.h | 80 +
hw/intc/realview_gic.c | 58 +
hw/misc/Makefile.objs| 3 +-
hw/misc/a9scu.c | 25 +---
hw/misc/arm11scu.c | 100
hw/timer/arm_mptimer.c | 60 +++---
include/hw/cpu/a15mpcore.h | 44 +++
include/hw/cpu/a9mpcore.h| 37 ++
include/hw/cpu/arm11mpcore.h | 35 ++
include/hw/intc/arm_gic.h| 42 +++
include/hw/intc/arm_gic_common.h | 92 ++
include/hw/intc/realview_gic.h | 28 +
include/hw/misc/a9scu.h | 31 +
include/hw/misc/arm11scu.h | 29 +
include/hw/timer/arm_mptimer.h | 54 +
22 files changed, 879 insertions(+), 450 deletions(-)
create mode 100644 hw/cpu/realview_mpcore.c
create mode 100644 hw/misc/arm11scu.c
create mode 100644 include/hw/cpu/a15mpcore.h
create mode 100644 include/hw/cpu/a9mpcore.h
create mode 100644 include/hw/cpu/arm11mpcore.h
create mode 100644 include/hw/intc/arm_gic.h
create mode 100644 include/hw/intc/arm_gic_common.h
create mode 100644 include/hw/intc/realview_gic.h
create mode 100644 include/hw/misc/a9scu.h
create mode 100644 include/hw/misc/arm11scu.h
create mode 100644 include/hw/timer/arm_mptimer.h
--
1.8.1.4
[Qemu-devel] [PATCH v4 15/24] arm11mpcore: Fix typo in MemoryRegion name
mpcode - mpcore Signed-off-by: Andreas Färber afaer...@suse.de --- hw/cpu/arm11mpcore.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index a786c62..27cd32b 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -93,7 +93,7 @@ static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s-mptimer); SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s-wdtimer); memory_region_init(s-container, OBJECT(s), - mpcode-priv-container, 0x2000); + mpcore-priv-container, 0x2000); memory_region_init_io(s-iomem, OBJECT(s), mpcore_scu_ops, s, mpcore-scu, 0x100); memory_region_add_subregion(s-container, 0, s-iomem); -- 1.8.1.4
[Qemu-devel] [PATCH v4 13/24] a15mpcore: Prepare for QOM embedding
From: Andreas Färber andreas.faer...@web.de
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a15mpcore.c | 21 +
include/hw/cpu/a15mpcore.h | 44
2 files changed, 45 insertions(+), 20 deletions(-)
create mode 100644 include/hw/cpu/a15mpcore.h
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index 10dc35a..acc419e 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -18,27 +18,8 @@
* with this program; if not, see http://www.gnu.org/licenses/.
*/
-#include hw/sysbus.h
+#include hw/cpu/a15mpcore.h
#include sysemu/kvm.h
-#include hw/intc/arm_gic.h
-
-/* A15MP private memory region. */
-
-#define TYPE_A15MPCORE_PRIV a15mpcore_priv
-#define A15MPCORE_PRIV(obj) \
-OBJECT_CHECK(A15MPPrivState, (obj), TYPE_A15MPCORE_PRIV)
-
-typedef struct A15MPPrivState {
-/* private */
-SysBusDevice parent_obj;
-/* public */
-
-uint32_t num_cpu;
-uint32_t num_irq;
-MemoryRegion container;
-
-GICState gic;
-} A15MPPrivState;
static void a15mp_priv_set_irq(void *opaque, int irq, int level)
{
diff --git a/include/hw/cpu/a15mpcore.h b/include/hw/cpu/a15mpcore.h
new file mode 100644
index 000..b423533
--- /dev/null
+++ b/include/hw/cpu/a15mpcore.h
@@ -0,0 +1,44 @@
+/*
+ * Cortex-A15MPCore internal peripheral emulation.
+ *
+ * Copyright (c) 2012 Linaro Limited.
+ * Written by Peter Maydell.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see http://www.gnu.org/licenses/.
+ */
+#ifndef HW_CPU_A15MPCORE_H
+#define HW_CPU_A15MPCORE_H
+
+#include hw/sysbus.h
+#include hw/intc/arm_gic.h
+
+/* A15MP private memory region. */
+
+#define TYPE_A15MPCORE_PRIV a15mpcore_priv
+#define A15MPCORE_PRIV(obj) \
+OBJECT_CHECK(A15MPPrivState, (obj), TYPE_A15MPCORE_PRIV)
+
+typedef struct A15MPPrivState {
+/* private */
+SysBusDevice parent_obj;
+/* public */
+
+uint32_t num_cpu;
+uint32_t num_irq;
+MemoryRegion container;
+
+GICState gic;
+} A15MPPrivState;
+
+#endif
--
1.8.1.4
[Qemu-devel] [PATCH v4 06/24] arm_mptimer: Convert to QOM realize
From: Andreas Färber andreas.faer...@web.de
Split the SysBusDevice initfn into instance_init and realizefn.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/timer/arm_mptimer.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c
index 8020c9f..2853db4 100644
--- a/hw/timer/arm_mptimer.c
+++ b/hw/timer/arm_mptimer.c
@@ -225,8 +225,18 @@ static void arm_mptimer_reset(DeviceState *dev)
}
}
-static int arm_mptimer_init(SysBusDevice *dev)
+static void arm_mptimer_init(Object *obj)
{
+ARMMPTimerState *s = ARM_MPTIMER(obj);
+
+memory_region_init_io(s-iomem, obj, arm_thistimer_ops, s,
+ arm_mptimer_timer, 0x20);
+sysbus_init_mmio(SYS_BUS_DEVICE(obj), s-iomem);
+}
+
+static void arm_mptimer_realize(DeviceState *dev, Error **errp)
+{
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
ARMMPTimerState *s = ARM_MPTIMER(dev);
int i;
@@ -243,19 +253,14 @@ static int arm_mptimer_init(SysBusDevice *dev)
* * timer for core 1
* and so on.
*/
-memory_region_init_io(s-iomem, OBJECT(s), arm_thistimer_ops, s,
- arm_mptimer_timer, 0x20);
-sysbus_init_mmio(dev, s-iomem);
for (i = 0; i s-num_cpu; i++) {
TimerBlock *tb = s-timerblock[i];
tb-timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, timerblock_tick, tb);
-sysbus_init_irq(dev, tb-irq);
+sysbus_init_irq(sbd, tb-irq);
memory_region_init_io(tb-iomem, OBJECT(s), timerblock_ops, tb,
arm_mptimer_timerblock, 0x20);
-sysbus_init_mmio(dev, tb-iomem);
+sysbus_init_mmio(sbd, tb-iomem);
}
-
-return 0;
}
static const VMStateDescription vmstate_timerblock = {
@@ -292,9 +297,8 @@ static Property arm_mptimer_properties[] = {
static void arm_mptimer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
-SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
-sbc-init = arm_mptimer_init;
+dc-realize = arm_mptimer_realize;
dc-vmsd = vmstate_arm_mptimer;
dc-reset = arm_mptimer_reset;
dc-no_user = 1;
@@ -305,6 +309,7 @@ static const TypeInfo arm_mptimer_info = {
.name = TYPE_ARM_MPTIMER,
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ARMMPTimerState),
+.instance_init = arm_mptimer_init,
.class_init= arm_mptimer_class_init,
};
--
1.8.1.4
[Qemu-devel] [PATCH v4 07/24] a9mpcore: Embed ARMMPTimerState
From: Andreas Färber andreas.faer...@web.de
Prepares for QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 29 ++-
hw/timer/arm_mptimer.c | 35 ---
include/hw/timer/arm_mptimer.h | 54 ++
3 files changed, 76 insertions(+), 42 deletions(-)
create mode 100644 include/hw/timer/arm_mptimer.h
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index df92e3f..db3907e 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -11,6 +11,7 @@
#include hw/sysbus.h
#include hw/intc/arm_gic.h
#include hw/misc/a9scu.h
+#include hw/timer/arm_mptimer.h
#define TYPE_A9MPCORE_PRIV a9mpcore_priv
#define A9MPCORE_PRIV(obj) \
@@ -23,12 +24,12 @@ typedef struct A9MPPrivState {
uint32_t num_cpu;
MemoryRegion container;
-DeviceState *mptimer;
-DeviceState *wdt;
uint32_t num_irq;
GICState gic;
A9SCUState scu;
+ARMMPTimerState mptimer;
+ARMMPTimerState wdt;
} A9MPPrivState;
static void a9mp_priv_set_irq(void *opaque, int irq, int level)
@@ -50,12 +51,18 @@ static void a9mp_priv_initfn(Object *obj)
object_initialize(s-scu, sizeof(s-scu), TYPE_A9_SCU);
qdev_set_parent_bus(DEVICE(s-scu), sysbus_get_default());
+
+object_initialize(s-mptimer, sizeof(s-mptimer), TYPE_ARM_MPTIMER);
+qdev_set_parent_bus(DEVICE(s-mptimer), sysbus_get_default());
+
+object_initialize(s-wdt, sizeof(s-wdt), TYPE_ARM_MPTIMER);
+qdev_set_parent_bus(DEVICE(s-wdt), sysbus_get_default());
}
static int a9mp_priv_init(SysBusDevice *dev)
{
A9MPPrivState *s = A9MPCORE_PRIV(dev);
-DeviceState *gicdev, *scudev;
+DeviceState *gicdev, *scudev, *mptimerdev, *wdtdev;
SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev;
int i;
@@ -76,15 +83,15 @@ static int a9mp_priv_init(SysBusDevice *dev)
qdev_init_nofail(scudev);
scubusdev = SYS_BUS_DEVICE(s-scu);
-s-mptimer = qdev_create(NULL, arm_mptimer);
-qdev_prop_set_uint32(s-mptimer, num-cpu, s-num_cpu);
-qdev_init_nofail(s-mptimer);
-timerbusdev = SYS_BUS_DEVICE(s-mptimer);
+mptimerdev = DEVICE(s-mptimer);
+qdev_prop_set_uint32(mptimerdev, num-cpu, s-num_cpu);
+qdev_init_nofail(mptimerdev);
+timerbusdev = SYS_BUS_DEVICE(s-mptimer);
-s-wdt = qdev_create(NULL, arm_mptimer);
-qdev_prop_set_uint32(s-wdt, num-cpu, s-num_cpu);
-qdev_init_nofail(s-wdt);
-wdtbusdev = SYS_BUS_DEVICE(s-wdt);
+wdtdev = DEVICE(s-wdt);
+qdev_prop_set_uint32(wdtdev, num-cpu, s-num_cpu);
+qdev_init_nofail(wdtdev);
+wdtbusdev = SYS_BUS_DEVICE(s-wdt);
/* Memory map (addresses are offsets from PERIPHBASE):
* 0x-0x00ff -- Snoop Control Unit
diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c
index 2853db4..d9f9494 100644
--- a/hw/timer/arm_mptimer.c
+++ b/hw/timer/arm_mptimer.c
@@ -19,7 +19,7 @@
* with this program; if not, see http://www.gnu.org/licenses/.
*/
-#include hw/sysbus.h
+#include hw/timer/arm_mptimer.h
#include qemu/timer.h
#include qom/cpu.h
@@ -27,34 +27,6 @@
* which is used in both the ARM11MPCore and Cortex-A9MP.
*/
-#define MAX_CPUS 4
-
-/* State of a single timer or watchdog block */
-typedef struct {
-uint32_t count;
-uint32_t load;
-uint32_t control;
-uint32_t status;
-int64_t tick;
-QEMUTimer *timer;
-qemu_irq irq;
-MemoryRegion iomem;
-} TimerBlock;
-
-#define TYPE_ARM_MPTIMER arm_mptimer
-#define ARM_MPTIMER(obj) \
-OBJECT_CHECK(ARMMPTimerState, (obj), TYPE_ARM_MPTIMER)
-
-typedef struct {
-/* private */
-SysBusDevice parent_obj;
-/* public */
-
-uint32_t num_cpu;
-TimerBlock timerblock[MAX_CPUS];
-MemoryRegion iomem;
-} ARMMPTimerState;
-
static inline int get_current_cpu(ARMMPTimerState *s)
{
if (current_cpu-cpu_index = s-num_cpu) {
@@ -240,8 +212,9 @@ static void arm_mptimer_realize(DeviceState *dev, Error
**errp)
ARMMPTimerState *s = ARM_MPTIMER(dev);
int i;
-if (s-num_cpu 1 || s-num_cpu MAX_CPUS) {
-hw_error(%s: num-cpu must be between 1 and %d\n, __func__, MAX_CPUS);
+if (s-num_cpu 1 || s-num_cpu ARM_MPTIMER_MAX_CPUS) {
+hw_error(%s: num-cpu must be between 1 and %d\n,
+ __func__, ARM_MPTIMER_MAX_CPUS);
}
/* We implement one timer block per CPU, and expose multiple MMIO regions:
* * region 0 is timer for this core
diff --git a/include/hw/timer/arm_mptimer.h b/include/hw/timer/arm_mptimer.h
new file mode 100644
index 000..b34cba0
--- /dev/null
+++ b/include/hw/timer/arm_mptimer.h
@@ -0,0 +1,54 @@
+/*
+ * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
+ *
+ * Copyright (c) 2006-2007 CodeSourcery.
+ * Copyright (c) 2011 Linaro Limited
+ * Written by Paul Brook, Peter Maydell
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General
[Qemu-devel] [PATCH v4 16/24] arm11mpcore: Drop unused fields
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/cpu/arm11mpcore.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
index 27cd32b..8719634 100644
--- a/hw/cpu/arm11mpcore.c
+++ b/hw/cpu/arm11mpcore.c
@@ -20,8 +20,6 @@ typedef struct ARM11MPCorePriveState {
SysBusDevice parent_obj;
uint32_t scu_control;
-int iomemtype;
-uint32_t old_timer_status[8];
uint32_t num_cpu;
MemoryRegion iomem;
MemoryRegion container;
--
1.8.1.4
[Qemu-devel] [PATCH v4 21/24] realview_gic: Prepare for QOM embedding
Move state struct, type constant and cast macro to a new header.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/intc/realview_gic.c | 15 +--
include/hw/intc/realview_gic.h | 28
2 files changed, 29 insertions(+), 14 deletions(-)
create mode 100644 include/hw/intc/realview_gic.h
diff --git a/hw/intc/realview_gic.c b/hw/intc/realview_gic.c
index 4ff48bb..6c81296 100644
--- a/hw/intc/realview_gic.c
+++ b/hw/intc/realview_gic.c
@@ -7,20 +7,7 @@
* This code is licensed under the GPL.
*/
-#include hw/sysbus.h
-#include hw/intc/arm_gic.h
-
-#define TYPE_REALVIEW_GIC realview_gic
-#define REALVIEW_GIC(obj) \
-OBJECT_CHECK(RealViewGICState, (obj), TYPE_REALVIEW_GIC)
-
-typedef struct RealViewGICState {
-SysBusDevice parent_obj;
-
-MemoryRegion container;
-
-GICState gic;
-} RealViewGICState;
+#include hw/intc/realview_gic.h
static void realview_gic_set_irq(void *opaque, int irq, int level)
{
diff --git a/include/hw/intc/realview_gic.h b/include/hw/intc/realview_gic.h
new file mode 100644
index 000..1783ea1
--- /dev/null
+++ b/include/hw/intc/realview_gic.h
@@ -0,0 +1,28 @@
+/*
+ * ARM RealView Emulation Baseboard Interrupt Controller
+ *
+ * Copyright (c) 2006-2007 CodeSourcery.
+ * Written by Paul Brook
+ *
+ * This code is licensed under the GPL.
+ */
+
+#ifndef HW_INTC_REALVIEW_GIC_H
+#define HW_INTC_REALVIEW_GIC_H
+
+#include hw/sysbus.h
+#include hw/intc/arm_gic.h
+
+#define TYPE_REALVIEW_GIC realview_gic
+#define REALVIEW_GIC(obj) \
+OBJECT_CHECK(RealViewGICState, (obj), TYPE_REALVIEW_GIC)
+
+typedef struct RealViewGICState {
+SysBusDevice parent_obj;
+
+MemoryRegion container;
+
+GICState gic;
+} RealViewGICState;
+
+#endif
--
1.8.1.4
[Qemu-devel] [PATCH v4 19/24] arm11mpcore: Convert ARM11MPCorePriveState to QOM realize
Embed child devices and replace SysBus initfn with realizefn.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/cpu/arm11mpcore.c | 84 ++--
1 file changed, 56 insertions(+), 28 deletions(-)
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
index 5dcc73a..f372283 100644
--- a/hw/cpu/arm11mpcore.c
+++ b/hw/cpu/arm11mpcore.c
@@ -9,6 +9,8 @@
#include hw/sysbus.h
#include hw/misc/arm11scu.h
+#include hw/intc/arm_gic.h
+#include hw/timer/arm_mptimer.h
#include qemu/timer.h
/* MPCore private memory region. */
@@ -22,12 +24,12 @@ typedef struct ARM11MPCorePriveState {
uint32_t num_cpu;
MemoryRegion container;
-DeviceState *mptimer;
-DeviceState *wdtimer;
-DeviceState *gic;
uint32_t num_irq;
ARM11SCUState scu;
+GICState gic;
+ARMMPTimerState mptimer;
+ARMMPTimerState wdtimer;
} ARM11MPCorePriveState;
/* Per-CPU private memory mapped IO. */
@@ -36,16 +38,18 @@ typedef struct ARM11MPCorePriveState {
static void mpcore_priv_set_irq(void *opaque, int irq, int level)
{
ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
-qemu_set_irq(qdev_get_gpio_in(s-gic, irq), level);
+
+qemu_set_irq(qdev_get_gpio_in(DEVICE(s-gic), irq), level);
}
static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
{
int i;
SysBusDevice *scubusdev = SYS_BUS_DEVICE(s-scu);
-SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s-gic);
-SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s-mptimer);
-SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s-wdtimer);
+DeviceState *gicdev = DEVICE(s-gic);
+SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s-gic);
+SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s-mptimer);
+SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s-wdtimer);
memory_region_add_subregion(s-container, 0,
sysbus_mmio_get_region(scubusdev, 0));
@@ -76,44 +80,58 @@ static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
for (i = 0; i s-num_cpu; i++) {
int ppibase = (s-num_irq - 32) + i * 32;
sysbus_connect_irq(timerbusdev, i,
- qdev_get_gpio_in(s-gic, ppibase + 29));
+ qdev_get_gpio_in(gicdev, ppibase + 29));
sysbus_connect_irq(wdtbusdev, i,
- qdev_get_gpio_in(s-gic, ppibase + 30));
+ qdev_get_gpio_in(gicdev, ppibase + 30));
}
}
-static int mpcore_priv_init(SysBusDevice *sbd)
+static void mpcore_priv_realize(DeviceState *dev, Error **errp)
{
-DeviceState *dev = DEVICE(sbd);
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
DeviceState *scudev = DEVICE(s-scu);
+DeviceState *gicdev = DEVICE(s-gic);
+DeviceState *mptimerdev = DEVICE(s-mptimer);
+DeviceState *wdtimerdev = DEVICE(s-wdtimer);
+Error *err = NULL;
qdev_prop_set_uint32(scudev, num-cpu, s-num_cpu);
-qdev_init_nofail(scudev);
+object_property_set_bool(OBJECT(s-scu), true, realized, err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
-s-gic = qdev_create(NULL, arm_gic);
-qdev_prop_set_uint32(s-gic, num-cpu, s-num_cpu);
-qdev_prop_set_uint32(s-gic, num-irq, s-num_irq);
-/* Request the legacy 11MPCore GIC behaviour: */
-qdev_prop_set_uint32(s-gic, revision, 0);
-qdev_init_nofail(s-gic);
+qdev_prop_set_uint32(gicdev, num-cpu, s-num_cpu);
+qdev_prop_set_uint32(gicdev, num-irq, s-num_irq);
+object_property_set_bool(OBJECT(s-gic), true, realized, err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
/* Pass through outbound IRQ lines from the GIC */
-sysbus_pass_irq(sbd, SYS_BUS_DEVICE(s-gic));
+sysbus_pass_irq(sbd, SYS_BUS_DEVICE(s-gic));
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(dev, mpcore_priv_set_irq, s-num_irq - 32);
-s-mptimer = qdev_create(NULL, arm_mptimer);
-qdev_prop_set_uint32(s-mptimer, num-cpu, s-num_cpu);
-qdev_init_nofail(s-mptimer);
+qdev_prop_set_uint32(mptimerdev, num-cpu, s-num_cpu);
+object_property_set_bool(OBJECT(s-mptimer), true, realized, err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
-s-wdtimer = qdev_create(NULL, arm_mptimer);
-qdev_prop_set_uint32(s-wdtimer, num-cpu, s-num_cpu);
-qdev_init_nofail(s-wdtimer);
+qdev_prop_set_uint32(wdtimerdev, num-cpu, s-num_cpu);
+object_property_set_bool(OBJECT(s-wdtimer), true, realized, err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
mpcore_priv_map_setup(s);
-return 0;
}
static void mpcore_priv_initfn(Object *obj)
@@ -127,6 +145,17 @@ static void mpcore_priv_initfn(Object *obj)
object_initialize(s-scu, sizeof(s-scu), TYPE_ARM11_SCU);
qdev_set_parent_bus(DEVICE(s-scu), sysbus_get_default
[Qemu-devel] [PATCH v4 23/24] arm11mpcore: Prepare for QOM embedding
Move state struct, type constant and cast macro to a new header.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/cpu/arm11mpcore.c | 27 +--
include/hw/cpu/arm11mpcore.h | 35 +++
2 files changed, 36 insertions(+), 26 deletions(-)
create mode 100644 include/hw/cpu/arm11mpcore.h
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
index 578e3d3..0ec27c7 100644
--- a/hw/cpu/arm11mpcore.c
+++ b/hw/cpu/arm11mpcore.c
@@ -7,33 +7,8 @@
* This code is licensed under the GPL.
*/
-#include hw/sysbus.h
-#include hw/misc/arm11scu.h
-#include hw/intc/arm_gic.h
+#include hw/cpu/arm11mpcore.h
#include hw/intc/realview_gic.h
-#include hw/timer/arm_mptimer.h
-#include qemu/timer.h
-
-/* MPCore private memory region. */
-
-#define TYPE_ARM11MPCORE_PRIV arm11mpcore_priv
-#define ARM11MPCORE_PRIV(obj) \
-OBJECT_CHECK(ARM11MPCorePriveState, (obj), TYPE_ARM11MPCORE_PRIV)
-
-typedef struct ARM11MPCorePriveState {
-SysBusDevice parent_obj;
-
-uint32_t num_cpu;
-MemoryRegion container;
-uint32_t num_irq;
-
-ARM11SCUState scu;
-GICState gic;
-ARMMPTimerState mptimer;
-ARMMPTimerState wdtimer;
-} ARM11MPCorePriveState;
-
-/* Per-CPU private memory mapped IO. */
static void mpcore_priv_set_irq(void *opaque, int irq, int level)
diff --git a/include/hw/cpu/arm11mpcore.h b/include/hw/cpu/arm11mpcore.h
new file mode 100644
index 000..6196109
--- /dev/null
+++ b/include/hw/cpu/arm11mpcore.h
@@ -0,0 +1,35 @@
+/*
+ * ARM11MPCore internal peripheral emulation.
+ *
+ * Copyright (c) 2006-2007 CodeSourcery.
+ * Written by Paul Brook
+ *
+ * This code is licensed under the GPL.
+ */
+
+#ifndef HW_CPU_ARM11MPCORE_H
+#define HW_CPU_ARM11MPCORE_H
+
+#include hw/sysbus.h
+#include hw/misc/arm11scu.h
+#include hw/intc/arm_gic.h
+#include hw/timer/arm_mptimer.h
+
+#define TYPE_ARM11MPCORE_PRIV arm11mpcore_priv
+#define ARM11MPCORE_PRIV(obj) \
+OBJECT_CHECK(ARM11MPCorePriveState, (obj), TYPE_ARM11MPCORE_PRIV)
+
+typedef struct ARM11MPCorePriveState {
+SysBusDevice parent_obj;
+
+uint32_t num_cpu;
+MemoryRegion container;
+uint32_t num_irq;
+
+ARM11SCUState scu;
+GICState gic;
+ARMMPTimerState mptimer;
+ARMMPTimerState wdtimer;
+} ARM11MPCorePriveState;
+
+#endif
--
1.8.1.4
[Qemu-devel] [PATCH v4 20/24] realview_gic: Convert to QOM realize
Embed GICState and replace SysBus initfn with realizefn.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/intc/realview_gic.c | 51 ++
1 file changed, 35 insertions(+), 16 deletions(-)
diff --git a/hw/intc/realview_gic.c b/hw/intc/realview_gic.c
index ce80447..4ff48bb 100644
--- a/hw/intc/realview_gic.c
+++ b/hw/intc/realview_gic.c
@@ -8,40 +8,46 @@
*/
#include hw/sysbus.h
+#include hw/intc/arm_gic.h
#define TYPE_REALVIEW_GIC realview_gic
#define REALVIEW_GIC(obj) \
OBJECT_CHECK(RealViewGICState, (obj), TYPE_REALVIEW_GIC)
-typedef struct {
+typedef struct RealViewGICState {
SysBusDevice parent_obj;
-DeviceState *gic;
MemoryRegion container;
+
+GICState gic;
} RealViewGICState;
static void realview_gic_set_irq(void *opaque, int irq, int level)
{
RealViewGICState *s = (RealViewGICState *)opaque;
-qemu_set_irq(qdev_get_gpio_in(s-gic, irq), level);
+
+qemu_set_irq(qdev_get_gpio_in(DEVICE(s-gic), irq), level);
}
-static int realview_gic_init(SysBusDevice *sbd)
+static void realview_gic_realize(DeviceState *dev, Error **errp)
{
-DeviceState *dev = DEVICE(sbd);
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
RealViewGICState *s = REALVIEW_GIC(dev);
SysBusDevice *busdev;
+Error *err = NULL;
/* The GICs on the RealView boards have a fixed nonconfigurable
* number of interrupt lines, so we don't need to expose this as
* a qdev property.
*/
int numirq = 96;
-s-gic = qdev_create(NULL, arm_gic);
-qdev_prop_set_uint32(s-gic, num-cpu, 1);
-qdev_prop_set_uint32(s-gic, num-irq, numirq);
-qdev_init_nofail(s-gic);
-busdev = SYS_BUS_DEVICE(s-gic);
+qdev_prop_set_uint32(DEVICE(s-gic), num-irq, numirq);
+object_property_set_bool(OBJECT(s-gic), true, realized, err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
+busdev = SYS_BUS_DEVICE(s-gic);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(sbd, busdev);
@@ -49,27 +55,40 @@ static int realview_gic_init(SysBusDevice *sbd)
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(dev, realview_gic_set_irq, numirq - 32);
-memory_region_init(s-container, OBJECT(s),
- realview-gic-container, 0x2000);
memory_region_add_subregion(s-container, 0,
sysbus_mmio_get_region(busdev, 1));
memory_region_add_subregion(s-container, 0x1000,
sysbus_mmio_get_region(busdev, 0));
+}
+
+static void realview_gic_init(Object *obj)
+{
+SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+RealViewGICState *s = REALVIEW_GIC(obj);
+DeviceState *gicdev;
+
+memory_region_init(s-container, OBJECT(s),
+ realview-gic-container, 0x2000);
sysbus_init_mmio(sbd, s-container);
-return 0;
+
+object_initialize(s-gic, sizeof(s-gic), TYPE_ARM_GIC);
+gicdev = DEVICE(s-gic);
+qdev_set_parent_bus(gicdev, sysbus_get_default());
+qdev_prop_set_uint32(gicdev, num-cpu, 1);
}
-static void realview_gic_class_init(ObjectClass *klass, void *data)
+static void realview_gic_class_init(ObjectClass *oc, void *data)
{
-SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+DeviceClass *dc = DEVICE_CLASS(oc);
-sdc-init = realview_gic_init;
+dc-realize = realview_gic_realize;
}
static const TypeInfo realview_gic_info = {
.name = TYPE_REALVIEW_GIC,
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(RealViewGICState),
+.instance_init = realview_gic_init,
.class_init= realview_gic_class_init,
};
--
1.8.1.4
[Qemu-devel] [PATCH v4 09/24] a9mpcore: Prepare for QOM embedding
From: Andreas Färber andreas.faer...@web.de
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 24 +---
include/hw/cpu/a9mpcore.h | 37 +
2 files changed, 38 insertions(+), 23 deletions(-)
create mode 100644 include/hw/cpu/a9mpcore.h
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index a162ff0..918a7d1 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -8,29 +8,7 @@
* This code is licensed under the GPL.
*/
-#include hw/sysbus.h
-#include hw/intc/arm_gic.h
-#include hw/misc/a9scu.h
-#include hw/timer/arm_mptimer.h
-
-#define TYPE_A9MPCORE_PRIV a9mpcore_priv
-#define A9MPCORE_PRIV(obj) \
-OBJECT_CHECK(A9MPPrivState, (obj), TYPE_A9MPCORE_PRIV)
-
-typedef struct A9MPPrivState {
-/* private */
-SysBusDevice parent_obj;
-/* public */
-
-uint32_t num_cpu;
-MemoryRegion container;
-uint32_t num_irq;
-
-GICState gic;
-A9SCUState scu;
-ARMMPTimerState mptimer;
-ARMMPTimerState wdt;
-} A9MPPrivState;
+#include hw/cpu/a9mpcore.h
static void a9mp_priv_set_irq(void *opaque, int irq, int level)
{
diff --git a/include/hw/cpu/a9mpcore.h b/include/hw/cpu/a9mpcore.h
new file mode 100644
index 000..010489b
--- /dev/null
+++ b/include/hw/cpu/a9mpcore.h
@@ -0,0 +1,37 @@
+/*
+ * Cortex-A9MPCore internal peripheral emulation.
+ *
+ * Copyright (c) 2009 CodeSourcery.
+ * Copyright (c) 2011 Linaro Limited.
+ * Written by Paul Brook, Peter Maydell.
+ *
+ * This code is licensed under the GPL.
+ */
+#ifndef HW_CPU_A9MPCORE_H
+#define HW_CPU_A9MPCORE_H
+
+#include hw/sysbus.h
+#include hw/intc/arm_gic.h
+#include hw/misc/a9scu.h
+#include hw/timer/arm_mptimer.h
+
+#define TYPE_A9MPCORE_PRIV a9mpcore_priv
+#define A9MPCORE_PRIV(obj) \
+OBJECT_CHECK(A9MPPrivState, (obj), TYPE_A9MPCORE_PRIV)
+
+typedef struct A9MPPrivState {
+/* private */
+SysBusDevice parent_obj;
+/* public */
+
+uint32_t num_cpu;
+MemoryRegion container;
+uint32_t num_irq;
+
+GICState gic;
+A9SCUState scu;
+ARMMPTimerState mptimer;
+ARMMPTimerState wdt;
+} A9MPPrivState;
+
+#endif
--
1.8.1.4
[Qemu-devel] [PATCH v4 22/24] arm11mpcore: Convert mpcore_rirq_state to QOM realize
Embed ARM11MPCorePriveState and RealViewGICState and replace SysBus
initfn with realizefn.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/cpu/arm11mpcore.c | 58 +++-
1 file changed, 44 insertions(+), 14 deletions(-)
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
index f372283..578e3d3 100644
--- a/hw/cpu/arm11mpcore.c
+++ b/hw/cpu/arm11mpcore.c
@@ -10,6 +10,7 @@
#include hw/sysbus.h
#include hw/misc/arm11scu.h
#include hw/intc/arm_gic.h
+#include hw/intc/realview_gic.h
#include hw/timer/arm_mptimer.h
#include qemu/timer.h
@@ -168,10 +169,12 @@ static void mpcore_priv_initfn(Object *obj)
typedef struct {
SysBusDevice parent_obj;
-SysBusDevice *priv;
qemu_irq cpuic[32];
qemu_irq rvic[4][64];
uint32_t num_cpu;
+
+ARM11MPCorePriveState priv;
+RealViewGICState gic[4];
} mpcore_rirq_state;
/* Map baseboard IRQs onto CPU IRQ lines. */
@@ -198,34 +201,61 @@ static void mpcore_rirq_set_irq(void *opaque, int irq,
int level)
}
}
-static int realview_mpcore_init(SysBusDevice *sbd)
+static void realview_mpcore_realize(DeviceState *dev, Error **errp)
{
-DeviceState *dev = DEVICE(sbd);
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
+DeviceState *priv = DEVICE(s-priv);
DeviceState *gic;
-DeviceState *priv;
+SysBusDevice *gicbusdev;
+Error *err = NULL;
int n;
int i;
-priv = qdev_create(NULL, TYPE_ARM11MPCORE_PRIV);
qdev_prop_set_uint32(priv, num-cpu, s-num_cpu);
-qdev_init_nofail(priv);
-s-priv = SYS_BUS_DEVICE(priv);
-sysbus_pass_irq(sbd, s-priv);
+object_property_set_bool(OBJECT(s-priv), true, realized, err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
+sysbus_pass_irq(sbd, SYS_BUS_DEVICE(s-priv));
for (i = 0; i 32; i++) {
s-cpuic[i] = qdev_get_gpio_in(priv, i);
}
/* ??? IRQ routing is hardcoded to normal mode. */
for (n = 0; n 4; n++) {
-gic = sysbus_create_simple(realview_gic, 0x1004 + n * 0x1,
- s-cpuic[10 + n]);
+object_property_set_bool(OBJECT(s-gic[n]), true, realized, err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
+gic = DEVICE(s-gic[n]);
+gicbusdev = SYS_BUS_DEVICE(s-gic[n]);
+sysbus_mmio_map(gicbusdev, 0, 0x1004 + n * 0x1);
+sysbus_connect_irq(gicbusdev, 0, s-cpuic[10 + n]);
for (i = 0; i 64; i++) {
s-rvic[n][i] = qdev_get_gpio_in(gic, i);
}
}
qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
-sysbus_init_mmio(sbd, sysbus_mmio_get_region(s-priv, 0));
-return 0;
+}
+
+static void mpcore_rirq_init(Object *obj)
+{
+SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(obj);
+SysBusDevice *privbusdev;
+int i;
+
+object_initialize(s-priv, sizeof(s-priv), TYPE_ARM11MPCORE_PRIV);
+qdev_set_parent_bus(DEVICE(s-priv), sysbus_get_default());
+privbusdev = SYS_BUS_DEVICE(s-priv);
+sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
+
+for (i = 0; i 4; i++) {
+object_initialize(s-gic[i], sizeof(s-gic[i]), TYPE_REALVIEW_GIC);
+qdev_set_parent_bus(DEVICE(s-gic[i]), sysbus_get_default());
+}
}
static Property mpcore_rirq_properties[] = {
@@ -236,9 +266,8 @@ static Property mpcore_rirq_properties[] = {
static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
-SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-k-init = realview_mpcore_init;
+dc-realize = realview_mpcore_realize;
dc-props = mpcore_rirq_properties;
}
@@ -246,6 +275,7 @@ static const TypeInfo mpcore_rirq_info = {
.name = TYPE_REALVIEW_MPCORE_RIRQ,
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(mpcore_rirq_state),
+.instance_init = mpcore_rirq_init,
.class_init= mpcore_rirq_class_init,
};
--
1.8.1.4
[Qemu-devel] [PATCH v4 05/24] a9mpcore: Embed A9SCUState
From: Andreas Färber andreas.faer...@web.de
Prepares for QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 16 ++--
hw/misc/a9scu.c | 18 +-
include/hw/misc/a9scu.h | 31 +++
3 files changed, 42 insertions(+), 23 deletions(-)
create mode 100644 include/hw/misc/a9scu.h
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index c57b149..df92e3f 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -10,6 +10,7 @@
#include hw/sysbus.h
#include hw/intc/arm_gic.h
+#include hw/misc/a9scu.h
#define TYPE_A9MPCORE_PRIV a9mpcore_priv
#define A9MPCORE_PRIV(obj) \
@@ -24,10 +25,10 @@ typedef struct A9MPPrivState {
MemoryRegion container;
DeviceState *mptimer;
DeviceState *wdt;
-DeviceState *scu;
uint32_t num_irq;
GICState gic;
+A9SCUState scu;
} A9MPPrivState;
static void a9mp_priv_set_irq(void *opaque, int irq, int level)
@@ -46,12 +47,15 @@ static void a9mp_priv_initfn(Object *obj)
object_initialize(s-gic, sizeof(s-gic), TYPE_ARM_GIC);
qdev_set_parent_bus(DEVICE(s-gic), sysbus_get_default());
+
+object_initialize(s-scu, sizeof(s-scu), TYPE_A9_SCU);
+qdev_set_parent_bus(DEVICE(s-scu), sysbus_get_default());
}
static int a9mp_priv_init(SysBusDevice *dev)
{
A9MPPrivState *s = A9MPCORE_PRIV(dev);
-DeviceState *gicdev;
+DeviceState *gicdev, *scudev;
SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev;
int i;
@@ -67,10 +71,10 @@ static int a9mp_priv_init(SysBusDevice *dev)
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(DEVICE(dev), a9mp_priv_set_irq, s-num_irq - 32);
-s-scu = qdev_create(NULL, a9-scu);
-qdev_prop_set_uint32(s-scu, num-cpu, s-num_cpu);
-qdev_init_nofail(s-scu);
-scubusdev = SYS_BUS_DEVICE(s-scu);
+scudev = DEVICE(s-scu);
+qdev_prop_set_uint32(scudev, num-cpu, s-num_cpu);
+qdev_init_nofail(scudev);
+scubusdev = SYS_BUS_DEVICE(s-scu);
s-mptimer = qdev_create(NULL, arm_mptimer);
qdev_prop_set_uint32(s-mptimer, num-cpu, s-num_cpu);
diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
index 2661014..4434945 100644
--- a/hw/misc/a9scu.c
+++ b/hw/misc/a9scu.c
@@ -8,23 +8,7 @@
* This code is licensed under the GPL.
*/
-#include hw/sysbus.h
-
-/* A9MP private memory region. */
-
-typedef struct A9SCUState {
-/* private */
-SysBusDevice parent_obj;
-/* public */
-
-MemoryRegion iomem;
-uint32_t control;
-uint32_t status;
-uint32_t num_cpu;
-} A9SCUState;
-
-#define TYPE_A9_SCU a9-scu
-#define A9_SCU(obj) OBJECT_CHECK(A9SCUState, (obj), TYPE_A9_SCU)
+#include hw/misc/a9scu.h
static uint64_t a9_scu_read(void *opaque, hwaddr offset,
unsigned size)
diff --git a/include/hw/misc/a9scu.h b/include/hw/misc/a9scu.h
new file mode 100644
index 000..efb0c30
--- /dev/null
+++ b/include/hw/misc/a9scu.h
@@ -0,0 +1,31 @@
+/*
+ * Cortex-A9MPCore Snoop Control Unit (SCU) emulation.
+ *
+ * Copyright (c) 2009 CodeSourcery.
+ * Copyright (c) 2011 Linaro Limited.
+ * Written by Paul Brook, Peter Maydell.
+ *
+ * This code is licensed under the GPL.
+ */
+#ifndef HW_MISC_A9SCU_H
+#define HW_MISC_A9SCU_H
+
+#include hw/sysbus.h
+
+/* A9MP private memory region. */
+
+typedef struct A9SCUState {
+/* private */
+SysBusDevice parent_obj;
+/* public */
+
+MemoryRegion iomem;
+uint32_t control;
+uint32_t status;
+uint32_t num_cpu;
+} A9SCUState;
+
+#define TYPE_A9_SCU a9-scu
+#define A9_SCU(obj) OBJECT_CHECK(A9SCUState, (obj), TYPE_A9_SCU)
+
+#endif
--
1.8.1.4
[Qemu-devel] [PATCH v4 24/24] arm11mpcore: Split off RealView MPCore
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/cpu/Makefile.objs | 1 +
hw/cpu/arm11mpcore.c | 121 -
hw/cpu/realview_mpcore.c | 139 +++
3 files changed, 140 insertions(+), 121 deletions(-)
create mode 100644 hw/cpu/realview_mpcore.c
diff --git a/hw/cpu/Makefile.objs b/hw/cpu/Makefile.objs
index df287c1..6381238 100644
--- a/hw/cpu/Makefile.objs
+++ b/hw/cpu/Makefile.objs
@@ -1,4 +1,5 @@
obj-$(CONFIG_ARM11MPCORE) += arm11mpcore.o
+obj-$(CONFIG_REALVIEW) += realview_mpcore.o
obj-$(CONFIG_A9MPCORE) += a9mpcore.o
obj-$(CONFIG_A15MPCORE) += a15mpcore.o
obj-$(CONFIG_ICC_BUS) += icc_bus.o
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
index 0ec27c7..717d3e4 100644
--- a/hw/cpu/arm11mpcore.c
+++ b/hw/cpu/arm11mpcore.c
@@ -134,126 +134,6 @@ static void mpcore_priv_initfn(Object *obj)
qdev_set_parent_bus(DEVICE(s-wdtimer), sysbus_get_default());
}
-#define TYPE_REALVIEW_MPCORE_RIRQ realview_mpcore
-#define REALVIEW_MPCORE_RIRQ(obj) \
-OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)
-
-/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
- controllers. The output of these, plus some of the raw input lines
- are fed into a single SMP-aware interrupt controller on the CPU. */
-typedef struct {
-SysBusDevice parent_obj;
-
-qemu_irq cpuic[32];
-qemu_irq rvic[4][64];
-uint32_t num_cpu;
-
-ARM11MPCorePriveState priv;
-RealViewGICState gic[4];
-} mpcore_rirq_state;
-
-/* Map baseboard IRQs onto CPU IRQ lines. */
-static const int mpcore_irq_map[32] = {
--1, -1, -1, -1, 1, 2, -1, -1,
--1, -1, 6, -1, 4, 5, -1, -1,
--1, 14, 15, 0, 7, 8, -1, -1,
--1, -1, -1, -1, 9, 3, -1, -1,
-};
-
-static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
-{
-mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
-int i;
-
-for (i = 0; i 4; i++) {
-qemu_set_irq(s-rvic[i][irq], level);
-}
-if (irq 32) {
-irq = mpcore_irq_map[irq];
-if (irq = 0) {
-qemu_set_irq(s-cpuic[irq], level);
-}
-}
-}
-
-static void realview_mpcore_realize(DeviceState *dev, Error **errp)
-{
-SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
-mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
-DeviceState *priv = DEVICE(s-priv);
-DeviceState *gic;
-SysBusDevice *gicbusdev;
-Error *err = NULL;
-int n;
-int i;
-
-qdev_prop_set_uint32(priv, num-cpu, s-num_cpu);
-object_property_set_bool(OBJECT(s-priv), true, realized, err);
-if (err != NULL) {
-error_propagate(errp, err);
-return;
-}
-sysbus_pass_irq(sbd, SYS_BUS_DEVICE(s-priv));
-for (i = 0; i 32; i++) {
-s-cpuic[i] = qdev_get_gpio_in(priv, i);
-}
-/* ??? IRQ routing is hardcoded to normal mode. */
-for (n = 0; n 4; n++) {
-object_property_set_bool(OBJECT(s-gic[n]), true, realized, err);
-if (err != NULL) {
-error_propagate(errp, err);
-return;
-}
-gic = DEVICE(s-gic[n]);
-gicbusdev = SYS_BUS_DEVICE(s-gic[n]);
-sysbus_mmio_map(gicbusdev, 0, 0x1004 + n * 0x1);
-sysbus_connect_irq(gicbusdev, 0, s-cpuic[10 + n]);
-for (i = 0; i 64; i++) {
-s-rvic[n][i] = qdev_get_gpio_in(gic, i);
-}
-}
-qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
-}
-
-static void mpcore_rirq_init(Object *obj)
-{
-SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(obj);
-SysBusDevice *privbusdev;
-int i;
-
-object_initialize(s-priv, sizeof(s-priv), TYPE_ARM11MPCORE_PRIV);
-qdev_set_parent_bus(DEVICE(s-priv), sysbus_get_default());
-privbusdev = SYS_BUS_DEVICE(s-priv);
-sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
-
-for (i = 0; i 4; i++) {
-object_initialize(s-gic[i], sizeof(s-gic[i]), TYPE_REALVIEW_GIC);
-qdev_set_parent_bus(DEVICE(s-gic[i]), sysbus_get_default());
-}
-}
-
-static Property mpcore_rirq_properties[] = {
-DEFINE_PROP_UINT32(num-cpu, mpcore_rirq_state, num_cpu, 1),
-DEFINE_PROP_END_OF_LIST(),
-};
-
-static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
-{
-DeviceClass *dc = DEVICE_CLASS(klass);
-
-dc-realize = realview_mpcore_realize;
-dc-props = mpcore_rirq_properties;
-}
-
-static const TypeInfo mpcore_rirq_info = {
-.name = TYPE_REALVIEW_MPCORE_RIRQ,
-.parent= TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(mpcore_rirq_state),
-.instance_init = mpcore_rirq_init,
-.class_init= mpcore_rirq_class_init,
-};
-
static Property mpcore_priv_properties[] = {
DEFINE_PROP_UINT32(num-cpu, ARM11MPCorePriveState, num_cpu, 1),
/* The ARM11 MPCORE TRM says the on-chip controller may have
@@ -286,7 +166,6 @@ static const TypeInfo mpcore_priv_info = {
static void
[Qemu-devel] [PATCH v4 03/24] a9mpcore: Embed GICState
From: Andreas Färber andreas.faer...@web.de
Prepares for conversion to QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index acbdab5..c57b149 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -9,6 +9,7 @@
*/
#include hw/sysbus.h
+#include hw/intc/arm_gic.h
#define TYPE_A9MPCORE_PRIV a9mpcore_priv
#define A9MPCORE_PRIV(obj) \
@@ -23,15 +24,17 @@ typedef struct A9MPPrivState {
MemoryRegion container;
DeviceState *mptimer;
DeviceState *wdt;
-DeviceState *gic;
DeviceState *scu;
uint32_t num_irq;
+
+GICState gic;
} A9MPPrivState;
static void a9mp_priv_set_irq(void *opaque, int irq, int level)
{
A9MPPrivState *s = (A9MPPrivState *)opaque;
-qemu_set_irq(qdev_get_gpio_in(s-gic, irq), level);
+
+qemu_set_irq(qdev_get_gpio_in(DEVICE(s-gic), irq), level);
}
static void a9mp_priv_initfn(Object *obj)
@@ -40,19 +43,23 @@ static void a9mp_priv_initfn(Object *obj)
memory_region_init(s-container, obj, a9mp-priv-container, 0x2000);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), s-container);
+
+object_initialize(s-gic, sizeof(s-gic), TYPE_ARM_GIC);
+qdev_set_parent_bus(DEVICE(s-gic), sysbus_get_default());
}
static int a9mp_priv_init(SysBusDevice *dev)
{
A9MPPrivState *s = A9MPCORE_PRIV(dev);
+DeviceState *gicdev;
SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev;
int i;
-s-gic = qdev_create(NULL, arm_gic);
-qdev_prop_set_uint32(s-gic, num-cpu, s-num_cpu);
-qdev_prop_set_uint32(s-gic, num-irq, s-num_irq);
-qdev_init_nofail(s-gic);
-gicbusdev = SYS_BUS_DEVICE(s-gic);
+gicdev = DEVICE(s-gic);
+qdev_prop_set_uint32(gicdev, num-cpu, s-num_cpu);
+qdev_prop_set_uint32(gicdev, num-irq, s-num_irq);
+qdev_init_nofail(gicdev);
+gicbusdev = SYS_BUS_DEVICE(s-gic);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(dev, gicbusdev);
@@ -107,9 +114,9 @@ static int a9mp_priv_init(SysBusDevice *dev)
for (i = 0; i s-num_cpu; i++) {
int ppibase = (s-num_irq - 32) + i * 32;
sysbus_connect_irq(timerbusdev, i,
- qdev_get_gpio_in(s-gic, ppibase + 29));
+ qdev_get_gpio_in(gicdev, ppibase + 29));
sysbus_connect_irq(wdtbusdev, i,
- qdev_get_gpio_in(s-gic, ppibase + 30));
+ qdev_get_gpio_in(gicdev, ppibase + 30));
}
return 0;
}
--
1.8.1.4
[Qemu-devel] [PATCH v4 02/24] arm_gic: Extract headers hw/intc/arm_gic{, _common}.h
Rename NCPU to GIC_NCPU and move GICState away from gic_internal.h.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/intc/arm_gic_common.c | 18
hw/intc/gic_internal.h | 80 +-
include/hw/intc/arm_gic.h| 42 ++
include/hw/intc/arm_gic_common.h | 92
4 files changed, 145 insertions(+), 87 deletions(-)
create mode 100644 include/hw/intc/arm_gic.h
create mode 100644 include/hw/intc/arm_gic_common.h
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index 709b5c2..c765850 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -64,17 +64,17 @@ static const VMStateDescription vmstate_gic = {
.post_load = gic_post_load,
.fields = (VMStateField[]) {
VMSTATE_BOOL(enabled, GICState),
-VMSTATE_BOOL_ARRAY(cpu_enabled, GICState, NCPU),
+VMSTATE_BOOL_ARRAY(cpu_enabled, GICState, GIC_NCPU),
VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
vmstate_gic_irq_state, gic_irq_state),
VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
-VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, NCPU),
+VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
-VMSTATE_UINT16_2DARRAY(last_active, GICState, GIC_MAXIRQ, NCPU),
-VMSTATE_UINT16_ARRAY(priority_mask, GICState, NCPU),
-VMSTATE_UINT16_ARRAY(running_irq, GICState, NCPU),
-VMSTATE_UINT16_ARRAY(running_priority, GICState, NCPU),
-VMSTATE_UINT16_ARRAY(current_pending, GICState, NCPU),
+VMSTATE_UINT16_2DARRAY(last_active, GICState, GIC_MAXIRQ, GIC_NCPU),
+VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU),
+VMSTATE_UINT16_ARRAY(running_irq, GICState, GIC_NCPU),
+VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU),
+VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
VMSTATE_END_OF_LIST()
}
};
@@ -84,9 +84,9 @@ static void arm_gic_common_realize(DeviceState *dev, Error
**errp)
GICState *s = ARM_GIC_COMMON(dev);
int num_irq = s-num_irq;
-if (s-num_cpu NCPU) {
+if (s-num_cpu GIC_NCPU) {
error_setg(errp, requested %u CPUs exceeds GIC maximum %d,
- s-num_cpu, NCPU);
+ s-num_cpu, GIC_NCPU);
return;
}
s-num_irq += GIC_BASE_IRQ;
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index 1426437..3989fd1 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -21,16 +21,9 @@
#ifndef QEMU_ARM_GIC_INTERNAL_H
#define QEMU_ARM_GIC_INTERNAL_H
-#include hw/sysbus.h
+#include hw/intc/arm_gic.h
-/* Maximum number of possible interrupts, determined by the GIC architecture */
-#define GIC_MAXIRQ 1020
-/* First 32 are private to each CPU (SGIs and PPIs). */
-#define GIC_INTERNAL 32
-/* Maximum number of possible CPU interfaces, determined by GIC architecture */
-#define NCPU 8
-
-#define ALL_CPU_MASK ((unsigned)(((1 NCPU) - 1)))
+#define ALL_CPU_MASK ((unsigned)(((1 GIC_NCPU) - 1)))
/* The NVIC has 16 internal vectors. However these are not exposed
through the normal GIC interface. */
@@ -59,48 +52,6 @@
s-priority2[(irq) - GIC_INTERNAL])
#define GIC_TARGET(irq) s-irq_target[irq]
-typedef struct gic_irq_state {
-/* The enable bits are only banked for per-cpu interrupts. */
-uint8_t enabled;
-uint8_t pending;
-uint8_t active;
-uint8_t level;
-bool model; /* 0 = N:N, 1 = 1:N */
-bool trigger; /* nonzero = edge triggered. */
-} gic_irq_state;
-
-typedef struct GICState {
-/* private */
-SysBusDevice parent_obj;
-/* public */
-
-qemu_irq parent_irq[NCPU];
-bool enabled;
-bool cpu_enabled[NCPU];
-
-gic_irq_state irq_state[GIC_MAXIRQ];
-uint8_t irq_target[GIC_MAXIRQ];
-uint8_t priority1[GIC_INTERNAL][NCPU];
-uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
-uint16_t last_active[GIC_MAXIRQ][NCPU];
-
-uint16_t priority_mask[NCPU];
-uint16_t running_irq[NCPU];
-uint16_t running_priority[NCPU];
-uint16_t current_pending[NCPU];
-
-uint32_t num_cpu;
-
-MemoryRegion iomem; /* Distributor */
-/* This is just so we can have an opaque pointer which identifies
- * both this GIC and which CPU interface we should be accessing.
- */
-struct GICState *backref[NCPU];
-MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */
-uint32_t num_irq;
-uint32_t revision;
-} GICState;
-
/* The special cases for the revision property: */
#define REV_11MPCORE 0
#define REV_NVIC 0x
@@ -111,31 +62,4 @@ void gic_complete_irq(GICState *s, int cpu, int irq);
void gic_update(GICState *s);
void gic_init_irqs_and_distributor(GICState *s, int num_irq);
-#define TYPE_ARM_GIC_COMMON
[Qemu-devel] [PATCH v4 08/24] a9mpcore: Convert to QOM realize
From: Andreas Färber andreas.faer...@web.de
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 36 ++--
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index db3907e..a162ff0 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -59,38 +59,56 @@ static void a9mp_priv_initfn(Object *obj)
qdev_set_parent_bus(DEVICE(s-wdt), sysbus_get_default());
}
-static int a9mp_priv_init(SysBusDevice *dev)
+static void a9mp_priv_realize(DeviceState *dev, Error **errp)
{
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
A9MPPrivState *s = A9MPCORE_PRIV(dev);
DeviceState *gicdev, *scudev, *mptimerdev, *wdtdev;
SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev;
+Error *err = NULL;
int i;
gicdev = DEVICE(s-gic);
qdev_prop_set_uint32(gicdev, num-cpu, s-num_cpu);
qdev_prop_set_uint32(gicdev, num-irq, s-num_irq);
-qdev_init_nofail(gicdev);
+object_property_set_bool(OBJECT(s-gic), true, realized, err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
gicbusdev = SYS_BUS_DEVICE(s-gic);
/* Pass through outbound IRQ lines from the GIC */
-sysbus_pass_irq(dev, gicbusdev);
+sysbus_pass_irq(sbd, gicbusdev);
/* Pass through inbound GPIO lines to the GIC */
-qdev_init_gpio_in(DEVICE(dev), a9mp_priv_set_irq, s-num_irq - 32);
+qdev_init_gpio_in(dev, a9mp_priv_set_irq, s-num_irq - 32);
scudev = DEVICE(s-scu);
qdev_prop_set_uint32(scudev, num-cpu, s-num_cpu);
-qdev_init_nofail(scudev);
+object_property_set_bool(OBJECT(s-scu), true, realized, err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
scubusdev = SYS_BUS_DEVICE(s-scu);
mptimerdev = DEVICE(s-mptimer);
qdev_prop_set_uint32(mptimerdev, num-cpu, s-num_cpu);
-qdev_init_nofail(mptimerdev);
+object_property_set_bool(OBJECT(s-mptimer), true, realized, err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
timerbusdev = SYS_BUS_DEVICE(s-mptimer);
wdtdev = DEVICE(s-wdt);
qdev_prop_set_uint32(wdtdev, num-cpu, s-num_cpu);
-qdev_init_nofail(wdtdev);
+object_property_set_bool(OBJECT(s-wdt), true, realized, err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
wdtbusdev = SYS_BUS_DEVICE(s-wdt);
/* Memory map (addresses are offsets from PERIPHBASE):
@@ -129,7 +147,6 @@ static int a9mp_priv_init(SysBusDevice *dev)
sysbus_connect_irq(wdtbusdev, i,
qdev_get_gpio_in(gicdev, ppibase + 30));
}
-return 0;
}
static Property a9mp_priv_properties[] = {
@@ -147,9 +164,8 @@ static Property a9mp_priv_properties[] = {
static void a9mp_priv_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
-SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-k-init = a9mp_priv_init;
+dc-realize = a9mp_priv_realize;
dc-props = a9mp_priv_properties;
}
--
1.8.1.4
[Qemu-devel] [PATCH v4 14/24] a9scu: Build only once
It does not have a target or ARMCPU dependency. Signed-off-by: Andreas Färber afaer...@suse.de --- hw/misc/Makefile.objs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 2578e29..5636299 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -10,6 +10,7 @@ obj-$(CONFIG_VMPORT) += vmport.o # ARM devices common-obj-$(CONFIG_PL310) += arm_l2x0.o +common-obj-$(CONFIG_A9SCU) += a9scu.o # PKUnity SoC devices common-obj-$(CONFIG_PUV3) += puv3_pm.o @@ -22,7 +23,6 @@ obj-$(CONFIG_LINUX) += vfio.o endif obj-$(CONFIG_REALVIEW) += arm_sysctl.o -obj-$(CONFIG_A9SCU) += a9scu.o obj-$(CONFIG_NSERIES) += cbus.o obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o -- 1.8.1.4
[Qemu-devel] [PATCH v4 18/24] arm11mpcore: Split off SCU device
Inspired by a9scu.
Signed-off-by: Andreas Färber afaer...@suse.de
---
default-configs/arm-softmmu.mak | 1 +
hw/cpu/arm11mpcore.c| 65 ++
hw/misc/Makefile.objs | 1 +
hw/misc/arm11scu.c | 100
include/hw/misc/arm11scu.h | 29
5 files changed, 145 insertions(+), 51 deletions(-)
create mode 100644 hw/misc/arm11scu.c
create mode 100644 include/hw/misc/arm11scu.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index ac0815d..52d263a 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -62,6 +62,7 @@ CONFIG_BITBANG_I2C=y
CONFIG_FRAMEBUFFER=y
CONFIG_XILINX_SPIPS=y
+CONFIG_ARM11SCU=y
CONFIG_A9SCU=y
CONFIG_MARVELL_88W8618=y
CONFIG_OMAP=y
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
index 5f80e7b..5dcc73a 100644
--- a/hw/cpu/arm11mpcore.c
+++ b/hw/cpu/arm11mpcore.c
@@ -8,6 +8,7 @@
*/
#include hw/sysbus.h
+#include hw/misc/arm11scu.h
#include qemu/timer.h
/* MPCore private memory region. */
@@ -19,64 +20,18 @@
typedef struct ARM11MPCorePriveState {
SysBusDevice parent_obj;
-uint32_t scu_control;
uint32_t num_cpu;
-MemoryRegion iomem;
MemoryRegion container;
DeviceState *mptimer;
DeviceState *wdtimer;
DeviceState *gic;
uint32_t num_irq;
+
+ARM11SCUState scu;
} ARM11MPCorePriveState;
/* Per-CPU private memory mapped IO. */
-static uint64_t mpcore_scu_read(void *opaque, hwaddr offset,
-unsigned size)
-{
-ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
-int id;
-/* SCU */
-switch (offset) {
-case 0x00: /* Control. */
-return s-scu_control;
-case 0x04: /* Configuration. */
-id = ((1 s-num_cpu) - 1) 4;
-return id | (s-num_cpu - 1);
-case 0x08: /* CPU status. */
-return 0;
-case 0x0c: /* Invalidate all. */
-return 0;
-default:
-qemu_log_mask(LOG_GUEST_ERROR,
- mpcore_priv_read: Bad offset %x\n, (int)offset);
-return 0;
-}
-}
-
-static void mpcore_scu_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned size)
-{
-ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
-/* SCU */
-switch (offset) {
-case 0: /* Control register. */
-s-scu_control = value 1;
-break;
-case 0x0c: /* Invalidate all. */
-/* This is a no-op as cache is not emulated. */
-break;
-default:
-qemu_log_mask(LOG_GUEST_ERROR,
- mpcore_priv_read: Bad offset %x\n, (int)offset);
-}
-}
-
-static const MemoryRegionOps mpcore_scu_ops = {
-.read = mpcore_scu_read,
-.write = mpcore_scu_write,
-.endianness = DEVICE_NATIVE_ENDIAN,
-};
static void mpcore_priv_set_irq(void *opaque, int irq, int level)
{
@@ -87,12 +42,13 @@ static void mpcore_priv_set_irq(void *opaque, int irq, int
level)
static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
{
int i;
+SysBusDevice *scubusdev = SYS_BUS_DEVICE(s-scu);
SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s-gic);
SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s-mptimer);
SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s-wdtimer);
-memory_region_init_io(s-iomem, OBJECT(s),
- mpcore_scu_ops, s, mpcore-scu, 0x100);
-memory_region_add_subregion(s-container, 0, s-iomem);
+
+memory_region_add_subregion(s-container, 0,
+sysbus_mmio_get_region(scubusdev, 0));
/* GIC CPU interfaces: current CPU at 0x100, then specific CPUs
* at 0x200, 0x300...
*/
@@ -130,6 +86,10 @@ static int mpcore_priv_init(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
+DeviceState *scudev = DEVICE(s-scu);
+
+qdev_prop_set_uint32(scudev, num-cpu, s-num_cpu);
+qdev_init_nofail(scudev);
s-gic = qdev_create(NULL, arm_gic);
qdev_prop_set_uint32(s-gic, num-cpu, s-num_cpu);
@@ -164,6 +124,9 @@ static void mpcore_priv_initfn(Object *obj)
memory_region_init(s-container, OBJECT(s),
mpcore-priv-container, 0x2000);
sysbus_init_mmio(sbd, s-container);
+
+object_initialize(s-scu, sizeof(s-scu), TYPE_ARM11_SCU);
+qdev_set_parent_bus(DEVICE(s-scu), sysbus_get_default());
}
#define TYPE_REALVIEW_MPCORE_RIRQ realview_mpcore
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 5636299..a30bf5e 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -11,6 +11,7 @@ obj-$(CONFIG_VMPORT) += vmport.o
# ARM devices
common-obj-$(CONFIG_PL310) += arm_l2x0.o
common-obj-$(CONFIG_A9SCU) += a9scu.o
+common-obj-$(CONFIG_ARM11SCU) += arm11scu.o
# PKUnity SoC devices
common-obj-$(CONFIG_PUV3) += puv3_pm.o
diff --git a/hw/misc/arm11scu.c b/hw/misc
[Qemu-devel] [PATCH v4 12/24] a15mpcore: Convert to QOM realize
From: Andreas Färber andreas.faer...@web.de
Turn SysBusDevice initfn into a QOM realizefn.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a15mpcore.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index b2614e7..10dc35a 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -67,24 +67,30 @@ static void a15mp_priv_initfn(Object *obj)
qdev_prop_set_uint32(gicdev, revision, 2);
}
-static int a15mp_priv_init(SysBusDevice *dev)
+static void a15mp_priv_realize(DeviceState *dev, Error **errp)
{
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
A15MPPrivState *s = A15MPCORE_PRIV(dev);
DeviceState *gicdev;
SysBusDevice *busdev;
int i;
+Error *err = NULL;
gicdev = DEVICE(s-gic);
qdev_prop_set_uint32(gicdev, num-cpu, s-num_cpu);
qdev_prop_set_uint32(gicdev, num-irq, s-num_irq);
-qdev_init_nofail(gicdev);
+object_property_set_bool(OBJECT(s-gic), true, realized, err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
busdev = SYS_BUS_DEVICE(s-gic);
/* Pass through outbound IRQ lines from the GIC */
-sysbus_pass_irq(dev, busdev);
+sysbus_pass_irq(sbd, busdev);
/* Pass through inbound GPIO lines to the GIC */
-qdev_init_gpio_in(DEVICE(dev), a15mp_priv_set_irq, s-num_irq - 32);
+qdev_init_gpio_in(dev, a15mp_priv_set_irq, s-num_irq - 32);
/* Wire the outputs from each CPU's generic timer to the
* appropriate GIC PPI inputs
@@ -114,8 +120,6 @@ static int a15mp_priv_init(SysBusDevice *dev)
sysbus_mmio_get_region(busdev, 0));
memory_region_add_subregion(s-container, 0x2000,
sysbus_mmio_get_region(busdev, 1));
-
-return 0;
}
static Property a15mp_priv_properties[] = {
@@ -133,8 +137,8 @@ static Property a15mp_priv_properties[] = {
static void a15mp_priv_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
-SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-k-init = a15mp_priv_init;
+
+dc-realize = a15mp_priv_realize;
dc-props = a15mp_priv_properties;
/* We currently have no savable state */
}
--
1.8.1.4
[Qemu-devel] [PATCH v4 11/24] a15mpcore: Embed GICState
From: Andreas Färber andreas.faer...@web.de
This covers both emulated and KVM GIC.
Prepares for QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a15mpcore.c | 39 ---
1 file changed, 24 insertions(+), 15 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index af29c35..b2614e7 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -20,6 +20,7 @@
#include hw/sysbus.h
#include sysemu/kvm.h
+#include hw/intc/arm_gic.h
/* A15MP private memory region. */
@@ -35,41 +36,49 @@ typedef struct A15MPPrivState {
uint32_t num_cpu;
uint32_t num_irq;
MemoryRegion container;
-DeviceState *gic;
+
+GICState gic;
} A15MPPrivState;
static void a15mp_priv_set_irq(void *opaque, int irq, int level)
{
A15MPPrivState *s = (A15MPPrivState *)opaque;
-qemu_set_irq(qdev_get_gpio_in(s-gic, irq), level);
+
+qemu_set_irq(qdev_get_gpio_in(DEVICE(s-gic), irq), level);
}
static void a15mp_priv_initfn(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
A15MPPrivState *s = A15MPCORE_PRIV(obj);
+DeviceState *gicdev;
+const char *gictype = arm_gic;
+
+if (kvm_irqchip_in_kernel()) {
+gictype = kvm-arm-gic;
+}
memory_region_init(s-container, obj, a15mp-priv-container, 0x8000);
sysbus_init_mmio(sbd, s-container);
+
+object_initialize(s-gic, sizeof(s-gic), gictype);
+gicdev = DEVICE(s-gic);
+qdev_set_parent_bus(gicdev, sysbus_get_default());
+qdev_prop_set_uint32(gicdev, revision, 2);
}
static int a15mp_priv_init(SysBusDevice *dev)
{
A15MPPrivState *s = A15MPCORE_PRIV(dev);
+DeviceState *gicdev;
SysBusDevice *busdev;
-const char *gictype = arm_gic;
int i;
-if (kvm_irqchip_in_kernel()) {
-gictype = kvm-arm-gic;
-}
-
-s-gic = qdev_create(NULL, gictype);
-qdev_prop_set_uint32(s-gic, num-cpu, s-num_cpu);
-qdev_prop_set_uint32(s-gic, num-irq, s-num_irq);
-qdev_prop_set_uint32(s-gic, revision, 2);
-qdev_init_nofail(s-gic);
-busdev = SYS_BUS_DEVICE(s-gic);
+gicdev = DEVICE(s-gic);
+qdev_prop_set_uint32(gicdev, num-cpu, s-num_cpu);
+qdev_prop_set_uint32(gicdev, num-irq, s-num_irq);
+qdev_init_nofail(gicdev);
+busdev = SYS_BUS_DEVICE(s-gic);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(dev, busdev);
@@ -87,10 +96,10 @@ static int a15mp_priv_init(SysBusDevice *dev)
* since a real A15 always has TrustZone but QEMU doesn't.
*/
qdev_connect_gpio_out(cpudev, 0,
- qdev_get_gpio_in(s-gic, ppibase + 30));
+ qdev_get_gpio_in(gicdev, ppibase + 30));
/* virtual timer */
qdev_connect_gpio_out(cpudev, 1,
- qdev_get_gpio_in(s-gic, ppibase + 27));
+ qdev_get_gpio_in(gicdev, ppibase + 27));
}
/* Memory map (addresses are offsets from PERIPHBASE):
--
1.8.1.4
[Qemu-devel] [PATCH v4 01/24] a9mpcore: Split off instance_init
From: Andreas Färber andreas.faer...@web.de
Prepares for QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 3e675e3..acbdab5 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -34,6 +34,14 @@ static void a9mp_priv_set_irq(void *opaque, int irq, int
level)
qemu_set_irq(qdev_get_gpio_in(s-gic, irq), level);
}
+static void a9mp_priv_initfn(Object *obj)
+{
+A9MPPrivState *s = A9MPCORE_PRIV(obj);
+
+memory_region_init(s-container, obj, a9mp-priv-container, 0x2000);
+sysbus_init_mmio(SYS_BUS_DEVICE(obj), s-container);
+}
+
static int a9mp_priv_init(SysBusDevice *dev)
{
A9MPPrivState *s = A9MPCORE_PRIV(dev);
@@ -78,7 +86,6 @@ static int a9mp_priv_init(SysBusDevice *dev)
*
* We should implement the global timer but don't currently do so.
*/
-memory_region_init(s-container, OBJECT(s), a9mp-priv-container,
0x2000);
memory_region_add_subregion(s-container, 0,
sysbus_mmio_get_region(scubusdev, 0));
/* GIC CPU interface */
@@ -94,8 +101,6 @@ static int a9mp_priv_init(SysBusDevice *dev)
memory_region_add_subregion(s-container, 0x1000,
sysbus_mmio_get_region(gicbusdev, 0));
-sysbus_init_mmio(dev, s-container);
-
/* Wire up the interrupt from each watchdog and timer.
* For each core the timer is PPI 29 and the watchdog PPI 30.
*/
@@ -134,6 +139,7 @@ static const TypeInfo a9mp_priv_info = {
.name = TYPE_A9MPCORE_PRIV,
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(A9MPPrivState),
+.instance_init = a9mp_priv_initfn,
.class_init= a9mp_priv_class_init,
};
--
1.8.1.4
[Qemu-devel] [PATCH v4 10/24] a15mpcore: Split off instance_init
From: Andreas Färber andreas.faer...@web.de
Prepares for QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a15mpcore.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index 9abba67..af29c35 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -44,6 +44,15 @@ static void a15mp_priv_set_irq(void *opaque, int irq, int
level)
qemu_set_irq(qdev_get_gpio_in(s-gic, irq), level);
}
+static void a15mp_priv_initfn(Object *obj)
+{
+SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+A15MPPrivState *s = A15MPCORE_PRIV(obj);
+
+memory_region_init(s-container, obj, a15mp-priv-container, 0x8000);
+sysbus_init_mmio(sbd, s-container);
+}
+
static int a15mp_priv_init(SysBusDevice *dev)
{
A15MPPrivState *s = A15MPCORE_PRIV(dev);
@@ -92,14 +101,11 @@ static int a15mp_priv_init(SysBusDevice *dev)
* 0x5000-0x5fff -- GIC virtual interface control (not modelled)
* 0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
*/
-memory_region_init(s-container, OBJECT(s),
- a15mp-priv-container, 0x8000);
memory_region_add_subregion(s-container, 0x1000,
sysbus_mmio_get_region(busdev, 0));
memory_region_add_subregion(s-container, 0x2000,
sysbus_mmio_get_region(busdev, 1));
-sysbus_init_mmio(dev, s-container);
return 0;
}
@@ -128,6 +134,7 @@ static const TypeInfo a15mp_priv_info = {
.name = TYPE_A15MPCORE_PRIV,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(A15MPPrivState),
+.instance_init = a15mp_priv_initfn,
.class_init = a15mp_priv_class_init,
};
--
1.8.1.4
Re: [Qemu-devel] [PATCH] target-i386: set model=6 on qemu64 qemu32 CPU models
Am 11.09.2013 10:37, schrieb Igor Mammedov:
On Wed, 11 Sep 2013 10:25:58 +0200
Andreas Färber afaer...@suse.de wrote:
Am 11.09.2013 10:22, schrieb Igor Mammedov:
On Tue, 10 Sep 2013 17:48:59 -0300
Eduardo Habkost ehabk...@redhat.com wrote:
There's no Intel CPU with family=6,model=2, and Linux and Windows guests
disable SEP when seeing that combination due to Pentium Pro erratum #82.
In addition to just having SEP ignored by guests, Skype (and maybe other
applications) runs sysenter directly without passing through ntdll on
Windows, and crashes because Windows ignored the SEP CPUID bit.
So, having model 2 is a better default on qemu64 and qemu32 for two
reasons: making SEP really available for guests, and avoiding crashing
applications that work on bare metal.
model=3 would fix the problem, but it causes CPU enumeration problems
for Windows guests[1]. So this patch sets model=6, that matches Athlon
(PM core) on AMD and P2 with on-die L2 cache on Intel and it allows
Windows to use all CPUs as well as fixing sysenter.
[1] https://bugzilla.redhat.com/show_bug.cgi?id=508623
Cc: Andrea Arcangeli aarca...@redhat.com
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
---
include/hw/i386/pc.h | 8
target-i386/cpu.c| 4 ++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 7fb04d8..195e962 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -258,6 +258,14 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
.driver = TYPE_X86_CPU,\
.property = pmu,\
.value = on,\
+},{\
+.driver = qemu64- TYPE_X86_CPU,\
+.property = model,\
+.value= stringify(2),\
+},{\
+.driver = qemu32- TYPE_X86_CPU,\
+.property = model,\
+.value= stringify(3),\
}
#define PC_COMPAT_1_4 \
Shouldn't this hunk be in PC_COMPAT_1_6 rather than alongside PMU, which
I believe was for 1_5?
grr, you are right.
my reviewed-by stands, provided compats are moved to PC_COMPAT_1_6.
Fixed now that Stefan's net-next pull has been merged. Thanks, applied
to qom-cpu:
https://github.com/afaerber/qemu-cpu/commits/qom-cpu
Andreas
Andreas
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index c36345e..36cfbce 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -544,7 +544,7 @@ static x86_def_t builtin_x86_defs[] = {
.level = 4,
.vendor = CPUID_VENDOR_AMD,
.family = 6,
-.model = 2,
+.model = 6,
.stepping = 3,
.features[FEAT_1_EDX] =
PPRO_FEATURES |
@@ -647,7 +647,7 @@ static x86_def_t builtin_x86_defs[] = {
.level = 4,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
-.model = 3,
+.model = 6,
.stepping = 3,
.features[FEAT_1_EDX] =
PPRO_FEATURES,
Reviewed-By: Igor Mammedov imamm...@redhat.com
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] pc: add 1.7 machine types for piix,q35
Am 12.09.2013 08:24, schrieb Michael S. Tsirkin:
piix 1.7 is the default.
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/i386/pc_piix.c | 19 +--
hw/i386/pc_q35.c | 17 -
2 files changed, 33 insertions(+), 3 deletions(-)
Looks like you forget to rebase? Stefan's net-next tree was merged last
night, so there's already the two _v1_7 machines registered at least.
The pc_init_ function and the 1_6 - 1_7 #define might still be
applicable though.
Andreas
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 66551b4..0ade373 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -274,6 +274,11 @@ static void pc_compat_1_2(QEMUMachineInitArgs *args)
disable_kvm_pv_eoi();
}
+static void pc_init_pci_1_7(QEMUMachineInitArgs *args)
+{
+pc_init_pci(args);
+}
+
static void pc_init_pci_1_6(QEMUMachineInitArgs *args)
{
pc_compat_1_6(args);
@@ -344,14 +349,23 @@ static void pc_xen_hvm_init(QEMUMachineInitArgs *args)
.desc = Standard PC (i440FX + PIIX, 1996), \
.hot_add_cpu = pc_hot_add_cpu
-#define PC_I440FX_1_6_MACHINE_OPTIONS PC_I440FX_MACHINE_OPTIONS
+#define PC_I440FX_1_7_MACHINE_OPTIONS PC_I440FX_MACHINE_OPTIONS
+
+static QEMUMachine pc_i440fx_machine_v1_7 = {
+PC_I440FX_1_7_MACHINE_OPTIONS,
+.name = pc-i440fx-1.7,
+.alias = pc,
+.init = pc_init_pci_1_7,
+.is_default = 1,
+};
+
+#define PC_I440FX_1_6_MACHINE_OPTIONS PC_I440FX_1_7_MACHINE_OPTIONS
static QEMUMachine pc_i440fx_machine_v1_6 = {
PC_I440FX_1_6_MACHINE_OPTIONS,
.name = pc-i440fx-1.6,
.alias = pc,
.init = pc_init_pci_1_6,
-.is_default = 1,
};
static QEMUMachine pc_i440fx_machine_v1_5 = {
@@ -740,6 +754,7 @@ static QEMUMachine xenfv_machine = {
static void pc_machine_init(void)
{
+qemu_register_machine(pc_i440fx_machine_v1_7);
qemu_register_machine(pc_i440fx_machine_v1_6);
qemu_register_machine(pc_i440fx_machine_v1_5);
qemu_register_machine(pc_i440fx_machine_v1_4);
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 54c2b4c..0abd9b1 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -238,6 +238,11 @@ static void pc_compat_1_4(QEMUMachineInitArgs *args)
x86_cpu_compat_set_features(Westmere, FEAT_1_ECX, 0,
CPUID_EXT_PCLMULQDQ);
}
+static void pc_q35_init_1_7(QEMUMachineInitArgs *args)
+{
+pc_q35_init(args);
+}
+
static void pc_q35_init_1_6(QEMUMachineInitArgs *args)
{
pc_compat_1_6(args);
@@ -261,7 +266,16 @@ static void pc_q35_init_1_4(QEMUMachineInitArgs *args)
.desc = Standard PC (Q35 + ICH9, 2009), \
.hot_add_cpu = pc_hot_add_cpu
-#define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
+#define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
+
+static QEMUMachine pc_q35_machine_v1_7 = {
+PC_Q35_1_7_MACHINE_OPTIONS,
+.name = pc-q35-1.7,
+.alias = q35,
+.init = pc_q35_init_1_7,
+};
+
+#define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_1_7_MACHINE_OPTIONS
static QEMUMachine pc_q35_machine_v1_6 = {
PC_Q35_1_6_MACHINE_OPTIONS,
@@ -296,6 +310,7 @@ static QEMUMachine pc_q35_machine_v1_4 = {
static void pc_q35_machine_init(void)
{
+qemu_register_machine(pc_q35_machine_v1_7);
qemu_register_machine(pc_q35_machine_v1_6);
qemu_register_machine(pc_q35_machine_v1_5);
qemu_register_machine(pc_q35_machine_v1_4);
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 15/16] qdev-monitor: Clean up qdev_device_add() variable naming
Am 30.08.2013 19:19, schrieb Andreas Färber:
Am 26.08.2013 09:52, schrieb Wenchao Xia:
于 2013-8-24 8:00, Andreas Färber 写道:
Avoid confusion between object and object class.
between object class and device class?
No the issue is that by convention we usually use
Object *obj;
ObjectClass *oc; /* previously: klass or k */
rather than
ObjectClass *obj;
That makes the code more difficult to read.
Clarified the commit message and applied to qom-next:
https://github.com/afaerber/qemu-cpu/commits/qom-next
Andreas
This part of the series is not so important yet, so we can give it some
more review and thought.
Regards,
Andreas
Tidy DeviceClass variable while at it.
Signed-off-by: Andreas Färber afaer...@suse.de
---
qdev-monitor.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/qdev-monitor.c b/qdev-monitor.c
index 410cdcb..51bfec0 100644
--- a/qdev-monitor.c
+++ b/qdev-monitor.c
@@ -444,8 +444,8 @@ static BusState *qbus_find(const char *path)
DeviceState *qdev_device_add(QemuOpts *opts)
{
-ObjectClass *obj;
-DeviceClass *k;
+ObjectClass *oc;
+DeviceClass *dc;
const char *driver, *path, *id;
DeviceState *qdev;
BusState *bus = NULL;
@@ -457,22 +457,22 @@ DeviceState *qdev_device_add(QemuOpts *opts)
}
/* find driver */
-obj = object_class_by_name(driver);
-if (!obj) {
+oc = object_class_by_name(driver);
+if (!oc) {
const char *typename = find_typename_by_alias(driver);
if (typename) {
driver = typename;
-obj = object_class_by_name(driver);
+oc = object_class_by_name(driver);
}
}
-if (!obj) {
+if (!oc) {
qerror_report(QERR_INVALID_PARAMETER_VALUE, driver,
device type);
return NULL;
}
-k = DEVICE_CLASS(obj);
+dc = DEVICE_CLASS(oc);
/* find bus */
path = qemu_opt_get(opts, bus);
@@ -481,16 +481,16 @@ DeviceState *qdev_device_add(QemuOpts *opts)
if (!bus) {
return NULL;
}
-if (!object_dynamic_cast(OBJECT(bus), k-bus_type)) {
+if (!object_dynamic_cast(OBJECT(bus), dc-bus_type)) {
qerror_report(QERR_BAD_BUS_FOR_DEVICE,
driver, object_get_typename(OBJECT(bus)));
return NULL;
}
-} else if (k-bus_type != NULL) {
-bus = qbus_find_recursive(sysbus_get_default(), NULL,
k-bus_type);
+} else if (dc-bus_type != NULL) {
+bus = qbus_find_recursive(sysbus_get_default(), NULL,
dc-bus_type);
if (!bus) {
qerror_report(QERR_NO_BUS_FOR_DEVICE,
- k-bus_type, driver);
+ dc-bus_type, driver);
return NULL;
}
}
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] ui/Makefile.objs: delete unnecessary cocoa.o dependency
Am 12.09.2013 03:23, schrieb Fam Zheng: On Wed, 09/11 17:49, Peter Maydell wrote: Delete an unnecessary dependency for cocoa.o; we already have a general rule that tells Make that we can build a .o file from a .m source using an ObjC compiler, so this specific rule is unnecessary. Further, it is using the dubious construct $(SRC_PATH)/$(obj) to get at the source directory, which will break when $(obj) is redefined as part of the preparation for per-object library support. Signed-off-by: Peter Maydell peter.mayd...@linaro.org --- This needs to go in before Fam's patchset for modules can be applied, either via a cocoa maintainer queue or via -trivial or just as a first patch on the front of Fam's patches if they would otherwise be being held up by this. Sure, I'll apply to my tree and rebase if it's merged. If it works, fine with me: Reviewed-by: Andreas Färber andreas.faer...@web.de I don't think I have any other Cocoa patches queued - or did I miss a more acceptable version of the command-key workaround? Regards, Andreas Thanks, Fam ui/Makefile.objs | 2 -- 1 file changed, 2 deletions(-) diff --git a/ui/Makefile.objs b/ui/Makefile.objs index 6ddc0de..f33be47 100644 --- a/ui/Makefile.objs +++ b/ui/Makefile.objs @@ -17,6 +17,4 @@ common-obj-$(CONFIG_GTK) += gtk.o x_keymap.o $(obj)/sdl.o $(obj)/sdl_zoom.o: QEMU_CFLAGS += $(SDL_CFLAGS) -$(obj)/cocoa.o: $(SRC_PATH)/$(obj)/cocoa.m - $(obj)/gtk.o: QEMU_CFLAGS += $(GTK_CFLAGS) $(VTE_CFLAGS) -- 1.7.11.4
Re: [Qemu-devel] MSI-X doesn't work when running Windows as guest
Am 13.09.2013 14:31, schrieb Michael S. Tsirkin: On Fri, Sep 13, 2013 at 03:22:01PM +0300, Michael S. Tsirkin wrote: On Fri, Sep 13, 2013 at 01:14:43AM -0300, Eduardo Habkost wrote: On Fri, Sep 13, 2013 at 12:03:40AM +0300, Michael S. Tsirkin wrote: On Thu, Sep 12, 2013 at 04:45:01PM -0300, Eduardo Habkost wrote: On Thu, Sep 12, 2013 at 11:42:17AM +0300, Michael S. Tsirkin wrote: On Thu, Sep 12, 2013 at 11:23:46AM +0300, Gal Hammer wrote: Hi, I've notice that the virtio-serial Windows' driver doesn't use MSI-X vectors when running using upstream qemu or qemu-kvm-1.2.2-13.fc18.x86_64. The same VM works with MSI-X when using qemu-kvm-0.12.1.2-2.355.el6.x86_64. From what I saw, Windows is trying to enable MSI-X by writing a 2 bytes value to device's PCI-config address 66h. So when everything works well the flow goes like this: pci_default_write_config value: 8000 len: 2 pci_default_write_config value: 1 len: 2 msix_enabled 0 (67) pci_default_write_config value: e107 len: 2 pci_default_write_config value: 1 len: 2 msix_enabled 0 (67) pci_default_write_config value: 8001 len: 2 msix_enabled 1 (67) But on upstream it goes: pci_default_write_config addr: 66 value: 8000 size: 2 pci_default_write_config addr: 66 value: 1 size: 2 msix_enabled 0 (67) pci_default_write_config addr: 66 value: e307 size: 2 (NOTE: Value is diffrent!). pci_default_write_config addr: 66 value: 1 size: 2 msix_enabled 0 (67) (NOTE: Missing the write of 8001). My qemu's command line: --- snip --- /usr/bin/qemu-kvm -m 1G -smp 2 -enable-kvm -usb -device usb-tablet \ -device ide-drive,drive=drive-virtio0-0-0,id=virtio0-0-0,bootindex=1 \ -drive file=win7_32_viorng.qcow2,if=none,id=drive-virtio0-0-0,format=qcow2,werror=stop,rerror=stop,cache=none \ -monitor stdio \ -vga qxl -spice id=on,disable-ticketing,port=5903 \ -device virtio-serial-pci,id=virtio-serial0,vectors=2 \ -chardev spicevmc,id=spicechannel0,name=vdagent --- snip --- Thanks, Gal. So it's a known change from qemu-kvm to qemu. With qemu-kvm the default cpu was kvm64. With qemu the default cpu is qemu64 even if you use -enable-kvm. Not an issue for libvirt as that specifies -cpu, but will be an issue for command-line users. Maybe we should change the default for new machine types and when -enable-kvm is specified? What about simply making qemu64 as good as kvm64 (on newer machine-types)? This will likely mean extending tcg to emulate more CPU features. Do you want to spend cycles on this? Why? Features that are not supported by TCG are automatically removed on from CPUID on X86CPU initialization. What exactly is missing on qemu64 that causes the above problem? I remember windows checks that cpu is modern enough to enable msi-x. Dont' remember the exact details. It would be interesting to find out what exactly is necessary to make this work. Adding new feature bits to qemu64 should be harmless for TCG, but increasing family/model too much without adding new features may require a little more testing to check if guests don't get confused. That's why I'm saying switching to kvm64 is easier. Thinking back I think it's the CPU model that does it. Gal, could you please try adding -cpu qemu64,model=6? Or try git://github.com/afaerber/qemu-cpu.git qom-cpu branch, which has Eduardo's model=6 patch already. (Please keep me in the loop.) Andreas Also please try -cpu kvm64,model=2. -- Eduardo -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 21/47] hw/char/Kconfig: Add Kconfig file
Am 27.08.2013 00:40, schrieb Paolo Bonzini: Il 26/08/2013 19:15, Andreas Färber ha scritto: PCI devices are generally configurable, so you need to add prompts to them. IndustryPack is really misplaced in hw/char/ and I believe I posted patches to remedy that and let one actually find it in our source tree. There were no objections against hw/ipack/, alternatively it could go into hw/gpio/. (Currently my patch series is waiting to be respun due to changed QOM realize requirements from Anthony.) That having being said, IndustryPack does not depend on PCI, only the TPCI2000(?) PCI-IndustryPack bridge does. Both of them are under the same symbol right now. After all any of the two is basically unusable without the other, and plans for extension seem not to exist as even Linux has only that one bridge and one device. I have no objection to hw/ipack, but I have a question. Would you follow the SCSI/USB model (with devices under hw/ipack, also followed for IndustryPack in the Linux kernel) or the virtio model (where the device remains under hw/char)? Generally we've tried to follow Linux for hw/ structure unless maintainers preferred otherwise, so it would prefer the former. My quest is a) consistency and b) easily finding QOM base device classes for refactorings. PCI and USB were done before your big hw/ reorganization, and the biggest part of devices appears to follow the categorization by function (which is why I saw the overlap with Marcel's category markup). ipoctal232 looks correct in hw/char/ to me, so that it can benefit from any general char device refactorings. Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [RFC v5 1/5] hw/arm: add very initial support for Canon DIGIC SoC
Am 07.09.2013 09:04, schrieb Antony Pavlov: DIGIC is Canon Inc.'s name for a family of SoC for digital cameras and camcorders. There is no publicly available specification for DIGIC chips. All information about DIGIC chip internals is based on reverse engineering efforts made by CHDK (http://chdk.wikia.com) and Magic Lantern (http://www.magiclantern.fm) projects contributors. Signed-off-by: Antony Pavlov antonynpav...@gmail.com --- default-configs/arm-softmmu.mak | 1 + hw/arm/Makefile.objs| 1 + hw/arm/digic.c | 65 + include/hw/arm/digic.h | 35 ++ 4 files changed, 102 insertions(+) create mode 100644 hw/arm/digic.c create mode 100644 include/hw/arm/digic.h Perfect, Reviewed-by: Andreas Färber afaer...@suse.de Thanks for your patience, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v4 24/24] arm11mpcore: Split off RealView MPCore
Am 13.09.2013 17:33, schrieb Peter Maydell:
On 11 September 2013 15:37, Andreas Färber afaer...@suse.de wrote:
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/cpu/Makefile.objs | 1 +
hw/cpu/arm11mpcore.c | 121 -
hw/cpu/realview_mpcore.c | 139
+++
3 files changed, 140 insertions(+), 121 deletions(-)
create mode 100644 hw/cpu/realview_mpcore.c
diff --git a/hw/cpu/Makefile.objs b/hw/cpu/Makefile.objs
index df287c1..6381238 100644
--- a/hw/cpu/Makefile.objs
+++ b/hw/cpu/Makefile.objs
@@ -1,4 +1,5 @@
obj-$(CONFIG_ARM11MPCORE) += arm11mpcore.o
+obj-$(CONFIG_REALVIEW) += realview_mpcore.o
obj-$(CONFIG_A9MPCORE) += a9mpcore.o
obj-$(CONFIG_A15MPCORE) += a15mpcore.o
obj-$(CONFIG_ICC_BUS) += icc_bus.o
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
index 0ec27c7..717d3e4 100644
--- a/hw/cpu/arm11mpcore.c
+++ b/hw/cpu/arm11mpcore.c
@@ -134,126 +134,6 @@ static void mpcore_priv_initfn(Object *obj)
qdev_set_parent_bus(DEVICE(s-wdtimer), sysbus_get_default());
}
-#define TYPE_REALVIEW_MPCORE_RIRQ realview_mpcore
-#define REALVIEW_MPCORE_RIRQ(obj) \
-OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)
-
-/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
- controllers. The output of these, plus some of the raw input lines
- are fed into a single SMP-aware interrupt controller on the CPU. */
-typedef struct {
-SysBusDevice parent_obj;
-
-qemu_irq cpuic[32];
-qemu_irq rvic[4][64];
-uint32_t num_cpu;
-
-ARM11MPCorePriveState priv;
-RealViewGICState gic[4];
-} mpcore_rirq_state;
-
-/* Map baseboard IRQs onto CPU IRQ lines. */
-static const int mpcore_irq_map[32] = {
--1, -1, -1, -1, 1, 2, -1, -1,
--1, -1, 6, -1, 4, 5, -1, -1,
--1, 14, 15, 0, 7, 8, -1, -1,
--1, -1, -1, -1, 9, 3, -1, -1,
-};
-
-static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
-{
-mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
-int i;
-
-for (i = 0; i 4; i++) {
-qemu_set_irq(s-rvic[i][irq], level);
-}
-if (irq 32) {
-irq = mpcore_irq_map[irq];
-if (irq = 0) {
-qemu_set_irq(s-cpuic[irq], level);
-}
-}
-}
-
-static void realview_mpcore_realize(DeviceState *dev, Error **errp)
-{
-SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
-mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
-DeviceState *priv = DEVICE(s-priv);
-DeviceState *gic;
-SysBusDevice *gicbusdev;
-Error *err = NULL;
-int n;
-int i;
-
-qdev_prop_set_uint32(priv, num-cpu, s-num_cpu);
-object_property_set_bool(OBJECT(s-priv), true, realized, err);
-if (err != NULL) {
-error_propagate(errp, err);
-return;
-}
-sysbus_pass_irq(sbd, SYS_BUS_DEVICE(s-priv));
-for (i = 0; i 32; i++) {
-s-cpuic[i] = qdev_get_gpio_in(priv, i);
-}
-/* ??? IRQ routing is hardcoded to normal mode. */
-for (n = 0; n 4; n++) {
-object_property_set_bool(OBJECT(s-gic[n]), true, realized,
err);
-if (err != NULL) {
-error_propagate(errp, err);
-return;
-}
-gic = DEVICE(s-gic[n]);
-gicbusdev = SYS_BUS_DEVICE(s-gic[n]);
-sysbus_mmio_map(gicbusdev, 0, 0x1004 + n * 0x1);
-sysbus_connect_irq(gicbusdev, 0, s-cpuic[10 + n]);
-for (i = 0; i 64; i++) {
-s-rvic[n][i] = qdev_get_gpio_in(gic, i);
-}
-}
-qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
-}
-
-static void mpcore_rirq_init(Object *obj)
-{
-SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(obj);
-SysBusDevice *privbusdev;
-int i;
-
-object_initialize(s-priv, sizeof(s-priv), TYPE_ARM11MPCORE_PRIV);
-qdev_set_parent_bus(DEVICE(s-priv), sysbus_get_default());
-privbusdev = SYS_BUS_DEVICE(s-priv);
-sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
-
-for (i = 0; i 4; i++) {
-object_initialize(s-gic[i], sizeof(s-gic[i]), TYPE_REALVIEW_GIC);
-qdev_set_parent_bus(DEVICE(s-gic[i]), sysbus_get_default());
-}
-}
-
-static Property mpcore_rirq_properties[] = {
-DEFINE_PROP_UINT32(num-cpu, mpcore_rirq_state, num_cpu, 1),
-DEFINE_PROP_END_OF_LIST(),
-};
-
-static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
-{
-DeviceClass *dc = DEVICE_CLASS(klass);
-
-dc-realize = realview_mpcore_realize;
-dc-props = mpcore_rirq_properties;
-}
-
-static const TypeInfo mpcore_rirq_info = {
-.name = TYPE_REALVIEW_MPCORE_RIRQ,
-.parent= TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(mpcore_rirq_state),
-.instance_init = mpcore_rirq_init,
-.class_init= mpcore_rirq_class_init
Re: [Qemu-devel] [PATCH 0/8] [PATCH RFC v3] s390 cpu hotplug
Am 13.09.2013 17:01, schrieb Jason J. Herne: On 09/05/2013 10:06 AM, Andreas Färber wrote: Am 05.09.2013 15:10, schrieb Alexander Graf: On 05.09.2013, at 15:05, Andreas Färber wrote: Am 05.09.2013 14:54, schrieb Alexander Graf: Very simple and clean patch set. I don't think it deserves the RFC tag. Negative, see my review. If you want to fix up and queue patches 1-2 that's fine with me, but the others need a respin. No major blocker though, just some more footwork mostly related to QOM and Jason's shifted focus on cpu-add rather than device_add. Yeah, that's what I'm referring to. I've seen a lot worse patch sets at v8 than this RFC :). I don't think we should apply it as is, and I'm very happy to see your review and comment on the modeling bits :). But I try to never apply or cherry pick RFC patches - and this set looks like he sent it with the intent of getting it merged. Agreed, we can continue with PATCH v4. I was more upset about the very simple and clean bit after I commented on a number of unclean things to improve - mostly about doing things in different places. If you could find some time to review my two model string patches then I could supply Jason with a branch or even a pull to base on: http://patchwork.ozlabs.org/patch/272511/ http://patchwork.ozlabs.org/patch/272509/ I would also volunteer to provide a base patch for the link issue if there is agreement. Apart from the QOM API question this depends on the contradictory modelling of whether we allow CPU addresses 0..max_cpus as seen in this series or 0..somemax with = max_cpus non-NULL as discussed on #zkvm. According to http://wiki.qemu.org/Features/CPUHotplug: adding CPUs should be done in successive order from lower to higher IDs in [0..max-cpus) range. It's possible to add arbitrary CPUs in random order, however that would cause migration to fail on its target side. Considering that, in a virtual environment, it rarely (if ever) makes sense to define out of order cpu ids maybe we should keep the patch as is and only allow consecutive cpu ids to be used. Your previous series tried to make -device work in place of -smp. This series now only seems to focus on cpu-add, including you referencing its current limitations above. As I tried to explain, x86 needed cpu-add because unlike s390x its CPU is not yet a fully initialize'able QOM object and thus can't use device_add yet (and long-term we want to use containers instead of today's *-x86_64-cpu). So I would very much prefer to see s390x continuing to use -smp but using device_add for CPU hot-add and in a way where we don't have to change semantics and ABI again when we implement hot-unplug. I am fine with you implementing a cpu-add wrapper, but on top of a working implementation please rather than limiting your implementation by it upfront. By extension, hot-unplug would require that the highest id be unplugged. This is probably not acceptable in any type of mixed cpu environment because the greatest id may not be the cpu type you want to remove. I'm not sure if S390 will implement mixed cpu types. (childs390-cpu properties would allow to model the latter sparse address space very well, but an object can only have one parent in the hot-add case. We could of course add cpu[n] links390-cpu properties as CPUs get added, but that doesn't strike me as very clean. My underlying thought is to offload the error handling to QOM so that we don't start hardcoding s/smp_cpus/max_cpus/g (or some max_cpu_address) all around ipi_states.) I'm not sure I understand. What is meant by: an object can only have one parent in the hot-add case. What is the difference between childs390-cpu and cpu[n] links390-cpu? And why do you feel the link case would be unclean? child properties determine the canonical path of an object. Each object only has one canonical path. When using link properties, the linked-to objects still need a canonical path, which becomes the string value of the property on QMP level (pointer on C level). device_add assigns canonical paths. Realizing a device creates a canonical path in /machine/unassigned as fallback, but that won't work long-term as the composition tree will be our source to find devices to realize, so either the machine code or the S390CPU code should take care of assuring CPUs have canonical paths before manually realizing them. Btw an unanswered question: ipi_states is just pointers to CPUs currently, no further state. So what's ipi in the name? Will that array need to carry state beyond S390CPU someday? Quoting Jens Freimann: The ipi_states array holds all our S390CPU states. The position of a cpu within this array equals its cpu address. See section CPU address identification in the Principles of Operation. This cpu address is used for cpu signalling (inter-processor interrupts-ipi) via the sigp instruction. The cpu address does not contain information about which book this cpu
Re: [Qemu-devel] [PATCH] qom: helper macro for adding read-only properties
Am 15.09.2013 19:23, schrieb Michael S. Tsirkin:
Add a helper macro for adding read-only properties, that works in the
common case where the value is a constant.
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
I'm using this patch in my acpi work - any objections
to applying it on my tree?
Actually yes: Apart from the clang issues raised and the disturbing
upper-casing of arguments, this is hardcoding int type and NULL errp,
so I don't think it deserves to live in object.h as is. I do agree that
we could use more helper functions to deal with dynamic properties.
So what about taking bool/string property helpers as example and putting
intX_t getters into object.c, using a passed-through opaque argument to
obtain the value? We could then have real object_property_add_int32()
etc. functions using the appropriate type name, with field/value pointer
and Error** arguments. A pointer can be assumed to hold up to uint32_t
values or, to keep the API more general, use a local static const
variable for non-field values.
It does touch on the issue I brought up on a KVM call a couple weeks ago
of how dynamic and static properties are supposed to relate. I
personally welcome making dynamic properties more easy to deal with; an
alternative might be to extend qdev-properties.c with
DEFINE_PROP_READONLY_UINT32() etc. CC'ing Igor, who has dealt with
dynamic-vs.-static properties for X86CPU.
Regards,
Andreas
include/qom/object.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/include/qom/object.h b/include/qom/object.h
index 1a7b71a..4787de6 100644
--- a/include/qom/object.h
+++ b/include/qom/object.h
@@ -17,6 +17,7 @@
#include glib.h
#include stdint.h
#include stdbool.h
+#include qemu/typedefs.h
#include qemu/queue.h
struct Visitor;
@@ -792,6 +793,26 @@ void object_property_add(Object *obj, const char *name,
const char *type,
ObjectPropertyRelease *release,
void *opaque, struct Error **errp);
+/* Add a property that is an integer constant. */
+#define OBJECT_ADD_PROP_CONST(obj, name, value) \
+do {\
+void OBJECT_ADD_PROP_GET(Object *OBJECT_ADD_PROP_OBJ, \
+ struct Visitor *OBJECT_ADD_PROP_VISITOR, \
+ void *OBJECT_ADD_PROP_OPAQUE, \
+ const char *OBJECT_ADD_PROP_NAME, \
+ struct Error **OBJECT_ADD_PROP_VALUE_ERR) \
+{ \
+int64_t OBJECT_ADD_PROP_VALUE = value; \
+\
+visit_type_int64(OBJECT_ADD_PROP_VISITOR, \
+ OBJECT_ADD_PROP_VALUE,\
+ OBJECT_ADD_PROP_NAME, \
+ OBJECT_ADD_PROP_VALUE_ERR);\
+} \
+object_property_add(obj, name, int, OBJECT_ADD_PROP_GET, \
+NULL, NULL, NULL, NULL);\
+} while (0)
+
void object_property_del(Object *obj, const char *name, struct Error **errp);
/**
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [RFC 4/4] disas: implement host disassembly output for aarch64
Am 11.09.2013 15:08, schrieb Claudio Fontana:
use C++ libvixl to implement output, for now only enabled for the host output
disasm, since we don't have the aarch64 target yet.
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
---
configure | 6 +
disas.c | 2 ++
disas/Makefile.objs | 7 ++
disas/aarch64-cxx.cc| 53
+
disas/aarch64.c | 45 ++
disas/libvixl/Makefile.objs | 6 +
include/disas/bfd.h | 1 +
7 files changed, 120 insertions(+)
create mode 100644 disas/aarch64-cxx.cc
create mode 100644 disas/aarch64.c
create mode 100644 disas/libvixl/Makefile.objs
diff --git a/configure b/configure
index 6b73d99..1a2648a 100755
--- a/configure
+++ b/configure
@@ -4443,6 +4443,12 @@ ldflags=
for i in $ARCH $TARGET_BASE_ARCH ; do
case $i in
+ aarch64)
+if test x${cxx} != x; then
+ echo CONFIG_AARCH64_DIS=y $config_target_mak
+ echo CONFIG_AARCH64_DIS=y config-all-disas.mak
+fi
+ ;;
alpha)
echo CONFIG_ALPHA_DIS=y $config_target_mak
echo CONFIG_ALPHA_DIS=y config-all-disas.mak
diff --git a/disas.c b/disas.c
index 0203ef2..cc20c4a 100644
--- a/disas.c
+++ b/disas.c
@@ -356,6 +356,8 @@ void disas(FILE *out, void *code, unsigned long size)
#elif defined(_ARCH_PPC)
s.info.disassembler_options = (char *)any;
print_insn = print_insn_ppc;
+#elif defined(__aarch64__)
+print_insn = print_insn_aarch64;
#elif defined(__alpha__)
print_insn = print_insn_alpha;
#elif defined(__sparc__)
diff --git a/disas/Makefile.objs b/disas/Makefile.objs
index 3b1e77a..f468c22 100644
--- a/disas/Makefile.objs
+++ b/disas/Makefile.objs
@@ -1,3 +1,10 @@
+ifeq ($(CONFIG_AARCH64_DIS),y)
+libvixldir = $(SRC_PATH)/disas/libvixl/src
+QEMU_CFLAGS += -I$(libvixldir) -Wno-undef
+common-obj-$(CONFIG_AARCH64_DIS) += libvixl/
+common-obj-$(CONFIG_AARCH64_DIS) += aarch64.o aarch64-cxx.o
+endif
+
common-obj-$(CONFIG_ALPHA_DIS) += alpha.o
common-obj-$(CONFIG_ARM_DIS) += arm.o
common-obj-$(CONFIG_CRIS_DIS) += cris.o
diff --git a/disas/aarch64-cxx.cc b/disas/aarch64-cxx.cc
new file mode 100644
index 000..524f5ae
--- /dev/null
+++ b/disas/aarch64-cxx.cc
@@ -0,0 +1,53 @@
+/*
+ * Aarch64 disassembly output wrapper to libvixl - C++ part
+ * Copyright (c) 2013 Linaro Limited
+ * Written by Claudio Fontana
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see http://www.gnu.org/licenses/.
+ */
+
+#include a64/simulator-a64.h
+#include a64/macro-assembler-a64.h
+
+extern C {
+int vixl_is_initialized(int);
+int vixl_init(FILE *f);
+int vixl_decode_insn(uint8_t *bytes);
+}
+
+using namespace vixl;
+
+static Decoder *vixl_decoder = NULL;
+static Disassembler *vixl_disasm = NULL;
+
+int vixl_is_initialized(int unused)
+{
+return vixl_decoder != NULL;
+}
+
+/* Disassemble Aarch64 bytecode - wrappers */
+int vixl_init(FILE *f) {
+vixl_decoder = new Decoder();
+vixl_disasm = new PrintDisassembler(f);
+vixl_decoder-AppendVisitor(vixl_disasm);
+return 1;
+}
+
+int vixl_decode_insn(uint8_t *bytes)
+{
+Instr instr;
+instr = bytes[0] | bytes[1] 8 | bytes[2] 16 | bytes[3] 24;
+vixl_decoder-Decode(reinterpret_castInstruction*(instr));
+return 1;
+}
diff --git a/disas/aarch64.c b/disas/aarch64.c
new file mode 100644
index 000..7e44837
--- /dev/null
+++ b/disas/aarch64.c
@@ -0,0 +1,45 @@
+/*
+ * Aarch64 disassembly output wrapper to libvixl - C part
+ * Copyright (c) 2013 Linaro Limited
+ * Written by Claudio Fontana
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see http://www.gnu.org/licenses/.
+
Re: [Qemu-devel] [RFC qom-cpu v3 00/10] i386: add cpu hot remove support
Hi, Am 16.09.2013 04:40, schrieb Chen Fan: Via implementing ACPI standard methods _EJ0 in bios, after Guest OS hot remove one vCPU, it is able to send a signal to QEMU, then QEMU could notify the assigned vCPU of exiting. meanwhile, and intruduce the QOM command 'cpu-del' to remove vCPU from QEMU itself. this work is based on Andreas Färber's qom-cpu branch tree. git://github.com/afaerber/qemu-cpu.git Patch 04/10 is not yet 100% like I think it needs to be wrt unrealize, but I would like to start cherry-picking APIC preparations from this series. Since this is still an RFC, permission to do so? Regards, Andreas this series patches must be used with seabios patch and KVM patch together. for KVM patches: http://comments.gmane.org/gmane.comp.emulators.kvm.devel/114347 for seabios patches: http://comments.gmane.org/gmane.comp.emulators.qemu/230460 Chen Fan (10): x86: move apic_state field from CPUX86State to X86CPU apic: remove redundant variable 'apic_no' from apic_init_common() apic: remove local_apics array and using CPU_FOREACH instead x86: add x86_cpu_unrealizefn() for cpu apic remove qmp: add 'cpu-del' command support qom cpu: rename variable 'cpu_added_notifier' to 'cpu_hotplug_notifier' qom cpu: add UNPLUG cpu notifier support i386: implement pc interface pc_hot_del_cpu() piix4: implement function cpu_status_write() for vcpu ejection cpus: reclaim allocated vCPU objects cpu-exec.c | 2 +- cpus.c | 51 -- hw/acpi/piix4.c | 66 +++-- hw/i386/kvm/apic.c | 8 hw/i386/kvmvapic.c | 8 ++-- hw/i386/pc.c| 51 +- hw/i386/pc_piix.c | 1 + hw/intc/apic.c | 81 - hw/intc/apic_common.c | 6 +-- include/hw/boards.h | 2 + include/hw/i386/apic_internal.h | 2 - include/hw/i386/pc.h| 1 + include/qom/cpu.h | 20 ++ include/sysemu/kvm.h| 1 + include/sysemu/sysemu.h | 2 +- kvm-all.c | 25 + qapi-schema.json| 12 ++ qmp-commands.hx | 23 qmp.c | 9 + qom/cpu.c | 26 ++--- target-i386/cpu-qom.h | 5 +++ target-i386/cpu.c | 57 +++-- target-i386/cpu.h | 4 -- target-i386/helper.c| 9 ++--- target-i386/kvm.c | 23 +--- target-i386/misc_helper.c | 8 ++-- 26 files changed, 380 insertions(+), 123 deletions(-) -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] qom: helper macro for adding read-only properties
Am 16.09.2013 14:33, schrieb Michael S. Tsirkin: On Mon, Sep 16, 2013 at 08:32:13AM +0200, Andreas Färber wrote: Am 15.09.2013 19:23, schrieb Michael S. Tsirkin: Add a helper macro for adding read-only properties, that works in the common case where the value is a constant. Signed-off-by: Michael S. Tsirkin m...@redhat.com --- I'm using this patch in my acpi work - any objections to applying it on my tree? Actually yes: Apart from the clang issues raised and the disturbing upper-casing of arguments, this is hardcoding int type and NULL errp, so I don't think it deserves to live in object.h as is. I do agree that we could use more helper functions to deal with dynamic properties. So what about taking bool/string property helpers as example and putting intX_t getters into object.c, using a passed-through opaque argument to obtain the value? We could then have real object_property_add_int32() etc. functions using the appropriate type name, with field/value pointer and Error** arguments. A pointer can be assumed to hold up to uint32_t values or, to keep the API more general, use a local static const variable for non-field values. This reminds me. [mst@robin qemu]$ git grep object_property_set_bool backends/rng.c:object_property_set_bool(OBJECT(s), true, opened, errp); backends/tpm.c:object_property_set_bool(OBJECT(s), true, opened, errp); These look like two distinct properties used once each. [...] hw/core/qdev.c:object_property_set_bool(OBJECT(dev), true, realized, local_err); [...] hw/core/qdev.c:object_property_set_bool(obj, false, realized, NULL); hw/i386/pc.c:object_property_set_bool(OBJECT(cpu), true, realized, local_err); hw/pci-host/prep.c:object_property_set_bool(OBJECT(s-pci_dev), true, realized, errp); hw/pci-host/versatile.c:object_property_set_bool(OBJECT(s-pci_dev), true, realized, errp) hw/scsi/scsi-bus.c:object_property_set_bool(OBJECT(dev), true, realized, err); [...] target-alpha/cpu.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); target-arm/helper.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); target-cris/cpu.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); target-i386/cpu.c:object_property_set_bool(OBJECT(cpu), true, pmu, err); target-i386/cpu.c:object_property_set_bool(OBJECT(cpu), true, realized, error); target-lm32/helper.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); target-m68k/helper.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); target-microblaze/translate.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); target-mips/translate.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); target-moxie/cpu.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); target-openrisc/cpu.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); target-ppc/translate_init.c:object_property_set_bool(OBJECT(cpu), true, realized, err); target-s390x/helper.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); target-sh4/cpu.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); target-sparc/cpu.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); target-unicore32/helper.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); target-xtensa/helper.c:object_property_set_bool(OBJECT(cpu), true, realized, NULL); Leaving the bulk for realized. Shouldn't we have a constant for the realized string? That's a two-sided sword: We actually shouldn't be setting realized = true manually but once on machine init - in that case we wouldn't strictly need a constant. I pushed to get that central infrastructure in place to spare me/us the repetitive realized = true setting, but Paolo shot it down, asking for a full-fledged solver to make ordering guarantees. If there's a typo somewhere it will all fail at runtime in a hard to debug way, won't it? It would. However, this is typically executed once on startup, so with proper error handling we should notice this immediately. My qom-test (that Anthony didn't take for 1.6 and I still need to respin) served to test them, with focus on SysBusDevices. You are cordially invited to add trivial qtests covering instantiation of PCI/virtio devices you care about. :) Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 7/8] [PATCH RFC v3] s390-qemu: cpu hotplug - Implement hot_add_cpu hook
Am 13.09.2013 17:29, schrieb Jason J. Herne:
On 09/05/2013 08:38 AM, Andreas Färber wrote:
Am 01.08.2013 16:12, schrieb Jason J. Herne:
From: Jason J. Herne jjhe...@us.ibm.com
Implement hot_add_cpu for S390 to allow hot plugging of cpus.
Signed-off-by: Jason J. Herne jjhe...@us.ibm.com
---
hw/s390x/s390-virtio-ccw.c |3 +++
target-s390x/cpu.c | 32
target-s390x/cpu.h |2 ++
3 files changed, 37 insertions(+)
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index b469960..30b6a48 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -117,6 +117,9 @@ static QEMUMachine ccw_machine = {
.alias = s390-ccw,
.desc = VirtIO-ccw based S390 machine,
.init = ccw_init,
+#if !defined(CONFIG_USER_ONLY)
+.hot_add_cpu = ccw_hot_add_cpu,
+#endif
I doubt this #ifdeffery is necessary here?
This was needed because ccw_hot_add_cpu calls s390_cpu_addr2state which
is wrapped in the very same ifdef.
This whole file should never get compiled for CONFIG_USER_ONLY.
However, the offending line is this:
model_str = s390_cpu_addr2state(0)-env.cpu_model_str;
Since we're doing away with that line anyway I can probably remove that
ifdef. However, does it make sense to have a cpu-add command for the
linux-user target?
Also, do you know when your patch to remove the model string will hit
the master branch?
I've pushed it to qom-cpu-next branch for now, suggest to rebase on
that. It all depends on when I get to review all the pending patches and
respin some interfering ones and then get someone to pull, which is
outside of my control.
Cheers,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] in_asm substitute for accel=kvm:tcg
Hi, Am 17.09.2013 13:37, schrieb Andriy Gapon: It seems that when qemu is run with accel=kvm:tcg then -d in_asm does not produce anything. At least, with the qemu and kvm that I have access to. Are you saying that with accel=kvm:tcg when falling back to TCG, -d in_asm does not work? For accel=kvm it's expected not to produce any output since QEMU does not process any Translation Blocks then. Is there any way to obtain equivalent logging in such a configuration? A note: a host and a guest are both amd64 (x86_64). Under Linux, trace options for the kvm kernel module can be enabled via the file system. Regards, Andreas Some background. I am trying to debug a problem with booting a FreeBSD VM. If acceleration is not used then the VM boots just fine. But with acceleration the boot process hangs somewhere in FreeBSD boot loader, judging from what I see on a screen. I suspect that there could be a problem with jumping from real to protected mode or some such exotic environment. To narrow down the possibilities I would like to examine execution trace and see where execution goes into the weeds. Thank you very much in advance. -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] qdev: fix crash when device_add is called with abstract driver
Am 17.09.2013 15:32, schrieb Igor Mammedov:
user is able to crash running QEMU when following monitor
command is called:
device_add intel-hda-generic
crash is caused by assertion in object_initialize_with_type()
when type is abstract.
Checking if type is abstract before instance is created in
qdev_device_add() allows to prevent crash on incorrect user input.
Signed-off-by: Igor Mammedov imamm...@redhat.com
---
qdev-monitor.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
Thanks, rebased and applied to qom-next:
https://github.com/afaerber/qemu-cpu/commits/qom-next
One question though:
diff --git a/qdev-monitor.c b/qdev-monitor.c
index 410cdcb..bb2e1b6 100644
--- a/qdev-monitor.c
+++ b/qdev-monitor.c
@@ -472,6 +472,12 @@ DeviceState *qdev_device_add(QemuOpts *opts)
return NULL;
}
+if (object_class_is_abstract(obj)) {
+qerror_report(QERR_INVALID_PARAMETER_VALUE, driver,
+ non-abstract device type);
Is qerror_report() still okay despite the QERR_* considered obsolete for
error_set()? I.e. because this is only printing the text and not passing
on error classes? Or where do we draw the line? (CC Luiz)
Thanks,
Andreas
+return NULL;
+}
+
k = DEVICE_CLASS(obj);
/* find bus */
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v2 1/1] integrator: fix Linux boot failure by emulating dbg
Am 18.09.2013 16:31, schrieb alex.ben...@linaro.org:
From: Alex Bennée a...@bennee.com
Commit 9b8c69243 broke the ability to boot the kernel as the value
returned by unassigned_mem_read returned non-zero and left the kernel
looping forever waiting for it to change (see integrator_led_set in
the kernel code).
Relying on a varying implementation detail is incorrect anyway so this
introduces a memory region to emulate the debug/led region on the
integrator board. It is currently a basic stub as I have no idea what the
behaviour of this region should be so for now it simply returns 0's as
the old unassigned_mem_read did.
Signed-off-by: Alex Bennée a...@bennee.com
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/integratorcp.c | 1 +
hw/misc/Makefile.objs | 1 +
hw/misc/arm_intdbg.c| 90
+
4 files changed, 93 insertions(+)
create mode 100644 hw/misc/arm_intdbg.c
Looks okay in general, some minor nits below:
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index ac0815d..a5718d1 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -80,3 +80,4 @@ CONFIG_VERSATILE_PCI=y
CONFIG_VERSATILE_I2C=y
CONFIG_SDHCI=y
+CONFIG_INTEGRATOR_DBG=y
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index 2ef93ed..46dc615 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -508,6 +508,7 @@ static void integratorcp_init(QEMUMachineInitArgs *args)
icp_control_init(0xcb00);
sysbus_create_simple(pl050_keyboard, 0x1800, pic[3]);
sysbus_create_simple(pl050_mouse, 0x1900, pic[4]);
+sysbus_create_simple(integrator_dbg, 0x1a00, 0);
sysbus_create_varargs(pl181, 0x1c00, pic[23], pic[24], NULL);
if (nd_table[0].used)
smc91c111_init(nd_table[0], 0xc800, pic[27]);
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 2578e29..be284f3 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -10,6 +10,7 @@ obj-$(CONFIG_VMPORT) += vmport.o
# ARM devices
common-obj-$(CONFIG_PL310) += arm_l2x0.o
+common-obj-$(CONFIG_INTEGRATOR_DBG) += arm_intdbg.o
# PKUnity SoC devices
common-obj-$(CONFIG_PUV3) += puv3_pm.o
diff --git a/hw/misc/arm_intdbg.c b/hw/misc/arm_intdbg.c
new file mode 100644
index 000..b505d09
--- /dev/null
+++ b/hw/misc/arm_intdbg.c
@@ -0,0 +1,90 @@
+/*
+ * LED, Switch and Debug control registers for ARM Integrator Boards
+ *
+ * This currently is a stub for this functionality written with
+ * reference to what the Linux kernel looks at. Previously we relied
+ * on the behaviour of unassigned_mem_read() in the core.
+ *
+ * The real h/w is described at:
+ *
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0159b/Babbfijf.html
+ *
+ * Written by Alex Bennée
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include hw/hw.h
+#include hw/sysbus.h
+#include exec/address-spaces.h
+
+#define TYPE_ARM_INTDBG integrator_dbg
If you move this constant into an include/hw/misc/arm_integratorcp_dbg.h
then you can reuse it in hw/arm/integratorcp.c above. (Optional.)
+#define ARM_INTDBG(obj) \
+OBJECT_CHECK(ARMIntDbgState, (obj), TYPE_ARM_INTDBG)
+
+typedef struct {
+SysBusDevice parent_obj;
Please leave an empty line here to visually separate the parent field.
+MemoryRegion iomem;
+
+uint32_t alpha;
+uint32_t leds;
+uint32_t switches;
+} ARMIntDbgState;
+
+static uint64_t dbg_control_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+switch (offset 2) {
+case 0: /* ALPHA */
+case 1: /* LEDS */
+case 2: /* SWITCHES */
+qemu_log_mask(LOG_UNIMP, dbg_control_read: returning zero from
%x:%d\n, (int)offset, size);
HWADDR_PRIx, %u
Also suggest %s and __func__, cf. further below.
+return 0;
+default:
+qemu_log_mask(LOG_GUEST_ERROR, dbg_control_read: Bad offset %x\n,
(int)offset);
HWADDR_PRIx
+return 0;
+}
+}
+
+static void dbg_control_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+switch (offset 2) {
+case 1: /* ALPHA */
+case 2: /* LEDS */
+case 3: /* SWITCHES */
+/* Nothing interesting implemented yet. */
+qemu_log_mask(LOG_UNIMP, dbg_control_write: ignoring write of %lx
to %x:%d\n, value, (int)offset, size);
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR, dbg_control_write: write of %lx to
bad offset %x\n, value, (int)offset);
+}
+}
+
+static const MemoryRegionOps dbg_control_ops = {
+.read = dbg_control_read,
+.write = dbg_control_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void
Re: [Qemu-devel] [PATCH v4 00/24] arm: ARM11MPCore+A9MPCore+A15MPCore QOM'ification
Am 13.09.2013 17:38, schrieb Peter Maydell: On 11 September 2013 15:37, Andreas Färber afaer...@suse.de wrote: From: Andreas Färber andreas.faer...@web.de Hello Peter, This series fully QOM'ifies A9MPCore so that it can be embedded for Tegra2. It goes on to do the same for A15MPCore, which had previously been taken as template for Cortex-A57 by John Rigby, and since v3 ARM11MPCore. Separate headers are introduced to only expose device state to whom asks for it. Thanks; this version looks good to me. I had a few remarks on the realview stuff at the end but none that I think require delaying this patchset further. Reviewed-by: Peter Maydell peter.mayd...@linaro.org I'm assuming you'll take this through your qom tree... Thanks, I've queued them on qom-next now and will look into tweaking the realview file header, possibly adding a TODO so that it doesn't get forgotten. https://github.com/afaerber/qemu-cpu/commits/qom-next Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 2/2] qemu-kvm: paravirt: add feature kvm_pv_unhalt
Am 18.09.2013 16:41, schrieb Andrew Jones:
I don't know yet if want this feature on by default, so for now I'm
just adding support for -cpu ...,+kvm_pv_unhalt.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
target-i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 42c5de034ecc8..89491e7b1fba1 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -123,7 +123,7 @@ static const char *ext4_feature_name[] = {
static const char *kvm_feature_name[] = {
kvmclock, kvm_nopiodelay, kvm_mmu, kvmclock,
-kvm_asyncpf, kvm_steal_time, kvm_pv_eoi, NULL,
+kvm_asyncpf, kvm_steal_time, kvm_pv_eoi, kvm_pv_unhalt,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
Since there's linux-headers updates involved I can't take it through my
qom-cpu queue. If Paolo can tweak the subject to target-i386: Add
paravirt CPU feature kvm_pv_unhalt or so I'd be happy for this to go
through his uq/master queue. (qemu-kvm no longer exists, all QEMU
patches are about QEMU anyway and there's no discrete paravirt
subsystem or precedent in qemu.git history.)
Patch itself is
Reviewed-by: Andreas Färber afaer...@suse.de
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] QEMU SD card emulation problem
Hi, Am 17.09.2013 14:13, schrieb Taimoor Mirza: I have been trying to use SD card emulation of QEMU by providing host directory to QEMU to treat it as SD card. For this I am using option -sd fat:16:rw:/home/taimoor/temp/sdcard. This works fine for me and I can see list of files in guest system. But when I delete some file from guest system sdcard directory and then try adding new file there, I get following error: Could not open /home/taimoor/temp/sdcard... (Is a directory, 21) Error handling commits (-3) The short answer is: Don't delete or change files passed to a guest this way. When you plug a physical SD card to a reader, then no one else apart from the OS will modify the card's contents. Similarly QEMU emulates a disk image based on the directory contents. You will find similar discussions for vvfat with USB in the qemu-devel archives. Feel free to post patches handling this error situation more gracefully, but if you do want to change files on the host then use NFS or some other mechanism. Regards, Andreas I have debugged QEMU and have found that error is coming from open function call in qemu_open function that is called from commit_one_file call from ACTION_WRITEOUT case in handle_commits. Backtrace is: (gdb) bt #0 qemu_open (name=0x80c7a8c0 /home/taimoor/temp/sdcard, flags=66) at util/osdep.c:202 #1 0x80091dc1 in commit_one_file (s=0x80c7e3e0, dir_index=4, offset=0) at block/vvfat.c:2325 #2 0x800927b9 in handle_commits (s=0x80c7e3e0) at block/vvfat.c:2588 #3 0x80092cb1 in do_commit (s=0x80c7e3e0) at block/vvfat.c:2736 #4 0x80092df2 in try_commit (s=0x80c7e3e0) at block/vvfat.c:2766 #5 0x8009335a in vvfat_write (bs=0x80c7d258, sector_num=64, buf=0x80e1e000 \370\377\377\377\377\377\004, nb_sectors=1) at block/vvfat.c:2860 #6 0x800933f1 in vvfat_co_write (bs=0x80c7d258, sector_num=64, buf=0x80e1e000 \370\377\377\377\377\377\004, nb_sectors=1) at block/vvfat.c:2872 #7 0x80052898 in bdrv_aio_rw_vector (bs=0x80c7d258, sector_num=64, qiov=0xb50869b4, nb_sectors=1, cb=0x800530fe bdrv_co_io_em_complete, opaque=0xb5ceccf0, is_write=1) at block.c:4065 #8 0x80052a01 in bdrv_aio_writev_em (bs=0x80c7d258, sector_num=64, qiov=0xb50869b4, nb_sectors=1, cb=0x800530fe bdrv_co_io_em_complete, opaque=0xb5ceccf0) at block.c:4086 #9 0x800531fd in bdrv_co_io_em (bs=0x80c7d258, sector_num=64, nb_sectors=1, iov=0xb50869b4, is_write=true) at block.c:4283 #10 0x8005336d in bdrv_co_writev_em (bs=0x80c7d258, sector_num=64, nb_sectors=1, iov=0xb50869b4) at block.c:4310 #11 0x8004e772 in bdrv_co_do_writev (bs=0x80c7d258, sector_num=64, nb_sectors=1, qiov=0xb50869b4, flags=0) at block.c:2625 #12 0x8004e8b9 in bdrv_co_writev (bs=0x80c7d258, sector_num=64, nb_sectors=1, qiov=0xb50869b4) at block.c:2650 #13 0x8007a59d in raw_co_writev (bs=0x80c7b8c0, sector_num=64, nb_sectors=1, qiov=0xb50869b4) at block/raw.c:31 #14 0x8004e772 in bdrv_co_do_writev (bs=0x80c7b8c0, sector_num=64, nb_sectors=1, qiov=0xb50869b4, flags=0) at block.c:2625 #15 0x8004d40a in bdrv_rw_co_entry (opaque=0xb508692c) at block.c:2175 #16 0x8009978c in coroutine_trampoline (i0=-2134407824, i1=0) at coroutine-ucontext.c:118 #17 0x0059482b in makecontext () at ../sysdeps/unix/sysv/linux/i386/makecontext.S:88 #18 0x80c78570 in ?? () #19 0x8124 in ?? () #20 0x0001 in ?? () #21 0x in ?? () Few questions of mine are: 1) Is it problem with using directory with -sd option? I have seen that most of ppl. use -sd with SD card image file? 2) Why WRITE_THROUGH action only calls commit_one_file that looks to be handling only single file commits? 3) Is SD card emulation stable or its known to be broken? Thanks, Taimoor -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [RFC] Enabling x2apic on most (all?) x86 CPU models
Hi,
Am 18.09.2013 22:39, schrieb Eduardo Habkost:
Hi,
I would like to get your opinion on this:
Currently we have x2apic enabled only on SandyBridge and Haswell CPU
models because we try to keep the CPU models closer to real CPUs.
However, x2apic improves performance by reducing the overhead of APIC
accesses, and KVM can emulate it independently of host CPU support for
x2apic. This feature is present on KVM for 4 years, already (since
v2.6.32). There's no reason for people to not have x2apic enabled when
running KVM.
So, my question is: should we break the try to be close to real CPUs
rule and enable x2apic by default on most (or all) CPU models? I believe
it is a reasonable thing to do.
I disagree, since this would also affect TCG. I would prefer to add
x2apic only to models that really have it and would be open to generally
enabling it for kvm_enabled() in instance_init/registration (so that
users can disable it via ,-x2apic or soon QMP).
As always, software might make weird assumptions about effects of a
present CPUID bit, but I trust you'll do some more testing before
submitting a non-RFC patch. :)
Regards,
Andreas
Also: if we do it, should we do it for all CPU models on
target-i386/cpu.c, or just a subset of them? (maybe the more recent
ones?)
(The patch below touches only Conroe, Penryn, Nehalem, and Westmere, and
it lacks machine-type compatibility code. But I am planning to submit a
patch that changes all CPU models to include x2apic by default.)
---
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 9abb73f..f76c34b 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -791,7 +791,7 @@ static x86_def_t builtin_x86_defs[] = {
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
-CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
+CPUID_EXT_SSSE3 | CPUID_EXT_SSE3 | CPUID_EXT_X2APIC,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
@@ -814,7 +814,7 @@ static x86_def_t builtin_x86_defs[] = {
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_SSE3,
+ CPUID_EXT_SSE3 | CPUID_EXT_X2APIC,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
@@ -837,7 +837,8 @@ static x86_def_t builtin_x86_defs[] = {
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
- CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
+ CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3 |
+ CPUID_EXT_X2APIC,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.features[FEAT_8000_0001_ECX] =
@@ -861,7 +862,7 @@ static x86_def_t builtin_x86_defs[] = {
.features[FEAT_1_ECX] =
CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
+ CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_X2APIC,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.features[FEAT_8000_0001_ECX] =
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] block/stream.c -Werror build failure
Hello, As reported yesterday on IRC, since the last round of pulls I am getting the following warning-treated-as-error: CCblock/stream.o /home/andreas/QEMU/qemu/block/stream.c: In function ‘stream_run’: /home/andreas/QEMU/qemu/block/stream.c:111:14: error: ‘copy’ may be used uninitialized in this function [-Werror=maybe-uninitialized] cc1: all warnings being treated as errors make: *** [block/stream.o] Fehler 1 $ gcc --version gcc (SUSE Linux) 4.7.2 20130108 [gcc-4_7-branch revision 195012] However I only got this in 1 of 2 repositories I tried. It turns out that --enable-debug avoids this build issue. The stream.c code itself looks okay to me. In the case of ret = 0, copy is always assigned, including the goto code path. Still, could we initialize the copy variable to false or revert whatever change introduced this build regression? (-Wextra?) Regards, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
