[spi-devel-general] [PATCH 1/2] spi: Add support for dma_min_bytes configuration.

2010-04-06 Thread Roman Tereshonkov 
This parameters defines the minimum number of bytes when dma is used.

Signed-off-by: Roman Tereshonkov roman.tereshon...@nokia.com
---
 drivers/spi/spi.c   |1 +
 include/linux/spi/spi.h |3 +++
 2 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index b76f246..5bf7992 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -347,6 +347,7 @@ struct spi_device *spi_new_device(struct spi_master *master,
proxy-max_speed_hz = chip-max_speed_hz;
proxy-mode = chip-mode;
proxy-irq = chip-irq;
+   proxy-dma_min_bytes = chip-dma_min_bytes;
strlcpy(proxy-modalias, chip-modalias, sizeof(proxy-modalias));
proxy-dev.platform_data = (void *) chip-platform_data;
proxy-controller_data = chip-controller_data;
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 97b60b3..4e9961d 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -84,6 +84,7 @@ struct spi_device {
 #defineSPI_NO_CS   0x40/* 1 dev/bus, no 
chipselect */
 #defineSPI_READY   0x80/* slave pulls low to 
pause */
u8  bits_per_word;
+   int dma_min_bytes;
int irq;
void*controller_state;
void*controller_data;
@@ -727,6 +728,8 @@ struct spi_board_info {
 */
u8  mode;
 
+   /* dma_min_bytes defines minimum bytes when dma is used */
+   u32 dma_min_bytes;
/* ... may need additional spi_device chip config data here.
 * avoid stuff protocol drivers can set; but include stuff
 * needed to behave without being bound to a driver:
-- 
1.6.2.rc1.3.g81d3f


--
Download Intel#174; Parallel Studio Eval
Try the new software tools for yourself. Speed compiling, find bugs
proactively, and fine-tune applications for parallel performance.
See why Intel Parallel Studio got high marks during beta.
http://p.sf.net/sfu/intel-sw-dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

[spi-devel-general] [PATCH 2/2] omap2_mcspi: Use dma_min_bytes parameter when it is configured.

2010-04-06 Thread Roman Tereshonkov 
When dma_min_bytes parameter is set as non-zero from device configuration it
overlaps the global one DMA_MIN_BYTES.

Signed-off-by: Roman Tereshonkov roman.tereshon...@nokia.com
---
 drivers/spi/omap2_mcspi.c |   12 ++--
 1 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index a9d58ce..1befdf8 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -793,6 +793,7 @@ static void omap2_mcspi_work(struct work_struct *work)
int par_override = 0;
int status = 0;
u32 chconf;
+   u32 dma_min_bytes = DMA_MIN_BYTES;
 
m = container_of(mcspi-msg_queue.next, struct spi_message,
 queue);
@@ -803,6 +804,9 @@ static void omap2_mcspi_work(struct work_struct *work)
spi = m-spi;
cs = spi-controller_state;
 
+   if (spi-dma_min_bytes)
+   dma_min_bytes = spi-dma_min_bytes;
+
omap2_mcspi_set_enable(spi, 1);
list_for_each_entry(t, m-transfers, transfer_list) {
if (t-tx_buf == NULL  t-rx_buf == NULL  t-len) {
@@ -839,7 +843,7 @@ static void omap2_mcspi_work(struct work_struct *work)
__raw_writel(0, cs-base
+ OMAP2_MCSPI_TX0);
 
-   if (m-is_dma_mapped || t-len = DMA_MIN_BYTES)
+   if (m-is_dma_mapped || t-len = dma_min_bytes)
count = omap2_mcspi_txrx_dma(spi, t);
else
count = omap2_mcspi_txrx_pio(spi, t);
@@ -889,6 +893,7 @@ static int omap2_mcspi_transfer(struct spi_device *spi, 
struct spi_message *m)
struct omap2_mcspi  *mcspi;
unsigned long   flags;
struct spi_transfer *t;
+   u32 dma_min_bytes;
 
m-actual_length = 0;
m-status = 0;
@@ -896,6 +901,9 @@ static int omap2_mcspi_transfer(struct spi_device *spi, 
struct spi_message *m)
/* reject invalid messages and transfers */
if (list_empty(m-transfers) || !m-complete)
return -EINVAL;
+
+   dma_min_bytes = spi-dma_min_bytes ? spi-dma_min_bytes : DMA_MIN_BYTES;
+
list_for_each_entry(t, m-transfers, transfer_list) {
const void  *tx_buf = t-tx_buf;
void*rx_buf = t-rx_buf;
@@ -921,7 +929,7 @@ static int omap2_mcspi_transfer(struct spi_device *spi, 
struct spi_message *m)
return -EINVAL;
}
 
-   if (m-is_dma_mapped || len  DMA_MIN_BYTES)
+   if (m-is_dma_mapped || len  dma_min_bytes)
continue;
 
/* Do DMA mapping early for better error reporting and
-- 
1.6.2.rc1.3.g81d3f


--
Download Intel#174; Parallel Studio Eval
Try the new software tools for yourself. Speed compiling, find bugs
proactively, and fine-tune applications for parallel performance.
See why Intel Parallel Studio got high marks during beta.
http://p.sf.net/sfu/intel-sw-dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

[spi-devel-general] Decouvrez le grand canyon en famille

2010-04-06 Thread Fnac Eveil et Jeux par Fanito 
Si vous ne visualisez pas ce mail, suivez ce lien 
http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070C6000B8QL8



Afin d'être sûr de recevoir tous nos emails, ajoutez newslet...@fanito.fr à 
votre carnet d'adresses.











http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070BO000B8QL8 

http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070BP000B8QL8 

http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070BQ000B8QL8 


http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070BR000B8QL8 



http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070BS000B8QL8 

http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070BT000B8QL8 
un voyage en famille dans l'ouest des Etats-Unis
 et plein d'autres cadeaux !

http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070BU000B8QL8 



http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070BV000B8QL8 

http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070BW000B8QL8 


http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070BX000B8QL8 

http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070BY000B8QL8 


*Consulter le 
http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070BZ000B8QL8 
règlement


Jeu gratuit sans obligation d'achat. Photos non contractuelles.

Conformément à la loi informatique et libertés du 6 janvier 
1978 modifiée, vous pouvez à tout moment demander à accéder, faire rectifier ou 
supprimer les informations personnelles vous concernant ou vous opposer à leur 
traitement par Fnac éveil  jeux .

 



Si vous souhaitez vous désabonner, cliquez 
http://tr1.bp42.net/r5.aspx?GV1=KPYN02A001O50002BB00070CB8QL8fguidv5=0002B5
 
ici.



À tout moment, vous disposez d'un droit d'accès, de modification, de 
rectification et de suppression de vos données personnelles (art 34 de la loi 
Informatique et Libertés du 6 Janvier 1978).  Vous pouvez également en faire la 
demande par courrier :  Plebicom - Service Clients - 16 quai de la Mégisserie - 
75001Paris



  
--
Download Intel#174; Parallel Studio Eval
Try the new software tools for yourself. Speed compiling, find bugs
proactively, and fine-tune applications for parallel performance.
See why Intel Parallel Studio got high marks during beta.
http://p.sf.net/sfu/intel-sw-dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general

Re: [spi-devel-general] [PATCH v2 1/3] spi: implemented driver for Cirrus EP93xx SPI controller

2010-04-06 Thread Martin Guy 
On 4/6/10, Mika Westerberg mika.westerb...@iki.fi wrote:
 On Thu, Apr 01, 2010 at 01:15:20AM +0100, Martin Guy wrote:
   I have another question: like the Cirrus driver, this takes 100% CPU
   doing busy wait for the current transfer to complete.

  I tried to find out whether the driver did something wrong to get
  into busylooping but couldn't find anything. In case of MMC/SD
  cards, through mmc_spi, transfer sizes are = 512 bytes at a time
  and FIFO size is only 8 bytes (or words) so the CPU is expected to
  be pretty busy serving interrupts from the SSP.

Right. that explains it.
The board I'm testing it with just has a single mmc/sd card on the ssp port.

The docs say separate transmit and receive FIFO memory buffers, 16
bits wide, 8 locations deep.
Watching vmstat output with this driver, it gets 226 kB/sec reading
/dev/mmcblk0 at 100% system cpu usage with 2354 interrupts and 2724
context switches per second. I don't see how that relates to 8 bytes
or 8 halfwords per interrupt; it suggests 100 bytes transferred per
interrupt once you remove the 100/sec of clock tick irq.
Writing instead gets 228kB/sec incurring 1916 (read: 1815) irqs and
934 context switches.
Similarly, checking /proc/interrupts, writing 10MB to the raw device
incurs 83221 ep93xx-spi interrupts: one per 125 bytes transferred. Is
it maybe busy-waiting filling the output FIFO as fast as it is
emptying?

Here's the code I'm talking about:

static int ep93xx_spi_read_write(struct ep93xx_spi *espi)
{
...
/*
 * Write as long as TX FIFO is not full. After every write we check
 * whether RX FIFO has any new data in it (and in that case we read what
 * ever was in the RX FIFO).
 */
while ((ep93xx_spi_read_u8(espi, SSPSR)  SSPSR_TNF) 
espi-tx  t-len) {
ep93xx_do_write(espi, t);

if (ep93xx_spi_wait_busy(espi, SPI_TIMEOUT)) {
msg-status = -ETIMEDOUT;
return msg-status;
}

while ((ep93xx_spi_read_u8(espi, SSPSR)  SSPSR_RNE) 
espi-rx  t-len) {
ep93xx_do_read(espi, t);
}
}
...

and ep93xx_spi_wait_busy() reads a device register in an busy loop
with a timeout:

static int ep93xx_spi_wait_busy(const struct ep93xx_spi *espi,
unsigned long msecs)
{
unsigned long timeout = jiffies + msecs_to_jiffies(msecs);

while (time_before(jiffies, timeout)) {
if ((ep93xx_spi_read_u16(espi, SSPSR)  SSPSR_BSY) == 0)
return 0;
cpu_relax();
}

return -ETIMEDOUT;
}

The manual says that the BSY status bit means
SSP is currently transmitting and / or receiving a frame
or the transmit FIFO is non-empty.
so this would make the code
- output one byte/halfword
- wait busily until the FIFO is empty of that one datum
- maybe read one received word/byte
- loop

This seems bizarre compared to what the hardware suggests:
We only have one interrupt, which is triggered when
- the TX buffer is less than half empty (ie there is room for 4 or more words)
- the RX buffer is more than half full (ie there are four or more
words to read from it)
- RX overrun
and there are status bits to tell us whether the TX and RX buffers are
full, empty or half-full (the half-full bits triggering the
interrupts).

My understanding ATM is that this version enables interrupts to start
a transfer, immediately gets interrupted because the transmit buffer
is less than half empty, and if it is supposed to be reading from the
card, tramsmits a 0 byte/halfword for every byte/halfword it is
supposed to be receiving.

If it's supposed to be sending, it pokes one byte/halfword into the
write FIFO, waits for that to have been completely transmitted and for
the FIFO to be empty, then checks if it should read anything, then
writes another byte/halfword etc. and so on.

This seems completely at odds with what the hardware suggests, which would be
WRITE: fill the TX buffer, then wait for half-empty IRQ.
READ: react to half-full IRQ by emptying the RX buffer.
with some hackery because if you receive a final 1, 2 or 3
byte/halfwords, you don't get an RX interrupt.

I've tried removing the busy-wait from the read-write loop and the
kernel hangs forever as soon as it looks at the SSP device. Worse, my
serial console is dead so I can't be more expicit.

Am I missing something here, or is the current strategy forced by
undocumented brokenness of the hardware?

Lastly, what is the meaning of conditional operator(s) in
return t-bits_per_word ?: msg-spi-bits_per_word;
It compiles, but it's the first time I've seen this construct in 27
years of C programming. What is the normal syntax for this?

M

--
Download Intel#174; Parallel Studio Eval
Try the new software tools for

[SPAM] Жилищно - коммунальное хозяйство: правовое регулирование и налогообложениеaj

2010-04-06 Thread Руководителю Ж К Х 

*  14 - 15  апреля  2010г.
*
*   ЖКХ   (ЖИЛИЩНО  -  КОММУНАЛЬНОЕ  ХОЗЯЙСТВО): 
*   особенности регулирования и налогообложения
*


ПРИГЛАШАЮТСЯ: руководители предприятий ЖКХ, главные бухгалтеры, юристы.



ПРОГРАММА  СЕМИНАРА

1. Общие положения об оказании услуг в жилищно – коммунальном хозяйстве. Защита 
прав потребителей при оказании услуг в жилищно – коммунальном хозяйстве.

2. Прием построенных объектов на обслуживание (в управление). Бюджетное 
финансирование предприятий жилищно - коммунального комплекса. Бюджетные 
учреждения жилищно - коммунального комплекса. Плата за наем жилья. 
Налогообложение целевого финансирования и целевых поступлений. Финансирование 
капитального ремонта, в том числе накопление. Муниципальный заказ.

3. Квартплата – система налогообложения в соответствии со структурой. Часть 
квартплаты, за услуги по управлению и содержанию общего имущества (без 
перепредъявляемых коммунальных платежей). Квартплата – документооборот. 
Кассовые операции в жилищно - коммунальном комплексе. Коммунальные платежи, 
выставляемые жильцам по посреднической квалификации. Получение из бюджета 
финансирования на компенсацию квартплаты – квалификация, учет и 
налогообложение. Определение тарифов в жилищно - коммунальном комплексе. 

4. Налог на прибыль по обслуживающим производствам и хозяйствам. Упрощенная 
система налогообложения в жилищно - коммунальном комплексе. ЕНВД в жилищно - 
коммунальном комплексе.

5. Концессионные соглашения – правовые основы. Концессионные соглашения – 
бухгалтерский учет. Концессионные соглашения – налогообложение прибыли. Налог 
на имущество при концессионных. Концессионное соглашение и НДС.

6. Управляющие организации, правовые основы, конкурс по выбору. Управляющие 
организации – бухгалтерский учет. Управляющие организации – налогообложение.

7. Недвижимость как основное средство, проблемы связанные с датой начала 
налогового или бухгалтерского учета. Жилье как основное средство. Налог на 
имущество в ЖКХ. Земля как основное средство. Приобретение земельных участков в 
собственность. Земельный налог в ЖКХ.

8. Жилищный накопительный кооператив – правовые основы. Жилищный 
(жилищно-строительный) кооператив – правовые основы. Строительство с созданием 
организации для объединения у организации (ЖСК и т.п.). Строительство с 
созданием организации для объединения у инвестора (ЖСК и т.п.).

9. Товарищества собственников жилья (ТСЖ) – правовые основы. Товарищества 
собственников жилья – бухгалтерский учет. Товарищества собственников жилья – 
налогообложение.

10. Собственные котельные. Плата за отопление – регулирование, учет и 
налогообложение. Плата за электричество – регулирование, учет и 
налогообложение. Плата за газоснабжение – регулирование, учет и 
налогообложение. Плата за водоснабжение – регулирование, учет и 
налогообложение. Плата за водоотведение – регулирование, учет и 
налогообложение. 

11. Использование общего имущества (кондоминиум). Ответственность за вред, 
нанесенный общим имуществом. Плата за негативное воздействие на окружающую 
среду и вывоз твердых бытовых отходов.

12. Документооборот по ремонту жилищного фонда. Текущий ремонт жилищного фонда. 
Расходы по благоустройству – налог на прибыль. Придомовые автостоянки.

13. Садоводческое, огородническое или дачное некоммерческое объединение граждан 
– правовые основы. Садоводческое товарищество – учет и налогообложение. 
Собственные скважины, с учетом водного налога.

Ответы на все вопросы по жилищно-коммунальному хозяйству.



14 - 15 апреля 2010 года.  (2 дня с 10.00 до 18.00) 

Место проведения: Москва, м. Ботанический сад, Учебная гостиница

Стоимость участия: 17 500 руб. (В стоимость входит обучение, печатные материалы 
по теме семинара, обеды, кофе-паузы). По окончании выдается сертификат о 
прохождении обучения по данной теме. Иногородним поможем забронировать номера в 
гостинице. Обучение и проживание в одном здании.




Подробная информация и регистрация по телефону: 8 (495) 229 - 04 - 33








Внимание! Если Ваш адрес случайно попал в базу рассылки, и Вы больше не хотите 
получать информацию об образовательных мероприятиях, 
просто отправьте пустое письмо в Вашего адреса на адрес 
unsubscr...@notseminar.ru?subject=spi-devel-general@lists.sourceforge.net и в 
теме письма укажите Ваш адрес электронной почты. 


Ваш адрес будет автоматически удален из рассылки в течение 1 (одного) дня!


TO  UNSUBSCRIBE   SEND  YOUR   EMAIL   ADDRESS IN SUBJECT TO   
unsubscr...@notseminar.ru?subject=spi-devel-general@lists.sourceforge.net

Re: [spi-devel-general] [PATCH v2 1/3] spi: implemented driver for Cirrus EP93xx SPI controller

2010-04-06 Thread Mika Westerberg 
On Tue, Apr 06, 2010 at 01:50:44PM +0100, Martin Guy wrote:
 On 4/6/10, Mika Westerberg mika.westerb...@iki.fi wrote:
  On Thu, Apr 01, 2010 at 01:15:20AM +0100, Martin Guy wrote:
I have another question: like the Cirrus driver, this takes 100% CPU
doing busy wait for the current transfer to complete.
 
   I tried to find out whether the driver did something wrong to get
   into busylooping but couldn't find anything. In case of MMC/SD
   cards, through mmc_spi, transfer sizes are = 512 bytes at a time
   and FIFO size is only 8 bytes (or words) so the CPU is expected to
   be pretty busy serving interrupts from the SSP.
 
 Right. that explains it.
 The board I'm testing it with just has a single mmc/sd card on the ssp port.
 
 The docs say separate transmit and receive FIFO memory buffers, 16
 bits wide, 8 locations deep.
 Watching vmstat output with this driver, it gets 226 kB/sec reading
 /dev/mmcblk0 at 100% system cpu usage with 2354 interrupts and 2724
 context switches per second. I don't see how that relates to 8 bytes
 or 8 halfwords per interrupt; it suggests 100 bytes transferred per
 interrupt once you remove the 100/sec of clock tick irq.
 Writing instead gets 228kB/sec incurring 1916 (read: 1815) irqs and
 934 context switches.
 Similarly, checking /proc/interrupts, writing 10MB to the raw device
 incurs 83221 ep93xx-spi interrupts: one per 125 bytes transferred. Is
 it maybe busy-waiting filling the output FIFO as fast as it is
 emptying?

If you check the sizes of the transfers for the MMC case it is something like:

[ 1796.08] ep93xx-spi ep93xx-spi: setup: mode 0, cpsr 2, scr 0, dss 7
[ 1796.08] ep93xx-spi ep93xx-spi: setup: cr0 0x7
[ 1796.08] ep93xx-spi ep93xx-spi: ep93xx_spi_process_transfer: transferring 
512 bytes
[ 1796.08] ep93xx-spi ep93xx-spi: ep93xx_spi_interrupt: handling interrupt
[ 1796.08] ep93xx-spi ep93xx-spi: ep93xx_spi_read_write: tx=512, rx=512
[ 1796.08] ep93xx-spi ep93xx-spi: ep93xx_spi_process_transfer: transferring 
2 bytes
[ 1796.08] ep93xx-spi ep93xx-spi: ep93xx_spi_interrupt: handling interrupt
[ 1796.08] ep93xx-spi ep93xx-spi: ep93xx_spi_read_write: tx=2, rx=2
[ 1796.08] ep93xx-spi ep93xx-spi: ep93xx_spi_process_transfer: transferring 
1 bytes
[ 1796.08] ep93xx-spi ep93xx-spi: ep93xx_spi_interrupt: handling interrupt
[ 1796.08] ep93xx-spi ep93xx-spi: ep93xx_spi_read_write: tx=1, rx=1

So size of the transfer varies, depending on what kind of message
is passed from mmc_spi to the driver. From the above, we can see
that ep93xx_spi_read_write() transfers 512 bytes before passing control
back to the calling interrupt handler.

I got the same results with polling enabled (this is with v3 which is not yet
posted).

 
 Here's the code I'm talking about:
 
 static int ep93xx_spi_read_write(struct ep93xx_spi *espi)
 {
 ...
 /*
  * Write as long as TX FIFO is not full. After every write we check
  * whether RX FIFO has any new data in it (and in that case we read 
 what
  * ever was in the RX FIFO).
  */
 while ((ep93xx_spi_read_u8(espi, SSPSR)  SSPSR_TNF) 
 espi-tx  t-len) {
 ep93xx_do_write(espi, t);
 
 if (ep93xx_spi_wait_busy(espi, SPI_TIMEOUT)) {
 msg-status = -ETIMEDOUT;
 return msg-status;
 }
 
 while ((ep93xx_spi_read_u8(espi, SSPSR)  SSPSR_RNE) 
 espi-rx  t-len) {
 ep93xx_do_read(espi, t);
 }
 }
 ...
 
 and ep93xx_spi_wait_busy() reads a device register in an busy loop
 with a timeout:
 
 static int ep93xx_spi_wait_busy(const struct ep93xx_spi *espi,
 unsigned long msecs)
 {
 unsigned long timeout = jiffies + msecs_to_jiffies(msecs);
 
 while (time_before(jiffies, timeout)) {
 if ((ep93xx_spi_read_u16(espi, SSPSR)  SSPSR_BSY) == 0)
 return 0;
 cpu_relax();
 }
 
 return -ETIMEDOUT;
 }
 
 The manual says that the BSY status bit means
 SSP is currently transmitting and / or receiving a frame
 or the transmit FIFO is non-empty.

I think that when the controller is enabled (SSE is set), it is
transmitting/receiving once there is data (TX). It even enables the
SPI output clock only when TX data is put into TX FIFO (I checked
this with oscilloscope).

I added debug print to this function (ep93xx_spi_wait_busy()) and
it loops only once. If I don't wait while the bit is cleared, the
controller hangs.

 so this would make the code
 - output one byte/halfword
 - wait busily until the FIFO is empty of that one datum
 - maybe read one received word/byte
 - loop
 
 This seems bizarre compared to what the hardware suggests:
 We only have one interrupt, which is triggered when
 - the TX buffer is less than half empty (ie there is room for 4 or more words)
 - the RX

Re: [spi-devel-general] [PATCH v2 1/3] spi: implemented driver for Cirrus EP93xx SPI controller

2010-04-06 Thread Martin Guy 
On 4/6/10, Mika Westerberg mika.westerb...@iki.fi wrote:
  I only have one ep9302 board and 2 SPI devices

If you'd like one of the MMC-only boards to test on, I can ship it to
you - please provide smail mail address by private mail if that would
be welcome

   Lastly, what is the meaning of conditional operator(s) in
   return t-bits_per_word ?: msg-spi-bits_per_word;
   It compiles, but it's the first time I've seen this construct in 27
   years of C programming. What is the normal syntax for this?

 It is an GCC extension:

  http://gcc.gnu.org/onlinedocs/gcc-4.4.3/gcc/Conditionals.html#Conditionals

  I've been using it once I saw it somewhere in the kernel source.

OK, I suggest we don't use GNU extensions if they can be avoided,
and program in C. The GCC monoculture is ending, thanks to llvm. and
those gnu-heads are not the most wise people on the planet. (OK, the
ANSI committe are worse, but :)

   M

--
Download Intel#174; Parallel Studio Eval
Try the new software tools for yourself. Speed compiling, find bugs
proactively, and fine-tune applications for parallel performance.
See why Intel Parallel Studio got high marks during beta.
http://p.sf.net/sfu/intel-sw-dev
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general