[U-Boot] [PATCH v2 2/3] ARM:AM33XX: Add mmc/sd support
This patch add supports for mmc/sd driver on AM335X platform.
PLL and pinmux configurations for mmc/sd are configured in this
patch.
Signed-off-by: Chandan Nath chandan.n...@ti.com
Signed-off-by: Tom Rini tr...@ti.com
---
Changes since v1:
- Removed unwanted code from omap_hsmmc.c file
- Rebased to master branch
arch/arm/cpu/armv7/am33xx/board.c |7 +
arch/arm/cpu/armv7/am33xx/clock.c |5 +
arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 164 +++
board/ti/am335x/mux.c | 20 +++
include/configs/am335x_evm.h|9 ++
5 files changed, 205 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-am33xx/mmc_host_def.h
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 78db3a5..312643c 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -64,3 +64,10 @@ void init_timer(void)
/* Start the Timer */
writel(0x1, (timer_base-tclr));
}
+
+#if defined(CONFIG_OMAP_HSMMC) !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
index 7070e7d..98cfd93 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -108,6 +108,11 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, cmwkup-wkup_uart0ctrl);
while (readl(cmwkup-wkup_uart0ctrl) != PRCM_MOD_EN)
;
+
+ /* MMC0*/
+ writel(PRCM_MOD_EN, cmper-mmc0clkctrl);
+ while (readl(cmper-mmc0clkctrl) != PRCM_MOD_EN)
+ ;
}
static void mpu_pll_config(void)
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
new file mode 100644
index 000..e56c018
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -0,0 +1,164 @@
+/*
+ * mmc_host_def.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/*
+ * OMAP HSMMC register definitions
+ */
+#define OMAP_HSMMC1_BASE 0x48060100
+#define OMAP_HSMMC2_BASE 0x481D8000
+#define OMAP_HSMMC3_BASE 0x47C24000
+
+typedef struct hsmmc {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned int sysstatus; /* 0x14 */
+ unsigned char res2[0x14];
+ unsigned int con; /* 0x2C */
+ unsigned char res3[0xD4];
+ unsigned int blk; /* 0x104 */
+ unsigned int arg; /* 0x108 */
+ unsigned int cmd; /* 0x10C */
+ unsigned int rsp10; /* 0x110 */
+ unsigned int rsp32; /* 0x114 */
+ unsigned int rsp54; /* 0x118 */
+ unsigned int rsp76; /* 0x11C */
+ unsigned int data; /* 0x120 */
+ unsigned int pstate;/* 0x124 */
+ unsigned int hctl; /* 0x128 */
+ unsigned int sysctl;/* 0x12C */
+ unsigned int stat; /* 0x130 */
+ unsigned int ie;/* 0x134 */
+ unsigned char res4[0x8];
+ unsigned int capa; /* 0x140 */
+} hsmmc_t;
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET (0x1 1)
+#define RESETDONE (0x1 0)
+#define NOOPENDRAIN(0x0 0)
+#define OPENDRAIN (0x1 0)
+#define OD (0x1 0)
+#define INIT_NOINIT(0x0 1)
+#define INIT_INITSTREAM(0x1 1)
+#define HR_NOHOSTRESP (0x0 2)
+#define STR_BLOCK (0x0 3)
+#define MODE_FUNC (0x0 4)
+#define DW8_1_4BITMODE (0x0 5)
+#define MIT_CTO(0x0 6)
+#define CDP_ACTIVEHIGH (0x0 7)
+#define WPP_ACTIVEHIGH (0x0 8)
+#define RESERVED_MASK (0x3 9)
+#define CTPL_MMC_SD(0x0 11)
+#define BLEN_512BYTESLEN (0x200 0)
+#define NBLK_STPCNT(0x0 16)
+#define DE_DISABLE (0x0 0)
+#define BCE_DISABLE(0x0 1)
+#define BCE_ENABLE (0x1 1)
+#define ACEN_DISABLE
[U-Boot] [PATCH v2 0/3] Added SPL support
This patch series is submitted to add support for MMC/SD along with SPL support. Also, fixed incorrect register offset of ddr and timer registers. The patches have been compile tested and run on AM335X EVM. The patches depends on previous patch series which was submitted for supporting AM33xx platform. The patches are applies on uboot master branch. Changes since v1: - Removed unwanted code from omap_hsmmc.c file - Changed CONFIG_AM335X to CONFIG_AM33XX - Rebased to master branch - Replaced am33xx/lowleve_init.S with omap-common/lowlevel_init.S in order to use common code for omap_bootmode. Chandan Nath (3): ARM:AM33XX: Fix ddr and timer register offset ARM:AM33XX: Add mmc/sd support ARM:AM33XX: Add SPL support for AM335X EVM Makefile|2 +- arch/arm/cpu/armv7/am33xx/Makefile |2 - arch/arm/cpu/armv7/am33xx/board.c | 80 ++- arch/arm/cpu/armv7/am33xx/clock.c |8 + arch/arm/cpu/armv7/am33xx/config.mk | 18 +++ arch/arm/cpu/armv7/am33xx/emif4.c |2 +- arch/arm/cpu/armv7/am33xx/lowlevel_init.S | 72 -- arch/arm/cpu/armv7/omap-common/Makefile |3 + arch/arm/include/asm/arch-am33xx/common_def.h | 22 +++ arch/arm/include/asm/arch-am33xx/cpu.h | 44 +++--- arch/arm/include/asm/arch-am33xx/ddr_defs.h |6 +- arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 164 +++ arch/arm/include/asm/arch-am33xx/sys_proto.h|1 + arch/arm/include/asm/omap_common.h |5 + board/ti/am335x/common_def.h| 24 board/ti/am335x/evm.c |2 +- board/ti/am335x/mux.c | 22 +++- include/configs/am335x_evm.h| 61 +++-- spl/Makefile| 13 +- 19 files changed, 398 insertions(+), 153 deletions(-) create mode 100644 arch/arm/cpu/armv7/am33xx/config.mk delete mode 100644 arch/arm/cpu/armv7/am33xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-am33xx/common_def.h create mode 100644 arch/arm/include/asm/arch-am33xx/mmc_host_def.h delete mode 100644 board/ti/am335x/common_def.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/3] ARM:AM33XX: Fix ddr and timer register offset
This patch is added to update incorrect ddr, pll and timer
register offset along with some additional cleanup like
removing unused code. Also, generic CONFIG_AM33XX symbol
is added for AM33XX platform.
Signed-off-by: Chandan Nath chandan.n...@ti.com
Signed-off-by: Tom Rini tr...@ti.com
---
Changes since v1:
- Changed CONFIG_AM335X to CONFIG_AM33XX
- Rebased to master branch
Makefile|2 +-
arch/arm/cpu/armv7/am33xx/board.c |8 ++--
arch/arm/cpu/armv7/am33xx/clock.c |3 ++
arch/arm/include/asm/arch-am33xx/cpu.h | 44 ++-
arch/arm/include/asm/arch-am33xx/ddr_defs.h |6 ++--
include/configs/am335x_evm.h| 13 ++-
6 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/Makefile b/Makefile
index 0438f1e..1f90afa 100644
--- a/Makefile
+++ b/Makefile
@@ -294,7 +294,7 @@ LIBS += lib/libfdt/libfdt.o
LIBS += api/libapi.o
LIBS += post/libpost.o
-ifneq ($(CONFIG_AM335X)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS += $(CPUDIR)/omap-common/libomap-common.o
endif
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 2d6d359..78db3a5 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -26,7 +26,7 @@
DECLARE_GLOBAL_DATA_PTR;
struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE;
+struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
/*
* early system init of muxing and clocks.
@@ -55,12 +55,12 @@ void s_init(u32 in_ddr)
void init_timer(void)
{
/* Reset the Timer */
- writel(0x2, (timerreg-tsicrreg));
+ writel(0x2, (timer_base-tscir));
/* Wait until the reset is done */
- while (readl(timerreg-tiocpcfgreg) 1)
+ while (readl(timer_base-tiocp_cfg) 1)
;
/* Start the Timer */
- writel(0x1, (timerreg-tclrreg));
+ writel(0x1, (timer_base-tclr));
}
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
index 4ca6c45..7070e7d 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -101,6 +101,9 @@ static void enable_per_clocks(void)
while (readl(cmper-timer2clkctrl) != PRCM_MOD_EN)
;
+ /* Select the Master osc 24 MHZ as Timer2 clock source */
+ writel(0x1, cmdpll-clktimer2clk);
+
/* UART0 */
writel(PRCM_MOD_EN, cmwkup-wkup_uart0ctrl);
while (readl(cmwkup-wkup_uart0ctrl) != PRCM_MOD_EN)
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
b/arch/arm/include/asm/arch-am33xx/cpu.h
index ad9156e..25558a2 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -51,7 +51,7 @@
| BIT(3) | BIT(4))
/* Reset control */
-#ifdef CONFIG_AM335X
+#ifdef CONFIG_AM33XX
#define PRM_RSTCTRL0x44E00F00
#endif
#define PRM_RSTCTRL_RESET 0x01
@@ -108,22 +108,36 @@ struct cm_perpll {
unsigned int l3sclkstctrl; /* offset 0x04 */
unsigned int l4fwclkstctrl; /* offset 0x08 */
unsigned int l3clkstctrl; /* offset 0x0c */
- unsigned int resv1[6];
+ unsigned int resv1;
+ unsigned int cpgmac0clkctrl;/* offset 0x14 */
+ unsigned int resv2[4];
unsigned int emifclkctrl; /* offset 0x28 */
unsigned int ocmcramclkctrl;/* offset 0x2c */
- unsigned int resv2[12];
+ unsigned int gpmcclkctrl; /* offset 0x30 */
+ unsigned int resv3[2];
+ unsigned int mmc0clkctrl; /* offset 0x3C */
+ unsigned int elmclkctrl;/* offset 0x40 */
+ unsigned int i2c2clkctrl; /* offset 0x44 */
+ unsigned int i2c1clkctrl; /* offset 0x48 */
+ unsigned int spi0clkctrl; /* offset 0x4C */
+ unsigned int spi1clkctrl; /* offset 0x50 */
+ unsigned int resv4[3];
unsigned int l4lsclkctrl; /* offset 0x60 */
unsigned int l4fwclkctrl; /* offset 0x64 */
- unsigned int resv3[6];
+ unsigned int resv5[6];
unsigned int timer2clkctrl; /* offset 0x80 */
- unsigned int resv4[19];
+ unsigned int resv6[11];
+ unsigned int gpio2clkctrl; /* offset 0xB0 */
+ unsigned int resv7[7];
unsigned int emiffwclkctrl; /* offset 0xD0 */
- unsigned int resv5[2];
+ unsigned int resv8[2];
unsigned int l3instrclkctrl;/* offset 0xDC */
unsigned int l3clkctrl; /* Offset 0xE0 */
- unsigned int resv6[14];
+ unsigned int resv9[14];
unsigned int l4hsclkstctrl; /* offset 0x11C */
unsigned int l4hsclkctrl; /* offset 0x120 */
+ unsigned int resv10[8];
+
[U-Boot] [PATCH v2 3/3] ARM:AM33XX: Add SPL support for AM335X EVM
This patch is added to support SPL feature on AM335X
platform. In this patch, MMC1 is configured as boot
device for SPL and support for other devices will be
added in the next patch series.
Signed-off-by: Chandan Nath chandan.n...@ti.com
Signed-off-by: Tom Rini tr...@ti.com
---
Changes since v1:
- Rebased to master branch
- Replaced am33xx/lowleve_init.S with omap-common/lowlevel_init.S
in order to use common code for omap_bootmode.
arch/arm/cpu/armv7/am33xx/Makefile|2 -
arch/arm/cpu/armv7/am33xx/board.c | 65 +--
arch/arm/cpu/armv7/am33xx/config.mk | 18 ++
arch/arm/cpu/armv7/am33xx/emif4.c |2 +-
arch/arm/cpu/armv7/am33xx/lowlevel_init.S | 72 -
arch/arm/cpu/armv7/omap-common/Makefile |3 +
arch/arm/include/asm/arch-am33xx/common_def.h | 22
arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
arch/arm/include/asm/omap_common.h|5 ++
board/ti/am335x/common_def.h | 24
board/ti/am335x/evm.c |2 +-
board/ti/am335x/mux.c |2 +-
include/configs/am335x_evm.h | 39 -
spl/Makefile | 13 ++---
14 files changed, 155 insertions(+), 115 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/config.mk
delete mode 100644 arch/arm/cpu/armv7/am33xx/lowlevel_init.S
create mode 100644 arch/arm/include/asm/arch-am33xx/common_def.h
delete mode 100644 board/ti/am335x/common_def.h
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile
b/arch/arm/cpu/armv7/am33xx/Makefile
index 6beafbb..7768912 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -16,8 +16,6 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
-SOBJS := lowlevel_init.o
-
COBJS += clock.o
COBJS += sys_info.o
COBJS += ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 312643c..2a45933 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -19,19 +19,45 @@
#include common.h
#include asm/arch/cpu.h
#include asm/arch/hardware.h
+#include asm/arch/omap.h
#include asm/arch/ddr_defs.h
#include asm/arch/clock.h
+#include asm/arch/mmc_host_def.h
+#include asm/arch/common_def.h
#include asm/io.h
+#include asm/omap_common.h
DECLARE_GLOBAL_DATA_PTR;
struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
+struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+
+struct omap_boot_parameters boot_params __attribute__ ((section(.data)));
+
+#ifdef CONFIG_SPL_BUILD
+u32 omap_bootmode = MMCSD_MODE_FAT;
+
+u32 omap_boot_device(void)
+{
+ return (u32) (boot_params.omap_bootdevice);
+}
+
+u32 omap_boot_mode(void)
+{
+ return omap_bootmode;
+}
+
+/* UART Defines */
+#define UART_RESET (0x1 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 0x3)
+#endif
/*
* early system init of muxing and clocks.
*/
-void s_init(u32 in_ddr)
+void s_init(void)
{
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid random resets
@@ -43,12 +69,37 @@ void s_init(u32 in_ddr)
while (readl(wdtimer-wdtwwps) != 0x0)
;
+#ifdef CONFIG_SPL_BUILD
/* Setup the PLLs and the clocks for the peripherals */
-#ifdef CONFIG_SETUP_PLL
pll_init();
+
+ /* UART softreset */
+ u32 regVal;
+
+ enable_uart0_pin_mux();
+
+ regVal = readl(uart_base-uartsyscfg);
+ regVal |= UART_RESET;
+ writel(regVal, uart_base-uartsyscfg);
+ while ((readl(uart_base-uartsyssts)
+ UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+ ;
+
+ /* Disable smart idle */
+ regVal = readl(uart_base-uartsyscfg);
+ regVal |= UART_SMART_IDLE_EN;
+ writel(regVal, uart_base-uartsyscfg);
+
+ /* Initialize the Timer */
+ init_timer();
+
+ preloader_console_init();
+
+ config_ddr();
#endif
- if (!in_ddr)
- config_ddr();
+
+ /* Enable MMC0 */
+ enable_mmc0_pin_mux();
}
/* Initialize timer */
@@ -71,3 +122,9 @@ int board_mmc_init(bd_t *bis)
return omap_mmc_init(0);
}
#endif
+
+void setup_clocks_for_console(void)
+{
+ /* Not yet implemented */
+ return;
+}
diff --git a/arch/arm/cpu/armv7/am33xx/config.mk
b/arch/arm/cpu/armv7/am33xx/config.mk
new file mode 100644
index 000..5750bbd
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/config.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation;
Re: [U-Boot] Secure update of uboot devices?
sha1sum sum is yes enough to verify that no files have been modified on the file system on the already installed Linux device. But my case here is if one need to update the software on the device out somewhere in the world we have now made a usb stick and uboot looks for special files first on the usb stick before it continues normal boot. How can one ensure that the software on the usb stick is not altered on the way to include some additional unwanted features? I mean a sha1sum on the usb stick one would ofcource also modify at same time as one add some files to the sub stick. I have been thinking of public/private keys but then you have the problem that these expires ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Secure update of uboot devices?
Dear Andreas, In message CAB+EkH4j-UoUyHb=XgDbGRncX=oq6+3+mnjwstiuojooyuc...@mail.gmail.com you wrote: sha1sum sum is yes enough to verify that no files have been modified on the file system on the already installed Linux device. It is also good enough to ensure that the files on any distribution media have not been corrupted or modified in some way. Of course it dies not protect against intentional modifications. But my case here is if one need to update the software on the device out somewhere in the world we have now made a usb stick and uboot looks for special files first on the usb stick before it continues normal boot. How can one ensure that the software on the usb stick is not altered on the way to include some additional unwanted features? You cannot. Actually you would have to insure first that the U-Boot running on that system has not been tampered with. If I were to attack such a system, I'd probably first install (or otherwise run) a version of U-boot that has any such security checks disabled or removed. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de There is, however, a strange, musty smell in the air that reminds me of something...hmm...yes...I've got it...there's a VMS nearby, or I'm a Blit. - Larry Wall in Configure from the perl distribution ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] common/image.c: align usage of fdt_high with initrd_high
The commit message of a28afca (Add uboot fdt_high enviroment variable)
states that fdt_high behaves similarly to the existing initrd_high.
But fdt_high actually has an outstanding difference from initrd_high.
The former specifies the start address, while the later specifies the
end address.
As fdt_high and initrd_high will likely be used together, it'd be nice
to have them behave same. The patch changes the behavior of fdt_high
to have it aligned with initrd_high.
Signed-off-by: Shawn Guo shawn@linaro.org
---
common/image.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/common/image.c b/common/image.c
index 77ca6e4..12ceacf 100644
--- a/common/image.c
+++ b/common/image.c
@@ -1294,10 +1294,8 @@ int boot_relocate_fdt(struct lmb *lmb, char
**of_flat_tree, ulong *of_size)
if (desired_addr) {
of_start =
(void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
- ((ulong)
- desired_addr)
- + of_len);
- if (desired_addr of_start != desired_addr) {
+ (ulong)desired_addr);
+ if (of_start == 0) {
puts(Failed using fdt_high value for Device
Tree);
goto error;
}
--
1.7.4.1
___
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Re: [U-Boot] [RFC PATCH 0/19] Create generic board init and move ARM and x86 to it
Hi Simon,
Sorry for the delay in reviewing this - I've been doing a lot of work on
the x86 side of things. I now have a working solution to the
board_init_f_r() / global data clobbering problem which involves having the
gd 'variable' as a register like all other arch's. The solution is
non-trivial and gd access is slightly more expensive than the vanilla
variable approach, but it makes this a lot cleaner cross-arch wise...
Here's a hint ;)
static inline gd_t *get_fs_gd_ptr(void)
{
gd_t *gd_ptr;
asm volatile(fs movl 0, %0\n : =r (gd_ptr));
return gd_ptr;
}
#define gd get_fs_gd_ptr()
On 28/12/11 17:35, Simon Glass wrote:
This series creates a generic board.c implementation which contains
the essential functions of the various arch/xxx/lib/board.c files.
What is the motivation for this change?
[snip]
I think that we can all agree that there is strong motivation for change.
However, I think this approach is not the right one - and I think the CFI
driver backs me up. Your plan is to create generic code which you want ALL
arches to cross over to, but you only look to migrate two initially and
migrate the rest 'later'. This is similar to what happened with the CFI
driver, and there are still boards with custom flash.c files which are
completely redundant.
But, creating a single patch-set to migrate everyone in one go is going to
be too massive a job to do in one go, and too prone to introducing breakage.
All the functions of board_init_f() and board_init_r() are broken into
separate function calls so that they can easily be included or excluded
for a particular architecture. It also makes it easier to adopt Graeme's
initcall proposal later if desired.
I think we should look at this sooner rather than later. I've shown with
x86 that the init sequence has three distinct phases:
1) Execute in flash using temporary RAM
2) Copy U-Boot from flash to RAM
3) Execute in RAM
My latest work now has all init functions having the same signature (i.e.
void parameter returning int). For x86, there is a little 'magic' that
needs to be done as gd is copied from temporary RAM to SDRAM, but for other
arches using a dedicated register, this is otherwise trivial.
So instead of trying to pluck out something (relocation in this case) from
the molasses of ten different board.c files and having to perform
open-heart surgery on them all to get the code grafted in, I think we
should approach it from the generic init sequence angle.
If we work each individual arch to use a generic init sequence (like the
proposed x86 code) then the init processing naturally falls out as common
code and the patch to realise this is trivial. From there, we can start to
pull out common init code like init_baudrate() and hang() and change the
function signatures of the functions that require wrappers and move some
#ifdef's into more appropriate locations - One example in board.c:
#ifdef CONFIG_BITBANGMII
int bb_miiphy_init_r(void)
{
bb_miiphy_init();
return 0;
}
#endif
Ouch!
The other big benefit is that you only touch one architecture at a time up
until you 'pull the switch'. And when you do pull the switch, you should be
factoring out identical code so the chances of breaking something should be
vastly reduced. Take a look at the history of ARM relocation for example -
that was constrained to one arch but still the amount of breakage was massive.
Generic relocation is used (see previous series) but now rather than
calling relocate_code() to do everything, we call the individual
relocation steps one by one. Again this makes it easier to leave things
out, particularly for SPL.
Note that not all arches need and/or use ELF relocation - Attacking this
first does not move towards unity of board.c
ARM is a relatively large board.c file and one which I can test, therefore
I think it is a good target for this series. On the other hand, x86 is
relatively small and simple, but different enough that it introduces a
few issues to be solved. So I have chosen both ARM and x86 for this series.
The next target should probably be PowerPC, since it is large and has
some additional features. I suspect we may want to leave some of these
very architecture-specific functions in arch/powerpc/lib/board.c, taking
out only the generic code. I haven't felt a strong need to do this for
ARM/x86, but we could even go as far as putting the initcall list into
the architecture-specific board file if the architecture adds a lot of
unusual calls.
A generic global_data structure is also required. This might upset a few
people. Here is my basic reasoning: most fields are the same, all
architectures include and need it, most global_data.h files already have
#ifdefs to select fields for a particular SOC, so it is hard to
see why architecures are different in this area. We can perhaps add a
way to put architecture-specific fields into a separate header file, but
for now I have judged that to be
Re: [U-Boot] [RFC PATCH 0/19] Create generic board init and move ARM and x86 to it
Dear Graeme Russ, In message 4efddd7d.50...@gmail.com you wrote: I honestly think we should get the x86 init sequence patches finalised first for several reasons: - Because x86 is so small, it provides a good test-bed - ELF relocation was first finalised on x86 (it came and went with varying levels of success previously) - They bring x86 in line with other arches re: global data - They are now fully run-tested I agree with that. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The game of life is a game of boomerangs. Our thoughts, deeds and words return to us sooner or later with astounding accuracy. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 0/19] Create generic board init and move ARM and x86 to it
Hi Graeme,
On Fri, Dec 30, 2011 at 7:49 AM, Graeme Russ graeme.r...@gmail.com wrote:
Hi Simon,
Sorry for the delay in reviewing this - I've been doing a lot of work on
the x86 side of things. I now have a working solution to the
board_init_f_r() / global data clobbering problem which involves having the
gd 'variable' as a register like all other arch's. The solution is
non-trivial and gd access is slightly more expensive than the vanilla
variable approach, but it makes this a lot cleaner cross-arch wise...
Here's a hint ;)
static inline gd_t *get_fs_gd_ptr(void)
{
gd_t *gd_ptr;
asm volatile(fs movl 0, %0\n : =r (gd_ptr));
return gd_ptr;
}
#define gd get_fs_gd_ptr()
On 28/12/11 17:35, Simon Glass wrote:
This series creates a generic board.c implementation which contains
the essential functions of the various arch/xxx/lib/board.c files.
What is the motivation for this change?
[snip]
I think that we can all agree that there is strong motivation for change.
However, I think this approach is not the right one - and I think the CFI
driver backs me up. Your plan is to create generic code which you want ALL
arches to cross over to, but you only look to migrate two initially and
migrate the rest 'later'. This is similar to what happened with the CFI
driver, and there are still boards with custom flash.c files which are
completely redundant.
But, creating a single patch-set to migrate everyone in one go is going to
be too massive a job to do in one go, and too prone to introducing breakage.
Yes to some extent. However, my patch basically splits the two
board_init_x() functions into parts, and puts them in a function
table.
I don't think it is a huge job to do this for PowerPC also, and that
seems to be the most feature-full architecture.
Also it does depend on expectations. I would hope that moving an
architecture over would be a fairly small task:
- getting generic relocation working
- adding functions for anything that is missing from board init code
- removing things which don't work on the architecture?
- worrying about differences in ordering between functions
All the functions of board_init_f() and board_init_r() are broken into
separate function calls so that they can easily be included or excluded
for a particular architecture. It also makes it easier to adopt Graeme's
initcall proposal later if desired.
I think we should look at this sooner rather than later. I've shown with
x86 that the init sequence has three distinct phases:
1) Execute in flash using temporary RAM
2) Copy U-Boot from flash to RAM
3) Execute in RAM
My latest work now has all init functions having the same signature (i.e.
void parameter returning int). For x86, there is a little 'magic' that
needs to be done as gd is copied from temporary RAM to SDRAM, but for other
arches using a dedicated register, this is otherwise trivial.
So instead of trying to pluck out something (relocation in this case) from
the molasses of ten different board.c files and having to perform
open-heart surgery on them all to get the code grafted in, I think we
should approach it from the generic init sequence angle.
If we work each individual arch to use a generic init sequence (like the
proposed x86 code) then the init processing naturally falls out as common
code and the patch to realise this is trivial. From there, we can start to
pull out common init code like init_baudrate() and hang() and change the
function signatures of the functions that require wrappers and move some
#ifdef's into more appropriate locations - One example in board.c:
Well it seems like a lot of work to refactor each arch/xxx/board.c
file into functions with a function pointer list, then later remove
this code function by function.
My feeling is that with a generic board, it should hopefully be a
fairly small amount of work for someone familiar with an architecture
to find the bugs and patch the generic code to suit their
architecture. It is something that needs to be done once, not every
time there is a new patch removing (almost) common code.
#ifdef CONFIG_BITBANGMII
int bb_miiphy_init_r(void)
{
bb_miiphy_init();
return 0;
}
#endif
Ouch!
The other big benefit is that you only touch one architecture at a time up
until you 'pull the switch'. And when you do pull the switch, you should be
factoring out identical code so the chances of breaking something should be
vastly reduced. Take a look at the history of ARM relocation for example -
that was constrained to one arch but still the amount of breakage was massive.
From previous discussions, if something is optional then the switch
will never happen. The code you are talking about is sometimes
identical, sometimes slightly different. In some cases the order is
different. I see many ways of introducing breakages. I do agree that
doing one architecture at a time is best - with the proviso that we
need to pick
[U-Boot] [PATCH 85xx-next 2/8] sbc8548: relocate 64MB user flash to sane boundary
The current situation has the 64MB user flash at an awkward
alignment; shifted back from 0xfc00_ by 8M, to leave an 8MB hole
for the soldered on boot flash @ EOM. But to switch to optionally
supporting booting off the 64MB flash, the 64MB will then be mapped
at the sane address of 0xfc00_.
This leads to awkward things when programming the 64MB flash prior
to transitioning to it -- i.e. even though the chip spans from
0xfb80_ to 0xff7f_, you would have to program a u-boot image
into the two sectors from 0xfbf0_ -- 0xfbff_ so that it was
in the right place when JP12/SW2.8 were switched to make the 64MB on
/CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_)
We also have to have three TLB entries responsible for dealing with
mapping the 64MB flash due to this 8MB of misalignment.
In the end, there is address space from 0xec00_ to 0xefff_
where we can map it, and then the transition from booting from one
config to the other will be a simple 0xec -- 0xfc mapping. Plus we
can toss out a TLB entry.
Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot
flash; this means we won't have to change it when the alternate
config uses the full 64MB for booting, in TLB0.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/law.c |3 ++-
board/sbc8548/tlb.c | 23 ---
doc/README.sbc8548|8 +++-
include/configs/sbc8548.h | 10 +-
4 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index 5fa9db0..febb682 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -36,9 +36,9 @@
* 0xe000_ 0xe000_ CCSR1M
* 0xe200_ 0xe27f_ PCI1 IO 8M
* 0xe280_ 0xe2ff_ PCIe IO 8M
+ * 0xec00_ 0xefff_ FLASH (2nd bank)64M
* 0xf000_ 0xf7ff_ SDRAM 128M
* 0xf8b0_ 0xf80f_ EEPROM 1M
- * 0xfb80_ 0xff7f_ FLASH (2nd bank)64M
* 0xff80_ 0x_ FLASH (boot bank) 8M
*
* Notes:
@@ -47,6 +47,7 @@
*/
struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index bb4c052..e9cedc7 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -46,12 +46,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
/*
* TLB 0: 64M Non-cacheable, guarded
-* 0xfc00 56M 8MB - 64MB of user flash
+* 0xfc00 56M unused
* 0xff80 8M boot FLASH
+* or
+* 0xfc00 64M user flash
+*
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x80,
- CONFIG_SYS_ALT_FLASH + 0x80,
+ SET_TLB_ENTRY(1, 0xfc00, 0xfc00,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
@@ -103,21 +105,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 5, BOOKE_PAGESZ_16M, 1),
/*
-* TLB 6: 4M Non-cacheable, guarded
-* 0xfb80 4M 1st 4MB block of 64MB user FLASH
+* TLB 6: 64M Non-cacheable, guarded
+* 0xec00 64M 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_4M, 1),
-
- /*
-* TLB 7: 4M Non-cacheable, guarded
-* 0xfbc0 4M 2nd 4MB block of 64MB user FLASH
-*/
- SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x40,
- CONFIG_SYS_ALT_FLASH + 0x40,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_4M, 1),
+ 0, 6, BOOKE_PAGESZ_64M, 1),
};
diff --git a/doc/README.sbc8548 b/doc/README.sbc8548
index 6cbe12f..5fa9c93 100644
--- a/doc/README.sbc8548
+++ b/doc/README.sbc8548
@@ -100,6 +100,9 @@ Boot flash:
Sodimm flash:
intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_
+ Note that this address reflects the default setting for
+ the JTAG debugging tools, but since the alignment is
+ rather inconvenient, u-boot puts it at 0xec00_.
Jumpers:
@@ -187,9 +190,12 @@ start end CSn width Desc.
_ 0fff_ MCS0,1 64 DDR2 (256MB)
f000_ f7ff_ CS3,4 32 LB SDRAM (128MB)
f800_ f8b0_1fff CS5 - EPLD
-fb80_ ff7f_ CS6 32 SODIMM flash (64MB)
+fb80_
[U-Boot] [PATCH 85xx-next 1/8] Revert SBC8548: fix address mask to allow 64M flash
This reverts commit ccf1ad535ae1c0dc2d466235c668adbdfe3a55b7.
The commit SBC8548: fix address mask to allow 64M flash
essentially made this change:
* OR6:
- *Addr Mask = 64M = OR6[0:16] = 1100 0
+ *Addr Mask = 64M = OR6[0:16] = 1000 0
But this makes no sense, as section 13.3.1.2.1 in the
MPC8548ERM v2 clearly indicates the masks:
__1000__0 8 Mbytes
_1100___0 64 Mbytes
_1000___0 128 Mbytes
So the original value was correct, and the commit was invalid,
causing a 128MB mapping for a 64MB flash device. The problem
rears its head when trying to configure u-boot to have access
to both flash, since the default memory map is:
FB80_ – FF7F_ 32-bits 64MB FLASH SODIMM
FF80_ – _ 8-bits 8MB FLASH
By extending the mapping of the 64MB flash to 128MB, it now
conflicts with the normal 8MB boot flash, causing issues.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
include/configs/sbc8548.h |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index ba7612c..7c26207 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -173,7 +173,7 @@
* 1000 0110 1110 0110 0101 = ff806e65OR0
*
* OR6:
- *Addr Mask = 64M = OR6[0:16] = 1000 0
+ *Addr Mask = 64M = OR6[0:16] = 1100 0
*XAM = OR6[17:18] = 11
*CSNT = OR6[20] = 1
*ACS = half cycle delay = OR6[21:22] = 11
@@ -182,7 +182,7 @@
*EAD = use external address latch delay = OR6[31] = 1
*
* 04812 16 20 24 28
- * 1000 0110 1110 0110 0101 = f8006e65OR6
+ * 1100 0110 1110 0110 0101 = fc006e65OR6
*/
#define CONFIG_SYS_BOOT_BLOCK 0xff80 /* start of 8MB Flash */
@@ -193,7 +193,7 @@
#define CONFIG_SYS_BR6_PRELIM 0xfb801801
#defineCONFIG_SYS_OR0_PRELIM 0xff806e65
-#defineCONFIG_SYS_OR6_PRELIM 0xf8006e65
+#defineCONFIG_SYS_OR6_PRELIM 0xfc006e65
#define CONFIG_SYS_FLASH_BANKS_LIST{CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_ALT_FLASH}
--
1.7.4.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 85xx-next 0/8] Updates for Wind River sbc8548 board
This updates the sbc8548 board support with several improvements for the end users. -ability to use SPD DDR config for easy RAM upgrades -ability to use alternate SODIMM flash for backup u-boot image -localbus config settings fixed so 128MB LBC SDRAM works reliably The discovery of a hardware errata (overlapping I2C SPD addresses) is at the core of what now allows the use of SPD configuration. The relocation of the 64MB user flash is to align it on a 64MB boundary, which simplifies a whole lot of things, both in the code and for the end user. (The previous mapping meant the last sector on the chip wasn't consistently the last sector in the address space assigned to the chip for all jumper configurations.) Reverting a bogus commit from the past that incorrectly set the windows for the 64MB flash to 128MB was the starting point for getting this all working. Paul. --- The following changes since commit cba9a894fdb1cb49b60fcd1d1d6919cbd7995dd5: Prepare v2011.12 (2011-12-23 20:25:35 +0100) are available in the git repository at: git://openlinux.windriver.com/people/paulg/u-boot sbc8548-Dec30_2011 Paul Gortmaker (8): Revert SBC8548: fix address mask to allow 64M flash sbc8548: relocate 64MB user flash to sane boundary sbc8548: enable ability to boot from alternate flash sbc8548: Fix LBC SDRAM initialization settings sbc8548: Make enabling SPD RAM configuration work sbc8548: relocate fixed ddr init code to ddr.c file sbc8548: enable support for hardware SPD errata workaround sbc8548: Fix up local bus init to be frequency aware board/sbc8548/ddr.c | 77 +++ board/sbc8548/law.c | 16 +- board/sbc8548/sbc8548.c | 111 +++-- board/sbc8548/tlb.c | 24 ++-- doc/README.sbc8548| 79 ++-- include/configs/sbc8548.h | 151 +++-- 6 files changed, 355 insertions(+), 103 deletions(-) -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 85xx-next 4/8] sbc8548: Fix LBC SDRAM initialization settings
These were cloned from the mpc8548cds platform which has
a different memory layout (1/2 the size). Set the values
by comparing to the register file for the board used during
JTAG init sequence:
LSDMR1 0x2863B727 /* PCHALL */
LSDMR2 0x0863B727 /* NORMAL */
LSDMR3 0x1863B727 /* MRW*/
LSDMR4 0x4063B727 /* RFEN */
This differs from what was there already in that the RFEN is
not bundled in all four steps implicitly, but issued once
as the final step.
The other difference seen when comparing vs. the register file init,
is that since the memory is split across /CS3 and /CS4, the dummy
writes need to go to 0xf000_ _and_ to 0xf400_.
We also rewrite the final LBC SDRAM inits as macros, as there is
no real need for them to be a local variable that is modified
on the fly at runtime.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/sbc8548.c | 29 -
include/configs/sbc8548.h | 21 ++---
2 files changed, 30 insertions(+), 20 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 63d504d..96554b2 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -107,13 +107,14 @@ void lbc_sdram_init(void)
#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx;
+ const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
- uint lsdmr_common;
+ uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
puts(SDRAM: );
- print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, \n);
+ print_size(size, \n);
/*
* Setup SDRAM Base and Option Registers
@@ -131,47 +132,49 @@ void lbc_sdram_init(void)
asm(msync);
/*
-* MPC8548 uses new 15-16 style addressing.
-*/
- lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
- lsdmr_common |= LSDMR_BSMA1516;
-
- /*
* Issue PRECHARGE ALL command.
*/
- out_be32(lbc-lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
+ out_be32(lbc-lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
asm(sync;msync);
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
udelay(100);
/*
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx 8; idx++) {
- out_be32(lbc-lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
+ out_be32(lbc-lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
asm(sync;msync);
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
udelay(100);
}
/*
* Issue 8 MODE-set command.
*/
- out_be32(lbc-lsdmr, lsdmr_common | LSDMR_OP_MRW);
+ out_be32(lbc-lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
asm(sync;msync);
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
udelay(100);
/*
-* Issue NORMAL OP command.
+* Issue RFEN command.
*/
- out_be32(lbc-lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
+ out_be32(lbc-lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
asm(sync;msync);
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
udelay(200);/* Overkill. Must wait 200 bus cycles */
#endif /* enable SDRAM init */
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index fb07d09..1df2225 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -362,19 +362,26 @@
/*
* Common settings for all Local Bus SDRAM commands.
- * At run time, either BSMA1516 (for CPU 1.1)
- * or BSMA1617 (for CPU 1.0) (old)
- * is OR'ed in too.
*/
#define CONFIG_SYS_LBC_LSDMR_COMMON( LSDMR_RFCR16 \
- | LSDMR_PRETOACT7 \
- | LSDMR_ACTTORW7\
+ | LSDMR_BSMA1516\
+ | LSDMR_PRETOACT3 \
+ | LSDMR_ACTTORW3\
+ | LSDMR_BUFCMD \
| LSDMR_BL8 \
- | LSDMR_WRC4\
+ | LSDMR_WRC2\
| LSDMR_CL3 \
- | LSDMR_RFEN\
)
+#define CONFIG_SYS_LBC_LSDMR_PCHALL\
+
[U-Boot] [PATCH 85xx-next 3/8] sbc8548: enable ability to boot from alternate flash
This board has an 8MB soldered on flash, and a 64MB SODIMM
flash module. Normally the board boots from the 8MB flash,
but the hardware can be configured for booting from the 64MB
flash as well by swapping CS0 and CS6. This can be handy
for recovery purposes, or for supporting u-boot and VxBoot
at the same time.
To support this in u-boot, we need to have different BR0/OR0
and BR6/OR6 settings in place for when the board is configured
in this way, and a different TEXT_BASE needs to be used due
to the larger sector size of the 64MB flash module.
We introduce the suffix _8M and _64M for the BR0/BR6 and the
OR0/OR6 values so it is clear which is being used to map what
specific device.
The larger sector size (512k) of the alternate flash needs
a larger malloc pool, otherwise you'll get failures when
running saveenv, so bump it up accordingly.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/law.c |8 +++
board/sbc8548/sbc8548.c |2 +-
board/sbc8548/tlb.c | 19
doc/README.sbc8548| 34 +--
include/configs/sbc8548.h | 106 +++-
5 files changed, 142 insertions(+), 27 deletions(-)
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index febb682..c263191 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -41,13 +41,21 @@
* 0xf8b0_ 0xf80f_ EEPROM 1M
* 0xff80_ 0x_ FLASH (boot bank) 8M
*
+ * If swapped CS0/CS6 via JP12+SW2.8:
+ * 0xef80_ 0xefff_ FLASH (2nd bank)8M
+ * 0xfc00_ 0x_ FLASH (boot bank) 64M
+ *
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
struct law_entry law_table[] = {
+#ifdef CONFIG_SYS_ALT_BOOT
+ SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
+#else
SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#endif
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 26095a5..63d504d 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -113,7 +113,7 @@ void lbc_sdram_init(void)
puts(SDRAM: );
- print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, \n);
+ print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, \n);
/*
* Setup SDRAM Base and Option Registers
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index e9cedc7..4bf7214 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -104,6 +104,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_16M, 1),
+#ifndef CONFIG_SYS_ALT_BOOT
/*
* TLB 6: 64M Non-cacheable, guarded
* 0xec00 64M 64MB user FLASH
@@ -111,6 +112,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
+#else
+ /*
+* TLB 6: 4M Non-cacheable, guarded
+* 0xef80 4M 1st 1/2 8MB soldered FLASH
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_4M, 1),
+
+ /*
+* TLB 7: 4M Non-cacheable, guarded
+* 0xefc0 4M 2nd half 8MB soldered FLASH
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x40,
+ CONFIG_SYS_ALT_FLASH + 0x40,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_4M, 1),
+#endif
};
diff --git a/doc/README.sbc8548 b/doc/README.sbc8548
index 5fa9c93..e6b8abe 100644
--- a/doc/README.sbc8548
+++ b/doc/README.sbc8548
@@ -86,6 +86,33 @@ The md steps in the above are just a precautionary step
that allow
you to confirm the u-boot version that was downloaded, and then confirm
that it was copied to flash.
+The above assumes that you are using the default board settings which
+have u-boot in the 8MB flash, tied to /CS0.
+
+If you are running the default 8MB /CS0 settings but want to store an
+image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
+(as a backup, etc) then the steps will become:
+
+ tftp u-boot.bin
+ md 20 10
+ protect off all
+ era eff0 efff
+ cp.b 20 eff0 10
+ md eff0 10
+ protect on all
+
+Finally, if you are running the alternate 64MB /CS0 settings and want
+to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT
+enabled) the steps will become:
+
+ tftp u-boot.bin
+
[U-Boot] [PATCH 85xx-next 8/8] sbc8548: Fix up local bus init to be frequency aware
The code here was copied from the mpc8548cds support, and it
wasn't using the CONFIG_SYS_LBC_LCRR define, and was just
unconditionally setting the LCRR_EADC bit. Snooping with a
hardware debugger also showed we had LCRR_DBYP set, since we were
setting it based on a read of an uninitialized lcrr read via
clkdiv. Borrow from the code in the tqm85xx.c support to add
LBC frequency aware masking of these bits.
This change will correct reliability issues associated with trying
to use the 128MB of LBC 100MHz SDRAM on this board. Thanks to
Keith Savage for assistance in diagnosing the root cause of this.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/sbc8548.c | 38 +++---
1 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index d1ef3be..371d076 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -76,11 +76,15 @@ local_bus_init(void)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- uint clkdiv;
+ uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
sys_info_t sysinfo;
get_sys_info(sysinfo);
- clkdiv = (in_be32(lbc-lcrr) LCRR_CLKDIV) * 2;
+
+ lbc_mhz = sysinfo.freqLocalBus / 100;
+ clkdiv = sysinfo.freqSystemBus / sysinfo.freqLocalBus;
+
+ debug(LCRR=0x%x, CD=%d, MHz=%d\n, lcrr, clkdiv, lbc_mhz);
out_be32(gur-lbiuiplldcr1, 0x00078080);
if (clkdiv == 16) {
@@ -91,10 +95,38 @@ local_bus_init(void)
out_be32(gur-lbiuiplldcr0, 0x5c0f1bf0);
}
- setbits_be32(lbc-lcrr, 0x0003);
+ /*
+* Local Bus Clock 83.3 MHz. According to timing
+* specifications set LCRR[EADC] to 2 delay cycles.
+*/
+ if (lbc_mhz 83) {
+ lcrr = ~LCRR_EADC;
+ lcrr |= LCRR_EADC_2;
+ }
+
+ /*
+* According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
+* disable PLL bypass for Local Bus Clock 83 MHz.
+*/
+ if (lbc_mhz = 66)
+ lcrr = (~LCRR_DBYP); /* DLL Enabled */
+
+ else
+ lcrr |= LCRR_DBYP; /* DLL Bypass */
+ out_be32(lbc-lcrr, lcrr);
asm(sync;isync;msync);
+/*
+* According to MPC8548ERMAD Rev.1.3 read back LCRR
+* and terminate with isync
+*/
+ lcrr = in_be32(lbc-lcrr);
+ asm (isync;);
+
+ /* let DLL stabilize */
+ udelay(500);
+
out_be32(lbc-ltesr, 0x); /* Clear LBC error IRQs */
out_be32(lbc-lteir, 0x); /* Enable LBC error IRQs */
}
--
1.7.4.4
___
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[U-Boot] [PATCH 85xx-next 6/8] sbc8548: relocate fixed ddr init code to ddr.c file
Nothing to see here, just a relocation of the fixed ddr init
sequence to live in the actual ddr.c file itself.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/ddr.c | 48 +
board/sbc8548/sbc8548.c | 44 -
include/configs/sbc8548.h |1 +
3 files changed, 49 insertions(+), 44 deletions(-)
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index 996ffe2..0d9a1ba 100644
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -54,3 +54,51 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
popts-half_strength_driver_enable = 0;
}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * fixed_sdram init -- doesn't use serial presence detect.
+ * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
+ */
+phys_size_t fixed_sdram(void)
+{
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+
+ out_be32(ddr-cs0_bnds,0x007f);
+ out_be32(ddr-cs1_bnds,0x008000ff);
+ out_be32(ddr-cs2_bnds,0x);
+ out_be32(ddr-cs3_bnds,0x);
+
+ out_be32(ddr-cs0_config, 0x80010101);
+ out_be32(ddr-cs1_config, 0x80010101);
+ out_be32(ddr-cs2_config, 0x);
+ out_be32(ddr-cs3_config, 0x);
+
+ out_be32(ddr-timing_cfg_3,0x);
+ out_be32(ddr-timing_cfg_0,0x00220802);
+ out_be32(ddr-timing_cfg_1,0x38377322);
+ out_be32(ddr-timing_cfg_2,0x0fa044C7);
+
+ out_be32(ddr-sdram_cfg, 0x4300C000);
+ out_be32(ddr-sdram_cfg_2, 0x24401000);
+
+ out_be32(ddr-sdram_mode, 0x23C00542);
+ out_be32(ddr-sdram_mode_2,0x);
+
+ out_be32(ddr-sdram_interval, 0x05080100);
+ out_be32(ddr-sdram_md_cntl, 0x);
+ out_be32(ddr-sdram_data_init, 0x);
+ out_be32(ddr-sdram_clk_cntl, 0x0380);
+ asm(sync;isync;msync);
+ udelay(500);
+
+ #ifdef CONFIG_DDR_ECC
+ /* Enable ECC checking */
+ out_be32(ddr-sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x2000);
+ #else
+ out_be32(ddr-sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+ #endif
+
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 96554b2..d1ef3be 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -219,50 +219,6 @@ testdram(void)
}
#endif
-#if !defined(CONFIG_SPD_EEPROM)
-#define CONFIG_SYS_DDR_CONTROL 0xc300c000
-/*
- * fixed_sdram init -- doesn't use serial presence detect.
- * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
- /
-phys_size_t fixed_sdram(void)
-{
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-
- out_be32(ddr-cs0_bnds, 0x007f);
- out_be32(ddr-cs1_bnds, 0x008000ff);
- out_be32(ddr-cs2_bnds, 0x);
- out_be32(ddr-cs3_bnds, 0x);
- out_be32(ddr-cs0_config, 0x80010101);
- out_be32(ddr-cs1_config, 0x80010101);
- out_be32(ddr-cs2_config, 0x);
- out_be32(ddr-cs3_config, 0x);
- out_be32(ddr-timing_cfg_3, 0x);
- out_be32(ddr-timing_cfg_0, 0x00220802);
- out_be32(ddr-timing_cfg_1, 0x38377322);
- out_be32(ddr-timing_cfg_2, 0x0fa044C7);
- out_be32(ddr-sdram_cfg, 0x4300C000);
- out_be32(ddr-sdram_cfg_2, 0x24401000);
- out_be32(ddr-sdram_mode, 0x23C00542);
- out_be32(ddr-sdram_mode_2, 0x);
- out_be32(ddr-sdram_interval, 0x05080100);
- out_be32(ddr-sdram_md_cntl, 0x);
- out_be32(ddr-sdram_data_init, 0x);
- out_be32(ddr-sdram_clk_cntl, 0x0380);
- asm(sync;isync;msync);
- udelay(500);
-
- #if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- out_be32(ddr-sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x2000);
- #else
- out_be32(ddr-sdram_cfg, CONFIG_SYS_DDR_CONTROL);
- #endif
-
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif
-
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI1 */
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 44c7526..09245b5 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -148,6 +148,7 @@
*/
#ifndef CONFIG_SPD_EEPROM
#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
+ #define CONFIG_SYS_DDR_CONTROL 0xc300c000
#endif
#undef CONFIG_CLOCKS_IN_MHZ
--
1.7.4.4
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[U-Boot] [PATCH 85xx-next 7/8] sbc8548: enable support for hardware SPD errata workaround
Existing boards by default have an issue where the LBC SDRAM
SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51.
After the hardware modification listed in the README is made,
then the DDR2 SPD EEPROM appears at 0x53. So this implements
a board specific get_spd() by taking advantage of the existing
weak linkage, that 1st tries reading at 0x53 and then if that
fails, it falls back to the old 0x51.
Since the old dependency issue of SPD implies no LBC SDRAM
gets removed with the hardware errata fix, remove that restriction
in the code, so both LBC SDRAM and SPD can be selected.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/ddr.c | 31 ++-
doc/README.sbc8548| 20 ++--
include/configs/sbc8548.h | 14 ++
3 files changed, 58 insertions(+), 7 deletions(-)
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index 0d9a1ba..45ec485 100644
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -7,6 +7,7 @@
*/
#include common.h
+#include i2c.h
#include asm/fsl_ddr_sdram.h
#include asm/fsl_ddr_dimm_params.h
@@ -55,7 +56,35 @@ void fsl_ddr_board_options(memctl_options_t *popts,
popts-half_strength_driver_enable = 0;
}
-#if !defined(CONFIG_SPD_EEPROM)
+#ifdef CONFIG_SPD_EEPROM
+/*
+ * Workaround for hardware errata. An i2c address conflict
+ * existed on earlier boards; the workaround moved the DDR
+ * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and
+ * if that fails, then fall back to reading at 0x51.
+ */
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+ int ret;
+
+#ifdef ALT_SPD_EEPROM_ADDRESS
+ if (i2c_address == SPD_EEPROM_ADDRESS) {
+ ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
+ if (ret == 0)
+ return; /* Good data at 0x53 */
+ memset(spd, 0, sizeof(generic_spd_eeprom_t));
+ }
+#endif
+ ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
+ if (ret) {
+ printf(DDR: failed to read SPD from addr %u\n, i2c_address);
+ memset(spd, 0, sizeof(generic_spd_eeprom_t));
+ }
+}
+
+#else
/*
* fixed_sdram init -- doesn't use serial presence detect.
* Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
diff --git a/doc/README.sbc8548 b/doc/README.sbc8548
index f9e2dea..0f3f543 100644
--- a/doc/README.sbc8548
+++ b/doc/README.sbc8548
@@ -71,7 +71,22 @@ EEPROM data to read what memory is installed.
There is a hardware errata, which causes the older local bus SDRAM
SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
-that the SPD data can not be read reliably.
+that the SPD data can not be read reliably. You can test if your
+board has the errata fix by running i2c probe. If you see 0x53
+as a valid device, it has been fixed. If you only see 0x50, 0x51
+then your board does not have the fix.
+
+You can also visually inspect the board to see if this hardware
+fix has been applied:
+
+ 1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
+ the back of the PCB behind the DDR SDRAM SODIMM connector.
+ 2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
+ to R313 pin 2. Pin 2 for each resistor is the end of the
+ resistor closest to the CPU.
+
+Boards without the mod will have R314 and R313 in parallel, like ||.
+After the mod, they will be touching and form an L shape.
If you want to upgrade to larger RAM size, you can simply enable
#define CONFIG_SPD_EEPROM
@@ -79,7 +94,8 @@ If you want to upgrade to larger RAM size, you can simply
enable
in include/configs/sbc8548.h file. (The lines are already there
but listed as #undef).
-Note that you will have to physically remove the LBC 128MB DIMM
+If you did the i2c test, and your board does not have the errata
+fix, then you will have to physically remove the LBC 128MB DIMM
from the board's socket to resolve the above i2c address overlap
issue and allow SPD autodetection of RAM to work.
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 09245b5..d87394c 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -124,7 +124,9 @@
* A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
* to collide, meaning you couldn't reliably read either. So
* physically remove the LBC PC100 SDRAM module from the board
- * before enabling the two SPD options below.
+ * before enabling the two SPD options below, or check that you
+ * have the hardware fix on your board via i2c probe and looking
+ * for a device at 0x53.
*/
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_SPD
@@ -140,8 +142,13 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define
[U-Boot] [PATCH 85xx-next 5/8] sbc8548: Make enabling SPD RAM configuration work
Previously, SPD configuration of RAM was non functional on
this board. Now that the root cause is known (an i2c address
conflict), there is a simple end-user workaround - remove the
old slower local bus 128MB module and then SPD detection on the
main DDR2 memory module works fine.
We make the enablement of the LBC SDRAM support conditional on
being not SPD enabled. We can revisit this dependency as the
hardware workaround becomes available.
Turning off LBC SDRAM support revealed a couple implict dependencies
in the tlb/law code that always expected an LBC SDRAM address.
This has been tested with the default 256MB module, a 512MB
a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration
worked fine in all cases.
The default configuration remains to go with the hard coded
DDR config, so the default build will continue to work on boards
where people don't bother to read the docs. But the advantage
of going to the SPD config is that even the small default module
gets configured for CL3 instead of CL4.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/law.c |5 +
board/sbc8548/tlb.c |2 ++
doc/README.sbc8548| 21 +
include/configs/sbc8548.h | 13 -
4 files changed, 40 insertions(+), 1 deletions(-)
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index c263191..322af76 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -59,8 +59,13 @@ struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
/* LBC window - maps 256M 0xf000 - 0x */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#else
+ /* LBC window - maps 128M 0xf800 - 0x */
+ SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index 4bf7214..af927f1 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -76,6 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_64M, 1),
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
/*
* TLB 3: 64M Cacheable, non-guarded
* 0xf000 64M LBC SDRAM First half
@@ -92,6 +93,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
CONFIG_SYS_LBC_SDRAM_BASE + 0x400,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 4, BOOKE_PAGESZ_64M, 1),
+#endif
/*
* TLB 5: 16M Cacheable, non-guarded
diff --git a/doc/README.sbc8548 b/doc/README.sbc8548
index e6b8abe..f9e2dea 100644
--- a/doc/README.sbc8548
+++ b/doc/README.sbc8548
@@ -62,6 +62,27 @@ a 33MHz PCI configuration is currently untested.)
02.00.00 0x1148 0x9e00 Network controller 0x00
=
+Memory Size and using SPD:
+==
+
+The default configuration uses hard coded memory configuration settings
+for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD
+EEPROM data to read what memory is installed.
+
+There is a hardware errata, which causes the older local bus SDRAM
+SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
+that the SPD data can not be read reliably.
+
+If you want to upgrade to larger RAM size, you can simply enable
+ #define CONFIG_SPD_EEPROM
+ #define CONFIG_DDR_SPD
+in include/configs/sbc8548.h file. (The lines are already there
+but listed as #undef).
+
+Note that you will have to physically remove the LBC 128MB DIMM
+from the board's socket to resolve the above i2c address overlap
+issue and allow SPD autodetection of RAM to work.
+
Updating U-boot with U-boot:
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 1df2225..44c7526 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -119,9 +119,15 @@
/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+/*
+ * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
+ * to collide, meaning you couldn't reliably read either. So
+ * physically remove the LBC PC100 SDRAM module from the board
+ * before enabling the two SPD options below.
+ */
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_SPD
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
@@ -283,9 +289,14 @@
/*
* SDRAM on the Local Bus (CS3 and CS4)
+ * Note that most boards have a hardware errata where both the
+ * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
+ *
