[U-Boot] [PATCH v2] Introduce a new linker flag LDFLAGS_FINAL
From: Haiying Wang haiying.w...@freescale.com commit 8aba9dceebb14144e07d19593111ee3a999c37fc Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS breaks the usage of --gc-section to build nand_spl. We still need linker option --gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes the --gc-sections to each uboot image. Because we add PLATFORM_FLAGS to LDFLAGS_FINAL via LDFLAGS in toplevel config.mk , we use LDFLAGS_FINAL to replace the PLATFORM_LDFLAGS in the Makefile of each nand_spl board. Signed-off-by: Scott Wood scottw...@freescale.com Signed-off-by: Haiying Wang haiying.w...@freescale.com --- v2: make changes based on the current top of the tree. arch/blackfin/config.mk |2 +- arch/i386/config.mk |2 +- arch/nios2/config.mk |2 +- arch/powerpc/config.mk|2 +- arch/sh/config.mk |2 +- config.mk |3 ++- nand_spl/board/amcc/acadia/Makefile |2 +- nand_spl/board/amcc/bamboo/Makefile |2 +- nand_spl/board/amcc/canyonlands/Makefile |2 +- nand_spl/board/amcc/kilauea/Makefile |2 +- nand_spl/board/amcc/sequoia/Makefile |2 +- nand_spl/board/davinci/da8xxevm/Makefile |2 +- nand_spl/board/freescale/mpc8313erdb/Makefile |4 ++-- nand_spl/board/freescale/mpc8315erdb/Makefile |4 ++-- nand_spl/board/freescale/mpc8536ds/Makefile |2 +- nand_spl/board/freescale/mpc8569mds/Makefile |2 +- nand_spl/board/freescale/mpc8572ds/Makefile |2 +- nand_spl/board/freescale/mx31pdk/Makefile |2 +- nand_spl/board/freescale/p1_p2_rdb/Makefile |3 ++- nand_spl/board/karo/tx25/Makefile |2 +- nand_spl/board/samsung/smdk6400/Makefile |2 +- nand_spl/board/sheldon/simpc8313/Makefile |4 ++-- 22 files changed, 27 insertions(+), 25 deletions(-) diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index 0cba294..f4503ea 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -30,7 +30,7 @@ CONFIG_BFIN_BOOT_MODE := $(strip $(subst ,,$(CONFIG_BFIN_BOOT_MODE))) PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -LDFLAGS_u-boot += --gc-sections +LDFLAGS_FINAL += --gc-sections LDFLAGS += -m elf32bfin PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/i386/config.mk b/arch/i386/config.mk index a84af63..67aac0d 100644 --- a/arch/i386/config.mk +++ b/arch/i386/config.mk @@ -38,6 +38,6 @@ PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions -LDFLAGS_u-boot += --gc-sections -pie +LDFLAGS_FINAL += --gc-sections -pie LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index fa93180..d241a96 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -31,5 +31,5 @@ PLATFORM_CPPFLAGS += -G0 LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds -LDFLAGS_u-boot += --gc-sections +LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 64191c7..31e4416 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -24,7 +24,7 @@ CROSS_COMPILE ?= ppc_8xx- STANDALONE_LOAD_ADDR = 0x4 -LDFLAGS_u-boot = --gc-sections +LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -mrelocatable -ffunction-sections -fdata-sections PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ PLATFORM_LDFLAGS += -n diff --git a/arch/sh/config.mk b/arch/sh/config.mk index 433cc15..48393b5 100644 --- a/arch/sh/config.mk +++ b/arch/sh/config.mk @@ -30,7 +30,7 @@ endif PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE) -LDFLAGS_u-boot = --gc-sections +LDFLAGS_FINAL = --gc-sections ifdef CONFIG_SYS_LDSCRIPT LDSCRIPT := $(subst ,,$(CONFIG_SYS_LDSCRIPT)) diff --git a/config.mk b/config.mk index 5147c35..caa6221 100644 --- a/config.mk +++ b/config.mk @@ -205,8 +205,9 @@ endif AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) LDFLAGS += $(PLATFORM_LDFLAGS) +LDFLAGS_FINAL += -Bstatic $(LDFLAGS) -LDFLAGS_u-boot += -Bstatic -T $(obj)u-boot.lds $(PLATFORM_LDFLAGS) +LDFLAGS_u-boot += -T $(obj)u-boot.lds $(LDFLAGS_FINAL) ifneq ($(CONFIG_SYS_TEXT_BASE),) LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) endif diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile index f8ca654..8799457 100644 --- a/nand_spl/board/amcc/acadia/Makefile +++ b/nand_spl/board/amcc/acadia/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS=
[U-Boot] [PATCH v3] Introduce a new linker flag LDFLAGS_FINAL
From: Haiying Wang haiying.w...@freescale.com commit 8aba9dceebb14144e07d19593111ee3a999c37fc Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS breaks the usage of --gc-section to build nand_spl. We still need linker option --gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes the --gc-sections to each uboot image. To get the proper linker flags, we use LDFLAGS and LDFLAGS_FINAL to replace PLATFORM_LDFLAGS in the Makefile of each nand_spl board. Signed-off-by: Scott Wood scottw...@freescale.com Signed-off-by: Haiying Wang haiying.w...@freescale.com --- v3: remove LDFLAGS from LDFLAGS_FINAL since it is already in LDFLAGS_u-boot, and add LDFLAGS to each nand_spl board's LDFLAGS arch/blackfin/config.mk |2 +- arch/i386/config.mk |2 +- arch/nios2/config.mk |2 +- arch/powerpc/config.mk|2 +- arch/sh/config.mk |2 +- config.mk |3 ++- nand_spl/board/amcc/acadia/Makefile |3 ++- nand_spl/board/amcc/bamboo/Makefile |3 ++- nand_spl/board/amcc/canyonlands/Makefile |3 ++- nand_spl/board/amcc/kilauea/Makefile |3 ++- nand_spl/board/amcc/sequoia/Makefile |3 ++- nand_spl/board/davinci/da8xxevm/Makefile |3 ++- nand_spl/board/freescale/mpc8313erdb/Makefile |4 ++-- nand_spl/board/freescale/mpc8315erdb/Makefile |4 ++-- nand_spl/board/freescale/mpc8536ds/Makefile |3 ++- nand_spl/board/freescale/mpc8569mds/Makefile |3 ++- nand_spl/board/freescale/mpc8572ds/Makefile |3 ++- nand_spl/board/freescale/mx31pdk/Makefile |3 ++- nand_spl/board/freescale/p1_p2_rdb/Makefile |3 ++- nand_spl/board/karo/tx25/Makefile |3 ++- nand_spl/board/samsung/smdk6400/Makefile |3 ++- nand_spl/board/sheldon/simpc8313/Makefile |4 ++-- 22 files changed, 39 insertions(+), 25 deletions(-) diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index 0cba294..f4503ea 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -30,7 +30,7 @@ CONFIG_BFIN_BOOT_MODE := $(strip $(subst ,,$(CONFIG_BFIN_BOOT_MODE))) PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -LDFLAGS_u-boot += --gc-sections +LDFLAGS_FINAL += --gc-sections LDFLAGS += -m elf32bfin PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/i386/config.mk b/arch/i386/config.mk index a84af63..67aac0d 100644 --- a/arch/i386/config.mk +++ b/arch/i386/config.mk @@ -38,6 +38,6 @@ PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions -LDFLAGS_u-boot += --gc-sections -pie +LDFLAGS_FINAL += --gc-sections -pie LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index fa93180..d241a96 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -31,5 +31,5 @@ PLATFORM_CPPFLAGS += -G0 LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds -LDFLAGS_u-boot += --gc-sections +LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 64191c7..31e4416 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -24,7 +24,7 @@ CROSS_COMPILE ?= ppc_8xx- STANDALONE_LOAD_ADDR = 0x4 -LDFLAGS_u-boot = --gc-sections +LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -mrelocatable -ffunction-sections -fdata-sections PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ PLATFORM_LDFLAGS += -n diff --git a/arch/sh/config.mk b/arch/sh/config.mk index 433cc15..48393b5 100644 --- a/arch/sh/config.mk +++ b/arch/sh/config.mk @@ -30,7 +30,7 @@ endif PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE) -LDFLAGS_u-boot = --gc-sections +LDFLAGS_FINAL = --gc-sections ifdef CONFIG_SYS_LDSCRIPT LDSCRIPT := $(subst ,,$(CONFIG_SYS_LDSCRIPT)) diff --git a/config.mk b/config.mk index 5147c35..d80c02a 100644 --- a/config.mk +++ b/config.mk @@ -205,8 +205,9 @@ endif AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) LDFLAGS += $(PLATFORM_LDFLAGS) +LDFLAGS_FINAL += -Bstatic -LDFLAGS_u-boot += -Bstatic -T $(obj)u-boot.lds $(PLATFORM_LDFLAGS) +LDFLAGS_u-boot += -T $(obj)u-boot.lds $(LDFLAGS_FINAL) ifneq ($(CONFIG_SYS_TEXT_BASE),) LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) endif diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile index f8ca654..f4323d5 100644 --- a/nand_spl/board/amcc/acadia/Makefile +++ b/nand_spl/board/amcc/acadia/Makefile @@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk LDSCRIPT=
[U-Boot] [PATCH 4/4 v2] p1021mds: add QE and UEC support
From: Haiying Wang haiying.w...@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
P1021MDS has to load the microcode from NAND flash, this patchs add support to
load ucode from NAND before initializing qe.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v2: remove misc_init_r, make changes based on laste commits in u-boot-85xx.git
arch/powerpc/cpu/mpc85xx/speed.c |4 ++
arch/powerpc/include/asm/immap_85xx.h | 13
board/freescale/p1021mds/p1021mds.c | 51 +
drivers/qe/uec.c | 40 +-
include/configs/P1021MDS.h| 44
5 files changed, 151 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index f2aa8d0..ae94ee8 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -165,10 +165,14 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
+#ifdef CONFIG_P1021
+ sysInfo-freqQE = sysInfo-freqSystemBus;
+#else
qe_ratio = ((gur-porpllsr) MPC85xx_PORPLLSR_QE_RATIO)
MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo-freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#endif
#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 99ecb83..d0fa79b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1909,6 +1909,19 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SD_DATA 0x8000
#define MPC85xx_PMUXCR_SDHC_CD 0x4000
#define MPC85xx_PMUXCR_SDHC_WP 0x2000
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE1 0x4000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE100x0020
+#define MPC85xx_PMUXCR_QE110x0010
+#define MPC85xx_PMUXCR_QE120x0008
u32 pmuxcr2;/* Alt. function signal multiplex control 2 */
u8 res6[8];
u32 devdisr;/* Device disable control */
diff --git a/board/freescale/p1021mds/p1021mds.c
b/board/freescale/p1021mds/p1021mds.c
index 2dfcf13..29972f8 100644
--- a/board/freescale/p1021mds/p1021mds.c
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -37,6 +37,45 @@
#include tsec.h
#include netdev.h
+#ifdef CONFIG_QE
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC*/
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B*/
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B*/
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B*/
+ {0, 17, 2, 0, 2}, /* ENET1_CRS*/
+ {0, 16, 2, 0, 2}, /* ENET1_COL*/
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B*/
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B*/
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B*/
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
int board_early_init_f(void)
{
@@ -100,6 +139,14 @@ int board_eth_init(bd_t *bis)
tsec_eth_init(bis, tsec_info, num);
+#if defined(CONFIG_UEC_ETH)
+ /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
+
[U-Boot] [PATCH 3/4] powerpc/85xx: load ucode from nand flash before qe_init
From: Haiying Wang haiying.w...@freescale.com
In the case the QE's microcode is stored in nand flash, we need to load it from
NAND flash to ddr first then the qe_init can get the ucode correctly.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 215b7b3..5642cd7 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -37,6 +37,10 @@
#include asm/fsl_law.h
#include asm/fsl_serdes.h
#include mp.h
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#include nand.h
+#include errno.h
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -448,6 +452,19 @@ void cpu_secondary_init_r(void)
{
#ifdef CONFIG_QE
uint qe_base = CONFIG_SYS_IMMR + 0x0008; /* QE immr base */
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+ int ret;
+ size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
+
+ /* load QE firmware from NAND flash to DDR first */
+ ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
+ fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
+
+ if (ret ret == -EUCLEAN) {
+ printf (NAND read for QE firmware at offset %x failed %d\n,
+ CONFIG_SYS_QE_FW_IN_NAND, ret);
+ }
+#endif
qe_init(qe_base);
qe_reset();
#endif
--
1.7.3.1.50.g1e633
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[U-Boot] [PATCH 2/4 v2] powerpc/85xx: Add more P1021 defines
From: Haiying Wang haiying.w...@freescale.com
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v2: re-number the res defines in immap_85xx.h, make changes to P1021 specific
defines based on the latest commit in u-boot-85xx git tree.
arch/powerpc/include/asm/config_mpc85xx.h |4
arch/powerpc/include/asm/immap_85xx.h | 24 +++-
2 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index d7d1fb6..b25cd30 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -125,6 +125,10 @@
#define CONFIG_SYS_FSL_NUM_LAWS12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define QE_MURAM_SIZE 0x6000UL
+#define MAX_QE_RISC1
+#define QE_NUM_OF_SNUM 28
+
#elif defined(CONFIG_P1022)
#define CONFIG_MAX_CPUS2
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 6bd83ba..99ecb83 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1942,29 +1942,35 @@ typedef struct ccsr_gur {
u8 res9[12];
u32 pvr;/* Processor version */
u32 svr;/* System version */
- u8 res10a[8];
+ u8 res10[8];
u32 rstcr; /* Reset control */
#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
- u8 res10b[76];
+ u8 res11a[76];
par_io_t qe_par_io[7];
- u8 res10c[1600];
+ u8 res11b[1600];
+#elif defined(CONFIG_P1021)
+ u8 res11a[12];
+ u32 iovselsr;
+ u8 res11b[60];
+ par_io_t qe_par_io[3];
+ u8 res11c[1496];
#else
- u8 res10b[1868];
+ u8 res11a[1868];
#endif
u32 clkdvdr;/* Clock Divide register */
- u8 res10d[1532];
+ u8 res12[1532];
u32 clkocr; /* Clock out select */
- u8 res11[12];
+ u8 res13[12];
u32 ddrdllcr; /* DDR DLL control */
- u8 res12[12];
+ u8 res14[12];
u32 lbcdllcr; /* LBC DLL control */
- u8 res13[248];
+ u8 res15[248];
u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
u32 ddrioovcr; /* DDR IO Override Control */
u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
- u8 res15[61648];
+ u8 res16[61648];
} ccsr_gur_t;
#endif
--
1.7.3.1.50.g1e633
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[U-Boot] [PATCH] Introduce a new linker flag LDFLAGS_FINAL
From: Haiying Wang haiying.w...@freescale.com commit 8aba9dceebb14144e07d19593111ee3a999c37fc Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS breaks the usage of --gc-section to build nand_spl. We still need linker option --gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes the --gc-sections to each uboot image. Signed-off-by: Scott Wood scottw...@freescale.com Signed-off-by: Haiying Wang haiying.w...@freescale.com --- arch/blackfin/config.mk |2 +- arch/i386/config.mk |2 +- arch/nios2/config.mk |2 +- arch/powerpc/config.mk|2 +- arch/sh/config.mk |2 +- config.mk |3 ++- nand_spl/board/amcc/acadia/Makefile |4 ++-- nand_spl/board/amcc/bamboo/Makefile |4 ++-- nand_spl/board/amcc/canyonlands/Makefile |4 ++-- nand_spl/board/amcc/kilauea/Makefile |4 ++-- nand_spl/board/amcc/sequoia/Makefile |4 ++-- nand_spl/board/davinci/da8xxevm/Makefile |4 ++-- nand_spl/board/freescale/mpc8313erdb/Makefile |6 +++--- nand_spl/board/freescale/mpc8315erdb/Makefile |6 +++--- nand_spl/board/freescale/mpc8536ds/Makefile |4 ++-- nand_spl/board/freescale/mpc8569mds/Makefile |4 ++-- nand_spl/board/freescale/mpc8572ds/Makefile |4 ++-- nand_spl/board/freescale/mx31pdk/Makefile |4 ++-- nand_spl/board/freescale/p1_p2_rdb/Makefile |5 +++-- nand_spl/board/karo/tx25/Makefile |4 ++-- nand_spl/board/samsung/smdk6400/Makefile |4 ++-- nand_spl/board/sheldon/simpc8313/Makefile |6 +++--- 22 files changed, 43 insertions(+), 41 deletions(-) diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index 0cba294..f4503ea 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -30,7 +30,7 @@ CONFIG_BFIN_BOOT_MODE := $(strip $(subst ,,$(CONFIG_BFIN_BOOT_MODE))) PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -LDFLAGS_u-boot += --gc-sections +LDFLAGS_FINAL += --gc-sections LDFLAGS += -m elf32bfin PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/i386/config.mk b/arch/i386/config.mk index 3fb97c1..2848435 100644 --- a/arch/i386/config.mk +++ b/arch/i386/config.mk @@ -36,5 +36,5 @@ PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2) PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ LDFLAGS += --cref -LDFLAGS_u-boot += --gc-sections +LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -ffunction-sections diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index fa93180..d241a96 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -31,5 +31,5 @@ PLATFORM_CPPFLAGS += -G0 LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds -LDFLAGS_u-boot += --gc-sections +LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 64191c7..31e4416 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -24,7 +24,7 @@ CROSS_COMPILE ?= ppc_8xx- STANDALONE_LOAD_ADDR = 0x4 -LDFLAGS_u-boot = --gc-sections +LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -mrelocatable -ffunction-sections -fdata-sections PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ PLATFORM_LDFLAGS += -n diff --git a/arch/sh/config.mk b/arch/sh/config.mk index 4ef85e3..6318e77 100644 --- a/arch/sh/config.mk +++ b/arch/sh/config.mk @@ -30,5 +30,5 @@ endif PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE) -LDFLAGS_u-boot = --gc-sections +LDFLAGS_FINAL += --gc-sections LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/config.mk b/config.mk index 5147c35..caa6221 100644 --- a/config.mk +++ b/config.mk @@ -205,8 +205,9 @@ endif AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) LDFLAGS += $(PLATFORM_LDFLAGS) +LDFLAGS_FINAL += -Bstatic $(LDFLAGS) -LDFLAGS_u-boot += -Bstatic -T $(obj)u-boot.lds $(PLATFORM_LDFLAGS) +LDFLAGS_u-boot += -T $(obj)u-boot.lds $(LDFLAGS_FINAL) ifneq ($(CONFIG_SYS_TEXT_BASE),) LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) endif diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile index f8ca654..92ace9d 100644 --- a/nand_spl/board/amcc/acadia/Makefile +++ b/nand_spl/board/amcc/acadia/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS= -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS) +LDFLAGS_spl := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL @@
[U-Boot] [PATCH 4/6] powerpc/p1021: add more P1021 defines.
From: Haiying Wang haiying.w...@freescale.com
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |6 ++
arch/powerpc/include/asm/immap_qe.h |9 +++--
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 6bd83ba..77e3629 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1948,6 +1948,12 @@ typedef struct ccsr_gur {
u8 res10b[76];
par_io_t qe_par_io[7];
u8 res10c[1600];
+#elif defined(CONFIG_P1021)
+ u8 res10b1[12];
+ u32 iovselsr;
+ u8 res10b2[60];
+ par_io_t qe_par_io[3];
+ u8 res10c[1496];
#else
u8 res10b[1868];
#endif
diff --git a/arch/powerpc/include/asm/immap_qe.h
b/arch/powerpc/include/asm/immap_qe.h
index 531cfc8..0fffba2 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -3,7 +3,7 @@
* The Internal Memory Map for devices with QE on them. This
* is the superset of all QE devices (8360, etc.).
*
- * Copyright (c) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
* Author: Shlomi Gridih grid...@freescale.com
*
* This program is free software; you can redistribute it and/or modify it
@@ -588,6 +588,9 @@ typedef struct qe_immap {
#elif defined(CONFIG_MPC8569)
u8 muram[0x2]; /* 0x1_ - 0x3_ Multi-user RAM */
u8 res17[0x1]; /* 0x3_ - 0x4_ */
+#elif defined(CONFIG_P1021)
+ u8 muram[0x06000]; /* 0x1_ - 0x1_6000 Multi-user RAM */
+ u8 res17[0x1a000]; /* 0x1_6000 - 0x3_ */
#else
u8 muram[0xC000]; /* 0x11 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x14 */
@@ -601,13 +604,15 @@ extern qe_map_t *qe_immr;
#define QE_MURAM_SIZE 0x1UL
#elif defined(CONFIG_MPC8569)
#define QE_MURAM_SIZE 0x2UL
+#elif defined(CONFIG_P1021)
+#define QE_MURAM_SIZE 0x6000UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832x)
#define QE_MURAM_SIZE 0x4000UL
#endif
-#if defined(CONFIG_MPC8323)
+#if defined(CONFIG_MPC8323) || defined(CONFIG_P1021)
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_MPC8569)
--
1.7.3.1.50.g1e633
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[U-Boot] [PATCH 5/6] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash
From: Haiying Wang haiying.w...@freescale.com For some board which doesn't have NOR flash and the QE's firmware(ucode) is saved in its NAND flash, we don't want call qe_init in cpu_init_r, but will call it later after nand is initialized. Signed-off-by: Haiying Wang haiying.w...@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 8ece970..fcf9e7b 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -384,7 +384,7 @@ int cpu_init_r(void) enable_cpc(); -#ifdef CONFIG_QE +#if defined(CONFIG_QE) !defined(CONFIG_SYS_QE_FW_IN_NAND) uint qe_base = CONFIG_SYS_IMMR + 0x0008; /* QE immr base */ qe_init(qe_base); qe_reset(); -- 1.7.3.1.50.g1e633 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
This patchset adds support for TPL(Tertiary Program Loader) and P1021MDS board. It is a rework of patchset at http://lists.denx.de/pipermail/u-boot/2010-December/082881.html, addresses the comments from the list and is based on the top of the tree. It needs to be applied after patch http://lists.denx.de/pipermail/u-boot/2011-January/086346.html and patch http://lists.denx.de/pipermail/u-boot/2011-January/086524.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/6] P1021: add P1021MDS board support
From: Haiying Wang haiying.w...@freescale.com Support P1021MDS board to boot from NAND flash (No NOR flash on this board). And because P1021 only has 256K L2 SRAM, which can not used for final uboot image, this patch also enables the TPL BOOT on P1021MDS so that DDR can be initialized in L2 SRAM through SPD code. So there are three stage uboot images: * nand_spl, pad from 4KB size to 16KB, load tpl_boot from offset 16KB in NAND. * tpl_boot, 112KB size. The env variables are copied to offset 128KB in L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 128KB in NAND. * final uboot image, size is variable depends on the functions enabled. Signed-off-by: Haiying Wang haiying.w...@freescale.com Signed-off-by: Mohit Kumar mohit.ku...@freescale.com Signed-off-by: Yu Liu yu@freescale.com Signed-off-by: Kai Jiang kai.ji...@freescale.com --- MAINTAINERS |4 + board/freescale/p1021mds/Makefile | 52 +++ board/freescale/p1021mds/config.mk| 31 ++ board/freescale/p1021mds/ddr.c| 107 + board/freescale/p1021mds/law.c| 34 ++ board/freescale/p1021mds/p1021mds.c | 133 ++ board/freescale/p1021mds/tlb.c| 102 + boards.cfg|1 + include/configs/P1021MDS.h| 535 + nand_spl/board/freescale/p1021mds/Makefile| 134 ++ nand_spl/board/freescale/p1021mds/nand_boot.c | 69 nand_spl/nand_boot_fsl_elbc.c |6 +- tpl/board/freescale/p1021mds/Makefile | 257 tpl/board/freescale/p1021mds/tpl_boot.c | 79 14 files changed, 1543 insertions(+), 1 deletions(-) create mode 100644 board/freescale/p1021mds/Makefile create mode 100644 board/freescale/p1021mds/config.mk create mode 100644 board/freescale/p1021mds/ddr.c create mode 100644 board/freescale/p1021mds/law.c create mode 100644 board/freescale/p1021mds/p1021mds.c create mode 100644 board/freescale/p1021mds/tlb.c create mode 100644 include/configs/P1021MDS.h create mode 100644 nand_spl/board/freescale/p1021mds/Makefile create mode 100644 nand_spl/board/freescale/p1021mds/nand_boot.c create mode 100644 tpl/board/freescale/p1021mds/Makefile create mode 100644 tpl/board/freescale/p1021mds/tpl_boot.c diff --git a/MAINTAINERS b/MAINTAINERS index edd1c5c..da1b2a3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17,6 +17,10 @@ # Board CPU # # +Haiying Wang haiying.w...@freescale.com + + P1021MDSP1021 + Poonam Aggrwal poonam.aggr...@freescale.com P2020RDBP2020 diff --git a/board/freescale/p1021mds/Makefile b/board/freescale/p1021mds/Makefile new file mode 100644 index 000..50d4743 --- /dev/null +++ b/board/freescale/p1021mds/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (C) 2010-2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS-y+= $(BOARD).o +COBJS-y+= law.o +COBJS-y+= tlb.o +COBJS-y+= ddr.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/freescale/p1021mds/config.mk b/board/freescale/p1021mds/config.mk new file mode 100644 index 000..3888f61 --- /dev/null +++ b/board/freescale/p1021mds/config.mk @@ -0,0 +1,31 @@ +# +# Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project.
[U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
From: Haiying Wang haiying.w...@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
P1021MDS has to load the microcode from NAND flash, this patch defines
misc_init_r() for loading ucode and initializing qe.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc85xx/speed.c |4 ++
arch/powerpc/include/asm/immap_85xx.h | 13 +
board/freescale/p1021mds/p1021mds.c | 83 +
drivers/qe/uec.c | 40 +++-
include/configs/P1021MDS.h| 47 ++
5 files changed, 186 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index f2aa8d0..ae94ee8 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -165,10 +165,14 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
+#ifdef CONFIG_P1021
+ sysInfo-freqQE = sysInfo-freqSystemBus;
+#else
qe_ratio = ((gur-porpllsr) MPC85xx_PORPLLSR_QE_RATIO)
MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo-freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#endif
#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 77e3629..9b7de6b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1909,6 +1909,19 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SD_DATA 0x8000
#define MPC85xx_PMUXCR_SDHC_CD 0x4000
#define MPC85xx_PMUXCR_SDHC_WP 0x2000
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE1 0x4000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE100x0020
+#define MPC85xx_PMUXCR_QE110x0010
+#define MPC85xx_PMUXCR_QE120x0008
u32 pmuxcr2;/* Alt. function signal multiplex control 2 */
u8 res6[8];
u32 devdisr;/* Device disable control */
diff --git a/board/freescale/p1021mds/p1021mds.c
b/board/freescale/p1021mds/p1021mds.c
index c7a7e57..e1ee1cf 100644
--- a/board/freescale/p1021mds/p1021mds.c
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -37,6 +37,54 @@
#include tsec.h
#include netdev.h
+#ifdef CONFIG_QE
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#include nand.h
+#include asm/errno.h
+#endif
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+#endif
+
+#ifdef CONFIG_QE
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC*/
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B*/
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B*/
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B*/
+ {0, 17, 2, 0, 2}, /* ENET1_CRS*/
+ {0, 16, 2, 0, 2}, /* ENET1_COL*/
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B*/
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B*/
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B*/
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
int board_early_init_f(void)
{
@@ -100,6 +148,14 @@ int board_eth_init(bd_t *bis)
tsec_eth_init(bis, tsec_info, num);
+#if defined(CONFIG_UEC_ETH)
+ /* QE0 and QE3
[U-Boot] [PATCH 1/6] Introduce the Tertiary Program loader
From: Haiying Wang haiying.w...@freescale.com
TPL is introduced to enable a loader stub that boots out of some type of RAM,
after being loaded by an SPL or similar platform-specific mechanism.
One example of using this tpl loader is to initialize the ddr through spd code
in case the L2 SRAM size is not big enough to hold the final uboot image and
the nand spl code needs to be limitated to 4K byte, then tpl code will load the
final uboot image after ddr is initialized.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
Makefile | 15 ++-
README | 27 +++
2 files changed, 41 insertions(+), 1 deletions(-)
diff --git a/Makefile b/Makefile
index 0d1ea5d..ae5db69 100644
--- a/Makefile
+++ b/Makefile
@@ -402,8 +402,19 @@ $(obj)u-boot.lds: $(LDSCRIPT)
nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
+tpl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
+ $(MAKE) -C tpl/board/$(BOARDDIR) all
+
+NAND_SPL_OBJS-y += $(obj)nand_spl/u-boot-spl-16k.bin
+NAND_SPL_OBJS-$(CONFIG_HAS_TPL) += $(obj)tpl/u-boot-tpl.bin
+NAND_SPL_OBJS-y += $(obj)u-boot.bin
+
+ifeq ($(CONFIG_HAS_TPL),y)
+$(obj)u-boot-nand.bin: nand_spl tpl $(obj)u-boot.bin
+else
$(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin
- cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin
$(obj)u-boot-nand.bin
+endif
+ cat $(NAND_SPL_OBJS-y) $(obj)u-boot-nand.bin
onenand_ipl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
@@ -1221,6 +1232,7 @@ clean:
@rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
+ @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.map}
@rm -f $(ONENAND_BIN)
@rm -f $(obj)onenand_ipl/u-boot.lds
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@@ -1245,6 +1257,7 @@ clobber: clean
@rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name * -type l
-print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name * -type l
-print | xargs rm -f
+ @[ ! -d $(obj)tpl ] || find $(obj)tpl -name * -type l -print | xargs
rm -f
ifeq ($(OBJTREE),$(SRCTREE))
mrproper \
diff --git a/README b/README
index 755d17c..447fff0 100644
--- a/README
+++ b/README
@@ -2124,6 +2124,33 @@ FIT uImage format:
Adds the MTD partitioning infrastructure from the Linux
kernel. Needed for UBI support.
+- NAND Boot Support
+ CONFIG_NAND_U_BOOT
+
+ Builds a U-Boot image that boots from NAND, prefixed by a small
+ loader stub (secondary program loader -- SPL) that loads the
+ rest of U-Boot into RAM. This symbol will be set in all build
+ phases.
+
+ CONFIG_NAND_SPL
+
+ This is set by the build system when compiling code to go into
+ the SPL. It is not set when building the code that the SPL
+ loads.
+
+- TPL Boot Support
+ CONFIG_HAS_TPL
+
+ Builds a U-Boot image that contains a loader stub (tertiary
+ program loader -- TPL) that boots out of some type of RAM,
+ after being loaded by an SPL or similar platform-specific
+ mechanism. This symbol will be set in all build phases.
+
+ CONFIG_IN_TPL
+
+ This is set by the build system when compiling code to go into
+ the TPL. It is not set when building the code that the TPL
+ loads, or when building the SPL.
Modem Support:
--
--
1.7.3.1.50.g1e633
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/8 v4] P1021: add P1021MDS board support
From: Haiying Wang haiying.w...@freescale.com Support P1021MDS board to boot from NAND flash (No NOR flash on this board). And because P1021 only has 256K L2 SRAM, which can not used for final uboot image, this patch also enables the TPL BOOT on P1021MDS so that DDR can be initialized in L2 SRAM through SPD code. So there are three stage uboot images: * nand_spl, pad from 4KB size to 16KB, load tpl_boot from offset 16KB in NAND. * tpl_boot, 112KB size. The env variables are copied to offset 128KB in L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 128KB in NAND. * final uboot image, size is variable depends on the functions enabled. Signed-off-by: Haiying Wang haiying.w...@freescale.com Signed-off-by: Mohit Kumar mohit.ku...@freescale.com Signed-off-by: Yu Liu yu@freescale.com Signed-off-by: Kai Jiang kai.ji...@freescale.com --- v4: Remove PCIe LAW setting in board law.c, and fix the comments of CONFIG_PCI. MAINTAINERS |4 + board/freescale/p1021mds/Makefile | 52 +++ board/freescale/p1021mds/config.mk| 31 ++ board/freescale/p1021mds/ddr.c| 107 + board/freescale/p1021mds/law.c| 34 ++ board/freescale/p1021mds/p1021mds.c | 133 ++ board/freescale/p1021mds/tlb.c| 102 + boards.cfg|1 + include/configs/P1021MDS.h| 571 + nand_spl/board/freescale/p1021mds/Makefile| 134 ++ nand_spl/board/freescale/p1021mds/nand_boot.c | 69 +++ nand_spl/nand_boot_fsl_elbc.c |6 +- tpl/board/freescale/p1021mds/Makefile | 256 +++ tpl/board/freescale/p1021mds/tpl_boot.c | 79 14 files changed, 1578 insertions(+), 1 deletions(-) create mode 100644 board/freescale/p1021mds/Makefile create mode 100644 board/freescale/p1021mds/config.mk create mode 100644 board/freescale/p1021mds/ddr.c create mode 100644 board/freescale/p1021mds/law.c create mode 100644 board/freescale/p1021mds/p1021mds.c create mode 100644 board/freescale/p1021mds/tlb.c create mode 100644 include/configs/P1021MDS.h create mode 100644 nand_spl/board/freescale/p1021mds/Makefile create mode 100644 nand_spl/board/freescale/p1021mds/nand_boot.c create mode 100644 tpl/board/freescale/p1021mds/Makefile create mode 100644 tpl/board/freescale/p1021mds/tpl_boot.c diff --git a/MAINTAINERS b/MAINTAINERS index edd1c5c..da1b2a3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17,6 +17,10 @@ # Board CPU # # +Haiying Wang haiying.w...@freescale.com + + P1021MDSP1021 + Poonam Aggrwal poonam.aggr...@freescale.com P2020RDBP2020 diff --git a/board/freescale/p1021mds/Makefile b/board/freescale/p1021mds/Makefile new file mode 100644 index 000..50d4743 --- /dev/null +++ b/board/freescale/p1021mds/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (C) 2010-2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS-y+= $(BOARD).o +COBJS-y+= law.o +COBJS-y+= tlb.o +COBJS-y+= ddr.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/freescale/p1021mds/config.mk b/board/freescale/p1021mds/config.mk new file mode 100644 index 000..3888f61 --- /dev/null +++ b/board/freescale/p1021mds/config.mk @@ -0,0 +1,31 @@ +# +# Copyright (C) 2010 - 2011 Freescale Semiconductor, Inc.
[U-Boot] [PATCH] Fix NAND_SPL and ONENAND_IPL in Makefile
From: Haiying Wang haiying.w...@freescale.com Signed-off-by: Haiying Wang haiying.w...@freescale.com Acked-by: Scott Wood scottw...@freescale.com --- Makefile | 30 ++ 1 files changed, 14 insertions(+), 16 deletions(-) diff --git a/Makefile b/Makefile index 5f93646..0d1ea5d 100644 --- a/Makefile +++ b/Makefile @@ -287,17 +287,6 @@ LDPPFLAGS += \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') -ifeq ($(CONFIG_NAND_U_BOOT),y) -NAND_SPL = nand_spl -U_BOOT_NAND = $(obj)u-boot-nand.bin -endif - -ifeq ($(CONFIG_ONENAND_U_BOOT),y) -ONENAND_IPL = onenand_ipl -U_BOOT_ONENAND = $(obj)u-boot-onenand.bin -ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin -endif - __OBJS := $(subst $(obj),,$(OBJS)) __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD)) @@ -320,7 +309,16 @@ BOARD_SIZE_CHECK = endif # Always append ALL so that arch config.mk's can add custom ones -ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) +ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map + +ifeq ($(CONFIG_NAND_U_BOOT),y) +ALL += $(obj)u-boot-nand.bin +endif + +ifeq ($(CONFIG_ONENAND_U_BOOT),y) +ALL += $(obj)u-boot-onenand.bin +ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin +endif all: $(ALL) @@ -401,16 +399,16 @@ $(LDSCRIPT): depend $(obj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - $^ $@ -$(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) depend +nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C nand_spl/board/$(BOARDDIR) all -$(U_BOOT_NAND):$(NAND_SPL) $(obj)u-boot.bin +$(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin $(obj)u-boot-nand.bin -$(ONENAND_IPL):$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk +onenand_ipl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all -$(U_BOOT_ONENAND): $(ONENAND_IPL) $(obj)u-boot.bin +$(obj)u-boot-onenand.bin: onenand_ipl $(obj)u-boot.bin cat $(ONENAND_BIN) $(obj)u-boot.bin $(obj)u-boot-onenand.bin $(VERSION_FILE): -- 1.7.3.1.50.g1e633 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
From: Haiying Wang haiying.w...@freescale.com Support P1021MDS board to boot from NAND flash (No NOR flash on this board). And because P1021 only has 256K L2 SRAM, which can not used for final uboot image, this patch also enables the TPL BOOT on P1021MDS so that DDR can be initialized in L2 SRAM through SPD code. So there are three stage uboot images: * nand_spl, pad from 4KB size to 16KB, load tpl_boot from offset 16KB in NAND. * tpl_boot, 112KB size. The env variables are copied to offset 128KB in L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 128KB in NAND. * final uboot image, size is variable depends on the functions enabled. Signed-off-by: Haiying Wang haiying.w...@freescale.com Signed-off-by: Mohit Kumar mohit.ku...@freescale.com Signed-off-by: Yu Liu yu@freescale.com Signed-off-by: Kai Jiang kai.ji...@freescale.com --- v3: use CONFIG_HAS_TPL and CONFIG_IN_TPL, update copyright year, remove pci.c, incoperate with the changes in upstream. MAINTAINERS |4 + board/freescale/p1021mds/Makefile | 52 +++ board/freescale/p1021mds/config.mk| 31 ++ board/freescale/p1021mds/ddr.c| 107 + board/freescale/p1021mds/law.c| 38 ++ board/freescale/p1021mds/p1021mds.c | 133 ++ board/freescale/p1021mds/tlb.c| 102 + boards.cfg|1 + include/configs/P1021MDS.h| 571 + nand_spl/board/freescale/p1021mds/Makefile| 134 ++ nand_spl/board/freescale/p1021mds/nand_boot.c | 69 +++ nand_spl/nand_boot_fsl_elbc.c |6 +- tpl/board/freescale/p1021mds/Makefile | 256 +++ tpl/board/freescale/p1021mds/tpl_boot.c | 79 14 files changed, 1582 insertions(+), 1 deletions(-) create mode 100644 board/freescale/p1021mds/Makefile create mode 100644 board/freescale/p1021mds/config.mk create mode 100644 board/freescale/p1021mds/ddr.c create mode 100644 board/freescale/p1021mds/law.c create mode 100644 board/freescale/p1021mds/p1021mds.c create mode 100644 board/freescale/p1021mds/tlb.c create mode 100644 include/configs/P1021MDS.h create mode 100644 nand_spl/board/freescale/p1021mds/Makefile create mode 100644 nand_spl/board/freescale/p1021mds/nand_boot.c create mode 100644 tpl/board/freescale/p1021mds/Makefile create mode 100644 tpl/board/freescale/p1021mds/tpl_boot.c diff --git a/MAINTAINERS b/MAINTAINERS index edd1c5c..da1b2a3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17,6 +17,10 @@ # Board CPU # # +Haiying Wang haiying.w...@freescale.com + + P1021MDSP1021 + Poonam Aggrwal poonam.aggr...@freescale.com P2020RDBP2020 diff --git a/board/freescale/p1021mds/Makefile b/board/freescale/p1021mds/Makefile new file mode 100644 index 000..50d4743 --- /dev/null +++ b/board/freescale/p1021mds/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (C) 2010-2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS-y+= $(BOARD).o +COBJS-y+= law.o +COBJS-y+= tlb.o +COBJS-y+= ddr.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/freescale/p1021mds/config.mk b/board/freescale/p1021mds/config.mk new file mode 100644 index 000..3888f61 --- /dev/null +++ b/board/freescale/p1021mds/config.mk @@ -0,0 +1,31 @@ +# +# Copyright (C)
[U-Boot] [PATCH 8/8 v3] p1021mds: add QE and UEC support
From: Haiying Wang haiying.w...@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
P1021MDS has to load the microcode from NAND flash, this patch defines
misc_init_r() for loading ucode and initializing qe.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v3: make changes in p1021mds.c and P1021MDS.h according to the changes in patch
5/8, update the copyright years.
arch/powerpc/cpu/mpc85xx/speed.c |4 ++
arch/powerpc/include/asm/immap_85xx.h | 13 +
board/freescale/p1021mds/p1021mds.c | 83 +
drivers/qe/uec.c | 40 +++-
include/configs/P1021MDS.h| 47 ++
5 files changed, 186 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index f2aa8d0..ae94ee8 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -165,10 +165,14 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
+#ifdef CONFIG_P1021
+ sysInfo-freqQE = sysInfo-freqSystemBus;
+#else
qe_ratio = ((gur-porpllsr) MPC85xx_PORPLLSR_QE_RATIO)
MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo-freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#endif
#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 77e3629..9b7de6b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1909,6 +1909,19 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SD_DATA 0x8000
#define MPC85xx_PMUXCR_SDHC_CD 0x4000
#define MPC85xx_PMUXCR_SDHC_WP 0x2000
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE1 0x4000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE100x0020
+#define MPC85xx_PMUXCR_QE110x0010
+#define MPC85xx_PMUXCR_QE120x0008
u32 pmuxcr2;/* Alt. function signal multiplex control 2 */
u8 res6[8];
u32 devdisr;/* Device disable control */
diff --git a/board/freescale/p1021mds/p1021mds.c
b/board/freescale/p1021mds/p1021mds.c
index c7a7e57..e1ee1cf 100644
--- a/board/freescale/p1021mds/p1021mds.c
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -37,6 +37,54 @@
#include tsec.h
#include netdev.h
+#ifdef CONFIG_QE
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#include nand.h
+#include asm/errno.h
+#endif
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+#endif
+
+#ifdef CONFIG_QE
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC*/
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B*/
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B*/
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B*/
+ {0, 17, 2, 0, 2}, /* ENET1_CRS*/
+ {0, 16, 2, 0, 2}, /* ENET1_COL*/
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B*/
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B*/
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B*/
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
int board_early_init_f(void)
{
@@ -100,6 +148,14 @@ int
[U-Boot] [PATCH 4/8 v3] powerpc/85xx: add TPL support
From: Haiying Wang haiying.w...@freescale.com
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v3: Use HAS_TPL and IN_TPL, change initdram for TPL, fix the inconsistent
comments.
arch/powerpc/cpu/mpc85xx/cpu.c |7 ++
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 22 ++-
arch/powerpc/cpu/mpc85xx/start.S | 12 ++--
arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds | 99 ++
4 files changed, 132 insertions(+), 8 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 1aad2ba..e923547 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -296,6 +296,12 @@ void mpc85xx_reginfo(void)
#ifndef CONFIG_FSL_CORENET
phys_size_t initdram(int board_type)
{
+#if defined(CONFIG_HAS_TPL) !defined(CONFIG_IN_TPL)
+ /* ddr has been initialized in tpl boot stage thus we only need
+* to get the ddr dram size for the final uboot.
+*/
+ return fsl_ddr_sdram_size();
+#else
phys_size_t dram_size = 0;
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
@@ -342,6 +348,7 @@ phys_size_t initdram(int board_type)
puts(DDR: );
return dram_size;
+#endif /* CONFIG_HAS_TPL */
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 8fb27ab..65c32d9 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009 - 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -23,6 +23,8 @@
#include common.h
#include asm/io.h
+DECLARE_GLOBAL_DATA_PTR;
+
void cpu_init_f(void)
{
fsl_lbc_t *lbc = LBC_BASE_ADDR;
@@ -40,7 +42,8 @@ void cpu_init_f(void)
#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
#endif
-#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L2_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L2_ADDR) \
+!defined(CONFIG_IN_TPL)
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
char *l2srbar;
int i;
@@ -60,4 +63,19 @@ void cpu_init_f(void)
for (i = 0; i CONFIG_SYS_L2_SIZE; i++)
l2srbar[i] = 0;
#endif
+#ifdef CONFIG_IN_TPL
+ init_used_tlb_cams();
+#endif
+}
+
+#ifdef CONFIG_IN_TPL
+/*
+ * Because the primary cpu's info is enough for the 2nd stage, we define the
+ * cpu number to 1 so as to keep code size for 2nd stage binary as small as
+ * possible.
+ */
+int cpu_numcores()
+{
+ return 1;
}
+#endif /* CONFIG_IN_TPL */
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index fa98af6..5496fc4 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -58,12 +58,12 @@
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) !defined(CONFIG_IN_TPL)
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
-#endif
+#endif /* !CONFIG_NAND_SPL !CONFIG_IN_TPL*/
GOT_ENTRY(__init_end)
GOT_ENTRY(_end)
@@ -435,7 +435,7 @@ _start_cont:
/* NOTREACHED - board_init_f() does not return */
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) !defined(CONFIG_IN_TPL)
. = EXC_OFF_SYS_RESET
.globl _start_of_vectors
_start_of_vectors:
@@ -877,7 +877,7 @@ in32:
in32r:
lwbrx r3,r0,r3
blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !CONFIG_NAND_SPL !CONFIG_IN_TPL */
/*--*/
@@ -1067,7 +1067,7 @@ clear_bss:
mr r4,r10 /* Destination Address */
bl board_init_r
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) !defined(CONFIG_IN_TPL)
/*
* Copy exception vector code to low memory
*
@@ -1207,4 +1207,4 @@ setup_ivors:
#include fixed_ivor.S
blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !CONFIG_NAND_SPL !CONFIG_IN_TPL */
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
b/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
new file mode 100644
index 000..d8ff62b
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but
[U-Boot] [PATCH 3/8 v3] Introduce the Tertiary Program loader
From: Haiying Wang haiying.w...@freescale.com
TPL is introduced to enable a loader stub that boots out of some type of RAM,
after being loaded by an SPL or similar platform-specific mechanism.
One example of using this tpl loader is to initialize the ddr through spd code
in case the L2 SRAM size is not big enough to hold the final uboot image and
the nand spl code needs to be limitated to 4K byte, then tpl code will load the
final uboot image after ddr is initialized.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v3: remove TPL_BOOT, use HAS_TPL and IN_TPL
Makefile | 15 ++-
README | 27 +++
2 files changed, 41 insertions(+), 1 deletions(-)
diff --git a/Makefile b/Makefile
index 0d1ea5d..ae5db69 100644
--- a/Makefile
+++ b/Makefile
@@ -402,8 +402,19 @@ $(obj)u-boot.lds: $(LDSCRIPT)
nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
+tpl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
+ $(MAKE) -C tpl/board/$(BOARDDIR) all
+
+NAND_SPL_OBJS-y += $(obj)nand_spl/u-boot-spl-16k.bin
+NAND_SPL_OBJS-$(CONFIG_HAS_TPL) += $(obj)tpl/u-boot-tpl.bin
+NAND_SPL_OBJS-y += $(obj)u-boot.bin
+
+ifeq ($(CONFIG_HAS_TPL),y)
+$(obj)u-boot-nand.bin: nand_spl tpl $(obj)u-boot.bin
+else
$(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin
- cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin
$(obj)u-boot-nand.bin
+endif
+ cat $(NAND_SPL_OBJS-y) $(obj)u-boot-nand.bin
onenand_ipl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
@@ -1221,6 +1232,7 @@ clean:
@rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
+ @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.map}
@rm -f $(ONENAND_BIN)
@rm -f $(obj)onenand_ipl/u-boot.lds
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@@ -1245,6 +1257,7 @@ clobber: clean
@rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name * -type l
-print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name * -type l
-print | xargs rm -f
+ @[ ! -d $(obj)tpl ] || find $(obj)tpl -name * -type l -print | xargs
rm -f
ifeq ($(OBJTREE),$(SRCTREE))
mrproper \
diff --git a/README b/README
index 755d17c..a37fdb1 100644
--- a/README
+++ b/README
@@ -2124,6 +2124,33 @@ FIT uImage format:
Adds the MTD partitioning infrastructure from the Linux
kernel. Needed for UBI support.
+- NAND Boot Support
+ CONFIG_NAND_U_BOOT
+
+ Builds a U-Boot image that boots from NAND, prefixed by a small
+ loader stub (secondary program loader -- SPL) that loads the
+ rest of U-Boot into RAM. This symbol will be set in all build
+ phases.
+
+ CONFIG_NAND_SPL
+
+ This is set by the build system when compiling code to go into
+ the SPL. It is not set when building the code that the SPL
+ loads.
+
+- TPL Boot Support
+ CONFIG_HAS_TPL
+
+ Builds a U-Boot image that contains a loader stub (tertiary
+ program loader -- TPL) that boots out of some type of RAM,
+ after being loaded by an SPL or similar platform-specific
+ mechanism. This symbol will be set in all build phases.
+
+ CONFIG_IN_TPL
+
+ This is set by the build system when compiling code to go into
+ the TPL. It is not set when building the code that the TPL
+ loads, or when building the SPL.
Modem Support:
--
--
1.7.3.1.50.g1e633
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[U-Boot] [PATCH 7/7] add gc-sections to TPL boot
From: Haiying Wang haiying.w...@freescale.com Signed-off-by: Haiying Wang haiying.w...@freescale.com --- arch/powerpc/config.mk |4 config.mk |7 ++- 2 files changed, 10 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 64191c7..78e53c4 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -27,7 +27,11 @@ STANDALONE_LOAD_ADDR = 0x4 LDFLAGS_u-boot = --gc-sections PLATFORM_RELFLAGS += -mrelocatable -ffunction-sections -fdata-sections PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ +ifdef CONFIG_HAS_TPL +PLATFORM_LDFLAGS += -n --gc-sections +else PLATFORM_LDFLAGS += -n +endif ifdef CONFIG_SYS_LDSCRIPT # need to strip off double quotes diff --git a/config.mk b/config.mk index 5147c35..d7bb07f 100644 --- a/config.mk +++ b/config.mk @@ -260,8 +260,13 @@ $(obj)%.s: %.c # # If the list of objects to link is empty, just create an empty built-in.o +ifdef CONFIG_HAS_TPL +cmd_link_o_target = $(if $(strip $1),\ + $(LD) -r -o $@ $1,\ + rm -f $@; $(AR) rcs $@ ) +else cmd_link_o_target = $(if $(strip $1),\ $(LD) $(LDFLAGS) -r -o $@ $1,\ rm -f $@; $(AR) rcs $@ ) - +endif # -- 1.7.3.1.50.g1e633 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/8] powerpc/85xx: do not reloc l2srbar if CONFIG_FLASH_BASE is not defined
From: Haiying Wang haiying.w...@freescale.com
This fixes the compiling error for the board which doesn't have NOR flash
(so CONFIG_FLASH_BASE is not defined)
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 27236a0..4b8faa5 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -327,7 +327,7 @@ int cpu_init_r(void)
if (l2cache-l2ctl MPC85xx_L2CTL_L2E) {
puts(already enabled);
l2srbar = l2cache-l2srbar0;
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#if defined(CONFIG_SYS_INIT_L2_ADDR) defined(CONFIG_SYS_FLASH_BASE)
if (l2cache-l2ctl MPC85xx_L2CTL_L2SRAM_ENTIRE
l2srbar = CONFIG_SYS_FLASH_BASE) {
l2srbar = CONFIG_SYS_INIT_L2_ADDR;
--
1.7.3.1.50.g1e633
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[U-Boot] [PATCH 0/8 v2] Add support to tpl boot and p1021mds board
This is the second version of patchset to add support of TPL(Tertiary Program Loader) and P1021MDS board. Compared with the previous version, patch #3 is splitted into two patches and incorporates the comments from Wolfgang and Mike. Patch#4 has changes based on 2010.12-rc2 release. The other patches remain unchanged. [PATCH 1/8] powerpc/85xx: do not reloc l2srbar if CONFIG_FLASH_BASE is not defined [PATCH 2/8] 8xxx/ddr: add support to only compute the ddr sdram size [PATCH 3/8 v2] Introduce the Tertiary Program loader [PATCH 4/8 v2] powerpc/85xx: add TPL_BOOT support [PATCH 5/8 v2] P1021MDS: add P1021MDS board support [PATCH 6/8] powerpc/p1021: add more P1021 defines. [PATCH 7/8] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash [PATCH 8/8] p1021mds: add QE and UEC support ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/8] 8xxx/ddr: add support to only compute the ddr sdram size
From: Haiying Wang haiying.w...@freescale.com
This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in
case that the DDR SDRAM is initialized in the 2nd stage uboot and should not
be intialized again in the final stage uboot.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 10 -
arch/powerpc/cpu/mpc8xxx/ddr/ddr.h |8 --
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 31 +
3 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 3fec100..8fdafdb 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1176,7 +1176,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t
*popts,
fsl_ddr_cfg_regs_t *ddr,
const common_timing_params_t *common_dimm,
const dimm_params_t *dimm_params,
- unsigned int dbw_cap_adj)
+ unsigned int dbw_cap_adj,
+ unsigned int size_only)
{
unsigned int i;
unsigned int cas_latency;
@@ -1394,6 +1395,13 @@ compute_fsl_memctl_config_regs(const memctl_options_t
*popts,
printf(CS%d is disabled.\n, i);
}
+ /*
+* In the case we only need to compute the ddr sdram size, we only need
+* to set csn registers, so return from here.
+*/
+ if (size_only)
+ return 0;
+
set_ddr_eor(ddr, popts);
#if !defined(CONFIG_FSL_DDR1)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index 98acb8d..8c24131 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -55,7 +55,8 @@ typedef struct {
#define STEP_ALL 0xFFF
extern unsigned long long
-fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step);
+fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
+ unsigned int size_only);
extern const char * step_to_string(unsigned int step);
@@ -64,7 +65,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
fsl_ddr_cfg_regs_t *ddr,
const common_timing_params_t *common_dimm,
const dimm_params_t *dimm_parameters,
- unsigned int dbw_capacity_adjust);
+ unsigned int dbw_capacity_adjust,
+ unsigned int size_only);
extern unsigned int
compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 6d582e9..b89b471 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -233,7 +233,8 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
}
unsigned long long
-fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
+fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
+ unsigned int size_only)
{
unsigned int i, j;
unsigned int all_controllers_memctl_interleaving = 0;
@@ -338,7 +339,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int
start_step)
pinfo-memctl_opts[i],
ddr_reg[i], timing_params[i],
pinfo-dimm_params[i],
- dbw_capacity_adjust[i]);
+ dbw_capacity_adjust[i],
+ size_only);
}
default:
@@ -405,7 +407,7 @@ phys_size_t fsl_ddr_sdram(void)
memset(info, 0, sizeof(fsl_ddr_info_t));
/* Compute it once normally. */
- total_memory = fsl_ddr_compute(info, STEP_GET_SPD);
+ total_memory = fsl_ddr_compute(info, STEP_GET_SPD, 0);
/* Check for memory controller interleaving. */
memctl_interleaved = 0;
@@ -430,7 +432,8 @@ phys_size_t fsl_ddr_sdram(void)
info.memctl_opts[i].memctl_interleaving = 0;
[U-Boot] [PATCH 3/8 v2] Introduce the Tertiary Program loader
From: Haiying Wang haiying.w...@freescale.com
TPL is introduced to enable a loader stub that boots out of some type of RAM,
after being loaded by an SPL or similar platform-specific mechanism.
One example of using this tpl loader is to initialize the ddr through spd code
in case the L2 SRAM size is not big enough to hold the final uboot image and
the nand spl code needs to be limitated to 4K byte, then tpl code will load the
final uboot image after ddr is initialized.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
Incorporate Mike's comment to use new variable NAND_SPL_OBJS-y
Makefile | 17 +++--
README | 27 +++
2 files changed, 42 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
index 87a383d..94af465 100644
--- a/Makefile
+++ b/Makefile
@@ -290,6 +290,10 @@ LDPPFLAGS += \
$(shell $(LD) --version | \
sed -ne 's/GNU ld version
\([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
+ifeq ($(CONFIG_TPL_U_BOOT),y)
+TPL_BOOT = tpl
+endif
+
ifeq ($(CONFIG_NAND_U_BOOT),y)
NAND_SPL = nand_spl
U_BOOT_NAND = $(obj)u-boot-nand.bin
@@ -407,8 +411,15 @@ $(obj)u-boot.lds: $(LDSCRIPT)
$(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) depend
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
-$(U_BOOT_NAND):$(NAND_SPL) $(obj)u-boot.bin
- cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin
$(obj)u-boot-nand.bin
+$(TPL_BOOT): $(TIMESTAMP_FILE) $(VERSION_FILE) depend
+ $(MAKE) -C tpl/board/$(BOARDDIR) all
+
+NAND_SPL_OBJS-y += $(obj)nand_spl/u-boot-spl-16k.bin
+NAND_SPL_OBJS-$(CONFIG_TPL_U_BOOT) += $(obj)tpl/u-boot-tpl.bin
+NAND_SPL_OBJS-y += $(obj)u-boot.bin
+
+$(U_BOOT_NAND): $(NAND_SPL) $(TPL_BOOT) $(obj)u-boot.bin
+ cat $(NAND_SPL_OBJS-y) u-boot-nand.bin
$(ONENAND_IPL):$(TIMESTAMP_FILE) $(VERSION_FILE)
$(obj)include/autoconf.mk
$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
@@ -1226,6 +1237,7 @@ clean:
@rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
+ @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.map}
@rm -f $(ONENAND_BIN)
@rm -f $(obj)onenand_ipl/u-boot.lds
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@@ -1250,6 +1262,7 @@ clobber: clean
@rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name * -type l
-print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name * -type l
-print | xargs rm -f
+ @[ ! -d $(obj)tpl ] || find $(obj)tpl -name * -type l -print | xargs
rm -f
ifeq ($(OBJTREE),$(SRCTREE))
mrproper \
diff --git a/README b/README
index 68f5fb0..9c7d40d 100644
--- a/README
+++ b/README
@@ -2108,6 +2108,33 @@ FIT uImage format:
Adds the MTD partitioning infrastructure from the Linux
kernel. Needed for UBI support.
+- NAND Boot Support
+ CONFIG_NAND_U_BOOT
+
+ Builds a U-Boot image that boots from NAND, prefixed by a small
+ loader stub (secondary program loader -- SPL) that loads the
+ rest of U-Boot into RAM. This symbol will be set in all build
+ phases.
+
+ CONFIG_NAND_SPL
+
+ This is set by the build system when compiling code to go into
+ the SPL. It is not set when building the code that the SPL
+ loads.
+
+- TPL Boot Support
+ CONFIG_TPL_U_BOOT
+
+ Builds a U-Boot image that contains a loader stub (tertiary
+ program loader -- TPL) that boots out of some type of RAM,
+ after being loaded by an SPL or similar platform-specific
+ mechanism. This symbol will be set in all build phases.
+
+ CONFIG_TPL_BOOT
+
+ This is set by the build system when compiling code to go into
+ the TPL. It is not set when building the code that the TPL
+ loads, or when building the SPL.
Modem Support:
--
--
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[U-Boot] [PATCH 4/8 v2] powerpc/85xx: add TPL_BOOT support
From: Haiying Wang haiying.w...@freescale.com
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
Splitted from TPL patch to only address 85xx changes
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 34 ++-
arch/powerpc/cpu/mpc85xx/start.S | 12 ++--
arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds | 99 ++
3 files changed, 137 insertions(+), 8 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 8fb27ab..decedca 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -40,7 +40,8 @@ void cpu_init_f(void)
#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
#endif
-#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L2_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L2_ADDR) \
+!defined(CONFIG_TPL_BOOT)
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
char *l2srbar;
int i;
@@ -60,4 +61,33 @@ void cpu_init_f(void)
for (i = 0; i CONFIG_SYS_L2_SIZE; i++)
l2srbar[i] = 0;
#endif
+#ifdef CONFIG_TPL_BOOT
+ init_used_tlb_cams();
+#endif
+}
+
+#ifdef CONFIG_TPL_BOOT
+/*
+ * Because the primary cpu's info is enough for the 2nd stage, we define the
+ * cpu number to 1 so as to keep code size for 2nd stage binary as small as
+ * possible.
+ */
+int cpu_numcores()
+{
+ return 1;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Get timebase clock frequency
+ */
+unsigned long get_tbclk(void)
+{
+#ifdef CONFIG_FSL_CORENET
+ return (gd-bus_clk + 8) / 16;
+#else
+ return (gd-bus_clk + 4UL)/8UL;
+#endif
}
+#endif /* CONFIG_TPL_BOOT */
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 945c1b8..12b0ebb 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -58,12 +58,12 @@
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) !defined(CONFIG_TPL_BOOT)
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
-#endif
+#endif /* !CONFIG_TPL_BOOT || !CONFIG_NAND_SPL*/
GOT_ENTRY(__init_end)
GOT_ENTRY(_end)
@@ -435,7 +435,7 @@ _start_cont:
/* NOTREACHED - board_init_f() does not return */
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) !defined(CONFIG_TPL_BOOT)
. = EXC_OFF_SYS_RESET
.globl _start_of_vectors
_start_of_vectors:
@@ -877,7 +877,7 @@ in32:
in32r:
lwbrx r3,r0,r3
blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !CONFIG_NAND_SPL !CONFIG_TPL_BOOT */
/*--*/
@@ -1067,7 +1067,7 @@ clear_bss:
mr r4,r10 /* Destination Address */
bl board_init_r
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) !defined(CONFIG_TPL_BOOT)
/*
* Copy exception vector code to low memory
*
@@ -1207,4 +1207,4 @@ setup_ivors:
#include fixed_ivor.S
blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !CONFIG_NAND_SPL !CONFIG_TPL_BOOT */
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
b/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
new file mode 100644
index 000..1c17acf
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .text :
+ {
+*(.text*)
+ } :text
+_etext = .;
+PROVIDE (etext = .);
+.rodata:
+ {
+*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } :text
[U-Boot] [PATCH 6/8] powerpc/p1021: add more P1021 defines.
From: Haiying Wang haiying.w...@freescale.com
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |6 ++
arch/powerpc/include/asm/immap_qe.h |9 +++--
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 30c64eb..9eb106c 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1963,6 +1963,12 @@ typedef struct ccsr_gur {
u8 res10b[76];
par_io_t qe_par_io[7];
u8 res10c[1600];
+#elif defined(CONFIG_P1021)
+ u8 res10b1[12];
+ u32 iovselsr;
+ u8 res10b2[60];
+ par_io_t qe_par_io[3];
+ u8 res10c[1496];
#else
u8 res10b[1868];
#endif
diff --git a/arch/powerpc/include/asm/immap_qe.h
b/arch/powerpc/include/asm/immap_qe.h
index 531cfc8..74c9013 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -3,7 +3,7 @@
* The Internal Memory Map for devices with QE on them. This
* is the superset of all QE devices (8360, etc.).
*
- * Copyright (c) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (c) 2006-2010 Freescale Semiconductor, Inc.
* Author: Shlomi Gridih grid...@freescale.com
*
* This program is free software; you can redistribute it and/or modify it
@@ -588,6 +588,9 @@ typedef struct qe_immap {
#elif defined(CONFIG_MPC8569)
u8 muram[0x2]; /* 0x1_ - 0x3_ Multi-user RAM */
u8 res17[0x1]; /* 0x3_ - 0x4_ */
+#elif defined(CONFIG_P1021)
+ u8 muram[0x06000]; /* 0x1_ - 0x1_6000 Multi-user RAM */
+ u8 res17[0x1a000]; /* 0x1_6000 - 0x3_ */
#else
u8 muram[0xC000]; /* 0x11 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x14 */
@@ -601,13 +604,15 @@ extern qe_map_t *qe_immr;
#define QE_MURAM_SIZE 0x1UL
#elif defined(CONFIG_MPC8569)
#define QE_MURAM_SIZE 0x2UL
+#elif defined(CONFIG_P1021)
+#define QE_MURAM_SIZE 0x6000UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832x)
#define QE_MURAM_SIZE 0x4000UL
#endif
-#if defined(CONFIG_MPC8323)
+#if defined(CONFIG_MPC8323) || defined(CONFIG_P1021)
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_MPC8569)
--
1.7.3.1.50.g1e633
___
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[U-Boot] [PATCH 7/8] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash
From: Haiying Wang haiying.w...@freescale.com For some board which doesn't have NOR flash and the QE's firmware(ucode) is saved in its NAND flash, we don't want call qe_init in cpu_init_r, but will call it later after nand is initialized. Signed-off-by: Haiying Wang haiying.w...@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4b8faa5..eb34378 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -369,7 +369,7 @@ int cpu_init_r(void) enable_cpc(); -#ifdef CONFIG_QE +#if defined(CONFIG_QE) !defined(CONFIG_SYS_QE_FW_IN_NAND) uint qe_base = CONFIG_SYS_IMMR + 0x0008; /* QE immr base */ qe_init(qe_base); qe_reset(); -- 1.7.3.1.50.g1e633 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 8/8] p1021mds: add QE and UEC support
From: Haiying Wang haiying.w...@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
P1021MDS has to load the microcode from NAND flash, this patch defines
misc_init_r() for loading ucode and initializing qe.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc85xx/speed.c |4 ++
arch/powerpc/include/asm/immap_85xx.h | 13 +
board/freescale/p1021mds/p1021mds.c | 82 +
drivers/qe/uec.c | 38 +++
include/configs/P1021MDS.h| 47 +++
5 files changed, 184 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index dd4c6b3..6f1aa7b 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -163,10 +163,14 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
+#ifdef CONFIG_P1021
+ sysInfo-freqQE = sysInfo-freqSystemBus;
+#else
qe_ratio = ((gur-porpllsr) MPC85xx_PORPLLSR_QE_RATIO)
MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo-freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#endif
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 9eb106c..1e4dae9 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1924,6 +1924,19 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SD_DATA 0x8000
#define MPC85xx_PMUXCR_SDHC_CD 0x4000
#define MPC85xx_PMUXCR_SDHC_WP 0x2000
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE1 0x4000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE100x0020
+#define MPC85xx_PMUXCR_QE110x0010
+#define MPC85xx_PMUXCR_QE120x0008
u32 pmuxcr2;/* Alt. function signal multiplex control 2 */
u8 res6[8];
u32 devdisr;/* Device disable control */
diff --git a/board/freescale/p1021mds/p1021mds.c
b/board/freescale/p1021mds/p1021mds.c
index 5d981e2..7d71bd7 100644
--- a/board/freescale/p1021mds/p1021mds.c
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -37,6 +37,54 @@
#include tsec.h
#include netdev.h
+#ifdef CONFIG_QE
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#include nand.h
+#include asm/errno.h
+#endif
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+#endif
+
+#ifdef CONFIG_QE
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC*/
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B*/
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B*/
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B*/
+ {0, 17, 2, 0, 2}, /* ENET1_CRS*/
+ {0, 16, 2, 0, 2}, /* ENET1_COL*/
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B*/
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B*/
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B*/
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
int board_early_init_f(void)
{
@@ -98,6 +146,14 @@ int board_eth_init(bd_t *bis)
tsec_eth_init(bis, tsec_info, num);
+#if defined(CONFIG_UEC_ETH)
+
[U-Boot] [PATCH] Introduce the Tertiary Program loader
From: Haiying Wang haiying.w...@freescale.com
TPL is introduced to enable a loader stub that boots out of some type of RAM,
after being loaded by an SPL or similar platform-specific mechanism.
One example of using this tpl loader is to initialize the ddr through spd code
in case the L2 SRAM size is not big enough to hold the final uboot image and
the nand spl code is limited to 4K byte. The tpl code will load the final uboot
image after ddr is initialized.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
It is used to replace the [PATCH 3/7] Add support for third program loader
Makefile | 14 ++
README | 27 +++
2 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
index b4aae89..e561706 100644
--- a/Makefile
+++ b/Makefile
@@ -287,6 +287,10 @@ LDPPFLAGS += \
$(shell $(LD) --version | \
sed -ne 's/GNU ld version
\([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
+ifeq ($(CONFIG_TPL_U_BOOT),y)
+TPL_BOOT = tpl
+endif
+
ifeq ($(CONFIG_NAND_U_BOOT),y)
NAND_SPL = nand_spl
U_BOOT_NAND = $(obj)u-boot-nand.bin
@@ -404,8 +408,16 @@ $(obj)u-boot.lds: $(LDSCRIPT)
$(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) depend
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
+$(TPL_BOOT): $(TIMESTAMP_FILE) $(VERSION_FILE) depend
+ $(MAKE) -C tpl/board/$(BOARDDIR) all
+
+ifeq ($(CONFIG_TPL_U_BOOT),y)
+$(U_BOOT_NAND): $(NAND_SPL) $(TPL_BOOT) $(obj)u-boot.bin
+ cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)tpl/u-boot-tpl.bin
$(obj)u-boot.bin $(obj)u-boot-nand.bin
+else
$(U_BOOT_NAND):$(NAND_SPL) $(obj)u-boot.bin
cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin
$(obj)u-boot-nand.bin
+endif
$(ONENAND_IPL):$(TIMESTAMP_FILE) $(VERSION_FILE)
$(obj)include/autoconf.mk
$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
@@ -1223,6 +1235,7 @@ clean:
@rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
+ @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.map}
@rm -f $(ONENAND_BIN)
@rm -f $(obj)onenand_ipl/u-boot.lds
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@@ -1247,6 +1260,7 @@ clobber: clean
@rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name * -type l
-print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name * -type l
-print | xargs rm -f
+ @[ ! -d $(obj)tpl ] || find $(obj)tpl -name * -type l -print | xargs
rm -f
ifeq ($(OBJTREE),$(SRCTREE))
mrproper \
diff --git a/README b/README
index 1acf9a3..53665b0 100644
--- a/README
+++ b/README
@@ -2108,6 +2108,33 @@ FIT uImage format:
Adds the MTD partitioning infrastructure from the Linux
kernel. Needed for UBI support.
+- NAND Boot Support
+ CONFIG_NAND_U_BOOT
+
+ Builds a U-Boot image that boots from NAND, prefixed by a small
+ loader stub (secondary program loader -- SPL) that loads the
+ rest of U-Boot into RAM. This symbol will be set in all build
+ phases.
+
+ CONFIG_NAND_SPL
+
+ This is set by the build system when compiling code to go into
+ the SPL. It is not set when building the code that the SPL
+ loads.
+
+- TPL Boot Support
+ CONFIG_TPL_U_BOOT
+
+ Builds a U-Boot image that contains a loader stub (tertiary
+ program loader -- TPL) that boots out of some type of RAM,
+ after being loaded by an SPL or similar platform-specific
+ mechanism. This symbol will be set in all build phases.
+
+ CONFIG_TPL_BOOT
+
+ This is set by the build system when compiling code to go into
+ the TPL. It is not set when building the code that the TPL
+ loads, or when building the SPL.
Modem Support:
--
--
1.7.3.1.50.g1e633
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[U-Boot] [PATCH 2/7] 8xxx/ddr: add support to only compute the ddr sdram size
From: Haiying Wang haiying.w...@freescale.com
This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in
case that the DDR SDRAM is initialized in the 2nd stage uboot and should not
be intialized again in the final stage uboot.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 10 -
arch/powerpc/cpu/mpc8xxx/ddr/ddr.h |8 --
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 31 +
3 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 3fec100..8fdafdb 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1176,7 +1176,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t
*popts,
fsl_ddr_cfg_regs_t *ddr,
const common_timing_params_t *common_dimm,
const dimm_params_t *dimm_params,
- unsigned int dbw_cap_adj)
+ unsigned int dbw_cap_adj,
+ unsigned int size_only)
{
unsigned int i;
unsigned int cas_latency;
@@ -1394,6 +1395,13 @@ compute_fsl_memctl_config_regs(const memctl_options_t
*popts,
printf(CS%d is disabled.\n, i);
}
+ /*
+* In the case we only need to compute the ddr sdram size, we only need
+* to set csn registers, so return from here.
+*/
+ if (size_only)
+ return 0;
+
set_ddr_eor(ddr, popts);
#if !defined(CONFIG_FSL_DDR1)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index 98acb8d..8c24131 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -55,7 +55,8 @@ typedef struct {
#define STEP_ALL 0xFFF
extern unsigned long long
-fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step);
+fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
+ unsigned int size_only);
extern const char * step_to_string(unsigned int step);
@@ -64,7 +65,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
fsl_ddr_cfg_regs_t *ddr,
const common_timing_params_t *common_dimm,
const dimm_params_t *dimm_parameters,
- unsigned int dbw_capacity_adjust);
+ unsigned int dbw_capacity_adjust,
+ unsigned int size_only);
extern unsigned int
compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 6d582e9..b89b471 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -233,7 +233,8 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
}
unsigned long long
-fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
+fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
+ unsigned int size_only)
{
unsigned int i, j;
unsigned int all_controllers_memctl_interleaving = 0;
@@ -338,7 +339,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int
start_step)
pinfo-memctl_opts[i],
ddr_reg[i], timing_params[i],
pinfo-dimm_params[i],
- dbw_capacity_adjust[i]);
+ dbw_capacity_adjust[i],
+ size_only);
}
default:
@@ -405,7 +407,7 @@ phys_size_t fsl_ddr_sdram(void)
memset(info, 0, sizeof(fsl_ddr_info_t));
/* Compute it once normally. */
- total_memory = fsl_ddr_compute(info, STEP_GET_SPD);
+ total_memory = fsl_ddr_compute(info, STEP_GET_SPD, 0);
/* Check for memory controller interleaving. */
memctl_interleaved = 0;
@@ -430,7 +432,8 @@ phys_size_t fsl_ddr_sdram(void)
info.memctl_opts[i].memctl_interleaving = 0;
[U-Boot] [PATCH 5/7] powerpc/p1021: add more P1021 defines.
From: Haiying Wang haiying.w...@freescale.com
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |6 ++
arch/powerpc/include/asm/immap_qe.h |9 +++--
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 30c64eb..9eb106c 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1963,6 +1963,12 @@ typedef struct ccsr_gur {
u8 res10b[76];
par_io_t qe_par_io[7];
u8 res10c[1600];
+#elif defined(CONFIG_P1021)
+ u8 res10b1[12];
+ u32 iovselsr;
+ u8 res10b2[60];
+ par_io_t qe_par_io[3];
+ u8 res10c[1496];
#else
u8 res10b[1868];
#endif
diff --git a/arch/powerpc/include/asm/immap_qe.h
b/arch/powerpc/include/asm/immap_qe.h
index 531cfc8..74c9013 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -3,7 +3,7 @@
* The Internal Memory Map for devices with QE on them. This
* is the superset of all QE devices (8360, etc.).
*
- * Copyright (c) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (c) 2006-2010 Freescale Semiconductor, Inc.
* Author: Shlomi Gridih grid...@freescale.com
*
* This program is free software; you can redistribute it and/or modify it
@@ -588,6 +588,9 @@ typedef struct qe_immap {
#elif defined(CONFIG_MPC8569)
u8 muram[0x2]; /* 0x1_ - 0x3_ Multi-user RAM */
u8 res17[0x1]; /* 0x3_ - 0x4_ */
+#elif defined(CONFIG_P1021)
+ u8 muram[0x06000]; /* 0x1_ - 0x1_6000 Multi-user RAM */
+ u8 res17[0x1a000]; /* 0x1_6000 - 0x3_ */
#else
u8 muram[0xC000]; /* 0x11 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x14 */
@@ -601,13 +604,15 @@ extern qe_map_t *qe_immr;
#define QE_MURAM_SIZE 0x1UL
#elif defined(CONFIG_MPC8569)
#define QE_MURAM_SIZE 0x2UL
+#elif defined(CONFIG_P1021)
+#define QE_MURAM_SIZE 0x6000UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832x)
#define QE_MURAM_SIZE 0x4000UL
#endif
-#if defined(CONFIG_MPC8323)
+#if defined(CONFIG_MPC8323) || defined(CONFIG_P1021)
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_MPC8569)
--
1.7.3.1.50.g1e633
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[U-Boot] [PATCH 1/7] powerpc/85xx: do not reloc l2srbar if CONFIG_FLASH_BASE is not defined
From: Haiying Wang haiying.w...@freescale.com
This fixes the compiling error for the board which doesn't have NOR flash
(so CONFIG_FLASH_BASE is not defined)
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 27236a0..4b8faa5 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -327,7 +327,7 @@ int cpu_init_r(void)
if (l2cache-l2ctl MPC85xx_L2CTL_L2E) {
puts(already enabled);
l2srbar = l2cache-l2srbar0;
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#if defined(CONFIG_SYS_INIT_L2_ADDR) defined(CONFIG_SYS_FLASH_BASE)
if (l2cache-l2ctl MPC85xx_L2CTL_L2SRAM_ENTIRE
l2srbar = CONFIG_SYS_FLASH_BASE) {
l2srbar = CONFIG_SYS_INIT_L2_ADDR;
--
1.7.3.1.50.g1e633
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[U-Boot] [PATCH 6/7] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash
From: Haiying Wang haiying.w...@freescale.com For some board which doesn't have NOR flash and the QE's firmware(ucode) is saved in its NAND flash, we don't want call qe_init in cpu_init_r, but will call it later after nand is initialized. Signed-off-by: Haiying Wang haiying.w...@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4b8faa5..eb34378 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -369,7 +369,7 @@ int cpu_init_r(void) enable_cpc(); -#ifdef CONFIG_QE +#if defined(CONFIG_QE) !defined(CONFIG_SYS_QE_FW_IN_NAND) uint qe_base = CONFIG_SYS_IMMR + 0x0008; /* QE immr base */ qe_init(qe_base); qe_reset(); -- 1.7.3.1.50.g1e633 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/7] Add support for third program loader
From: Haiying Wang haiying.w...@freescale.com
This patch introduces the third program loader(TPL) to load the final uboot
image after the spl code. Once the CONFIG_SYS_TPL_BOOT is defined,
the CONFIG_TPL_BOOT is enabled to generate the u-boot-tpl.bin. There are two
examples to use tpl:
1. NAND boot. The 4K NAND SPL uboot can not enable ddr through spd code because
of the 4k size limitation, and the l2/l3 as SRAM also is not large enough to
accommodate the final uboot image.
2. SD/eSPI boot. We don't want to statically init ddr in SD/eSPI's configuration
structure in ROM, but the l2/l3 SRAM size is small for final uboot.
It can also be used for other cases which need to execute the necessary init
steps before loading the final uboot image.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
Makefile | 14
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 34 ++-
arch/powerpc/cpu/mpc85xx/start.S | 11 +++
arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds | 98 ++
nand_spl/nand_boot_fsl_elbc.c|6 ++-
5 files changed, 160 insertions(+), 3 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
diff --git a/Makefile b/Makefile
index b4aae89..71aaa9c 100644
--- a/Makefile
+++ b/Makefile
@@ -287,6 +287,10 @@ LDPPFLAGS += \
$(shell $(LD) --version | \
sed -ne 's/GNU ld version
\([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
+ifeq ($(CONFIG_SYS_TPL_BOOT),y)
+TPL_BOOT = tpl
+endif
+
ifeq ($(CONFIG_NAND_U_BOOT),y)
NAND_SPL = nand_spl
U_BOOT_NAND = $(obj)u-boot-nand.bin
@@ -404,8 +408,16 @@ $(obj)u-boot.lds: $(LDSCRIPT)
$(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) depend
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
+$(TPL_BOOT): $(TIMESTAMP_FILE) $(VERSION_FILE) depend
+ $(MAKE) -C tpl/board/$(BOARDDIR) all
+
+ifeq ($(CONFIG_SYS_TPL_BOOT),y)
+$(U_BOOT_NAND): $(NAND_SPL) $(TPL_BOOT) $(obj)u-boot.bin
+ cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)tpl/u-boot-tpl.bin
$(obj)u-boot.bin $(obj)u-boot-nand.bin
+else
$(U_BOOT_NAND):$(NAND_SPL) $(obj)u-boot.bin
cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin
$(obj)u-boot-nand.bin
+endif
$(ONENAND_IPL):$(TIMESTAMP_FILE) $(VERSION_FILE)
$(obj)include/autoconf.mk
$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
@@ -1223,6 +1235,7 @@ clean:
@rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
+ @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.map}
@rm -f $(ONENAND_BIN)
@rm -f $(obj)onenand_ipl/u-boot.lds
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@@ -1247,6 +1260,7 @@ clobber: clean
@rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name * -type l
-print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name * -type l
-print | xargs rm -f
+ @[ ! -d $(obj)tpl ] || find $(obj)tpl -name * -type l -print | xargs
rm -f
ifeq ($(OBJTREE),$(SRCTREE))
mrproper \
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 8fb27ab..decedca 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -40,7 +40,8 @@ void cpu_init_f(void)
#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
#endif
-#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L2_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) defined(CONFIG_SYS_INIT_L2_ADDR) \
+!defined(CONFIG_TPL_BOOT)
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
char *l2srbar;
int i;
@@ -60,4 +61,33 @@ void cpu_init_f(void)
for (i = 0; i CONFIG_SYS_L2_SIZE; i++)
l2srbar[i] = 0;
#endif
+#ifdef CONFIG_TPL_BOOT
+ init_used_tlb_cams();
+#endif
+}
+
+#ifdef CONFIG_TPL_BOOT
+/*
+ * Because the primary cpu's info is enough for the 2nd stage, we define the
+ * cpu number to 1 so as to keep code size for 2nd stage binary as small as
+ * possible.
+ */
+int cpu_numcores()
+{
+ return 1;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Get timebase clock frequency
+ */
+unsigned long get_tbclk(void)
+{
+#ifdef CONFIG_FSL_CORENET
+ return (gd-bus_clk + 8) / 16;
+#else
+ return (gd-bus_clk + 4UL)/8UL;
+#endif
}
+#endif /* CONFIG_TPL_BOOT */
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 945c1b8..91f9eeb 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -58,12 +58,14 @@
GOT_ENTRY(_GOT2_TABLE_)
[U-Boot] [PATCH 7/7] p1021mds: add QE and UEC support
From: Haiying Wang haiying.w...@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
P1021MDS has to load the microcode from NAND flash, this patch defines
misc_init_r() for loading ucode and init qe.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc85xx/speed.c |4 ++
arch/powerpc/include/asm/immap_85xx.h | 13 +
board/freescale/p1021mds/p1021mds.c | 82 +
drivers/qe/uec.c | 38 +++
include/configs/P1021MDS.h| 45 ++
5 files changed, 182 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index dd4c6b3..6f1aa7b 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -163,10 +163,14 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
+#ifdef CONFIG_P1021
+ sysInfo-freqQE = sysInfo-freqSystemBus;
+#else
qe_ratio = ((gur-porpllsr) MPC85xx_PORPLLSR_QE_RATIO)
MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo-freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#endif
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 9eb106c..1e4dae9 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1924,6 +1924,19 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SD_DATA 0x8000
#define MPC85xx_PMUXCR_SDHC_CD 0x4000
#define MPC85xx_PMUXCR_SDHC_WP 0x2000
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE1 0x4000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE100x0020
+#define MPC85xx_PMUXCR_QE110x0010
+#define MPC85xx_PMUXCR_QE120x0008
u32 pmuxcr2;/* Alt. function signal multiplex control 2 */
u8 res6[8];
u32 devdisr;/* Device disable control */
diff --git a/board/freescale/p1021mds/p1021mds.c
b/board/freescale/p1021mds/p1021mds.c
index 5d981e2..7d71bd7 100644
--- a/board/freescale/p1021mds/p1021mds.c
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -37,6 +37,54 @@
#include tsec.h
#include netdev.h
+#ifdef CONFIG_QE
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#include nand.h
+#include asm/errno.h
+#endif
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+#endif
+
+#ifdef CONFIG_QE
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC*/
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B*/
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B*/
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B*/
+ {0, 17, 2, 0, 2}, /* ENET1_CRS*/
+ {0, 16, 2, 0, 2}, /* ENET1_COL*/
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B*/
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B*/
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B*/
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
int board_early_init_f(void)
{
@@ -98,6 +146,14 @@ int board_eth_init(bd_t *bis)
tsec_eth_init(bis, tsec_info, num);
+#if defined(CONFIG_UEC_ETH)
+ /*
[U-Boot] [PATCH 4/7] arch/powerpc: Add P1021MDS board support
From: Haiying Wang haiying.w...@freescale.com This patch supports P1021MDS board to boot from NAND flash (No NOR flash on this board). And because P1021 only has 256K L2 SRAM, can not used for final uboot image, this patch defines the CONFIG_SYS_TPL_BOOT for P1021MDS so that DDR can be initialized in L2 SRAM through SPD code. Signed-off-by: Haiying Wang haiying.w...@freescale.com Signed-off-by: Mohit Kumar mohit.ku...@freescale.com Signed-off-by: Yu.Liu yu@freescale.com --- MAINTAINERS |4 + board/freescale/p1021mds/Makefile | 53 +++ board/freescale/p1021mds/config.mk| 31 ++ board/freescale/p1021mds/ddr.c| 162 +++ board/freescale/p1021mds/law.c| 38 ++ board/freescale/p1021mds/p1021mds.c | 132 ++ board/freescale/p1021mds/pci.c| 105 + board/freescale/p1021mds/tlb.c| 102 + boards.cfg|1 + include/configs/P1021MDS.h| 566 + nand_spl/board/freescale/p1021mds/Makefile| 135 ++ nand_spl/board/freescale/p1021mds/nand_boot.c | 69 +++ tpl/board/freescale/p1021mds/Makefile | 173 tpl/board/freescale/p1021mds/tpl_boot.c | 79 14 files changed, 1650 insertions(+), 0 deletions(-) create mode 100644 board/freescale/p1021mds/Makefile create mode 100644 board/freescale/p1021mds/config.mk create mode 100644 board/freescale/p1021mds/ddr.c create mode 100644 board/freescale/p1021mds/law.c create mode 100644 board/freescale/p1021mds/p1021mds.c create mode 100644 board/freescale/p1021mds/pci.c create mode 100644 board/freescale/p1021mds/tlb.c create mode 100644 include/configs/P1021MDS.h create mode 100644 nand_spl/board/freescale/p1021mds/Makefile create mode 100644 nand_spl/board/freescale/p1021mds/nand_boot.c create mode 100644 tpl/board/freescale/p1021mds/Makefile create mode 100644 tpl/board/freescale/p1021mds/tpl_boot.c diff --git a/MAINTAINERS b/MAINTAINERS index 9258cb1..95b7d7a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17,6 +17,10 @@ # Board CPU # # +Haiying Wang haiying.w...@freescale.com + + P1021MDSP1021 + Poonam Aggrwal poonam.aggr...@freescale.com P2020RDBP2020 diff --git a/board/freescale/p1021mds/Makefile b/board/freescale/p1021mds/Makefile new file mode 100644 index 000..c3dc5cc --- /dev/null +++ b/board/freescale/p1021mds/Makefile @@ -0,0 +1,53 @@ +# +# Copyright (C) 2010 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS-y+= $(BOARD).o +COBJS-y+= law.o +COBJS-y+= tlb.o +COBJS-y+= pci.o +COBJS-y+= ddr.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/freescale/p1021mds/config.mk b/board/freescale/p1021mds/config.mk new file mode 100644 index 000..ce903f6 --- /dev/null +++ b/board/freescale/p1021mds/config.mk @@ -0,0 +1,31 @@ +# +# Copyright (C) 2010 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even
[U-Boot] [PATCH 1/2] powerpc/85xx: Fix lds for nand build
From: Haiying Wang haiying.w...@freescale.com
Fix u-boot-nand.lds and u-boot-nand_spl.lds according to:
Author: Peter Tyser pty...@xes-inc.com
Date: Wed Sep 29 14:05:56 2010 -0500
commit fbe53f59bd40b3b1ab66dc98859e26589d64d1b7
85xx: Use gc-sections to reduce image size
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc85xx/u-boot-nand.lds | 49 +-
arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds | 12 +++---
2 files changed, 15 insertions(+), 46 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
index 5fd3e6c..fa2088b 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
@@ -34,42 +34,16 @@ SECTIONS
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym: { *(.dynsym)}
- .dynstr: { *(.dynstr)}
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata: { *(.rel.rodata)}
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors: { *(.rela.ctors)}
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors: { *(.rela.dtors)}
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
-*(.text)
-*(.got1)
+*(.text*)
} :text
_etext = .;
PROVIDE (etext = .);
.rodata:
{
-*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
} :text
- .fini : { *(.fini)} =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) 0xFF00;
@@ -77,23 +51,19 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
-*(.got)
+KEEP(*(.got))
_GOT2_TABLE_ = .;
-*(.got2)
+KEEP(*(.got2))
_FIXUP_TABLE_ = .;
-*(.fixup)
+KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) 2;
__fixup_entries = (. - _FIXUP_TABLE_) 2;
.data:
{
-*(.data)
-*(.data1)
-*(.sdata)
-*(.sdata2)
-*(.dynamic)
-CONSTRUCTORS
+*(.data*)
+*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
@@ -117,7 +87,7 @@ SECTIONS
.bootpg ADDR(.text) - 0x1000 :
{
-arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
+arch/powerpc/cpu/mpc85xx/start.o KEEP(*(.bootpg))
} :text = 0x
. = ADDR(.text) + 0x8;
@@ -125,9 +95,8 @@ SECTIONS
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.sbss*)
+ *(.bss*)
*(COMMON)
} :bss
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
index 7d9cee9..b10e0f9 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
@@ -28,15 +28,15 @@ SECTIONS
{
. = 0xfff0;
.text : {
- *(.text)
+ *(.text*)
}
_etext = .;
.reloc : {
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) 2;
__fixup_entries = (. - _FIXUP_TABLE_) 2;
@@ -54,13 +54,13 @@ SECTIONS
__init_end = .;
.resetvec ADDR(.text) + 0xffc : {
- *(.resetvec)
+ KEEP(*(.resetvec))
} = 0x
__bss_start = .;
.bss : {
- *(.sbss)
- *(.bss)
+ *(.sbss*)
+ *(.bss*)
}
_end = .;
}
--
1.7.3.1.50.g1e633
___
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[U-Boot] [PATCH 2/2] powerpc/85xx: add CONFIG_SYS_TEXT_BASE_SPL for 85xx nand spl build
From: Haiying Wang haiying.w...@freescale.com Signed-off-by: Haiying Wang haiying.w...@freescale.com --- arch/powerpc/cpu/mpc85xx/start.S | 12 include/configs/MPC8536DS.h |8 ++-- include/configs/MPC8569MDS.h | 10 +++--- include/configs/P1_P2_RDB.h |8 ++-- nand_spl/board/freescale/mpc8536ds/Makefile |4 ++-- nand_spl/board/freescale/mpc8569mds/Makefile |4 ++-- nand_spl/board/freescale/p1_p2_rdb/Makefile |4 ++-- 7 files changed, 37 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 291557d..5386be7 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -146,7 +146,11 @@ _start_e500: beq 2b /* Setup interrupt vectors */ +#ifdef CONFIG_NAND_SPL + lis r1,config_sys_text_base_...@h +#else lis r1,config_sys_text_b...@h +#endif mtspr IVPR,r1 li r1,0x0100 @@ -306,11 +310,19 @@ _start_e500: lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l +#ifdef CONFIG_NAND_SPL + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE_SPL, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE_SPL, (MAS2_I|MAS2_G))@l + + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE_SPL, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE_SPL, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#else lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@h ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@l lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#endif /* CONFIG_NAND_SPL */ #endif mtspr MAS0,r6 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 8410bb7..fa9bc93 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -36,7 +36,13 @@ #ifdef CONFIG_NAND #define CONFIG_NAND_U_BOOT 1 #define CONFIG_RAMBOOT_NAND1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff0 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else #define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor */ +#endif /* CONFIG_NAND_SPL */ #endif #ifdef CONFIG_SDCARD @@ -233,8 +239,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT6 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor */ - #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 6a15da5..3199559 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -65,7 +65,13 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_NAND #define CONFIG_NAND_U_BOOT 1 #define CONFIG_RAMBOOT_NAND1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff0 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else #define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor */ +#endif #endif #ifndef CONFIG_SYS_TEXT_BASE @@ -194,8 +200,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_ERASE_TOUT6 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor */ - #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) #define CONFIG_SYS_RAMBOOT #else @@ -548,7 +552,7 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_MMC 1 +#undef CONFIG_MMC #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index b99f383..673e29d 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -46,7 +46,13 @@ #ifdef CONFIG_NAND #define CONFIG_NAND_U_BOOT 1 #define CONFIG_RAMBOOT_NAND1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff0 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else #define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor
[U-Boot] [PATCH 2/2 v2] powerpc/85xx: add CONFIG_SYS_TEXT_BASE_SPL for 85xx nand spl build
From: Haiying Wang haiying.w...@freescale.com Signed-off-by: Haiying Wang haiying.w...@freescale.com --- v2 change: remove 8569 CONFIG_MMC change which should not be in this patch. arch/powerpc/cpu/mpc85xx/start.S | 12 include/configs/MPC8536DS.h |8 ++-- include/configs/MPC8569MDS.h |8 ++-- include/configs/P1_P2_RDB.h |8 ++-- nand_spl/board/freescale/mpc8536ds/Makefile |4 ++-- nand_spl/board/freescale/mpc8569mds/Makefile |4 ++-- nand_spl/board/freescale/p1_p2_rdb/Makefile |4 ++-- 7 files changed, 36 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 291557d..5386be7 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -146,7 +146,11 @@ _start_e500: beq 2b /* Setup interrupt vectors */ +#ifdef CONFIG_NAND_SPL + lis r1,config_sys_text_base_...@h +#else lis r1,config_sys_text_b...@h +#endif mtspr IVPR,r1 li r1,0x0100 @@ -306,11 +310,19 @@ _start_e500: lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l +#ifdef CONFIG_NAND_SPL + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE_SPL, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE_SPL, (MAS2_I|MAS2_G))@l + + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE_SPL, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE_SPL, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#else lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@h ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@l lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#endif /* CONFIG_NAND_SPL */ #endif mtspr MAS0,r6 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 8410bb7..fa9bc93 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -36,7 +36,13 @@ #ifdef CONFIG_NAND #define CONFIG_NAND_U_BOOT 1 #define CONFIG_RAMBOOT_NAND1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff0 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else #define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor */ +#endif /* CONFIG_NAND_SPL */ #endif #ifdef CONFIG_SDCARD @@ -233,8 +239,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT6 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor */ - #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 6a15da5..b11076f 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -65,7 +65,13 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_NAND #define CONFIG_NAND_U_BOOT 1 #define CONFIG_RAMBOOT_NAND1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff0 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else #define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor */ +#endif #endif #ifndef CONFIG_SYS_TEXT_BASE @@ -194,8 +200,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_ERASE_TOUT6 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor */ - #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) #define CONFIG_SYS_RAMBOOT #else diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index b99f383..673e29d 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -46,7 +46,13 @@ #ifdef CONFIG_NAND #define CONFIG_NAND_U_BOOT 1 #define CONFIG_RAMBOOT_NAND1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff0 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else #define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor */ +#endif /* CONFIG_NAND_SPL */ #endif #ifdef CONFIG_SDCARD @@ -192,8 +198,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
[U-Boot] [PATCH 2/2 v3] powerpc/85xx: add CONFIG_SYS_TEXT_BASE_SPL for 85xx nand spl build
From: Haiying Wang haiying.w...@freescale.com Signed-off-by: Haiying Wang haiying.w...@freescale.com --- v3 change: %s/CONFIG_SYS_TEXT_BASE/CONFIG_SYS_MONITOR_BASE/g arch/powerpc/cpu/mpc85xx/start.S | 18 +- include/configs/MPC8536DS.h |8 ++-- include/configs/MPC8569MDS.h |8 ++-- include/configs/P1_P2_RDB.h |8 ++-- nand_spl/board/freescale/mpc8536ds/Makefile |4 ++-- nand_spl/board/freescale/mpc8569mds/Makefile |4 ++-- nand_spl/board/freescale/p1_p2_rdb/Makefile |4 ++-- 7 files changed, 33 insertions(+), 21 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 291557d..af7e39b 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -146,7 +146,7 @@ _start_e500: beq 2b /* Setup interrupt vectors */ - lis r1,config_sys_text_b...@h + lis r1,config_sys_monitor_b...@h mtspr IVPR,r1 li r1,0x0100 @@ -292,25 +292,25 @@ _start_e500: lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE 0xffc0, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE 0xffc0, (MAS2_I|MAS2_G))@l + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE 0xffc0, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE 0xffc0, (MAS2_I|MAS2_G))@l /* The 85xx has the default boot window 0xff80 - 0x */ lis r9,FSL_BOOKE_MAS3(0xffc0, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h ori r9,r9,FSL_BOOKE_MAS3(0xffc0, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l #else /* -* create a temp mapping in AS=1 to the 1M CONFIG_SYS_TEXT_BASE space, the main -* image has been relocated to CONFIG_SYS_TEXT_BASE on the second stage. +* create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main +* image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. */ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@l + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l - lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l #endif mtspr MAS0,r6 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 8410bb7..fa9bc93 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -36,7 +36,13 @@ #ifdef CONFIG_NAND #define CONFIG_NAND_U_BOOT 1 #define CONFIG_RAMBOOT_NAND1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff0 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else #define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor */ +#endif /* CONFIG_NAND_SPL */ #endif #ifdef CONFIG_SDCARD @@ -233,8 +239,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT6 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor */ - #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 6a15da5..b11076f 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -65,7 +65,13 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_NAND #define CONFIG_NAND_U_BOOT 1 #define CONFIG_RAMBOOT_NAND1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff0 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else #define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor */ +#endif #endif #ifndef CONFIG_SYS_TEXT_BASE @@ -194,8 +200,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_ERASE_TOUT6 /* Flash Erase Timeout (ms) */ #define
[U-Boot] [PATCH 2/3] mpc8569mds: fix consuming long time while relocating code.
From: Haiying Wang haiying.w...@freescale.com
The original code maps boot flash as non-cacheable region. When calling
relocate_code in flash to copy u-boot from flash to ddr, every loop copy command
is read from flash. The flash read speed will be the bottleneck, which consuming
long time to do this operation. To resovle this, map the boot flash as
write-through cache via tlb. And set tlb to remap the flash after code
executing in ddr, to confirm flash erase operation properly done.
Signed-off-by: Kai.Jiang kai.ji...@freescale.com
---
board/freescale/mpc8569mds/mpc8569mds.c | 25 +
board/freescale/mpc8569mds/tlb.c| 15 ++-
include/configs/MPC8569MDS.h|3 ++-
3 files changed, 37 insertions(+), 6 deletions(-)
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c
b/board/freescale/mpc8569mds/mpc8569mds.c
index 01b7dcb..7028ce8 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -211,6 +211,31 @@ int board_early_init_f (void)
return 0;
}
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
+ const u8 flash_esel = 0;
+
+ /*
+* Remap Boot flash to caching-inhibited
+* so that flash can be erased properly.
+*/
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, /* ts, esel */
+ BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
+
+ return 0;
+}
+
int checkboard (void)
{
printf (Board: 8569 MDS\n);
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
index 73dcc3e..f852fc3 100644
--- a/board/freescale/mpc8569mds/tlb.c
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
@@ -46,15 +46,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 Initializations */
/*
-* TLBe 0: 64M Non-cacheable, guarded
+* TLBe 0: 64M write-through, guarded
* Out of reset this entry is only 4K.
-* 0xfc00 256KNAND FLASH (CS3)
-* 0xfe00 32M NOR FLASH (CS0)
+* 0xfc00 32MBNAND FLASH (CS3)
+* 0xfe00 32MBNOR FLASH (CS0)
*/
+#ifdef CONFIG_NAND_SPL
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
-
+#endif
/*
* TLBe 1: 256KB Non-cacheable, guarded
* 0xf800 32K BCSR
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 936f1af..95c0a9f 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -74,6 +74,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R 1
#define CONFIG_HWCONFIG
#define CONFIG_SYS_MEMTEST_START 0x0020 /* memtest works on */
--
1.7.0
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[U-Boot] [PATCH 3/3] mpc8569mds: fix some ddr settings
From: Haiying Wang haiying.w...@freescale.com Enable half drive strength, set RTT to 60Ohm and set write leveling override. Signed-off-by: Haiying Wang haiying.w...@freescale.com --- board/freescale/mpc8569mds/ddr.c | 16 +--- 1 files changed, 13 insertions(+), 3 deletions(-) diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index e938788..e3f5b4a 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -77,8 +77,18 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts-write_data_delay = 2; /* -* Factors to consider for half-strength driver enable: -* - number of DIMMs installed +* Enable half drive strength */ - popts-half_strength_driver_enable = 0; + popts-half_strength_driver_enable = 1; + + /* Write leveling override */ + popts-wrlvl_en = 1; + popts-wrlvl_override = 1; + popts-wrlvl_sample = 0xa; + popts-wrlvl_start = 0x4; + + /* Rtt and Rtt_W override */ + popts-rtt_override = 1; + popts-rtt_override_value = DDR3_RTT_60_OHM; + popts-rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ } -- 1.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] mpc8569mds: fix CONFIG_ENV_SIZE
From: Haiying Wang haiying.w...@freescale.com CONFIG_ENV_SIZE of MPC8569MDS was wrongly set to CONFIG_ENV_SECT_SIZE which is 128KB, so it took longer time to do crc32 calculation for ENV than it should do. It causes the bootup for MPC8569MDS significantly slow. This patch fixs it to 0x2000(8KB), also fix the comment for CONFIG_ENV_SECT_SIZE to correct size. Signed-off-by: Kai.Jiang kai.ji...@freescale.com Signed-off-by: Haiying Wang haiying.w...@freescale.com --- include/configs/MPC8569MDS.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 8ffd458..936f1af 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -505,8 +505,8 @@ extern unsigned long get_clock_freq(void); #else #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SECT_SIZE 0x2 /* 256K(one sector) for env */ -#define CONFIG_ENV_SIZECONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE 0x2 /* 128K(one sector) for env */ +#define CONFIG_ENV_SIZE0x2000 #endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -- 1.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] mpc8569mds: fix consuming long time while relocating code.
From: Haiying Wang haiying.w...@freescale.com
The original code maps boot flash as non-cacheable region. When calling
relocate_code in flash to copy u-boot from flash to ddr, every loop copy command
is read from flash. The flash read speed will be the bottleneck, which consuming
long time to do this operation. To resovle this, map the boot flash as
write-through cache via tlb. And set tlb to remap the flash after code
executing in ddr, to confirm flash erase operation properly done.
Signed-off-by: Kai.Jiang kai.ji...@freescale.com
---
board/freescale/mpc8569mds/mpc8569mds.c | 25 +
board/freescale/mpc8569mds/tlb.c| 15 ++-
include/configs/MPC8569MDS.h|3 ++-
3 files changed, 37 insertions(+), 6 deletions(-)
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c
b/board/freescale/mpc8569mds/mpc8569mds.c
index 01b7dcb..7028ce8 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -211,6 +211,31 @@ int board_early_init_f (void)
return 0;
}
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
+ const u8 flash_esel = 0;
+
+ /*
+* Remap Boot flash to caching-inhibited
+* so that flash can be erased properly.
+*/
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, /* ts, esel */
+ BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
+
+ return 0;
+}
+
int checkboard (void)
{
printf (Board: 8569 MDS\n);
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
index 73dcc3e..f852fc3 100644
--- a/board/freescale/mpc8569mds/tlb.c
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
@@ -46,15 +46,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 Initializations */
/*
-* TLBe 0: 64M Non-cacheable, guarded
+* TLBe 0: 64M write-through, guarded
* Out of reset this entry is only 4K.
-* 0xfc00 256KNAND FLASH (CS3)
-* 0xfe00 32M NOR FLASH (CS0)
+* 0xfc00 32MBNAND FLASH (CS3)
+* 0xfe00 32MBNOR FLASH (CS0)
*/
+#ifdef CONFIG_NAND_SPL
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
-
+#endif
/*
* TLBe 1: 256KB Non-cacheable, guarded
* 0xf800 32K BCSR
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 936f1af..95c0a9f 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -74,6 +74,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R 1
#define CONFIG_HWCONFIG
#define CONFIG_SYS_MEMTEST_START 0x0020 /* memtest works on */
--
1.7.0
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[U-Boot] [PATCH 3/3] mpc8569mds: fix some ddr settings
From: Haiying Wang haiying.w...@freescale.com Enable half drive strength, set RTT to 60Ohm and set write leveling override. Signed-off-by: Haiying Wang haiying.w...@freescale.com --- board/freescale/mpc8569mds/ddr.c | 16 +--- 1 files changed, 13 insertions(+), 3 deletions(-) diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index e938788..e3f5b4a 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -77,8 +77,18 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts-write_data_delay = 2; /* -* Factors to consider for half-strength driver enable: -* - number of DIMMs installed +* Enable half drive strength */ - popts-half_strength_driver_enable = 0; + popts-half_strength_driver_enable = 1; + + /* Write leveling override */ + popts-wrlvl_en = 1; + popts-wrlvl_override = 1; + popts-wrlvl_sample = 0xa; + popts-wrlvl_start = 0x4; + + /* Rtt and Rtt_W override */ + popts-rtt_override = 1; + popts-rtt_override_value = DDR3_RTT_60_OHM; + popts-rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ } -- 1.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] mpc8569mds: fix CONFIG_ENV_SIZE
From: Haiying Wang haiying.w...@freescale.com CONFIG_ENV_SIZE of MPC8569MDS was wrongly set to CONFIG_ENV_SECT_SIZE which is 128KB, so it took longer time to do crc32 calculation for ENV than it should do. It causes the bootup for MPC8569MDS significantly slow. This patch fixs it to 0x2000(8KB), also fix the comment for CONFIG_ENV_SECT_SIZE to correct size. Signed-off-by: Kai.Jiang kai.ji...@freescale.com Signed-off-by: Haiying Wang haiying.w...@freescale.com --- include/configs/MPC8569MDS.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 8ffd458..936f1af 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -505,8 +505,8 @@ extern unsigned long get_clock_freq(void); #else #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SECT_SIZE 0x2 /* 256K(one sector) for env */ -#define CONFIG_ENV_SIZECONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE 0x2 /* 128K(one sector) for env */ +#define CONFIG_ENV_SIZE0x2000 #endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -- 1.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
