Q: sp805 watchdog is only for fsl ?

2020-08-30 Thread Ran Shalit 
Hello,

In watchdog sp805_wdt.c there is usage of gd->bus_clk which seems to
be initialized only in fsl code.
So, it seems that sp805 usage is limited to fsl chips.

I think it could have been generic for any other chip if the clock was
initialized using device tree.

What do you think?

Thanks

[U-Boot] send message on serial ports

2018-04-19 Thread Ran Shalit 
Hello,

Is it possible to send a message on different uart ports , while
leaving the console in the same port ?
Which command in common can be used for that ?

Thank you,
ranran
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Re: [U-Boot] u-boot environment tool

2018-03-29 Thread Ran Shalit 
On Thu, Mar 29, 2018 at 10:57 AM, Chris Packham <judge.pack...@gmail.com> wrote:
> On Thu, Mar 29, 2018 at 8:19 PM, Ran Shalit <ransha...@gmail.com> wrote:
>> Hello,
>>
>> Is there a tool to create u-boot environment from text and save into
>> SPI NOR flash ?
>>
>
> You'll get some mileage out of tools/env. It's intended for use on a
> target so that you can access the target's own u-boot environment from
> a Linux userland. I'm not sure if it suits your use-case or if you
> want something you can run on a different host.

I need to prepare the environment from text , then create the binary
and then program into spi nor flash.
As I understand now, it seems that this tool can do this.
https://bootlin.com/blog/mkenvimage-uboot-binary-env-generator/

 Thanks,
ranran
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[U-Boot] u-boot environment tool

2018-03-29 Thread Ran Shalit 
Hello,

Is there a tool to create u-boot environment from text and save into
SPI NOR flash ?

Thank you,
Ran
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Re: [U-Boot] tftp reliability

2017-09-18 Thread Ran Shalit 
On Tue, Sep 19, 2017 at 7:04 AM, Chris Packham <judge.pack...@gmail.com> wrote:
> On Tue, Sep 19, 2017 at 8:26 AM, Ran Shalit <ransha...@gmail.com> wrote:
>> Hello,
>>
>> Does tftp checks the integrity of the file with checksum or any other
>> similar method ? If not - how can it assure the reliability of the
>> file that was transferred ?
>
> In short it doesn't. Beyond a simple block id and ack there is nothing
> that ensures what was sent is what was received.
>
> You need to rely on something else to verify the data. Fortunately
> u-boot supports some options for doing so. At $dayjob we use FIT[1]
> images for our firmware which can include multiple hashes and even
> signatures if desired.
>
> [1] - http://git.denx.de/?p=u-boot.git;a=tree;f=doc/uImage.FIT


Chris, Bob,

Thank you very much.
Ran
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[U-Boot] tftp reliability

2017-09-18 Thread Ran Shalit 
Hello,

Does tftp checks the integrity of the file with checksum or any other
similar method ? If not - how can it assure the reliability of the
file that was transferred ?

Thank you,
Ran
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[U-Boot] standalone application

2017-06-06 Thread Ran Shalit 
Hello,

I am trying to load standalone application.
It works fine with the hello_world example ( bin format).
Then I move to build and run another application (uc/os) in eclipse.
The problem is that the bin format is very large.
Is there a way to load other a standalone application in another format ?

Regards,
Ran
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[U-Boot] AES library used for kernel loading ?

2017-03-13 Thread Ran Shalit 
Hello,

I intend to use AES for kernel loading, and before kernel programming
from u-boot.
Is there some package which already does that yet ?

Another thing, can I expect that it will work if we use openssl 128,
cbc in host for sending the file (from hoist to target) ?

I see that library support only  aes 128, cbc format, which means that
we must use this same format in host.

Thank you!
Ran
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Re: [U-Boot] i2c_set_bus_num freeze

2017-01-26 Thread Ran Shalit 
On Fri, Jan 27, 2017 at 9:08 AM, Ran Shalit <ransha...@gmail.com> wrote:

>
>
> On Fri, Jan 27, 2017 at 8:46 AM, Heiko Schocher <h...@denx.de> wrote:
>
>> Hello Ran,
>>
>> Am 26.01.2017 um 18:42 schrieb Ran Shalit:
>>
>>> Hello,
>>>
>>> I have some issue in u-boot trying to access bus #1.
>>>
>>
>> On which hardware? Is the board in mainline?
>
>
> Yes, it's TI's dm8148 (ti81xx, ti814x)
>
>>
>>
>> I can access bus #0, #2 with i2c dev 0/2
>>>
>>> I can also access bus #0,1,2 from linux.
>>>
>>> But on trying to access i2c #1 in u-boot in hangs:
>>>
>>> The function i2c_set_bus_num get stuck .
>>>
>>>
>>> ret = i2c_set_bus_num(1);
>>>
>>> <<--- never gets here .
>>>   if (ret)
>>>   printf("Failure changing bus number (%d)\n", ret);
>>>
>>> It hangs in i2c_set_bus_num->i2c_init->
>>>
>>> ..
>>>
>>>  printf("i2c_init 8\n");
>>>
>>
>> You see this printf?
>
>
> Yes, it seems to get stuck here:
>
> if (readw (I2C_CON) & I2C_CON_EN) {
> <<- we never gets here !!!
> writew (0, I2C_CON);
>
>
>
>>
>>
>> bus_initialized[current_bus] = 1;
>>> if (readw (I2C_CON) & I2C_CON_EN) {
>>> writew (0, I2C_CON);
>>> udelay (5);
>>> }
>>>
>>> writew(psc, I2C_PSC);
>>> writew(scll, I2C_SCLL);
>>> writew(sclh, I2C_SCLH);
>>>
>>> /* own address */
>>> writew (slaveadd, I2C_OA);
>>> writew (I2C_CON_EN, I2C_CON);
>>>
>>>  printf("i2c_init 9\n");  <<-- never get printed
>>> ..
>>>
>>> I have seen a similar question, yet I am doing this access after u-boot
>>> complete, and command prompt.
>>>
>>> Is anyone familiar with this ?
>>>
>>
>> Hmm.. no reason, why the last printf should not come ...
>>
>> As I do not know, on which hw ... I just can speculate ...
>>
>> Is the clock for the i2c subsystem 1 in the SoC enabled?
>>
>
> TI's DM8148.
> I remember that I once used that code and it works, so I quite amazed that
> it stopped working now.
> The board had some changes from that time when I tried the code, and the
> sw too some minor changes (i2c eerom added in bus #0),  but I really don't
> understand why it doesn't work any more :(
>
> It might be clock issue, I'll check.
>
>

I still don't understand what reason for it to get stuck in:
 if (readw (I2C_CON) & I2C_CON_EN)
It's a simple register reading, Right ?
So why should it hangs after calling ?

Regards,
Ran


>> bye,
>> Heiko
>>
>>
>>> Regards,
>>>
>>> Ran
>>> ___
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>>>
>> --
>> DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>>
>
>
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Re: [U-Boot] i2c_set_bus_num freeze

2017-01-26 Thread Ran Shalit 
On Fri, Jan 27, 2017 at 8:46 AM, Heiko Schocher <h...@denx.de> wrote:

> Hello Ran,
>
> Am 26.01.2017 um 18:42 schrieb Ran Shalit:
>
>> Hello,
>>
>> I have some issue in u-boot trying to access bus #1.
>>
>
> On which hardware? Is the board in mainline?


Yes, it's TI's dm8148 (ti81xx, ti814x)

>
>
> I can access bus #0, #2 with i2c dev 0/2
>>
>> I can also access bus #0,1,2 from linux.
>>
>> But on trying to access i2c #1 in u-boot in hangs:
>>
>> The function i2c_set_bus_num get stuck .
>>
>>
>> ret = i2c_set_bus_num(1);
>>
>> <<--- never gets here .
>>   if (ret)
>>   printf("Failure changing bus number (%d)\n", ret);
>>
>> It hangs in i2c_set_bus_num->i2c_init->
>>
>> ..
>>
>>  printf("i2c_init 8\n");
>>
>
> You see this printf?


Yes, it seems to get stuck here:

if (readw (I2C_CON) & I2C_CON_EN) {
<<- we never gets here !!!
writew (0, I2C_CON);



>
>
> bus_initialized[current_bus] = 1;
>> if (readw (I2C_CON) & I2C_CON_EN) {
>> writew (0, I2C_CON);
>> udelay (5);
>> }
>>
>> writew(psc, I2C_PSC);
>> writew(scll, I2C_SCLL);
>> writew(sclh, I2C_SCLH);
>>
>> /* own address */
>> writew (slaveadd, I2C_OA);
>> writew (I2C_CON_EN, I2C_CON);
>>
>>  printf("i2c_init 9\n");  <<-- never get printed
>> ..
>>
>> I have seen a similar question, yet I am doing this access after u-boot
>> complete, and command prompt.
>>
>> Is anyone familiar with this ?
>>
>
> Hmm.. no reason, why the last printf should not come ...
>
> As I do not know, on which hw ... I just can speculate ...
>
> Is the clock for the i2c subsystem 1 in the SoC enabled?
>

TI's DM8148.
I remember that I once used that code and it works, so I quite amazed that
it stopped working now.
The board had some changes from that time when I tried the code, and the sw
too some minor changes (i2c eerom added in bus #0),  but I really don't
understand why it doesn't work any more :(

It might be clock issue, I'll check.


>
> bye,
> Heiko
>
>
>> Regards,
>>
>> Ran
>> ___
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>>
> --
> DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>
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Re: [U-Boot] i2c_set_bus_num freeze

2017-01-26 Thread Ran Shalit 
On Jan 27, 2017 1:20 AM, "Adam Ford" <aford...@gmail.com> wrote:
>
>
>
> On Jan 26, 2017 11:44 AM, "Ran Shalit" <ransha...@gmail.com> wrote:
>>
>> Hello,
>>
>> I have some issue in u-boot trying to access bus #1.
>>
>> I can access bus #0, #2 with i2c dev 0/2
>>
>> I can also access bus #0,1,2 from linux.
>>
>> But on trying to access i2c #1 in u-boot in hangs:
>>
>> The function i2c_set_bus_num get stuck .
>>
>>
>> ret = i2c_set_bus_num(1);
>>
>> <<--- never gets here .
>>  if (ret)
>>  printf("Failure changing bus number (%d)\n", ret);
>>
>> It hangs in i2c_set_bus_num->i2c_init->
>>
>> ..
>>
>> printf("i2c_init 8\n");
>>
>> bus_initialized[current_bus] = 1;
>> if (readw (I2C_CON) & I2C_CON_EN) {
>> writew (0, I2C_CON);
>> udelay (5);
>> }
>>
>> writew(psc, I2C_PSC);
>> writew(scll, I2C_SCLL);
>> writew(sclh, I2C_SCLH);
>>
>> /* own address */
>> writew (slaveadd, I2C_OA);
>> writew (I2C_CON_EN, I2C_CON);
>>
>> printf("i2c_init 9\n");  <<-- never get printed
..
>>
>> I have seen a similar question, yet I am doing this access after u-boot
>> complete, and command prompt.
>>
>> Is anyone familiar with this ?
>>
>>
>> What platform are you using?

I am using dm8148 TI.
I suspected pinmux but it seems to be ok and it is the same pinmux used in
linux. In linux access to i2c 0,1,2 works without issues.

>
>
>
>> Regards,
>>
>> Ran
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>
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[U-Boot] i2c_set_bus_num freeze

2017-01-26 Thread Ran Shalit 
Hello,

I have some issue in u-boot trying to access bus #1.

I can access bus #0, #2 with i2c dev 0/2

I can also access bus #0,1,2 from linux.

But on trying to access i2c #1 in u-boot in hangs:

The function i2c_set_bus_num get stuck .


ret = i2c_set_bus_num(1);

<<--- never gets here .
 if (ret)
 printf("Failure changing bus number (%d)\n", ret);

It hangs in i2c_set_bus_num->i2c_init->

..

printf("i2c_init 8\n");

bus_initialized[current_bus] = 1;
if (readw (I2C_CON) & I2C_CON_EN) {
writew (0, I2C_CON);
udelay (5);
}

writew(psc, I2C_PSC);
writew(scll, I2C_SCLL);
writew(sclh, I2C_SCLH);

/* own address */
writew (slaveadd, I2C_OA);
writew (I2C_CON_EN, I2C_CON);

printf("i2c_init 9\n");  <<-- never get printed ..

I have seen a similar question, yet I am doing this access after u-boot
complete, and command prompt.

Is anyone familiar with this ?

Regards,

Ran
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[U-Boot] eeprom with i2c (instead spi)

2016-12-29 Thread Ran Shalit 
Hello,

I'm trying to use eeprom with u-boot.
I've added CONFIG_CMD_EEPROM,
But then I see that the file uses spi eeprom (because config use
CONFIG_SPI for other devices - not eeprom).
Does it mean I just need to
#undef CONFIG_SPI
at the start of cmd_eeprom.c file ?

Thank you!
Ran
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[U-Boot] eeprom - spi collides with i2c

2016-12-02 Thread Ran Shalit 
Hello,

I'm trying to use eeprom with u-boot.
I've added CONFIG_CMD_EEPROM,
But then I see that the file uses spi epprom (bacause config use
CONFIG_SPI for other devices - not eeprom).
Does it mean I just need to
#undef CONFIG_SPI
at the start of cmd_eeprom.c file ?

Thank you!
Ran
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[U-Boot] Q: erase.raw for NAND ?

2016-07-26 Thread Ran Shalit 
Hello,

I am trying to detect bad blocks in nand by erasing blocks and
checking if all bytes are 0x...
I want to include the OOB area in such testing (so that I treat them
as regular bytes in nand, which can be read,write, and erased)

In u-boot there is support for nand read.raw & write.raw, but I could
not find erase.raw (or somthing similar).

Is there some simple way to erase pages which includes the OOB area ?

Best Regards,
Ran
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[U-Boot] nand bad block identification

2016-07-26 Thread Ran Shalit 
 Hello,

I would like to ask if u-boot is capable of identifying bad blocks, as
described in the following article in section "Recognizing Bad Blocks"
(page 2).
In essence, it says that we should scan the first page in each block
and check if the first word in OOB is equal 0xff (if not - it's bad
block).

https://www.google.co.il/url?sa=t=j==s=web=1=2=0ahUKEwjS9d6a2JDOAhWQOSwKHfaoDB8QFggaMAA=https%3A%2F%2Fwww.micron.com%2F~%2Fmedia%2Fdocuments%2Fproducts%2Ftechnical-note%2Fnand-flash%2Ftn2959_bbm_in_nand_flash.pdf=AFQjCNFABBv41Z9fZRUzqTdwXIsdEGmt7w=bv.127984354,d.bGg

If not implemented - Is there some simple way we can integrate it into u-boot ?

Thanks,
Ran
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[U-Boot] can't change stdin and stdout environment

2016-03-19 Thread Ran Shalit 
Hello,

I have some strange behaviour when trying to modify stdin and stdout
in u-boot environment.
I do
$setenv stdout nc
but on watching the value
$pri stdout
stdout=serial

It always keeps serial , and it given no error on trying to modify it.

Is there any idea ?

Regards,
Ran
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Re: [U-Boot] Periodic task

2015-08-26 Thread Ran Shalit 
On Wed, Aug 26, 2015 at 7:45 AM, Heiko Schocher h...@denx.de wrote:
 Hello Ran,

 Am 25.08.2015 um 22:03 schrieb Ran Shalit:

 Hello,

 I need to do some periodic very simple task during u-boot prompt
 (while u-boot wais for commands). The task is very simple, just
 writing into a watchdog refresh register.
 But it seems that it's very difficult to hack u-boot with such periodic
 task.
 I see that main loop is waiting in loop for characters in a call to
 getc, which is a blocking command. If it was non-blocking, it might
 have help me. I'm not sure if there is a way to replace the getc with
 a non-blocking call.

 Does anyone have any idea if there is some simple way to do periodic
 task in u-boot  ?


 As you want to trigger a watchdog, have a look at
 u-boot:/drivers/watchdog
 and grep the U-Boot code for
 CONFIG_WATCHDOG
 CONFIG_HW_WATCHDOG

 bye,
 Heiko
 --


Hi Heiko,

That's a great suggestion.
I can understand from this, that there is timer interrupt in the
background for the watchdog refresh activity.

Regards,
Ran
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Re: [U-Boot] Periodic task

2015-08-26 Thread Ran Shalit 
On Wed, Aug 26, 2015 at 10:05 AM, Heiko Schocher h...@denx.de wrote:
 Hello Ran,


 Am 26.08.2015 um 08:09 schrieb Ran Shalit:

 On Wed, Aug 26, 2015 at 7:45 AM, Heiko Schocher h...@denx.de wrote:

 Hello Ran,

 Am 25.08.2015 um 22:03 schrieb Ran Shalit:


 Hello,

 I need to do some periodic very simple task during u-boot prompt
 (while u-boot wais for commands). The task is very simple, just
 writing into a watchdog refresh register.
 But it seems that it's very difficult to hack u-boot with such
 periodic
 task.
 I see that main loop is waiting in loop for characters in a call to
 getc, which is a blocking command. If it was non-blocking, it might
 have help me. I'm not sure if there is a way to replace the getc with
 a non-blocking call.

 Does anyone have any idea if there is some simple way to do periodic
 task in u-boot  ?



 As you want to trigger a watchdog, have a look at
 u-boot:/drivers/watchdog
 and grep the U-Boot code for
 CONFIG_WATCHDOG
 CONFIG_HW_WATCHDOG

 bye,
 Heiko
 --



 Hi Heiko,

 That's a great suggestion.
 I can understand from this, that there is timer interrupt in the
 background for the watchdog refresh activity.


 I do not know anything about your hw ... but timer interrupt is not
 necessary.

 WATCHDOG_RESET is called from the U-Boot code ..
 see definition in include/watchdog.h


 bye,
 Heiko
 --


Hi Heiko,

I am using PPC mpc8349 freescale.
In the arch/powerpc/lib/board.c file it does the following:

for (;;) {
WATCHDOG_RESET();
main_loop();
}

There is something in the concept of u-boot flow that I don't uunderstand.
How is it that main_loop will perdiocally return to WATCHDOG_RESET  if
it waits for keyboard activity with getc() blocking function.

Thank you for the time!
Ran
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Re: [U-Boot] Periodic task

2015-08-26 Thread Ran Shalit 
On Wed, Aug 26, 2015 at 12:29 PM, Heiko Schocher h...@denx.de wrote:
 Hello Ran,


 Am 26.08.2015 um 10:57 schrieb Ran Shalit:

 On Wed, Aug 26, 2015 at 10:05 AM, Heiko Schocher h...@denx.de wrote:

 Hello Ran,


 Am 26.08.2015 um 08:09 schrieb Ran Shalit:


 On Wed, Aug 26, 2015 at 7:45 AM, Heiko Schocher h...@denx.de wrote:


 Hello Ran,

 Am 25.08.2015 um 22:03 schrieb Ran Shalit:



 Hello,

 I need to do some periodic very simple task during u-boot prompt
 (while u-boot wais for commands). The task is very simple, just
 writing into a watchdog refresh register.
 But it seems that it's very difficult to hack u-boot with such
 periodic
 task.
 I see that main loop is waiting in loop for characters in a call to
 getc, which is a blocking command. If it was non-blocking, it might
 have help me. I'm not sure if there is a way to replace the getc with
 a non-blocking call.

 Does anyone have any idea if there is some simple way to do periodic
 task in u-boot  ?




 As you want to trigger a watchdog, have a look at
 u-boot:/drivers/watchdog
 and grep the U-Boot code for
 CONFIG_WATCHDOG
 CONFIG_HW_WATCHDOG

 bye,
 Heiko
 --




 Hi Heiko,

 That's a great suggestion.
 I can understand from this, that there is timer interrupt in the
 background for the watchdog refresh activity.



 I do not know anything about your hw ... but timer interrupt is not
 necessary.

 WATCHDOG_RESET is called from the U-Boot code ..
 see definition in include/watchdog.h


 bye,
 Heiko
 --



 Hi Heiko,

 I am using PPC mpc8349 freescale.
 In the arch/powerpc/lib/board.c file it does the following:
 
 for (;;) {
 WATCHDOG_RESET();
 main_loop();
 }

 There is something in the concept of u-boot flow that I don't uunderstand.
 How is it that main_loop will perdiocally return to WATCHDOG_RESET  if
 it waits for keyboard activity with getc() blocking function.


 Look into the serial driver: drivers/serial/ns16550.c
 NS16550_getc() triggers periodically the watchdog ...


 bye,
 Heiko
 --


Hi Heiko,

Thaks for the pointers.
I think I start to understand the general idea.
it seems that WATCHDOG_RESET is triggered wherever possible in the code flow.

Thanks very much,
Ran
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[U-Boot] Periodic task

2015-08-25 Thread Ran Shalit 
Hello,

I need to do some periodic very simple task during u-boot prompt
(while u-boot wais for commands). The task is very simple, just
writing into a watchdog refresh register.
But it seems that it's very difficult to hack u-boot with such periodic task.
I see that main loop is waiting in loop for characters in a call to
getc, which is a blocking command. If it was non-blocking, it might
have help me. I'm not sure if there is a way to replace the getc with
a non-blocking call.

Does anyone have any idea if there is some simple way to do periodic
task in u-boot  ?

Regards,

Ran
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[U-Boot] Environement in NVRAM

2012-06-17 Thread Ran Shalit 
Hello,

Is there a way to save environemnet in NVRAM ?
I did not find any information about that.

Best Regards,
Ran
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[U-Boot] Atmel spi flash

2012-02-19 Thread Ran Shalit 
Hello,

I am using U-boot with Atmel SPI flash AT45DB321D.
After erase command (using sf erase)  and reading the first page (sf
read) in the block, I see that the whole page is filled with 0x...
( just as expected)
But then on writing any byte in any offset in the page (using sf
write) and reading the page after that to see its contents, I see that
the specific byte value is correct, but surprisingly I also see values
of other bytes in the page (in different offset) which were written
before the last erase.
I would like to ask if anyone is familiar with such kind of problem
before I get more deeply into the atmel driver.

Best Regards,

Ran
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Re: [U-Boot] Q: Bad bits in Nand Write

2012-02-17 Thread Ran Shalit 
On Thu, Feb 16, 2012 at 9:21 PM, Scott Wood scottw...@freescale.com wrote:
 On 02/14/2012 09:05 AM, Ran Shalit wrote:
 Hello,

 I am using Micron Nand MT29F1G08ABC , with OMAP-L138 board, and I
 write the Nand with the following sequence in U-Boot:
 1. erase block
 2, read complete page change the first byte and then write back the
 complete page (2048 bytes)
 3, read complete page change the next byte and then write back the
 complete page (2048 bytes)
 4. back to 3. until page is written completely

 What I see is that after about ~1200 bytes, bytes which are after the
 last offset such as 1400 and 1500 offset are not 0xff but instead one
 of the bits is zero (such as 0xbf)
 What Do you think might be the problem here ...

 Read the manual for your NAND chip -- this is almost certainly violating
 the chip's specs.  There's a limit on the number of partial programmings
 that you can do to a page in between erases.  1, 4, and 8 are common
 limits.  2048 is not.

 -Scott

Hi Scott,
I checked and it is truely said in the manual, and no one was aware
about this limitation (4 page writes) in the design stage.
It is also interesting to add that the manual says that randsom pages
write is prohibeted (only sequential pages). I understand from this
that it is allowed to write the same page 4 times before moving to the
next (sequential) page.
Thank you! Ran
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[U-Boot] Q: Bad bits in Nand Write

2012-02-14 Thread Ran Shalit 
Hello,

I am using Micron Nand MT29F1G08ABC , with OMAP-L138 board, and I
write the Nand with the following sequence in U-Boot:
1. erase block
2, read complete page change the first byte and then write back the
complete page (2048 bytes)
3, read complete page change the next byte and then write back the
complete page (2048 bytes)
4. back to 3. until page is written completely

What I see is that after about ~1200 bytes, bytes which are after the
last offset such as 1400 and 1500 offset are not 0xff but instead one
of the bits is zero (such as 0xbf)
What Do you think might be the problem here ...

Is it that the writing sequence is wrong ? Is it that I write too many
times into page after only one erase ? Is it the driver of Nand Micron
?

I thank you for any idea or Guidance,

Regards,

Ran
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Re: [U-Boot] stuck after redirecting stdout to nc

2012-01-06 Thread Ran Shalit 
On Fri, Jan 6, 2012 at 1:26 AM, Mike Frysinger vap...@gentoo.org wrote:

 On Monday 02 January 2012 09:50:42 ran shalit wrote:
  On uboot loading, I checking a specific environement (called
 consoleddev),
  to decide to rediect console to nc or staying in serial.
  I then see some strange behaviour:
  if the environment tell uboot to redirect to net console, everything
 works
  well, but only if the ethernet cable is connected. if it is not connected
  then I see that the kernel is not loading.

 there could easily be a bug where netconsole does not work if the network
 is
 not available.  patches welcome to add timeouts.
 -mike

Do you think such bug is independent of architecture type ?
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Re: [U-Boot] stuck after redirecting stdout to nc

2012-01-06 Thread Ran Shalit 
On Fri, Jan 6, 2012 at 11:18 AM, Wolfgang Denk w...@denx.de wrote:

 Dear Ran Shalit,

 In message CAJ2oMhKLcdT_NFjbfcJ4O7kGz+B-TK93MWynb4=F02iLnBB=
 s...@mail.gmail.com you wrote:
 
  Do you think such bug is independent of architecture type ?

 This is impossible to say without knowing where and what the bug is.

 Best regards,

 Wolfgang Denk


 You're right.
What I did see in my tests is as follows:
1. only if there is connection to PC and the PC's interface ip is the same
as the ncip environement, then and only then, I see that the u-boot finish
its job and starts the bootcmd, and loading the kernel. I also see the
u-boot prints in the ethernet if I start netconsole, but event without
starting netconsole, the kernel starts (as expected)
2. Otherwise, if the network interface ip is not the same as ncip, or cable
is disconnected the u-boot does not start bootcmd, and I actually do not
know where it stoped and why.

Please tell me if you have any advice where to look, and what should be
checked,

Best Regards,
Ran
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[U-Boot] stuck after redirecting stdout to nc

2012-01-02 Thread ran shalit 

Hello,

On uboot loading, I checking a specific environement (called consoleddev),
to decide to rediect console to nc or staying in serial.
I then see some strange behaviour:
if the environment tell uboot to redirect to net console, everything works
well, but only if the ethernet cable is connected. if it is not connected
then I see that the kernel is not loading. 

*relevant environemets:
ncip 192.168.3.10
ipaddr 192.168.3.33

I would appreciate your advice,

Regards,

Ran
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Re: [U-Boot] Q: NAND read/write: unaligned offset

2011-07-02 Thread Ran Shalit 

   When using nand_write_skip_bad, the aligned offset refers to page (not
  sector or block), so if as I understand , I can read from the start of
  page the whole relevant data, then modify only the parts which is
 changed,

 That's not the same thing as just filling in the parts you're not writing
 with 0xFFs, but still it's not safe unless you erase the block.  Even if
 the
 main portion of the page doesn't contain any bits that go from 0 to 1, and
 you've got the data to calculate the proper new ECC, the ECC itself will
 probably have bits going from 0 to 1.

 Plus, some chips may not take writing 0xFFs as a no-op -- see the
 recent patches to support skipping pages with all 0xFFs on write.

 -Scott

 I wanted to write different parts of the page each time. And now I
undertsand that
the ECC is stored for each page, which mean that what I am trying to do , is
impossible  (if I am using ecc),
i.e. writing the same page without erasing is not allowed when using ecc. Am
I right about this conclusion ?

Thanks, Ran
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[U-Boot] Q: NAND read/write: unaligned offset

2011-07-01 Thread Ran Shalit 
Hello,

I am trying to read\write NAND from unaligned offset  length.
I saw Scott Wood patch in
http://lists.denx.de/pipermail/u-boot/2010-August/076435.html for allowing
unaligned length, but I see that it still demands unaligned offset in write,
and also the patch added demand for unaligned offset in reading too.
My question: Should I wrap the call to
nand_read_skip_bad\nand_write_skip_bad to that I will call the function with
aligned offset and then retrieve the data parts which I am intereseted in
(for the write I should also wrap the data of start of page with
F...),
or Is there a way to patch nand_read_skip_bad\nand_write_skip_bad in a way
that I will be able to read\write from unaligned offset ?

Thank you very much for your time,

Ran
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Re: [U-Boot] Q: NAND read/write: unaligned offset

2011-07-01 Thread Ran Shalit 



 For writes, you'll need to do a read-modify-write sequence on the entire
 block, after you determine what the proper block is given prior
 block-skipping.  Or better, don't try to use this simplistic mechanism to
 do writes in the middle of a partition -- use something like ubi that was
 meant for this.

 -Scott


Hello Scott,

Thank you for the kind reply. Is it also possible instead of using
read-modify-write which you've suggested, just to call the
nand_write_skip_bad (the patch version) with 0x...  at the start of
partition, so that nand_write_skip_bad is given aligned offset  unaligned
length? As I undesratnd, an attempt to write ff in nand will result in no
change of data.

Best Regards,

Ran
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Re: [U-Boot] Q: NAND read/write: unaligned offset

2011-07-01 Thread Ran Shalit 
For writes, you'll need to do a read-modify-write sequence on the entire
block, after you determine what the proper block is given prior
block-skipping.  Or better, don't try to use this simplistic mechanism to
do writes in the middle of a partition -- use something like ubi that was
meant for this.
-Scott

 Thank you for the kind reply. Is it also possible instead of using
 read-modify-write which you've suggested, just to call the
 nand_write_skip_bad (the patch version) with 0x...  at the start of
 partition, so that nand_write_skip_bad is given aligned offset  unaligned
 length? As I undesratnd, an attempt to write ff in nand will result in
no
 change of data.

This will result in improper ECC being written.

-Scott

I might be missing something...
 When using nand_write_skip_bad, the aligned offset refers to page (not
sector or block), so if as I understand , I can read from the start of page
the whole relevant data, then modify only the parts which is changed, and
then write it again, but the writing is not for the entire block: I will use
the  nand_write_skip_bad given offset of  the start of page, and length will
be the unaligned length for the whole data being written (which is part of
the entire block).

Ran
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Re: [U-Boot] Q: NAND read/write: unaligned offset

2011-07-01 Thread Ran Shalit 
On Fri, Jul 1, 2011 at 1:42 PM, Scott Wood scottw...@freescale.com wrote:

 On Fri, 1 Jul 2011 13:29:41 -0700
 Ran Shalit ransha...@gmail.com wrote:

  I might be missing something...
   When using nand_write_skip_bad, the aligned offset refers to page (not
  sector or block), so if as I understand , I can read from the start of
  page the whole relevant data, then modify only the parts which is
 changed,

 That's not the same thing as just filling in the parts you're not writing
 with 0xFFs, but still it's not safe unless you erase the block.  Even if
 the
 main portion of the page doesn't contain any bits that go from 0 to 1, and
 you've got the data to calculate the proper new ECC, the ECC itself will
 probably have bits going from 0 to 1.

 Plus, some chips may not take writing 0xFFs as a no-op -- see the
 recent patches to support skipping pages with all 0xFFs on write.

  and then write it again, but the writing is not for the entire block: I
 will
  use the  nand_write_skip_bad given offset of  the start of page, and
 length
  will be the unaligned length for the whole data being written (which is
 part
  of the entire block).

 If you're going to keep things page-aligned but just not block-aligned,
 you'll be OK as far as ECC and such goes, but you're on your own for making
 sure you've accounted for any previous bad blocks that were supposed to be
 skipped.

 What is the high-level goal you're trying to accomplish?

 -Scott


The high-level Goal is writingreading data which reside in unaligned
offset with unaligned data.
I hoped that I'll accomplish that by using my own functions which will
call the nand_write_skip_bad  nand_read_skip_bad with some sort
of read-modify-write method, or (other option I thought of) by adding patch
to the nand_write_skip_badnand_read_skip_bad  functions, so that they will
handle unaligned offsetdata. As I understand doing the second option right
might be more complex.

Ran

Ran
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Re: [U-Boot] bank8 in OMAP-L138 ?

2011-05-23 Thread Ran Shalit 
On Sun, May 22, 2011 at 9:55 PM, Ran Shalit ransha...@gmail.com wrote:

  Hello,

 It seems that bank 8 is missing in
  [u-boot.git] http://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=tree /
 arch http://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=tree;f=arch /
 arm http://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=tree;f=arch/arm/
 includehttp://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=tree;f=arch/arm/include/
 asmhttp://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=tree;f=arch/arm/include/asm/
 arch-davincihttp://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=tree;f=arch/arm/include/asm/arch-davinci/
 gpio_defs.hhttp://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=blob_plain;f=arch/arm/include/asm/arch-davinci/gpio_defs.h
 reference for bank 8 can be found in TI document:
 http://focus.ti.com/docs/prod/folders/print/omap-l138.html

 I have tried to add it to my code as following:

 #ifndef CONFIG_SOC_DA8XX
 #define DAVINCI_GPIO_BINTEN0x01C67008
 #define DAVINCI_GPIO_BANK010x01C67010
 #define DAVINCI_GPIO_BANK230x01C67038
 #define DAVINCI_GPIO_BANK450x01C67060
 #define DAVINCI_GPIO_BANK670x01C67088
 + #define DAVINCI_GPIO_BANK80x01C670B0
 #else /* CONFIG_SOC_DA8XX */
 #define DAVINCI_GPIO_BINTEN0x01E26008
 #define DAVINCI_GPIO_BANK010x01E26010
 #define DAVINCI_GPIO_BANK230x01E26038
 #define DAVINCI_GPIO_BANK450x01E26060
 #define DAVINCI_GPIO_BANK670x01E26088
 +#define DAVINCI_GPIO_BANK80x01E260B0
 #endif /* CONFIG_SOC_DA8XX */

 #define davinci_gpio_bank01 ((structI  davinci_gpio *)DAVINCI_GPIO_BANK01)
 #define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
 #define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
 #define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
 +#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
 The thing is that on accesing bank 8  the u-boot crashes. Is there any
 memory allocation or power management of bank 8 that I am not familiar with
 ?

 Regards,
  Ran


Hello,

I am still unsure as to what can be the problem, if anyone can please send
any idea...
Thank you!
Ran
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[U-Boot] bank8 im OMAP-L138

2011-05-22 Thread Ran Shalit 
Hello,

It seems that bank 8 is missing in
 [u-boot.git] http://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=tree /
arch http://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=tree;f=arch
/ armhttp://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=tree;f=arch/arm/
includehttp://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=tree;f=arch/arm/include/
asmhttp://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=tree;f=arch/arm/include/asm/
arch-davincihttp://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=tree;f=arch/arm/include/asm/arch-davinci/
gpio_defs.hhttp://e2e.ti.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=blob_plain;f=arch/arm/include/asm/arch-davinci/gpio_defs.h
reference for bank 8 can be found in TI document:
http://focus.ti.com/docs/prod/folders/print/omap-l138.html

I have tried to add it to my code as following:

#ifndef CONFIG_SOC_DA8XX
#define DAVINCI_GPIO_BINTEN0x01C67008
#define DAVINCI_GPIO_BANK010x01C67010
#define DAVINCI_GPIO_BANK230x01C67038
#define DAVINCI_GPIO_BANK450x01C67060
#define DAVINCI_GPIO_BANK670x01C67088
+ #define DAVINCI_GPIO_BANK80x01C670B0
#else /* CONFIG_SOC_DA8XX */
#define DAVINCI_GPIO_BINTEN0x01E26008
#define DAVINCI_GPIO_BANK010x01E26010
#define DAVINCI_GPIO_BANK230x01E26038
#define DAVINCI_GPIO_BANK450x01E26060
#define DAVINCI_GPIO_BANK670x01E26088
+#define DAVINCI_GPIO_BANK80x01E260B0
#endif /* CONFIG_SOC_DA8XX */

#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
+#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
The thing is that on accesing bank 8  the u-boot crashes. Is there any
memory allocation or power management of bank 8 that I am not familiar with
?

Regards,
 Ran
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Re: [U-Boot] ramtron f-ram

2011-04-12 Thread Ran Shalit 
Hello,

I use the spi interfaces with more then one flash in the U-Boot. Actually I
use one spi fram(ramtron) and one spi flash (stmicro).
I first thought that configuring both flags is just what I need:
CONFIG_SPI_FLASH_STMICRO
CONFIG_SPI_FLASH_RAMTRON
But since the ramtron implementation change the value of IDCODE_CONT_LEN, I
will get that this constant (IDCODE_CONT_LEN)
is OK for one flash but wrong in the other. I had no choice but to make
changes in the code for my case. just wandered if there is
really such limitation (that I cannot use ramtron  other spi flash
together).
Best Regards,
Ran

+++ b/drivers/mtd/spi/spi_flash.c
@@ -146,10 +146,18 @@ static const struct {
 #ifdef CONFIG_SPI_FLASH_WINBOND
  { 0, 0xef, spi_flash_probe_winbond, },
 #endif
+#ifdef CONFIG_SPI_FRAM_RAMTRON
+ { 6, 0xc2, spi_fram_probe_ramtron, },
*+# undef IDCODE_CONT_LEN
+# define IDCODE_CONT_LEN 6
*+#endif
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Re: [U-Boot] SPI - cs validity

2011-04-06 Thread Ran Shalit 
 It seems that currently both atmel  davinci boards supports only 1 spi
 instance at a time.

 In order to support different spi instances,
 In case of atmel declare SPIx_BASE as required  set CONFIG_DEFAULT_SPI_BUS
 to required bus
 In case of davinci set CONFIG_SYS_SPI_BASE to base address of required spi
 instance

 Also, spi_cs_is_valid() function needs to be updated to support different
 spi instances. spi_cs_is_valid() function is board dependednt.

 Hope this helps.

 Regards,
 Gururaja



Hi Gururaja,

It seems that the implementation limit the validity only for bus==0. This
means that trying other bus(=spi port ?)  will fail even if its not at the
same time. In addition to that the CPU's data sheet make no limit.

Best Regards,
Ran
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[U-Boot] SPI - cs validity

2011-04-05 Thread Ran Shalit 
Hello,

I am trying to understand the logic behind the implementation of SPI
interface, and came across a validity routine (for different baords it is
about the same):

for Atmel and Davinci for example:

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
 return bus == 0  cs == 0;
}

Althout atmel and davinci can have more then one spi port, it seems that
they will fail in configuration if bus is different then 0.
I wander if any one can solve this issue for me.

Many Thanks,

Ran
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Re: [U-Boot] Q: nand usage

2011-03-18 Thread ran shalit 

Hello,

I think my question was not very well expressed. I ment to ask about the
mapping of the partitions inside the NAND: Does each partitions need some
spare blocks (padding block) becuase of the bad block skipping in the Nand ?
As I said, I did not find any information about the strategy of mapping
partitions in the Nand. 

Best Regards,

Ran
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Re: [U-Boot] Q: nand usage

2011-03-18 Thread ran shalit 



wd wrote:
 
 
 I think my question was not very well expressed. I ment to ask about the
 mapping of the partitions inside the NAND: Does each partitions need some
 spare blocks (padding block) becuase of the bad block skipping in the
 Nand ?
 As I said, I did not find any information about the strategy of mapping
 partitions in the Nand. 
 
 As you are talking about partitions, I assume you refert to the MTD
 partitioning.  In this case the bad block handling needs to be done in
 by the file system code, when you create a file system insinde one of
 the partitions.
 
 [Note that this differs from UBI, where bad block handling is done for
 the whole device, independent of the volumes that you create on top of
 it.]
 
 

Sorry, I probably use the wrong terms in my question. I do not mean
partition using file system,
but just saving files using the u-boot interface, for example saving the
kernel file in some space in the NAND and for the u-boot file in another
space in the NAND, and all done with the given write command in the uboot
(nand write...). And again with this u-boot interface I still need some
strategy for deciding where to put each file.

Thanks again,

Ran
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[U-Boot] Q: nand usage

2011-03-17 Thread Ran Shalit 
Hello,

When using the nand, with regards to its implementation in U-boot or linux,
does a good strategy would be to map Nand to areas with *space* between the
end of one area to the start on another ? It seems a good ideas becuase of
the bad block issue and the skipping of bad blocks. I did not find
information about the Nand usage.

Best Regards,

Ran
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[U-Boot] Q: MII read

2011-03-13 Thread Ran Shalit 
Hello,

I would like to ask a question regarding the MII functionality :
When using mii commands (cmd_mii.c) everything works well, until trying to
do a ping (using net command).
After any ping try(with success or not), the mii read function is
stuck.  Maybe it has to do with davinci mii implementation, but I am not
sure if this is the problem or not.
Any advice is welcomed.

Regards,

Ran
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[U-Boot] multiple serial

2011-03-04 Thread Ran Shalit 
Hello,
I am trying to undertsnad the multiple serial configuration/usage in u-boot.
in 
dochttp://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=tree;f=doc;hb=42d44f631c4e8e5359775bdc098f2fffde4e5c05/
README.serial_multihttp://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=blob_plain;f=doc/README.serial_multi;hb=42d44f631c4e8e5359775bdc098f2fffde4e5c05
it
is said:

* 1* The support for multiple serial interfaces as implemented is mainly
2http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=blob;f=doc/README.serial_multi;h=ad61d4261b66a00564c741db0176ca51ecece408;hb=42d44f631c4e8e5359775bdc098f2fffde4e5c05#l2intended
to allow for modem dial-in / dial-out while still being able
3http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=blob;f=doc/README.serial_multi;h=ad61d4261b66a00564c741db0176ca51ecece408;hb=42d44f631c4e8e5359775bdc098f2fffde4e5c05#l3to
use a serial console on a (different) serial port.

I am not sure I undertand what is ment in the
words modem dial-in / dial-out.
What is actually the benefit of using multiple serial (#define
CONFIG_MULTI_SERIAL) instead of using direcet call to ns15669 driver (for
the UART'S which are not the console).
If we have a case where there is only one same UART which is the console, is
there any benefit of multiple serial ?

Best Regards,

Ran
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[U-Boot] question: ns16550 clock

2011-03-01 Thread Ran Shalit 
Hello,
I am using multiple serials (all UART'S) , and I am confused as to the
meaning of the ns16550 clock.
By default it is defined :

#define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)

But if ns16550 driver is the same for all UART'S, it seems wrong to define
it to depend on UART2 clock only  (UART2 is the console) . Should I change
this definition ?

Regards,

Ran
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Re: [U-Boot] question: multiple serial

2011-02-27 Thread ran shalit 



Stefano Babic wrote:
 
 On 02/24/2011 09:53 PM, Ran Shalit wrote:
 Hello,
 
 I try to understand what is the right way in U-Boot to configure multiple
 serials.
 
 That is correct.
 
 I use in my board more 3 UART's , one of them is the console.
 Should I define config_serial_multi ?
 
 Yes
 
 when I did try to do so, I got
 #error No default console though UART2 is defined as console. Could it
 be
 that da850evm does not support configuration of multiple serials ?
 
 The da850evm uses the NS16550 driver, and multiple uarts are supported.
 It seems to me you have not set CONFIG_CONS_INDEX in your config file.
 
 Best regards,
 Stefano Babic
 
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Hello Stafno,

Thank you for the reply.
The strange thing is that although the OMAP L138 have the ability for using
more then one UART, it seems that in the u-boot, it is not well supported:
Only if I add in /common/serial.c the following line:
line 45: || defined (CONFIG_MACH_DAVINCI_DA850EVM), and same include in
/common/serial.h
then compiler error is solved. it is as if this file support several cpu's
but the OMAP is not one of them. Is It correct to add this flags in order to
support multiple serials in OMAP L138 EVM ? I tried to ask in TI forum, but
got no reply yet.

Thank you very much,

Ran
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Re: [U-Boot] question: multiple serial

2011-02-27 Thread ran shalit 

Hi,

In the same subject of multiple serials, there is something else which I am
not sure about: All the serial use the same driver (NS16550), but in the
board h. file (da850evm.h) there is the following definition:
#define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
UART2 is the console, but does it mean that the ns16550 CLK, which is used
for the other uart's too should be defined as clk_get(DAVINCI_UART2_CLKID) ?  
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[U-Boot] question: multiple serial

2011-02-24 Thread Ran Shalit 
Hello,

I try to understand what is the right way in U-Boot to configure multiple
serials. I use in my board more 3 UART's , one of them is the console.
Should I define config_serial_multi ? when I did try to do so, I got
#error No default console though UART2 is defined as console. Could it be
that da850evm does not support configuration of multiple serials ?

Thank you very much,

Ran
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[U-Boot] write to mcBsp address space

2011-02-14 Thread Ran Shalit 
Hello,

I'm working on OMAPL138 EVM board, with the U-BOOT.
I'm trying to access and write into the register (which have write bits),
but I always read 0 in all the map space of the mcBSP0 and mcBSP1.
(0x01d1 - 0x1d10800, 0x01d11000 - 0x1d11800).
I wonder what I missed here. any ideas are welcomed.

Thank you very much,

Ran
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[U-Boot] multiple serial in evaluation board

2011-02-04 Thread Ran Shalit 
Hello,

I would like to configure multiple serial (UART's) in the OMAP l-138
evaluation board (da850evm). I thought that in the serial section of the
da850evm.h I should only add CONFIG_SERIAL_MULTI, but then I got compilation
problem: \common\serial.c
 #error No default console .
It also seem that this file is only being compiled when using the
CONFIG_SERIAL_MULTI flag.

I can also add that I thought it is better to use that flag becuase I want
to use the functions in \drivers\serial\serial.c such as serial_getc_dev
instead of _serial_getc, but I see that inorder to use this function I need
to define this flag (CONFIG_SERIAL_MULTI)
Should this flag  be used whenever using more then one UART ?

I appreciate your help!

Ran
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