https://github.com/qemu/qemu/commit/fa9079a86d94c202c316c97ca2eb61ca3e763907
Author: Richard Henderson
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/vis_helper.c
Log Message:
---
target/sparc: Fix ARRAY8
Follow the Oracle Sparc 2015 implementation note and
This operation returns the high 16 bits of a 24-bit multiply
that has been sign-extended to 32 bits.
Signed-off-by: Richard Henderson
---
target/sparc/vis_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/cpu-feature.h.inc | 1 +
target/sparc/translate.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc
index e2e6de9144..be81005237
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/insns.decode | 3 +++
target/sparc/translate.c | 14 ++
2 files changed, 17 insertions(+)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 056fba98f9..5d1c55aa78 100644
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 4
target/sparc/insns.decode | 5 +
target/sparc/translate.c | 9 +
target/sparc/vis_helper.c | 40 +++
4 files changed, 58 insertions
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/insns.decode | 2 ++
target/sparc/translate.c | 14 ++
2 files changed, 16 insertions(+)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 2ebee5a1ca..a7720560f8 100644
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/cpu-feature.h.inc | 1 +
target/sparc/insns.decode | 3 +++
linux-user/elfload.c | 1 +
target/sparc/cpu.c | 3 +++
target/sparc/translate.c | 24
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/insns.decode | 9 +
target/sparc/translate.c | 82 +++
2 files changed, 91 insertions(+)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index
Form the proper register decoding from the start.
Because we're removing the translation from the inner-most
gen_load_fpr_* and gen_store_fpr_* routines, this must be
done for all insns at once.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/insns.decode
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 2 ++
target/sparc/insns.decode | 9 +
target/sparc/translate.c | 11 +++
target/sparc/vis_helper.c | 36
4 files changed, 58 insertions
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/insns.decode | 1 +
target/sparc/translate.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index a7720560f8..fbcb4f7aef 100644
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/insns.decode | 14 ++
target/sparc/translate.c | 14 ++
2 files changed, 28 insertions(+)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index be591171ad
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 1 +
target/sparc/insns.decode | 1 +
target/sparc/translate.c | 32
target/sparc/vis_helper.c | 23 +++
4 files changed, 57 insertions
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/insns.decode | 2 ++
target/sparc/translate.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index febd1a4a13..70ca41a69a 100644
--- a/target
Use explicit loads and stores to env instead.
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 158 +--
1 file changed, 84 insertions(+), 74 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 750a3e6554
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 1 +
target/sparc/cpu.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 6a1457346a..cb79580431 100644
--- a/linux-user/elfload.c
+++ b
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/insns.decode | 1 +
target/sparc/translate.c | 8
2 files changed, 9 insertions(+)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 09c8adca37..508175eccd 100644
--- a/target
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 5 +++
target/sparc/insns.decode | 11 ++
target/sparc/fop_helper.c | 68 +++
target/sparc/translate.c | 76 +++
4 files changed, 160 insertions(+)
diff
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 3 +++
target/sparc/insns.decode | 4
target/sparc/translate.c | 13 +
target/sparc/vis_helper.c | 38 ++
4 files changed, 58 insertions
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/insns.decode | 9 +
target/sparc/translate.c | 11 +++
2 files changed, 20 insertions(+)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 0913fe7a86..80579642d1
for BLKBSZSET
Michael Vogt (1):
linux-user: Add ioctl for BLKBSZSET
Richard Henderson (37):
target/sparc: Fix ARRAY8
target/sparc: Rewrite gen_edge
target/sparc: Fix do_dc
target/sparc: Fix helper_fmul8ulx16
The manual separates VIS 3 and VIS 3B, even though they are both
present in all extant cpus. For clarity, let the translator
match the manual but otherwise leave them on the same feature bit.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/cpu
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 88da5254e8..9bacfb68cb 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -552,6 +552,7
VIS4 completes the set, adding missing signed 8-bit ops
and missing unsigned 16 and 32-bit ops.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 12 +--
target/sparc/insns.decode | 6 ++
target/sparc/translate.c | 12 +++
target/sparc
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 2 ++
target/sparc/insns.decode | 2 ++
target/sparc/translate.c | 4
target/sparc/vis_helper.c | 11 +++
4 files changed, 19 insertions(+)
diff --git a/target/sparc/helper.h b
Follow the Oracle Sparc 2015 implementation note and bound
the input value of N to 5 from the lower 3 bits of rs2.
Spell out all of the intermediate values, matching the diagram
in the manual. Fix extraction of upper_x and upper_y for N=0.
Signed-off-by: Richard Henderson
---
target/sparc
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 1 +
target/sparc/insns.decode | 1 +
target/sparc/translate.c | 30 ++
target/sparc/vis_helper.c | 21 +
4 files changed, 53 insertions
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 1 +
target/sparc/insns.decode | 1 +
target/sparc/fop_helper.c | 6 ++
target/sparc/translate.c | 11 +--
4 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/target
Signed-off-by: Richard Henderson
---
target/sparc/helper.h | 2 ++
target/sparc/insns.decode | 4
target/sparc/fop_helper.c | 46 +++
target/sparc/translate.c | 34 +
4 files changed, 86 insertions(+)
diff --git
Apply DFPREG to compute the register number.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 00c2a11353..1eb1a6decf 100644
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/insns.decode | 1 +
target/sparc/translate.c | 33 ++---
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
Ignore the "monitor" portion and treat them the same
as their base ASIs.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/asi.h | 4
target/sparc/ldst_helper.c | 4
target/sparc/translate.c | 8
3 files changed, 16
From: Michael Vogt
Tiny patch to add the ioctl wrapper definition for BLKBSZSET.
Signed-off-by: Michael Vogt
Message-Id: <20240423152438.19841-2-mv...@redhat.com>
---
linux-user/ioctls.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h
index
Replace with tcg_temp_new_i64.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 27 +++
1 file changed, 11 insertions(+), 16 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index
Drop the tables and compute the left and right edges directly.
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 98 +++-
1 file changed, 37 insertions(+), 61 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index
tus
Just so that when we need to look through the Inappropriate patches
(once we're cleared all the Pending) we can know what these ones are at
a glance.
Cheers,
Richard
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View/Reply Online (#200376):
https://lists.openem
> Am 05.06.2024 um 18:39 schrieb Qing Zhao :
>
>
>
>> On Jun 5, 2024, at 03:26, Richard Biener wrote:
>>
>>> On Tue, Jun 4, 2024 at 10:31 PM Qing Zhao wrote:
>>>
>>>
>>>
>>>> On Jun 4, 2024, at 03:43, Richard Bien
CPUINFO_SSE4 is dead.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
Commit: 294ac64e459aca023f43441651d860980c9784f1
https://github.com/qemu/qemu/commit/294ac64e459aca023f43441651d860980c9784f1
Author: Paolo Bonzini
Date: 2024
On 6/5/24 04:02, Paolo Bonzini wrote:
The following changes since commit 3ab42e46acf867c45bc929fcc37693e327a35a24:
Merge tag 'pull-ufs-20240603' ofhttps://gitlab.com/jeuk20.kim/qemu into
staging (2024-06-03 08:18:14 -0500)
are available in the Git repository at:
On 6/5/24 11:11, Jonathan Cameron wrote:
Sure. By what incantation do I produce a dump?
If you still have the /mnt/aml-GHR602 above then either upload that somewhere or
iasl -d /mnt/aml-GHR602
should generate you a suitable text file. However generic ports are fairly
recent
so you may need
richard pushed to branch tor-browser-115.12.0esr-13.5-1 at The Tor Project /
Applications / Tor Browser
Commits:
5517e6b0 by Pier Angelo Vendrame at 2024-06-05T13:01:37+02:00
fixup! Bug 41089: Add tor-browser build scripts + Makefile to tor-browser
Use the correct volume name on macOS
richard pushed to branch tor-browser-115.12.0esr-13.5-1 at The Tor Project /
Applications / Tor Browser
Commits:
5517e6b0 by Pier Angelo Vendrame at 2024-06-05T13:01:37+02:00
fixup! Bug 41089: Add tor-browser build scripts + Makefile to tor-browser
Use the correct volume name on macOS
richard pushed to branch main at The Tor Project / Applications /
tor-browser-build
Commits:
3ffc1e6d by Nicolas Vigier at 2024-06-05T16:26:06+00:00
Bug 41154: Update keyring/boklm.gpg for new subkeys
- - - - -
1 changed file:
- keyring/boklm.gpg
Changes
richard pushed to branch main at The Tor Project / Applications /
tor-browser-build
Commits:
3ffc1e6d by Nicolas Vigier at 2024-06-05T16:26:06+00:00
Bug 41154: Update keyring/boklm.gpg for new subkeys
- - - - -
1 changed file:
- keyring/boklm.gpg
Changes
YunQiang Su writes:
> Richard Sandiford 于2024年6月5日周三 23:20写道：
>>
>> YunQiang Su writes:
>> > Richard Sandiford 于2024年6月5日周三 22:14写道：
>> >>
>> >> YunQiang Su writes:
>> >> > PR target/113179.
>> >> >
>> >
On 6/5/24 02:27, Philippe Mathieu-Daudé wrote:
On 26/5/24 21:42, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/insns.decode | 1 +
target/sparc/translate.c | 11 +++
2 files changed, 12 insertions(+)
+static void do_wrmwait(DisasContext *dc, TCGv
On 6/5/24 10:27, Jonathan Cameron wrote:
This fails testing:
https://gitlab.com/qemu-project/qemu/-/jobs/7021105504
acpi-test: Warning! SRAT binary file mismatch. Actual [aml:/tmp/aml-GHR6O2],
Expected
[aml:tests/data/acpi/q35/SRAT.acpihmat-generic-x].
See source file
YunQiang Su writes:
> Richard Sandiford 于2024年6月5日周三 22:14写道：
>>
>> YunQiang Su writes:
>> > PR target/113179.
>> >
>> > In `store_bit_field_using_insv`, we just use SUBREG if value_mode
>> >>= op_mode, while in some ports, a sign_extend wil
CPUINFO_SSE4 is dead.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
Commit: 294ac64e459aca023f43441651d860980c9784f1
https://github.com/qemu/qemu/commit/294ac64e459aca023f43441651d860980c9784f1
Author: Paolo Bonzini
Date: 2024
On 6/5/24 02:27, Michael S. Tsirkin wrote:
On Tue, Jun 04, 2024 at 03:06:01PM -0400, Michael S. Tsirkin wrote:
The following changes since commit 60b54b67c63d8f076152e0f7dccf39854dfc6a77:
Merge tag 'pull-lu-20240526' of https://gitlab.com/rth7680/qemu into staging
(2024-05-26 17:51:00
On 6/4/24 14:08, Michael S. Tsirkin wrote:
From: Jonathan Cameron
Given this is a new configuration, there are affects on APIC, CEDT
and DSDT, but the key elements are in SRAT (plus related data in
HMAT). The configuration has node to exercise many different combinations.
0) CPUs + Memory
1)
a semantically
equivalent call (that would be no longer optimized). That is, your intent is
to enable a subset of optimizations only enabled by denoting the semantic
equivalence. That subset at least needs documenting.
Richard
>
> Ciao,
> Michael.
tmp = gen_lowpart (op_mode, force_reg (value_mode, value1));
}
(also inclues unnesting of the else). Could you try changing the code
to do that and push the change if it works?
IMO the patch (in that form) is OK for backports after it has had a
couple of weeks on trun
Looking for a weeder or two to help me remove the gout weed that is trying to
take over our flower beds. Generous compensation.
Sent from my iPad
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The LincolnTalk mailing list.
To post, send mail to Lincoln@lincolntalk.org.
Browse the archives at
Wilco Dijkstra writes:
> Hi Richard,
>
>>> Essentially anything covered by HWCAP doesn't need an explicit check. So I
>>> kept
>>> the LS64 and PREDRES checks since they don't have a HWCAP allocated (I'm not
>>> entirely convinced we need these, let al
Richard Biener writes:
> On Tue, 4 Jun 2024, Richard Sandiford wrote:
>
>> Richard Biener writes:
>> > The following emulates classical interleaving for SLP load permutes
>> > that we are unlikely handling natively. This is to handle cases
>> >
On Wed, 5 Jun 2024, Richard Biener wrote:
> On Tue, 4 Jun 2024, Richard Sandiford wrote:
>
> > Richard Biener writes:
> > > The following emulates classical interleaving for SLP load permutes
> > > that we are unlikely handling natively. This is to handle
On Wed, 5 Jun 2024, Tamar Christina wrote:
> > -Original Message-
> > From: Richard Biener
> > Sent: Tuesday, June 4, 2024 3:33 PM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Richard Sandiford ; Tamar Christina
> >
> > Subject: [PATCH] [RFC]
On Tue, 4 Jun 2024, Richard Sandiford wrote:
> Richard Biener writes:
> > The following emulates classical interleaving for SLP load permutes
> > that we are unlikely handling natively. This is to handle cases
> > where interleaving (or load/store-lanes)
O'Riordan and Sophie Fitzpatrick (Wikimedia Community Ireland), Richard
Nevell (WMUK) or Léa Lacroix. [4]
[1] https://meta.wikimedia.org/wiki/Celtic_Knot_Conference_2024
[2]
https://meta.wikimedia.org/wiki/Celtic_Knot_Conference_2024/Call_for_submissions
[3] https://meta.wikimedia.org/wiki
O'Riordan and Sophie Fitzpatrick (Wikimedia Community Ireland), Richard
Nevell (WMUK) or Léa Lacroix. [4]
[1] https://meta.wikimedia.org/wiki/Celtic_Knot_Conference_2024
[2]
https://meta.wikimedia.org/wiki/Celtic_Knot_Conference_2024/Call_for_submissions
[3] https://meta.wikimedia.org/wiki
mp;& (modified_in_p (cc_cmp, seq2)
> + || (rev_cc_cmp && modified_in_p (rev_cc_cmp, seq2
> + seq2 = NULL;
It looks like this still has the problem that I mentioned in the
previous round: that modified_in_p only checks the first instruction
in seq2, not the wh
:
Amy O'Riordan and Sophie Fitzpatrick (Wikimedia Community Ireland), Richard
Nevell (WMUK), or Léa Lacroix. [4]
[1] https://meta.wikimedia.org/wiki/Celtic_Knot_Conference_2024
[2]
https://meta.wikimedia.org/wiki/Celtic_Knot_Conference_2024/Call_for_submissions
[3] https://meta.wikimedia.org/wiki
process is
now open until Sunday, June 30th. You can find the form and the
instructions on the Attend page. [3]
We are looking forward to receiving your contributions to the program and
scholarship requests!
If you have any questions, feel free to reach out to the organising team:
Richard Nevell
Jan Beulich writes:
> Much like AT_HWCAP is already provided in case the platform headers
> don't have the value (yet).
>
> libgcc/
>
> * config/aarch64/cpuinfo.c: Provide AT_HWCAP2.
OK for trunk and GCC 14.
Thanks,
Richard
> ---
> Observed as build failure
[
https://issues.apache.org/jira/browse/MNG-7868?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel=17852366#comment-17852366
]
Richard Eckart de Castilho edited comment on MNG-7868 at 6/5/24 10:23 AM
[
https://issues.apache.org/jira/browse/MNG-7868?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel=17852352#comment-17852352
]
Richard Eckart de Castilho edited comment on MNG-7868 at 6/5/24 10:16 AM
[
https://issues.apache.org/jira/browse/MNG-7868?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel=17852366#comment-17852366
]
Richard Eckart de Castilho edited comment on MNG-7868 at 6/5/24 10:14 AM
[
https://issues.apache.org/jira/browse/MNG-7868?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel=17852366#comment-17852366
]
Richard Eckart de Castilho edited comment on MNG-7868 at 6/5/24 10:12 AM
[
https://issues.apache.org/jira/browse/MNG-7868?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel=17852366#comment-17852366
]
Richard Eckart de Castilho commented on MNG-7868:
-
Well, that's the information I shared
On Fri, May 24, 2024 at 9:08 PM Richard Guo wrote:
> On the basis of the parser infrastructure fixup, 0002 patch adds the
> nullingrel bit that references the grouping RTE to the grouping
> expressions.
I found a bug in the v6 patch. The following query would trigger t
[
https://issues.apache.org/jira/browse/MNG-7868?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel=17852352#comment-17852352
]
Richard Eckart de Castilho commented on MNG-7868:
-
I have a dump of the lock factory, but I
Branch: refs/heads/master
Home: https://github.com/openssl/tools
Commit: f76f116d4c66e1ce31a7ea867163cc7e2c5c62b6
https://github.com/openssl/tools/commit/f76f116d4c66e1ce31a7ea867163cc7e2c5c62b6
Author: Richard Levitte
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths
Hongyu Wang writes:
> CC'd Richard for ccmp part as previously it is added only for aarch64.
> The original logic will not interrupted since if
> aarch64_gen_ccmp_first succeeded, aarch64_gen_ccmp_next will also
> success, the cmp/fcmp and ccmp/fccmp supports
On Wed, 5 Jun 2024, Tamar Christina wrote:
> > -Original Message-
> > From: Richard Biener
> > Sent: Wednesday, June 5, 2024 9:07 AM
> > To: Manolis Tsamis
> > Cc: gcc-patches@gcc.gnu.org; Christoph Müllner
> > ;
> > Kewen . Lin ; Philipp Toms
ine for
insn_cost-based calculations. It has two (supposed) advantages:
it caches the old costs, and it takes execution frequency into
account when optimising for speed.
The comment is out of date though. The name of the routine is
changes_are_worthwhile rather than change_is_worthwhile. Co
opname_1[20];
> + char opname_2[20];
> + gen_opname (opname_0, 0);
> +
> + fprintf_indent (f, indent,
> +"tree %s = build2 (gimple_cond_code (_ct_%d), "
> +"boolean_type_node, _cond_lhs_%d, _cond_rhs_%d);\n",
> +opname_0, depth, depth,
Evgeny Karpov writes:
> Richard and Uros, could you please review the changes for v2?
> Additionally, we have detected an issue with GCC GC in winnt-dll.cc. The fix
> will be included in v2.
Would it be possible to have a more "purposeful" name than
CMODEL_IS_NOT_LARGE_OR_
icit enum
and open-coding each case?
Another general note is that trying (and then undo on fail) such ticks
eats at the discovery limit we have in place to avoid exponential run-off
in exactly this degenerate cases.
Thanks,
Richard.
> This targets the vectorization of the SPEC2017 x264
n email to devel-le...@lists.fedoraproject.org
> Fedora Code of Conduct:
> https://docs.fedoraproject.org/en-US/project/code-of-conduct/
> List Guidelines: https://fedoraproject.org/wiki/Mailing_list_guidelines
> List Archives:
> https://lists.fedoraproject.org/archives/list/deve
On Tue, Jun 4, 2024 at 10:31 PM Qing Zhao wrote:
>
>
>
> > On Jun 4, 2024, at 03:43, Richard Biener wrote:
> >
> > On Mon, Jun 3, 2024 at 4:48 PM David Malcolm wrote:
> >>
> >> On Mon, 2024-06-03 at 08:29 +0200, Richard Biener wrote:
> >>>
k 2, loop depth 0
> ;;pred: ENTRY
> _6 = .SAT_SUB (x_4(D), y_5(D)); [tail call]
> return _6;
> ;;succ: EXIT
> }
>
> The below tests are running for this patch:
> *. The riscv fully regression tests.
> *. The x86 bootstrap tests.
> *. Th
On Tue, 4 Jun 2024, Thomas Schwinge wrote:
> Hi!
>
> On 2011-01-10T13:56:06+0100, Richard Guenther wrote:
> > On Sun, 9 Jan 2011, Jan Hubicka wrote:
> >> On 2011-01-09T07:24:57-0800, "H.J. Lu" wrote:
> >> > On Sat, Jan 8, 2011 at 5:01 PM, Jan Hubi
The single-lane case isn't different from non-SLP, no re-association
implied. But the transform stage cannot handle a conditional reduction
op which isn't checked during analysis - this makes it work, exercised
with a single-lane non-reduction-chain by gcc.target/i386/pr112464.c
*
The following makes double reduction vectorization work when
using (single-lane) SLP vectorization.
* tree-vect-loop.cc (vect_analyze_scalar_cycles_1): Queue
double reductions in LOOP_VINFO_REDUCTIONS.
(vect_create_epilog_for_reduction): Remove asserts disabling
The following enables single-lane COND_REDUCTION vectorization.
* tree-vect-loop.cc (vect_create_epilog_for_reduction):
Adjust for single-lane COND_REDUCTION SLP vectorization.
(vectorizable_reduction): Likewise.
(vect_transform_cycle_phi): Likewise.
---
Allow one-lane SLP but for the case where we need to swap the arms.
* tree-vect-stmts.cc (vectorizable_condition): Allow
single-lane SLP, but not when we need to swap then and
else clause.
---
gcc/tree-vect-stmts.cc | 6 +-
1 file changed, 5 insertions(+), 1
cs/mesa/files/0001-Revert-meson-do-not-pull-in-clc-for-clover.patch
It does sound complicated, I'm afraid I don't have any specific advice
but avoiding a rust dependency would be nice if we can and requiring
clang would be much more problematic.
Cheers,
Richard
-=-=-=-=-=-=-=-=-=-=-=-
Links: You
ssue, and happy git pushing resumed.
>
> But how do I fix this so that the next apache update doesn't clobber this?
>
Copy the file to /etc/systemd/system and it will override the package
provided file in /lib/systemd/system
Thanks,
Richard
--
__
Branch: refs/heads/main
Home: https://github.com/WebKit/WebKit
Commit: 7b3437ee1d1a10ad097c60b3d602dc956e153196
https://github.com/WebKit/WebKit/commit/7b3437ee1d1a10ad097c60b3d602dc956e153196
Author: Richard Robinson
Date: 2024-06-04 (Tue, 04 Jun 2024)
Changed paths
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 0b7ca10a059089caef535e86c6523991240e5f29
https://github.com/qemu/qemu/commit/0b7ca10a059089caef535e86c6523991240e5f29
Author: Si-Wei Liu
Date: 2024-05-27 (Mon, 27 May 2024)
Changed paths:
M
warnings, 79 lines checked
Misc HW & accelerators patch queue
- Use async exit in debugexit model (Thomas)
- Fixed bug reading xlnx_dpdma descriptor (Peter)
- Initialise plugin state before vCPU/thread creation (Alex)
- Few sprintf() calls rem
e sprintf() by snprintf()
sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1,
resulting in painful developper experience. Use snprintf() instead.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-Id: <20240411104340.6617-9-phi...@linaro.
. This could be fixed within bitbake or it could be fixed
within the SDK environment. This patch does the latter for now. We
really need to improve openssl relocation within the SDK in general.
Fixing this has become more urgent to fix failing builds in automated
testing.
Signed-off-by: Richard Purdie
Richard Zowalla created OWB-1441:
Summary: Adding a User-defined Interceptor Bean via CDI Extension
fails due to missing no-arg constructor
Key: OWB-1441
URL: https://issues.apache.org/jira/browse/OWB-1441
Richard Biener writes:
> The following emulates classical interleaving for SLP load permutes
> that we are unlikely handling natively. This is to handle cases
> where interleaving (or load/store-lanes) is the optimal choice for
> vectorizing even when we are doing that within SLP.
e sprintf() by snprintf()
sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1,
resulting in painful developper experience. Use snprintf() instead.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-Id: <20240411104340.6617-9-phi...@linaro.
On 6/4/24 02:37, Jason Wang wrote:
The following changes since commit 3ab42e46acf867c45bc929fcc37693e327a35a24:
Merge tag 'pull-ufs-20240603' ofhttps://gitlab.com/jeuk20.kim/qemu into
staging (2024-06-03 08:18:14 -0500)
are available in the Git repository at:
us patches, and overall,
the 'system' source set should be used like in pre-'eBPF blob' patches.
Signed-off-by: Andrew Melnychenko
Signed-off-by: Jason Wang
Commit: 6e47f7cfcd78ed8e6f192cb0a4c61f209d0c2aaf
https://github.com/qemu/qemu/commit/6e47f7cfcd78ed8e6f192cb0a4c61f209d0c2aaf
Auth
This WG does not get to decide which hybrids will exist or be standardized,
unless it has implications on the TLS protocol, which it does not.
--RLB
On Tue, Jun 4, 2024 at 2:51 PM Salz, Rich wrote:
> I urge the chairs to call cloture on this thread. There is nothing
> relevant for the working
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