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*INFOTECH ENTERPRISES LIMITED,* *ELECTRONICS CITY,* *BANGALORE.* * * * * *Embedded Software Requirements for Bengaluru* * * *Position: Engineers/Leads* *Job Location: Bangalore.* * * B.E/B.Tech or M.E/M.Tech in ECE/EEE/CSE with 3 - 8 years of experience* in any *of the following areas. - RTOS and OS internals and mobile framework platforms (Linux, WinCE, Android) - Firmware and Device Driver development for Mobile and Set Top Box based peripherals and Connectivity/MM/Memory Devices - Experience in Pre and Post silicon validation. - Porting of protocol Stacks (GPS/AGPS, BT,WLAN), Middleware, Knowledge of Telephony Frameworks - Developing Board Support Package (BSP), boot loaders, OS porting and bring up on emulators/simulators/SDPs. - Good understanding of processor (ARM, MIPS, x86) and Overall System architecture. - Experience in Porting/Optimizing the Multimedia Codecs (Video, Audio, Image and Speech) and adaptation of Frameworks (G Streamer, Open Max) and Hardware accelerators. · Good understanding of BT stack and expertise on BT profile development. Familiarity with any one or more of the following profiles BPP, SAP, PBAP, A2DP, AVRCP, DUN, SPP, HF, FTP, OPP · Experience with Linux block device driver, file system, BootROM/option ROM BIOS/UEFI in the PCIe for ATA AHCI/SATA/SCSI/SAS transport protocols. · Experience in GUI application development involving interactions with device management (register configuration, firmware update, hardware diagnostic) · Validation experience on various Linux based device drivers, file systems, BootROM, firmware, BIOS/UEFI and GUI applications. - C/C++ and Assembly Programming Skills. - Android experience will be an advantage and Candidates with customer interfacing skills will be given preference *Position: Project Managers* *Job location: Bangalore* *Qualification*: BE/BTech or ME/MTech/MS in CS/ECE *Experience: 8 –* 10 +Years * * *Job description:* 8-10+ years of experience, should be able to manage a team of 20+ software/Firmware engineers in the above technologies. Good customer interaction skills/ ability to work with multi location teams and thorough understanding of software processes are mandatory. Should be willing to travel. * * *ASIC positions for Hyderabad and Bengaluru*** The candidate should possess *BE/B.Tech or ME/M**.Tech/MS in EEE/ECE with 4+ years of experience in any of the following areas.* * * *Position: Engineers/Leads* *Job Location:** Hyderabad/Bengaluru* *Logic Design:* Microarchitecture, Logic Design, RTL Coding, Logic Synthesis, Expertise on ARM and Cortex processors and designing subsystems around them. C/C++, Verilog/VHDL, System Verilog. *Verification*: Block level and System level (SoC) verification, Test Bench development, Test Cases development, BFM models, coverage driven verification, Gate level simulations, Verilog/VHDL, System Verilog/Specman/Vera, C/C++, VMM/RVM/OVM verification, writing test cases in “C” and C-based SoC level verification * * *Physical Design*: Partitioning, IO ring preparation, Floorplanning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis, Physical verification, Signal Integrity, Low Power design. *DFT*: JTAG, MBIST, Custom MBIST, Scan, ATPG, At-speed Scan, Scan Compression, Logic BIST, Silicon bring-up on ATE floor *Implementation*: Logic Synthesis, Low Power Synthesis, Timing Constraints, Timing Closure, Static Timing Analysis, Cross talk analysis and Repair, Formal Verification. *Analog Layout*: P-cell creation, expertise on PDKs, Floor planning, Device Matching techniques, Routing, Electro Migration prevention techniques, Physical Verification, SKILL programming. *Position**: Physical Design Managers* *Job location**: Hyderabad* *Qualification*: BE/BTech or ME/MTech/MS in EEE/ECE/VLSI Job description: 8-10+ years of experience, should be able to manage a team of 10+ physical design engineers with expertise on Partitioning, IO ring preparation, Floorplanning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis, Physical verification, Signal Integrity, Low Power design. *Position**: ASIC Design Manager* *Job location**: Bengaluru* *Qualification*: BE/BTech or ME/MTech/MS in EEE/ECE/VLSI Job description: 10-12+ years of experience, should be able to manage frontend and backend teams, exposure to overall ASIC design cycle - Logic Design, Verification, Synthesis, Physical design, DFT and STA. On Thu, Mar 3, 2011 at 4:54 PM, Ananthapadmanaban < gapadmana...@e-consystems.com> wrote: > Hi All, > > Using camera application available in the froyo build, I was able to > stream VGA frame at 7 fps maximum. > But my sensor streaming frame rate at 30 fps. How to optimize the camera > application ? > > *Test environment: * > Board : Omap3evm board. > Application : Default camera application came with froyo distribution. > > I googled the same problem and got some patches available for ecliar. > http://code.google.com/p/android/issues/detail?id=2794 > > Like this similar patch available for froyo too ? > > Thanks and regards, > Ananth. > > -- > unsubscribe: android-porting+unsubscr...@googlegroups.com > website: http://groups.google.com/group/android-porting > -- unsubscribe: android-porting+unsubscr...@googlegroups.com website: http://groups.google.com/group/android-porting
